Changing action file so data and addr only commands set the status reg correctly

Change-Id: I49d41a35e04ee5e33b9fbee442b685caf085dba2
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23218
Tested-by: Jenkins Server
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Basabjit Sengupta <basengup@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24141

1 files changed, 130 insertions, 22 deletions

diff --git a/import/chips/p9/sw_simulation/chip.act b/import/chips/p9/sw_simulation/chip.act
index a5971f03..7996ffd7 100644
--- a/import/chips/p9/sw_simulation/chip.act
+++ b/import/chips/p9/sw_simulation/chip.act
@@ -32,7 +32,7 @@ CAUSE_EFFECT{
   CAUSE: TARGET=[REG(0x068001)] OP=[BIT,ON] BIT=[2]
 
   #If the reset is set unset bit 7 to show that the PBA Slave reset is no longer in progress
-  EFFECT: TARGET=[REG(0x068007)] OP=[BIT,OFF] BIT=[7]
+  EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[7]
 
 }
 #Basabjit had me separate these into the read and write because of their read/writeMainstore modules 
@@ -42,31 +42,70 @@ CAUSE_EFFECT{
   LABEL=[PBA Read to set the PBARBUFVAL PBAWBUFVAL and PBASLVRST]
   #If the data register is read
   WATCH_READ=[REG(0x0006D075)] #OCBDR3
-  CAUSE: TARGET=[REG(0x00068007)] OP=[BIT,OFF] BIT=[4]
+  CAUSE: TARGET=[REG(0x00068001)] OP=[BIT,OFF] BIT=[11]
 
   #Basabjit had me add these
   # Read from the Memory
-  EFFECT: TARGET=[MODULE(readMainstore, 0x0006D070)] OP=[MODULECALL]  DATA=[REG(0x0006D075)]
-  EFFECT: TARGET=[REG(0x0006D070)] OP=[INCREMENT,MASK] INCVAL=[8] MASK=[LITERAL(64,00000000 0000FFFF)]  # incr addr reg by 8
+  EFFECT: TARGET=[REG(0x00068FFE)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,80000000 00000000)] #Force refresh of address
+  EFFECT: TARGET=[MODULE(readMainstore, 0x00068FFF)] OP=[MODULECALL]  DATA=[REG(0x0006D075)]
+  EFFECT: TARGET=[REG(0x0006D070)] OP=[INCREMENT,MASK] INCVAL=[8] MASK=[LITERAL(64, 07FFFFFF 00000000)]
 
   #set PBARBUFVAL0[buffer_status] to 0b0000001
-  EFFECT: TARGET=[REG(0x05012850)] OP=[BUF,MASK] DATA=[LITERAL(64,00000000 01000000)] MASK=[LITERAL(64,00000000 7F000000)]
+  EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,OFF] BIT=[33]
+  EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,OFF] BIT=[34]
+  EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,OFF] BIT=[35]
+  EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,OFF] BIT=[36]
+  EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,OFF] BIT=[37]
+  EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,OFF] BIT=[38]
+  EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,ON] BIT=[39]
   #set PBARBUFVAL1[buffer_status] to 0b0000001
-  EFFECT: TARGET=[REG(0x05012851)] OP=[BUF,MASK] DATA=[LITERAL(64,00000000 01000000)] MASK=[LITERAL(64,00000000 7F000000)]
+  EFFECT: TARGET=[REG(0x05012851)] OP=[BIT,OFF] BIT=[33]
+  EFFECT: TARGET=[REG(0x05012851)] OP=[BIT,OFF] BIT=[34]
+  EFFECT: TARGET=[REG(0x05012851)] OP=[BIT,OFF] BIT=[35]
+  EFFECT: TARGET=[REG(0x05012851)] OP=[BIT,OFF] BIT=[36]
+  EFFECT: TARGET=[REG(0x05012851)] OP=[BIT,OFF] BIT=[37]
+  EFFECT: TARGET=[REG(0x05012851)] OP=[BIT,OFF] BIT=[38]
+  EFFECT: TARGET=[REG(0x05012851)] OP=[BIT,ON] BIT=[39]
   #set PBARBUFVAL2[buffer_status] to 0b0000001
-  EFFECT: TARGET=[REG(0x05012852)] OP=[BUF,MASK] DATA=[LITERAL(64,00000000 01000000)] MASK=[LITERAL(64,00000000 7F000000)]
+  EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,OFF] BIT=[33]
+  EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,OFF] BIT=[34]
+  EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,OFF] BIT=[35]
+  EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,OFF] BIT=[36]
+  EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,OFF] BIT=[37]
+  EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,OFF] BIT=[38]
+  EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,ON] BIT=[39]
   #set PBARBUFVAL3[buffer_status] to 0b0000001
-  EFFECT: TARGET=[REG(0x05012853)] OP=[BUF,MASK] DATA=[LITERAL(64,00000000 01000000)] MASK=[LITERAL(64,00000000 7F000000)]
+  EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,OFF] BIT=[33]
+  EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,OFF] BIT=[34]
+  EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,OFF] BIT=[35]
+  EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,OFF] BIT=[36]
+  EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,OFF] BIT=[37]
+  EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,OFF] BIT=[38]
+  EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,ON] BIT=[39]
   #set PBARBUFVAL4[buffer_status] to 0b0000001
-  EFFECT: TARGET=[REG(0x05012854)] OP=[BUF,MASK] DATA=[LITERAL(64,00000000 01000000)] MASK=[LITERAL(64,00000000 7F000000)]
+  EFFECT: TARGET=[REG(0x05012854)] OP=[BIT,OFF] BIT=[33]
+  EFFECT: TARGET=[REG(0x05012854)] OP=[BIT,OFF] BIT=[34]
+  EFFECT: TARGET=[REG(0x05012854)] OP=[BIT,OFF] BIT=[35]
+  EFFECT: TARGET=[REG(0x05012854)] OP=[BIT,OFF] BIT=[36]
+  EFFECT: TARGET=[REG(0x05012854)] OP=[BIT,OFF] BIT=[37]
+  EFFECT: TARGET=[REG(0x05012854)] OP=[BIT,OFF] BIT=[38]
+  EFFECT: TARGET=[REG(0x05012854)] OP=[BIT,ON] BIT=[39]
   #set PBARBUFVAL5[buffer_status] to 0b0000001
-  EFFECT: TARGET=[REG(0x05012855)] OP=[BUF,MASK] DATA=[LITERAL(64,00000000 01000000)] MASK=[LITERAL(64,00000000 7F000000)]
-
+  EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,OFF] BIT=[33]
+  EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,OFF] BIT=[34]
+  EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,OFF] BIT=[35]
+  EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,OFF] BIT=[36]
+  EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,OFF] BIT=[37]
+  EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,OFF] BIT=[38]
+  EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,ON] BIT=[39]
 
   #unset PBASLVRST[in_prog] bit
   EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[7]
   #set PBASLVRST[busy_status] to 0b0000 bits 8:11
-  EFFECT: TARGET=[REG(0x068001)] OP=[BUF,MASK] DATA=[LITERAL(64,00000000 00000000)] MASK=[LITERAL(64,00F00000 00000000)]
+  EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[8]
+  EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[9]
+  EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[11]  
 }
 
 #If a write is done need to set the PBAWBUFVAL[0, 1] wr buffer status (bits 35:39) to 0b00001
@@ -75,23 +114,69 @@ CAUSE_EFFECT{
   LABEL=[PBA Write to set the PBARBUFVAL, PBAWBUFVAL, and PBASLVRST]
   #If the data register is written
   WATCH=[REG(0x0006D075)] #OCBDR3
-  CAUSE: TARGET=[REG(0x00068007)] OP=[BIT,OFF] BIT=[4]
+  CAUSE: TARGET=[REG(0x00068001)] OP=[BIT,OFF] BIT=[11]
 
   # Write into from the Memory
-  EFFECT: TARGET=[MODULE(writeMainstore, 0x0006D070)] OP=[MODULECALL]  DATA=[REG(0x0006D075)]
-  EFFECT: TARGET=[REG(0x0006D070)] OP=[INCREMENT,MASK] INCVAL=[8] MASK=[LITERAL(64,00000000 0000FFFF)]  # incr addr reg by 8
+  EFFECT: TARGET=[REG(0x00068FFE)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,80000000 00000000)] #Force refresh of PBA address
+  EFFECT: TARGET=[MODULE(writeMainstore, 0x00068FFF)] OP=[MODULECALL]  DATA=[REG(0x0006D075)]
+  EFFECT: TARGET=[REG(0x0006D070)] OP=[INCREMENT,MASK] INCVAL=[8] MASK=[LITERAL(64, 07FFFFFF 00000000)]
 
   #set PBAWBUFVAL0[buffer_status] to 0b00001
-  EFFECT: TARGET=[REG(0x05012858)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(64,00000000 01000000)] MASK=[LITERAL(64, 00000000 1F000000)]
+  EFFECT: TARGET=[REG(0x05012858)] OP=[BIT,OFF] BIT=[35]
+  EFFECT: TARGET=[REG(0x05012858)] OP=[BIT,OFF] BIT=[36]
+  EFFECT: TARGET=[REG(0x05012858)] OP=[BIT,OFF] BIT=[37]
+  EFFECT: TARGET=[REG(0x05012858)] OP=[BIT,OFF] BIT=[38]
+  EFFECT: TARGET=[REG(0x05012858)] OP=[BIT,ON] BIT=[39]
 
   #set PBAWBUFVAL0[buffer_status] to 0b00001
-  EFFECT: TARGET=[REG(0x05012859)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(64,00000000 01000000)] MASK=[LITERAL(64, 00000000 1F000000)]
+  EFFECT: TARGET=[REG(0x05012859)] OP=[BIT,OFF] BIT=[35]
+  EFFECT: TARGET=[REG(0x05012859)] OP=[BIT,OFF] BIT=[36]
+  EFFECT: TARGET=[REG(0x05012859)] OP=[BIT,OFF] BIT=[37]
+  EFFECT: TARGET=[REG(0x05012859)] OP=[BIT,OFF] BIT=[38]
+  EFFECT: TARGET=[REG(0x05012859)] OP=[BIT,ON] BIT=[39]
 
   #unset PBASLVRST[in_prog] bit
-  EFFECT: TARGET=[REG(0x0068007)] OP=[BIT,OFF] BIT=[7]
+  EFFECT: TARGET=[REG(0x0068001)] OP=[BIT,OFF] BIT=[7]
 
   #set PBASLVRST[busy_status] to 0b0000 bits 8:11
-  EFFECT: TARGET=[REG(0x0068001)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(64,00000000 00000000)] MASK=[LITERAL(64, 00F00000 00000000)]
+  EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[8]
+  EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[9]
+  EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[11]
+}
+
+# PBA ADDRESS CALC
+CAUSE_EFFECT{
+  LABEL=[PBA ADDR Calculation]
+  #If the data register is read
+  WATCH=[REG(0x00068FFE)]
+
+  #Determine PBA Address
+  EFFECT: TARGET=[REG(0x00068FFF)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+  EFFECT: TARGET=[REG(0x00068FFF)] OP=[EQUALTO,BUF,MASK,SHIFT] DATA=[REG(0x0006D070)] MASK=[LITERAL(64,00000000 000FFFFF)] SHIFT=[32]
+
+  #bits 37:43 if PBA mask set
+  EFFECT: TARGET=[PBAADDR(0x1)] OP=[EQUALTO,BUF,SHIFT] DATA=[REG(0x0006D070)] SHIFT=[32] 
+  EFFECT: TARGET=[PBAADDR(0x1)] OP=[AND,BUF] DATA=[REG(0x05012B07)]
+  EFFECT: TARGET=[PBAADDR(0x1)] OP=[AND,BUF] DATA=[LITERAL(64,00000000 07F00000)]
+  EFFECT: TARGET=[REG(0x00068FFF)] OP=[OR,BUF] DATA=[PBAADDR(0x1)]
+
+  #bits 23:43 if PBA mask set
+  EFFECT: TARGET=[PBAADDR(0x1)] OP=[EQUALTO,BUF,MASK,SHIFT] DATA=[REG(0x00068007)] MASK=[LITERAL(64,00000000 0FFFC000)] SHIFT=[-13]
+  EFFECT: TARGET=[PBAADDR(0x1)] OP=[AND,BUF] DATA=[REG(0x05012B07)]
+  EFFECT: TARGET=[REG(0x00068FFF))] OP=[OR,BUF] DATA=[PBAADDR(0x1)]
+
+  #bits 23:43 if PBA mask clear
+  EFFECT: TARGET=[PBAADDR(0x1)] OP=[EQUALTO,BUF] DATA=[REG(0x05012B03)]
+  EFFECT: TARGET=[PBAADDR(0x0)] OP=[EQUALTO,BUF,INVERT] DATA=[REG(0x05012B07)]
+  EFFECT: TARGET=[PBAADDR(0x1)] OP=[AND,BUF] DATA=[PBAADDR(0x0)]
+  EFFECT: TARGET=[PBAADDR(0x1)] OP=[AND,BUF] DATA=[LITERAL(64,000001FF FFF00000)]
+  EFFECT: TARGET=[REG(0x00068FFF)] OP=[OR,BUF] DATA=[PBAADDR(0x1)]
+
+  #bits 8:22 always based on PBA BAR
+  EFFECT: TARGET=[PBAADDR(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x05012B03)]
+  EFFECT: TARGET=[PBAADDR(0x0)] OP=[AND,BUF] DATA=[LITERAL(64,00FFFE00 00000000)]
+  EFFECT: TARGET=[REG(0x00068FFF)] OP=[OR,BUF] DATA=[PBAADDR(0x1)]
 }
 
 # ==========================================================================
@@ -107,12 +192,36 @@ CAUSE_EFFECT{
 
   #Set the ALTD_STATUS Register so these bits are set: 
   #FBC_ALTD_BUSY = WAIT_CMD_ARBIT = WAIT_RESP = OVERRUN_ERR = AUTOINC_ERR = COMMAND_ERR = ADDRESS_ERR = COMMAND_HANG_ERR = DATA_HANG_ERR = PBINIT_MISSING = ECC_CE = ECC_UE = ECC_SUE = 0
-  #ADDR_DONE = DATA_DONE =1
   EFFECT: TARGET=[REG(0x00090003)] OP=[BUF,AND] DATA=[LITERAL(64,001FDFFF FFFF1FFF)] 
   EFFECT: TARGET=[REG(0x00090003)] OP=[BUF,OR] DATA=[LITERAL(64,30000000 00000000)]
-  EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2]
+}
+
+#If a read/write is done to the ALTD_DATA Register and the Address only bit is not set then set the DATA_DONE bit to 1 
+CAUSE_EFFECT{
+  LABEL=[ADU Read or write to set ALTD_STATUS[DATA_DONE] bit]
+  #If the data register is read
+  WATCH_READ=[REG(0x00090004)]
+  #If the data register is written
+  WATCH=[REG(0x00090004)]
+  CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6]
+
+  #Set the DATA_DONE bit         
   EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3]
 }
+
+#If a read/write is done to the ALTD_DATA Register and the Data only bit is not set then set the ADDR_DONE bit to 1 
+CAUSE_EFFECT{
+  LABEL=[ADU Read or write to set ALTD_STATUS[ADDR_DONE] bit]
+  #If the data register is read
+  WATCH_READ=[REG(0x00090004)]
+  #If the data register is written
+  WATCH=[REG(0x00090004)]
+  CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7]
+
+  #Set the ADDR_DONE bit 
+  EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2]
+}
+
 #If a read is done to the ALTD_CMD Register and it sets the lock set the ALTD_STATUS Register so the ALTD_STATUS_BUSY bit is set 
 CAUSE_EFFECT{
   LABEL=[ADU Write to set ALTD_STATUS_BUSY]
@@ -130,5 +239,4 @@ CAUSE_EFFECT{
 
   #Unset the ALTD_STATUS Register so the ALTD_STATUS_BUSY is unset
   EFFECT: TARGET=[REG(0x090003)] OP=[BIT,OFF] BIT=[0]
-  EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3]
 }