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author | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-06-30 12:39:58 -0500 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-07-11 06:48:23 -0400 |
commit | b84517fe54a55eb353f5b98ad97c383370985d50 (patch) | |
tree | f3f00a92cc800b44cb7ec1fffcf7c66119c8e41e | |
parent | 25de058404ac120cd384cfd7bf6ce00eb3aa5adf (diff) | |
download | talos-sbe-b84517fe54a55eb353f5b98ad97c383370985d50.tar.gz talos-sbe-b84517fe54a55eb353f5b98ad97c383370985d50.zip |
Support for fused core mode
Change-Id: I1d898b5b0be1329b2a838d102833b48257215faf
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42668
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42788
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
-rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C | 64 |
1 files changed, 48 insertions, 16 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C index 3ad213b5..2667b39a 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C @@ -357,29 +357,61 @@ fapi2::ReturnCode p9_sbe_load_bootloader( } { - //instantiate the basic RamCore class - RamCore ram(l_coreTarget, 0); - //Set the HRMOR + fapi2::ATTR_FUSED_CORE_MODE_Type l_attr_fused_mode; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FUSED_CORE_MODE, + FAPI_SYSTEM, + l_attr_fused_mode)); + l_dataBuf.flush<0>(); + //Override PM_EXIT on master core bit 4 is for core 0 bit 5 is for core 1 - if (l_master_core % 2 == 0) + if ( (l_master_core % 2 == 0) || + (l_attr_fused_mode == fapi2::ENUM_ATTR_FUSED_CORE_MODE_CORE_FUSED)) { - l_dataBuf.flush<0>().setBit<EQ_CME_SCOM_SICR_PM_EXIT_C0>(); + l_dataBuf.setBit<EQ_CME_SCOM_SICR_PM_EXIT_C0>(); } - else + + if ( (l_master_core % 2 != 0) || + (l_attr_fused_mode == fapi2::ENUM_ATTR_FUSED_CORE_MODE_CORE_FUSED)) { - l_dataBuf.flush<0>().setBit<EQ_CME_SCOM_SICR_PM_EXIT_C1>(); + l_dataBuf.setBit<EQ_CME_SCOM_SICR_PM_EXIT_C1>(); } - FAPI_TRY(fapi2::putScom(i_master_ex_target, EX_0_CME_SCOM_SICR_SCOM2, l_dataBuf), - "Error overriding PM_EXIT"); - //Set ram_thread_active for t0 - l_dataBuf.flush<0>().setBit<C_0_THREAD_INFO_RAM_THREAD_ACTIVE_T0>(); - FAPI_TRY(fapi2::putScom(l_coreTarget, C_0_THREAD_INFO, l_dataBuf), - "Error setting thread active for t0"); - l_dataBuf.flush<0>().insertFromRight<0, 64>(l_drawer_base_address_nm0); - //call RamCore put_reg method - FAPI_TRY(ram.put_reg(REG_SPR, 313, &l_dataBuf), "Error ramming HRMOR"); + FAPI_TRY(fapi2::putScom(i_master_ex_target, EX_0_CME_SCOM_SICR_SCOM2, + l_dataBuf) ) + + for (auto& coreTgt : i_master_ex_target.getChildren<fapi2::TARGET_TYPE_CORE>()) + { + + // In non-fused mode, set HRMOR for master core only + if ((l_attr_fused_mode != fapi2::ENUM_ATTR_FUSED_CORE_MODE_CORE_FUSED) && + (( coreTgt != l_coreTarget))) + { + continue; + } + + //instantiate the basic RamCore class + RamCore ram(coreTgt, 0); + //Set the HRMOR + + //Set ram_thread_active for t0 + l_dataBuf.flush<0>().setBit<C_0_THREAD_INFO_RAM_THREAD_ACTIVE_T0>(); + FAPI_TRY(fapi2::putScom(coreTgt, C_0_THREAD_INFO, l_dataBuf), + "Error setting thread active for t0"); + + if( coreTgt == l_coreTarget ) + { + l_dataBuf.flush<0>().insertFromRight<0, 64>(l_drawer_base_address_nm0); + } + else + { + l_dataBuf.flush<0>().insertFromRight<0, 64>( + l_drawer_base_address_nm0 - l_bootloader_offset); + } + + //call RamCore put_reg method + FAPI_TRY(ram.put_reg(REG_SPR, 313, &l_dataBuf), "Error ramming HRMOR"); + } } fapi_try_exit: |