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path: root/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c
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* drm/nouveau/disp/nv50-: fetch mask of available sors during oneinitBen Skeggs2018-05-181-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/nv50-: avoid creating ORs that aren't present on HWBen Skeggs2017-06-171-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/nv50-: implement a common supervisor 2.2Ben Skeggs2017-06-161-0/+3
| | | | | | | | This makes use of all the additional routing and state added in previous commits, making it possible to deal with GM20x macro link routing, while also sharing code between the NV50 and GF119 implementations. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp: remove hw-specific customisation of output pathsBen Skeggs2017-06-161-12/+0
| | | | | | | All of the necessary hw-specific logic is now handled at the output resource level, so all of this can go away. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/gf119-: port OR DP VCPI control to nvkm_iorBen Skeggs2017-06-161-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/gt215-: port HDA ELD controls to nvkm_iorBen Skeggs2017-06-161-0/+5
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/g94-: port OR DP drive setting control to nvkm_iorBen Skeggs2017-06-161-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/g94-: port OR DP training pattern control to nvkm_iorBen Skeggs2017-06-161-7/+6
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/g94-: port OR DP link power control to nvkm_iorBen Skeggs2017-06-161-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/g94-: port OR DP link setup to nvkm_iorBen Skeggs2017-06-161-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/g94-: port OR DP lane mapping to nvkm_iorBen Skeggs2017-06-161-0/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/g84-: port OR HDMI control to nvkm_iorBen Skeggs2017-06-161-0/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/nv50-: port OR power state control to nvkm_iorBen Skeggs2017-06-161-0/+1
| | | | | | | Also removes the user-facing methods to these controls, as they're not currently utilised by the DD anyway. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/nv50-: fetch head/OR state at beginning of supervisorBen Skeggs2017-06-161-0/+1
| | | | | | | This data will be used by essentially every part of the supervisor handling process. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp: introduce input/output resource abstractionBen Skeggs2017-06-161-0/+11
| | | | | | | | | | In order to properly support the SOR -> SOR + pad macro separation that occurred with GM20x GPUs, we need to separate OR handling out of the output path code. This will be used as the base to support ORs (DAC, SOR, PIOR). Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp: shuffle functions aroundBen Skeggs2017-06-161-1/+0
| | | | | | | | | | Upcoming changes to split OR from output path drastically change the placement of various operations. In order to make the real changes clearer, do the moving around part ahead of time. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/sor/gf119-: add method to program mst payload informationBen Skeggs2016-11-071-0/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/sor/gm107: training pattern registers are like gm200Ben Skeggs2016-06-071-0/+53
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Cc: stable@vger.kernel.org
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