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* drm/nouveau/disp/gv100-: halt NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_ERROR stormsBen Skeggs2020-02-031-0/+6
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/gv100-: not all channel types support reporting error codesBen Skeggs2020-01-291-6/+17
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/nv50-: prevent oops when no channel method map providedBen Skeggs2020-01-291-0/+2
| | | | | | | | | | | | | The implementations for most channel types contains a map of methods to priv registers in order to provide debugging info when a disp exception has been raised. This info is missing from the implementation of PIO channels as they're rather simplistic already, however, if an exception is raised by one of them, we'd end up triggering a NULL-pointer deref. Not ideal... Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=206299 Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gr/gp10b: Use gp100_grctx and gp100_gr_zbcThierry Reding2020-01-233-3/+4
| | | | | | | | | gp10b doesn't have all the registers that gp102_gr_zbc wants to access, which causes IBUS MMIO faults to occur. Avoid this by using the gp100 variants of grctx and gr_zbc. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gr/tu10x: initial supportBen Skeggs2020-01-1510-11/+309
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/acr/tu10x: initial supportBen Skeggs2020-01-151-0/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/secboot: removeBen Skeggs2020-01-153-4/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/acr: implement new subdev to replace "secure boot"Ben Skeggs2020-01-1510-24/+226
| | | | | | | | | | | | | | | | | | | | | | | ACR is responsible for managing the firmware for LS (Low Secure) falcons, this was previously handled in the driver by SECBOOT. This rewrite started from some test code that attempted to replicate the procedure RM uses in order to debug early Turing ACR firmwares that were provided by NVIDIA for development. Compared with SECBOOT, the code is structured into more individual steps, with the aim of making the process easier to follow/debug, whilst making it possible to support newer firmware versions that may have a different binary format or API interface. The HS (High Secure) binary(s) are now booted earlier in device init, to match the behaviour of RM, whereas SECBOOT would delay this until we try to boot the first LS falcon. There's also additional debugging features available, with the intention of making it easier to solve issues during FW/HW bring-up in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/secboot: move code to boot LS falcons to subdevsBen Skeggs2020-01-152-2/+12
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/msgq: pass explicit message queue pointer to recv()Ben Skeggs2020-01-151-7/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/msgq: move handling of init message to subdevsBen Skeggs2020-01-153-1/+51
| | | | | | | | | | When the PMU/SEC2 LS FWs have booted, they'll send a message to the host with various information, including the configuration of message/command queues that are available. Move the handling for this to the relevant subdevs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/cmdq: move command generation to subdevsBen Skeggs2020-01-152-0/+45
| | | | | | | This moves the code to generate commands for the ACR unit of the PMU/SEC2 LS firmwares to those subdevs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/msgq: explicitly create message queue from subdevsBen Skeggs2020-01-151-1/+3
| | | | | | | | | Code to interface with LS firmwares is being moved to the subdevs where it belongs, rather than living in the common falcon code. This is an incremental step towards that goal. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/cmdq: explicitly create command queue(s) from subdevsBen Skeggs2020-01-151-1/+4
| | | | | | | | | Code to interface with LS firmwares is being moved to the subdevs where it belongs, rather than living in the common falcon code. This is an incremental step towards that goal. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/qmgr: explicitly create queue manager from subdevsBen Skeggs2020-01-151-0/+4
| | | | | | | | | Code to interface with LS firmwares is being moved to the subdevs where it belongs, rather than living in the common falcon code. This is an incremental step towards that goal. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn: reset sec2/gsp falcons harderBen Skeggs2020-01-151-1/+10
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn: specify queue register offsets from subdevBen Skeggs2020-01-152-0/+4
| | | | | | Also fixes the values for Turing, even though we don't use it yet. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn: specify debug/production register offset from subdevBen Skeggs2020-01-153-0/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn: specify EMEM address from subdevBen Skeggs2020-01-152-0/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn: move bind_context WAR out of common codeBen Skeggs2020-01-152-2/+42
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn: specify FBIF offset from subdevBen Skeggs2020-01-155-0/+5
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvenc: add a stub implementation for the GPUs where it should be ↵Ben Skeggs2020-01-155-4/+173
| | | | | | | | supported Mostly so we don't lose info hidden in falcon. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvdec/gm107-: add missing engine instancesBen Skeggs2020-01-151-0/+8
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvdec/gm107: rename from gp102 implementationBen Skeggs2020-01-153-20/+20
| | | | | | | NVDEC is available from GM107, and we currently only have a stub implementation anyway, let's make it explicit. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvdec: initialise SW state for falcon from constructorBen Skeggs2020-01-153-21/+20
| | | | | | | This will allow us to register the falcon with ACR, and further customise its behaviour by providing the nvkm_falcon_func structure directly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvdec: select implementation based on available fwBen Skeggs2020-01-153-7/+45
| | | | | | | This will allow for further customisation of the subdev depending on what firmware is available. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/sec2: move interrupt handler to hw-specific moduleBen Skeggs2020-01-154-21/+31
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/sec2: use falcon funcsBen Skeggs2020-01-151-8/+6
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/sec2: initialise SW state for falcon from constructorBen Skeggs2020-01-154-20/+39
| | | | | | | This will allow us to register the falcon with ACR, and further customise its behaviour by providing the nvkm_falcon_func structure directly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/sec2: select implementation based on available firmwareBen Skeggs2020-01-155-24/+128
| | | | | | | This will allow for further customisation of the subdev depending on what firmware is available. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/sec2/gp108: split from gp102 implementationBen Skeggs2020-01-153-2/+31
| | | | | | | ACR LS FW loading is moving out of SECBOOT and into their specific subdevs, and the available GP108/GV100 FWs differ from the other GP10x boards. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gr/gf100-: initialise SW state for falcon from constructorBen Skeggs2020-01-154-34/+50
| | | | | | | This will allow us to register the falcon with ACR, and further customise its behaviour by providing the nvkm_falcon_func structure directly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gr/gf100-: select implementation based on available FWBen Skeggs2020-01-1522-176/+498
| | | | | | | This will allow for further customisation of the subdev depending on what firmware is available. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gr/gp108: split from gp107Ben Skeggs2020-01-155-2/+33
| | | | | | | ACR LS FW loading is moving out of SECBOOT and into their specific subdevs, and the available GP107/GP108 FWs have interface differences. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gr/gf100-: move fecs/gpccs ucode into their substructuresBen Skeggs2020-01-154-22/+25
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gr/gf100-: drop fuc_ prefix on sw initBen Skeggs2020-01-156-33/+27
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gr/gk20a,gm200-: use nvkm_firmware_load_blob for sw initBen Skeggs2020-01-153-48/+44
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gr/gf100-: use nvkm_blob structure for fecs/gpccs fwBen Skeggs2020-01-153-33/+20
| | | | | | It serves the exact same purpose. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pmu/gp10b: split from gm20b implementationBen Skeggs2020-01-151-1/+1
| | | | | | | ACR LS FW loading is moving out of SECBOOT and into their specific subdevs, and the available GM20B/GP10B FWs have interface differences. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/acr: add stub implementation for all GPUs currently supported by ↵Ben Skeggs2020-01-151-0/+12
| | | | | | | | | SECBOOT PMU, SEC2 and GR will be modified to register their falcons with ACR before the main commit switching everything over. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: define ACR subdevBen Skeggs2020-01-152-0/+3
| | | | | | | This will replace the current SECBOOT subdev for handling firmware on secure falcons. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/dp: fix typo when determining failsafe link configurationBen Skeggs2020-01-151-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gr/gv100-: modify gr init to match newer version of RMBen Skeggs2020-01-154-16/+27
| | | | | | Will be used as a basis for implementing changes needed for Turing. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gr/gk20a,gm200-: add terminators to method lists read from fwBen Skeggs2020-01-151-10/+11
| | | | | | | | | | | Method init is typically ordered by class in the FW image as ThreeD, TwoD, Compute. Due to a bug in parsing the FW into our internal format, we've been accidentally sending Twod + Compute methods to the ThreeD class, as well as Compute methods to the TwoD class - oops. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gr/gf100-: remove dtorBen Skeggs2020-01-152-3/+0
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ce/gp10b: Use correct copy engineThierry Reding2020-01-151-1/+1
| | | | | | | | | | | gp10b uses the new engine enumeration mechanism introduced in the Pascal architecture. As a result, the copy engine, which used to be at index 2 for prior Tegra GPU instantiations, has now moved to index 0. Fix up the index and also use the gp100 variant of the copy engine class because on gp10b the PASCAL_DMA_COPY_B class is not supported. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ltc/gp10b: Add custom L2 cache implementationThierry Reding2020-01-151-1/+1
| | | | | | | | | There are extra registers that need to be programmed to make the level 2 cache work on GP10B, such as the stream ID register that is used when an SMMU is used to translate memory addresses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/tegra: Set clock rate if not setThierry Reding2020-01-151-0/+12
| | | | | | | | If the GPU clock has not had a rate set, initialize it to the maximum clock rate to make sure it does run. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/tegra: Avoid pulsing reset twiceThierry Reding2020-01-151-6/+6
| | | | | | | | | | | | | | When the GPU powergate is controlled by a generic power domain provider, the reset will automatically be asserted and deasserted as part of the power-ungating procedure. On some Jetson TX2 boards, doing an additional assert and deassert of the GPU outside of the power-ungate procedure can cause the GPU to go into a bad state where the memory interface can no longer access system memory. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fault: Add support for GP10BThierry Reding2020-01-151-1/+1
| | | | | | | | | | | There is no BAR2 on GP10B and there is no need to map through BAR2 because all memory is shared between the GPU and the CPU. Add a custom implementation of the fault sub-device that uses nvkm_memory_addr() instead of nvkm_memory_bar2() to return the address of a pinned fault buffer. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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