diff options
Diffstat (limited to 'src/ppe/hwp/perv')
30 files changed, 1978 insertions, 62 deletions
diff --git a/src/ppe/hwp/perv/p9_sbe_arrayinit.C b/src/ppe/hwp/perv/p9_sbe_arrayinit.C new file mode 100644 index 0000000..e6ae399 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_arrayinit.C @@ -0,0 +1,53 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_arrayinit.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_arrayinit.C +/// +/// @brief array init procedure to be called with any chiplet target +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_arrayinit.H" + + + +fapi2::ReturnCode p9_sbe_arrayinit(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip) +{ + FAPI_DBG("Entering ..."); + + FAPI_DBG("Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_arrayinit.H b/src/ppe/hwp/perv/p9_sbe_arrayinit.H new file mode 100644 index 0000000..6e82ed1 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_arrayinit.H @@ -0,0 +1,60 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_arrayinit.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_arrayinit.H +/// +/// @brief array init procedure to be called with any chiplet target +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_ARRAYINIT_H_ +#define _P9_SBE_ARRAYINIT_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_arrayinit_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &); + +/// @brief --Run arrayinit on all enabled chiplets +/// --Scan flush 0 to all rings except GPTR, Time, Repair on all enabled chiplets +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_arrayinit(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_arrayinit_errors.xml b/src/ppe/hwp/perv/p9_sbe_arrayinit_errors.xml new file mode 100644 index 0000000..4e7f371 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_arrayinit_errors.xml @@ -0,0 +1,36 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/ppe/hwp/perv/p9_sbe_arrayinit_errors.xml $ --> +<!-- --> +<!-- OpenPOWER OnChipController Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2015 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- This is an automatically generated file. --> +<!-- File: p9_sbe_arrayinit_errors.xml. --> +<!-- Halt codes for p9_sbe_arrayinit --> + +<hwpErrors> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_ABIST_DONE</rc> + <description>Check Abist Done bit after Array Init</description> + </hwpError> + <!-- ******************************************************************** --> +</hwpErrors> diff --git a/src/ppe/hwp/perv/p9_sbe_chiplet_init.C b/src/ppe/hwp/perv/p9_sbe_chiplet_init.C new file mode 100644 index 0000000..65cf28d --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_chiplet_init.C @@ -0,0 +1,55 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_chiplet_init.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_init.C +/// +/// @brief init procedure for all enabled chiplets +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_chiplet_init.H" + + + +fapi2::ReturnCode p9_sbe_chiplet_init(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip) +{ + FAPI_DBG("Entering ..."); + + FAPI_DBG("Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_chiplet_init.H b/src/ppe/hwp/perv/p9_sbe_chiplet_init.H new file mode 100644 index 0000000..d79634d --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_chiplet_init.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_chiplet_init.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_init.H +/// +/// @brief init procedure for all enabled chiplets +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_CHIPLET_INIT_H_ +#define _P9_SBE_CHIPLET_INIT_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_chiplet_init_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &); + +/// @brief Scan 0 all rings (except time, repair, gptr) on all enabled chiplets +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_chiplet_init(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_chiplet_init_errors.xml b/src/ppe/hwp/perv/p9_sbe_chiplet_init_errors.xml new file mode 100644 index 0000000..6796f1e --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_chiplet_init_errors.xml @@ -0,0 +1,49 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/ppe/hwp/perv/p9_sbe_chiplet_init_errors.xml $ --> +<!-- --> +<!-- OpenPOWER OnChipController Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2015 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- This is an automatically generated file. --> +<!-- File: p9_sbe_chiplet_init_errors.xml. --> +<!-- Halt codes for p9_sbe_chiplet_init --> + +<hwpErrors> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_CHECKSTOP_STAGE_1_ERR</rc> + <description>Checkstop error after MC config</description> + <ffdc>CHIP</ffdc> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_CHECKSTOP_STAGE_2_ERR</rc> + <description>Checkstop error after scan0</description> + <ffdc>CHIP</ffdc> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_CHECKSTOP_STAGE_3_ERR</rc> + <description>Checkstop checks</description> + <ffdc>CHIP</ffdc> + </hwpError> + <!-- ******************************************************************** --> +</hwpErrors> diff --git a/src/ppe/hwp/perv/p9_sbe_chiplet_pll_initf.C b/src/ppe/hwp/perv/p9_sbe_chiplet_pll_initf.C new file mode 100644 index 0000000..3b2ab46 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_chiplet_pll_initf.C @@ -0,0 +1,55 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_chiplet_pll_initf.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_pll_initf.C +/// +/// @brief procedure for scan initializing PLL config bits for L2 and L3 plls +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : srinivas naga Email: srinivan@in.ibm.com +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_chiplet_pll_initf.H" + + + +fapi2::ReturnCode p9_sbe_chiplet_pll_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip) +{ + FAPI_DBG("Entering ..."); + + FAPI_DBG("Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_chiplet_pll_initf.H b/src/ppe/hwp/perv/p9_sbe_chiplet_pll_initf.H new file mode 100644 index 0000000..ce69926 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_chiplet_pll_initf.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_chiplet_pll_initf.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_pll_initf.H +/// +/// @brief procedure for scan initializing PLL config bits for L2 and L3 plls +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : srinivas naga Email: srinivan@in.ibm.com +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_CHIPLET_PLL_INITF_H_ +#define _P9_SBE_CHIPLET_PLL_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_chiplet_pll_initf_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &); + +/// @brief load the pll config settings for L2 AND L3 plls +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_chiplet_pll_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_chiplet_pll_setup.C b/src/ppe/hwp/perv/p9_sbe_chiplet_pll_setup.C new file mode 100644 index 0000000..f7e2c38 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_chiplet_pll_setup.C @@ -0,0 +1,55 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_chiplet_pll_setup.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_pll_setup.C +/// +/// @brief PLL set up for L2 and L3 plls +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_chiplet_pll_setup.H" + + + +fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip) +{ + FAPI_DBG("Entering ..."); + + FAPI_DBG("Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_chiplet_pll_setup.H b/src/ppe/hwp/perv/p9_sbe_chiplet_pll_setup.H new file mode 100644 index 0000000..3e997de --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_chiplet_pll_setup.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_chiplet_pll_setup.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_pll_setup.H +/// +/// @brief PLL set up for L2 and L3 plls +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_CHIPLET_PLL_SETUP_H_ +#define _P9_SBE_CHIPLET_PLL_SETUP_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_chiplet_pll_setup_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &); + +/// @brief PLL setup for L2 and L3 levels +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_chiplet_reset.C b/src/ppe/hwp/perv/p9_sbe_chiplet_reset.C new file mode 100644 index 0000000..1b10744 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_chiplet_reset.C @@ -0,0 +1,58 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_chiplet_reset.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_reset.C +/// +/// @brief Identify all good chiplets excluding EQ/EC +/// Setup multicast groups for all chiplets +/// For all good chiplets excluding EQ/EC +/// For all enabled chiplets +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_chiplet_reset.H" + + + +fapi2::ReturnCode p9_sbe_chiplet_reset(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip) +{ + FAPI_DBG("Entering ..."); + + FAPI_DBG("Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_chiplet_reset.H b/src/ppe/hwp/perv/p9_sbe_chiplet_reset.H new file mode 100644 index 0000000..91f0ef9 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_chiplet_reset.H @@ -0,0 +1,78 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_chiplet_reset.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_reset.H +/// +/// @brief Identify all good chiplets excluding EQ/EC +/// Setup multicast groups for all chiplets +/// For all good chiplets excluding EQ/EC +/// For all enabled chiplets +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_CHIPLET_RESET_H_ +#define _P9_SBE_CHIPLET_RESET_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_chiplet_reset_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &); + +/// @brief Identify all good chiplets excluding EQ/EC +/// -- All chiplets will be reset and PLLs started +/// -- Partial bad - All nest Chiplets must be good, MC, IO can be partial bad +/// Setup multicast groups for all chiplets +/// -- Can't use the multicast for all non-nest chiplets +/// -- This is intended to be the eventual product setting +/// -- This includes the core/cache chiplets +/// For all good chiplets excluding EQ/EC +/// -- Setup Chiplet GP3 regs +/// -- Reset to default state +/// -- Set chiplet enable on all all good chiplets excluding EQ/EC +/// For all enabled chiplets +/// -- Start vital clocks and release endpoint reset +/// -- PCB Slave error register Reset +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_chiplet_reset(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_gptr_time_repr_initf.C b/src/ppe/hwp/perv/p9_sbe_gptr_time_repr_initf.C new file mode 100644 index 0000000..179a0a4 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_gptr_time_repr_initf.C @@ -0,0 +1,55 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_gptr_time_repr_initf.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_gptr_time_repr_initf.C +/// +/// @brief Scan 0 and Load repair , time and GPTR rings for all enabled chiplets +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_gptr_time_repr_initf.H" + + + +fapi2::ReturnCode p9_sbe_gptr_time_repr_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip) +{ + FAPI_DBG("Entering ..."); + + FAPI_DBG("Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_gptr_time_repr_initf.H b/src/ppe/hwp/perv/p9_sbe_gptr_time_repr_initf.H new file mode 100644 index 0000000..4fb1104 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_gptr_time_repr_initf.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_gptr_time_repr_initf.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_gptr_time_repr_initf.H +/// +/// @brief Scan 0 and Load repair , time and GPTR rings for all enabled chiplets +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_GPTR_TIME_REPR_INITF_H_ +#define _P9_SBE_GPTR_TIME_REPR_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_gptr_time_repr_initf_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &); + +/// @brief Scan 0 all rings on all enabled chiplets (except for TP) +/// Load Repair, Time and GPTR rings for all enabled chiplets +/// -- All chip customization data is within the repair and time rings -- array repair, DTS setting +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_gptr_time_repr_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_nest_enable_ridi.C b/src/ppe/hwp/perv/p9_sbe_nest_enable_ridi.C new file mode 100644 index 0000000..19c0e15 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_nest_enable_ridi.C @@ -0,0 +1,55 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_nest_enable_ridi.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_enable_ridi.C +/// +/// @brief Enable ridi controls for NEST logic +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_nest_enable_ridi.H" + + + +fapi2::ReturnCode p9_sbe_nest_enable_ridi(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip) +{ + FAPI_DBG("Entering ..."); + + FAPI_DBG("Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_nest_enable_ridi.H b/src/ppe/hwp/perv/p9_sbe_nest_enable_ridi.H new file mode 100644 index 0000000..e18ecc6 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_nest_enable_ridi.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_nest_enable_ridi.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_enable_ridi.H +/// +/// @brief Enable ridi controls for NEST logic +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_NEST_ENABLE_RIDI_H_ +#define _P9_SBE_NEST_ENABLE_RIDI_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_nest_enable_ridi_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &); + +/// @brief procedure enables ridi for nest region +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_nest_enable_ridi(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_setup_evid.C b/src/ppe/hwp/perv/p9_sbe_setup_evid.C new file mode 100644 index 0000000..c998a29 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_setup_evid.C @@ -0,0 +1,82 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_setup_evid.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_sbe_setup_evid.C +/// @brief Setup External Voltage IDs and Boot Frequency +/// +// *HW Owner : Greg Still <stillgs@us.ibm.com> +// *FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *Team : PM +// *Consumed by : SBE +// *Level : 1 +/// +/// @verbatim +/// Procedure Summary: +/// - Use Attributes to send VDD, VCS via the AVS bus to VRMs +/// - Use Attributes to adjust the VDN and send via I2C to VRM +/// - Read core frequency ATTR and write to the Quad PPM +/// @endverbatim + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +#include "p9_sbe_setup_evid.H" + +//----------------------------------------------------------------------------- +// Procedure +//----------------------------------------------------------------------------- + +fapi2::ReturnCode +p9_sbe_setup_evid(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) +{ + + //fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS; + + // Substep indicators + + // commented out in Level 1 to not have "unused variable" warnings + // until the SBE substep management "macro" or "call" is defined. + + // const uint32_t STEP_SBE_EVID_START = 0x1; + // const uint32_t STEP_SBE_EVID_CONFIG = 0x2; + // const uint32_t STEP_SBE_EVID_WRITE_VDN = 0x3; + // const uint32_t STEP_SBE_EVID_POLL_VDN_STATUS = 0x4; + // const uint32_t STEP_SBE_EVID_WRITE_VDD = 0x5; + // const uint32_t STEP_SBE_EVID_POLL_VDD_STATUS = 0x6; + // const uint32_t STEP_SBE_EVID_WRITE_VCS = 0x7; + // const uint32_t STEP_SBE_EVID_POLL_VCS_STATUS = 0x8; + // const uint32_t STEP_SBE_EVID_TIMEOUT = 0x9; + // const uint32_t STEP_SBE_EVID_BOOT_FREQ = 0xA; + // const uint32_t STEP_SBE_EVID_COMPLETE = 0xB; + +// The inclusion of the following will cause a "label 'fapi_try_exit' defined but not used" +// compile error in Cronus. This will be uncommented when FAPI_TRY functions are added +// during the real procedure development. However, this is NOT needed for Level 1. +//fapi_try_exit: + return fapi2::current_err; + +} // Procedure + diff --git a/src/ppe/hwp/perv/p9_sbe_setup_evid.H b/src/ppe/hwp/perv/p9_sbe_setup_evid.H new file mode 100644 index 0000000..c543f62 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_setup_evid.H @@ -0,0 +1,65 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_setup_evid.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_sbe_setup_evid.H +/// @brief Setup External Voltage IDs and Boot Frequency +/// +/// *HW Owner : Greg Still <stillgs@us.ibm.com> +/// *FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *Team : PM +/// *Consumed by : SBE +/// *Level : 1 +/// + +#ifndef __P9_SBE_SETUP_EVID_H__ +#define __P9_SBE_SETUP_EVID_H__ + +extern "C" +{ + +/// @typedef p9_sbe_setup_evid_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_sbe_setup_evid_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &); + +/// @brief Read attributes containing this part's boot voltages (VDD, VCS and VDN) +/// and set these voltage using the AVSBUS interface (VDD, VCS) an I2C (VDN). +/// Also reads a differnt attribute containing the boot frequency and set that +/// into each configured EQ chiplet. +/// @param [in] i_target TARGET_TYPE_PROC_CHIP +/// @attr +/// @attritem ATTR_BOOT_FREQ uint16_t - 9 bit frequency multiplier of the refclk right justified +/// @attritem ATTR_VCS_BOOT_VOLTAGE uint16_t - 1mV grandularity setting for the VCS rail +/// @attritem ATTR_VDD_BOOT_VOLTAGE uint16_t - 1mV grandularity setting for the VDD rail +/// @attritem ATTR_VDN_BOOT_VOLTAGE uint16_t - 1mV grandularity setting for the VDN rail +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_sbe_setup_evid(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + + +} // extern C + +#endif // __P9_SBE_SETUP_EVID_H__ diff --git a/src/ppe/hwp/perv/p9_sbe_setup_evid_errors.xml b/src/ppe/hwp/perv/p9_sbe_setup_evid_errors.xml new file mode 100644 index 0000000..588797d --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_setup_evid_errors.xml @@ -0,0 +1,56 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/ppe/hwp/perv/p9_sbe_setup_evid_errors.xml $ --> +<!-- --> +<!-- OpenPOWER OnChipController Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2015 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> + +<!-- *HWP HWP Owner: Greg Still <stillgs @us.ibm.com> --> +<!-- *HWP FW Owner: Bilicon Patil <bilpatil@in.ibm.com> --> +<!-- *HWP Team: PM --> +<!-- *HWP Level: 1 --> +<!-- *HWP Consumed by: FSP:HS --> + +<!-- Error definitions for p9_avsbus_lib procedure --> +<hwpErrors> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_PROCPM_EVID_READVOLTAGE_TIMEOUT</rc> + <description> + A timeout occured reading voltage from an AVSBus interface + </description> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_PROCPM_EVID_WRITEVOLTAGE_TIMEOUT</rc> + <description> + A timeout occured writing a voltage to an AVSBus interface + </description> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_PROCPM_EVID_IDLEFRAME_TIMEOUT</rc> + <description> + A timeout occured writing an idle from to an AVSBus interface + </description> + </hwpError> + <!-- ******************************************************************** --> +</hwpErrors> diff --git a/src/ppe/hwp/perv/p9_sbe_startclock_chiplets.C b/src/ppe/hwp/perv/p9_sbe_startclock_chiplets.C new file mode 100644 index 0000000..f91cde3 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_startclock_chiplets.C @@ -0,0 +1,53 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_startclock_chiplets.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_startclock_chiplets.C +/// +/// @brief Start clock procedure for XBUS, OBUS, PCIe +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_startclock_chiplets.H" + + + +fapi2::ReturnCode p9_sbe_startclock_chiplets(const + fapi2::Target<fapi2::TARGET_TYPE_PERV> & i_target_chiplets) +{ + FAPI_DBG("Entering ..."); + + FAPI_DBG("Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_startclock_chiplets.H b/src/ppe/hwp/perv/p9_sbe_startclock_chiplets.H new file mode 100644 index 0000000..2e7a413 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_startclock_chiplets.H @@ -0,0 +1,60 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_startclock_chiplets.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_startclock_chiplets.H +/// +/// @brief Start clock procedure for XBUS, OBUS, PCIe +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_STARTCLOCK_CHIPLETS_H_ +#define _P9_SBE_STARTCLOCK_CHIPLETS_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_startclock_chiplets_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PERV> &); + +/// @brief Start Xbus, Obus, PCIe clocks +/// Start clocks on configured chiplets for all chips (master and slaves) +/// +/// @param[in] i_target_chiplets Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_startclock_chiplets(const + fapi2::Target<fapi2::TARGET_TYPE_PERV> & i_target_chiplets); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.C b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.C index 4756b0b..bfb01b6 100644 --- a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.C +++ b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.C @@ -25,28 +25,62 @@ //------------------------------------------------------------------------------ /// @file p9_sbe_tp_chiplet_init1.C /// -/// @brief IPL STEP 2.3: SBE TP Chiplet Init 1 :: Releases PCB Reset, Sets TP chiplet enable, Drops Perv chiplet fence -// *! -// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com -// *! BACKUP NAME : Email: +/// @brief Initial steps of PIB AND PCB //------------------------------------------------------------------------------ -// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> -// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> -// *HWP Team : Perv -// *HWP Level : 1 -// *HWP Consumed by : SBE +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE //------------------------------------------------------------------------------ //## auto_generated #include "p9_sbe_tp_chiplet_init1.H" + +#include "perv_scom_addresses.H" + + fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip) { - FAPI_DBG("p9_sbe_tp_chiplet_init1: Entering ..."); + fapi2::buffer<uint64_t> l_data64; + FAPI_DBG("Entering ..."); + + //Setting ROOT_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + l_data64.clearBit<15>(); //PIB.ROOT_CTRL0.VDD2VIO_LVL_FENCE_DC = 0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + + FAPI_INF("Release PCB Reset"); + //Setting ROOT_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + l_data64.clearBit<30>(); //PIB.ROOT_CTRL0.PCB_RESET_DC = 0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + + FAPI_INF("Set Chiplet Enable"); + //Setting PERV_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64)); + l_data64.setBit<0>(); //PIB.PERV_CTRL0.TP_CHIPLET_EN_DC = 1 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64)); + + FAPI_INF("Drop TP Chiplet Fence Enable"); + //Setting PERV_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64)); + l_data64.clearBit<18>(); //PIB.PERV_CTRL0.TP_FENCE_EN_DC = 0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64)); + + FAPI_INF("Drop Global Endpoint reset"); + //Setting ROOT_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + l_data64.clearBit<31>(); //PIB.ROOT_CTRL0.GLOBAL_EP_RESET_DC = 0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + FAPI_INF("Switching PIB trace bus to SBE tracing"); - FAPI_DBG("p9_sbe_tp_chiplet_init1: Exiting ..."); + FAPI_DBG("Exiting ..."); - return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; } diff --git a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.H b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.H index 601c167..11547f3 100644 --- a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.H +++ b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.H @@ -25,16 +25,14 @@ //------------------------------------------------------------------------------ /// @file p9_sbe_tp_chiplet_init1.H /// -/// @brief IPL STEP 2.3: SBE TP Chiplet Init 1 :: Releases PCB Reset, Sets TP chiplet enable, Drops Perv chiplet fence -// *! -// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com -// *! BACKUP NAME : Email: +/// @brief Initial steps of PIB AND PCB //------------------------------------------------------------------------------ -// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> -// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> -// *HWP Team : Perv -// *HWP Level : 1 -// *HWP Consumed by : SBE +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE //------------------------------------------------------------------------------ @@ -48,11 +46,10 @@ typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_init1_FP_t)( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &); -/// @brief DESCRIPTION -- Drop VSS2VIO fence -/// -- Releases PCB reset -/// -- Sets PRV Chiplet Enable -/// -- Drops PRV Chiplet fence enable -/// -- Drop Global Endpoint Reset +/// @brief Releases the Pervasive Control Bus (PCB) reset +/// Sets TP chiplet enable +/// Drops pervasive chiplet fences +/// /// /// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target /// @return FAPI2_RC_SUCCESS if success, else error code. diff --git a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.C b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.C index bc90079..358885e 100644 --- a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.C +++ b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.C @@ -25,28 +25,37 @@ //------------------------------------------------------------------------------ /// @file p9_sbe_tp_chiplet_reset.C /// -/// @brief IPL STEP 2.8 : SBE TP Chiplet Reset :: setup hangcounter 6 for TP chiplet -// *! -// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com -// *! BACKUP NAME : Email: +/// @brief setup hangcounter 6 for TP chiplet //------------------------------------------------------------------------------ -// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> -// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> -// *HWP Team : Perv -// *HWP Level : 1 -// *HWP Consumed by : SBE +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE //------------------------------------------------------------------------------ //## auto_generated #include "p9_sbe_tp_chiplet_reset.H" + +#include "perv_scom_addresses.H" + + fapi2::ReturnCode p9_sbe_tp_chiplet_reset(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip) { - FAPI_DBG("p9_sbe_tp_chiplet_reset: Entering ..."); + FAPI_DBG("Entering ..."); + + FAPI_INF("Initializing Hangcounter 6 for PRV Cplt"); + //Setting HANG_PULSE_6_REG register value + //PERV.HANG_PULSE_6_REG = HANG_PULSE_VALUE + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_HANG_PULSE_6_REG, + HANG_PULSE_VALUE)); - FAPI_DBG("p9_sbe_tp_chiplet_reset: Exiting ..."); + FAPI_DBG("Exiting ..."); - return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; } diff --git a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.H b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.H index 9f3c7ae..b972831 100644 --- a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.H +++ b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.H @@ -25,16 +25,14 @@ //------------------------------------------------------------------------------ /// @file p9_sbe_tp_chiplet_reset.H /// -/// @brief IPL STEP 2.8 : SBE TP Chiplet Reset :: setup hangcounter 6 for TP chiplet -// *! -// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com -// *! BACKUP NAME : Email: +/// @brief setup hangcounter 6 for TP chiplet //------------------------------------------------------------------------------ -// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> -// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> -// *HWP Team : Perv -// *HWP Level : 1 -// *HWP Consumed by : SBE +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE //------------------------------------------------------------------------------ @@ -45,10 +43,15 @@ #include <fapi2.H> +enum P9_SBE_TP_CHIPLET_RESET_Constants +{ + HANG_PULSE_VALUE = 0x0c00000000000000 +}; + typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_reset_FP_t)( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &); -/// @brief --Setup hang counter for PCB slaves/master +/// @brief Setup hang counter for PCB slaves/master /// /// /// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target diff --git a/src/ppe/hwp/perv/p9_sbe_tp_enable_ridi.C b/src/ppe/hwp/perv/p9_sbe_tp_enable_ridi.C new file mode 100644 index 0000000..7fb1bcc --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_tp_enable_ridi.C @@ -0,0 +1,64 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_tp_enable_ridi.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_enable_ridi.C +/// +/// @brief enables ridi bits in RC regs after scan initialize and start clock the pervasive chiplet +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_enable_ridi.H" + +#include "perv_scom_addresses.H" + + +fapi2::ReturnCode p9_sbe_tp_enable_ridi(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_DBG("Entering ..."); + + FAPI_INF("Enable Recievers, Drivers DI1 & DI2"); + //Setting ROOT_CTRL1 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL1_SCOM, l_data64)); + l_data64.setBit<19>(); //PIB.ROOT_CTRL1.TP_RI_DC_B = 1 + l_data64.setBit<20>(); //PIB.ROOT_CTRL1.TP_DI1_DC_B = 1 + l_data64.setBit<21>(); //PIB.ROOT_CTRL1.TP_DI2_DC_B = 1 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL1_SCOM, l_data64)); + + FAPI_DBG("Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_tp_enable_ridi.H b/src/ppe/hwp/perv/p9_sbe_tp_enable_ridi.H new file mode 100644 index 0000000..d96bb51 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_tp_enable_ridi.H @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_tp_enable_ridi.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_enable_ridi.H +/// +/// @brief enables ridi bits in RC regs after scan initialize and start clock the pervasive chiplet +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_ENABLE_RIDI_H_ +#define _P9_SBE_TP_ENABLE_RIDI_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_enable_ridi_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &); + +/// @brief Enable drivers/receivers for PRV chiplet +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_enable_ridi(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/pervasive.act b/src/ppe/hwp/perv/pervasive.act new file mode 100644 index 0000000..9c19ccc --- /dev/null +++ b/src/ppe/hwp/perv/pervasive.act @@ -0,0 +1,472 @@ +# ============================================================================= +# Simics action for p9_sbe_arrayinit and p9_sbe_chiplet_init +# ============================================================================= + +CAUSE_EFFECT{ +LABEL=[SEEPROM ARRAY INIT for N0] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x02030002)] +# OPCG_REG0.RUNN_MODE = 1 +CAUSE: TARGET=[REG(0x02030002)] OP=[BIT,ON] BIT=[0] +# OPCG_REG0.OPCG_STARTS_BIST = 1 +CAUSE: TARGET=[REG(0x02030002)] OP=[BIT,ON] BIT=[14] +# OPCG_REG0.OPCG_GO = 1 +CAUSE: TARGET=[REG(0x02030002)] OP=[BIT,ON] BIT=[1] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x02000100)] OP=[BIT,ON] BIT=[8] +# SRAM Abist Done +EFFECT: TARGET=[REG(0x02000100)] OP=[BIT,ON] BIT=[0] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM SCAN0 MODULE for N0] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x02030002)] +# OPCG_REG0.RUN_SCAN0 = 1 +CAUSE: TARGET=[REG(0x02030002)] OP=[BIT,ON] BIT=[2] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x02000100)] OP=[BIT,ON] BIT=[8] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM ARRAY INIT for N1] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x03030002)] +# # OPCG_REG0.RUNN_MODE = 1 +CAUSE: TARGET=[REG(0x03030002)] OP=[BIT,ON] BIT=[0] +# OPCG_REG0.OPCG_STARTS_BIST = 1 +CAUSE: TARGET=[REG(0x03030002)] OP=[BIT,ON] BIT=[14] +# OPCG_REG0.OPCG_GO = 1 +CAUSE: TARGET=[REG(0x03030002)] OP=[BIT,ON] BIT=[1] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x03000100)] OP=[BIT,ON] BIT=[8] +# SRAM Abist Done +EFFECT: TARGET=[REG(0x03000100)] OP=[BIT,ON] BIT=[0] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM SCAN0 MODULE for N1] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x03030002)] +# OPCG_REG0.RUN_SCAN0 = 1 +CAUSE: TARGET=[REG(0x03030002)] OP=[BIT,ON] BIT=[2] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x03000100)] OP=[BIT,ON] BIT=[8] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM ARRAY INIT for N2] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x04030002)] +# OPCG_REG0.RUNN_MODE = 1 +CAUSE: TARGET=[REG(0x04030002)] OP=[BIT,ON] BIT=[0] +# OPCG_REG0.OPCG_STARTS_BIST = 1 +CAUSE: TARGET=[REG(0x04030002)] OP=[BIT,ON] BIT=[14] +# OPCG_REG0.OPCG_GO = 1 +CAUSE: TARGET=[REG(0x04030002)] OP=[BIT,ON] BIT=[1] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x04000100)] OP=[BIT,ON] BIT=[8] +# SRAM Abist Done +EFFECT: TARGET=[REG(0x04000100)] OP=[BIT,ON] BIT=[0] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM SCAN0 MODULE for N2] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x04030002)] +# OPCG_REG0.RUN_SCAN0 = 1 +CAUSE: TARGET=[REG(0x04030002)] OP=[BIT,ON] BIT=[2] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x04000100)] OP=[BIT,ON] BIT=[8] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM ARRAY INIT for N3] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x05030002)] +# OPCG_REG0.RUNN_MODE = 1 +CAUSE: TARGET=[REG(0x05030002)] OP=[BIT,ON] BIT=[0] +# OPCG_REG0.OPCG_STARTS_BIST = 1 +CAUSE: TARGET=[REG(0x05030002)] OP=[BIT,ON] BIT=[14] +# OPCG_REG0.OPCG_GO = 1 +CAUSE: TARGET=[REG(0x05030002)] OP=[BIT,ON] BIT=[1] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x05000100)] OP=[BIT,ON] BIT=[8] +# SRAM Abist Done +EFFECT: TARGET=[REG(0x05000100)] OP=[BIT,ON] BIT=[0] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM SCAN0 MODULE for N3] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x05030002)] +# OPCG_REG0.RUN_SCAN0 = 1 +CAUSE: TARGET=[REG(0x05030002)] OP=[BIT,ON] BIT=[2] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x05000100)] OP=[BIT,ON] BIT=[8] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM ARRAY INIT for XB] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x06030002)] +# OPCG_REG0.RUNN_MODE = 1 +CAUSE: TARGET=[REG(0x06030002)] OP=[BIT,ON] BIT=[0] +# OPCG_REG0.OPCG_STARTS_BIST = 1 +CAUSE: TARGET=[REG(0x06030002)] OP=[BIT,ON] BIT=[14] +# OPCG_REG0.OPCG_GO = 1 +CAUSE: TARGET=[REG(0x06030002)] OP=[BIT,ON] BIT=[1] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x06000100)] OP=[BIT,ON] BIT=[8] +# SRAM Abist Done +EFFECT: TARGET=[REG(0x06000100)] OP=[BIT,ON] BIT=[0] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM SCAN0 MODULE for XB] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x06030002)] +OPCG_REG0.RUN_SCAN0 = 1 +CAUSE: TARGET=[REG(0x06030002)] OP=[BIT,ON] BIT=[2] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x06000100)] OP=[BIT,ON] BIT=[8] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM ARRAY INIT for MC01] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x07030002)] +# OPCG_REG0.RUNN_MODE = 1 +CAUSE: TARGET=[REG(0x07030002)] OP=[BIT,ON] BIT=[0] +# OPCG_REG0.OPCG_STARTS_BIST = 1 +CAUSE: TARGET=[REG(0x07030002)] OP=[BIT,ON] BIT=[14] +# OPCG_REG0.OPCG_GO = 1 +CAUSE: TARGET=[REG(0x07030002)] OP=[BIT,ON] BIT=[1] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x07000100)] OP=[BIT,ON] BIT=[8] +# SRAM Abist Done +EFFECT: TARGET=[REG(0x07000100)] OP=[BIT,ON] BIT=[0] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM SCAN0 MODULE for MC01] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x07030002)] +# OPCG_REG0.RUN_SCAN0 = 1 +CAUSE: TARGET=[REG(0x07030002)] OP=[BIT,ON] BIT=[2] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x07000100)] OP=[BIT,ON] BIT=[8] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM ARRAY INIT for MC029] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x08030002)] +# OPCG_REG0.RUNN_MODE = 1 +CAUSE: TARGET=[REG(0x08030002)] OP=[BIT,ON] BIT=[0] +# OPCG_REG0.OPCG_STARTS_BIST = 1 +CAUSE: TARGET=[REG(0x08030002)] OP=[BIT,ON] BIT=[14] +# OPCG_REG0.OPCG_GO = 1 +CAUSE: TARGET=[REG(0x08030002)] OP=[BIT,ON] BIT=[1] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x08000100)] OP=[BIT,ON] BIT=[8] +# SRAM Abist Done +EFFECT: TARGET=[REG(0x08000100)] OP=[BIT,ON] BIT=[0] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM SCAN0 MODULE for MC029] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x08030002)] +# OPCG_REG0.RUN_SCAN0 = 1 +CAUSE: TARGET=[REG(0x08030002)] OP=[BIT,ON] BIT=[2] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x08000100)] OP=[BIT,ON] BIT=[8] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM ARRAY INIT for OB0] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x09030002)] +#OPCG_REG0.RUNN_MODE = 1 +CAUSE: TARGET=[REG(0x09030002)] OP=[BIT,ON] BIT=[0] +# OPCG_REG0.OPCG_STARTS_BIST = 1 +CAUSE: TARGET=[REG(0x09030002)] OP=[BIT,ON] BIT=[14] +# OPCG_REG0.OPCG_GO = 1 +CAUSE: TARGET=[REG(0x09030002)] OP=[BIT,ON] BIT=[1] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x09000100)] OP=[BIT,ON] BIT=[8] +# SRAM Abist Done +EFFECT: TARGET=[REG(0x09000100)] OP=[BIT,ON] BIT=[0] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM SCAN0 MODULE for OB0] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x09030002)] +# OPCG_REG0.RUN_SCAN0 = 1 +CAUSE: TARGET=[REG(0x09030002)] OP=[BIT,ON] BIT=[2] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x09000100)] OP=[BIT,ON] BIT=[8] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM ARRAY INIT for OB1] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x0A030002)] +# OPCG_REG0.RUNN_MODE = 1 +CAUSE: TARGET=[REG(0x0A030002)] OP=[BIT,ON] BIT=[0] +# OPCG_REG0.OPCG_STARTS_BIST = 1 +CAUSE: TARGET=[REG(0x0A030002)] OP=[BIT,ON] BIT=[14] +# OPCG_REG0.OPCG_GO = 1 +CAUSE: TARGET=[REG(0x0A030002)] OP=[BIT,ON] BIT=[1] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x0A000100)] OP=[BIT,ON] BIT=[8] +# SRAM Abist Done +EFFECT: TARGET=[REG(0x0A000100)] OP=[BIT,ON] BIT=[0] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM SCAN0 MODULE for OB1] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x0A030002)] +# OPCG_REG0.RUN_SCAN0 = 1 +CAUSE: TARGET=[REG(0x0A030002)] OP=[BIT,ON] BIT=[2] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x0A000100)] OP=[BIT,ON] BIT=[8] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM ARRAY INIT for OB2] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x0B030002)] +# OPCG_REG0.RUNN_MODE = 1 +CAUSE: TARGET=[REG(0x0B030002)] OP=[BIT,ON] BIT=[0] +# OPCG_REG0.OPCG_STARTS_BIST = 1 +CAUSE: TARGET=[REG(0x0B030002)] OP=[BIT,ON] BIT=[14] +# OPCG_REG0.OPCG_GO = 1 +CAUSE: TARGET=[REG(0x0B030002)] OP=[BIT,ON] BIT=[1] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x0B000100)] OP=[BIT,ON] BIT=[8] +# SRAM Abist Done +EFFECT: TARGET=[REG(0x0B000100)] OP=[BIT,ON] BIT=[0] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM SCAN0 MODULE for OB2] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x0B030002)] +# OPCG_REG0.RUN_SCAN0 = 1 +CAUSE: TARGET=[REG(0x0B030002)] OP=[BIT,ON] BIT=[2] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x0B000100)] OP=[BIT,ON] BIT=[8] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM ARRAY INIT for OB3] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x0C030002)] +# OPCG_REG0.RUNN_MODE = 1 +CAUSE: TARGET=[REG(0x0C030002)] OP=[BIT,ON] BIT=[0] +# OPCG_REG0.OPCG_STARTS_BIST = 1 +CAUSE: TARGET=[REG(0x0C030002)] OP=[BIT,ON] BIT=[14] +# OPCG_REG0.OPCG_GO = 1 +CAUSE: TARGET=[REG(0x0C030002)] OP=[BIT,ON] BIT=[1] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x0C000100)] OP=[BIT,ON] BIT=[8] +# SRAM Abist Done +EFFECT: TARGET=[REG(0x0C000100)] OP=[BIT,ON] BIT=[0] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM SCAN0 MODULE for OB3] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x0C030002)] +# OPCG_REG0.RUN_SCAN0 = 1 +CAUSE: TARGET=[REG(0x0C030002)] OP=[BIT,ON] BIT=[2] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x0C000100)] OP=[BIT,ON] BIT=[8] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM ARRAY INIT for PCI0] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x0D030002)] +# OPCG_REG0.RUNN_MODE = 1 +CAUSE: TARGET=[REG(0x0D030002)] OP=[BIT,ON] BIT=[0] +# OPCG_REG0.OPCG_STARTS_BIST = 1 +CAUSE: TARGET=[REG(0x0D030002)] OP=[BIT,ON] BIT=[14] +# OPCG_REG0.OPCG_GO = 1 +CAUSE: TARGET=[REG(0x0D030002)] OP=[BIT,ON] BIT=[1] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x0D000100)] OP=[BIT,ON] BIT=[8] +# SRAM Abist Done +EFFECT: TARGET=[REG(0x0D000100)] OP=[BIT,ON] BIT=[0] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM SCAN0 MODULE for PCI0] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x0D030002)] +# OPCG_REG0.RUN_SCAN0 = 1 +CAUSE: TARGET=[REG(0x0D030002)] OP=[BIT,ON] BIT=[2] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x0D000100)] OP=[BIT,ON] BIT=[8] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM ARRAY INIT for PCI1] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x0E030002)] +# OPCG_REG0.RUNN_MODE = 1 +CAUSE: TARGET=[REG(0x0E030002)] OP=[BIT,ON] BIT=[0] +# OPCG_REG0.OPCG_STARTS_BIST = 1 +CAUSE: TARGET=[REG(0x0E030002)] OP=[BIT,ON] BIT=[14] +# OPCG_REG0.OPCG_GO = 1 +CAUSE: TARGET=[REG(0x0E030002)] OP=[BIT,ON] BIT=[1] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x0E000100)] OP=[BIT,ON] BIT=[8] +# SRAM Abist Done +EFFECT: TARGET=[REG(0x0E000100)] OP=[BIT,ON] BIT=[0] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM SCAN0 MODULE for PCI1] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x0E030002)] +# OPCG_REG0.RUN_SCAN0 = 1 +CAUSE: TARGET=[REG(0x0E030002)] OP=[BIT,ON] BIT=[2] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x0E000100)] OP=[BIT,ON] BIT=[8] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM ARRAY INIT for PCI2] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x0F030002)] +# OPCG_REG0.RUNN_MODE = 1 +CAUSE: TARGET=[REG(0x0F030002)] OP=[BIT,ON] BIT=[0] +# OPCG_REG0.OPCG_STARTS_BIST = 1 +CAUSE: TARGET=[REG(0x0F030002)] OP=[BIT,ON] BIT=[14] +# OPCG_REG0.OPCG_GO = 1 +CAUSE: TARGET=[REG(0x0F030002)] OP=[BIT,ON] BIT=[1] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x0F000100)] OP=[BIT,ON] BIT=[8] +# SRAM Abist Done +EFFECT: TARGET=[REG(0x0F000100)] OP=[BIT,ON] BIT=[0] +} + +CAUSE_EFFECT{ +LABEL=[SEEPROM SCAN0 MODULE for PCI2] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x0F030002)] +# OPCG_REG0.RUN_SCAN0 = 1 +CAUSE: TARGET=[REG(0x0F030002)] OP=[BIT,ON] BIT=[2] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x0F000100)] OP=[BIT,ON] BIT=[8] +} + + +# ============================================================================= +# Simics action for p9_sbe_tp_arrayinit +# ============================================================================= + +CAUSE_EFFECT{ +LABEL=[SEEPROM ARRAY INIT] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x01030002)] +# OPCG_REG0.RUNN_MODE = 1 +CAUSE: TARGET=[REG(0x01030002)] OP=[BIT,ON] BIT=[0] +# OPCG_REG0.OPCG_STARTS_BIST = 1 +CAUSE: TARGET=[REG(0x01030002)] OP=[BIT,ON] BIT=[14] +# OPCG_REG0.OPCG_GO = 1 +CAUSE: TARGET=[REG(0x01030002)] OP=[BIT,ON] BIT=[1] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x01000100)] OP=[BIT,ON] BIT=[8] +# SRAM Abist Done +EFFECT: TARGET=[REG(0x01000100)] OP=[BIT,ON] BIT=[0] +} + +# This cause-effect block is also used for "p9_sbe_tp_chiplet_init2.C" +CAUSE_EFFECT{ +LABEL=[SEEPROM SCAN0 MODULE] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x01030002)] +# OPCG_REG0.RUN_SCAN0 = 1 +CAUSE: TARGET=[REG(0x01030002)] OP=[BIT,ON] BIT=[2] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x01000100)] OP=[BIT,ON] BIT=[8] +} + + +# ============================================================================= +# Simics action for p9_sbe_tp_chiplet_init3 +# ============================================================================= + +CAUSE_EFFECT{ +LABEL=[Common_Clock_Start_AllRegions] +# Watch PERV_CLK_REGION register +WATCH=[REG(0x01030006)] +# Setup all Clock Domains and Clock Types +CAUSE: TARGET=[REG(0x01030006)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0x4FFF0000 0x0000E000)] +# Clock running status for SL type should match with expected values. +EFFECT: TARGET=[REG(0x01030008)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0xF001FFFF 0xFFFFFFFF)] +# Clock running status for NSL type should match with expected values. +EFFECT: TARGET=[REG(0x01030009)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0xF001FFFF 0xFFFFFFFF]) +# Clock running status for ARY type should match with expected values. +EFFECT: TARGET=[REG(0x0103000A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0xF001FFFF 0xFFFFFFFF)] +} + + +# ============================================================================= +# Simics action for p9_sbe_npll_setup +# ============================================================================= + +CAUSE_EFFECT{ +LABEL=[SS PLL lock] +#Watch PERV_ROOT_CTRL8_SCOM register +WATCH=[REG(0x00050018)] +# PIB.ROOT_CTRL8.TP_PLL_TEST_ENABLE_DC = 0 +CAUSE: TARGET=[REG(0x00050018)] OP=[BIT,OFF] BIT=[12] +# PIB.ROOT_CTRL8.TP_SSPLL_PLL_RESET0_DC = 0 +CAUSE: TARGET=[REG(0x00050018)] OP=[BIT,OFF] BIT=[0] +# Check SS PLL lock +EFFECT: TARGET=[REG(0x010F0019)] OP=[BIT,ON] BIT=[0] +} + +CAUSE_EFFECT{ +LABEL=[CP and IO PLL lock] +# Watch PERV_ROOT_CTRL8_SCOM register +WATCH=[REG(0x00050018)] +# PIB.ROOT_CTRL8.TP_FILTPLL_PLL_RESET1_DC = 0 +CAUSE: TARGET=[REG(0x00050018)] OP=[BIT,OFF] BIT=[4] +# Check PLL_LOCK_REG register value +EFFECT: TARGET=[REG(0x010F0019)] OP=[BIT,ON] BIT=[1] +EFFECT: TARGET=[REG(0x010F0019)] OP=[BIT,ON] BIT=[2] +} + +CAUSE_EFFECT{ +LABEL=[NEST PLL LOCK] +# Watch PERV_ROOT_CTRL8_SCOM register +WATCH=[REG(0x00050018)] +# PIB.PERV_CTRL0.TP_PLLRST_DC = 0 +CAUSE: TARGET=[REG(0x00050018)] OP=[BIT,OFF] BIT=[4] +# Check NEST PLL lock +EFFECT: TARGET=[REG(0x010F0019)] OP=[BIT,ON] BIT=[3] +} + +# ============================================================================= +# Simics action for istep 4 shared modules +# ============================================================================= + +CAUSE_EFFECT{ +LABEL=[SEEPROM SCAN0 MODULE for EQ/CORE target] +# Watch PERV_OPCG_REG0 +WATCH=[REG(0x00030002)] +# OPCG_REG0.RUN_SCAN0 = 1 +CAUSE: TARGET=[REG(0x00030002)] OP=[BIT,ON] BIT=[2] +# OPCG_DONE for CPLT_STAT0 register +EFFECT: TARGET=[REG(0x00000100)] OP=[BIT,ON] BIT=[8] +} + + diff --git a/src/ppe/hwp/perv/perverrors.mk b/src/ppe/hwp/perv/perverrors.mk new file mode 100644 index 0000000..6a21918 --- /dev/null +++ b/src/ppe/hwp/perv/perverrors.mk @@ -0,0 +1,41 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ppe/hwp/perv/perverrors.mk $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# @file perverrors.mk +# +# @brief mk for including library common error files +# +# @page ChangeLogs Change Logs +# @section perverrors.mk +# +########################################################################## +# Error Files +########################################################################## + +PERV_CURR_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) + +# This variable name must not change +ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_setup_evid_errors.xml + + diff --git a/src/ppe/hwp/perv/pervfiles.mk b/src/ppe/hwp/perv/pervfiles.mk index c99113c..2112360 100644 --- a/src/ppe/hwp/perv/pervfiles.mk +++ b/src/ppe/hwp/perv/pervfiles.mk @@ -36,35 +36,40 @@ # Object Files ########################################################################## -PERV-CPP-SOURCES = p9_sbe_setup_evid.C +PERV-CPP-SOURCES =p9_sbe_arrayinit.C PERV-CPP-SOURCES +=p9_sbe_attr_setup.C -PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init1.C PERV-CPP-SOURCES +=p9_sbe_check_master.C -PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init2.C +PERV-CPP-SOURCES +=p9_sbe_chiplet_init.C +PERV-CPP-SOURCES +=p9_sbe_chiplet_pll_initf.C +PERV-CPP-SOURCES +=p9_sbe_chiplet_pll_setup.C +PERV-CPP-SOURCES +=p9_sbe_chiplet_reset.C PERV-CPP-SOURCES +=p9_sbe_enable_seeprom.C -PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init3.C +PERV-CPP-SOURCES +=p9_sbe_gptr_time_repr_initf.C PERV-CPP-SOURCES +=p9_sbe_lpc_init.C +PERV-CPP-SOURCES +=p9_sbe_nest_enable_ridi.C +PERV-CPP-SOURCES +=p9_sbe_nest_initf.C +PERV-CPP-SOURCES +=p9_sbe_nest_startclocks.C +PERV-CPP-SOURCES +=p9_sbe_npll_initf.C +PERV-CPP-SOURCES +=p9_sbe_npll_setup.C +PERV-CPP-SOURCES +=p9_sbe_select_ex.C +PERV-CPP-SOURCES +=p9_sbe_startclock_chiplets.C +PERV-CPP-SOURCES +=p9_sbe_tp_arrayinit.C +PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init1.C +PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init2.C +PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init3.C PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_reset.C -PERV-CPP-SOURCES +=p9_sbe_nest_arrayinit.C +PERV-CPP-SOURCES +=p9_sbe_tp_enable_ridi.C PERV-CPP-SOURCES +=p9_sbe_tp_gptr_time_repr_initf.C -PERV-CPP-SOURCES +=p9_sbe_nest_chiplet_init.C PERV-CPP-SOURCES +=p9_sbe_tp_initf.C -PERV-CPP-SOURCES +=p9_sbe_nest_chiplet_reset.C PERV-CPP-SOURCES +=p9_sbe_tp_ld_image.C -PERV-CPP-SOURCES +=p9_sbe_nest_gptr_time_repr_initf.C PERV-CPP-SOURCES +=p9_sbe_tp_switch_gears.C -PERV-CPP-SOURCES +=p9_sbe_nest_initf.C PERV-CPP-SOURCES +=p9_select_boot_master.C -PERV-CPP-SOURCES +=p9_sbe_nest_startclocks.C PERV-CPP-SOURCES +=p9_select_clock_mux.C -PERV-CPP-SOURCES +=p9_sbe_npll_initf.C PERV-CPP-SOURCES +=p9_set_fsi_gp_shadow.C -PERV-CPP-SOURCES +=p9_sbe_npll_setup.C PERV-CPP-SOURCES +=p9_setup_clock_term.C -PERV-CPP-SOURCES +=p9_sbe_select_ex.C PERV-CPP-SOURCES +=p9_setup_sbe_config.C -PERV-CPP-SOURCES +=p9_sbe_tp_arrayinit.C PERV-CPP-SOURCES +=p9_start_cbs.C +PERV-CPP-SOURCES +=p9_sbe_setup_evid.C PERV-C-SOURCES = PERV-S-SOURCES = |
