diff options
Diffstat (limited to 'src/ppe/hwp/perv/p9_sbe_arrayinit.C')
| -rw-r--r-- | src/ppe/hwp/perv/p9_sbe_arrayinit.C | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/src/ppe/hwp/perv/p9_sbe_arrayinit.C b/src/ppe/hwp/perv/p9_sbe_arrayinit.C new file mode 100644 index 0000000..e6ae399 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_arrayinit.C @@ -0,0 +1,53 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_arrayinit.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_arrayinit.C +/// +/// @brief array init procedure to be called with any chiplet target +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_arrayinit.H" + + + +fapi2::ReturnCode p9_sbe_arrayinit(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip) +{ + FAPI_DBG("Entering ..."); + + FAPI_DBG("Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} |
