Update new PPE HW code

Change-Id: I8e0f107fc08c857b00102fa67f35516a04ee6c78
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20731
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Tested-by: William A. Bryan <wilbryan@us.ibm.com>

193 files changed, 129154 insertions, 1397 deletions

diff --git a/src/ppe/hwp/cache/cachehcderrors.mk b/src/ppe/hwp/cache/cachehcderrors.mk
new file mode 100644
index 0000000..a12e81c
--- /dev/null
+++ b/src/ppe/hwp/cache/cachehcderrors.mk
@@ -0,0 +1,52 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ppe/hwp/cache/cachehcderrors.mk $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file cachehcderrors.mk
+#
+#  @brief mk for including cache error files
+#
+#  @page ChangeLogs Change Logs
+#  @section cachehcderrors.mk
+#
+##########################################################################
+# Error Files
+##########################################################################
+
+CACHE_CURR_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+
+# This variable name must not change
+#ERROR_XML_FILES += $(CACHE_CURR_DIR)/p9_hcd_cache_arrayinit.C
+#ERROR_XML_FILES += $(CACHE_CURR_DIR)/p9_hcd_cache_chiplet_init.C
+#ERROR_XML_FILES += $(CACHE_CURR_DIR)/p9_hcd_cache_chiplet_reset.C
+#ERROR_XML_FILES += $(CACHE_CURR_DIR)/p9_hcd_cache_dpll_setup.C
+#ERROR_XML_FILES += $(CACHE_CURR_DIR)/p9_hcd_cache_gptr_time_initf.C
+#ERROR_XML_FILES += $(CACHE_CURR_DIR)/p9_hcd_cache_initf.C
+#ERROR_XML_FILES += $(CACHE_CURR_DIR)/p9_hcd_cache_occ_runtime_scom.C
+#ERROR_XML_FILES += $(CACHE_CURR_DIR)/p9_hcd_cache_poweron.C
+#ERROR_XML_FILES += $(CACHE_CURR_DIR)/p9_hcd_cache_ras_runtime_scom.C
+#ERROR_XML_FILES += $(CACHE_CURR_DIR)/p9_hcd_cache_repair_initf.C
+#ERROR_XML_FILES += $(CACHE_CURR_DIR)/p9_hcd_cache_runinit.C
+#ERROR_XML_FILES += $(CACHE_CURR_DIR)/p9_hcd_cache_scomcust.C
+#ERROR_XML_FILES += $(CACHE_CURR_DIR)/p9_hcd_cache_scominit.C
+#ERROR_XML_FILES += $(CACHE_CURR_DIR)/p9_hcd_cache_startclocks.C
diff --git a/src/ppe/hwp/cache/doc/Makefile b/src/ppe/hwp/cache/doc/Makefile
new file mode 100755
index 0000000..db0d23d
--- /dev/null
+++ b/src/ppe/hwp/cache/doc/Makefile
@@ -0,0 +1,43 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ppe/hwp/cache/doc/Makefile $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+
+# Process the Doxygen html using the stadard CTE doxygen
+CTEPATH = /afs/awd.austin.ibm.com/projects/cte
+#DOXYGEN = /usr/bin$(CTEPATH)/tools/gsiexe/eclipz/doxygen
+DOXYGEN = doxygen
+
+.PHONY : dox
+dox: 
+	$(DOXYGEN) hcd_cache.dox >hcd_cache.dox.lst 2>&1
+
+
+#  Publish the Doxygen HTML (pending final decision on where to put it)
+
+#POKDOC = /afs/apd/func/vlsi/eclipz/common/doc/www/sys/ras/scom/p8/poreve
+
+#publish:
+#	rm -rf $(POKDOC)/doxygen
+#	cp -a html $(POKDOC)/doxygen
+
diff --git a/src/ppe/hwp/cache/doc/hcd_cache.dox b/src/ppe/hwp/cache/doc/hcd_cache.dox
new file mode 100644
index 0000000..7044114
--- /dev/null
+++ b/src/ppe/hwp/cache/doc/hcd_cache.dox
@@ -0,0 +1,1721 @@
+
+# This file describes the settings to be used by the documentation system
+# doxygen (www.doxygen.org) for a project.
+#
+# All text after a hash (#) is considered a comment and will be ignored.
+# The format is:
+#       TAG = value [value, ...]
+# For lists items can also be appended using:
+#       TAG += value [value, ...]
+# Values that contain spaces should be placed between quotes (" ").
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+
+# This tag specifies the encoding used for all characters in the config file
+# that follow. The default is UTF-8 which is also the encoding used for all
+# text before the first occurrence of this tag. Doxygen uses libiconv (or the
+# iconv built into libc) for the transcoding. See
+# http://www.gnu.org/software/libiconv for the list of possible encodings.
+
+DOXYFILE_ENCODING      = UTF-8
+
+# The PROJECT_NAME tag is a single word (or a sequence of words surrounded
+# by quotes) that should identify the project.
+
+PROJECT_NAME           = P9_Power_Management_Hcode
+
+# The PROJECT_NUMBER tag can be used to enter a project or revision number.
+# This could be handy for archiving the generated documentation or
+# if some version control system is used.
+
+PROJECT_NUMBER         =
+
+# Using the PROJECT_BRIEF tag one can provide an optional one line description
+# for a project that appears at the top of each page and should give viewer
+# a quick idea about the purpose of the project. Keep the description short.
+
+PROJECT_BRIEF          = P9 Power Management Hcode
+
+# With the PROJECT_LOGO tag one can specify an logo or icon that is
+# included in the documentation. The maximum height of the logo should not
+# exceed 55 pixels and the maximum width should not exceed 200 pixels.
+# Doxygen will copy the logo to the output directory.
+
+PROJECT_LOGO           =
+
+# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
+# base path where the generated documentation will be put.
+# If a relative path is entered, it will be relative to the location
+# where doxygen was started. If left blank the current directory will be used.
+
+OUTPUT_DIRECTORY       =
+
+# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create
+# 4096 sub-directories (in 2 levels) under the output directory of each output
+# format and will distribute the generated files over these directories.
+# Enabling this option can be useful when feeding doxygen a huge amount of
+# source files, where putting all generated files in the same directory would
+# otherwise cause performance problems for the file system.
+
+CREATE_SUBDIRS         = NO
+
+# The OUTPUT_LANGUAGE tag is used to specify the language in which all
+# documentation generated by doxygen is written. Doxygen will use this
+# information to generate all constant output in the proper language.
+# The default language is English, other supported languages are:
+# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional,
+# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German,
+# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English
+# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian,
+# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrillic, Slovak,
+# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese.
+
+OUTPUT_LANGUAGE        = English
+
+# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will
+# include brief member descriptions after the members that are listed in
+# the file and class documentation (similar to JavaDoc).
+# Set to NO to disable this.
+
+BRIEF_MEMBER_DESC      = YES
+
+# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend
+# the brief description of a member or function before the detailed description.
+# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the
+# brief descriptions will be completely suppressed.
+
+REPEAT_BRIEF           = YES
+
+# This tag implements a quasi-intelligent brief description abbreviator
+# that is used to form the text in various listings. Each string
+# in this list, if found as the leading text of the brief description, will be
+# stripped from the text and the result after processing the whole list, is
+# used as the annotated text. Otherwise, the brief description is used as-is.
+# If left blank, the following values are used ("$name" is automatically
+# replaced with the name of the entity): "The $name class" "The $name widget"
+# "The $name file" "is" "provides" "specifies" "contains"
+# "represents" "a" "an" "the"
+
+ABBREVIATE_BRIEF       =
+
+# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then
+# Doxygen will generate a detailed section even if there is only a brief
+# description.
+
+ALWAYS_DETAILED_SEC    = NO
+
+# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all
+# inherited members of a class in the documentation of that class as if those
+# members were ordinary class members. Constructors, destructors and assignment
+# operators of the base classes will not be shown.
+
+INLINE_INHERITED_MEMB  = NO
+
+# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full
+# path before files name in the file list and in the header files. If set
+# to NO the shortest path that makes the file name unique will be used.
+
+FULL_PATH_NAMES        = NO
+
+# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag
+# can be used to strip a user-defined part of the path. Stripping is
+# only done if one of the specified strings matches the left-hand part of
+# the path. The tag can be used to show relative paths in the file list.
+# If left blank the directory from which doxygen is run is used as the
+# path to strip.
+
+STRIP_FROM_PATH        =
+
+# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of
+# the path mentioned in the documentation of a class, which tells
+# the reader which header file to include in order to use a class.
+# If left blank only the name of the header file containing the class
+# definition is used. Otherwise one should specify the include paths that
+# are normally passed to the compiler using the -I flag.
+
+STRIP_FROM_INC_PATH    =
+
+# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter
+# (but less readable) file names. This can be useful if your file system
+# doesn't support long names like on DOS, Mac, or CD-ROM.
+
+SHORT_NAMES            = NO
+
+# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen
+# will interpret the first line (until the first dot) of a JavaDoc-style
+# comment as the brief description. If set to NO, the JavaDoc
+# comments will behave just like regular Qt-style comments
+# (thus requiring an explicit @brief command for a brief description.)
+
+JAVADOC_AUTOBRIEF      = NO
+
+# If the QT_AUTOBRIEF tag is set to YES then Doxygen will
+# interpret the first line (until the first dot) of a Qt-style
+# comment as the brief description. If set to NO, the comments
+# will behave just like regular Qt-style comments (thus requiring
+# an explicit \brief command for a brief description.)
+
+QT_AUTOBRIEF           = NO
+
+# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen
+# treat a multi-line C++ special comment block (i.e. a block of //! or ///
+# comments) as a brief description. This used to be the default behaviour.
+# The new default is to treat a multi-line C++ comment block as a detailed
+# description. Set this tag to YES if you prefer the old behaviour instead.
+
+MULTILINE_CPP_IS_BRIEF = YES
+
+# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented
+# member inherits the documentation from any documented member that it
+# re-implements.
+
+INHERIT_DOCS           = YES
+
+# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce
+# a new page for each member. If set to NO, the documentation of a member will
+# be part of the file/class/namespace that contains it.
+
+SEPARATE_MEMBER_PAGES  = NO
+
+# The TAB_SIZE tag can be used to set the number of spaces in a tab.
+# Doxygen uses this value to replace tabs by spaces in code fragments.
+
+TAB_SIZE               = 8
+
+# This tag can be used to specify a number of aliases that acts
+# as commands in the documentation. An alias has the form "name=value".
+# For example adding "sideeffect=\par Side Effects:\n" will allow you to
+# put the command \sideeffect (or @sideeffect) in the documentation, which
+# will result in a user-defined paragraph with heading "Side Effects:".
+# You can put \n's in the value part of an alias to insert newlines.
+
+ALIASES                 += attr="\par \b Attributes:"
+ALIASES                 += attritem{2}="\1 \2"
+
+# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C
+# sources only. Doxygen will then generate output that is more tailored for C.
+# For instance, some of the names that are used will be different. The list
+# of all members will be omitted, etc.
+
+OPTIMIZE_OUTPUT_FOR_C  = NO
+
+# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java
+# sources only. Doxygen will then generate output that is more tailored for
+# Java. For instance, namespaces will be presented as packages, qualified
+# scopes will look different, etc.
+
+OPTIMIZE_OUTPUT_JAVA   = NO
+
+# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran
+# sources only. Doxygen will then generate output that is more tailored for
+# Fortran.
+
+OPTIMIZE_FOR_FORTRAN   = NO
+
+# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL
+# sources. Doxygen will then generate output that is tailored for
+# VHDL.
+
+OPTIMIZE_OUTPUT_VHDL   = NO
+
+# Doxygen selects the parser to use depending on the extension of the files it
+# parses. With this tag you can assign which parser to use for a given extension.
+# Doxygen has a built-in mapping, but you can override or extend it using this
+# tag. The format is ext=language, where ext is a file extension, and language
+# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C,
+# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make
+# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C
+# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions
+# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen.
+
+EXTENSION_MAPPING      =
+
+# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want
+# to include (a tag file for) the STL sources as input, then you should
+# set this tag to YES in order to let doxygen match functions declarations and
+# definitions whose arguments contain STL classes (e.g. func(std::string); v.s.
+# func(std::string) {}). This also makes the inheritance and collaboration
+# diagrams that involve STL classes more complete and accurate.
+
+BUILTIN_STL_SUPPORT    = NO
+
+# If you use Microsoft's C++/CLI language, you should set this option to YES to
+# enable parsing support.
+
+CPP_CLI_SUPPORT        = NO
+
+# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only.
+# Doxygen will parse them like normal C++ but will assume all classes use public
+# instead of private inheritance when no explicit protection keyword is present.
+
+SIP_SUPPORT            = NO
+
+# For Microsoft's IDL there are propget and propput attributes to indicate getter
+# and setter methods for a property. Setting this option to YES (the default)
+# will make doxygen replace the get and set methods by a property in the
+# documentation. This will only work if the methods are indeed getting or
+# setting a simple type. If this is not the case, or you want to show the
+# methods anyway, you should set this option to NO.
+
+IDL_PROPERTY_SUPPORT   = YES
+
+# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC
+# tag is set to YES, then doxygen will reuse the documentation of the first
+# member in the group (if any) for the other members of the group. By default
+# all members of a group must be documented explicitly.
+
+DISTRIBUTE_GROUP_DOC   = NO
+
+# Set the SUBGROUPING tag to YES (the default) to allow class member groups of
+# the same type (for instance a group of public functions) to be put as a
+# subgroup of that type (e.g. under the Public Functions section). Set it to
+# NO to prevent subgrouping. Alternatively, this can be done per class using
+# the \nosubgrouping command.
+
+SUBGROUPING            = YES
+
+# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and
+# unions are shown inside the group in which they are included (e.g. using
+# @ingroup) instead of on a separate page (for HTML and Man pages) or
+# section (for LaTeX and RTF).
+
+INLINE_GROUPED_CLASSES = NO
+
+# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum
+# is documented as struct, union, or enum with the name of the typedef. So
+# typedef struct TypeS {} TypeT, will appear in the documentation as a struct
+# with name TypeT. When disabled the typedef will appear as a member of a file,
+# namespace, or class. And the struct will be named TypeS. This can typically
+# be useful for C code in case the coding convention dictates that all compound
+# types are typedef'ed and only the typedef is referenced, never the tag name.
+
+TYPEDEF_HIDES_STRUCT   = NO
+
+# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to
+# determine which symbols to keep in memory and which to flush to disk.
+# When the cache is full, less often used symbols will be written to disk.
+# For small to medium size projects (<1000 input files) the default value is
+# probably good enough. For larger projects a too small cache size can cause
+# doxygen to be busy swapping symbols to and from disk most of the time
+# causing a significant performance penalty.
+# If the system has enough physical memory increasing the cache will improve the
+# performance by keeping more symbols in memory. Note that the value works on
+# a logarithmic scale so increasing the size by one will roughly double the
+# memory usage. The cache size is given by this formula:
+# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0,
+# corresponding to a cache size of 2^16 = 65536 symbols
+
+SYMBOL_CACHE_SIZE      = 0
+
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+
+# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in
+# documentation are documented, even if no documentation was available.
+# Private class members and static file members will be hidden unless
+# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES
+### TODO ###
+EXTRACT_ALL            = YES
+
+# If the EXTRACT_PRIVATE tag is set to YES all private members of a class
+# will be included in the documentation.
+
+EXTRACT_PRIVATE        = NO
+
+# If the EXTRACT_STATIC tag is set to YES all static members of a file
+# will be included in the documentation.
+
+EXTRACT_STATIC         = NO
+
+# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs)
+# defined locally in source files will be included in the documentation.
+# If set to NO only classes defined in header files are included.
+
+EXTRACT_LOCAL_CLASSES  = YES
+
+# This flag is only useful for Objective-C code. When set to YES local
+# methods, which are defined in the implementation section but not in
+# the interface are included in the documentation.
+# If set to NO (the default) only methods in the interface are included.
+
+EXTRACT_LOCAL_METHODS  = NO
+
+# If this flag is set to YES, the members of anonymous namespaces will be
+# extracted and appear in the documentation as a namespace called
+# 'anonymous_namespace{file}', where file will be replaced with the base
+# name of the file that contains the anonymous namespace. By default
+# anonymous namespaces are hidden.
+
+EXTRACT_ANON_NSPACES   = NO
+
+# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all
+# undocumented members of documented classes, files or namespaces.
+# If set to NO (the default) these members will be included in the
+# various overviews, but no documentation section is generated.
+# This option has no effect if EXTRACT_ALL is enabled.
+
+HIDE_UNDOC_MEMBERS     = NO
+
+# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all
+# undocumented classes that are normally visible in the class hierarchy.
+# If set to NO (the default) these classes will be included in the various
+# overviews. This option has no effect if EXTRACT_ALL is enabled.
+
+HIDE_UNDOC_CLASSES     = NO
+
+# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all
+# friend (class|struct|union) declarations.
+# If set to NO (the default) these declarations will be included in the
+# documentation.
+
+HIDE_FRIEND_COMPOUNDS  = NO
+
+# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any
+# documentation blocks found inside the body of a function.
+# If set to NO (the default) these blocks will be appended to the
+# function's detailed documentation block.
+
+HIDE_IN_BODY_DOCS      = NO
+
+# The INTERNAL_DOCS tag determines if documentation
+# that is typed after a \internal command is included. If the tag is set
+# to NO (the default) then the documentation will be excluded.
+# Set it to YES to include the internal documentation.
+
+INTERNAL_DOCS          = NO
+
+# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate
+# file names in lower-case letters. If set to YES upper-case letters are also
+# allowed. This is useful if you have classes or files whose names only differ
+# in case and if your file system supports case sensitive file names. Windows
+# and Mac users are advised to set this option to NO.
+
+CASE_SENSE_NAMES       = YES
+
+# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen
+# will show members with their full class and namespace scopes in the
+# documentation. If set to YES the scope will be hidden.
+
+HIDE_SCOPE_NAMES       = NO
+
+# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen
+# will put a list of the files that are included by a file in the documentation
+# of that file.
+
+SHOW_INCLUDE_FILES     = YES
+
+# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen
+# will list include files with double quotes in the documentation
+# rather than with sharp brackets.
+
+FORCE_LOCAL_INCLUDES   = NO
+
+# If the INLINE_INFO tag is set to YES (the default) then a tag [inline]
+# is inserted in the documentation for inline members.
+
+INLINE_INFO            = YES
+
+# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen
+# will sort the (detailed) documentation of file and class members
+# alphabetically by member name. If set to NO the members will appear in
+# declaration order.
+
+SORT_MEMBER_DOCS       = YES
+
+# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the
+# brief documentation of file, namespace and class members alphabetically
+# by member name. If set to NO (the default) the members will appear in
+# declaration order.
+
+SORT_BRIEF_DOCS        = NO
+
+# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen
+# will sort the (brief and detailed) documentation of class members so that
+# constructors and destructors are listed first. If set to NO (the default)
+# the constructors will appear in the respective orders defined by
+# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS.
+# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO
+# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO.
+
+SORT_MEMBERS_CTORS_1ST = NO
+
+# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the
+# hierarchy of group names into alphabetical order. If set to NO (the default)
+# the group names will appear in their defined order.
+
+SORT_GROUP_NAMES       = NO
+
+# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be
+# sorted by fully-qualified names, including namespaces. If set to
+# NO (the default), the class list will be sorted only by class name,
+# not including the namespace part.
+# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.
+# Note: This option applies only to the class list, not to the
+# alphabetical list.
+
+SORT_BY_SCOPE_NAME     = NO
+
+# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to
+# do proper type resolution of all parameters of a function it will reject a
+# match between the prototype and the implementation of a member function even
+# if there is only one candidate or it is obvious which candidate to choose
+# by doing a simple string match. By disabling STRICT_PROTO_MATCHING doxygen
+# will still accept a match between prototype and implementation in such cases.
+
+STRICT_PROTO_MATCHING  = NO
+
+# The GENERATE_TODOLIST tag can be used to enable (YES) or
+# disable (NO) the todo list. This list is created by putting \todo
+# commands in the documentation.
+
+GENERATE_TODOLIST      = YES
+
+# The GENERATE_TESTLIST tag can be used to enable (YES) or
+# disable (NO) the test list. This list is created by putting \test
+# commands in the documentation.
+
+GENERATE_TESTLIST      = YES
+
+# The GENERATE_BUGLIST tag can be used to enable (YES) or
+# disable (NO) the bug list. This list is created by putting \bug
+# commands in the documentation.
+
+GENERATE_BUGLIST       = YES
+
+# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or
+# disable (NO) the deprecated list. This list is created by putting
+# \deprecated commands in the documentation.
+
+GENERATE_DEPRECATEDLIST= YES
+
+# The ENABLED_SECTIONS tag can be used to enable conditional
+# documentation sections, marked by \if sectionname ... \endif.
+
+ENABLED_SECTIONS       =
+
+# The MAX_INITIALIZER_LINES tag determines the maximum number of lines
+# the initial value of a variable or macro consists of for it to appear in
+# the documentation. If the initializer consists of more lines than specified
+# here it will be hidden. Use a value of 0 to hide initializers completely.
+# The appearance of the initializer of individual variables and macros in the
+# documentation can be controlled using \showinitializer or \hideinitializer
+# command in the documentation regardless of this setting.
+
+MAX_INITIALIZER_LINES  = 30
+
+# Set the SHOW_USED_FILES tag to NO to disable the list of files generated
+# at the bottom of the documentation of classes and structs. If set to YES the
+# list will mention the files that were used to generate the documentation.
+
+SHOW_USED_FILES        = YES
+
+# If the sources in your project are distributed over multiple directories
+# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy
+# in the documentation. The default is NO.
+
+SHOW_DIRECTORIES       = NO
+
+# Set the SHOW_FILES tag to NO to disable the generation of the Files page.
+# This will remove the Files entry from the Quick Index and from the
+# Folder Tree View (if specified). The default is YES.
+
+SHOW_FILES             = YES
+
+# Set the SHOW_NAMESPACES tag to NO to disable the generation of the
+# Namespaces page.
+# This will remove the Namespaces entry from the Quick Index
+# and from the Folder Tree View (if specified). The default is YES.
+
+SHOW_NAMESPACES        = YES
+
+# The FILE_VERSION_FILTER tag can be used to specify a program or script that
+# doxygen should invoke to get the current version for each file (typically from
+# the version control system). Doxygen will invoke the program by executing (via
+# popen()) the command <command> <input-file>, where <command> is the value of
+# the FILE_VERSION_FILTER tag, and <input-file> is the name of an input file
+# provided by doxygen. Whatever the program writes to standard output
+# is used as the file version. See the manual for examples.
+
+FILE_VERSION_FILTER    =
+
+# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed
+# by doxygen. The layout file controls the global structure of the generated
+# output files in an output format independent way. The create the layout file
+# that represents doxygen's defaults, run doxygen with the -l option.
+# You can optionally specify a file name after the option, if omitted
+# DoxygenLayout.xml will be used as the name of the layout file.
+
+LAYOUT_FILE            =
+
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+
+# The QUIET tag can be used to turn on/off the messages that are generated
+# by doxygen. Possible values are YES and NO. If left blank NO is used.
+
+QUIET                  = NO
+
+# The WARNINGS tag can be used to turn on/off the warning messages that are
+# generated by doxygen. Possible values are YES and NO. If left blank
+# NO is used.
+
+WARNINGS               = YES
+
+# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings
+# for undocumented members. If EXTRACT_ALL is set to YES then this flag will
+# automatically be disabled.
+
+WARN_IF_UNDOCUMENTED   = YES
+
+# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for
+# potential errors in the documentation, such as not documenting some
+# parameters in a documented function, or documenting parameters that
+# don't exist or using markup commands wrongly.
+
+WARN_IF_DOC_ERROR      = YES
+
+# The WARN_NO_PARAMDOC option can be enabled to get warnings for
+# functions that are documented, but have no documentation for their parameters
+# or return value. If set to NO (the default) doxygen will only warn about
+# wrong or incomplete parameter documentation, but not about the absence of
+# documentation.
+
+WARN_NO_PARAMDOC       = NO
+
+# The WARN_FORMAT tag determines the format of the warning messages that
+# doxygen can produce. The string should contain the $file, $line, and $text
+# tags, which will be replaced by the file and line number from which the
+# warning originated and the warning text. Optionally the format may contain
+# $version, which will be replaced by the version of the file (if it could
+# be obtained via FILE_VERSION_FILTER)
+
+WARN_FORMAT            = "$file:$line: $text"
+
+# The WARN_LOGFILE tag can be used to specify a file to which warning
+# and error messages should be written. If left blank the output is written
+# to stderr.
+
+WARN_LOGFILE           =
+
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+
+# The INPUT tag can be used to specify the files and/or directories that contain
+# documented source files. You may enter file names like "myfile.cpp" or
+# directories like "/usr/src/myproject". Separate the files or directories
+# with spaces.
+
+INPUT                  = "../"
+                          
+
+# This tag can be used to specify the character encoding of the source files
+# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is
+# also the default input encoding. Doxygen uses libiconv (or the iconv built
+# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for
+# the list of possible encodings.
+
+INPUT_ENCODING         = UTF-8
+
+# If the value of the INPUT tag contains directories, you can use the
+# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
+# and *.h) to filter out the source-files in the directories. If left
+# blank the following patterns are tested:
+# *.c *.cc *.cxx *.cpp *.c++ *.d *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh
+# *.hxx *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.dox *.py
+# *.f90 *.f *.for *.vhd *.vhdl
+
+FILE_PATTERNS          =  *hcd*.dox *hcd*.C *hcd*.H *.S
+                      
+                         
+                         
+
+# The RECURSIVE tag can be used to turn specify whether or not subdirectories
+# should be searched for input files as well. Possible values are YES and NO.
+# If left blank NO is used.
+
+RECURSIVE              = NO
+
+# The EXCLUDE tag can be used to specify files and/or directories that should
+# excluded from the INPUT source files. This way you can easily exclude a
+# subdirectory from a directory tree whose root is specified with the INPUT tag.
+
+EXCLUDE                =
+
+# The EXCLUDE_SYMLINKS tag can be used select whether or not files or
+# directories that are symbolic links (a Unix file system feature) are excluded
+# from the input.
+
+EXCLUDE_SYMLINKS       = NO
+
+# If the value of the INPUT tag contains directories, you can use the
+# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude
+# certain files from those directories. Note that the wildcards are matched
+# against the file with absolute path, so to exclude all test directories
+# for example use the pattern */test/*
+
+EXCLUDE_PATTERNS       =
+
+# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names
+# (namespaces, classes, functions, etc.) that should be excluded from the
+# output. The symbol name can be a fully qualified name, a word, or if the
+# wildcard * is used, a substring. Examples: ANamespace, AClass,
+# AClass::ANamespace, ANamespace::*Test
+
+EXCLUDE_SYMBOLS        =
+
+# The EXAMPLE_PATH tag can be used to specify one or more files or
+# directories that contain example code fragments that are included (see
+# the \include command).
+
+EXAMPLE_PATH           =
+
+# If the value of the EXAMPLE_PATH tag contains directories, you can use the
+# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
+# and *.h) to filter out the source-files in the directories. If left
+# blank all files are included.
+
+EXAMPLE_PATTERNS       =
+
+# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be
+# searched for input files to be used with the \include or \dontinclude
+# commands irrespective of the value of the RECURSIVE tag.
+# Possible values are YES and NO. If left blank NO is used.
+
+EXAMPLE_RECURSIVE      = NO
+
+# The IMAGE_PATH tag can be used to specify one or more files or
+# directories that contain image that are included in the documentation (see
+# the \image command).
+
+IMAGE_PATH             =
+
+# The INPUT_FILTER tag can be used to specify a program that doxygen should
+# invoke to filter for each input file. Doxygen will invoke the filter program
+# by executing (via popen()) the command <filter> <input-file>, where <filter>
+# is the value of the INPUT_FILTER tag, and <input-file> is the name of an
+# input file. Doxygen will then use the output that the filter program writes
+# to standard output.
+# If FILTER_PATTERNS is specified, this tag will be
+# ignored.
+
+INPUT_FILTER           =
+
+# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern
+# basis.
+# Doxygen will compare the file name with each pattern and apply the
+# filter if there is a match.
+# The filters are a list of the form:
+# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further
+# info on how filters are used. If FILTER_PATTERNS is empty or if
+# non of the patterns match the file name, INPUT_FILTER is applied.
+
+FILTER_PATTERNS        =
+
+# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using
+# INPUT_FILTER) will be used to filter the input files when producing source
+# files to browse (i.e. when SOURCE_BROWSER is set to YES).
+
+FILTER_SOURCE_FILES    = NO
+
+# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file
+# pattern. A pattern will override the setting for FILTER_PATTERN (if any)
+# and it is also possible to disable source filtering for a specific pattern
+# using *.ext= (so without naming a filter). This option only has effect when
+# FILTER_SOURCE_FILES is enabled.
+
+FILTER_SOURCE_PATTERNS =
+
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+
+# If the SOURCE_BROWSER tag is set to YES then a list of source files will
+# be generated. Documented entities will be cross-referenced with these sources.
+# Note: To get rid of all source code in the generated output, make sure also
+# VERBATIM_HEADERS is set to NO.
+
+SOURCE_BROWSER         = YES
+
+# Setting the INLINE_SOURCES tag to YES will include the body
+# of functions and classes directly in the documentation.
+
+INLINE_SOURCES         = NO
+
+# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct
+# doxygen to hide any special comment blocks from generated source code
+# fragments. Normal C and C++ comments will always remain visible.
+
+STRIP_CODE_COMMENTS    = YES
+
+# If the REFERENCED_BY_RELATION tag is set to YES
+# then for each documented function all documented
+# functions referencing it will be listed.
+
+REFERENCED_BY_RELATION = NO
+
+# If the REFERENCES_RELATION tag is set to YES
+# then for each documented function all documented entities
+# called/used by that function will be listed.
+
+REFERENCES_RELATION    = NO
+
+# If the REFERENCES_LINK_SOURCE tag is set to YES (the default)
+# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from
+# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will
+# link to the source code.
+# Otherwise they will link to the documentation.
+
+REFERENCES_LINK_SOURCE = YES
+
+# If the USE_HTAGS tag is set to YES then the references to source code
+# will point to the HTML generated by the htags(1) tool instead of doxygen
+# built-in source browser. The htags tool is part of GNU's global source
+# tagging system (see http://www.gnu.org/software/global/global.html). You
+# will need version 4.8.6 or higher.
+
+USE_HTAGS              = NO
+
+# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen
+# will generate a verbatim copy of the header file for each class for
+# which an include is specified. Set to NO to disable this.
+
+VERBATIM_HEADERS       = YES
+
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+
+# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index
+# of all compounds will be generated. Enable this if the project
+# contains a lot of classes, structs, unions or interfaces.
+
+ALPHABETICAL_INDEX     = NO
+
+# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then
+# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns
+# in which this list will be split (can be a number in the range [1..20])
+
+COLS_IN_ALPHA_INDEX    = 5
+
+# In case all classes in a project start with a common prefix, all
+# classes will be put under the same header in the alphabetical index.
+# The IGNORE_PREFIX tag can be used to specify one or more prefixes that
+# should be ignored while generating the index headers.
+
+IGNORE_PREFIX          =
+
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_HTML tag is set to YES (the default) Doxygen will
+# generate HTML output.
+
+GENERATE_HTML          = YES
+
+# The HTML_OUTPUT tag is used to specify where the HTML docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `html' will be used as the default path.
+
+HTML_OUTPUT            = html
+
+# The HTML_FILE_EXTENSION tag can be used to specify the file extension for
+# each generated HTML page (for example: .htm,.php,.asp). If it is left blank
+# doxygen will generate files with .html extension.
+
+HTML_FILE_EXTENSION    = .html
+
+# The HTML_HEADER tag can be used to specify a personal HTML header for
+# each generated HTML page. If it is left blank doxygen will generate a
+# standard header. Note that when using a custom header you are responsible
+# for the proper inclusion of any scripts and style sheets that doxygen
+# needs, which is dependent on the configuration options used.
+# It is adviced to generate a default header using "doxygen -w html
+# header.html footer.html stylesheet.css YourConfigFile" and then modify
+# that header. Note that the header is subject to change so you typically
+# have to redo this when upgrading to a newer version of doxygen or when changing the value of configuration settings such as GENERATE_TREEVIEW!
+
+HTML_HEADER            =
+
+# The HTML_FOOTER tag can be used to specify a personal HTML footer for
+# each generated HTML page. If it is left blank doxygen will generate a
+# standard footer.
+
+HTML_FOOTER            =
+
+# The HTML_STYLESHEET tag can be used to specify a user-defined cascading
+# style sheet that is used by each HTML page. It can be used to
+# fine-tune the look of the HTML output. If the tag is left blank doxygen
+# will generate a default style sheet. Note that doxygen will try to copy
+# the style sheet file to the HTML output directory, so don't put your own
+# stylesheet in the HTML output directory as well, or it will be erased!
+
+HTML_STYLESHEET        =
+
+# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or
+# other source files which should be copied to the HTML output directory. Note
+# that these files will be copied to the base HTML output directory. Use the
+# $relpath$ marker in the HTML_HEADER and/or HTML_FOOTER files to load these
+# files. In the HTML_STYLESHEET file, use the file name only. Also note that
+# the files will be copied as-is; there are no commands or markers available.
+
+HTML_EXTRA_FILES       =
+
+# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output.
+# Doxygen will adjust the colors in the stylesheet and background images
+# according to this color. Hue is specified as an angle on a colorwheel,
+# see http://en.wikipedia.org/wiki/Hue for more information.
+# For instance the value 0 represents red, 60 is yellow, 120 is green,
+# 180 is cyan, 240 is blue, 300 purple, and 360 is red again.
+# The allowed range is 0 to 359.
+
+HTML_COLORSTYLE_HUE    = 220
+
+# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of
+# the colors in the HTML output. For a value of 0 the output will use
+# grayscales only. A value of 255 will produce the most vivid colors.
+
+HTML_COLORSTYLE_SAT    = 100
+
+# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to
+# the luminance component of the colors in the HTML output. Values below
+# 100 gradually make the output lighter, whereas values above 100 make
+# the output darker. The value divided by 100 is the actual gamma applied,
+# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2,
+# and 100 does not change the gamma.
+
+HTML_COLORSTYLE_GAMMA  = 80
+
+# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML
+# page will contain the date and time when the page was generated. Setting
+# this to NO can help when comparing the output of multiple runs.
+
+HTML_TIMESTAMP         = YES
+
+# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes,
+# files or namespaces will be aligned in HTML using tables. If set to
+# NO a bullet list will be used.
+
+HTML_ALIGN_MEMBERS     = YES
+
+# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML
+# documentation will contain sections that can be hidden and shown after the
+# page has loaded. For this to work a browser that supports
+# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox
+# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari).
+
+HTML_DYNAMIC_SECTIONS  = NO
+
+# If the GENERATE_DOCSET tag is set to YES, additional index files
+# will be generated that can be used as input for Apple's Xcode 3
+# integrated development environment, introduced with OSX 10.5 (Leopard).
+# To create a documentation set, doxygen will generate a Makefile in the
+# HTML output directory. Running make will produce the docset in that
+# directory and running "make install" will install the docset in
+# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find
+# it at startup.
+# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html
+# for more information.
+
+GENERATE_DOCSET        = NO
+
+# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the
+# feed. A documentation feed provides an umbrella under which multiple
+# documentation sets from a single provider (such as a company or product suite)
+# can be grouped.
+
+DOCSET_FEEDNAME        = "Doxygen generated docs"
+
+# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that
+# should uniquely identify the documentation set bundle. This should be a
+# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen
+# will append .docset to the name.
+
+DOCSET_BUNDLE_ID       = org.doxygen.Project
+
+# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify
+# the documentation publisher. This should be a reverse domain-name style
+# string, e.g. com.mycompany.MyDocSet.documentation.
+
+DOCSET_PUBLISHER_ID    = org.doxygen.Publisher
+
+# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher.
+
+DOCSET_PUBLISHER_NAME  = Publisher
+
+# If the GENERATE_HTMLHELP tag is set to YES, additional index files
+# will be generated that can be used as input for tools like the
+# Microsoft HTML help workshop to generate a compiled HTML help file (.chm)
+# of the generated HTML documentation.
+
+GENERATE_HTMLHELP      = NO
+
+# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can
+# be used to specify the file name of the resulting .chm file. You
+# can add a path in front of the file if the result should not be
+# written to the html output directory.
+
+CHM_FILE               =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can
+# be used to specify the location (absolute path including file name) of
+# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run
+# the HTML help compiler on the generated index.hhp.
+
+HHC_LOCATION           =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag
+# controls if a separate .chi index file is generated (YES) or that
+# it should be included in the master .chm file (NO).
+
+GENERATE_CHI           = NO
+
+# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING
+# is used to encode HtmlHelp index (hhk), content (hhc) and project file
+# content.
+
+CHM_INDEX_ENCODING     =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag
+# controls whether a binary table of contents is generated (YES) or a
+# normal table of contents (NO) in the .chm file.
+
+BINARY_TOC             = NO
+
+# The TOC_EXPAND flag can be set to YES to add extra items for group members
+# to the contents of the HTML help documentation and to the tree view.
+
+TOC_EXPAND             = NO
+
+# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and
+# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated
+# that can be used as input for Qt's qhelpgenerator to generate a
+# Qt Compressed Help (.qch) of the generated HTML documentation.
+
+GENERATE_QHP           = NO
+
+# If the QHG_LOCATION tag is specified, the QCH_FILE tag can
+# be used to specify the file name of the resulting .qch file.
+# The path specified is relative to the HTML output folder.
+
+QCH_FILE               =
+
+# The QHP_NAMESPACE tag specifies the namespace to use when generating
+# Qt Help Project output. For more information please see
+# http://doc.trolltech.com/qthelpproject.html#namespace
+
+QHP_NAMESPACE          = org.doxygen.Project
+
+# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating
+# Qt Help Project output. For more information please see
+# http://doc.trolltech.com/qthelpproject.html#virtual-folders
+
+QHP_VIRTUAL_FOLDER     = doc
+
+# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to
+# add. For more information please see
+# http://doc.trolltech.com/qthelpproject.html#custom-filters
+
+QHP_CUST_FILTER_NAME   =
+
+# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the
+# custom filter to add. For more information please see
+# <a href="http://doc.trolltech.com/qthelpproject.html#custom-filters">
+# Qt Help Project / Custom Filters</a>.
+
+QHP_CUST_FILTER_ATTRS  =
+
+# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this
+# project's
+# filter section matches.
+# <a href="http://doc.trolltech.com/qthelpproject.html#filter-attributes">
+# Qt Help Project / Filter Attributes</a>.
+
+QHP_SECT_FILTER_ATTRS  =
+
+# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can
+# be used to specify the location of Qt's qhelpgenerator.
+# If non-empty doxygen will try to run qhelpgenerator on the generated
+# .qhp file.
+
+QHG_LOCATION           =
+
+# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files
+#  will be generated, which together with the HTML files, form an Eclipse help
+# plugin. To install this plugin and make it available under the help contents
+# menu in Eclipse, the contents of the directory containing the HTML and XML
+# files needs to be copied into the plugins directory of eclipse. The name of
+# the directory within the plugins directory should be the same as
+# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before
+# the help appears.
+
+GENERATE_ECLIPSEHELP   = NO
+
+# A unique identifier for the eclipse help plugin. When installing the plugin
+# the directory name containing the HTML and XML files should also have
+# this name.
+
+ECLIPSE_DOC_ID         = org.doxygen.Project
+
+# The DISABLE_INDEX tag can be used to turn on/off the condensed index at
+# top of each HTML page. The value NO (the default) enables the index and
+# the value YES disables it.
+
+DISABLE_INDEX          = NO
+
+# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values
+# (range [0,1..20]) that doxygen will group on one line in the generated HTML
+# documentation. Note that a value of 0 will completely suppress the enum
+# values from appearing in the overview section.
+
+ENUM_VALUES_PER_LINE   = 4
+
+# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index
+# structure should be generated to display hierarchical information.
+# If the tag value is set to YES, a side panel will be generated
+# containing a tree-like index structure (just like the one that
+# is generated for HTML Help). For this to work a browser that supports
+# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser).
+# Windows users are probably better off using the HTML help feature.
+
+GENERATE_TREEVIEW      = NO
+
+# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories,
+# and Class Hierarchy pages using a tree view instead of an ordered list.
+
+USE_INLINE_TREES       = NO
+
+# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be
+# used to set the initial width (in pixels) of the frame in which the tree
+# is shown.
+
+TREEVIEW_WIDTH         = 250
+
+# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open
+# links to external symbols imported via tag files in a separate window.
+
+EXT_LINKS_IN_WINDOW    = NO
+
+# Use this tag to change the font size of Latex formulas included
+# as images in the HTML documentation. The default is 10. Note that
+# when you change the font size after a successful doxygen run you need
+# to manually remove any form_*.png images from the HTML output directory
+# to force them to be regenerated.
+
+FORMULA_FONTSIZE       = 10
+
+# Use the FORMULA_TRANPARENT tag to determine whether or not the images
+# generated for formulas are transparent PNGs. Transparent PNGs are
+# not supported properly for IE 6.0, but are supported on all modern browsers.
+# Note that when changing this option you need to delete any form_*.png files
+# in the HTML output before the changes have effect.
+
+FORMULA_TRANSPARENT    = YES
+
+# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax
+# (see http://www.mathjax.org) which uses client side Javascript for the
+# rendering instead of using prerendered bitmaps. Use this if you do not
+# have LaTeX installed or if you want to formulas look prettier in the HTML
+# output. When enabled you also need to install MathJax separately and
+# configure the path to it using the MATHJAX_RELPATH option.
+
+USE_MATHJAX            = NO
+
+# When MathJax is enabled you need to specify the location relative to the
+# HTML output directory using the MATHJAX_RELPATH option. The destination
+# directory should contain the MathJax.js script. For instance, if the mathjax
+# directory is located at the same level as the HTML output directory, then
+# MATHJAX_RELPATH should be ../mathjax. The default value points to the
+# mathjax.org site, so you can quickly see the result without installing
+# MathJax, but it is strongly recommended to install a local copy of MathJax
+# before deployment.
+
+MATHJAX_RELPATH        = http://www.mathjax.org/mathjax
+
+# When the SEARCHENGINE tag is enabled doxygen will generate a search box
+# for the HTML output. The underlying search engine uses javascript
+# and DHTML and should work on any modern browser. Note that when using
+# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets
+# (GENERATE_DOCSET) there is already a search function so this one should
+# typically be disabled. For large projects the javascript based search engine
+# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution.
+
+SEARCHENGINE           = YES
+
+# When the SERVER_BASED_SEARCH tag is enabled the search engine will be
+# implemented using a PHP enabled web server instead of at the web client
+# using Javascript. Doxygen will generate the search PHP script and index
+# file to put on the web server. The advantage of the server
+# based approach is that it scales better to large projects and allows
+# full text search. The disadvantages are that it is more difficult to setup
+# and does not have live searching capabilities.
+
+SERVER_BASED_SEARCH    = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will
+# generate Latex output.
+
+GENERATE_LATEX         = YES
+
+# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `latex' will be used as the default path.
+
+LATEX_OUTPUT           = latex
+
+# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be
+# invoked. If left blank `latex' will be used as the default command name.
+# Note that when enabling USE_PDFLATEX this option is only used for
+# generating bitmaps for formulas in the HTML output, but not in the
+# Makefile that is written to the output directory.
+
+LATEX_CMD_NAME         = latex
+
+# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to
+# generate index for LaTeX. If left blank `makeindex' will be used as the
+# default command name.
+
+MAKEINDEX_CMD_NAME     = makeindex
+
+# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact
+# LaTeX documents. This may be useful for small projects and may help to
+# save some trees in general.
+
+COMPACT_LATEX          = NO
+
+# The PAPER_TYPE tag can be used to set the paper type that is used
+# by the printer. Possible values are: a4, letter, legal and
+# executive. If left blank a4wide will be used.
+
+PAPER_TYPE             = a4wide
+
+# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX
+# packages that should be included in the LaTeX output.
+
+EXTRA_PACKAGES         =
+
+# The LATEX_HEADER tag can be used to specify a personal LaTeX header for
+# the generated latex document. The header should contain everything until
+# the first chapter. If it is left blank doxygen will generate a
+# standard header. Notice: only use this tag if you know what you are doing!
+
+LATEX_HEADER           =
+
+# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for
+# the generated latex document. The footer should contain everything after
+# the last chapter. If it is left blank doxygen will generate a
+# standard footer. Notice: only use this tag if you know what you are doing!
+
+LATEX_FOOTER           =
+
+# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated
+# is prepared for conversion to pdf (using ps2pdf). The pdf file will
+# contain links (just like the HTML output) instead of page references
+# This makes the output suitable for online browsing using a pdf viewer.
+
+PDF_HYPERLINKS         = YES
+
+# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of
+# plain latex in the generated Makefile. Set this option to YES to get a
+# higher quality PDF documentation.
+
+USE_PDFLATEX           = YES
+
+# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode.
+# command to the generated LaTeX files. This will instruct LaTeX to keep
+# running if errors occur, instead of asking the user for help.
+# This option is also used when generating formulas in HTML.
+
+LATEX_BATCHMODE        = NO
+
+# If LATEX_HIDE_INDICES is set to YES then doxygen will not
+# include the index chapters (such as File Index, Compound Index, etc.)
+# in the output.
+
+LATEX_HIDE_INDICES     = NO
+
+# If LATEX_SOURCE_CODE is set to YES then doxygen will include
+# source code with syntax highlighting in the LaTeX output.
+# Note that which sources are shown also depends on other settings
+# such as SOURCE_BROWSER.
+
+LATEX_SOURCE_CODE      = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output
+# The RTF output is optimized for Word 97 and may not look very pretty with
+# other RTF readers or editors.
+
+GENERATE_RTF           = NO
+
+# The RTF_OUTPUT tag is used to specify where the RTF docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `rtf' will be used as the default path.
+
+RTF_OUTPUT             = rtf
+
+# If the COMPACT_RTF tag is set to YES Doxygen generates more compact
+# RTF documents. This may be useful for small projects and may help to
+# save some trees in general.
+
+COMPACT_RTF            = NO
+
+# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated
+# will contain hyperlink fields. The RTF file will
+# contain links (just like the HTML output) instead of page references.
+# This makes the output suitable for online browsing using WORD or other
+# programs which support those fields.
+# Note: wordpad (write) and others do not support links.
+
+RTF_HYPERLINKS         = NO
+
+# Load stylesheet definitions from file. Syntax is similar to doxygen's
+# config file, i.e. a series of assignments. You only have to provide
+# replacements, missing definitions are set to their default value.
+
+RTF_STYLESHEET_FILE    =
+
+# Set optional variables used in the generation of an rtf document.
+# Syntax is similar to doxygen's config file.
+
+RTF_EXTENSIONS_FILE    =
+
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_MAN tag is set to YES (the default) Doxygen will
+# generate man pages
+
+GENERATE_MAN           = NO
+
+# The MAN_OUTPUT tag is used to specify where the man pages will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `man' will be used as the default path.
+
+MAN_OUTPUT             = man
+
+# The MAN_EXTENSION tag determines the extension that is added to
+# the generated man pages (default is the subroutine's section .3)
+
+MAN_EXTENSION          = .3
+
+# If the MAN_LINKS tag is set to YES and Doxygen generates man output,
+# then it will generate one additional man file for each entity
+# documented in the real man page(s). These additional files
+# only source the real man page, but without them the man command
+# would be unable to find the correct page. The default is NO.
+
+MAN_LINKS              = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_XML tag is set to YES Doxygen will
+# generate an XML file that captures the structure of
+# the code including all documentation.
+
+GENERATE_XML           = NO
+
+# The XML_OUTPUT tag is used to specify where the XML pages will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `xml' will be used as the default path.
+
+XML_OUTPUT             = xml
+
+# The XML_SCHEMA tag can be used to specify an XML schema,
+# which can be used by a validating XML parser to check the
+# syntax of the XML files.
+
+XML_SCHEMA             =
+
+# The XML_DTD tag can be used to specify an XML DTD,
+# which can be used by a validating XML parser to check the
+# syntax of the XML files.
+
+XML_DTD                =
+
+# If the XML_PROGRAMLISTING tag is set to YES Doxygen will
+# dump the program listings (including syntax highlighting
+# and cross-referencing information) to the XML output. Note that
+# enabling this will significantly increase the size of the XML output.
+
+XML_PROGRAMLISTING     = YES
+
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will
+# generate an AutoGen Definitions (see autogen.sf.net) file
+# that captures the structure of the code including all
+# documentation. Note that this feature is still experimental
+# and incomplete at the moment.
+
+GENERATE_AUTOGEN_DEF   = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_PERLMOD tag is set to YES Doxygen will
+# generate a Perl module file that captures the structure of
+# the code including all documentation. Note that this
+# feature is still experimental and incomplete at the
+# moment.
+
+GENERATE_PERLMOD       = NO
+
+# If the PERLMOD_LATEX tag is set to YES Doxygen will generate
+# the necessary Makefile rules, Perl scripts and LaTeX code to be able
+# to generate PDF and DVI output from the Perl module output.
+
+PERLMOD_LATEX          = NO
+
+# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be
+# nicely formatted so it can be parsed by a human reader.
+# This is useful
+# if you want to understand what is going on.
+# On the other hand, if this
+# tag is set to NO the size of the Perl module output will be much smaller
+# and Perl will parse it just the same.
+
+PERLMOD_PRETTY         = YES
+
+# The names of the make variables in the generated doxyrules.make file
+# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX.
+# This is useful so different doxyrules.make files included by the same
+# Makefile don't overwrite each other's variables.
+
+PERLMOD_MAKEVAR_PREFIX =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+
+# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will
+# evaluate all C-preprocessor directives found in the sources and include
+# files.
+
+ENABLE_PREPROCESSING   = YES
+
+# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro
+# names in the source code. If set to NO (the default) only conditional
+# compilation will be performed. Macro expansion can be done in a controlled
+# way by setting EXPAND_ONLY_PREDEF to YES.
+
+MACRO_EXPANSION        = NO
+
+# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES
+# then the macro expansion is limited to the macros specified with the
+# PREDEFINED and EXPAND_AS_DEFINED tags.
+
+EXPAND_ONLY_PREDEF     = NO
+
+# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files
+# pointed to by INCLUDE_PATH will be searched when a #include is found.
+
+SEARCH_INCLUDES        = YES
+
+# The INCLUDE_PATH tag can be used to specify one or more directories that
+# contain include files that are not input files but should be processed by
+# the preprocessor.
+
+INCLUDE_PATH           =
+
+# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard
+# patterns (like *.h and *.hpp) to filter out the header-files in the
+# directories. If left blank, the patterns specified with FILE_PATTERNS will
+# be used.
+
+INCLUDE_FILE_PATTERNS  =
+
+# The PREDEFINED tag can be used to specify one or more macro names that
+# are defined before the preprocessor is started (similar to the -D option of
+# gcc). The argument of the tag is a list of macros of the form: name
+# or name=definition (no spaces). If the definition and the = are
+# omitted =1 is assumed. To prevent a macro definition from being
+# undefined via #undef or recursively expanded use the := operator
+# instead of the = operator.
+
+PREDEFINED             =
+
+# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then
+# this tag can be used to specify a list of macro names that should be expanded.
+# The macro definition that is found in the sources will be used.
+# Use the PREDEFINED tag if you want to use a different macro definition that
+# overrules the definition found in the source code.
+
+EXPAND_AS_DEFINED      =
+
+# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then
+# doxygen's preprocessor will remove all references to function-like macros
+# that are alone on a line, have an all uppercase name, and do not end with a
+# semicolon, because these will confuse the parser if not removed.
+
+SKIP_FUNCTION_MACROS   = YES
+
+#---------------------------------------------------------------------------
+# Configuration::additions related to external references
+#---------------------------------------------------------------------------
+
+# The TAGFILES option can be used to specify one or more tagfiles.
+# Optionally an initial location of the external documentation
+# can be added for each tagfile. The format of a tag file without
+# this location is as follows:
+#
+# TAGFILES = file1 file2 ...
+# Adding location for the tag files is done as follows:
+#
+# TAGFILES = file1=loc1 "file2 = loc2" ...
+# where "loc1" and "loc2" can be relative or absolute paths or
+# URLs. If a location is present for each tag, the installdox tool
+# does not have to be run to correct the links.
+# Note that each tag file must have a unique name
+# (where the name does NOT include the path)
+# If a tag file is not located in the directory in which doxygen
+# is run, you must also specify the path to the tagfile here.
+
+TAGFILES               =
+
+# When a file name is specified after GENERATE_TAGFILE, doxygen will create
+# a tag file that is based on the input files it reads.
+
+GENERATE_TAGFILE       =
+
+# If the ALLEXTERNALS tag is set to YES all external classes will be listed
+# in the class index. If set to NO only the inherited external classes
+# will be listed.
+
+ALLEXTERNALS           = NO
+
+# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed
+# in the modules index. If set to NO, only the current project's groups will
+# be listed.
+
+EXTERNAL_GROUPS        = YES
+
+# The PERL_PATH should be the absolute path and name of the perl script
+# interpreter (i.e. the result of `which perl').
+
+PERL_PATH              = /usr/bin/perl
+
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+
+# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will
+# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base
+# or super classes. Setting the tag to NO turns the diagrams off. Note that
+# this option also works with HAVE_DOT disabled, but it is recommended to
+# install and use dot, since it yields more powerful graphs.
+
+CLASS_DIAGRAMS         = YES
+
+# You can define message sequence charts within doxygen comments using the \msc
+# command. Doxygen will then run the mscgen tool (see
+# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the
+# documentation. The MSCGEN_PATH tag allows you to specify the directory where
+# the mscgen tool resides. If left empty the tool is assumed to be found in the
+# default search path.
+
+MSCGEN_PATH            =
+
+# If set to YES, the inheritance and collaboration graphs will hide
+# inheritance and usage relations if the target is undocumented
+# or is not a class.
+
+HIDE_UNDOC_RELATIONS   = YES
+
+# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is
+# available from the path. This tool is part of Graphviz, a graph visualization
+# toolkit from AT&T and Lucent Bell Labs. The other options in this section
+# have no effect if this option is set to NO (the default)
+
+HAVE_DOT               = NO
+
+# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is
+# allowed to run in parallel. When set to 0 (the default) doxygen will
+# base this on the number of processors available in the system. You can set it
+# explicitly to a value larger than 0 to get control over the balance
+# between CPU load and processing speed.
+
+DOT_NUM_THREADS        = 0
+
+# By default doxygen will write a font called Helvetica to the output
+# directory and reference it in all dot files that doxygen generates.
+# When you want a differently looking font you can specify the font name
+# using DOT_FONTNAME. You need to make sure dot is able to find the font,
+# which can be done by putting it in a standard location or by setting the
+# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory
+# containing the font.
+
+DOT_FONTNAME           = FreeSans
+
+# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs.
+# The default size is 10pt.
+
+DOT_FONTSIZE           = 10
+
+# By default doxygen will tell dot to use the output directory to look for the
+# FreeSans.ttf font (which doxygen will put there itself). If you specify a
+# different font using DOT_FONTNAME you can set the path where dot
+# can find it using this tag.
+
+DOT_FONTPATH           =
+
+# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen
+# will generate a graph for each documented class showing the direct and
+# indirect inheritance relations. Setting this tag to YES will force the
+# the CLASS_DIAGRAMS tag to NO.
+
+CLASS_GRAPH            = YES
+
+# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen
+# will generate a graph for each documented class showing the direct and
+# indirect implementation dependencies (inheritance, containment, and
+# class references variables) of the class with other documented classes.
+
+COLLABORATION_GRAPH    = YES
+
+# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen
+# will generate a graph for groups, showing the direct groups dependencies
+
+GROUP_GRAPHS           = YES
+
+# If the UML_LOOK tag is set to YES doxygen will generate inheritance and
+# collaboration diagrams in a style similar to the OMG's Unified Modeling
+# Language.
+### TODO ###
+
+UML_LOOK               = YES
+
+# If set to YES, the inheritance and collaboration graphs will show the
+# relations between templates and their instances.
+
+TEMPLATE_RELATIONS     = NO
+
+# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT
+# tags are set to YES then doxygen will generate a graph for each documented
+# file showing the direct and indirect include dependencies of the file with
+# other documented files.
+
+INCLUDE_GRAPH          = YES
+
+# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and
+# HAVE_DOT tags are set to YES then doxygen will generate a graph for each
+# documented header file showing the documented files that directly or
+# indirectly include this file.
+
+INCLUDED_BY_GRAPH      = YES
+
+# If the CALL_GRAPH and HAVE_DOT options are set to YES then
+# doxygen will generate a call dependency graph for every global function
+# or class method. Note that enabling this option will significantly increase
+# the time of a run. So in most cases it will be better to enable call graphs
+# for selected functions only using the \callgraph command.
+
+CALL_GRAPH             = NO
+
+# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then
+# doxygen will generate a caller dependency graph for every global function
+# or class method. Note that enabling this option will significantly increase
+# the time of a run. So in most cases it will be better to enable caller
+# graphs for selected functions only using the \callergraph command.
+
+CALLER_GRAPH           = NO
+
+# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen
+# will generate a graphical hierarchy of all classes instead of a textual one.
+
+GRAPHICAL_HIERARCHY    = YES
+
+# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES
+# then doxygen will show the dependencies a directory has on other directories
+# in a graphical way. The dependency relations are determined by the #include
+# relations between the files in the directories.
+
+DIRECTORY_GRAPH        = YES
+
+# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images
+# generated by dot. Possible values are svg, png, jpg, or gif.
+# If left blank png will be used.
+
+DOT_IMAGE_FORMAT       = png
+
+# The tag DOT_PATH can be used to specify the path where the dot tool can be
+# found. If left blank, it is assumed the dot tool can be found in the path.
+
+DOT_PATH               =
+
+# The DOTFILE_DIRS tag can be used to specify one or more directories that
+# contain dot files that are included in the documentation (see the
+# \dotfile command).
+
+DOTFILE_DIRS           =
+
+# The MSCFILE_DIRS tag can be used to specify one or more directories that
+# contain msc files that are included in the documentation (see the
+# \mscfile command).
+
+MSCFILE_DIRS           =
+
+# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of
+# nodes that will be shown in the graph. If the number of nodes in a graph
+# becomes larger than this value, doxygen will truncate the graph, which is
+# visualized by representing a node as a red box. Note that doxygen if the
+# number of direct children of the root node in a graph is already larger than
+# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note
+# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.
+
+DOT_GRAPH_MAX_NODES    = 50
+
+# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the
+# graphs generated by dot. A depth value of 3 means that only nodes reachable
+# from the root by following a path via at most 3 edges will be shown. Nodes
+# that lay further from the root node will be omitted. Note that setting this
+# option to 1 or 2 may greatly reduce the computation time needed for large
+# code bases. Also note that the size of a graph can be further restricted by
+# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction.
+
+MAX_DOT_GRAPH_DEPTH    = 0
+
+# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent
+# background. This is disabled by default, because dot on Windows does not
+# seem to support this out of the box. Warning: Depending on the platform used,
+# enabling this option may lead to badly anti-aliased labels on the edges of
+# a graph (i.e. they become hard to read).
+
+DOT_TRANSPARENT        = NO
+
+# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output
+# files in one run (i.e. multiple -o and -T options on the command line). This
+# makes dot run faster, but since only newer versions of dot (>1.8.10)
+# support this, this feature is disabled by default.
+
+DOT_MULTI_TARGETS      = NO
+
+# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will
+# generate a legend page explaining the meaning of the various boxes and
+# arrows in the dot generated graphs.
+
+GENERATE_LEGEND        = YES
+
+# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will
+# remove the intermediate dot files that are used to generate
+# the various graphs.
+
+DOT_CLEANUP            = YES
diff --git a/src/ppe/hwp/cache/p9_hcd_cache_poweron.C b/src/ppe/hwp/cache/p9_hcd_cache_poweron.C
index 0aa81a1..3cdf385 100644
--- a/src/ppe/hwp/cache/p9_hcd_cache_poweron.C
+++ b/src/ppe/hwp/cache/p9_hcd_cache_poweron.C
@@ -26,17 +26,17 @@
 /// @file  p9_hcd_cache_poweron.C
 /// @brief Cache Chiplet Power-on
 ///
-/// *HWP HWP Owner   : David Du       <daviddu@us.ibm.com>
-/// *HWP FW Owner    : Sangeetha T S  <sangeet2@in.ibm.com>
-/// *HWP Team        : PM
-/// *HWP Consumed by : SBE:SGPE
-/// *HWP Level       : 1
-///
-/// Procedure Summary:
-///   Command the cache PFET controller to power-on
-///   Check for valid power on completion
-///   Polled Timeout:  100us
-///
+// *HWP HWP Owner   : David Young       <davidy@us.ibm.com>
+// *HWP FW Owner    : Sangeetha T S     <sangeet2@in.ibm.com>
+// *HWP Team        : PM
+// *HWP Consumed by : SBE:SGPE
+// *HWP Level       : 2
+//
+// Procedure Summary:
+//   Command the cache PFET controller to power-on
+//   Check for valid power on completion
+//   Polled Timeout:  100us
+//
 
 //------------------------------------------------------------------------------
 // Includes
@@ -53,32 +53,13 @@
 //------------------------------------------------------------------------------
 // Procedure: Cache Chiplet Power-on
 //------------------------------------------------------------------------------
-
-extern "C"
-{
+#define FAPI_CLEANUP() fapi_try_exit:
 
 fapi2::ReturnCode
 p9_hcd_cache_poweron(
-    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target,
-    const uint32_t i_operation)
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
 {
-
-#if 0
-    fapi2::buffer<uint64_t> data;
-
-    return fapi2::FAPI2_RC_SUCCESS;
-
-    FAPI_CLEANUP();
-    return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA;
-
-#endif
-
-    return fapi2::FAPI2_RC_SUCCESS;
-
+    fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS;
+    FAPI_EXEC_HWP(l_rc, p9_common_poweronoff, i_target, p9power::POWER_ON);
+    return l_rc;
 } // Procedure
-
-
-} // extern C
-
-
-
diff --git a/src/ppe/hwp/cache/p9_hcd_cache_poweron.H b/src/ppe/hwp/cache/p9_hcd_cache_poweron.H
index 89bcffc..5fb5500 100644
--- a/src/ppe/hwp/cache/p9_hcd_cache_poweron.H
+++ b/src/ppe/hwp/cache/p9_hcd_cache_poweron.H
@@ -25,42 +25,38 @@
 ///
 /// @file  p9_hcd_cache_poweron.H
 /// @brief Cache Chiplet Power-on
-///
-/// *HWP HWP Owner   : David Du       <daviddu@us.ibm.com>
-/// *HWP FW Owner    : Sangeetha T S  <sangeet2@in.ibm.com>
-/// *HWP Team        : PM
-/// *HWP Consumed by : SBE:SGPE
-/// *HWP Level       : 1
-///
+
+//
+// *HWP HWP Owner   : David Young       <davidy@us.ibm.com>
+// *HWP FW Owner    : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team        : PM
+// *HWP Level       : 2
+// *HWP Consumed by : SBE:SGPE
+//
 
 #ifndef __P9_HCD_CACHE_POWERON_H__
 #define __P9_HCD_CACHE_POWERON_H__
 
-extern "C"
-{
+#include "p9_common_poweronoff.H"
 
 /// @typedef p9_hcd_cache_poweron_FP_t
 /// function pointer typedef definition for HWP call support
 typedef fapi2::ReturnCode (*p9_hcd_cache_poweron_FP_t) (
-    const fapi2::Target<fapi2::TARGET_TYPE_EQ>&,
-    const uint32_t);
-
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
 
+extern "C"
+{
 /// @brief Cache Chiplet Power-on
-///
 /// @param [in] i_target    TARGET_TYPE_EQ target
 /// @param [in] i_operation ENUM(ON,OFF)
 ///
 /// @attr
 /// @attritem ATTR_PFET_*
 ///
-/// @retval FAPI_RC_SUCCESS
+/// @retval FAPI2_RC_SUCCESS if success, else error code
+
 fapi2::ReturnCode
 p9_hcd_cache_poweron(
-    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target,
-    const uint32_t i_operation);
-
-
-} // extern C
-
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
+}
 #endif  // __P9_HCD_CACHE_POWERON_H__
diff --git a/src/ppe/hwp/cache/wrapper/proc_cache_poweron_wrap.C b/src/ppe/hwp/cache/wrapper/proc_cache_poweron_wrap.C
new file mode 100644
index 0000000..fbfc511
--- /dev/null
+++ b/src/ppe/hwp/cache/wrapper/proc_cache_poweron_wrap.C
@@ -0,0 +1,248 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/cache/wrapper/proc_cache_poweron_wrap.C $         */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// ----------------------------------------------------------------------
+// Includes / eCMD Includes
+// ----------------------------------------------------------------------
+#include <prcdUtils.H>
+
+#include <croClientCapi.H>
+#include <ecmdClientCapi.H>
+#include <ecmdUtils.H>
+#include <ecmdSharedUtils.H>
+#include <fapi2.H>
+#include <fapi2ClientCapi.H>
+#include <fapi2SharedUtils.H>
+
+#include <string>
+#include <sstream>
+
+#include <p9_hcd_cache_poweron.H>
+
+
+// ----------------------------------------------------------------------
+// Function definitions
+// ----------------------------------------------------------------------
+
+// display help message
+void help()
+{
+    // procedure constants
+    const std::string PROCEDURE = "p9_hcd_cache_poweron_wrap";
+    const std::string REVISION  = "$Revision: 1.1 $";
+    // build help message
+    char outstr[200];
+    snprintf(outstr, sizeof(outstr), "\nThis is the help text for the procedure %s (%s)\n", PROCEDURE.c_str(), REVISION.c_str());
+    ecmdOutput(outstr);
+    snprintf(outstr, sizeof(outstr), "Syntax: %s\n", PROCEDURE.c_str());
+    ecmdOutput(outstr);
+    ecmdOutput("        [-h] [-k#] [-n#] [-s#] [-p#] [-verif]\n");
+    ecmdOutput("\n");
+    ecmdOutput("Additional options:\n");
+    ecmdOutput("      -h                           This help\n");
+    ecmdOutput("\n");
+}
+
+
+// main function
+int main(int argc, char *argv[])
+{
+    // procedure constants
+    const std::string PROCEDURE = "p9_hcd_cache_poweron_wrap";
+    const std::string REVISION  = "$Revision: 1.1 $";
+
+    // from prcdUtils
+    extern bool GLOBAL_SIM_MODE;
+    extern bool GLOBAL_VERIF_MODE;
+
+    // flow/control variables
+    uint32_t rc = ECMD_SUCCESS;
+    ecmdDllInfo DLLINFO;
+    ecmdLooperData looper;
+    ecmdChipTarget target;
+    bool valid_pos_found = false;
+    char outstr[200];
+
+    fapi2::ReturnCode rc_fapi(fapi2::FAPI2_RC_SUCCESS);
+
+
+    //-----------------------------------------------------------------------------------------
+    // load and initialize the eCMD Dll
+    // if left NULL, which DLL to load is determined by the ECMD_DLL_FILE environment variable
+    // if set to a specific value, the specified DLL will be loaded
+    //-----------------------------------------------------------------------------------------
+    rc = ecmdLoadDll("");
+    if (rc) return rc;
+
+    //-----------------------------------------------------------------------------------------
+    // This is needed if you're running a FAPI procedure from this eCMD procedure
+    //-----------------------------------------------------------------------------------------
+
+    // initalize FAPI2 extension
+    rc = fapi2InitExtension();
+    if (rc)
+    {
+        ecmdOutputError("Error initializing FAPI2 extension!\n");
+        return rc;
+    }
+
+
+
+    // establish if this is a simulation run or not
+    rc = ecmdQueryDllInfo(DLLINFO);
+    if (rc)
+    {
+        ecmdUnloadDll();
+        return rc;
+    }
+    if (DLLINFO.dllEnv == ECMD_DLL_ENV_SIM)
+    {
+        GLOBAL_SIM_MODE = true;
+    }
+
+    //-------------------------------------------------------------------------------------------------
+    // Parse out user options (excluding -pX, -cX, -coe, -debug, etc
+    // E.G., ecmdRunHwp.x86 -testmode
+    //-------------------------------------------------------------------------------------------------
+    if (ecmdParseOption(&argc, &argv, "-h"))
+    {
+        help();
+        ecmdUnloadDll();
+        return rc;
+    }
+
+
+    // run procedure in sim verification mode
+    if (ecmdParseOption(&argc, &argv, "-verif"))
+    {
+        GLOBAL_VERIF_MODE = true;
+    }
+
+    //-------------------------------------------------------------------------------------------------
+    // Parse out common eCMD args like -p0, -c0, -coe, etc..
+    // Any found args will be removed from arg list upon return
+    //-------------------------------------------------------------------------------------------------
+    rc = ecmdCommandArgs(&argc, &argv);
+    if (rc)
+    {
+        ecmdUnloadDll();
+        return rc;
+    }
+
+    // unsupported arguments left over?
+    if (argc != 1)
+    {
+        ecmdOutputError("Unknown/unsupported arguments specified!\n");
+        help();
+        ecmdUnloadDll();
+        return ECMD_INVALID_ARGS;
+    }
+
+    //-------------------------------------------------------------------------------------------------
+    // Let's always print the dll info to the screen, unless in quiet mode
+    //-------------------------------------------------------------------------------------------------
+
+    if (!ecmdGetGlobalVar(ECMD_GLOBALVAR_QUIETMODE))
+    {
+        // print informational message
+        snprintf(outstr, sizeof(outstr), "Procedure %s: %s\n", PROCEDURE.c_str(), REVISION.c_str());
+        ecmdOutput(outstr);
+
+        // always print the DLL info to the screen, unless in quiet mode
+        rc = ecmdDisplayDllInfo();
+        if (rc)
+        {
+            return rc;
+        }
+    }
+
+    //-------------------------------------------------------------------------------------------------
+    // Loop over all all pu chips
+    //-------------------------------------------------------------------------------------------------
+    target.chipType      = "pu";
+    target.chipTypeState = ECMD_TARGET_FIELD_VALID;
+    target.cageState     = ECMD_TARGET_FIELD_WILDCARD;
+    target.nodeState     = ECMD_TARGET_FIELD_WILDCARD;
+    target.slotState     = ECMD_TARGET_FIELD_WILDCARD;
+    target.posState      = ECMD_TARGET_FIELD_WILDCARD;
+    target.coreState     = ECMD_TARGET_FIELD_UNUSED;
+    target.threadState   = ECMD_TARGET_FIELD_UNUSED;
+
+    rc = ecmdConfigLooperInit(target, ECMD_SELECTED_TARGETS_LOOP, looper);
+    if (rc)
+    {
+        ecmdOutputError("Error initializing proc chip looper!\n");
+        ecmdUnloadDll();
+        return rc;
+    }
+    while (ecmdConfigLooperNext(target, looper))
+    {
+        if (!ecmdGetGlobalVar(ECMD_GLOBALVAR_QUIETMODE))
+        {
+            snprintf(outstr, sizeof(outstr),
+                     "Going to call %s on proc k%d:n%d:s%d:p%02d\n",
+                     PROCEDURE.c_str(), target.cage, target.node,
+                                        target.slot, target.pos);
+            ecmdOutput(outstr);
+        }
+
+        // EXAMPLE setting up a fapi2::Target from an ecmdChipTarget
+        fapi2::Target<fapi2::TARGET_TYPE_EQ> fapi_target(&target);
+
+        // invoke FAPI procedure core
+        FAPI_EXEC_HWP(rc_fapi, p9_hcd_cache_poweron, fapi_target);
+        rc = (uint64_t) rc_fapi;
+        if (rc)
+        {
+            snprintf(outstr, sizeof(outstr),
+                     "ERROR: %s FAPI call exited with return code = %s 0x%08x \n",
+                     PROCEDURE.c_str(), ecmdParseReturnCode(rc).c_str(), rc);
+            ecmdOutputError(outstr);
+            ecmdUnloadDll();
+            return rc;
+        }
+
+        // mark that valid position has been found
+        valid_pos_found = true;
+    }
+
+    // check that a valid target was found
+    if (rc == ECMD_SUCCESS && !valid_pos_found)
+    {
+        ecmdOutputError("No valid targets found!\n");
+        ecmdUnloadDll();
+        return ECMD_TARGET_NOT_CONFIGURED;
+    }
+
+    prcdInfoMessage("----------------------------------------\n");
+    prcdInfoMessage("      p9_hcd_cache_poweron is done\n");
+    prcdInfoMessage("----------------------------------------\n");
+
+    //-----------------------------------------------------------------------------------------------
+    // Unload the eCMD Dll, this should always be the last thing you do
+    //-----------------------------------------------------------------------------------------------
+
+    ecmdUnloadDll();
+    return rc;
+}
diff --git a/src/ppe/hwp/core/corehcderrors.mk b/src/ppe/hwp/core/corehcderrors.mk
new file mode 100644
index 0000000..706cbe6
--- /dev/null
+++ b/src/ppe/hwp/core/corehcderrors.mk
@@ -0,0 +1,54 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ppe/hwp/core/corehcderrors.mk $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file corehcderrors.mk
+#
+#  @brief mk for including core error files
+#
+#  @page ChangeLogs Change Logs
+#  @section corehcderrors.mk
+#
+##########################################################################
+# Error Files
+##########################################################################
+
+CORE_CURR_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+
+# This variable name must not change
+#ERROR_XML_FILES += $(CORE_CURR_DIR)/p9_hcd_core_arrayinit_errors.xml
+#ERROR_XML_FILES += $(CORE_CURR_DIR)/p9_hcd_core_chiplet_init_errors.xml
+#ERROR_XML_FILES += $(CORE_CURR_DIR)/p9_hcd_core_chiplet_reset_errors.xml
+#ERROR_XML_FILES += $(CORE_CURR_DIR)/p9_hcd_core_gptr_time_initf_errors.xml
+#ERROR_XML_FILES += $(CORE_CURR_DIR)/p9_hcd_core_initf_errors.xml
+#ERROR_XML_FILES += $(CORE_CURR_DIR)/p9_hcd_core_occ_runtime_scom_errors.xml
+#ERROR_XML_FILES += $(CORE_CURR_DIR)/p9_hcd_core_pcb_arb_errors.xml
+#ERROR_XML_FILES += $(CORE_CURR_DIR)/p9_hcd_core_poweron_errors.xml
+#ERROR_XML_FILES += $(CORE_CURR_DIR)/p9_hcd_core_ras_runtime_scom_errors.xml
+#ERROR_XML_FILES += $(CORE_CURR_DIR)/p9_hcd_core_repair_initf_errors.xml
+#ERROR_XML_FILES += $(CORE_CURR_DIR)/p9_hcd_core_runinit_errors.xml
+#ERROR_XML_FILES += $(CORE_CURR_DIR)/p9_hcd_core_scomcust_errors.xml
+#ERROR_XML_FILES += $(CORE_CURR_DIR)/p9_hcd_core_scominit_errors.xml
+#ERROR_XML_FILES += $(CORE_CURR_DIR)/p9_hcd_core_startclocks_errors.xml
+
+
diff --git a/src/ppe/hwp/core/doc/Makefile b/src/ppe/hwp/core/doc/Makefile
new file mode 100755
index 0000000..5dc397f
--- /dev/null
+++ b/src/ppe/hwp/core/doc/Makefile
@@ -0,0 +1,43 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ppe/hwp/core/doc/Makefile $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+
+# Process the Doxygen html using the stadard CTE doxygen
+CTEPATH = /afs/awd.austin.ibm.com/projects/cte
+#DOXYGEN = $(CTEPATH)/tools/gsiexe/eclipz/doxygen
+DOXYGEN = doxygen
+
+.PHONY : dox
+dox: 
+	$(DOXYGEN) hcd_core.dox >hcd_core.dox.lst 2>&1
+
+
+#  Publish the Doxygen HTML (pending final decision on where to put it)
+
+#POKDOC = /afs/apd/func/vlsi/eclipz/common/doc/www/sys/ras/scom/p8/poreve
+
+#publish:
+#	rm -rf $(POKDOC)/doxygen
+#	cp -a html $(POKDOC)/doxygen
+
diff --git a/src/ppe/hwp/core/doc/hcd_core.dox b/src/ppe/hwp/core/doc/hcd_core.dox
new file mode 100644
index 0000000..7044114
--- /dev/null
+++ b/src/ppe/hwp/core/doc/hcd_core.dox
@@ -0,0 +1,1721 @@
+
+# This file describes the settings to be used by the documentation system
+# doxygen (www.doxygen.org) for a project.
+#
+# All text after a hash (#) is considered a comment and will be ignored.
+# The format is:
+#       TAG = value [value, ...]
+# For lists items can also be appended using:
+#       TAG += value [value, ...]
+# Values that contain spaces should be placed between quotes (" ").
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+
+# This tag specifies the encoding used for all characters in the config file
+# that follow. The default is UTF-8 which is also the encoding used for all
+# text before the first occurrence of this tag. Doxygen uses libiconv (or the
+# iconv built into libc) for the transcoding. See
+# http://www.gnu.org/software/libiconv for the list of possible encodings.
+
+DOXYFILE_ENCODING      = UTF-8
+
+# The PROJECT_NAME tag is a single word (or a sequence of words surrounded
+# by quotes) that should identify the project.
+
+PROJECT_NAME           = P9_Power_Management_Hcode
+
+# The PROJECT_NUMBER tag can be used to enter a project or revision number.
+# This could be handy for archiving the generated documentation or
+# if some version control system is used.
+
+PROJECT_NUMBER         =
+
+# Using the PROJECT_BRIEF tag one can provide an optional one line description
+# for a project that appears at the top of each page and should give viewer
+# a quick idea about the purpose of the project. Keep the description short.
+
+PROJECT_BRIEF          = P9 Power Management Hcode
+
+# With the PROJECT_LOGO tag one can specify an logo or icon that is
+# included in the documentation. The maximum height of the logo should not
+# exceed 55 pixels and the maximum width should not exceed 200 pixels.
+# Doxygen will copy the logo to the output directory.
+
+PROJECT_LOGO           =
+
+# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
+# base path where the generated documentation will be put.
+# If a relative path is entered, it will be relative to the location
+# where doxygen was started. If left blank the current directory will be used.
+
+OUTPUT_DIRECTORY       =
+
+# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create
+# 4096 sub-directories (in 2 levels) under the output directory of each output
+# format and will distribute the generated files over these directories.
+# Enabling this option can be useful when feeding doxygen a huge amount of
+# source files, where putting all generated files in the same directory would
+# otherwise cause performance problems for the file system.
+
+CREATE_SUBDIRS         = NO
+
+# The OUTPUT_LANGUAGE tag is used to specify the language in which all
+# documentation generated by doxygen is written. Doxygen will use this
+# information to generate all constant output in the proper language.
+# The default language is English, other supported languages are:
+# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional,
+# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German,
+# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English
+# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian,
+# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrillic, Slovak,
+# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese.
+
+OUTPUT_LANGUAGE        = English
+
+# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will
+# include brief member descriptions after the members that are listed in
+# the file and class documentation (similar to JavaDoc).
+# Set to NO to disable this.
+
+BRIEF_MEMBER_DESC      = YES
+
+# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend
+# the brief description of a member or function before the detailed description.
+# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the
+# brief descriptions will be completely suppressed.
+
+REPEAT_BRIEF           = YES
+
+# This tag implements a quasi-intelligent brief description abbreviator
+# that is used to form the text in various listings. Each string
+# in this list, if found as the leading text of the brief description, will be
+# stripped from the text and the result after processing the whole list, is
+# used as the annotated text. Otherwise, the brief description is used as-is.
+# If left blank, the following values are used ("$name" is automatically
+# replaced with the name of the entity): "The $name class" "The $name widget"
+# "The $name file" "is" "provides" "specifies" "contains"
+# "represents" "a" "an" "the"
+
+ABBREVIATE_BRIEF       =
+
+# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then
+# Doxygen will generate a detailed section even if there is only a brief
+# description.
+
+ALWAYS_DETAILED_SEC    = NO
+
+# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all
+# inherited members of a class in the documentation of that class as if those
+# members were ordinary class members. Constructors, destructors and assignment
+# operators of the base classes will not be shown.
+
+INLINE_INHERITED_MEMB  = NO
+
+# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full
+# path before files name in the file list and in the header files. If set
+# to NO the shortest path that makes the file name unique will be used.
+
+FULL_PATH_NAMES        = NO
+
+# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag
+# can be used to strip a user-defined part of the path. Stripping is
+# only done if one of the specified strings matches the left-hand part of
+# the path. The tag can be used to show relative paths in the file list.
+# If left blank the directory from which doxygen is run is used as the
+# path to strip.
+
+STRIP_FROM_PATH        =
+
+# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of
+# the path mentioned in the documentation of a class, which tells
+# the reader which header file to include in order to use a class.
+# If left blank only the name of the header file containing the class
+# definition is used. Otherwise one should specify the include paths that
+# are normally passed to the compiler using the -I flag.
+
+STRIP_FROM_INC_PATH    =
+
+# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter
+# (but less readable) file names. This can be useful if your file system
+# doesn't support long names like on DOS, Mac, or CD-ROM.
+
+SHORT_NAMES            = NO
+
+# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen
+# will interpret the first line (until the first dot) of a JavaDoc-style
+# comment as the brief description. If set to NO, the JavaDoc
+# comments will behave just like regular Qt-style comments
+# (thus requiring an explicit @brief command for a brief description.)
+
+JAVADOC_AUTOBRIEF      = NO
+
+# If the QT_AUTOBRIEF tag is set to YES then Doxygen will
+# interpret the first line (until the first dot) of a Qt-style
+# comment as the brief description. If set to NO, the comments
+# will behave just like regular Qt-style comments (thus requiring
+# an explicit \brief command for a brief description.)
+
+QT_AUTOBRIEF           = NO
+
+# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen
+# treat a multi-line C++ special comment block (i.e. a block of //! or ///
+# comments) as a brief description. This used to be the default behaviour.
+# The new default is to treat a multi-line C++ comment block as a detailed
+# description. Set this tag to YES if you prefer the old behaviour instead.
+
+MULTILINE_CPP_IS_BRIEF = YES
+
+# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented
+# member inherits the documentation from any documented member that it
+# re-implements.
+
+INHERIT_DOCS           = YES
+
+# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce
+# a new page for each member. If set to NO, the documentation of a member will
+# be part of the file/class/namespace that contains it.
+
+SEPARATE_MEMBER_PAGES  = NO
+
+# The TAB_SIZE tag can be used to set the number of spaces in a tab.
+# Doxygen uses this value to replace tabs by spaces in code fragments.
+
+TAB_SIZE               = 8
+
+# This tag can be used to specify a number of aliases that acts
+# as commands in the documentation. An alias has the form "name=value".
+# For example adding "sideeffect=\par Side Effects:\n" will allow you to
+# put the command \sideeffect (or @sideeffect) in the documentation, which
+# will result in a user-defined paragraph with heading "Side Effects:".
+# You can put \n's in the value part of an alias to insert newlines.
+
+ALIASES                 += attr="\par \b Attributes:"
+ALIASES                 += attritem{2}="\1 \2"
+
+# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C
+# sources only. Doxygen will then generate output that is more tailored for C.
+# For instance, some of the names that are used will be different. The list
+# of all members will be omitted, etc.
+
+OPTIMIZE_OUTPUT_FOR_C  = NO
+
+# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java
+# sources only. Doxygen will then generate output that is more tailored for
+# Java. For instance, namespaces will be presented as packages, qualified
+# scopes will look different, etc.
+
+OPTIMIZE_OUTPUT_JAVA   = NO
+
+# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran
+# sources only. Doxygen will then generate output that is more tailored for
+# Fortran.
+
+OPTIMIZE_FOR_FORTRAN   = NO
+
+# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL
+# sources. Doxygen will then generate output that is tailored for
+# VHDL.
+
+OPTIMIZE_OUTPUT_VHDL   = NO
+
+# Doxygen selects the parser to use depending on the extension of the files it
+# parses. With this tag you can assign which parser to use for a given extension.
+# Doxygen has a built-in mapping, but you can override or extend it using this
+# tag. The format is ext=language, where ext is a file extension, and language
+# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C,
+# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make
+# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C
+# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions
+# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen.
+
+EXTENSION_MAPPING      =
+
+# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want
+# to include (a tag file for) the STL sources as input, then you should
+# set this tag to YES in order to let doxygen match functions declarations and
+# definitions whose arguments contain STL classes (e.g. func(std::string); v.s.
+# func(std::string) {}). This also makes the inheritance and collaboration
+# diagrams that involve STL classes more complete and accurate.
+
+BUILTIN_STL_SUPPORT    = NO
+
+# If you use Microsoft's C++/CLI language, you should set this option to YES to
+# enable parsing support.
+
+CPP_CLI_SUPPORT        = NO
+
+# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only.
+# Doxygen will parse them like normal C++ but will assume all classes use public
+# instead of private inheritance when no explicit protection keyword is present.
+
+SIP_SUPPORT            = NO
+
+# For Microsoft's IDL there are propget and propput attributes to indicate getter
+# and setter methods for a property. Setting this option to YES (the default)
+# will make doxygen replace the get and set methods by a property in the
+# documentation. This will only work if the methods are indeed getting or
+# setting a simple type. If this is not the case, or you want to show the
+# methods anyway, you should set this option to NO.
+
+IDL_PROPERTY_SUPPORT   = YES
+
+# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC
+# tag is set to YES, then doxygen will reuse the documentation of the first
+# member in the group (if any) for the other members of the group. By default
+# all members of a group must be documented explicitly.
+
+DISTRIBUTE_GROUP_DOC   = NO
+
+# Set the SUBGROUPING tag to YES (the default) to allow class member groups of
+# the same type (for instance a group of public functions) to be put as a
+# subgroup of that type (e.g. under the Public Functions section). Set it to
+# NO to prevent subgrouping. Alternatively, this can be done per class using
+# the \nosubgrouping command.
+
+SUBGROUPING            = YES
+
+# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and
+# unions are shown inside the group in which they are included (e.g. using
+# @ingroup) instead of on a separate page (for HTML and Man pages) or
+# section (for LaTeX and RTF).
+
+INLINE_GROUPED_CLASSES = NO
+
+# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum
+# is documented as struct, union, or enum with the name of the typedef. So
+# typedef struct TypeS {} TypeT, will appear in the documentation as a struct
+# with name TypeT. When disabled the typedef will appear as a member of a file,
+# namespace, or class. And the struct will be named TypeS. This can typically
+# be useful for C code in case the coding convention dictates that all compound
+# types are typedef'ed and only the typedef is referenced, never the tag name.
+
+TYPEDEF_HIDES_STRUCT   = NO
+
+# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to
+# determine which symbols to keep in memory and which to flush to disk.
+# When the cache is full, less often used symbols will be written to disk.
+# For small to medium size projects (<1000 input files) the default value is
+# probably good enough. For larger projects a too small cache size can cause
+# doxygen to be busy swapping symbols to and from disk most of the time
+# causing a significant performance penalty.
+# If the system has enough physical memory increasing the cache will improve the
+# performance by keeping more symbols in memory. Note that the value works on
+# a logarithmic scale so increasing the size by one will roughly double the
+# memory usage. The cache size is given by this formula:
+# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0,
+# corresponding to a cache size of 2^16 = 65536 symbols
+
+SYMBOL_CACHE_SIZE      = 0
+
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+
+# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in
+# documentation are documented, even if no documentation was available.
+# Private class members and static file members will be hidden unless
+# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES
+### TODO ###
+EXTRACT_ALL            = YES
+
+# If the EXTRACT_PRIVATE tag is set to YES all private members of a class
+# will be included in the documentation.
+
+EXTRACT_PRIVATE        = NO
+
+# If the EXTRACT_STATIC tag is set to YES all static members of a file
+# will be included in the documentation.
+
+EXTRACT_STATIC         = NO
+
+# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs)
+# defined locally in source files will be included in the documentation.
+# If set to NO only classes defined in header files are included.
+
+EXTRACT_LOCAL_CLASSES  = YES
+
+# This flag is only useful for Objective-C code. When set to YES local
+# methods, which are defined in the implementation section but not in
+# the interface are included in the documentation.
+# If set to NO (the default) only methods in the interface are included.
+
+EXTRACT_LOCAL_METHODS  = NO
+
+# If this flag is set to YES, the members of anonymous namespaces will be
+# extracted and appear in the documentation as a namespace called
+# 'anonymous_namespace{file}', where file will be replaced with the base
+# name of the file that contains the anonymous namespace. By default
+# anonymous namespaces are hidden.
+
+EXTRACT_ANON_NSPACES   = NO
+
+# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all
+# undocumented members of documented classes, files or namespaces.
+# If set to NO (the default) these members will be included in the
+# various overviews, but no documentation section is generated.
+# This option has no effect if EXTRACT_ALL is enabled.
+
+HIDE_UNDOC_MEMBERS     = NO
+
+# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all
+# undocumented classes that are normally visible in the class hierarchy.
+# If set to NO (the default) these classes will be included in the various
+# overviews. This option has no effect if EXTRACT_ALL is enabled.
+
+HIDE_UNDOC_CLASSES     = NO
+
+# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all
+# friend (class|struct|union) declarations.
+# If set to NO (the default) these declarations will be included in the
+# documentation.
+
+HIDE_FRIEND_COMPOUNDS  = NO
+
+# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any
+# documentation blocks found inside the body of a function.
+# If set to NO (the default) these blocks will be appended to the
+# function's detailed documentation block.
+
+HIDE_IN_BODY_DOCS      = NO
+
+# The INTERNAL_DOCS tag determines if documentation
+# that is typed after a \internal command is included. If the tag is set
+# to NO (the default) then the documentation will be excluded.
+# Set it to YES to include the internal documentation.
+
+INTERNAL_DOCS          = NO
+
+# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate
+# file names in lower-case letters. If set to YES upper-case letters are also
+# allowed. This is useful if you have classes or files whose names only differ
+# in case and if your file system supports case sensitive file names. Windows
+# and Mac users are advised to set this option to NO.
+
+CASE_SENSE_NAMES       = YES
+
+# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen
+# will show members with their full class and namespace scopes in the
+# documentation. If set to YES the scope will be hidden.
+
+HIDE_SCOPE_NAMES       = NO
+
+# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen
+# will put a list of the files that are included by a file in the documentation
+# of that file.
+
+SHOW_INCLUDE_FILES     = YES
+
+# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen
+# will list include files with double quotes in the documentation
+# rather than with sharp brackets.
+
+FORCE_LOCAL_INCLUDES   = NO
+
+# If the INLINE_INFO tag is set to YES (the default) then a tag [inline]
+# is inserted in the documentation for inline members.
+
+INLINE_INFO            = YES
+
+# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen
+# will sort the (detailed) documentation of file and class members
+# alphabetically by member name. If set to NO the members will appear in
+# declaration order.
+
+SORT_MEMBER_DOCS       = YES
+
+# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the
+# brief documentation of file, namespace and class members alphabetically
+# by member name. If set to NO (the default) the members will appear in
+# declaration order.
+
+SORT_BRIEF_DOCS        = NO
+
+# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen
+# will sort the (brief and detailed) documentation of class members so that
+# constructors and destructors are listed first. If set to NO (the default)
+# the constructors will appear in the respective orders defined by
+# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS.
+# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO
+# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO.
+
+SORT_MEMBERS_CTORS_1ST = NO
+
+# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the
+# hierarchy of group names into alphabetical order. If set to NO (the default)
+# the group names will appear in their defined order.
+
+SORT_GROUP_NAMES       = NO
+
+# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be
+# sorted by fully-qualified names, including namespaces. If set to
+# NO (the default), the class list will be sorted only by class name,
+# not including the namespace part.
+# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.
+# Note: This option applies only to the class list, not to the
+# alphabetical list.
+
+SORT_BY_SCOPE_NAME     = NO
+
+# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to
+# do proper type resolution of all parameters of a function it will reject a
+# match between the prototype and the implementation of a member function even
+# if there is only one candidate or it is obvious which candidate to choose
+# by doing a simple string match. By disabling STRICT_PROTO_MATCHING doxygen
+# will still accept a match between prototype and implementation in such cases.
+
+STRICT_PROTO_MATCHING  = NO
+
+# The GENERATE_TODOLIST tag can be used to enable (YES) or
+# disable (NO) the todo list. This list is created by putting \todo
+# commands in the documentation.
+
+GENERATE_TODOLIST      = YES
+
+# The GENERATE_TESTLIST tag can be used to enable (YES) or
+# disable (NO) the test list. This list is created by putting \test
+# commands in the documentation.
+
+GENERATE_TESTLIST      = YES
+
+# The GENERATE_BUGLIST tag can be used to enable (YES) or
+# disable (NO) the bug list. This list is created by putting \bug
+# commands in the documentation.
+
+GENERATE_BUGLIST       = YES
+
+# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or
+# disable (NO) the deprecated list. This list is created by putting
+# \deprecated commands in the documentation.
+
+GENERATE_DEPRECATEDLIST= YES
+
+# The ENABLED_SECTIONS tag can be used to enable conditional
+# documentation sections, marked by \if sectionname ... \endif.
+
+ENABLED_SECTIONS       =
+
+# The MAX_INITIALIZER_LINES tag determines the maximum number of lines
+# the initial value of a variable or macro consists of for it to appear in
+# the documentation. If the initializer consists of more lines than specified
+# here it will be hidden. Use a value of 0 to hide initializers completely.
+# The appearance of the initializer of individual variables and macros in the
+# documentation can be controlled using \showinitializer or \hideinitializer
+# command in the documentation regardless of this setting.
+
+MAX_INITIALIZER_LINES  = 30
+
+# Set the SHOW_USED_FILES tag to NO to disable the list of files generated
+# at the bottom of the documentation of classes and structs. If set to YES the
+# list will mention the files that were used to generate the documentation.
+
+SHOW_USED_FILES        = YES
+
+# If the sources in your project are distributed over multiple directories
+# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy
+# in the documentation. The default is NO.
+
+SHOW_DIRECTORIES       = NO
+
+# Set the SHOW_FILES tag to NO to disable the generation of the Files page.
+# This will remove the Files entry from the Quick Index and from the
+# Folder Tree View (if specified). The default is YES.
+
+SHOW_FILES             = YES
+
+# Set the SHOW_NAMESPACES tag to NO to disable the generation of the
+# Namespaces page.
+# This will remove the Namespaces entry from the Quick Index
+# and from the Folder Tree View (if specified). The default is YES.
+
+SHOW_NAMESPACES        = YES
+
+# The FILE_VERSION_FILTER tag can be used to specify a program or script that
+# doxygen should invoke to get the current version for each file (typically from
+# the version control system). Doxygen will invoke the program by executing (via
+# popen()) the command <command> <input-file>, where <command> is the value of
+# the FILE_VERSION_FILTER tag, and <input-file> is the name of an input file
+# provided by doxygen. Whatever the program writes to standard output
+# is used as the file version. See the manual for examples.
+
+FILE_VERSION_FILTER    =
+
+# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed
+# by doxygen. The layout file controls the global structure of the generated
+# output files in an output format independent way. The create the layout file
+# that represents doxygen's defaults, run doxygen with the -l option.
+# You can optionally specify a file name after the option, if omitted
+# DoxygenLayout.xml will be used as the name of the layout file.
+
+LAYOUT_FILE            =
+
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+
+# The QUIET tag can be used to turn on/off the messages that are generated
+# by doxygen. Possible values are YES and NO. If left blank NO is used.
+
+QUIET                  = NO
+
+# The WARNINGS tag can be used to turn on/off the warning messages that are
+# generated by doxygen. Possible values are YES and NO. If left blank
+# NO is used.
+
+WARNINGS               = YES
+
+# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings
+# for undocumented members. If EXTRACT_ALL is set to YES then this flag will
+# automatically be disabled.
+
+WARN_IF_UNDOCUMENTED   = YES
+
+# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for
+# potential errors in the documentation, such as not documenting some
+# parameters in a documented function, or documenting parameters that
+# don't exist or using markup commands wrongly.
+
+WARN_IF_DOC_ERROR      = YES
+
+# The WARN_NO_PARAMDOC option can be enabled to get warnings for
+# functions that are documented, but have no documentation for their parameters
+# or return value. If set to NO (the default) doxygen will only warn about
+# wrong or incomplete parameter documentation, but not about the absence of
+# documentation.
+
+WARN_NO_PARAMDOC       = NO
+
+# The WARN_FORMAT tag determines the format of the warning messages that
+# doxygen can produce. The string should contain the $file, $line, and $text
+# tags, which will be replaced by the file and line number from which the
+# warning originated and the warning text. Optionally the format may contain
+# $version, which will be replaced by the version of the file (if it could
+# be obtained via FILE_VERSION_FILTER)
+
+WARN_FORMAT            = "$file:$line: $text"
+
+# The WARN_LOGFILE tag can be used to specify a file to which warning
+# and error messages should be written. If left blank the output is written
+# to stderr.
+
+WARN_LOGFILE           =
+
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+
+# The INPUT tag can be used to specify the files and/or directories that contain
+# documented source files. You may enter file names like "myfile.cpp" or
+# directories like "/usr/src/myproject". Separate the files or directories
+# with spaces.
+
+INPUT                  = "../"
+                          
+
+# This tag can be used to specify the character encoding of the source files
+# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is
+# also the default input encoding. Doxygen uses libiconv (or the iconv built
+# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for
+# the list of possible encodings.
+
+INPUT_ENCODING         = UTF-8
+
+# If the value of the INPUT tag contains directories, you can use the
+# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
+# and *.h) to filter out the source-files in the directories. If left
+# blank the following patterns are tested:
+# *.c *.cc *.cxx *.cpp *.c++ *.d *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh
+# *.hxx *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.dox *.py
+# *.f90 *.f *.for *.vhd *.vhdl
+
+FILE_PATTERNS          =  *hcd*.dox *hcd*.C *hcd*.H *.S
+                      
+                         
+                         
+
+# The RECURSIVE tag can be used to turn specify whether or not subdirectories
+# should be searched for input files as well. Possible values are YES and NO.
+# If left blank NO is used.
+
+RECURSIVE              = NO
+
+# The EXCLUDE tag can be used to specify files and/or directories that should
+# excluded from the INPUT source files. This way you can easily exclude a
+# subdirectory from a directory tree whose root is specified with the INPUT tag.
+
+EXCLUDE                =
+
+# The EXCLUDE_SYMLINKS tag can be used select whether or not files or
+# directories that are symbolic links (a Unix file system feature) are excluded
+# from the input.
+
+EXCLUDE_SYMLINKS       = NO
+
+# If the value of the INPUT tag contains directories, you can use the
+# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude
+# certain files from those directories. Note that the wildcards are matched
+# against the file with absolute path, so to exclude all test directories
+# for example use the pattern */test/*
+
+EXCLUDE_PATTERNS       =
+
+# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names
+# (namespaces, classes, functions, etc.) that should be excluded from the
+# output. The symbol name can be a fully qualified name, a word, or if the
+# wildcard * is used, a substring. Examples: ANamespace, AClass,
+# AClass::ANamespace, ANamespace::*Test
+
+EXCLUDE_SYMBOLS        =
+
+# The EXAMPLE_PATH tag can be used to specify one or more files or
+# directories that contain example code fragments that are included (see
+# the \include command).
+
+EXAMPLE_PATH           =
+
+# If the value of the EXAMPLE_PATH tag contains directories, you can use the
+# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
+# and *.h) to filter out the source-files in the directories. If left
+# blank all files are included.
+
+EXAMPLE_PATTERNS       =
+
+# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be
+# searched for input files to be used with the \include or \dontinclude
+# commands irrespective of the value of the RECURSIVE tag.
+# Possible values are YES and NO. If left blank NO is used.
+
+EXAMPLE_RECURSIVE      = NO
+
+# The IMAGE_PATH tag can be used to specify one or more files or
+# directories that contain image that are included in the documentation (see
+# the \image command).
+
+IMAGE_PATH             =
+
+# The INPUT_FILTER tag can be used to specify a program that doxygen should
+# invoke to filter for each input file. Doxygen will invoke the filter program
+# by executing (via popen()) the command <filter> <input-file>, where <filter>
+# is the value of the INPUT_FILTER tag, and <input-file> is the name of an
+# input file. Doxygen will then use the output that the filter program writes
+# to standard output.
+# If FILTER_PATTERNS is specified, this tag will be
+# ignored.
+
+INPUT_FILTER           =
+
+# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern
+# basis.
+# Doxygen will compare the file name with each pattern and apply the
+# filter if there is a match.
+# The filters are a list of the form:
+# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further
+# info on how filters are used. If FILTER_PATTERNS is empty or if
+# non of the patterns match the file name, INPUT_FILTER is applied.
+
+FILTER_PATTERNS        =
+
+# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using
+# INPUT_FILTER) will be used to filter the input files when producing source
+# files to browse (i.e. when SOURCE_BROWSER is set to YES).
+
+FILTER_SOURCE_FILES    = NO
+
+# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file
+# pattern. A pattern will override the setting for FILTER_PATTERN (if any)
+# and it is also possible to disable source filtering for a specific pattern
+# using *.ext= (so without naming a filter). This option only has effect when
+# FILTER_SOURCE_FILES is enabled.
+
+FILTER_SOURCE_PATTERNS =
+
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+
+# If the SOURCE_BROWSER tag is set to YES then a list of source files will
+# be generated. Documented entities will be cross-referenced with these sources.
+# Note: To get rid of all source code in the generated output, make sure also
+# VERBATIM_HEADERS is set to NO.
+
+SOURCE_BROWSER         = YES
+
+# Setting the INLINE_SOURCES tag to YES will include the body
+# of functions and classes directly in the documentation.
+
+INLINE_SOURCES         = NO
+
+# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct
+# doxygen to hide any special comment blocks from generated source code
+# fragments. Normal C and C++ comments will always remain visible.
+
+STRIP_CODE_COMMENTS    = YES
+
+# If the REFERENCED_BY_RELATION tag is set to YES
+# then for each documented function all documented
+# functions referencing it will be listed.
+
+REFERENCED_BY_RELATION = NO
+
+# If the REFERENCES_RELATION tag is set to YES
+# then for each documented function all documented entities
+# called/used by that function will be listed.
+
+REFERENCES_RELATION    = NO
+
+# If the REFERENCES_LINK_SOURCE tag is set to YES (the default)
+# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from
+# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will
+# link to the source code.
+# Otherwise they will link to the documentation.
+
+REFERENCES_LINK_SOURCE = YES
+
+# If the USE_HTAGS tag is set to YES then the references to source code
+# will point to the HTML generated by the htags(1) tool instead of doxygen
+# built-in source browser. The htags tool is part of GNU's global source
+# tagging system (see http://www.gnu.org/software/global/global.html). You
+# will need version 4.8.6 or higher.
+
+USE_HTAGS              = NO
+
+# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen
+# will generate a verbatim copy of the header file for each class for
+# which an include is specified. Set to NO to disable this.
+
+VERBATIM_HEADERS       = YES
+
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+
+# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index
+# of all compounds will be generated. Enable this if the project
+# contains a lot of classes, structs, unions or interfaces.
+
+ALPHABETICAL_INDEX     = NO
+
+# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then
+# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns
+# in which this list will be split (can be a number in the range [1..20])
+
+COLS_IN_ALPHA_INDEX    = 5
+
+# In case all classes in a project start with a common prefix, all
+# classes will be put under the same header in the alphabetical index.
+# The IGNORE_PREFIX tag can be used to specify one or more prefixes that
+# should be ignored while generating the index headers.
+
+IGNORE_PREFIX          =
+
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_HTML tag is set to YES (the default) Doxygen will
+# generate HTML output.
+
+GENERATE_HTML          = YES
+
+# The HTML_OUTPUT tag is used to specify where the HTML docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `html' will be used as the default path.
+
+HTML_OUTPUT            = html
+
+# The HTML_FILE_EXTENSION tag can be used to specify the file extension for
+# each generated HTML page (for example: .htm,.php,.asp). If it is left blank
+# doxygen will generate files with .html extension.
+
+HTML_FILE_EXTENSION    = .html
+
+# The HTML_HEADER tag can be used to specify a personal HTML header for
+# each generated HTML page. If it is left blank doxygen will generate a
+# standard header. Note that when using a custom header you are responsible
+# for the proper inclusion of any scripts and style sheets that doxygen
+# needs, which is dependent on the configuration options used.
+# It is adviced to generate a default header using "doxygen -w html
+# header.html footer.html stylesheet.css YourConfigFile" and then modify
+# that header. Note that the header is subject to change so you typically
+# have to redo this when upgrading to a newer version of doxygen or when changing the value of configuration settings such as GENERATE_TREEVIEW!
+
+HTML_HEADER            =
+
+# The HTML_FOOTER tag can be used to specify a personal HTML footer for
+# each generated HTML page. If it is left blank doxygen will generate a
+# standard footer.
+
+HTML_FOOTER            =
+
+# The HTML_STYLESHEET tag can be used to specify a user-defined cascading
+# style sheet that is used by each HTML page. It can be used to
+# fine-tune the look of the HTML output. If the tag is left blank doxygen
+# will generate a default style sheet. Note that doxygen will try to copy
+# the style sheet file to the HTML output directory, so don't put your own
+# stylesheet in the HTML output directory as well, or it will be erased!
+
+HTML_STYLESHEET        =
+
+# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or
+# other source files which should be copied to the HTML output directory. Note
+# that these files will be copied to the base HTML output directory. Use the
+# $relpath$ marker in the HTML_HEADER and/or HTML_FOOTER files to load these
+# files. In the HTML_STYLESHEET file, use the file name only. Also note that
+# the files will be copied as-is; there are no commands or markers available.
+
+HTML_EXTRA_FILES       =
+
+# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output.
+# Doxygen will adjust the colors in the stylesheet and background images
+# according to this color. Hue is specified as an angle on a colorwheel,
+# see http://en.wikipedia.org/wiki/Hue for more information.
+# For instance the value 0 represents red, 60 is yellow, 120 is green,
+# 180 is cyan, 240 is blue, 300 purple, and 360 is red again.
+# The allowed range is 0 to 359.
+
+HTML_COLORSTYLE_HUE    = 220
+
+# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of
+# the colors in the HTML output. For a value of 0 the output will use
+# grayscales only. A value of 255 will produce the most vivid colors.
+
+HTML_COLORSTYLE_SAT    = 100
+
+# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to
+# the luminance component of the colors in the HTML output. Values below
+# 100 gradually make the output lighter, whereas values above 100 make
+# the output darker. The value divided by 100 is the actual gamma applied,
+# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2,
+# and 100 does not change the gamma.
+
+HTML_COLORSTYLE_GAMMA  = 80
+
+# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML
+# page will contain the date and time when the page was generated. Setting
+# this to NO can help when comparing the output of multiple runs.
+
+HTML_TIMESTAMP         = YES
+
+# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes,
+# files or namespaces will be aligned in HTML using tables. If set to
+# NO a bullet list will be used.
+
+HTML_ALIGN_MEMBERS     = YES
+
+# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML
+# documentation will contain sections that can be hidden and shown after the
+# page has loaded. For this to work a browser that supports
+# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox
+# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari).
+
+HTML_DYNAMIC_SECTIONS  = NO
+
+# If the GENERATE_DOCSET tag is set to YES, additional index files
+# will be generated that can be used as input for Apple's Xcode 3
+# integrated development environment, introduced with OSX 10.5 (Leopard).
+# To create a documentation set, doxygen will generate a Makefile in the
+# HTML output directory. Running make will produce the docset in that
+# directory and running "make install" will install the docset in
+# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find
+# it at startup.
+# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html
+# for more information.
+
+GENERATE_DOCSET        = NO
+
+# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the
+# feed. A documentation feed provides an umbrella under which multiple
+# documentation sets from a single provider (such as a company or product suite)
+# can be grouped.
+
+DOCSET_FEEDNAME        = "Doxygen generated docs"
+
+# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that
+# should uniquely identify the documentation set bundle. This should be a
+# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen
+# will append .docset to the name.
+
+DOCSET_BUNDLE_ID       = org.doxygen.Project
+
+# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify
+# the documentation publisher. This should be a reverse domain-name style
+# string, e.g. com.mycompany.MyDocSet.documentation.
+
+DOCSET_PUBLISHER_ID    = org.doxygen.Publisher
+
+# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher.
+
+DOCSET_PUBLISHER_NAME  = Publisher
+
+# If the GENERATE_HTMLHELP tag is set to YES, additional index files
+# will be generated that can be used as input for tools like the
+# Microsoft HTML help workshop to generate a compiled HTML help file (.chm)
+# of the generated HTML documentation.
+
+GENERATE_HTMLHELP      = NO
+
+# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can
+# be used to specify the file name of the resulting .chm file. You
+# can add a path in front of the file if the result should not be
+# written to the html output directory.
+
+CHM_FILE               =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can
+# be used to specify the location (absolute path including file name) of
+# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run
+# the HTML help compiler on the generated index.hhp.
+
+HHC_LOCATION           =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag
+# controls if a separate .chi index file is generated (YES) or that
+# it should be included in the master .chm file (NO).
+
+GENERATE_CHI           = NO
+
+# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING
+# is used to encode HtmlHelp index (hhk), content (hhc) and project file
+# content.
+
+CHM_INDEX_ENCODING     =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag
+# controls whether a binary table of contents is generated (YES) or a
+# normal table of contents (NO) in the .chm file.
+
+BINARY_TOC             = NO
+
+# The TOC_EXPAND flag can be set to YES to add extra items for group members
+# to the contents of the HTML help documentation and to the tree view.
+
+TOC_EXPAND             = NO
+
+# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and
+# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated
+# that can be used as input for Qt's qhelpgenerator to generate a
+# Qt Compressed Help (.qch) of the generated HTML documentation.
+
+GENERATE_QHP           = NO
+
+# If the QHG_LOCATION tag is specified, the QCH_FILE tag can
+# be used to specify the file name of the resulting .qch file.
+# The path specified is relative to the HTML output folder.
+
+QCH_FILE               =
+
+# The QHP_NAMESPACE tag specifies the namespace to use when generating
+# Qt Help Project output. For more information please see
+# http://doc.trolltech.com/qthelpproject.html#namespace
+
+QHP_NAMESPACE          = org.doxygen.Project
+
+# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating
+# Qt Help Project output. For more information please see
+# http://doc.trolltech.com/qthelpproject.html#virtual-folders
+
+QHP_VIRTUAL_FOLDER     = doc
+
+# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to
+# add. For more information please see
+# http://doc.trolltech.com/qthelpproject.html#custom-filters
+
+QHP_CUST_FILTER_NAME   =
+
+# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the
+# custom filter to add. For more information please see
+# <a href="http://doc.trolltech.com/qthelpproject.html#custom-filters">
+# Qt Help Project / Custom Filters</a>.
+
+QHP_CUST_FILTER_ATTRS  =
+
+# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this
+# project's
+# filter section matches.
+# <a href="http://doc.trolltech.com/qthelpproject.html#filter-attributes">
+# Qt Help Project / Filter Attributes</a>.
+
+QHP_SECT_FILTER_ATTRS  =
+
+# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can
+# be used to specify the location of Qt's qhelpgenerator.
+# If non-empty doxygen will try to run qhelpgenerator on the generated
+# .qhp file.
+
+QHG_LOCATION           =
+
+# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files
+#  will be generated, which together with the HTML files, form an Eclipse help
+# plugin. To install this plugin and make it available under the help contents
+# menu in Eclipse, the contents of the directory containing the HTML and XML
+# files needs to be copied into the plugins directory of eclipse. The name of
+# the directory within the plugins directory should be the same as
+# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before
+# the help appears.
+
+GENERATE_ECLIPSEHELP   = NO
+
+# A unique identifier for the eclipse help plugin. When installing the plugin
+# the directory name containing the HTML and XML files should also have
+# this name.
+
+ECLIPSE_DOC_ID         = org.doxygen.Project
+
+# The DISABLE_INDEX tag can be used to turn on/off the condensed index at
+# top of each HTML page. The value NO (the default) enables the index and
+# the value YES disables it.
+
+DISABLE_INDEX          = NO
+
+# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values
+# (range [0,1..20]) that doxygen will group on one line in the generated HTML
+# documentation. Note that a value of 0 will completely suppress the enum
+# values from appearing in the overview section.
+
+ENUM_VALUES_PER_LINE   = 4
+
+# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index
+# structure should be generated to display hierarchical information.
+# If the tag value is set to YES, a side panel will be generated
+# containing a tree-like index structure (just like the one that
+# is generated for HTML Help). For this to work a browser that supports
+# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser).
+# Windows users are probably better off using the HTML help feature.
+
+GENERATE_TREEVIEW      = NO
+
+# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories,
+# and Class Hierarchy pages using a tree view instead of an ordered list.
+
+USE_INLINE_TREES       = NO
+
+# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be
+# used to set the initial width (in pixels) of the frame in which the tree
+# is shown.
+
+TREEVIEW_WIDTH         = 250
+
+# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open
+# links to external symbols imported via tag files in a separate window.
+
+EXT_LINKS_IN_WINDOW    = NO
+
+# Use this tag to change the font size of Latex formulas included
+# as images in the HTML documentation. The default is 10. Note that
+# when you change the font size after a successful doxygen run you need
+# to manually remove any form_*.png images from the HTML output directory
+# to force them to be regenerated.
+
+FORMULA_FONTSIZE       = 10
+
+# Use the FORMULA_TRANPARENT tag to determine whether or not the images
+# generated for formulas are transparent PNGs. Transparent PNGs are
+# not supported properly for IE 6.0, but are supported on all modern browsers.
+# Note that when changing this option you need to delete any form_*.png files
+# in the HTML output before the changes have effect.
+
+FORMULA_TRANSPARENT    = YES
+
+# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax
+# (see http://www.mathjax.org) which uses client side Javascript for the
+# rendering instead of using prerendered bitmaps. Use this if you do not
+# have LaTeX installed or if you want to formulas look prettier in the HTML
+# output. When enabled you also need to install MathJax separately and
+# configure the path to it using the MATHJAX_RELPATH option.
+
+USE_MATHJAX            = NO
+
+# When MathJax is enabled you need to specify the location relative to the
+# HTML output directory using the MATHJAX_RELPATH option. The destination
+# directory should contain the MathJax.js script. For instance, if the mathjax
+# directory is located at the same level as the HTML output directory, then
+# MATHJAX_RELPATH should be ../mathjax. The default value points to the
+# mathjax.org site, so you can quickly see the result without installing
+# MathJax, but it is strongly recommended to install a local copy of MathJax
+# before deployment.
+
+MATHJAX_RELPATH        = http://www.mathjax.org/mathjax
+
+# When the SEARCHENGINE tag is enabled doxygen will generate a search box
+# for the HTML output. The underlying search engine uses javascript
+# and DHTML and should work on any modern browser. Note that when using
+# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets
+# (GENERATE_DOCSET) there is already a search function so this one should
+# typically be disabled. For large projects the javascript based search engine
+# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution.
+
+SEARCHENGINE           = YES
+
+# When the SERVER_BASED_SEARCH tag is enabled the search engine will be
+# implemented using a PHP enabled web server instead of at the web client
+# using Javascript. Doxygen will generate the search PHP script and index
+# file to put on the web server. The advantage of the server
+# based approach is that it scales better to large projects and allows
+# full text search. The disadvantages are that it is more difficult to setup
+# and does not have live searching capabilities.
+
+SERVER_BASED_SEARCH    = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will
+# generate Latex output.
+
+GENERATE_LATEX         = YES
+
+# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `latex' will be used as the default path.
+
+LATEX_OUTPUT           = latex
+
+# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be
+# invoked. If left blank `latex' will be used as the default command name.
+# Note that when enabling USE_PDFLATEX this option is only used for
+# generating bitmaps for formulas in the HTML output, but not in the
+# Makefile that is written to the output directory.
+
+LATEX_CMD_NAME         = latex
+
+# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to
+# generate index for LaTeX. If left blank `makeindex' will be used as the
+# default command name.
+
+MAKEINDEX_CMD_NAME     = makeindex
+
+# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact
+# LaTeX documents. This may be useful for small projects and may help to
+# save some trees in general.
+
+COMPACT_LATEX          = NO
+
+# The PAPER_TYPE tag can be used to set the paper type that is used
+# by the printer. Possible values are: a4, letter, legal and
+# executive. If left blank a4wide will be used.
+
+PAPER_TYPE             = a4wide
+
+# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX
+# packages that should be included in the LaTeX output.
+
+EXTRA_PACKAGES         =
+
+# The LATEX_HEADER tag can be used to specify a personal LaTeX header for
+# the generated latex document. The header should contain everything until
+# the first chapter. If it is left blank doxygen will generate a
+# standard header. Notice: only use this tag if you know what you are doing!
+
+LATEX_HEADER           =
+
+# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for
+# the generated latex document. The footer should contain everything after
+# the last chapter. If it is left blank doxygen will generate a
+# standard footer. Notice: only use this tag if you know what you are doing!
+
+LATEX_FOOTER           =
+
+# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated
+# is prepared for conversion to pdf (using ps2pdf). The pdf file will
+# contain links (just like the HTML output) instead of page references
+# This makes the output suitable for online browsing using a pdf viewer.
+
+PDF_HYPERLINKS         = YES
+
+# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of
+# plain latex in the generated Makefile. Set this option to YES to get a
+# higher quality PDF documentation.
+
+USE_PDFLATEX           = YES
+
+# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode.
+# command to the generated LaTeX files. This will instruct LaTeX to keep
+# running if errors occur, instead of asking the user for help.
+# This option is also used when generating formulas in HTML.
+
+LATEX_BATCHMODE        = NO
+
+# If LATEX_HIDE_INDICES is set to YES then doxygen will not
+# include the index chapters (such as File Index, Compound Index, etc.)
+# in the output.
+
+LATEX_HIDE_INDICES     = NO
+
+# If LATEX_SOURCE_CODE is set to YES then doxygen will include
+# source code with syntax highlighting in the LaTeX output.
+# Note that which sources are shown also depends on other settings
+# such as SOURCE_BROWSER.
+
+LATEX_SOURCE_CODE      = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output
+# The RTF output is optimized for Word 97 and may not look very pretty with
+# other RTF readers or editors.
+
+GENERATE_RTF           = NO
+
+# The RTF_OUTPUT tag is used to specify where the RTF docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `rtf' will be used as the default path.
+
+RTF_OUTPUT             = rtf
+
+# If the COMPACT_RTF tag is set to YES Doxygen generates more compact
+# RTF documents. This may be useful for small projects and may help to
+# save some trees in general.
+
+COMPACT_RTF            = NO
+
+# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated
+# will contain hyperlink fields. The RTF file will
+# contain links (just like the HTML output) instead of page references.
+# This makes the output suitable for online browsing using WORD or other
+# programs which support those fields.
+# Note: wordpad (write) and others do not support links.
+
+RTF_HYPERLINKS         = NO
+
+# Load stylesheet definitions from file. Syntax is similar to doxygen's
+# config file, i.e. a series of assignments. You only have to provide
+# replacements, missing definitions are set to their default value.
+
+RTF_STYLESHEET_FILE    =
+
+# Set optional variables used in the generation of an rtf document.
+# Syntax is similar to doxygen's config file.
+
+RTF_EXTENSIONS_FILE    =
+
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_MAN tag is set to YES (the default) Doxygen will
+# generate man pages
+
+GENERATE_MAN           = NO
+
+# The MAN_OUTPUT tag is used to specify where the man pages will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `man' will be used as the default path.
+
+MAN_OUTPUT             = man
+
+# The MAN_EXTENSION tag determines the extension that is added to
+# the generated man pages (default is the subroutine's section .3)
+
+MAN_EXTENSION          = .3
+
+# If the MAN_LINKS tag is set to YES and Doxygen generates man output,
+# then it will generate one additional man file for each entity
+# documented in the real man page(s). These additional files
+# only source the real man page, but without them the man command
+# would be unable to find the correct page. The default is NO.
+
+MAN_LINKS              = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_XML tag is set to YES Doxygen will
+# generate an XML file that captures the structure of
+# the code including all documentation.
+
+GENERATE_XML           = NO
+
+# The XML_OUTPUT tag is used to specify where the XML pages will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `xml' will be used as the default path.
+
+XML_OUTPUT             = xml
+
+# The XML_SCHEMA tag can be used to specify an XML schema,
+# which can be used by a validating XML parser to check the
+# syntax of the XML files.
+
+XML_SCHEMA             =
+
+# The XML_DTD tag can be used to specify an XML DTD,
+# which can be used by a validating XML parser to check the
+# syntax of the XML files.
+
+XML_DTD                =
+
+# If the XML_PROGRAMLISTING tag is set to YES Doxygen will
+# dump the program listings (including syntax highlighting
+# and cross-referencing information) to the XML output. Note that
+# enabling this will significantly increase the size of the XML output.
+
+XML_PROGRAMLISTING     = YES
+
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will
+# generate an AutoGen Definitions (see autogen.sf.net) file
+# that captures the structure of the code including all
+# documentation. Note that this feature is still experimental
+# and incomplete at the moment.
+
+GENERATE_AUTOGEN_DEF   = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_PERLMOD tag is set to YES Doxygen will
+# generate a Perl module file that captures the structure of
+# the code including all documentation. Note that this
+# feature is still experimental and incomplete at the
+# moment.
+
+GENERATE_PERLMOD       = NO
+
+# If the PERLMOD_LATEX tag is set to YES Doxygen will generate
+# the necessary Makefile rules, Perl scripts and LaTeX code to be able
+# to generate PDF and DVI output from the Perl module output.
+
+PERLMOD_LATEX          = NO
+
+# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be
+# nicely formatted so it can be parsed by a human reader.
+# This is useful
+# if you want to understand what is going on.
+# On the other hand, if this
+# tag is set to NO the size of the Perl module output will be much smaller
+# and Perl will parse it just the same.
+
+PERLMOD_PRETTY         = YES
+
+# The names of the make variables in the generated doxyrules.make file
+# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX.
+# This is useful so different doxyrules.make files included by the same
+# Makefile don't overwrite each other's variables.
+
+PERLMOD_MAKEVAR_PREFIX =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+
+# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will
+# evaluate all C-preprocessor directives found in the sources and include
+# files.
+
+ENABLE_PREPROCESSING   = YES
+
+# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro
+# names in the source code. If set to NO (the default) only conditional
+# compilation will be performed. Macro expansion can be done in a controlled
+# way by setting EXPAND_ONLY_PREDEF to YES.
+
+MACRO_EXPANSION        = NO
+
+# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES
+# then the macro expansion is limited to the macros specified with the
+# PREDEFINED and EXPAND_AS_DEFINED tags.
+
+EXPAND_ONLY_PREDEF     = NO
+
+# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files
+# pointed to by INCLUDE_PATH will be searched when a #include is found.
+
+SEARCH_INCLUDES        = YES
+
+# The INCLUDE_PATH tag can be used to specify one or more directories that
+# contain include files that are not input files but should be processed by
+# the preprocessor.
+
+INCLUDE_PATH           =
+
+# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard
+# patterns (like *.h and *.hpp) to filter out the header-files in the
+# directories. If left blank, the patterns specified with FILE_PATTERNS will
+# be used.
+
+INCLUDE_FILE_PATTERNS  =
+
+# The PREDEFINED tag can be used to specify one or more macro names that
+# are defined before the preprocessor is started (similar to the -D option of
+# gcc). The argument of the tag is a list of macros of the form: name
+# or name=definition (no spaces). If the definition and the = are
+# omitted =1 is assumed. To prevent a macro definition from being
+# undefined via #undef or recursively expanded use the := operator
+# instead of the = operator.
+
+PREDEFINED             =
+
+# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then
+# this tag can be used to specify a list of macro names that should be expanded.
+# The macro definition that is found in the sources will be used.
+# Use the PREDEFINED tag if you want to use a different macro definition that
+# overrules the definition found in the source code.
+
+EXPAND_AS_DEFINED      =
+
+# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then
+# doxygen's preprocessor will remove all references to function-like macros
+# that are alone on a line, have an all uppercase name, and do not end with a
+# semicolon, because these will confuse the parser if not removed.
+
+SKIP_FUNCTION_MACROS   = YES
+
+#---------------------------------------------------------------------------
+# Configuration::additions related to external references
+#---------------------------------------------------------------------------
+
+# The TAGFILES option can be used to specify one or more tagfiles.
+# Optionally an initial location of the external documentation
+# can be added for each tagfile. The format of a tag file without
+# this location is as follows:
+#
+# TAGFILES = file1 file2 ...
+# Adding location for the tag files is done as follows:
+#
+# TAGFILES = file1=loc1 "file2 = loc2" ...
+# where "loc1" and "loc2" can be relative or absolute paths or
+# URLs. If a location is present for each tag, the installdox tool
+# does not have to be run to correct the links.
+# Note that each tag file must have a unique name
+# (where the name does NOT include the path)
+# If a tag file is not located in the directory in which doxygen
+# is run, you must also specify the path to the tagfile here.
+
+TAGFILES               =
+
+# When a file name is specified after GENERATE_TAGFILE, doxygen will create
+# a tag file that is based on the input files it reads.
+
+GENERATE_TAGFILE       =
+
+# If the ALLEXTERNALS tag is set to YES all external classes will be listed
+# in the class index. If set to NO only the inherited external classes
+# will be listed.
+
+ALLEXTERNALS           = NO
+
+# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed
+# in the modules index. If set to NO, only the current project's groups will
+# be listed.
+
+EXTERNAL_GROUPS        = YES
+
+# The PERL_PATH should be the absolute path and name of the perl script
+# interpreter (i.e. the result of `which perl').
+
+PERL_PATH              = /usr/bin/perl
+
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+
+# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will
+# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base
+# or super classes. Setting the tag to NO turns the diagrams off. Note that
+# this option also works with HAVE_DOT disabled, but it is recommended to
+# install and use dot, since it yields more powerful graphs.
+
+CLASS_DIAGRAMS         = YES
+
+# You can define message sequence charts within doxygen comments using the \msc
+# command. Doxygen will then run the mscgen tool (see
+# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the
+# documentation. The MSCGEN_PATH tag allows you to specify the directory where
+# the mscgen tool resides. If left empty the tool is assumed to be found in the
+# default search path.
+
+MSCGEN_PATH            =
+
+# If set to YES, the inheritance and collaboration graphs will hide
+# inheritance and usage relations if the target is undocumented
+# or is not a class.
+
+HIDE_UNDOC_RELATIONS   = YES
+
+# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is
+# available from the path. This tool is part of Graphviz, a graph visualization
+# toolkit from AT&T and Lucent Bell Labs. The other options in this section
+# have no effect if this option is set to NO (the default)
+
+HAVE_DOT               = NO
+
+# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is
+# allowed to run in parallel. When set to 0 (the default) doxygen will
+# base this on the number of processors available in the system. You can set it
+# explicitly to a value larger than 0 to get control over the balance
+# between CPU load and processing speed.
+
+DOT_NUM_THREADS        = 0
+
+# By default doxygen will write a font called Helvetica to the output
+# directory and reference it in all dot files that doxygen generates.
+# When you want a differently looking font you can specify the font name
+# using DOT_FONTNAME. You need to make sure dot is able to find the font,
+# which can be done by putting it in a standard location or by setting the
+# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory
+# containing the font.
+
+DOT_FONTNAME           = FreeSans
+
+# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs.
+# The default size is 10pt.
+
+DOT_FONTSIZE           = 10
+
+# By default doxygen will tell dot to use the output directory to look for the
+# FreeSans.ttf font (which doxygen will put there itself). If you specify a
+# different font using DOT_FONTNAME you can set the path where dot
+# can find it using this tag.
+
+DOT_FONTPATH           =
+
+# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen
+# will generate a graph for each documented class showing the direct and
+# indirect inheritance relations. Setting this tag to YES will force the
+# the CLASS_DIAGRAMS tag to NO.
+
+CLASS_GRAPH            = YES
+
+# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen
+# will generate a graph for each documented class showing the direct and
+# indirect implementation dependencies (inheritance, containment, and
+# class references variables) of the class with other documented classes.
+
+COLLABORATION_GRAPH    = YES
+
+# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen
+# will generate a graph for groups, showing the direct groups dependencies
+
+GROUP_GRAPHS           = YES
+
+# If the UML_LOOK tag is set to YES doxygen will generate inheritance and
+# collaboration diagrams in a style similar to the OMG's Unified Modeling
+# Language.
+### TODO ###
+
+UML_LOOK               = YES
+
+# If set to YES, the inheritance and collaboration graphs will show the
+# relations between templates and their instances.
+
+TEMPLATE_RELATIONS     = NO
+
+# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT
+# tags are set to YES then doxygen will generate a graph for each documented
+# file showing the direct and indirect include dependencies of the file with
+# other documented files.
+
+INCLUDE_GRAPH          = YES
+
+# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and
+# HAVE_DOT tags are set to YES then doxygen will generate a graph for each
+# documented header file showing the documented files that directly or
+# indirectly include this file.
+
+INCLUDED_BY_GRAPH      = YES
+
+# If the CALL_GRAPH and HAVE_DOT options are set to YES then
+# doxygen will generate a call dependency graph for every global function
+# or class method. Note that enabling this option will significantly increase
+# the time of a run. So in most cases it will be better to enable call graphs
+# for selected functions only using the \callgraph command.
+
+CALL_GRAPH             = NO
+
+# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then
+# doxygen will generate a caller dependency graph for every global function
+# or class method. Note that enabling this option will significantly increase
+# the time of a run. So in most cases it will be better to enable caller
+# graphs for selected functions only using the \callergraph command.
+
+CALLER_GRAPH           = NO
+
+# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen
+# will generate a graphical hierarchy of all classes instead of a textual one.
+
+GRAPHICAL_HIERARCHY    = YES
+
+# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES
+# then doxygen will show the dependencies a directory has on other directories
+# in a graphical way. The dependency relations are determined by the #include
+# relations between the files in the directories.
+
+DIRECTORY_GRAPH        = YES
+
+# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images
+# generated by dot. Possible values are svg, png, jpg, or gif.
+# If left blank png will be used.
+
+DOT_IMAGE_FORMAT       = png
+
+# The tag DOT_PATH can be used to specify the path where the dot tool can be
+# found. If left blank, it is assumed the dot tool can be found in the path.
+
+DOT_PATH               =
+
+# The DOTFILE_DIRS tag can be used to specify one or more directories that
+# contain dot files that are included in the documentation (see the
+# \dotfile command).
+
+DOTFILE_DIRS           =
+
+# The MSCFILE_DIRS tag can be used to specify one or more directories that
+# contain msc files that are included in the documentation (see the
+# \mscfile command).
+
+MSCFILE_DIRS           =
+
+# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of
+# nodes that will be shown in the graph. If the number of nodes in a graph
+# becomes larger than this value, doxygen will truncate the graph, which is
+# visualized by representing a node as a red box. Note that doxygen if the
+# number of direct children of the root node in a graph is already larger than
+# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note
+# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.
+
+DOT_GRAPH_MAX_NODES    = 50
+
+# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the
+# graphs generated by dot. A depth value of 3 means that only nodes reachable
+# from the root by following a path via at most 3 edges will be shown. Nodes
+# that lay further from the root node will be omitted. Note that setting this
+# option to 1 or 2 may greatly reduce the computation time needed for large
+# code bases. Also note that the size of a graph can be further restricted by
+# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction.
+
+MAX_DOT_GRAPH_DEPTH    = 0
+
+# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent
+# background. This is disabled by default, because dot on Windows does not
+# seem to support this out of the box. Warning: Depending on the platform used,
+# enabling this option may lead to badly anti-aliased labels on the edges of
+# a graph (i.e. they become hard to read).
+
+DOT_TRANSPARENT        = NO
+
+# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output
+# files in one run (i.e. multiple -o and -T options on the command line). This
+# makes dot run faster, but since only newer versions of dot (>1.8.10)
+# support this, this feature is disabled by default.
+
+DOT_MULTI_TARGETS      = NO
+
+# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will
+# generate a legend page explaining the meaning of the various boxes and
+# arrows in the dot generated graphs.
+
+GENERATE_LEGEND        = YES
+
+# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will
+# remove the intermediate dot files that are used to generate
+# the various graphs.
+
+DOT_CLEANUP            = YES
diff --git a/src/ppe/hwp/core/p9_hcd_core_poweron.C b/src/ppe/hwp/core/p9_hcd_core_poweron.C
index e215c27..ad47eb2 100644
--- a/src/ppe/hwp/core/p9_hcd_core_poweron.C
+++ b/src/ppe/hwp/core/p9_hcd_core_poweron.C
@@ -26,25 +26,26 @@
 /// @file  p9_hcd_core_poweron.C
 /// @brief Core Chiplet Power-on
 ///
-/// *HWP HWP Owner   : David Du      <daviddu@us.ibm.com>
-/// *HWP FW Owner    : Reshmi Nair   <resnair5@in.ibm.com>
-/// *HWP Team        : PM
-/// *HWP Consumed by : SBE:CME
-/// *HWP Level       : 1
-///
-/// Procedure Summary:
-///   1.Command the core PFET controller to power-on, via putscom to CPPM
-///     -
-///   2.Check for valid power on completion, via getscom from CPPM
-///     Polled Timeout:  100us
-///
+// *HWP HWP Owner   : David Young          <davidy@us.ibm.com>
+// *HWP FW Owner    : Sangeetha T S     <sangeet2@in.ibm.com>
+// *HWP Team        : PM
+// *HWP Consumed by : SBE:CME
+// *HWP Level       : 2
+//
+// Procedure Summary:
+//   1.Command the core PFET controller to power-on, via putscom to CPPM
+//   2.Check for valid power on completion, via getscom from CPPM
+//     Polled Timeout:  100us
+//
 
 //-----------------------------------------------------------------------------
 // Includes
 //-----------------------------------------------------------------------------
 #include <fapi2.H>
-//#include <common_scom_addresses.H>
+#if 0
+#include <common_scom_addresses.H>
 //will be replaced with real scom address header file
+#endif
 #include "p9_hcd_core_poweron.H"
 
 //-----------------------------------------------------------------------------
@@ -55,30 +56,14 @@
 // Procedure: Core Chiplet Power-on
 //-----------------------------------------------------------------------------
 
-extern "C"
-{
+#define FAPI_CLEANUP() fapi_try_exit:
+#define FAPI_GOTO_EXIT() goto fapi_try_exit;
 
 fapi2::ReturnCode
 p9_hcd_core_poweron(
-    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target,
-    const uint32_t i_operation)
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
 {
-
-#if 0
-
-    fapi2::buffer<uint64_t> data;
-
-    return fapi2::FAPI2_RC_SUCCESS;
-
-    FAPI_CLEANUP();
-    return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA;
-
-#endif
-
-    return fapi2::FAPI2_RC_SUCCESS;
-
+    fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS;
+    FAPI_EXEC_HWP(l_rc, p9_common_poweronoff, i_target, p9power::POWER_ON_VDD);
+    return l_rc;
 } // Procedure
-
-
-} // extern C
-
diff --git a/src/ppe/hwp/core/p9_hcd_core_poweron.H b/src/ppe/hwp/core/p9_hcd_core_poweron.H
index 970d1e4..6e1fa57 100644
--- a/src/ppe/hwp/core/p9_hcd_core_poweron.H
+++ b/src/ppe/hwp/core/p9_hcd_core_poweron.H
@@ -26,27 +26,26 @@
 /// @file  p9_hcd_core_poweron.H
 /// @brief Core Chiplet Power-on
 ///
-/// *HWP HWP Owner   : David Du      <daviddu@us.ibm.com>
-/// *HWP FW Owner    : Reshmi Nair   <resnair5@in.ibm.com>
-/// *HWP Team        : PM
-/// *HWP Consumed by : SBE:CME
-/// *HWP Level       : 1
-///
+// *HWP HWP Owner   : David Young      <daviddu@us.ibm.com>
+// *HWP FW Owner    : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team        : PM
+// *HWP Consumed by : SBE:CME
+// *HWP Level       : 2
+//
 
 
 #ifndef __P9_HCD_CORE_POWERON_H__
 #define __P9_HCD_CORE_POWERON_H__
 
-extern "C"
-{
+#include "p9_common_poweronoff.H"
 
 /// @typedef p9_hcd_core_poweron_FP_t
 /// function pointer typedef definition for HWP call support
 typedef fapi2::ReturnCode (*p9_hcd_core_poweron_FP_t) (
-    const fapi2::Target<fapi2::TARGET_TYPE_CORE>&,
-    const uint32_t);
-
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>&);
 
+extern "C"
+{
 /// @brief Core Chiplet Power-on
 ///
 /// @param [in] i_target    TARGET_TYPE_CORE target
@@ -55,13 +54,9 @@ typedef fapi2::ReturnCode (*p9_hcd_core_poweron_FP_t) (
 /// @attr
 /// @attritem ATTR_PFET_*
 ///
-/// @retval FAPI_RC_SUCCESS
+/// @retval FAPI2_RC_SUCCESS if success, else error code
 fapi2::ReturnCode
 p9_hcd_core_poweron(
-    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target,
-    const uint32_t i_operation);
-
-
-} // extern C
-
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target);
+}
 #endif  // __P9_HCD_CORE_POWERON_H__
diff --git a/src/ppe/hwp/core/wrapper/proc_core_poweron_wrap.C b/src/ppe/hwp/core/wrapper/proc_core_poweron_wrap.C
new file mode 100644
index 0000000..98d32b5
--- /dev/null
+++ b/src/ppe/hwp/core/wrapper/proc_core_poweron_wrap.C
@@ -0,0 +1,248 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/core/wrapper/proc_core_poweron_wrap.C $           */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// ----------------------------------------------------------------------
+// Includes / eCMD Includes
+// ----------------------------------------------------------------------
+#include <prcdUtils.H>
+
+#include <croClientCapi.H>
+#include <ecmdClientCapi.H>
+#include <ecmdUtils.H>
+#include <ecmdSharedUtils.H>
+#include <fapi2.H>
+#include <fapi2ClientCapi.H>
+#include <fapi2SharedUtils.H>
+
+#include <string>
+#include <sstream>
+
+#include <p9_hcd_core_poweron.H>
+
+
+// ----------------------------------------------------------------------
+// Function definitions
+// ----------------------------------------------------------------------
+
+// display help message
+void help()
+{
+    // procedure constants
+    const std::string PROCEDURE = "p9_hcd_core_poweron_wrap";
+    const std::string REVISION  = "$Revision: 1.1 $";
+    // build help message
+    char outstr[200];
+    snprintf(outstr, sizeof(outstr), "\nThis is the help text for the procedure %s (%s)\n", PROCEDURE.c_str(), REVISION.c_str());
+    ecmdOutput(outstr);
+    snprintf(outstr, sizeof(outstr), "Syntax: %s\n", PROCEDURE.c_str());
+    ecmdOutput(outstr);
+    ecmdOutput("        [-h] [-k#] [-n#] [-s#] [-p#] [-verif]\n");
+    ecmdOutput("\n");
+    ecmdOutput("Additional options:\n");
+    ecmdOutput("      -h                           This help\n");
+    ecmdOutput("\n");
+}
+
+
+// main function
+int main(int argc, char *argv[])
+{
+    // procedure constants
+    const std::string PROCEDURE = "p9_hcd_core_poweron_wrap";
+    const std::string REVISION  = "$Revision: 1.1 $";
+
+    // from prcdUtils
+    extern bool GLOBAL_SIM_MODE;
+    extern bool GLOBAL_VERIF_MODE;
+
+    // flow/control variables
+    uint32_t rc = ECMD_SUCCESS;
+    ecmdDllInfo DLLINFO;
+    ecmdLooperData looper;
+    ecmdChipTarget target;
+    bool valid_pos_found = false;
+    char outstr[200];
+
+    fapi2::ReturnCode rc_fapi(fapi2::FAPI2_RC_SUCCESS);
+
+
+    //-----------------------------------------------------------------------------------------
+    // load and initialize the eCMD Dll
+    // if left NULL, which DLL to load is determined by the ECMD_DLL_FILE environment variable
+    // if set to a specific value, the specified DLL will be loaded
+    //-----------------------------------------------------------------------------------------
+    rc = ecmdLoadDll("");
+    if (rc) return rc;
+
+    //-----------------------------------------------------------------------------------------
+    // This is needed if you're running a FAPI procedure from this eCMD procedure
+    //-----------------------------------------------------------------------------------------
+
+    // initalize FAPI2 extension
+    rc = fapi2InitExtension();
+    if (rc)
+    {
+        ecmdOutputError("Error initializing FAPI2 extension!\n");
+        return rc;
+    }
+
+
+
+    // establish if this is a simulation run or not
+    rc = ecmdQueryDllInfo(DLLINFO);
+    if (rc)
+    {
+        ecmdUnloadDll();
+        return rc;
+    }
+    if (DLLINFO.dllEnv == ECMD_DLL_ENV_SIM)
+    {
+        GLOBAL_SIM_MODE = true;
+    }
+
+    //-------------------------------------------------------------------------------------------------
+    // Parse out user options (excluding -pX, -cX, -coe, -debug, etc
+    // E.G., ecmdRunHwp.x86 -testmode
+    //-------------------------------------------------------------------------------------------------
+    if (ecmdParseOption(&argc, &argv, "-h"))
+    {
+        help();
+        ecmdUnloadDll();
+        return rc;
+    }
+
+
+    // run procedure in sim verification mode
+    if (ecmdParseOption(&argc, &argv, "-verif"))
+    {
+        GLOBAL_VERIF_MODE = true;
+    }
+
+    //-------------------------------------------------------------------------------------------------
+    // Parse out common eCMD args like -p0, -c0, -coe, etc..
+    // Any found args will be removed from arg list upon return
+    //-------------------------------------------------------------------------------------------------
+    rc = ecmdCommandArgs(&argc, &argv);
+    if (rc)
+    {
+        ecmdUnloadDll();
+        return rc;
+    }
+
+    // unsupported arguments left over?
+    if (argc != 1)
+    {
+        ecmdOutputError("Unknown/unsupported arguments specified!\n");
+        help();
+        ecmdUnloadDll();
+        return ECMD_INVALID_ARGS;
+    }
+
+    //-------------------------------------------------------------------------------------------------
+    // Let's always print the dll info to the screen, unless in quiet mode
+    //-------------------------------------------------------------------------------------------------
+
+    if (!ecmdGetGlobalVar(ECMD_GLOBALVAR_QUIETMODE))
+    {
+        // print informational message
+        snprintf(outstr, sizeof(outstr), "Procedure %s: %s\n", PROCEDURE.c_str(), REVISION.c_str());
+        ecmdOutput(outstr);
+
+        // always print the DLL info to the screen, unless in quiet mode
+        rc = ecmdDisplayDllInfo();
+        if (rc)
+        {
+            return rc;
+        }
+    }
+
+    //-------------------------------------------------------------------------------------------------
+    // Loop over all all pu chips
+    //-------------------------------------------------------------------------------------------------
+    target.chipType      = "pu";
+    target.chipTypeState = ECMD_TARGET_FIELD_VALID;
+    target.cageState     = ECMD_TARGET_FIELD_WILDCARD;
+    target.nodeState     = ECMD_TARGET_FIELD_WILDCARD;
+    target.slotState     = ECMD_TARGET_FIELD_WILDCARD;
+    target.posState      = ECMD_TARGET_FIELD_WILDCARD;
+    target.coreState     = ECMD_TARGET_FIELD_UNUSED;
+    target.threadState   = ECMD_TARGET_FIELD_UNUSED;
+
+    rc = ecmdConfigLooperInit(target, ECMD_SELECTED_TARGETS_LOOP, looper);
+    if (rc)
+    {
+        ecmdOutputError("Error initializing proc chip looper!\n");
+        ecmdUnloadDll();
+        return rc;
+    }
+    while (ecmdConfigLooperNext(target, looper))
+    {
+        if (!ecmdGetGlobalVar(ECMD_GLOBALVAR_QUIETMODE))
+        {
+            snprintf(outstr, sizeof(outstr),
+                     "Going to call %s on proc k%d:n%d:s%d:p%02d\n",
+                     PROCEDURE.c_str(), target.cage, target.node,
+                                        target.slot, target.pos);
+            ecmdOutput(outstr);
+        }
+
+        // EXAMPLE setting up a fapi2::Target from an ecmdChipTarget
+        fapi2::Target<fapi2::TARGET_TYPE_CORE> fapi_target(&target);
+
+        // invoke FAPI procedure core
+        FAPI_EXEC_HWP(rc_fapi, p9_hcd_core_poweron, fapi_target);
+        rc = (uint64_t) rc_fapi;
+        if (rc)
+        {
+            snprintf(outstr, sizeof(outstr),
+                     "ERROR: %s FAPI call exited with return code = %s 0x%08x \n",
+                     PROCEDURE.c_str(), ecmdParseReturnCode(rc).c_str(), rc);
+            ecmdOutputError(outstr);
+            ecmdUnloadDll();
+            return rc;
+        }
+
+        // mark that valid position has been found
+        valid_pos_found = true;
+    }
+
+    // check that a valid target was found
+    if (rc == ECMD_SUCCESS && !valid_pos_found)
+    {
+        ecmdOutputError("No valid targets found!\n");
+        ecmdUnloadDll();
+        return ECMD_TARGET_NOT_CONFIGURED;
+    }
+
+    prcdInfoMessage("----------------------------------------\n");
+    prcdInfoMessage("      p9_hcd_core_poweron is done\n");
+    prcdInfoMessage("----------------------------------------\n");
+
+    //-----------------------------------------------------------------------------------------------
+    // Unload the eCMD Dll, this should always be the last thing you do
+    //-----------------------------------------------------------------------------------------------
+
+    ecmdUnloadDll();
+    return rc;
+}
diff --git a/src/ppe/hwp/lib/libcommonerrors.mk b/src/ppe/hwp/lib/libcommonerrors.mk
new file mode 100644
index 0000000..31116e9
--- /dev/null
+++ b/src/ppe/hwp/lib/libcommonerrors.mk
@@ -0,0 +1,44 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ppe/hwp/lib/libcommonerrors.mk $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file libcommonerrors.mk
+#
+#  @brief Error XML mk for common library files
+#
+#  @page ChangeLogs Change Logs
+#  @section libcommonerrors.mk
+#  @verbatim
+#
+#
+# @endverbatim
+#
+##########################################################################
+# Error Files
+##########################################################################
+
+LIB_CURR_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+
+# This variable name must not change
+ERROR_XML_FILES += $(LIB_CURR_DIR)/p9_avsbus_lib_errors.xml
+#ERROR_XML_FILES +=  $(LIB_CURR_DIR)/p9_common_pro_epi_log_errors.xml
diff --git a/src/ppe/hwp/lib/p9_avsbus_lib_errors.xml b/src/ppe/hwp/lib/p9_avsbus_lib_errors.xml
new file mode 100644
index 0000000..0981823
--- /dev/null
+++ b/src/ppe/hwp/lib/p9_avsbus_lib_errors.xml
@@ -0,0 +1,56 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/ppe/hwp/lib/p9_avsbus_lib_errors.xml $                    -->
+<!--                                                                        -->
+<!-- OpenPOWER OnChipController Project                                     -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+
+<!-- *HWP HWP Owner: Greg Still <stillgs @us.ibm.com>                       -->
+<!-- *HWP FW Owner: Bilicon Patil <bilpatil@in.ibm.com>                     -->
+<!-- *HWP Team: PM                                                          -->
+<!-- *HWP Level: 1                                                          -->
+<!-- *HWP Consumed by: FSP:HS                                               -->
+
+<!-- Error definitions for p9_avsbus_lib procedure -->
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_PROCPM_AVSBUS_READVOLTAGE_TIMEOUT</rc>
+    <description>
+    A timeout occured reading voltage from an AVSBus interface
+    </description>    
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_PROCPM_AVSBUS_WRITEVOLTAGE_TIMEOUT</rc>
+    <description>
+    A timeout occured writing a voltage to an AVSBus interface
+    </description>    
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_PROCPM_AVSBUS_IDLEFRAME_TIMEOUT</rc>
+    <description>
+    A timeout occured writing an idle from to an AVSBus interface
+    </description>    
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>
diff --git a/src/ppe/hwp/lib/p9_common_poweronoff.C b/src/ppe/hwp/lib/p9_common_poweronoff.C
index cd5e6f8..2d2a975 100644
--- a/src/ppe/hwp/lib/p9_common_poweronoff.C
+++ b/src/ppe/hwp/lib/p9_common_poweronoff.C
@@ -26,46 +26,433 @@
 /// @file  p9_common_poweronoff.C
 /// @brief common procedure for power on/off
 ///
-/// *HWP HWP Owner   : David Du      <daviddu@us.ibm.com>
-/// *HWP FW Owner    : Reshmi Nair   <resnair5@in.ibm.com>
-/// *HWP Team        : PM
-/// *HWP Consumed by : SBE:SGPE:CME
-/// *HWP Level       : 1
-///
-/// Procedure Summary:
-///
+// *HWP HWP Owner   : David Young   <davidy@us.ibm.com>
+// *HWP FW Owner    : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team        : PM
+// *HWP Consumed by : SBE:SGPE:CME
+// *HWP Level       : 2
+//
+// Procedure Summary:
+//
 
 //------------------------------------------------------------------------------
 // Includes
 //------------------------------------------------------------------------------
 #include <fapi2.H>
-//#include <common_scom_addresses.H>
+
+#if 0
+#include <common_scom_addresses.H>
 //will be replaced with real scom address header file
+#endif
 #include "p9_common_poweronoff.H"
 
 //------------------------------------------------------------------------------
 // Constant Definitions:
 //------------------------------------------------------------------------------
+enum { CYCLES_PER_MS = 500000,
+       INST_PER_LOOP = 8,
+       PFET_STATE_LENGTH = 2,
+       VXX_PG_SEL_LEN = 4};
+
+enum pfetRegField { PFET_NOP=0,
+                    PFET_FORCE_VOFF=1,
+                    PFET_NOP_RESERVERD=2,
+                    PFET_FORCE_VON=3};
+
+enum pgStateOffset { PG_STATE_IDLE_OFFSET=0,
+                     PG_STATE_INC_OFFSET=1,
+                     PG_STATE_DEC_OFFSET=2,
+                     PG_STATE_WAIT_OFFSET=3};
+
+
+enum PFCS_Bits { VDD_PFET_FORCE_STATE_BIT=0,
+                 VCS_PFET_FORCE_STATE_BIT=2,
+                 VDD_PFET_VAL_OVERRIDE_BIT=4,
+                 VDD_PFET_SEL_OVERRIDE_BIT=5,
+                 VCS_PFET_VAL_OVERRIDE_BIT=6,
+                 VCS_PFET_SEL_OVERRIDE_BIT=7,
+                 VDD_PFET_REGULATION_FINGER_EN_BIT=8,
+                 VDD_PFET_REGULATION_FINGER_VALUE_BIT=9,
+                 RESERVED1_BIT=10,
+                 VDD_PFET_ENABLE_VALUE_BIT=12,
+                 VDD_PFET_SEL_VALUE_BIT=20,
+                 VCS_PFET_ENABLE_VALUE_BIT=24,
+                 VCS_PFET_SEL_VALUE_BIT=32,
+                 RESERVED2_BIT=36,
+                 VDD_PG_STATE_BIT=42,
+                 VDD_PG_SEL_BIT=46,
+                 VCS_PG_STATE_BIT=50,
+                 VCS_PG_SEL_BIT=54,
+                 RESERVED3_BIT=58
+};
+
+
+enum { VDD_PFETS_ENABLED_SENSE_BIT=0,
+       VDD_PFETS_DISABLED_SENSE_BIT=1,
+       VCS_PFETS_ENABLED_SENSE_BIT=2,
+       VCS_PFETS_DISABLED_SENSE_BIT=3
+};
+
+enum { POWDN_DLY_BIT=0,
+       POWUP_DLY_BIT=4,
+       TP_VDD_PFET_ENABLE_ACTUAL_BIT=16,
+       TP_VCS_PFET_ENABLE_ACTUAL_BIT=24
+};
+
+enum { POWDN_DLY_LENGTH=4,
+       POWUP_DLY_LENGTH=4,
+       TP_VDD_PFET_ENABLE_ACTUAL_LENGTH=8,
+       TP_VCS_PFET_ENABLE_ACTUAL_LENGTH=8};
+
+// i_operation defines
+
+
+#define FAPI_CLEANUP() fapi_try_exit:
+#define FAPI_GOTO_EXIT() goto fapi_try_exit;
 
 //------------------------------------------------------------------------------
 // Procedure:
 //------------------------------------------------------------------------------
 
-extern "C"
-{
-
+#if OR_TARGET_ENABLED  // Cronus may not support
+                       //   fapi2::TARGET_TYPE_EQ|fapi2::TARGET_TYPE_CORE
 fapi2::ReturnCode
 p9_common_poweronoff(
     const fapi2::Target<fapi2::TARGET_TYPE_EQ|
                         fapi2::TARGET_TYPE_CORE>& i_target,
-    int i_operation)
+    const p9power::powerOperation_t i_operation)
+#else
+fapi2::ReturnCode
+p9_common_poweronoff(
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target,
+    const p9power::powerOperation_t i_operation)
+
+#endif
+
+
 {
-    return fapi2::FAPI2_RC_SUCCESS;
+    uint32_t l_loopsPerMs;
 
+    FAPI_INF(">>p9_common_poweronoff: %d",  i_operation);
 
-} // Procedure
+    fapi2::buffer<uint64_t> l_data;
+    fapi2::buffer<uint64_t> l_temp;  // extractToRight seems the require space to write into.
+    ///////////////////////////////////////////////////////////////////////////
+    // lambda functions for poweronoff procedure
+    ///////////////////////////////////////////////////////////////////////////
+    auto pollVddFSMIdle = [&] ()
+    {
+        //   Poll for PFETCNTLSTAT_REG[VDD_PG_STATE] for 0b1000 (FSM idle)
+        //      – Timeout value = 1ms
+        FAPI_DBG("Polling for power gate sequencer state: FSM idle");
+        l_loopsPerMs = CYCLES_PER_MS/INST_PER_LOOP;
+        // Note that the Lamda assumes that l_data already contains the
+        do
+        {
+            FAPI_TRY(fapi2::getScom(i_target, PPM_PFCS, l_data),
+                "getScom failed for address PPM_PFCS"); // poll
+        } while ((l_data.getBit<VDD_PG_STATE_BIT+PG_STATE_IDLE_OFFSET>()
+                  != 0 ) && (--l_loopsPerMs != 0));
+        FAPI_ASSERT((l_loopsPerMs != 0),
+                     fapi2::PMPROC_PFETLIB_TIMEOUT()
+                            .set_ADDRESS(PPM_PFCS),
+                     "VDD FSM idle timeout");
+
+        ///  (Optional) Check PFETCNTLSTAT_REG[VDD_PG_SEL]being 0x8
+        //              (Off encode point)
+#if 0  // this field does not get set yet
+        l_data.extractToRight<VDD_PG_SEL_BIT, VXX_PG_SEL_LEN>(l_temp);
+        FAPI_ASSERT((l_temp == 8),
+                     fapi2::PROCPM_PFET_CODE_BAD_MODE(),
+                     "VDD_PG_SEL != 8: l_temp %0x", l_temp);
+
+#endif
+        // fapi2::current_err will be initialized with FAPI2_RC_SUCCESS
+        FAPI_CLEANUP()
+        return static_cast<fapi2::ReturnCode>(fapi2::current_err);
+    };
+
+    auto pollVcsFSMIdle = [&] ()
+    {
+        //   Poll for PFETCNTLSTAT_REG[VDD_PG_STATE] for 0b1000 (FSM idle)
+        //      – Timeout value = 1ms
+        FAPI_DBG("Polling for power gate sequencer state: FSM idle");
+        l_loopsPerMs = CYCLES_PER_MS/INST_PER_LOOP;
+
+        do
+        {
+            FAPI_TRY(fapi2::getScom(i_target, PPM_PFCS, l_data),
+                    "getScom failed for address PPM_PFCS");  // poll
+            FAPI_DBG("timeout l_loopsPerMs. %x", l_loopsPerMs);
+        } while ((l_data.getBit<VCS_PG_STATE_BIT+PG_STATE_IDLE_OFFSET>()
+                  != 0 ) && (--l_loopsPerMs != 0));
+        FAPI_ASSERT((l_loopsPerMs != 0),
+                     fapi2::PMPROC_PFETLIB_TIMEOUT()
+                            .set_ADDRESS(PPM_PFCS),
+                     "VCS FSM idle timeout");
+
+        //   (Optional) Check PFETCNTLSTAT_REG[VDD_PG_SEL]
+        //              being 0x8 (Off encode point)
+
+
+#if 0  // this field does not get set yet
+        l_data.extractToRight<VCS_PG_SEL_BIT, VXX_PG_SEL_LEN>(l_temp);
+        FAPI_ASSERT((l_temp == 8),
+                     fapi2::PROCPM_PFET_CODE_BAD_MODE(),
+                     "VCS_PG_SEL != 8: l_temp %0x", l_temp);
+
+#endif
+        // fapi2::current_err will be initialized with FAPI2_RC_SUCCESS
+        FAPI_CLEANUP()
+        return static_cast<fapi2::ReturnCode>(fapi2::current_err);
+
+    };
+
+
+    auto powerOnVdd = [&] ()
+    {
+        // Command the cache PFET controller to power-on
+
+        //   Write PFETCNTLSTAT_REG:
+        //     vdd_pfet_force_state = 11 (Force Von)
+        //     vdd_pfet_val_override = 0 (Override disabled)
+        //     vdd_pfet_sel_override = 0 (Override disabled)
+        //     vdd_pfet_enable_regulation_finger = 0
+        //         (Regulation finger controlled by FSM)
+        FAPI_DBG("Force VDD on");
+        FAPI_DBG("Clear VDD PFET stage select and value override bits");
+        l_data.flush<0>().insertFromRight
+               <VDD_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(PFET_FORCE_VON).
+             clearBit<VDD_PFET_VAL_OVERRIDE_BIT>().
+             clearBit<VDD_PFET_SEL_OVERRIDE_BIT>();
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS, l_data),
+                "putScom failed for address PPM_PFCS");
 
+        FAPI_TRY(pollVddFSMIdle());
 
-} // extern C
+        //    Write PFETCNTLSTAT_REG_WCLEAR
+        //      vdd_pfet_force_state = 00 (No Operation);
+        //      all fields set to 1 for WAND
+        //    Use PPM_PFCS_CLR,
+        //      vdd_pfet_force_state = 0b11
+        FAPI_DBG("vdd_pfet_force_state = 00, or Idle");
+        l_data.flush<0>().insertFromRight
+               <VDD_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(~PFET_NOP);
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR, l_data),
+                "putScom failed for address PPM_PFCS_CLR");
 
+        // fapi2::current_err will be initialized with FAPI2_RC_SUCCESS
+        FAPI_CLEANUP()
+        return static_cast<fapi2::ReturnCode>(fapi2::current_err);
 
+    };
+
+    auto powerOnVcs = [&] ()
+    {
+        FAPI_DBG("Force VSS on");
+        FAPI_DBG("Clear VSS PFET stage select and value override bits");
+
+        // Command the PFET controller to power-on
+        //    Write PFETCNTLSTAT_REG_OR with values defined below
+        //      vcs_pfet_force_state = 11 (Force Von)
+        //    Write to PFETCNTLSTAT_REG_CLR
+        //      vcs_pfet_val_override = 0 (Override disabled)
+        //      vcs_pfet_sel_override = 0 (Override disabled)
+        //      vcs_pfet_enable_regulation_finger = 0
+        //          (Regulation finger controlled by FSM)
+        l_data.flush<0>().insertFromRight
+               <VCS_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(PFET_FORCE_VON);
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_OR, l_data),
+                "putScom failed for address PPM_PFCS_OR");
+
+        l_data.flush<0>().
+             setBit<VCS_PFET_VAL_OVERRIDE_BIT>().
+             setBit<VCS_PFET_SEL_OVERRIDE_BIT>();
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR, l_data),
+                "putScom failed for address PPM_PFCS_CLR");
+
+        // Check for valid power on completion
+        //     Polled Timeout:  100us
+        FAPI_TRY(pollVcsFSMIdle());
+
+        //   Write PFETCNTLSTAT_REG_WCLEAR
+        //      vcs_pfet_force_state = 00 (No Operation);
+        //      all fields set to 1 for WAND
+        //   Use PPM_PFCS_CLR,  vdd_pfet_force_state = ~(0b00)
+        FAPI_DBG("vss_pfet_force_state = 00, or Idle");
+        l_data.flush<0>().insertFromRight
+               <VCS_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(~PFET_NOP);
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR, l_data),
+                "putScom failed for address PPM_PFCS_CLR");
+
+        // fapi2::current_err will be initialized with FAPI2_RC_SUCCESS
+        FAPI_CLEANUP()
+        return static_cast<fapi2::ReturnCode>(fapi2::current_err);
+    };
+
+    auto powerOffVdd = [&] ()
+    {
+        // Command the PFET controller to power-off
+        //   Write PFETCNTLSTAT_REG:
+        //     vdd_pfet_force_state = 01 (Force Voff)
+        //     vdd_pfet_val_override = 0 (Override disabled)
+        //     vdd_pfet_sel_override = 0 (Override disabled)
+        //     vdd_pfet_enable_regulation_finger = 0
+        //                   (Regulation finger controlled by FSM)
+        FAPI_DBG("Force VDD off");
+        FAPI_DBG("Clear VDD PFET stage select and value override bits");
+        l_data.flush<0>().insertFromRight
+               <VDD_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(PFET_FORCE_VOFF).
+             clearBit<VDD_PFET_VAL_OVERRIDE_BIT>().
+             clearBit<VDD_PFET_SEL_OVERRIDE_BIT>();
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS, l_data),
+                "putScom failed for address PPM_PFCS");
+
+        FAPI_TRY(pollVddFSMIdle());
+
+        //    Write PFETCNTLSTAT_REG_WCLEAR
+        //      vdd_pfet_force_state = 00 (No Operation);
+        //      all fields set to 1 for WAND
+        //    Use PPM_PFCS_CLR,  vdd_pfet_force_state = 0b11
+        FAPI_DBG("vdd_pfet_force_state = 00, or Idle");
+        l_data.flush<0>().insertFromRight
+               <VDD_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(~PFET_NOP);
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR, l_data),
+                "putScom failed for address PPM_PFCS_CLR");
+
+        // fapi2::current_err will be initialized with FAPI2_RC_SUCCESS
+        FAPI_CLEANUP()
+        return static_cast<fapi2::ReturnCode>(fapi2::current_err);
+    };
+
+    auto powerOffVcs = [&] ()
+    {
+        // Command the PFET controller to power-off
+        FAPI_DBG("Force VSS off");
+        FAPI_DBG("Clear VSS PFET stage select and value override bits");
+
+        //    Write PFETCNTLSTAT_REG_OR with values defined below
+        //      vcs_pfet_force_state = 11 (Force Voff)
+        //    DOC BUG: ?? Write to PFETCNTLSTAT_REG_CLR
+        //      vcs_pfet_val_override = 0 (Override disabled)
+        //      vcs_pfet_sel_override = 0 (Override disabled)
+        //      vcs_pfet_enable_regulation_finger = 0
+        //         (Regulation finger controlled by FSM)
+        l_data.flush<0>().
+             insertFromRight
+               <VCS_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(PFET_FORCE_VOFF);
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_OR, l_data),
+                "putScom failed for address PPM_PFCS_OR");
+
+        l_data.flush<0>().
+             setBit<VCS_PFET_VAL_OVERRIDE_BIT>().
+             setBit<VCS_PFET_SEL_OVERRIDE_BIT>();
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR, l_data),
+                "putScom failed for address PPM_PFCS_CLR");
+
+        FAPI_TRY(pollVcsFSMIdle());
+
+        //   Write PFETCNTLSTAT_REG_WCLEAR
+        //      vcs_pfet_force_state = 00 (No Operation);
+        //          all fields set to 1 for WAND
+        //   Use PPM_PFCS_CLR,  vcs_pfet_force_state = ~(0b00)
+        FAPI_DBG("vcs_pfet_force_state = 00, or Idle");
+        l_data.flush<0>().insertFromRight
+               <VCS_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(~PFET_NOP);
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR, l_data),
+                "putScom failed for address PPM_PFCS_CLR");
+
+        // fapi2::current_err will be initialized with FAPI2_RC_SUCCESS
+        FAPI_CLEANUP()
+        return static_cast<fapi2::ReturnCode>(fapi2::current_err);
+    };
+
+    ///////////////////////////////////////////////////////////////////////////
+    // Initialization code
+    ///////////////////////////////////////////////////////////////////////////
+#if 0  // unneeded for AWAN operation.  Also, fails if delay field is > 8
+   l_data.flush<0>().insertFromRight<POWDN_DLY_BIT, POWDN_DLY_LENGTH>(0x8).
+                      insertFromRight<POWUP_DLY_BIT, POWUP_DLY_LENGTH>(0x8);
+
+    FAPI_TRY(fapi2::putScom(i_target, PPM_PFDLY, l_data),
+            "putScom failed for address PPM_PFDLY");
+#endif
+
+    ///////////////////////////////////////////////////////////////////////////
+    // Procedure code
+    ///////////////////////////////////////////////////////////////////////////
+    switch(i_operation)
+    {
+    case p9power::POWER_ON:  case p9power::POWER_ON_VDD:
+    {
+        // 4.3.8.1 Power-on via Hardware FSM
+
+        // VDD first, VCS second
+
+        // 1)  Read  PFETCNTLSTAT_REG:  check for bits 0:3 being 0b0000
+        l_data.flush<0>().
+             setBit<VCS_PFET_VAL_OVERRIDE_BIT>().
+             setBit<VCS_PFET_SEL_OVERRIDE_BIT>();
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR, l_data),
+                "putScom failed for address PPM_PFCS_CLR");
+
+        FAPI_DBG("Make sure that we are not forcing PFET for VCS or VDD off");
+        FAPI_TRY(fapi2::getScom(i_target, PPM_PFCS, l_data),
+                "getScom failed for address PPM_PFCS");
+        l_data.extractToRight
+                        <VDD_PFET_FORCE_STATE_BIT, 2*PFET_STATE_LENGTH>
+                        (l_temp);
+        FAPI_ASSERT((l_temp == 0),
+                     fapi2::PMPROC_PFETLIB_BAD_SCOM()
+                            .set_ADDRESS(PPM_PFCS),
+                     "PFET_FORCE_STATE not 0");
+
+        // 2) Set bits to program HW to enable VDD PFET, and
+        // 3) Poll state bit until Pfet sequence is complete
+        FAPI_TRY(powerOnVdd());
+
+        // 4) Set bits to program HW to enable VCS PFET, and
+        // 5) Poll state bit until Pfet sequence is complete
+
+        // Note: if (i_target.getType() & fapi2::TARGET_TYPE_EQ) doesn't work.
+        //   Created a  POWER_*_VDD label to delineate Vcs and Vdd
+        if (i_operation == p9power::POWER_ON)
+            FAPI_TRY(powerOnVcs());
+
+    } break;
+    case p9power::POWER_OFF:  case p9power::POWER_OFF_VDD:
+    {
+        // 4.3.8.2 Power-off via Hardware FSM
+        // 1)  Read  PFETCNTLSTAT_REG:  check for bits 0:3 being 0b0000
+        FAPI_DBG("Make sure that we are not forcing PFET for VCS or VDD off");
+        FAPI_TRY(fapi2::getScom(i_target, PPM_PFCS, l_data),
+                "getScom failed for address PPM_PFCS");
+
+        l_data.extractToRight
+                        <VDD_PFET_FORCE_STATE_BIT, 2*PFET_STATE_LENGTH>
+                        (l_temp);
+        FAPI_ASSERT((l_temp == 0),
+                     fapi2::PMPROC_PFETLIB_BAD_SCOM()
+                            .set_ADDRESS(PPM_PFCS),
+                     "PFET_FORCE_STATE not 0");
+
+        // 2) Set bits to program HW to turn off VDD PFET, and
+        // 3) Poll state bit until Pfet sequence is complete
+        FAPI_TRY(powerOffVdd());
+
+        // 4) Set bits to program HW to turn off VCS PFET, and
+        // 5) Poll state bit until Pfet sequence is complete
+
+        // Note: if (i_target.getType() & fapi2::TARGET_TYPE_EQ) doesn't work.
+        //   Created a  POWER_*_VDD label to delineate Vcs and Vdd
+        if (i_operation == p9power::POWER_OFF)
+            FAPI_TRY(powerOffVcs());
+
+    } break;
+    }
+
+    FAPI_INF("<<p9_common_poweronoff");
+    // fapi2::current_err will be initialized with FAPI2_RC_SUCCESS
+    FAPI_CLEANUP()
+    return fapi2::current_err;
+} // Procedure
diff --git a/src/ppe/hwp/lib/p9_common_poweronoff.H b/src/ppe/hwp/lib/p9_common_poweronoff.H
index a5bd036..743866a 100644
--- a/src/ppe/hwp/lib/p9_common_poweronoff.H
+++ b/src/ppe/hwp/lib/p9_common_poweronoff.H
@@ -26,27 +26,73 @@
 /// @file  p9_common_poweronoff.H
 /// @brief common procedure for power on/off
 ///
-/// *HWP HWP Owner   : David Du      <daviddu@us.ibm.com>
-/// *HWP FW Owner    : Reshmi Nair   <resnair5@in.ibm.com>
+/// *HWP HWP Owner   : David Young   <davidy@us.ibm.com>
+/// *HWP FW Owner    : Sangeetha T S  <sangeet2@in.ibm.com>
 /// *HWP Team        : PM
 /// *HWP Consumed by : SBE:SGPE:CME
-/// *HWP Level       : 1
+/// *HWP Level       : 2
 ///
 
 #ifndef __P9_COMMON_POWERONOFF_H__
 #define __P9_COMMON_POWERONOFF_H__
 
-extern "C"
+namespace p9power
+{
+    enum powerOperation_t
+    {
+        POWER_ON      = 0x0,
+        POWER_OFF     = 0xFF,
+        POWER_ON_VDD  = 0x1,
+        POWER_OFF_VDD = 0xFE
+    };
+}
+
+
+// Will be auto-generated by Ben Gass's Figtree file
+// #define PPM_PFCS C_PPM_PFCS_SCOM
+// #define PPM_PFCS_CLR C_PPM_PFCS_SCOM1
+// #define PPM_PFCS_OR C_PPM_PFCS_SCOM2
+
+#define PPM_PFCS 0x100f0118
+#define PPM_PFCS_CLR 0x100f0119
+#define PPM_PFCS_OR 0x100f011a
+
+#define PPM_PFDLY 0x100f011b
+#define PPM_PFSNS 0x100f011c
+#define PPM_PFOFF 0x100f011d
+
+#if 0
+namespace fapi2
 {
+// Will be auto-generated by error XML file
+
+const unsigned  RC_PMPROC_PFETLIB_BAD_DOMAIN = 0;
+const unsigned  RC_PMPROC_PFETLIB_BAD_SCOM = 1;
+const unsigned  RC_PMPROC_PFETLIB_BAD_OP = 2;
+const unsigned  RC_PMPROC_PFETLIB_RAIL_ON = 3;
+const unsigned  RC_PMPROC_PFETLIB_RAIL_OFF = 4;
+const unsigned  RC_PROCPM_PFETLIB_TIMEOUT = 5;
+const unsigned  RC_PROCPM_PFET_CODE_BAD_MODE = 6;
+const unsigned  RC_PROCPM_PFET_GET_ATTR = 7;
+}
+#endif
+#define OR_TARGET_ENABLED 1
 
-/// @typedef p9_common_proweronoff_FP_t
+/// @typedef p9_common_poweronoff_FP_t
 /// function pointer typedef definition for HWP call support
-typedef fapi2::ReturnCode (*p9_common_proweronoff_FP_t) (
+#if OR_TARGET_ENABLED  // Cronus may not support fapi2::TARGET_TYPE_EQ|fapi2::TARGET_TYPE_CORE
+typedef fapi2::ReturnCode (*p9_common_poweronoff_FP_t) (
     const fapi2::Target<fapi2::TARGET_TYPE_EQ|
                         fapi2::TARGET_TYPE_CORE>&,
-    int);
+    const p9power::powerOperation_t i_operation);
+#else
+typedef fapi2::ReturnCode (*p9_common_poweronoff_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>&, const uint32_t);
 
+#endif
 
+extern "C"
+{
 /// @brief common procedure for power on/off
 ///
 /// @param [in] i_target    TARGET_TYPE_EQ|TARGET_TYPE_CORE target
@@ -56,12 +102,18 @@ typedef fapi2::ReturnCode (*p9_common_proweronoff_FP_t) (
 /// @attritem ATTR_PFET_TIMING - EX target, uint32
 ///
 /// @retval FAPI_RC_SUCCESS
+#if OR_TARGET_ENABLED
 fapi2::ReturnCode
-p9_common_proweronoff(
+p9_common_poweronoff(
     const fapi2::Target<fapi2::TARGET_TYPE_EQ|
                         fapi2::TARGET_TYPE_CORE>& i_target,
-    int i_operation);
-
+    const p9power::powerOperation_t i_operation);
+#else
+fapi2::ReturnCode
+p9_common_poweronoff(
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target,
+    const p9power::powerOperation_t i_operation);
+#endif
 
 } // extern C
 
diff --git a/src/ppe/hwp/lib/p9_poweronoff_errors.xml b/src/ppe/hwp/lib/p9_poweronoff_errors.xml
new file mode 100644
index 0000000..e5be2f8
--- /dev/null
+++ b/src/ppe/hwp/lib/p9_poweronoff_errors.xml
@@ -0,0 +1,131 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/ppe/hwp/lib/p9_poweronoff_errors.xml $                    -->
+<!--                                                                        -->
+<!-- OpenPOWER OnChipController Project                                     -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Error definitions for p9_pfet_init and p9_pfet_lib procedures -->
+<hwpErrors>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <rc>RC_PMPROC_PFETLIB_BAD_DOMAIN</rc>
+    <description>Invalid domain value passed to p9_pfet_control.</description>
+    <ffdc>EX</ffdc>
+    <ffdc>DOMAIN</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <rc>RC_PMPROC_PFETLIB_BAD_SCOM</rc>
+    <description>SCOM request failed.</description>
+    <ffdc>EX</ffdc>
+    <ffdc>DOMAIN</ffdc>
+    <ffdc>ADDRESS</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <rc>RC_PMPROC_PFETLIB_BAD_OP</rc>
+    <description>Invalid operation value passed to p9_pfet_control.</description>
+    <ffdc>EX</ffdc>
+    <ffdc>DOMAIN</ffdc>
+    <ffdc>OPERATION</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <rc>RC_PMPROC_PFETLIB_RAIL_ON</rc>
+    <description>Error returned turning PFETs on in p9_pfet_control.</description>
+    <ffdc>EX</ffdc>
+    <ffdc>DOMAIN</ffdc>
+    <ffdc>OPERATION</ffdc>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <rc>RC_PMPROC_PFETLIB_RAIL_OFF</rc>
+    <description>Error returned turning PFETs off in p9_pfet_control.</description>
+    <ffdc>EX</ffdc>
+    <ffdc>DOMAIN</ffdc>
+    <ffdc>OPERATION</ffdc>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <rc>RC_PMPROC_PFETLIB_TIMEOUT</rc>
+    <description>
+        PFET sequencer timed out in p9_pfet_control.
+        Bad EX Chiplet
+    </description>
+    <ffdc>ADDRESS</ffdc>
+    <ffdc>PFETCONTROLVALUE</ffdc>
+    <ffdc>DOMAIN</ffdc>
+    <callout>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EX_CHIPLET</childType>
+        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EX_CHIPLET</childType>
+        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </deconfigure>
+    <gard>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EX_CHIPLET</childType>
+        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </gard>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <rc>RC_PMPROC_PFET_CODE_BAD_MODE</rc>
+    <description>Unknown mode passed to p9_pfet_init</description>
+    <ffdc>EX</ffdc>
+    <ffdc>DOMAIN</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <rc>RC_PMPROC_PFET_GET_ATTR</rc>
+    <description>p9_pfet_init could not get an attribute.</description>   
+    <ffdc>EX</ffdc>
+    <ffdc>DOMAIN</ffdc>
+    <ffdc>OPERATION</ffdc>
+  </hwpError>
+  <!-- ********************************************************************* -->
+</hwpErrors>
diff --git a/src/ppe/hwp/lib/wrapper/proc_poweronoff_wrap.C b/src/ppe/hwp/lib/wrapper/proc_poweronoff_wrap.C
new file mode 100644
index 0000000..7299238
--- /dev/null
+++ b/src/ppe/hwp/lib/wrapper/proc_poweronoff_wrap.C
@@ -0,0 +1,251 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/lib/wrapper/proc_poweronoff_wrap.C $              */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// ----------------------------------------------------------------------
+// Includes / eCMD Includes
+// ----------------------------------------------------------------------
+#include <prcdUtils.H>
+
+#include <croClientCapi.H>
+#include <ecmdClientCapi.H>
+#include <ecmdUtils.H>
+#include <ecmdSharedUtils.H>
+#include <fapi2.H>
+#include <fapi2ClientCapi.H>
+#include <fapi2SharedUtils.H>
+
+#include <string>
+#include <sstream>
+
+#include <p9_common_poweronoff.H>
+
+
+// ----------------------------------------------------------------------
+// Function definitions
+// ----------------------------------------------------------------------
+
+// display help message
+void help()
+{
+    // procedure constants
+    const std::string PROCEDURE = "proc_poweronoff_wrap";
+    const std::string REVISION  = "$Revision: 1.1 $";
+    // build help message
+    char outstr[200];
+    snprintf(outstr, sizeof(outstr), "\nThis is the help text for the procedure %s (%s)\n", PROCEDURE.c_str(), REVISION.c_str());
+    ecmdOutput(outstr);
+    snprintf(outstr, sizeof(outstr), "Syntax: %s\n", PROCEDURE.c_str());
+    ecmdOutput(outstr);
+    ecmdOutput("       [-off] [-h] [-k#] [-n#] [-s#] [-p#] [-verif]\n");
+    ecmdOutput("\n");
+    ecmdOutput("Additional options:\n");
+    ecmdOutput("      -h                           This help\n");
+    ecmdOutput("\n");
+}
+
+
+// main function
+int main(int argc, char *argv[])
+{
+    // procedure constants
+    const std::string PROCEDURE = "proc_poweronoff_wrap";
+    const std::string REVISION  = "$Revision: 1.1 $";
+
+    // from prcdUtils
+    extern bool GLOBAL_SIM_MODE;
+    extern bool GLOBAL_VERIF_MODE;
+
+    // flow/control variables
+    uint32_t rc = ECMD_SUCCESS;
+    ecmdDllInfo DLLINFO;
+    ecmdLooperData looper;
+    ecmdChipTarget target;
+    bool valid_pos_found = false;
+    char outstr[200];
+    p9power::powerOperation_t l_test1 = p9power::POWER_ON;  // turn on
+
+    fapi2::ReturnCode rc_fapi(fapi2::FAPI2_RC_SUCCESS);
+
+
+    //-----------------------------------------------------------------------------------------
+    // load and initialize the eCMD Dll
+    // if left NULL, which DLL to load is determined by the ECMD_DLL_FILE environment variable
+    // if set to a specific value, the specified DLL will be loaded
+    //-----------------------------------------------------------------------------------------
+    rc = ecmdLoadDll("");
+    if (rc) return rc;
+
+    //-----------------------------------------------------------------------------------------
+    // This is needed if you're running a FAPI procedure from this eCMD procedure
+    //-----------------------------------------------------------------------------------------
+
+    // initalize FAPI2 extension
+    rc = fapi2InitExtension();
+    if (rc)
+    {
+        ecmdOutputError("Error initializing FAPI2 extension!\n");
+        return rc;
+    }
+
+    // establish if this is a simulation run or not
+    rc = ecmdQueryDllInfo(DLLINFO);
+    if (rc)
+    {
+        ecmdUnloadDll();
+        return rc;
+    }
+    if (DLLINFO.dllEnv == ECMD_DLL_ENV_SIM)
+    {
+        GLOBAL_SIM_MODE = true;
+    }
+
+    //-------------------------------------------------------------------------------------------------
+    // Parse out user options (excluding -pX, -cX, -coe, -debug, etc
+    // E.G., ecmdRunHwp.x86 -testmode
+    //-------------------------------------------------------------------------------------------------
+    if (ecmdParseOption(&argc, &argv, "-h"))
+    {
+        help();
+        ecmdUnloadDll();
+        return rc;
+    }
+
+    if (ecmdParseOption(&argc, &argv, "-off"))
+    {
+        l_test1 = p9power::POWER_OFF;
+    }
+
+    // run procedure in sim verification mode
+    if (ecmdParseOption(&argc, &argv, "-verif"))
+    {
+        GLOBAL_VERIF_MODE = true;
+    }
+
+    //-------------------------------------------------------------------------------------------------
+    // Parse out common eCMD args like -p0, -c0, -coe, etc..
+    // Any found args will be removed from arg list upon return
+    //-------------------------------------------------------------------------------------------------
+    rc = ecmdCommandArgs(&argc, &argv);
+    if (rc)
+    {
+        ecmdUnloadDll();
+        return rc;
+    }
+
+    // unsupported arguments left over?
+    if (argc != 1)
+    {
+        ecmdOutputError("Unknown/unsupported arguments specified!\n");
+        help();
+        ecmdUnloadDll();
+        return ECMD_INVALID_ARGS;
+    }
+
+    //-------------------------------------------------------------------------------------------------
+    // Let's always print the dll info to the screen, unless in quiet mode
+    //-------------------------------------------------------------------------------------------------
+
+    if (!ecmdGetGlobalVar(ECMD_GLOBALVAR_QUIETMODE))
+    {
+        // print informational message
+        snprintf(outstr, sizeof(outstr), "Procedure %s: %s\n", PROCEDURE.c_str(), REVISION.c_str());
+        ecmdOutput(outstr);
+
+        // always print the DLL info to the screen, unless in quiet mode
+        rc = ecmdDisplayDllInfo();
+        if (rc)
+        {
+            return rc;
+        }
+    }
+
+    //-------------------------------------------------------------------------------------------------
+    // Loop over all all pu chips
+    //-------------------------------------------------------------------------------------------------
+    target.chipType      = "pu";
+    target.chipTypeState = ECMD_TARGET_FIELD_VALID;
+    target.cageState     = ECMD_TARGET_FIELD_WILDCARD;
+    target.nodeState     = ECMD_TARGET_FIELD_WILDCARD;
+    target.slotState     = ECMD_TARGET_FIELD_WILDCARD;
+    target.posState      = ECMD_TARGET_FIELD_WILDCARD;
+    target.coreState     = ECMD_TARGET_FIELD_UNUSED;
+    target.threadState   = ECMD_TARGET_FIELD_UNUSED;
+
+    rc = ecmdConfigLooperInit(target, ECMD_SELECTED_TARGETS_LOOP, looper);
+    if (rc)
+    {
+        ecmdOutputError("Error initializing proc chip looper!\n");
+        ecmdUnloadDll();
+        return rc;
+    }
+    while (ecmdConfigLooperNext(target, looper))
+    {
+        if (!ecmdGetGlobalVar(ECMD_GLOBALVAR_QUIETMODE))
+        {
+            snprintf(outstr, sizeof(outstr),
+                     "Going to call %s on proc k%d:n%d:s%d:p%02d\n",
+                     PROCEDURE.c_str(), target.cage, target.node,
+                                        target.slot, target.pos);
+            ecmdOutput(outstr);
+        }
+
+        // EXAMPLE setting up a fapi2::Target from an ecmdChipTarget
+        fapi2::Target<fapi2::TARGET_TYPE_EQ> fapi_target(&target);
+
+        // invoke FAPI procedure core
+        FAPI_EXEC_HWP(rc_fapi, p9_common_poweronoff, fapi_target, l_test1);
+        rc = (uint64_t) rc_fapi;
+        if (rc)
+        {
+            snprintf(outstr, sizeof(outstr),
+                     "ERROR: %s FAPI call exited with return code = %s 0x%08x \n",
+                     PROCEDURE.c_str(), ecmdParseReturnCode(rc).c_str(), rc);
+            ecmdOutputError(outstr);
+            ecmdUnloadDll();
+            return rc;
+        }
+
+        // mark that valid position has been found
+        valid_pos_found = true;
+    }
+
+    // check that a valid target was found
+    if (rc == ECMD_SUCCESS && !valid_pos_found)
+    {
+        ecmdOutputError("No valid targets found!\n");
+        ecmdUnloadDll();
+        return ECMD_TARGET_NOT_CONFIGURED;
+    }
+
+    prcdInfoMessage("----------------------------------------\n");
+    prcdInfoMessage("      proc_poweronoff is done\n");
+    prcdInfoMessage("----------------------------------------\n");
+
+    //-----------------------------------------------------------------------------------------------
+    // Unload the eCMD Dll, this should always be the last thing you do
+    //-----------------------------------------------------------------------------------------------
+
+    ecmdUnloadDll();
+    return rc;
+}
diff --git a/src/ppe/hwp/nest/Makefile b/src/ppe/hwp/nest/Makefile
new file mode 100644
index 0000000..7eca965
--- /dev/null
+++ b/src/ppe/hwp/nest/Makefile
@@ -0,0 +1,54 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ppe/hwp/nest/Makefile $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+
+# This Makefile compiles all of the nest hardware procedure code. See the
+# "nestfiles.mk" file in this directory.
+
+#all generated files from this makefile will end up in obj/nest
+export SUB_OBJDIR = /nest
+
+include img_defs.mk
+include nestfiles.mk
+
+
+OBJS := $(addprefix $(OBJDIR)/, $(NEST_OBJECTS))
+
+libnest.a: nest
+	$(AR) crs $(OBJDIR)/libnest.a $(OBJDIR)/*.o
+
+.PHONY: clean nest
+nest: $(OBJS)
+
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
+
+clean:
+	rm -fr $(OBJDIR)
+
+ifneq ($(MAKECMDGOALS),clean)
+include $(OBJS:.o=.d)
+endif
diff --git a/src/ppe/hwp/nest/nesterrors.mk b/src/ppe/hwp/nest/nesterrors.mk
new file mode 100644
index 0000000..0454df3
--- /dev/null
+++ b/src/ppe/hwp/nest/nesterrors.mk
@@ -0,0 +1,41 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ppe/hwp/nest/nesterrors.mk $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file nesterrors.mk
+#
+#  @brief mk for including error files
+#
+#  @page ChangeLogs Change Logs
+#  @section nesterrors.mk
+#
+##########################################################################
+# Error Files
+##########################################################################
+
+NEST_CURR_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+
+# This variable name must not change
+ERROR_XML_FILES += $(NEST_CURR_DIR)/p9_sbe_fabricinit_errors.xml
+
+
diff --git a/src/ppe/hwp/nest/nestfiles.mk b/src/ppe/hwp/nest/nestfiles.mk
new file mode 100644
index 0000000..0beb9b9
--- /dev/null
+++ b/src/ppe/hwp/nest/nestfiles.mk
@@ -0,0 +1,48 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ppe/hwp/nest/nestfiles.mk $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file nestfiles.mk
+#
+#  @brief mk for including nest object files
+#
+#  @page ChangeLogs Change Logs
+#  @section nestfiles.mk
+#  @verbatim
+#
+#  @endverbatim
+#
+##########################################################################
+# Object Files
+##########################################################################
+
+NEST-CPP-SOURCES = p9_sbe_mcs_setup.C
+NEST-CPP-SOURCES +=p9_sbe_scominit.C
+NEST-CPP-SOURCES +=p9_sbe_fabricinit.C
+
+NEST-C-SOURCES =
+NEST-S-SOURCES =
+
+NEST_OBJECTS += $(NEST-CPP-SOURCES:.C=.o)
+NEST_OBJECTS += $(NEST-C-SOURCES:.c=.o)
+NEST_OBJECTS += $(NEST-S-SOURCES:.S=.o)
diff --git a/src/ppe/hwp/nest/p9_sbe_fabricinit.C b/src/ppe/hwp/nest/p9_sbe_fabricinit.C
new file mode 100755
index 0000000..e25c9ce
--- /dev/null
+++ b/src/ppe/hwp/nest/p9_sbe_fabricinit.C
@@ -0,0 +1,186 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/nest/p9_sbe_fabricinit.C $                        */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file p9_sbe_fabricinit.C
+/// @brief Initialize island-mode fabric configuration (FAPI2)
+///
+/// @author Joe McGill <jmcgill@us.ibm.com>
+/// @author Christy Graves <clgraves@us.ibm.com>
+///
+
+//
+// *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: Nest
+// *HWP Level: 3
+// *HWP Consumed by: SBE
+//
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <p9_sbe_fabricinit.H>
+
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+
+// ADU SCOM register address definitions
+// TODO: these are currently incorrect in the FigTree/generated SCOM address header
+//       including locally defined address constants here for testing purposes
+const uint64_t PU_ALTD_CMD_REG = 0x00090001;
+const uint64_t PU_ALTD_STATUS_REG = 0x00090003;
+const uint64_t PU_SND_MODE_REG = 0x00090021;
+// FBC SCOM register address definitions
+// TODO: these are currently not present in the generated SCOM adddress header
+//       including locally defined address constants here for testing purposes
+const uint64_t PU_FBC_MODE_REG = 0x05011C0A;
+
+// ADU delay/polling constants
+const uint64_t FABRICINIT_DELAY_HW_NS = 1000; // 1us
+const uint64_t FABRICINIT_DELAY_SIM_CYCLES = 200;
+
+// ADU Command Register field/bit definitions
+const uint32_t ALTD_CMD_START_OP_BIT = 2;
+const uint32_t ALTD_CMD_CLEAR_STATUS_BIT = 3;
+const uint32_t ALTD_CMD_RESET_FSM_BIT = 4;
+const uint32_t ALTD_CMD_ADDRESS_ONLY_BIT = 6;
+const uint32_t ALTD_CMD_LOCK_BIT = 11;
+const uint32_t ALTD_CMD_DROP_PRIORITY_BIT = 20;
+const uint32_t ALTD_CMD_OVERWRITE_PBINIT_BIT = 22;
+const uint32_t ALTD_CMD_TTYPE_START_BIT = 25;
+const uint32_t ALTD_CMD_TTYPE_END_BIT = 31;
+const uint32_t ALTD_CMD_TSIZE_START_BIT = 32;
+const uint32_t ALTD_CMD_TSIZE_END_BIT = 39;
+
+const uint32_t ALTD_CMD_TTYPE_NUM_BITS = (ALTD_CMD_TTYPE_END_BIT-ALTD_CMD_TTYPE_START_BIT+1);
+const uint32_t ALTD_CMD_TSIZE_NUM_BITS = (ALTD_CMD_TSIZE_END_BIT-ALTD_CMD_TSIZE_START_BIT+1);
+
+const uint32_t ALTD_CMD_TTYPE_PBOP_EN_ALL = 0x3F;
+const uint32_t ALTD_CMD_TSIZE_PBOP_EN_ALL = 0x0B;
+
+// ADU Status Register field/bit definitions
+const uint32_t ALTD_STATUS_ADDR_DONE_BIT = 2;
+const uint32_t ALTD_STATUS_PBINIT_MISSING_BIT = 18;
+const uint32_t ALTD_STATUS_CRESP_START_BIT = 59;
+const uint32_t ALTD_STATUS_CRESP_END_BIT = 63;
+
+const uint32_t ALTD_STATUS_CRESP_NUM_BITS = (ALTD_STATUS_CRESP_END_BIT-ALTD_STATUS_CRESP_START_BIT+1);
+
+const uint32_t ALTD_STATUS_CRESP_ACK_DONE = 0x04;
+
+// ADU PMisc Register field/bit definitions
+const uint32_t ALTD_SND_MODE_FBC_STOP_BIT = 22;
+
+// FBC Mode Register field/bit definitions
+const uint32_t PU_FBC_MODE_PB_INITIALIZED_BIT = 0;
+
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+
+fapi2::ReturnCode
+p9_sbe_fabricinit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target)
+{
+    FAPI_INF("Start");
+
+    fapi2::buffer<uint64_t> l_cmd_data;
+    fapi2::buffer<uint64_t> l_pmisc_mode_data;
+    fapi2::buffer<uint64_t> l_status_data_act;
+    fapi2::buffer<uint64_t> l_status_data_exp;
+    fapi2::buffer<uint64_t> l_fbc_mode_data;
+
+    // check state of fabric pervasive stop control signal
+    // if set, this would prohibit all fabric commands from being broadcast
+    FAPI_TRY(fapi2::getScom(i_target, PU_SND_MODE_REG, l_pmisc_mode_data),
+             "Error reading ADU PMisc Mode register");
+    FAPI_ASSERT(!l_pmisc_mode_data.getBit<ALTD_SND_MODE_FBC_STOP_BIT>(),
+                fapi2::P9_SBE_FABRICINIT_FBC_STOPPED_ERR().set_TARGET(i_target),
+                "Pervasive stop control is asserted, so fabricinit will not run!");
+
+    // write ADU Command Register to attempt lock acquisition
+    // hold lock until finished with sequence
+    FAPI_DBG("Lock and reset ADU ...");
+    l_cmd_data.setBit<ALTD_CMD_LOCK_BIT>();
+    FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, l_cmd_data),
+             "Error writing ADU Command Register to acquire lock");
+
+    // clear ADU status/reset state machine
+    l_cmd_data.setBit<ALTD_CMD_CLEAR_STATUS_BIT>()
+              .setBit<ALTD_CMD_RESET_FSM_BIT>();
+    FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, l_cmd_data),
+             "Error writing ADU Command Register to clear status and reset state machine");
+
+    // launch init command
+    FAPI_DBG("Launching fabric init command via ADU ...");
+    l_cmd_data.setBit<ALTD_CMD_START_OP_BIT>()
+              .clearBit<ALTD_CMD_CLEAR_STATUS_BIT>()
+              .clearBit<ALTD_CMD_RESET_FSM_BIT>()
+              .setBit<ALTD_CMD_ADDRESS_ONLY_BIT>()
+              .setBit<ALTD_CMD_DROP_PRIORITY_BIT>()
+              .setBit<ALTD_CMD_OVERWRITE_PBINIT_BIT>();
+    l_cmd_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT,ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_PBOP_EN_ALL);
+    l_cmd_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT,ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_TSIZE_PBOP_EN_ALL);
+    FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, l_cmd_data),
+             "Error writing ADU Command Register to launch init operation");
+
+    // delay prior to checking for completion
+    FAPI_TRY(fapi2::delay(FABRICINIT_DELAY_HW_NS, FABRICINIT_DELAY_SIM_CYCLES),
+             "Error from delay");
+
+    // read ADU Status Register and check for expected pattern
+    FAPI_DBG("Checking status of ADU operation ...");
+    FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_STATUS_REG, l_status_data_act),
+             "Error polling ADU Status Register");
+
+    l_status_data_exp.setBit<ALTD_STATUS_ADDR_DONE_BIT>();
+    l_status_data_exp.insertFromRight<ALTD_STATUS_CRESP_START_BIT,ALTD_STATUS_CRESP_NUM_BITS>(ALTD_STATUS_CRESP_ACK_DONE);
+
+    FAPI_ASSERT(l_status_data_exp == l_status_data_act,
+                fapi2::P9_SBE_FABRICINIT_FAILED_ERR().set_TARGET(i_target),
+                "Fabric init failed, or mismatch in expected ADU status!");
+
+    // clear ADU Command Register to release lock
+    FAPI_DBG("Success! Releasing ADU lock ...");
+    l_cmd_data = 0;
+    FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, l_cmd_data),
+             "Error writing ADU Command Register to release lock");
+
+    // confirm that fabric was successfully initialized
+    FAPI_DBG("Checking status of FBC init ...");
+    FAPI_TRY(fapi2::getScom(i_target, PU_FBC_MODE_REG, l_fbc_mode_data),
+             "Error reading FBC Mode Register");
+    FAPI_ASSERT(l_fbc_mode_data.getBit<PU_FBC_MODE_PB_INITIALIZED_BIT>(),
+                fapi2::P9_SBE_FABRICINIT_NO_INIT_ERR().set_TARGET(i_target),
+                "ADU command succeded, but fabric was not initialized!");
+
+fapi_try_exit:
+    FAPI_INF("End");
+    return fapi2::current_err;
+}
diff --git a/src/ppe/hwp/nest/p9_sbe_fabricinit.H b/src/ppe/hwp/nest/p9_sbe_fabricinit.H
new file mode 100755
index 0000000..64bda1e
--- /dev/null
+++ b/src/ppe/hwp/nest/p9_sbe_fabricinit.H
@@ -0,0 +1,110 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/nest/p9_sbe_fabricinit.H $                        */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file p9_sbe_fabricinit.H
+/// @brief Initialize island-mode fabric configuration (FAPI2)
+///
+/// The purpose of this procedure is to initalize the fabric.
+///
+/// In the post scan flush/init state, the fabric command/data init lines on
+/// each chip are held de-asserted; this stops all local arbitration for
+/// command/data requests from attached units.  At the conclusion of this
+/// procedure, the fabric command/data init lines on the target chip
+/// will be asserted.  Units on the target chip may make fabric requests that
+/// will be processed and broadcast out to the SMP (consisting of the target
+/// chip only), based upon the defined fabric broadcast protocols.
+///
+/// The initialization is accomplished by injecting an init command (special
+/// ttype/tsize) into the fabric from the Alter Display Unit (ADU). This
+/// command is permitted to be broadcast (even though the target chip is not
+/// yet initialized), because the ADU is considered a trusted unit allowed
+/// to broadcast commands at any time.
+///
+/// When the init reflected command is observed by the fabric snooper logic
+/// (with target chip configured as fabric master), it will provide an
+/// lpc_ack partial response that generates a clean combined response
+/// (ack_done). Upon observation of the clean combined response broadcast,
+/// the fabric snooper logic will assert its command/data init lines to
+/// permit locally mastered requests to be arbitrated.
+///
+/// High-level procedure flow:
+/// - Check state of tc_pb_stop (set by checkstop), which if
+///   set would prohibit the init command from being broadcast
+/// - Acquire the ADU lock to guarantee exclusive use of ADU resources
+/// - Clear the ADU status register, reset ADU state machine
+/// - Program the ADU to issue & launch the init command
+/// - Check the status of the init command
+/// - Release the ADU lock
+/// - Confirm state of fabric init control
+///
+/// @author Joe McGill <jmcgill@us.ibm.com>
+/// @author Christy Graves <clgraves@us.ibm.com>
+///
+
+//
+// *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: Nest
+// *HWP Level: 3
+// *HWP Consumed by: SBE
+//
+
+#ifndef _P9_SBE_FABRICINIT_H_
+#define _P9_SBE_FABRICINIT_H_
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <fapi2.H>
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_sbe_fabricinit_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &);
+
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+extern "C"
+{
+
+///
+/// @brief Initialize fabric (in single chip 'island mode' configuration) by mastering
+/// an init command (ttype=pbop.init_all) from the Alter Display Unit (ADU)
+///
+/// @param[in] i_target Reference to processor chip target
+/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+///
+fapi2::ReturnCode p9_sbe_fabricinit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target);
+
+} // extern "C"
+
+#endif // _P9_SBE_FABRICINIT_H_
diff --git a/src/ppe/hwp/nest/p9_sbe_fabricinit_errors.xml b/src/ppe/hwp/nest/p9_sbe_fabricinit_errors.xml
new file mode 100755
index 0000000..13d0494
--- /dev/null
+++ b/src/ppe/hwp/nest/p9_sbe_fabricinit_errors.xml
@@ -0,0 +1,55 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/ppe/hwp/nest/p9_sbe_fabricinit_errors.xml $               -->
+<!--                                                                        -->
+<!-- OpenPOWER OnChipController Project                                     -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Halt codes for p9_sbe_fabricinit -->
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_P9_SBE_FABRICINIT_FBC_STOPPED_ERR</rc>
+    <description>
+      Procedure: p9_sbe_fabricinit
+      Fabric init sequence not attempted, fabric arbitration is stopped.
+    </description>
+    <ffdc>TARGET</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_P9_SBE_FABRICINIT_FAILED_ERR</rc>
+    <description>
+      Procedure: p9_sbe_fabricinit
+      Fabric init failed, or mismatch in expected ADU status.
+    </description>
+    <ffdc>TARGET</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_P9_SBE_FABRICINIT_NO_INIT_ERR</rc>
+    <description>
+      Procedure: p9_sbe_fabricinit
+      ADU operation completed successfully, but fabric was not initialized.
+    </description>
+    <ffdc>TARGET</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>
diff --git a/src/ppe/hwp/nest/p9_sbe_mcs_setup.C b/src/ppe/hwp/nest/p9_sbe_mcs_setup.C
new file mode 100644
index 0000000..7a55e0f
--- /dev/null
+++ b/src/ppe/hwp/nest/p9_sbe_mcs_setup.C
@@ -0,0 +1,55 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/nest/p9_sbe_mcs_setup.C $                         */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_mcs_setup.C
+///
+/// @brief Configure one MCS unit on the master chip to low point of
+/// coherency acknowledge preparations(lpc_ack preps). in support
+/// of dcbz(Data Cache Block Zero) operations executed by HBI code
+/// (while still running cache contained prior to memory configuration).
+//------------------------------------------------------------------------------
+// *HWP HW Owner         : Girisankar Paulraj <gpaulraj@in.ibm.com>
+// *HWP HW Backup Owner  : Joe McGill <jcmgill@us.ibm.com>
+// *HWP FW Owner         : Thi N. Tran <thi@us.ibm.com>
+// *HWP Team             : Nest
+// *HWP Level            : 1
+// *HWP Consumed by      : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_mcs_setup.H"
+
+
+fapi2::ReturnCode p9_sbe_mcs_setup(const
+                  fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target)
+{
+    FAPI_DBG("Entering ...");
+
+    FAPI_DBG("Exiting ...");
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+}
diff --git a/src/ppe/hwp/nest/p9_sbe_mcs_setup.H b/src/ppe/hwp/nest/p9_sbe_mcs_setup.H
new file mode 100644
index 0000000..014499a
--- /dev/null
+++ b/src/ppe/hwp/nest/p9_sbe_mcs_setup.H
@@ -0,0 +1,64 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/nest/p9_sbe_mcs_setup.H $                         */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_mcs_setup.H
+///
+/// @brief Configure one MCS unit on the master chip to low point of
+/// coherency acknowledge preparations(lpc_ack preps). in support
+/// of dcbz(Data Cache Block Zero) operations executed by HBI code
+/// (while still running cache contained prior to memory configuration).
+//------------------------------------------------------------------------------
+// *HWP HW Owner         : Girisankar Paulraj <gpaulraj@in.ibm.com>
+// *HWP HW Backup Owner  : Joe McGill <jcmgill@us.ibm.com>
+// *HWP FW Owner         : Thi N. Tran <thi@us.ibm.com>
+// *HWP Team             : Nest
+// *HWP Level            : 1
+// *HWP Consumed by      : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_MCS_SETUP_H_
+#define _P9_SBE_MCS_SETUP_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_mcs_setup_FP_t)(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &);
+
+/// @brief This function configures MCS BAR registers on master SBE chip
+/// to support of dcbz operation execution by HBI code and response
+/// on lpc_ack preps
+///
+/// @param[in]     i_target   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_mcs_setup(const
+                      fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target);
+}
+
+#endif
diff --git a/src/ppe/hwp/nest/p9_sbe_scominit.C b/src/ppe/hwp/nest/p9_sbe_scominit.C
new file mode 100644
index 0000000..7d6bf9c
--- /dev/null
+++ b/src/ppe/hwp/nest/p9_sbe_scominit.C
@@ -0,0 +1,58 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/nest/p9_sbe_scominit.C $                          */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_scominit.C
+///
+/// @brief This procedure contains SCOM based initialization required for
+///  fabric configuration & HBI operation
+/// *!
+/// *!   o Set fabric node/chip ID configuration for all configured
+/// *!     chiplets to chip specific values
+/// *!   o Establish ADU XSCOM BAR for HBI operation
+//------------------------------------------------------------------------------
+// *HWP HW Owner         : Girisankar Paulraj <gpaulraj@in.ibm.com>
+// *HWP HW Backup Owner  : Joe McGill <jmcgill@us.ibm.com>
+// *HWP FW Owner         : Thi N. Tran <thi@us.ibm.com>
+// *HWP Team             : Nest
+// *HWP Level            : 1
+// *HWP Consumed by      : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_scominit.H"
+
+
+
+fapi2::ReturnCode p9_sbe_scominit(const
+                  fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target)
+{
+    FAPI_DBG("Entering ...");
+
+    FAPI_DBG("Exiting ...");
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+}
diff --git a/src/ppe/hwp/nest/p9_sbe_scominit.H b/src/ppe/hwp/nest/p9_sbe_scominit.H
new file mode 100644
index 0000000..1511efb
--- /dev/null
+++ b/src/ppe/hwp/nest/p9_sbe_scominit.H
@@ -0,0 +1,66 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/nest/p9_sbe_scominit.H $                          */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_scominit.H
+///
+/// @brief This procedure contains SCOM based initialization required for
+///  fabric configuration & HBI operation
+/// *!
+/// *!   o Set fabric node/chip ID configuration for all configured
+/// *!     chiplets to chip specific values
+/// *!   o Establish ADU XSCOM BAR for HBI operation
+//------------------------------------------------------------------------------
+// *HWP HW Owner         : Girisankar Paulraj <gpaulraj@in.ibm.com>
+// *HWP HW Backup Owner  : Joe McGill <jmcgill@us.ibm.com>
+// *HWP FW Owner         : Thi N. Tran <thi@us.ibm.com>
+// *HWP Team             : Nest
+// *HWP Level            : 1
+// *HWP Consumed by      : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_SCOMINIT_H_
+#define _P9_SBE_SCOMINIT_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_scominit_FP_t)(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &);
+
+/// @brief This function does ADU BAR and XSCOM BAR base setup,
+/// Set Fabric node/chip ID for  all configured chiplets in nest
+/// area and Clearing/setting up FIR register
+///
+/// @param[in]     i_target   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_scominit(const
+                      fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target);
+}
+
+#endif
diff --git a/src/ppe/hwp/perv/p9_sbe_arrayinit.C b/src/ppe/hwp/perv/p9_sbe_arrayinit.C
new file mode 100644
index 0000000..e6ae399
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_arrayinit.C
@@ -0,0 +1,53 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/perv/p9_sbe_arrayinit.C $                         */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_arrayinit.C
+///
+/// @brief array init procedure to be called with any chiplet target
+//------------------------------------------------------------------------------
+// *HWP HWP Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner         : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team             : Perv
+// *HWP Level            : 1
+// *HWP Consumed by      : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_arrayinit.H"
+
+
+
+fapi2::ReturnCode p9_sbe_arrayinit(const
+                                   fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip)
+{
+    FAPI_DBG("Entering ...");
+
+    FAPI_DBG("Exiting ...");
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+}
diff --git a/src/ppe/hwp/perv/p9_sbe_arrayinit.H b/src/ppe/hwp/perv/p9_sbe_arrayinit.H
new file mode 100644
index 0000000..6e82ed1
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_arrayinit.H
@@ -0,0 +1,60 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/perv/p9_sbe_arrayinit.H $                         */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_arrayinit.H
+///
+/// @brief array init procedure to be called with any chiplet target
+//------------------------------------------------------------------------------
+// *HWP HWP Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner         : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team             : Perv
+// *HWP Level            : 1
+// *HWP Consumed by      : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_ARRAYINIT_H_
+#define _P9_SBE_ARRAYINIT_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_arrayinit_FP_t)(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &);
+
+/// @brief --Run arrayinit on all enabled chiplets
+/// --Scan flush 0 to all rings except GPTR, Time, Repair on all enabled chiplets
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_arrayinit(const
+                                       fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip);
+}
+
+#endif
diff --git a/src/ppe/hwp/perv/p9_sbe_arrayinit_errors.xml b/src/ppe/hwp/perv/p9_sbe_arrayinit_errors.xml
new file mode 100644
index 0000000..4e7f371
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_arrayinit_errors.xml
@@ -0,0 +1,36 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/ppe/hwp/perv/p9_sbe_arrayinit_errors.xml $                -->
+<!--                                                                        -->
+<!-- OpenPOWER OnChipController Project                                     -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- This is an automatically generated file. -->
+<!-- File: p9_sbe_arrayinit_errors.xml. -->
+<!-- Halt codes for p9_sbe_arrayinit -->
+
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_ABIST_DONE</rc>
+    <description>Check Abist Done bit after Array Init</description>
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>
diff --git a/src/ppe/hwp/perv/p9_sbe_chiplet_init.C b/src/ppe/hwp/perv/p9_sbe_chiplet_init.C
new file mode 100644
index 0000000..65cf28d
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_chiplet_init.C
@@ -0,0 +1,55 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/perv/p9_sbe_chiplet_init.C $                      */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_chiplet_init.C
+///
+/// @brief init procedure for all enabled chiplets
+// *!
+// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
+// *! BACKUP NAME :                   Email:
+//------------------------------------------------------------------------------
+// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team        : Perv
+// *HWP Level       : 1
+// *HWP Consumed by : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_chiplet_init.H"
+
+
+
+fapi2::ReturnCode p9_sbe_chiplet_init(const
+                                      fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip)
+{
+    FAPI_DBG("Entering ...");
+
+    FAPI_DBG("Exiting ...");
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+}
diff --git a/src/ppe/hwp/perv/p9_sbe_chiplet_init.H b/src/ppe/hwp/perv/p9_sbe_chiplet_init.H
new file mode 100644
index 0000000..d79634d
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_chiplet_init.H
@@ -0,0 +1,61 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/perv/p9_sbe_chiplet_init.H $                      */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_chiplet_init.H
+///
+/// @brief init procedure for all enabled chiplets
+// *!
+// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
+// *! BACKUP NAME :                   Email:
+//------------------------------------------------------------------------------
+// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team        : Perv
+// *HWP Level       : 1
+// *HWP Consumed by : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_CHIPLET_INIT_H_
+#define _P9_SBE_CHIPLET_INIT_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_chiplet_init_FP_t)(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &);
+
+/// @brief Scan 0 all rings (except time, repair, gptr) on all enabled chiplets
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_chiplet_init(const
+                                          fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip);
+}
+
+#endif
diff --git a/src/ppe/hwp/perv/p9_sbe_chiplet_init_errors.xml b/src/ppe/hwp/perv/p9_sbe_chiplet_init_errors.xml
new file mode 100644
index 0000000..6796f1e
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_chiplet_init_errors.xml
@@ -0,0 +1,49 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/ppe/hwp/perv/p9_sbe_chiplet_init_errors.xml $             -->
+<!--                                                                        -->
+<!-- OpenPOWER OnChipController Project                                     -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- This is an automatically generated file. -->
+<!-- File: p9_sbe_chiplet_init_errors.xml. -->
+<!-- Halt codes for p9_sbe_chiplet_init -->
+
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_CHECKSTOP_STAGE_1_ERR</rc>
+    <description>Checkstop error after MC config</description>
+    <ffdc>CHIP</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_CHECKSTOP_STAGE_2_ERR</rc>
+    <description>Checkstop error after scan0</description>
+    <ffdc>CHIP</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_CHECKSTOP_STAGE_3_ERR</rc>
+    <description>Checkstop checks</description>
+    <ffdc>CHIP</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>
diff --git a/src/ppe/hwp/perv/p9_sbe_chiplet_pll_initf.C b/src/ppe/hwp/perv/p9_sbe_chiplet_pll_initf.C
new file mode 100644
index 0000000..3b2ab46
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_chiplet_pll_initf.C
@@ -0,0 +1,55 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/perv/p9_sbe_chiplet_pll_initf.C $                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_chiplet_pll_initf.C
+///
+/// @brief procedure for scan initializing PLL config bits for L2 and L3 plls
+// *!
+// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
+// *! BACKUP NAME : srinivas naga     Email: srinivan@in.ibm.com
+//------------------------------------------------------------------------------
+// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP FW Owner    : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team        : Perv
+// *HWP Level       : 1
+// *HWP Consumed by : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_chiplet_pll_initf.H"
+
+
+
+fapi2::ReturnCode p9_sbe_chiplet_pll_initf(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip)
+{
+    FAPI_DBG("Entering ...");
+
+    FAPI_DBG("Exiting ...");
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+}
diff --git a/src/ppe/hwp/perv/p9_sbe_chiplet_pll_initf.H b/src/ppe/hwp/perv/p9_sbe_chiplet_pll_initf.H
new file mode 100644
index 0000000..ce69926
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_chiplet_pll_initf.H
@@ -0,0 +1,61 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/perv/p9_sbe_chiplet_pll_initf.H $                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_chiplet_pll_initf.H
+///
+/// @brief procedure for scan initializing PLL config bits for L2 and L3 plls
+// *!
+// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
+// *! BACKUP NAME : srinivas naga     Email: srinivan@in.ibm.com
+//------------------------------------------------------------------------------
+// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP FW Owner    : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team        : Perv
+// *HWP Level       : 1
+// *HWP Consumed by : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_CHIPLET_PLL_INITF_H_
+#define _P9_SBE_CHIPLET_PLL_INITF_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_chiplet_pll_initf_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &);
+
+/// @brief load the pll config settings for L2 AND L3 plls
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_chiplet_pll_initf(const
+            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip);
+}
+
+#endif
diff --git a/src/ppe/hwp/perv/p9_sbe_chiplet_pll_setup.C b/src/ppe/hwp/perv/p9_sbe_chiplet_pll_setup.C
new file mode 100644
index 0000000..f7e2c38
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_chiplet_pll_setup.C
@@ -0,0 +1,55 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/perv/p9_sbe_chiplet_pll_setup.C $                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_chiplet_pll_setup.C
+///
+/// @brief PLL set up for L2 and L3 plls
+// *!
+// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
+// *! BACKUP NAME :                   Email:
+//------------------------------------------------------------------------------
+// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP FW Owner    : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team        : Perv
+// *HWP Level       : 1
+// *HWP Consumed by : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_chiplet_pll_setup.H"
+
+
+
+fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip)
+{
+    FAPI_DBG("Entering ...");
+
+    FAPI_DBG("Exiting ...");
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+}
diff --git a/src/ppe/hwp/perv/p9_sbe_chiplet_pll_setup.H b/src/ppe/hwp/perv/p9_sbe_chiplet_pll_setup.H
new file mode 100644
index 0000000..3e997de
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_chiplet_pll_setup.H
@@ -0,0 +1,61 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/perv/p9_sbe_chiplet_pll_setup.H $                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_chiplet_pll_setup.H
+///
+/// @brief PLL set up for L2 and L3 plls
+// *!
+// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
+// *! BACKUP NAME :                   Email:
+//------------------------------------------------------------------------------
+// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP FW Owner    : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team        : Perv
+// *HWP Level       : 1
+// *HWP Consumed by : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_CHIPLET_PLL_SETUP_H_
+#define _P9_SBE_CHIPLET_PLL_SETUP_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_chiplet_pll_setup_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &);
+
+/// @brief PLL setup for L2 and L3 levels
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const
+            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip);
+}
+
+#endif
diff --git a/src/ppe/hwp/perv/p9_sbe_chiplet_reset.C b/src/ppe/hwp/perv/p9_sbe_chiplet_reset.C
new file mode 100644
index 0000000..1b10744
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_chiplet_reset.C
@@ -0,0 +1,58 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/perv/p9_sbe_chiplet_reset.C $                     */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_chiplet_reset.C
+///
+/// @brief Identify all good chiplets excluding EQ/EC
+/// Setup multicast groups for all chiplets
+/// For all good chiplets excluding EQ/EC
+/// For all enabled chiplets
+// *!
+// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
+// *! BACKUP NAME :                   Email:
+//------------------------------------------------------------------------------
+// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team        : Perv
+// *HWP Level       : 1
+// *HWP Consumed by : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_chiplet_reset.H"
+
+
+
+fapi2::ReturnCode p9_sbe_chiplet_reset(const
+                                       fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip)
+{
+    FAPI_DBG("Entering ...");
+
+    FAPI_DBG("Exiting ...");
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+}
diff --git a/src/ppe/hwp/perv/p9_sbe_chiplet_reset.H b/src/ppe/hwp/perv/p9_sbe_chiplet_reset.H
new file mode 100644
index 0000000..91f0ef9
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_chiplet_reset.H
@@ -0,0 +1,78 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/perv/p9_sbe_chiplet_reset.H $                     */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_chiplet_reset.H
+///
+/// @brief Identify all good chiplets excluding EQ/EC
+/// Setup multicast groups for all chiplets
+/// For all good chiplets excluding EQ/EC
+/// For all enabled chiplets
+// *!
+// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
+// *! BACKUP NAME :                   Email:
+//------------------------------------------------------------------------------
+// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team        : Perv
+// *HWP Level       : 1
+// *HWP Consumed by : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_CHIPLET_RESET_H_
+#define _P9_SBE_CHIPLET_RESET_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_chiplet_reset_FP_t)(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &);
+
+/// @brief Identify all good chiplets excluding EQ/EC
+///      -- All chiplets will be reset and PLLs started
+///      -- Partial bad - All nest Chiplets must be good, MC, IO can be partial bad
+/// Setup multicast groups for all chiplets
+///      -- Can't use the multicast for all non-nest chiplets
+///      -- This is intended to be the eventual product setting
+///      -- This includes the core/cache chiplets
+/// For all good chiplets excluding EQ/EC
+///      -- Setup Chiplet GP3 regs
+///          -- Reset to default state
+///          -- Set chiplet enable on all all good chiplets excluding EQ/EC
+/// For all enabled chiplets
+///      -- Start vital clocks and release endpoint reset
+///      -- PCB Slave error register Reset
+///
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_chiplet_reset(const
+                                           fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip);
+}
+
+#endif
diff --git a/src/ppe/hwp/perv/p9_sbe_gptr_time_repr_initf.C b/src/ppe/hwp/perv/p9_sbe_gptr_time_repr_initf.C
new file mode 100644
index 0000000..179a0a4
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_gptr_time_repr_initf.C
@@ -0,0 +1,55 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/perv/p9_sbe_gptr_time_repr_initf.C $              */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_gptr_time_repr_initf.C
+///
+/// @brief Scan 0  and Load repair , time and GPTR rings for all enabled chiplets
+// *!
+// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
+// *! BACKUP NAME :                   Email:
+//------------------------------------------------------------------------------
+// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team        : Perv
+// *HWP Level       : 1
+// *HWP Consumed by : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_gptr_time_repr_initf.H"
+
+
+
+fapi2::ReturnCode p9_sbe_gptr_time_repr_initf(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip)
+{
+    FAPI_DBG("Entering ...");
+
+    FAPI_DBG("Exiting ...");
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+}
diff --git a/src/ppe/hwp/perv/p9_sbe_gptr_time_repr_initf.H b/src/ppe/hwp/perv/p9_sbe_gptr_time_repr_initf.H
new file mode 100644
index 0000000..4fb1104
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_gptr_time_repr_initf.H
@@ -0,0 +1,63 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/perv/p9_sbe_gptr_time_repr_initf.H $              */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_gptr_time_repr_initf.H
+///
+/// @brief Scan 0  and Load repair , time and GPTR rings for all enabled chiplets
+// *!
+// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
+// *! BACKUP NAME :                   Email:
+//------------------------------------------------------------------------------
+// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team        : Perv
+// *HWP Level       : 1
+// *HWP Consumed by : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_GPTR_TIME_REPR_INITF_H_
+#define _P9_SBE_GPTR_TIME_REPR_INITF_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_gptr_time_repr_initf_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &);
+
+/// @brief Scan 0 all rings on all enabled chiplets (except for TP)
+/// Load Repair, Time and GPTR rings for all enabled chiplets
+///       -- All chip customization data is within the repair and time rings -- array repair, DTS setting
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_gptr_time_repr_initf(const
+            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip);
+}
+
+#endif
diff --git a/src/ppe/hwp/perv/p9_sbe_nest_enable_ridi.C b/src/ppe/hwp/perv/p9_sbe_nest_enable_ridi.C
new file mode 100644
index 0000000..19c0e15
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_nest_enable_ridi.C
@@ -0,0 +1,55 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/perv/p9_sbe_nest_enable_ridi.C $                  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_nest_enable_ridi.C
+///
+/// @brief Enable ridi controls for NEST logic
+// *!
+// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
+// *! BACKUP NAME :                   Email:
+//------------------------------------------------------------------------------
+// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP FW Owner    : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team        : Perv
+// *HWP Level       : 1
+// *HWP Consumed by : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_nest_enable_ridi.H"
+
+
+
+fapi2::ReturnCode p9_sbe_nest_enable_ridi(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip)
+{
+    FAPI_DBG("Entering ...");
+
+    FAPI_DBG("Exiting ...");
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+}
diff --git a/src/ppe/hwp/perv/p9_sbe_nest_enable_ridi.H b/src/ppe/hwp/perv/p9_sbe_nest_enable_ridi.H
new file mode 100644
index 0000000..e18ecc6
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_nest_enable_ridi.H
@@ -0,0 +1,61 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/perv/p9_sbe_nest_enable_ridi.H $                  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_nest_enable_ridi.H
+///
+/// @brief Enable ridi controls for NEST logic
+// *!
+// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
+// *! BACKUP NAME :                   Email:
+//------------------------------------------------------------------------------
+// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP FW Owner    : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team        : Perv
+// *HWP Level       : 1
+// *HWP Consumed by : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_NEST_ENABLE_RIDI_H_
+#define _P9_SBE_NEST_ENABLE_RIDI_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_nest_enable_ridi_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &);
+
+/// @brief procedure enables ridi for nest region
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_nest_enable_ridi(const
+            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip);
+}
+
+#endif
diff --git a/src/ppe/hwp/perv/p9_sbe_setup_evid.C b/src/ppe/hwp/perv/p9_sbe_setup_evid.C
new file mode 100644
index 0000000..c998a29
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_setup_evid.C
@@ -0,0 +1,82 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/perv/p9_sbe_setup_evid.C $                        */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_sbe_setup_evid.C
+/// @brief Setup External Voltage IDs and Boot Frequency
+///
+// *HW Owner    : Greg Still <stillgs@us.ibm.com>
+// *FW Owner    : Sangeetha T S <sangeet2@in.ibm.com>
+// *Team        : PM
+// *Consumed by : SBE
+// *Level       : 1
+///
+/// @verbatim
+/// Procedure Summary:
+///   - Use Attributes to send VDD, VCS via the AVS bus to VRMs
+///   - Use Attributes to adjust the VDN and send via I2C to VRM
+///   - Read core frequency ATTR and write to the Quad PPM
+/// @endverbatim
+
+//-----------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------
+#include <fapi2.H>
+#include "p9_sbe_setup_evid.H"
+
+//-----------------------------------------------------------------------------
+// Procedure
+//-----------------------------------------------------------------------------
+
+fapi2::ReturnCode
+p9_sbe_setup_evid(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+{
+
+    //fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS;
+
+    // Substep indicators
+
+    // commented out in Level 1 to not have "unused variable" warnings
+    // until the SBE substep management "macro" or "call" is defined.
+
+    // const uint32_t STEP_SBE_EVID_START              = 0x1;
+    // const uint32_t STEP_SBE_EVID_CONFIG             = 0x2;
+    // const uint32_t STEP_SBE_EVID_WRITE_VDN          = 0x3;
+    // const uint32_t STEP_SBE_EVID_POLL_VDN_STATUS    = 0x4;
+    // const uint32_t STEP_SBE_EVID_WRITE_VDD          = 0x5;
+    // const uint32_t STEP_SBE_EVID_POLL_VDD_STATUS    = 0x6;
+    // const uint32_t STEP_SBE_EVID_WRITE_VCS          = 0x7;
+    // const uint32_t STEP_SBE_EVID_POLL_VCS_STATUS    = 0x8;
+    // const uint32_t STEP_SBE_EVID_TIMEOUT            = 0x9;
+    // const uint32_t STEP_SBE_EVID_BOOT_FREQ          = 0xA;
+    // const uint32_t STEP_SBE_EVID_COMPLETE           = 0xB;
+
+// The inclusion of the following will cause a "label 'fapi_try_exit' defined but not used"
+// compile error in Cronus.  This will be uncommented when FAPI_TRY functions are added
+// during the real procedure development.  However, this is NOT needed for Level 1.
+//fapi_try_exit:
+    return fapi2::current_err;
+
+} // Procedure
+
diff --git a/src/ppe/hwp/perv/p9_sbe_setup_evid.H b/src/ppe/hwp/perv/p9_sbe_setup_evid.H
new file mode 100644
index 0000000..c543f62
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_setup_evid.H
@@ -0,0 +1,65 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/perv/p9_sbe_setup_evid.H $                        */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_sbe_setup_evid.H
+/// @brief Setup External Voltage IDs and Boot Frequency
+///
+/// *HW Owner    : Greg Still <stillgs@us.ibm.com>
+/// *FW Owner    : Sangeetha T S <sangeet2@in.ibm.com>
+/// *Team        : PM
+/// *Consumed by : SBE
+/// *Level       : 1
+///
+
+#ifndef __P9_SBE_SETUP_EVID_H__
+#define __P9_SBE_SETUP_EVID_H__
+
+extern "C"
+{
+
+/// @typedef p9_sbe_setup_evid_FP_t
+/// function pointer typedef definition for HWP call support
+    typedef fapi2::ReturnCode (*p9_sbe_setup_evid_FP_t) (
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &);
+
+/// @brief Read attributes containing this part's boot voltages (VDD, VCS and VDN)
+///        and set these voltage using the AVSBUS interface (VDD, VCS) an I2C (VDN).
+///        Also reads a differnt attribute containing the boot frequency and set that
+///        into each configured EQ chiplet.
+/// @param [in] i_target TARGET_TYPE_PROC_CHIP
+/// @attr
+/// @attritem   ATTR_BOOT_FREQ          uint16_t - 9 bit frequency multiplier of the refclk right justified
+/// @attritem   ATTR_VCS_BOOT_VOLTAGE   uint16_t - 1mV grandularity setting for the VCS rail
+/// @attritem   ATTR_VDD_BOOT_VOLTAGE   uint16_t - 1mV grandularity setting for the VDD rail
+/// @attritem   ATTR_VDN_BOOT_VOLTAGE   uint16_t - 1mV grandularity setting for the VDN rail
+///
+/// @retval FAPI_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_sbe_setup_evid(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+
+
+} // extern C
+
+#endif  // __P9_SBE_SETUP_EVID_H__
diff --git a/src/ppe/hwp/perv/p9_sbe_setup_evid_errors.xml b/src/ppe/hwp/perv/p9_sbe_setup_evid_errors.xml
new file mode 100644
index 0000000..588797d
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_setup_evid_errors.xml
@@ -0,0 +1,56 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/ppe/hwp/perv/p9_sbe_setup_evid_errors.xml $               -->
+<!--                                                                        -->
+<!-- OpenPOWER OnChipController Project                                     -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+
+<!-- *HWP HWP Owner: Greg Still <stillgs @us.ibm.com>                       -->
+<!-- *HWP FW Owner: Bilicon Patil <bilpatil@in.ibm.com>                     -->
+<!-- *HWP Team: PM                                                          -->
+<!-- *HWP Level: 1                                                          -->
+<!-- *HWP Consumed by: FSP:HS                                               -->
+
+<!-- Error definitions for p9_avsbus_lib procedure -->
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_PROCPM_EVID_READVOLTAGE_TIMEOUT</rc>
+    <description>
+    A timeout occured reading voltage from an AVSBus interface
+    </description>    
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_PROCPM_EVID_WRITEVOLTAGE_TIMEOUT</rc>
+    <description>
+    A timeout occured writing a voltage to an AVSBus interface
+    </description>    
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_PROCPM_EVID_IDLEFRAME_TIMEOUT</rc>
+    <description>
+    A timeout occured writing an idle from to an AVSBus interface
+    </description>    
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>
diff --git a/src/ppe/hwp/perv/p9_sbe_startclock_chiplets.C b/src/ppe/hwp/perv/p9_sbe_startclock_chiplets.C
new file mode 100644
index 0000000..f91cde3
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_startclock_chiplets.C
@@ -0,0 +1,53 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/perv/p9_sbe_startclock_chiplets.C $               */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_startclock_chiplets.C
+///
+/// @brief Start clock procedure for XBUS, OBUS, PCIe
+//------------------------------------------------------------------------------
+// *HWP HWP Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner         : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team             : Perv
+// *HWP Level            : 1
+// *HWP Consumed by      : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_startclock_chiplets.H"
+
+
+
+fapi2::ReturnCode p9_sbe_startclock_chiplets(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV> & i_target_chiplets)
+{
+    FAPI_DBG("Entering ...");
+
+    FAPI_DBG("Exiting ...");
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+}
diff --git a/src/ppe/hwp/perv/p9_sbe_startclock_chiplets.H b/src/ppe/hwp/perv/p9_sbe_startclock_chiplets.H
new file mode 100644
index 0000000..2e7a413
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_startclock_chiplets.H
@@ -0,0 +1,60 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/perv/p9_sbe_startclock_chiplets.H $               */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_startclock_chiplets.H
+///
+/// @brief Start clock procedure for XBUS, OBUS, PCIe
+//------------------------------------------------------------------------------
+// *HWP HWP Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner         : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team             : Perv
+// *HWP Level            : 1
+// *HWP Consumed by      : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_STARTCLOCK_CHIPLETS_H_
+#define _P9_SBE_STARTCLOCK_CHIPLETS_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_startclock_chiplets_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV> &);
+
+/// @brief Start Xbus, Obus, PCIe clocks
+/// Start clocks on configured chiplets for all chips (master and slaves)
+///
+/// @param[in]     i_target_chiplets   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_startclock_chiplets(const
+            fapi2::Target<fapi2::TARGET_TYPE_PERV> & i_target_chiplets);
+}
+
+#endif
diff --git a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.C b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.C
index 4756b0b..bfb01b6 100644
--- a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.C
+++ b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.C
@@ -25,28 +25,62 @@
 //------------------------------------------------------------------------------
 /// @file  p9_sbe_tp_chiplet_init1.C
 ///
-/// @brief IPL STEP 2.3: SBE TP Chiplet Init 1 :: Releases PCB Reset, Sets TP chiplet enable, Drops Perv chiplet fence
-// *!
-// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
-// *! BACKUP NAME :                   Email:
+/// @brief Initial steps of PIB AND PCB
 //------------------------------------------------------------------------------
-// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
-// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
-// *HWP Team        : Perv
-// *HWP Level       : 1
-// *HWP Consumed by : SBE
+// *HWP HWP Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner         : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team             : Perv
+// *HWP Level            : 2
+// *HWP Consumed by      : SBE
 //------------------------------------------------------------------------------
 
 
 //## auto_generated
 #include "p9_sbe_tp_chiplet_init1.H"
+
+#include "perv_scom_addresses.H"
+
+
 fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const
         fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip)
 {
-    FAPI_DBG("p9_sbe_tp_chiplet_init1: Entering ...");
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_DBG("Entering ...");
+
+    //Setting ROOT_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+    l_data64.clearBit<15>();  //PIB.ROOT_CTRL0.VDD2VIO_LVL_FENCE_DC = 0
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+
+    FAPI_INF("Release PCB Reset");
+    //Setting ROOT_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+    l_data64.clearBit<30>();  //PIB.ROOT_CTRL0.PCB_RESET_DC = 0
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+
+    FAPI_INF("Set Chiplet Enable");
+    //Setting PERV_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
+    l_data64.setBit<0>();  //PIB.PERV_CTRL0.TP_CHIPLET_EN_DC = 1
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
+
+    FAPI_INF("Drop TP Chiplet Fence Enable");
+    //Setting PERV_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
+    l_data64.clearBit<18>();  //PIB.PERV_CTRL0.TP_FENCE_EN_DC = 0
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
+
+    FAPI_INF("Drop Global Endpoint reset");
+    //Setting ROOT_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+    l_data64.clearBit<31>();  //PIB.ROOT_CTRL0.GLOBAL_EP_RESET_DC = 0
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+    FAPI_INF("Switching PIB trace bus to SBE tracing");
 
-    FAPI_DBG("p9_sbe_tp_chiplet_init1: Exiting ...");
+    FAPI_DBG("Exiting ...");
 
-    return fapi2::FAPI2_RC_SUCCESS;
+fapi_try_exit:
+    return fapi2::current_err;
 
 }
diff --git a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.H b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.H
index 601c167..11547f3 100644
--- a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.H
+++ b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.H
@@ -25,16 +25,14 @@
 //------------------------------------------------------------------------------
 /// @file  p9_sbe_tp_chiplet_init1.H
 ///
-/// @brief IPL STEP 2.3: SBE TP Chiplet Init 1 :: Releases PCB Reset, Sets TP chiplet enable, Drops Perv chiplet fence
-// *!
-// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
-// *! BACKUP NAME :                   Email:
+/// @brief Initial steps of PIB AND PCB
 //------------------------------------------------------------------------------
-// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
-// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
-// *HWP Team        : Perv
-// *HWP Level       : 1
-// *HWP Consumed by : SBE
+// *HWP HWP Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner         : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team             : Perv
+// *HWP Level            : 2
+// *HWP Consumed by      : SBE
 //------------------------------------------------------------------------------
 
 
@@ -48,11 +46,10 @@
 typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_init1_FP_t)(
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &);
 
-/// @brief DESCRIPTION  -- Drop VSS2VIO fence
-///                        -- Releases PCB reset
-///                        -- Sets PRV Chiplet Enable
-///                        -- Drops PRV Chiplet fence enable
-///                        -- Drop Global Endpoint Reset
+/// @brief Releases the Pervasive Control Bus (PCB) reset
+/// Sets TP chiplet enable
+/// Drops pervasive chiplet fences
+///
 ///
 /// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
 /// @return  FAPI2_RC_SUCCESS if success, else error code.
diff --git a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.C b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.C
index bc90079..358885e 100644
--- a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.C
+++ b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.C
@@ -25,28 +25,37 @@
 //------------------------------------------------------------------------------
 /// @file  p9_sbe_tp_chiplet_reset.C
 ///
-/// @brief IPL STEP 2.8 : SBE TP Chiplet Reset :: setup hangcounter 6 for TP chiplet
-// *!
-// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
-// *! BACKUP NAME :                   Email:
+/// @brief setup hangcounter 6 for TP chiplet
 //------------------------------------------------------------------------------
-// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
-// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
-// *HWP Team        : Perv
-// *HWP Level       : 1
-// *HWP Consumed by : SBE
+// *HWP HWP Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner         : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team             : Perv
+// *HWP Level            : 2
+// *HWP Consumed by      : SBE
 //------------------------------------------------------------------------------
 
 
 //## auto_generated
 #include "p9_sbe_tp_chiplet_reset.H"
+
+#include "perv_scom_addresses.H"
+
+
 fapi2::ReturnCode p9_sbe_tp_chiplet_reset(const
         fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip)
 {
-    FAPI_DBG("p9_sbe_tp_chiplet_reset: Entering ...");
+    FAPI_DBG("Entering ...");
+
+    FAPI_INF("Initializing Hangcounter 6 for PRV Cplt");
+    //Setting HANG_PULSE_6_REG register value
+    //PERV.HANG_PULSE_6_REG = HANG_PULSE_VALUE
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_HANG_PULSE_6_REG,
+                            HANG_PULSE_VALUE));
 
-    FAPI_DBG("p9_sbe_tp_chiplet_reset: Exiting ...");
+    FAPI_DBG("Exiting ...");
 
-    return fapi2::FAPI2_RC_SUCCESS;
+fapi_try_exit:
+    return fapi2::current_err;
 
 }
diff --git a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.H b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.H
index 9f3c7ae..b972831 100644
--- a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.H
+++ b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.H
@@ -25,16 +25,14 @@
 //------------------------------------------------------------------------------
 /// @file  p9_sbe_tp_chiplet_reset.H
 ///
-/// @brief IPL STEP 2.8 : SBE TP Chiplet Reset :: setup hangcounter 6 for TP chiplet
-// *!
-// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
-// *! BACKUP NAME :                   Email:
+/// @brief setup hangcounter 6 for TP chiplet
 //------------------------------------------------------------------------------
-// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
-// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
-// *HWP Team        : Perv
-// *HWP Level       : 1
-// *HWP Consumed by : SBE
+// *HWP HWP Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner         : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team             : Perv
+// *HWP Level            : 2
+// *HWP Consumed by      : SBE
 //------------------------------------------------------------------------------
 
 
@@ -45,10 +43,15 @@
 #include <fapi2.H>
 
 
+enum P9_SBE_TP_CHIPLET_RESET_Constants
+{
+    HANG_PULSE_VALUE = 0x0c00000000000000
+};
+
 typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_reset_FP_t)(
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &);
 
-/// @brief --Setup hang counter for PCB slaves/master
+/// @brief Setup hang counter for PCB slaves/master
 ///
 ///
 /// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
diff --git a/src/ppe/hwp/perv/p9_sbe_tp_enable_ridi.C b/src/ppe/hwp/perv/p9_sbe_tp_enable_ridi.C
new file mode 100644
index 0000000..7fb1bcc
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_tp_enable_ridi.C
@@ -0,0 +1,64 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/perv/p9_sbe_tp_enable_ridi.C $                    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_enable_ridi.C
+///
+/// @brief enables ridi bits in RC regs after scan initialize and start clock the pervasive chiplet
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner         : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team             : Perv
+// *HWP Level            : 2
+// *HWP Consumed by      : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_tp_enable_ridi.H"
+
+#include "perv_scom_addresses.H"
+
+
+fapi2::ReturnCode p9_sbe_tp_enable_ridi(const
+                                        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_DBG("Entering ...");
+
+    FAPI_INF("Enable Recievers, Drivers DI1 & DI2");
+    //Setting ROOT_CTRL1 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL1_SCOM, l_data64));
+    l_data64.setBit<19>();  //PIB.ROOT_CTRL1.TP_RI_DC_B = 1
+    l_data64.setBit<20>();  //PIB.ROOT_CTRL1.TP_DI1_DC_B = 1
+    l_data64.setBit<21>();  //PIB.ROOT_CTRL1.TP_DI2_DC_B = 1
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL1_SCOM, l_data64));
+
+    FAPI_DBG("Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/ppe/hwp/perv/p9_sbe_tp_enable_ridi.H b/src/ppe/hwp/perv/p9_sbe_tp_enable_ridi.H
new file mode 100644
index 0000000..d96bb51
--- /dev/null
+++ b/src/ppe/hwp/perv/p9_sbe_tp_enable_ridi.H
@@ -0,0 +1,59 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwp/perv/p9_sbe_tp_enable_ridi.H $                    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_enable_ridi.H
+///
+/// @brief enables ridi bits in RC regs after scan initialize and start clock the pervasive chiplet
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner         : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team             : Perv
+// *HWP Level            : 2
+// *HWP Consumed by      : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_TP_ENABLE_RIDI_H_
+#define _P9_SBE_TP_ENABLE_RIDI_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_tp_enable_ridi_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &);
+
+/// @brief Enable drivers/receivers for PRV chiplet
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_tp_enable_ridi(const
+                                            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip);
+}
+
+#endif
diff --git a/src/ppe/hwp/perv/pervasive.act b/src/ppe/hwp/perv/pervasive.act
new file mode 100644
index 0000000..9c19ccc
--- /dev/null
+++ b/src/ppe/hwp/perv/pervasive.act
@@ -0,0 +1,472 @@
+# =============================================================================
+# Simics action for p9_sbe_arrayinit and p9_sbe_chiplet_init
+# =============================================================================
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM ARRAY INIT for N0]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x02030002)]
+# OPCG_REG0.RUNN_MODE = 1
+CAUSE: TARGET=[REG(0x02030002)]  OP=[BIT,ON] BIT=[0]
+# OPCG_REG0.OPCG_STARTS_BIST = 1
+CAUSE: TARGET=[REG(0x02030002)]  OP=[BIT,ON] BIT=[14]
+# OPCG_REG0.OPCG_GO = 1
+CAUSE: TARGET=[REG(0x02030002)] OP=[BIT,ON] BIT=[1]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x02000100)] OP=[BIT,ON] BIT=[8]
+# SRAM Abist Done
+EFFECT: TARGET=[REG(0x02000100)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM SCAN0 MODULE for N0]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x02030002)]
+# OPCG_REG0.RUN_SCAN0 = 1
+CAUSE: TARGET=[REG(0x02030002)]  OP=[BIT,ON] BIT=[2]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x02000100)] OP=[BIT,ON] BIT=[8]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM ARRAY INIT for N1]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x03030002)]
+# # OPCG_REG0.RUNN_MODE = 1
+CAUSE: TARGET=[REG(0x03030002)]  OP=[BIT,ON] BIT=[0]
+# OPCG_REG0.OPCG_STARTS_BIST = 1
+CAUSE: TARGET=[REG(0x03030002)]  OP=[BIT,ON] BIT=[14]
+# OPCG_REG0.OPCG_GO = 1
+CAUSE: TARGET=[REG(0x03030002)] OP=[BIT,ON] BIT=[1]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x03000100)] OP=[BIT,ON] BIT=[8]
+# SRAM Abist Done
+EFFECT: TARGET=[REG(0x03000100)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM SCAN0 MODULE for N1]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x03030002)]
+# OPCG_REG0.RUN_SCAN0 = 1
+CAUSE: TARGET=[REG(0x03030002)]  OP=[BIT,ON] BIT=[2]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x03000100)] OP=[BIT,ON] BIT=[8]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM ARRAY INIT for N2]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x04030002)]
+# OPCG_REG0.RUNN_MODE = 1
+CAUSE: TARGET=[REG(0x04030002)]  OP=[BIT,ON] BIT=[0]
+# OPCG_REG0.OPCG_STARTS_BIST = 1
+CAUSE: TARGET=[REG(0x04030002)]  OP=[BIT,ON] BIT=[14]
+# OPCG_REG0.OPCG_GO = 1
+CAUSE: TARGET=[REG(0x04030002)] OP=[BIT,ON] BIT=[1]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x04000100)] OP=[BIT,ON] BIT=[8]
+# SRAM Abist Done
+EFFECT: TARGET=[REG(0x04000100)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM SCAN0 MODULE for N2]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x04030002)]
+# OPCG_REG0.RUN_SCAN0 = 1
+CAUSE: TARGET=[REG(0x04030002)]  OP=[BIT,ON] BIT=[2]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x04000100)] OP=[BIT,ON] BIT=[8]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM ARRAY INIT for N3]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x05030002)]
+# OPCG_REG0.RUNN_MODE = 1
+CAUSE: TARGET=[REG(0x05030002)]  OP=[BIT,ON] BIT=[0]
+# OPCG_REG0.OPCG_STARTS_BIST = 1
+CAUSE: TARGET=[REG(0x05030002)]  OP=[BIT,ON] BIT=[14]
+# OPCG_REG0.OPCG_GO = 1
+CAUSE: TARGET=[REG(0x05030002)] OP=[BIT,ON] BIT=[1]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x05000100)] OP=[BIT,ON] BIT=[8]
+# SRAM Abist Done
+EFFECT: TARGET=[REG(0x05000100)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM SCAN0 MODULE for N3]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x05030002)]
+# OPCG_REG0.RUN_SCAN0 = 1
+CAUSE: TARGET=[REG(0x05030002)]  OP=[BIT,ON] BIT=[2]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x05000100)] OP=[BIT,ON] BIT=[8]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM ARRAY INIT for XB]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x06030002)]
+# OPCG_REG0.RUNN_MODE = 1
+CAUSE: TARGET=[REG(0x06030002)]  OP=[BIT,ON] BIT=[0]
+# OPCG_REG0.OPCG_STARTS_BIST = 1
+CAUSE: TARGET=[REG(0x06030002)]  OP=[BIT,ON] BIT=[14]
+# OPCG_REG0.OPCG_GO = 1
+CAUSE: TARGET=[REG(0x06030002)] OP=[BIT,ON] BIT=[1]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x06000100)] OP=[BIT,ON] BIT=[8]
+# SRAM Abist Done
+EFFECT: TARGET=[REG(0x06000100)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM SCAN0 MODULE for XB]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x06030002)]
+OPCG_REG0.RUN_SCAN0 = 1
+CAUSE: TARGET=[REG(0x06030002)]  OP=[BIT,ON] BIT=[2]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x06000100)] OP=[BIT,ON] BIT=[8]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM ARRAY INIT for MC01]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x07030002)]
+# OPCG_REG0.RUNN_MODE = 1
+CAUSE: TARGET=[REG(0x07030002)]  OP=[BIT,ON] BIT=[0]
+# OPCG_REG0.OPCG_STARTS_BIST = 1
+CAUSE: TARGET=[REG(0x07030002)]  OP=[BIT,ON] BIT=[14]
+# OPCG_REG0.OPCG_GO = 1
+CAUSE: TARGET=[REG(0x07030002)] OP=[BIT,ON] BIT=[1]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x07000100)] OP=[BIT,ON] BIT=[8]
+# SRAM Abist Done
+EFFECT: TARGET=[REG(0x07000100)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM SCAN0 MODULE for MC01]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x07030002)]
+# OPCG_REG0.RUN_SCAN0 = 1
+CAUSE: TARGET=[REG(0x07030002)]  OP=[BIT,ON] BIT=[2]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x07000100)] OP=[BIT,ON] BIT=[8]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM ARRAY INIT for MC029]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x08030002)]
+# OPCG_REG0.RUNN_MODE = 1
+CAUSE: TARGET=[REG(0x08030002)]  OP=[BIT,ON] BIT=[0]
+# OPCG_REG0.OPCG_STARTS_BIST = 1
+CAUSE: TARGET=[REG(0x08030002)]  OP=[BIT,ON] BIT=[14]
+# OPCG_REG0.OPCG_GO = 1
+CAUSE: TARGET=[REG(0x08030002)] OP=[BIT,ON] BIT=[1]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x08000100)] OP=[BIT,ON] BIT=[8]
+# SRAM Abist Done
+EFFECT: TARGET=[REG(0x08000100)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM SCAN0 MODULE for MC029]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x08030002)]
+# OPCG_REG0.RUN_SCAN0 = 1
+CAUSE: TARGET=[REG(0x08030002)]  OP=[BIT,ON] BIT=[2]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x08000100)] OP=[BIT,ON] BIT=[8]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM ARRAY INIT for OB0]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x09030002)]
+#OPCG_REG0.RUNN_MODE = 1
+CAUSE: TARGET=[REG(0x09030002)]  OP=[BIT,ON] BIT=[0]
+# OPCG_REG0.OPCG_STARTS_BIST = 1
+CAUSE: TARGET=[REG(0x09030002)]  OP=[BIT,ON] BIT=[14]
+# OPCG_REG0.OPCG_GO = 1
+CAUSE: TARGET=[REG(0x09030002)] OP=[BIT,ON] BIT=[1]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x09000100)] OP=[BIT,ON] BIT=[8]
+# SRAM Abist Done
+EFFECT: TARGET=[REG(0x09000100)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM SCAN0 MODULE for OB0]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x09030002)]
+# OPCG_REG0.RUN_SCAN0 = 1
+CAUSE: TARGET=[REG(0x09030002)]  OP=[BIT,ON] BIT=[2]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x09000100)] OP=[BIT,ON] BIT=[8]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM ARRAY INIT for OB1]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x0A030002)]
+# OPCG_REG0.RUNN_MODE = 1
+CAUSE: TARGET=[REG(0x0A030002)]  OP=[BIT,ON] BIT=[0]
+# OPCG_REG0.OPCG_STARTS_BIST = 1
+CAUSE: TARGET=[REG(0x0A030002)]  OP=[BIT,ON] BIT=[14]
+# OPCG_REG0.OPCG_GO = 1
+CAUSE: TARGET=[REG(0x0A030002)] OP=[BIT,ON] BIT=[1]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x0A000100)] OP=[BIT,ON] BIT=[8]
+# SRAM Abist Done
+EFFECT: TARGET=[REG(0x0A000100)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM SCAN0 MODULE for OB1]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x0A030002)]
+# OPCG_REG0.RUN_SCAN0 = 1
+CAUSE: TARGET=[REG(0x0A030002)]  OP=[BIT,ON] BIT=[2]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x0A000100)] OP=[BIT,ON] BIT=[8]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM ARRAY INIT for OB2]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x0B030002)]
+# OPCG_REG0.RUNN_MODE = 1
+CAUSE: TARGET=[REG(0x0B030002)]  OP=[BIT,ON] BIT=[0]
+# OPCG_REG0.OPCG_STARTS_BIST = 1
+CAUSE: TARGET=[REG(0x0B030002)]  OP=[BIT,ON] BIT=[14]
+# OPCG_REG0.OPCG_GO = 1
+CAUSE: TARGET=[REG(0x0B030002)] OP=[BIT,ON] BIT=[1]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x0B000100)] OP=[BIT,ON] BIT=[8]
+# SRAM Abist Done
+EFFECT: TARGET=[REG(0x0B000100)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM SCAN0 MODULE for OB2]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x0B030002)]
+# OPCG_REG0.RUN_SCAN0 = 1
+CAUSE: TARGET=[REG(0x0B030002)]  OP=[BIT,ON] BIT=[2]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x0B000100)] OP=[BIT,ON] BIT=[8]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM ARRAY INIT for OB3]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x0C030002)]
+# OPCG_REG0.RUNN_MODE = 1
+CAUSE: TARGET=[REG(0x0C030002)]  OP=[BIT,ON] BIT=[0]
+# OPCG_REG0.OPCG_STARTS_BIST = 1
+CAUSE: TARGET=[REG(0x0C030002)]  OP=[BIT,ON] BIT=[14]
+# OPCG_REG0.OPCG_GO = 1
+CAUSE: TARGET=[REG(0x0C030002)] OP=[BIT,ON] BIT=[1]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x0C000100)] OP=[BIT,ON] BIT=[8]
+# SRAM Abist Done
+EFFECT: TARGET=[REG(0x0C000100)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM SCAN0 MODULE for OB3]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x0C030002)]
+# OPCG_REG0.RUN_SCAN0 = 1
+CAUSE: TARGET=[REG(0x0C030002)]  OP=[BIT,ON] BIT=[2]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x0C000100)] OP=[BIT,ON] BIT=[8]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM ARRAY INIT for PCI0]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x0D030002)]
+# OPCG_REG0.RUNN_MODE = 1
+CAUSE: TARGET=[REG(0x0D030002)]  OP=[BIT,ON] BIT=[0]
+# OPCG_REG0.OPCG_STARTS_BIST = 1
+CAUSE: TARGET=[REG(0x0D030002)]  OP=[BIT,ON] BIT=[14]
+# OPCG_REG0.OPCG_GO = 1
+CAUSE: TARGET=[REG(0x0D030002)] OP=[BIT,ON] BIT=[1]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x0D000100)] OP=[BIT,ON] BIT=[8]
+# SRAM Abist Done
+EFFECT: TARGET=[REG(0x0D000100)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM SCAN0 MODULE for PCI0]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x0D030002)]
+# OPCG_REG0.RUN_SCAN0 = 1
+CAUSE: TARGET=[REG(0x0D030002)]  OP=[BIT,ON] BIT=[2]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x0D000100)] OP=[BIT,ON] BIT=[8]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM ARRAY INIT for PCI1]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x0E030002)]
+# OPCG_REG0.RUNN_MODE = 1
+CAUSE: TARGET=[REG(0x0E030002)]  OP=[BIT,ON] BIT=[0]
+# OPCG_REG0.OPCG_STARTS_BIST = 1
+CAUSE: TARGET=[REG(0x0E030002)]  OP=[BIT,ON] BIT=[14]
+# OPCG_REG0.OPCG_GO = 1
+CAUSE: TARGET=[REG(0x0E030002)] OP=[BIT,ON] BIT=[1]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x0E000100)] OP=[BIT,ON] BIT=[8]
+# SRAM Abist Done
+EFFECT: TARGET=[REG(0x0E000100)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM SCAN0 MODULE for PCI1]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x0E030002)]
+# OPCG_REG0.RUN_SCAN0 = 1
+CAUSE: TARGET=[REG(0x0E030002)]  OP=[BIT,ON] BIT=[2]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x0E000100)] OP=[BIT,ON] BIT=[8]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM ARRAY INIT for PCI2]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x0F030002)]
+# OPCG_REG0.RUNN_MODE = 1
+CAUSE: TARGET=[REG(0x0F030002)]  OP=[BIT,ON] BIT=[0]
+# OPCG_REG0.OPCG_STARTS_BIST = 1
+CAUSE: TARGET=[REG(0x0F030002)]  OP=[BIT,ON] BIT=[14]
+# OPCG_REG0.OPCG_GO = 1
+CAUSE: TARGET=[REG(0x0F030002)] OP=[BIT,ON] BIT=[1]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x0F000100)] OP=[BIT,ON] BIT=[8]
+# SRAM Abist Done
+EFFECT: TARGET=[REG(0x0F000100)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM SCAN0 MODULE for PCI2]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x0F030002)]
+# OPCG_REG0.RUN_SCAN0 = 1
+CAUSE: TARGET=[REG(0x0F030002)]  OP=[BIT,ON] BIT=[2]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x0F000100)] OP=[BIT,ON] BIT=[8]
+}
+
+
+# =============================================================================
+# Simics action for p9_sbe_tp_arrayinit
+# =============================================================================
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM ARRAY INIT]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x01030002)]
+# OPCG_REG0.RUNN_MODE = 1
+CAUSE: TARGET=[REG(0x01030002)]  OP=[BIT,ON] BIT=[0]
+# OPCG_REG0.OPCG_STARTS_BIST = 1
+CAUSE: TARGET=[REG(0x01030002)]  OP=[BIT,ON] BIT=[14]
+# OPCG_REG0.OPCG_GO = 1
+CAUSE: TARGET=[REG(0x01030002)]  OP=[BIT,ON] BIT=[1]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x01000100)] OP=[BIT,ON] BIT=[8]
+# SRAM Abist Done
+EFFECT: TARGET=[REG(0x01000100)] OP=[BIT,ON] BIT=[0]
+}
+
+# This cause-effect block is also used for "p9_sbe_tp_chiplet_init2.C"
+CAUSE_EFFECT{
+LABEL=[SEEPROM SCAN0 MODULE]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x01030002)]
+# OPCG_REG0.RUN_SCAN0 = 1
+CAUSE: TARGET=[REG(0x01030002)]  OP=[BIT,ON] BIT=[2]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x01000100)] OP=[BIT,ON] BIT=[8]
+}
+
+
+# =============================================================================
+# Simics action for p9_sbe_tp_chiplet_init3
+# =============================================================================
+
+CAUSE_EFFECT{
+LABEL=[Common_Clock_Start_AllRegions]
+# Watch PERV_CLK_REGION register
+WATCH=[REG(0x01030006)]
+# Setup all Clock Domains and Clock Types
+CAUSE: TARGET=[REG(0x01030006)]  OP=[EQUALTO,BUF] DATA=[LITERAL(64,0x4FFF0000 0x0000E000)]
+# Clock running status for SL type should match with expected values.
+EFFECT: TARGET=[REG(0x01030008)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0xF001FFFF 0xFFFFFFFF)]
+# Clock running status for NSL type should match with expected values.
+EFFECT: TARGET=[REG(0x01030009)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0xF001FFFF 0xFFFFFFFF])
+# Clock running status for ARY type should match with expected values.
+EFFECT: TARGET=[REG(0x0103000A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0xF001FFFF 0xFFFFFFFF)]
+}
+
+
+# =============================================================================
+# Simics action for p9_sbe_npll_setup
+# =============================================================================
+
+CAUSE_EFFECT{
+LABEL=[SS PLL lock]
+#Watch PERV_ROOT_CTRL8_SCOM register
+WATCH=[REG(0x00050018)]
+# PIB.ROOT_CTRL8.TP_PLL_TEST_ENABLE_DC = 0
+CAUSE: TARGET=[REG(0x00050018)]  OP=[BIT,OFF] BIT=[12]
+# PIB.ROOT_CTRL8.TP_SSPLL_PLL_RESET0_DC = 0
+CAUSE: TARGET=[REG(0x00050018)]  OP=[BIT,OFF] BIT=[0]
+# Check SS PLL lock
+EFFECT: TARGET=[REG(0x010F0019)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT{
+LABEL=[CP and IO PLL lock]
+# Watch PERV_ROOT_CTRL8_SCOM register
+WATCH=[REG(0x00050018)]
+# PIB.ROOT_CTRL8.TP_FILTPLL_PLL_RESET1_DC = 0
+CAUSE: TARGET=[REG(0x00050018)]  OP=[BIT,OFF] BIT=[4]
+# Check PLL_LOCK_REG register value
+EFFECT: TARGET=[REG(0x010F0019)] OP=[BIT,ON] BIT=[1]
+EFFECT: TARGET=[REG(0x010F0019)] OP=[BIT,ON] BIT=[2]
+}
+
+CAUSE_EFFECT{
+LABEL=[NEST PLL LOCK]
+# Watch PERV_ROOT_CTRL8_SCOM register
+WATCH=[REG(0x00050018)]
+# PIB.PERV_CTRL0.TP_PLLRST_DC = 0
+CAUSE: TARGET=[REG(0x00050018)]  OP=[BIT,OFF] BIT=[4]
+# Check NEST PLL lock
+EFFECT: TARGET=[REG(0x010F0019)] OP=[BIT,ON] BIT=[3]
+}
+
+# =============================================================================
+# Simics action for istep 4 shared modules
+# =============================================================================
+
+CAUSE_EFFECT{
+LABEL=[SEEPROM SCAN0 MODULE for EQ/CORE target]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(0x00030002)]
+# OPCG_REG0.RUN_SCAN0 = 1
+CAUSE: TARGET=[REG(0x00030002)]  OP=[BIT,ON] BIT=[2]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(0x00000100)] OP=[BIT,ON] BIT=[8]
+}
+
+
diff --git a/src/ppe/hwp/perv/perverrors.mk b/src/ppe/hwp/perv/perverrors.mk
new file mode 100644
index 0000000..6a21918
--- /dev/null
+++ b/src/ppe/hwp/perv/perverrors.mk
@@ -0,0 +1,41 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ppe/hwp/perv/perverrors.mk $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file perverrors.mk
+#
+#  @brief mk for including library common error files
+#
+#  @page ChangeLogs Change Logs
+#  @section perverrors.mk
+#
+##########################################################################
+# Error Files
+##########################################################################
+
+PERV_CURR_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+
+# This variable name must not change
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_setup_evid_errors.xml
+
+
diff --git a/src/ppe/hwp/perv/pervfiles.mk b/src/ppe/hwp/perv/pervfiles.mk
index c99113c..2112360 100644
--- a/src/ppe/hwp/perv/pervfiles.mk
+++ b/src/ppe/hwp/perv/pervfiles.mk
@@ -36,35 +36,40 @@
 # Object Files
 ##########################################################################
 
-PERV-CPP-SOURCES = p9_sbe_setup_evid.C
+PERV-CPP-SOURCES =p9_sbe_arrayinit.C
 PERV-CPP-SOURCES +=p9_sbe_attr_setup.C
-PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init1.C
 PERV-CPP-SOURCES +=p9_sbe_check_master.C
-PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init2.C
+PERV-CPP-SOURCES +=p9_sbe_chiplet_init.C
+PERV-CPP-SOURCES +=p9_sbe_chiplet_pll_initf.C
+PERV-CPP-SOURCES +=p9_sbe_chiplet_pll_setup.C
+PERV-CPP-SOURCES +=p9_sbe_chiplet_reset.C
 PERV-CPP-SOURCES +=p9_sbe_enable_seeprom.C
-PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init3.C
+PERV-CPP-SOURCES +=p9_sbe_gptr_time_repr_initf.C
 PERV-CPP-SOURCES +=p9_sbe_lpc_init.C
+PERV-CPP-SOURCES +=p9_sbe_nest_enable_ridi.C
+PERV-CPP-SOURCES +=p9_sbe_nest_initf.C
+PERV-CPP-SOURCES +=p9_sbe_nest_startclocks.C
+PERV-CPP-SOURCES +=p9_sbe_npll_initf.C
+PERV-CPP-SOURCES +=p9_sbe_npll_setup.C
+PERV-CPP-SOURCES +=p9_sbe_select_ex.C
+PERV-CPP-SOURCES +=p9_sbe_startclock_chiplets.C
+PERV-CPP-SOURCES +=p9_sbe_tp_arrayinit.C
+PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init1.C
+PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init2.C
+PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init3.C
 PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_reset.C
-PERV-CPP-SOURCES +=p9_sbe_nest_arrayinit.C
+PERV-CPP-SOURCES +=p9_sbe_tp_enable_ridi.C
 PERV-CPP-SOURCES +=p9_sbe_tp_gptr_time_repr_initf.C
-PERV-CPP-SOURCES +=p9_sbe_nest_chiplet_init.C
 PERV-CPP-SOURCES +=p9_sbe_tp_initf.C
-PERV-CPP-SOURCES +=p9_sbe_nest_chiplet_reset.C
 PERV-CPP-SOURCES +=p9_sbe_tp_ld_image.C
-PERV-CPP-SOURCES +=p9_sbe_nest_gptr_time_repr_initf.C
 PERV-CPP-SOURCES +=p9_sbe_tp_switch_gears.C
-PERV-CPP-SOURCES +=p9_sbe_nest_initf.C
 PERV-CPP-SOURCES +=p9_select_boot_master.C
-PERV-CPP-SOURCES +=p9_sbe_nest_startclocks.C
 PERV-CPP-SOURCES +=p9_select_clock_mux.C
-PERV-CPP-SOURCES +=p9_sbe_npll_initf.C
 PERV-CPP-SOURCES +=p9_set_fsi_gp_shadow.C
-PERV-CPP-SOURCES +=p9_sbe_npll_setup.C
 PERV-CPP-SOURCES +=p9_setup_clock_term.C
-PERV-CPP-SOURCES +=p9_sbe_select_ex.C
 PERV-CPP-SOURCES +=p9_setup_sbe_config.C
-PERV-CPP-SOURCES +=p9_sbe_tp_arrayinit.C
 PERV-CPP-SOURCES +=p9_start_cbs.C
+PERV-CPP-SOURCES +=p9_sbe_setup_evid.C
 
 PERV-C-SOURCES =
 PERV-S-SOURCES =
diff --git a/src/ppe/hwp/utils/utilserrors.mk b/src/ppe/hwp/utils/utilserrors.mk
new file mode 100644
index 0000000..3e5ec8d
--- /dev/null
+++ b/src/ppe/hwp/utils/utilserrors.mk
@@ -0,0 +1,39 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ppe/hwp/utils/utilserrors.mk $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file utilserrors.mk
+#
+#  @brief mk for including utils error files
+#
+#  @page ChangeLogs Change Logs
+#  @section utilserrors.mk
+#
+##########################################################################
+# Error Files
+##########################################################################
+
+UTILS_CURR_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+
+# This variable name must not change
+#ERROR_XML_FILES += $(UTILS_CURR_DIR)/p9_XXX_errors.xml
diff --git a/src/ppe/hwpf/plat/include/buffer.H b/src/ppe/hwpf/plat/include/buffer.H
index 607107d..80b0f32 100644
--- a/src/ppe/hwpf/plat/include/buffer.H
+++ b/src/ppe/hwpf/plat/include/buffer.H
@@ -30,48 +30,118 @@
 #ifndef __FAPI2_INTEGRAL_BUFFER__
 #define __FAPI2_INTEGRAL_BUFFER__
 
-#include <buffer_base.H>
+#include <buffer_parameters.H>
+#include <buffer_traits.H>
 #include <return_code.H>
 
 namespace fapi2
 {
-    /// @brief Class representing a FAPI buffer<T>
-    /// @note Buffers support method chaining. So, rather than
-    /// this
-    /// @code
-    /// buffer<T> mask;
-    /// mask.setBit<B>();
-    /// mask.invert();
-    /// my_buffer &= mask;
-    /// @endcode
-    /// You can do
-    /// @code
-    /// my_buffer &= buffer<T>().setBit<B>.invert();
-    /// @endcode
-    template <typename T>
-    class buffer : public buffer_base<T>
-    {
+/// @brief Class representing a FAPI buffer<T>
+/// @tparam T, the integral type of the buffer (uint16_t, uint64_t, etc.)
+template <typename T, typename TT = bufferTraits<T> >
+class buffer
+{
     public:
-        /// Shortcut typedef to map to our traits class
-        typedef typename buffer_base<T, buffer>::bits_type bits_type;
+        /// Shortcut typedef to get to our traits class
+        typedef typename TT::bits_type bits_type;
 
         ///
         /// @brief Integral buffer assignment constructor
         /// @param[in] i_value initial value of the buffer
         /// Meaningless for variable types and thus protected.
         ///
-        inline buffer(T i_value = 0)
+        inline buffer(T i_value = 0):
+            iv_data(i_value)
+        {
+        }
+
+        ~buffer(void) = default;
+
+        #if !defined(DOXYGEN) && defined(FAPI2_DEBUG)
+        /// @brief Print the contents of the buffer to stdout
+        inline void print(void) const
+        {
+            TT::print(iv_data);
+        }
+        #endif
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return The contents of the buffer
+        ///
+        inline operator T() const
+        {
+            return iv_data;
+        }
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return The contents of the buffer
+        ///
+        inline operator T&()
+        {
+            return iv_data;
+        }
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return The contents of the buffer
+        ///
+        inline T& operator()(void)
+        {
+            return iv_data;
+        }
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return Reference to the contents of the buffer
+        ///
+        inline const T& operator()(void) const
+        {
+            return iv_data;
+        }
+
+        /// @name Buffer Manipulation Functions
+        ///@{
+
+        ///
+        /// @brief Set an OT of data in buffer
+        /// @param[in] i_value sizeof(OT) bits of data
+        /// @param[in] i_offset Start OT (start word, for example) in buffer
+        ///            - defaults to 0 (will by default write the left most element)
+        /// @return FAPI2_RC_SUCCESS on success, FAPI2_RC_OVERFLOW otherwise
+        /// @note This is is only available for integral types. To set a
+        ///    variable_buffer into a variable_buffer, use insert()
+        ///
+        template< typename OT>
+        inline fapi2::ReturnCode set(OT i_value, const bits_type i_offset = 0)
+        {
+            // Compile time check to make sure OT is integral
+            static_assert( std::is_integral<OT>::value,
+                           "Input must be an integral type" );
+
+            const uint32_t length = TT:: template size<OT>(iv_data);
+            static const bits_type bits_in_value = parameterTraits<OT>::bit_length();
+            const bits_type bit_length = TT::bit_length(iv_data);
+
+            if (i_offset + bits_in_value >= bit_length)
             {
-                // Why not an initializer list? That would force buffer_base<T>
-                // to have a ctor which took a T, and I want to avoid that in
-                // the generic case: this makes it more clear that the two
-                // ctor's (integral and container) behave very differently.
-                // variable_buffers also have a ctor which takes a single
-                // numerical value, and that represents a bit count, not an
-                // initial value.
-                this->iv_data = i_value;
+                return FAPI2_RC_OVERFLOW;
             }
 
+            // Create mask if part of this byte is not in the valid part of the buffer,
+            // Shift it left by the amount of unused bits,
+            // Clear the unused bits
+            if (((i_offset + 1) == length) && (bit_length % bits_in_value))
+            {
+                i_value &= parameterTraits<OT>::mask() << ((bits_in_value * length) -
+                           bit_length);
+            }
+
+            parameterTraits<OT>::template write_element<typename TT::unit_type>
+            (TT::get_address(iv_data), i_value, i_offset);
+            return FAPI2_RC_SUCCESS;
+        }
 
         /// @name Bit/Word Manipulation Functions
         ///@{
@@ -81,7 +151,9 @@ namespace fapi2
         /// @return Length in bits
         ///
         inline constexpr uint32_t getBitLength(void) const
-            { return bufferTraits<T>::bit_length(this->iv_data); }
+        {
+            return TT::bit_length(iv_data);
+        }
 
         ///
         /// @brief Return the length of the buffer in OT units
@@ -94,100 +166,198 @@ namespace fapi2
         template< typename OT >
         inline constexpr uint32_t getLength(void) const
         {
-            return bufferTraits<T>::template size<OT>(this->iv_data);
+            return TT::template size<OT>(iv_data);
         }
 
         ///
         /// @brief Templated setBit for integral types
         /// @tparam B the bit number to set.
+        /// @tparam C the count of bits to set, defaults to 1
         /// @return buffer& Useful for method chaining
         /// @note 0 is left-most
         /// @note Example: fapi2::buffer<uint64_t>().setBit<3>();
         ///
-        template <bits_type B>
+        template< bits_type B, bits_type C = 1 >
         inline buffer& setBit(void)
         {
             static_assert((B >= 0) &&
-                          (B < bufferTraits<T>::bits_per_unit), "failed range check");
+                          ((B + C - 1) < TT::bits_per_unit()), "failed range check");
 
-            // Force iv_data to be dependent on the template type to force
-            // its look up in the second phase
-            this->iv_data |= (static_cast<T>(1)) << (bufferTraits<T>::bits_per_unit - B - 1);
+            // This would be a candidate for a fast_mask (see variable_buffer) but
+            // we'd need tables for all the integral types which maybe we need to
+            // do ...
+            iv_data |= (T(~0) >> (TT::bits_per_unit() - C)) << (TT::bits_per_unit() - B -
+                       C);
             return *this;
         }
 
         ///
+        /// @brief Set a bit in the buffer
+        /// @param[in] i_bit the bit number to set.
+        /// @param[in] i_count the count of bits to set, defaults to 1
+        /// @note 0 is left-most
+        /// @return FAPI2_RC_SUCCESS if OK
+        ///
+        inline fapi2::ReturnCode setBit(const bits_type& i_bit,
+                                        const bits_type& i_count = 1)
+        {
+            if ((i_count + i_bit - 1) >= TT::bits_per_unit())
+            {
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            iv_data |= (T(~0) >> (TT::bits_per_unit() - i_count)) <<
+                       (TT::bits_per_unit() - i_bit - i_count);
+
+            return FAPI2_RC_SUCCESS;
+        }
+
+        ///
         /// @brief Clear a bit in buffer
         /// @tparam B Bit in buffer to clear.
+        /// @tparam C the count of bits to clear, defaults to 1
         /// @return buffer& Useful for method chaining
         /// @note Asserting that all the parameters are known at
         /// compile time so this can be templated only. If that is not
         /// the case we can add a function parameter version.
         ///
-        template< bits_type B >
+        template< bits_type B, bits_type C = 1>
         inline buffer& clearBit(void)
         {
             static_assert((B >= 0) &&
-                          (B < bufferTraits<T>::bits_per_unit), "failed range check");
+                          ((B + C - 1)< TT::bits_per_unit()), "failed range check");
 
-            this->iv_data &= buffer<T>().setBit<B>().invert();
+            iv_data &= buffer<T>().setBit<B, C>().invert();
             return *this;
         }
 
         ///
-        /// @brief Invert bit
-        /// @tparam B Bit in buffer to invert.
+        /// @brief Clear a bit in the buffer
+        /// @param[in] i_bit the bit number to clear.
+        /// @param[in] i_count the count of bits to clear, defaults to 1
+        /// @note 0 is left-most
+        /// @return FAPI2_RC_SUCCESS if OK
+        ///
+        inline fapi2::ReturnCode clearBit(const bits_type& i_bit,
+                                          const bits_type& i_count = 1)
+        {
+            if ((i_count + i_bit - 1) >= TT::bits_per_unit())
+            {
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            fapi2::buffer<T> l_scratch;
+
+            if (l_scratch.setBit(i_bit, i_count) != FAPI2_RC_SUCCESS)
+            {
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            iv_data &= l_scratch.invert();
+
+            return FAPI2_RC_SUCCESS;
+        }
+
+        ///
+        /// @brief Write a bit in buffer to a given value
+        /// @tparam B Bit in buffer to write
+        /// @tparam C the count of bits to write, defaults to 1
         /// @return buffer& Useful for method chaining
         /// @note Asserting that all the parameters are known at
         /// compile time so this can be templated only. If that is not
         /// the case we can add a function parameter version.
         ///
-        template< bits_type B >
-        inline buffer& flipBit(void)
+        template< bits_type B, bits_type C = 1 >
+        inline buffer& writeBit(const bool i_value)
         {
             static_assert((B >= 0) &&
-                          (B < bufferTraits<T>::bits_per_unit), "failed range check");
+                          ((B + C - 1)< TT::bits_per_unit()), "failed range check");
 
-            this->iv_data ^= buffer<T>().setBit<B>();
+            (i_value == 0) ? clearBit<B, C>() : setBit<B, C>();
             return *this;
         }
 
+
         ///
-        /// @brief Set a bit in the buffer
-        /// @param[in] i_bit the bit number to set.
-        /// @note 0 is left-most
-        /// @return FAPI2_RC_SUCCESS if OK
+        /// @brief Invert bit
+        /// @tparam B Bit in buffer to invert.
+        /// @tparam C the count of bits to flip, defaults to 1
+        /// @return buffer& Useful for method chaining
+        /// @note Asserting that all the parameters are known at
+        /// compile time so this can be templated only. If that is not
+        /// the case we can add a function parameter version.
         ///
-        inline fapi2::ReturnCode setBit(const bits_type& i_bit)
-            {
-                if (i_bit >= bufferTraits<T>::bits_per_unit)
-                {
-                    return FAPI2_RC_INVALID_PARAMETER;
-                }
-
-                // Force iv_data to be dependent on the template type to force
-                // its look up in the second phase
-                this->iv_data |=
-                    (static_cast<T>(1)) << (bufferTraits<T>::bits_per_unit - i_bit - 1);
-                return FAPI2_RC_SUCCESS;
-            }
+        template< bits_type B, bits_type C = 1 >
+        inline buffer& flipBit(void)
+        {
+            static_assert((B >= 0) &&
+                          ((B + C - 1) < TT::bits_per_unit()), "failed range check");
+
+            iv_data ^= buffer<T>().setBit<B, C>();
+            return *this;
+        }
 
         ///
         /// @brief Get the value of a bit in the buffer
         /// @tparam B Bit in buffer to get.
-        /// @return true if bit is on, false if bit is off
+        /// @tparam C the count of bits to get, defaults to 1
+        /// @return true if *any* bit is on, false if *every* bit is off
         ///
-        template< bits_type B >
+        template< bits_type B, bits_type C = 1>
         inline bool getBit(void) const
-            {
-                return buffer<T>().setBit<B>() & this->iv_data;
-            }
+        {
+            return buffer<T>().setBit<B, C>() & iv_data;
+        }
+
+        ///
+        /// @brief Set and entire buffer to X's
+        /// @tparam X {0,1} depending if you want to clear (0)
+        /// or fill (1) a buffer
+        /// @return buffer_base&, Useful for method chaining
+        ///
+        template< uint8_t X >
+        inline buffer& flush(void)
+        {
+            static_assert( (X == 1) || (X == 0), "bad argument to flush" );
+            (0 == X) ? TT::clear(iv_data) : TT::set(iv_data);
+            return *this;
+        }
+
+        ///
+        /// @brief Invert entire buffer
+        /// @return buffer_base&, Useful for method chaining
+        ///
+        inline buffer& invert(void)
+        {
+            TT::invert(iv_data);
+            return *this;
+        }
+
+        ///
+        /// @brief Bit reverse entire buffer
+        /// @return buffer_base&, Useful for method chaining
+        ///
+        inline buffer& reverse(void)
+        {
+            TT::reverse(iv_data);
+            return *this;
+        }
+
 
         ///@}
 
         /// @name Buffer Manipulation Functions
         ///@{
 
+        ///
+        /// @brief Get a pointer to the buffer bits
+        /// @return Pointer to the buffer itself
+        ///
+        inline T* pointer(void)
+        {
+            return &iv_data;
+        }
+
         // Note: Many (all?) of these are not needed and the compiler complains
         // as the cast to T yields a better operator. There are here mainly for
         // documenation purposes.
@@ -195,104 +365,102 @@ namespace fapi2
         ///
         /// @brief operator>>()
         ///
-#ifdef DOXYGEN
-        buffer<T>& operator>>(bits_type i_shiftnum);
-#endif
+        #ifdef DOXYGEN
+        inline buffer<T>& operator>>(bits_type i_shiftnum);
+        #endif
 
         ///
         /// @brief operator<<()
         ///
-#ifdef DOXYGEN
-        buffer<T>& operator<<(bits_type i_shiftnum);
-#endif
+        #ifdef DOXYGEN
+        inline buffer<T>& operator<<(bits_type i_shiftnum);
+        #endif
 
         ///
         /// @brief operator+()
         ///
-#ifdef DOXYGEN
-        buffer<T>& operator+(const T& rhs);
-#endif
+        #ifdef DOXYGEN
+        inline buffer<T>& operator+(const T& rhs);
+        #endif
 
         ///
         /// @brief operator+=()
         ///
-#ifdef DOXYGEN
-        buffer<T>& operator+=(const T& rhs);
-#endif
+        #ifdef DOXYGEN
+        inline buffer<T>& operator+=(const T& rhs);
+        #endif
 
         ///
         /// @brief operator|=()
         ///
-#ifdef DOXYGEN
-        buffer<T>& operator|=(const T& rhs);
-#endif
+        #ifdef DOXYGEN
+        inline buffer<T>& operator|=(const T& rhs);
+        #endif
 
         ///
         /// @brief operator&=()
         ///
-#ifdef DOXYGEN
-        buffer<T>& operator&=(const T& rhs);
-#endif
+        #ifdef DOXYGEN
+        inline buffer<T>& operator&=(const T& rhs);
+        #endif
 
         ///
         /// @brief operator|()
         ///
-#ifdef DOXYGEN
-        buffer<T>& operator|(const T& rhs);
-#endif
+        #ifdef DOXYGEN
+        inline buffer<T>& operator|(const T& rhs);
+        #endif
 
         ///
         /// @brief operator&()
         ///
-#ifdef DOXYGEN
-        buffer<T>& operator&(const T& rhs);
-#endif
+        #ifdef DOXYGEN
+        inline buffer<T>& operator&(const T& rhs);
+        #endif
 
         ///
         /// @brief operator^=()
         ///
-#ifdef DOXYGEN
-        buffer<T>& operator^=(const T& rhs);
-#endif
+        #ifdef DOXYGEN
+        inline buffer<T>& operator^=(const T& rhs);
+        #endif
 
         ///
         /// @brief operator~()
         ///
-#ifdef DOXYGEN
-        buffer<T>& operator~(const T& rhs) const;
-#endif
+        #ifdef DOXYGEN
+        inline buffer<T>& operator~(const T& rhs) const;
+        #endif
 
         ///
         /// @brief operator==()
         ///
-#ifdef DOXYGEN
-        bool operator==(const T& rhs) const;
-#endif
+        #ifdef DOXYGEN
+        inline bool operator==(const T& rhs) const;
+        #endif
 
         ///
         /// @brief operator!=()
         ///
-#ifdef DOXYGEN
-        bool operator!=(const T& rhs) const;
-#endif
+        #ifdef DOXYGEN
+        inline bool operator!=(const T& rhs) const;
+        #endif
 
         ///
         /// @brief Copy part of a OT into the DataBuffer
         /// @tparam TS Start bit to insert into (target start)
         /// @tparam L Length of bits to insert
-        /// @tparam SS Start bit in source
+        /// @tparam SS Start bit in source - defaults to bit 0
         /// @tparam OT the type of the incoming (origin) data
         /// @param[in] i_datain OT value to copy into DataBuffer
         ///    - data is taken left aligned
-        /// @note Asserting that all the parameters are known at
-        /// compile time so this can be templated only. If that is not
-        /// the case we can add a function parameter version.
+        /// @return buffer& Useful for method chaining
         ///
-        template<bits_type TS, bits_type L, bits_type SS, typename OT>
-        inline void insert(const OT i_datain)
+        template<bits_type TS, bits_type L, bits_type SS = 0, typename OT>
+        inline buffer& insert(const OT i_datain)
         {
-            const bits_type target_length = parameterTraits<T>::bit_length;
-            const bits_type source_length = parameterTraits<OT>::bit_length;
+            const bits_type target_length = parameterTraits<T>::bit_length();
+            const bits_type source_length = parameterTraits<OT>::bit_length();
 
             // Error if input data don't make sense
             static_assert((TS + L) <= target_length,
@@ -304,49 +472,109 @@ namespace fapi2
             static_assert(SS < source_length,
                           "insert(): Source Start is out of bounds");
 
+            // Normalize the input to 2 64 bit integers and adjust the starts accordingly
+            uint64_t source = static_cast<uint64_t>(i_datain);
+            const uint64_t target = static_cast<uint64_t>(iv_data);
+
+            const bits_type source_start = parameterTraits<uint64_t>::bit_length() -
+                                           (source_length - SS);
+            const bits_type target_start = parameterTraits<uint64_t>::bit_length() -
+                                           (target_length - TS);
+
             // Get mask value for Target buffer
-            // Note: Need "& ((T)-1) because bit shift left for Target buffer doesn't roll off
-            T mask =((T(~0) << (target_length - L)) & T(~0)) >> TS;
+            // Note: Need "& 0UL" because bit shift left for Target buffer doesn't roll off
+            uint64_t mask = ((~0UL << (parameterTraits<uint64_t>::bit_length() - L)) & ~0UL)
+                            >> target_start;
 
-            // Calculate the equivalent position of the input Source start for the size of the Target buffer.
+            // Align the source to the target. Make things signed so we know which way to shift.
+            int32_t shift = source_start - target_start;
 
-            // Assume OT is smaller (sizeof(T) > sizeof(OT))
-            uint64_t sourceShift = abs(TS - ((target_length - source_length) + SS));
-            uint64_t sourceAlign = T(i_datain) << sourceShift;
+            if (shift > 0)
+            {
+                source <<= shift;
+            }
+            else
+            {
+                shift = target_start - source_start;
+                source >>= shift;
+            }
+
+            iv_data = ((target & ~mask) | (source & mask));
+            return *this;
+        }
+
+        ///
+        /// @brief Copy part of a OT into the DataBuffer
+        /// @tparam OT the type of the incoming (origin) data
+        /// @param[in] i_datain OT value to copy into DataBuffer
+        ///    - data is taken left aligned
+        /// @param[in] Start bit to insert into (target start)
+        /// @param[in] Length of bits to insert
+        /// @param[in] Start bit in source - defaults to bit 0
+
+        /// @return FAPI2_RC_SUCCESS if successful
+        ///
+        template<typename OT>
+        fapi2::ReturnCode insert(const OT i_datain, const bits_type i_targetStart,
+                                 const bits_type i_len, const bits_type i_sourceStart = 0)
+        {
+            const bits_type target_length = parameterTraits<T>::bit_length();
+            const bits_type source_length = parameterTraits<OT>::bit_length();
+
+            // Error if input data don't make sense
+            if ((i_targetStart + i_len) > target_length)
+            {
+                FAPI_ERR("insert(): (Target Start + Len) is out of bounds");
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            if ((i_sourceStart + i_len) > source_length)
+            {
+                FAPI_ERR("insert(): (Source Start + Len) is out of bounds");
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            if (i_targetStart >= target_length)
+            {
+                FAPI_ERR("insert(): Target Start is out of bounds");
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
 
-            if (sizeof(T) == sizeof(OT))
+            if (i_sourceStart >= source_length)
             {
-                sourceShift = abs(SS - TS);
-                sourceAlign = (SS > TS) ? ((T)i_datain) << sourceShift : ((T)i_datain) >> sourceShift;
+                FAPI_ERR("insert(): Source Start is out of bounds");
+                return FAPI2_RC_INVALID_PARAMETER;
             }
 
-            if (sizeof(T) < sizeof(OT))
+            // Normalize the input to 2 64 bit integers and adjust the starts accordingly
+            uint64_t source = static_cast<uint64_t>(i_datain);
+            const uint64_t target = static_cast<uint64_t>(iv_data);
+
+            const bits_type source_start = parameterTraits<uint64_t>::bit_length() -
+                                           (source_length - i_sourceStart);
+            const bits_type target_start = parameterTraits<uint64_t>::bit_length() -
+                                           (target_length - i_targetStart);
+
+            // Get mask value for Target buffer
+            // Note: Need "& 0UL" because bit shift left for Target buffer doesn't roll off
+            uint64_t mask = ((~0UL << (parameterTraits<uint64_t>::bit_length() - i_len)) &
+                             ~0UL) >> target_start;
+
+            // Align the source to the target. Make things signed so we know which way to shift.
+            int32_t shift = source_start - target_start;
+
+            if (shift > 0)
             {
-                sourceShift = source_length - target_length;
-                if (SS <= sourceShift)
-                {
-                    sourceShift = sourceShift +  TS - SS;
-                    sourceAlign = ((OT)i_datain) >> sourceShift;
-                }
-
-                // (SS > sourceShift)
-                else
-                {
-                    if (sourceShift > TS)
-                    {
-                        sourceShift = SS - sourceShift - TS;
-                        sourceAlign = OT(i_datain) << sourceShift;
-                    }
-                    else
-                    {
-                        sourceShift = SS - sourceShift;
-                        sourceAlign = (sourceShift < TS) ? OT(i_datain) >> sourceShift : OT(i_datain);
-                    }
-                }
+                source <<= shift;
+            }
+            else
+            {
+                shift = target_start - source_start;
+                source >>= shift;
             }
 
-            this->iv_data = (this->iv_data & ~mask) | (sourceAlign & mask);
-            return;
+            iv_data = ((target & ~mask) | (source & mask));
+            return FAPI2_RC_SUCCESS;
         }
 
         ///
@@ -356,68 +584,181 @@ namespace fapi2
         /// @tparam OT the type of the incoming (origin) data
         /// @param[in] i_datain OT value to copy into DataBuffer
         ///    - data is taken right aligned
+        /// @return buffer& Useful for method chaining
         /// @note Data is assumed to be aligned on the word boundary of L
-        /// @note Asserting that all the parameters are known at
-        /// compile time so this can be templated only. If that is not
-        /// the case we can add a function parameter version.
         ///
         template<bits_type TS, bits_type L, typename OT>
-        inline void insertFromRight(const OT i_datain)
+        inline buffer& insertFromRight(const OT i_datain)
         {
             // Error if input data don't make sense
-            static_assert(L <= parameterTraits<OT>::bit_length,
-                          "insertFromRight(): Len >= input buffer");
-            static_assert(TS < parameterTraits<T>::bit_length,
+            static_assert(L <= parameterTraits<OT>::bit_length(),
+                          "insertFromRight(): Len > input buffer");
+            static_assert(TS < parameterTraits<T>::bit_length(),
                           "insertFromRight(): Target Start is out of bounds");
-            static_assert((TS + L) <= parameterTraits<T>::bit_length,
+            static_assert((TS + L) <= parameterTraits<T>::bit_length(),
                           "InsertFromRight(): (Target Start + Len) is out of bounds");
 
-            this->insert<TS, L, parameterTraits<OT>::bit_length - L>(i_datain);
-            return;
+            this->insert<TS, L, parameterTraits<OT>::bit_length() - L>(i_datain);
+            return *this;
+        }
+
+        ///
+        /// @brief Copy in a right aligned value
+        /// @tparam OT the type of the incoming (origin) data
+        /// @param[in] i_datain OT value to copy into DataBuffer
+        ///    - data is taken right aligned
+        /// @param[in] Start bit to insert into
+        /// @param[in] Length of bits to insert
+        /// @return FAPi2_RC_SUCCESS if no error
+        /// @note Data is assumed to be aligned on the word boundary of L
+        ///
+        template<typename OT>
+        fapi2::ReturnCode insertFromRight(const OT i_datain,
+                                          const bits_type i_targetStart,
+                                          const bits_type i_len)
+        {
+            // Error if input data don't make sense
+            if ((i_targetStart + i_len) > parameterTraits<T>::bit_length())
+            {
+                FAPI_ERR("insertFromRight(): (Target Start + Len) is out of bounds");
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            if (i_targetStart >= parameterTraits<T>::bit_length())
+            {
+                FAPI_ERR("insertFromRight(): Target Start is out of bounds");
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            if (i_len > parameterTraits<OT>::bit_length())
+            {
+                FAPI_ERR("insertFromRight(): Len > input buffer");
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            return this->insert(i_datain, i_targetStart, i_len,
+                                parameterTraits<OT>::bit_length() - i_len);
         }
 
         ///
         /// @brief Copy data from this buffer into an OT
-        /// @tparam TS Start bit to insert into (target start)
+        /// @tparam SS Start bit in source
         /// @tparam L Length of bits to insert
+        /// @tparam TS Start bit to insert into (target start)
+        /// @tparam OT the type of the outgoing (target)
+        /// @param[out] o_out OT to copy into - data is placed left aligned
+        /// @return const buffer& Useful for method chaining
+        ///
+        template<bits_type SS, bits_type L, bits_type TS = 0, typename OT>
+        inline const buffer& extract(OT& o_out) const
+        {
+            // Extraction is just an insert into o_out
+
+            buffer<OT> out(o_out);
+            out.insert<TS, L, SS>(iv_data);
+            o_out = out;
+            return *this;
+        }
+
+        ///
+        /// @brief Copy data from this buffer into an OT
         /// @tparam SS Start bit in source
+        /// @tparam L Length of bits to insert
+        /// @tparam TS Start bit to insert into (target start)
         /// @tparam OT the type of the outgoing (target)
         /// @param[out] o_out OT to copy into - data is placed left aligned
-        /// @note Asserting that all the parameters are known at
-        /// compile time so this can be templated only. If that is not
-        /// the case we can add a function parameter version.
+        /// @return buffer& Useful for method chaining
         ///
-        template<bits_type TS, bits_type L, bits_type SS, typename OT>
-        inline void extract(OT& o_out)
+        template<bits_type SS, bits_type L, bits_type TS = 0, typename OT>
+        inline buffer& extract(OT& o_out)
         {
             // Extraction is just an insert into o_out
 
             buffer<OT> out(o_out);
-            out.insert<TS, L, SS>(this->iv_data);
+            out.insert<TS, L, SS>(iv_data);
             o_out = out;
-            return;
+            return *this;
+        }
+
+        ///
+        /// @brief Copy data from this buffer into an OT
+        /// @tparam OT the type of the outgoing (target)
+        /// @param[out] o_out OT to copy into - data is placed left aligned
+        /// @param[in] Start bit in source
+        /// @param[in] Length of bits to extract
+        /// @param[in] Start bit to insert into (target start)
+        /// @return FAPI2_RC_SUCCESS if ok
+        ///
+        template<typename OT>
+        fapi2::ReturnCode extract(OT& o_out, const bits_type i_sourceStart,
+                                  const bits_type i_len, const bits_type i_targetStart = 0) const
+        {
+            // Extraction is just an insert into o_out
+
+            buffer<OT> out(o_out);
+
+            if (out.insert(iv_data, i_targetStart, i_len,
+                           i_sourceStart) != FAPI2_RC_SUCCESS)
+            {
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            o_out = out;
+            return FAPI2_RC_SUCCESS;
         }
 
-#if 0
         ///
         /// @brief Copy data from this buffer into an OT and right justify
-        /// @tparam OT the type of the outgoing data - defaults to T
-        /// @tparam SB Start bit to insert into - defaults to 0
-        /// @tparam SS Start bit in o_out - default value is zero
-        /// @tparam L Length of bits to copy - defaults to sizeof(OT) * 8
+        /// @tparam SS Start bit to insert into (source start)
+        /// @tparam L Length of bits to extract
+        /// @tparam OT the type of the outgoing (target)
         /// @param[out] o_out OT to copy into - data is placed right aligned
-        /// @note Asserting that all the parameters are known at
-        /// compile time so this can be templated only. If that is not
-        /// the case we can add a function parameter version.
-        /// @post Data is copied from specified location to o_out, right
-        /// aligned. Data is only right aligned if L < sizeof(bits_type)
+        /// @return const buffer& Useful for method chaining
         ///
-        template< typename OT = T, bits_type L = parameterTraits<OT>::bit_length,
-                  bits_type SB = 0, bits_type SS = 0 >
-        void extractFromRight(OT& o_out);
-#endif
+        template<bits_type SS, bits_type L, typename OT>
+        inline const buffer& extractToRight(OT& o_out) const
+        {
+            extract<SS, L, parameterTraits<OT>::bit_length() - L>(o_out);
+            return *this;
+        }
+
+        ///
+        /// @brief Copy data from this buffer into an OT and right justify
+        /// @tparam SS Start bit to insert into (source start)
+        /// @tparam L Length of bits to extract
+        /// @tparam OT the type of the outgoing (target)
+        /// @param[out] o_out OT to copy into - data is placed right aligned
+        /// @return buffer& Useful for method chaining
+        ///
+        template<bits_type SS, bits_type L, typename OT>
+        inline buffer& extractToRight(OT& o_out)
+        {
+            extract<SS, L, parameterTraits<OT>::bit_length() - L>(o_out);
+            return *this;
+        }
+
+        ///
+        /// @brief Copy data from this buffer into an OT and right justify
+        /// @tparam OT the type of the outgoing (target)
+        /// @param[out] o_out OT to copy into - data is placed right aligned
+        /// @param[in] Start bit to insert into (source start)
+        /// @param[in] Length of bits to insert
+        /// @return FAPI2_RC_SUCCESS if ok
+        ///
+        template<typename OT>
+        fapi2::ReturnCode extractToRight(OT& o_out, const bits_type i_sourceStart,
+                                         const bits_type i_len) const
+        {
+            return extract(o_out, i_sourceStart, i_len,
+                           parameterTraits<OT>::bit_length() - i_len);
+        }
+
         ///@}
-    };
+
+    private:
+        /// The contents of the buffer
+        T iv_data;
 };
+}
 
 #endif
diff --git a/src/ppe/hwpf/plat/include/buffer_base.H b/src/ppe/hwpf/plat/include/buffer_base.H
new file mode 100755
index 0000000..f5ac84b
--- /dev/null
+++ b/src/ppe/hwpf/plat/include/buffer_base.H
@@ -0,0 +1,331 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwpf/plat/include/buffer_base.H $                     */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file buffer_base.H
+ * @brief definitions for fapi2 buffer base class
+ */
+
+#ifndef __FAPI2_BUFFER_BASE__
+#define __FAPI2_BUFFER_BASE__
+
+#include <stdint.h>
+#include <initializer_list>
+#include <error_scope.H>
+#include <buffer_parameters.H>
+#include <buffer_traits.H>
+#include <return_code.H>
+
+namespace fapi2
+{
+    /// @brief Base class for buffers and variable buffers
+    /// @tparam T is the type of iv_data (std::vector, etc)
+    /// @tparam TT is the template trait, defaults to the trait for T
+    ///
+    /// Buffers can be of two styles; buffers made from an integral type and
+    /// buffers made from a container. Integral type buffers, while limited
+    /// in size, can be tightly controlled via the compiler by using c++
+    /// templates.
+    ///
+    /// C++ templates allow for very explicit control, but yield a
+    /// syntax different than the FAPI 1.x functional interface. For example,
+    /// a fapi2::buffer is defined as having a type:
+    /// @code
+    /// fapi2::buffer<uint64_t> new_buffer;
+    /// @endcode
+    /// defines a buffer with exactly 64 bits, and can be manipulated by the
+    /// compiler as a single intrgral value. These implementations result
+    /// in concise instruction streams, and a platform may choose to implement
+    /// all or some or none of the integral buffer types.
+    ///
+    /// Buffers which have containers as their underlying implementation
+    /// are found in the class fapi2::variable_buffer. variable_buffer is little
+    /// more than
+    /// @code
+    /// fapi2::buffer<fapi2::bits_container>
+    /// @endcode
+    /// where bits_container is the typedef of the underlying container (a
+    /// vector of uint32_t, for example)
+    ///
+    /// Examples:<br>
+    ///
+    /// * Simple uint64_t buffer
+    /// @code
+    /// const uint32_t x = 2;
+    ///
+    /// // this data buffer will contain data in a uint64_t type
+    /// fapi2::buffer<uint64_t> data;
+    ///
+    /// // Set using the template and a constant
+    /// data.setBit<x>();
+    ///
+    /// // Set using the template and a value
+    /// data.setBit<3>();
+    ///
+    /// // Set using the function interface, and a value
+    /// data.setBit(1);
+    ///
+    /// // compiler gets smart.
+    /// // movabs $0x7000000000000000,%rsi
+    /// @endcode
+    ///
+    /// * variable_buffer, same thing
+    /// @code
+    ///
+    /// const uint32_t x = 2;
+    ///
+    /// // Note: only 15 bits long
+    /// fapi2::variable_buffer data(15);
+    ///
+    ///
+    /// data.setBit(x);
+    /// data.setBit(3);
+    /// data.setBit(1);
+    /// @endcode
+    ///
+    /// * method chaining
+    /// Buffers support method chaining. So, rather than
+    /// this
+    /// @code
+    /// buffer<T> mask;
+    /// mask.setBit<B>();
+    /// mask.invert();
+    /// my_buffer &= mask;
+    /// @endcode
+    /// You can do
+    /// @code
+    /// my_buffer &= buffer<T>().setBit<B>.invert();
+    /// @endcode
+    ///
+    /// * buffer operations
+    /// @code
+    ///
+    /// // An 8 bit buffer, initialized with a value
+    /// fapi2::buffer<uint8_t> eight_bits = 0xAA;
+    /// fapi2::buffer<uint8_t> another_eight;
+    /// fapi2::buffer<uint16_t> sixteen_bits;
+    ///
+    /// // You can't assign an 8 bit buffer to a 16 bit buffer.
+    /// sixteen_bits = eight_bits; ERROR
+    ///
+    /// // But you can assign buffers of the same type
+    /// another_eight = eight_bits;
+    ///
+    /// // You can assign constants (or other known values) directly:
+    /// sixteen_bits = 0xAABB;
+    /// @endcode
+    ///
+    /// * Variable buffer operations
+    ///
+    /// @code
+    /// fapi2::variable_buffer data(16);
+    ///
+    /// // Very large buffers can be initialized rather than set bit by bit.
+    /// const fapi2::variable_buffer bit_settings_known(
+    ///     {0xFFFF0000, 0xAABBF0F0,
+    ///      0xFFFF0000, 0xAABBF0F0,
+    ///      0xFFFF0000, 0xAABBF0F0,});
+    ///
+    /// // Assignment will expand or shrink the size automatically.
+    /// data = bit_settings_known;
+    ///
+    /// // You can assign directly to the buffer:
+    /// fapi2::variable_buffer other_bits;
+    /// const fapi2::container_unit x = 0xFF00AA55;
+    /// other_bits = {x, 0xDEADBEEF};
+    /// @endcode
+    ///
+    template <typename T, typename TT = bufferTraits<T> >
+    class buffer_base
+    {
+
+    public:
+
+        /// Shortcut typedef to get to our traits class
+        typedef typename TT::bits_type bits_type;
+        /// Shortcut typedef to get to our traits class
+        typedef typename TT::unit_type unit_type;
+
+        ///
+        /// @brief Default constructor
+        /// @note iv_data will get the "default" construction, which is
+        /// correct - 0 for integral types, an empty container for the others.
+        ///
+        buffer_base(void):
+            iv_data()
+            {}
+
+        virtual ~buffer_base(void)
+            {}
+
+#ifndef DOXYGEN
+        /// @brief Print the contents of the buffer to stdout
+        inline void print(void) const
+        { TT::print(iv_data); }
+#endif
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return The contents of the buffer
+        ///
+        inline operator T() const { return iv_data; }
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return The contents of the buffer
+        ///
+        inline operator T&() { return iv_data; }
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return The contents of the buffer
+        ///
+        inline T& operator()(void) { return iv_data; }
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return Reference to the contents of the buffer
+        ///
+        inline const T& operator()(void) const { return iv_data; }
+
+        ///
+        /// @brief Get a pointer to the buffer bits
+        /// @return Pointer to the buffer itself
+        ///
+        inline T* pointer(void) { return &iv_data; }
+
+        /// @name Buffer Manipulation Functions
+        ///@{
+
+        ///
+        /// @brief Set an OT of data in buffer
+        /// @param[in] i_value sizeof(OT) bits of data
+        /// @param[in] i_offset Start OT (start word, for example) in buffer
+        ///            - defaults to 0 (will by default write the left most element)
+        /// @return FAPI2_RC_SUCCESS on success, FAPI2_RC_OVERFLOW otherwise
+        /// @note This is is only available for integral types. To set a
+        ///    variable_buffer into a variable_buffer, use insert()
+        ///
+        template< typename OT>
+        inline fapi2::ReturnCode set(OT i_value, const bits_type i_offset = 0)
+        {
+            // Compile time check to make sure OT isn't a variable buffer
+            static_assert( !std::is_same<bits_container, OT>::value,
+                           "Can't use a variable_buffer as input to set()" );
+
+            //
+            // There's a gotcha in here. size<OT>() returns the size in the buffer
+            // in OT units *rounded up*. This is the actual size of the buffer, not
+            // the perceived size of a variable_buffer. This should be OK however,
+            // as what we're trying to prevent is overflow, which this should do.
+            //
+            const uint32_t length = TT:: template size<OT>(iv_data);
+            static const bits_type bits_in_value = parameterTraits<OT>::bit_length;
+            const bits_type bit_length = TT::bit_length(iv_data);
+
+            if (i_offset >= length)
+            {
+                return FAPI2_RC_OVERFLOW;
+            }
+
+            // Create mask if part of this byte is not in the valid part of the buffer,
+            // Shift it left by the amount of unused bits,
+            // Clear the unused bits
+            if (((i_offset + 1) == length) && (bit_length % bits_in_value)) {
+                i_value &= parameterTraits<OT>::mask << ((bits_in_value * length) - bit_length);
+            }
+
+            parameterTraits<OT>::template write_element<unit_type>(TT::get_address(iv_data), i_value, i_offset);
+            return FAPI2_RC_SUCCESS;
+        }
+
+        ///
+        /// @brief Set and entire buffer to X's
+        /// @tparam X {0,1} depending if you want to clear (0)
+        /// or fill (1) a buffer
+        ///
+        template< uint8_t X >
+        inline void flush(void)
+            {
+                static_assert( (X == 1) || (X == 0), "bad argument to flush" );
+                (0 == X) ? TT::clear(iv_data) : TT::set(iv_data);
+            }
+
+        ///
+        /// @brief Invert entire buffer
+        /// @return buffer_base&, Useful for method chaining
+        ///
+        inline buffer_base& invert(void)
+            { TT::invert(iv_data); return *this; }
+
+        ///
+        /// @brief Bit reverse entire buffer
+        /// @return buffer_base&, Useful for method chaining
+        ///
+        inline buffer_base& reverse(void)
+            { TT::reverse(iv_data); return *this; }
+
+        //@}
+    protected:
+
+        ///
+        /// @brief Variable buffer constructor
+        /// @param[in] i_value number of *bits* (sizeof(container_units) * 8)
+        /// needed. Meaningless for integral types and thus protected.
+        ///
+        buffer_base(bits_type i_value);
+
+        ///
+        /// @brief Variable buffer construct from a list
+        /// @param[in] i_value an initializer list to initialize the container.
+        /// Meaningless for integral types and thus protected
+        ///
+        buffer_base(std::initializer_list<unit_type> i_value);
+
+        ///
+        /// @brief Clear the buffer
+        ///
+        inline void clear(void)
+            { TT::clear(iv_data); }
+
+        /// The contents of the buffer
+        T iv_data;
+    };
+
+    template <typename T, typename TT>
+    inline buffer_base<T, TT>::buffer_base(bits_type i_value):
+        iv_data( std::max(bits_type(1),
+                          bits_type(i_value / 8 / sizeof(bits_type))))
+    {
+    }
+
+    template <typename T, typename TT>
+    inline buffer_base<T, TT>::buffer_base(std::initializer_list<unit_type> i_value):
+        iv_data(i_value)
+    {
+    }
+};
+
+
+
+#endif
diff --git a/src/ppe/hwpf/plat/include/buffer_parameters.H b/src/ppe/hwpf/plat/include/buffer_parameters.H
index c34686e..a0c5f18 100644
--- a/src/ppe/hwpf/plat/include/buffer_parameters.H
+++ b/src/ppe/hwpf/plat/include/buffer_parameters.H
@@ -41,12 +41,17 @@ namespace fapi2
     class parameterTraits
     {
     public:
-        enum
-        {
-            mask = T(~0),
-            bit_length = sizeof(T) * 8,
-            byte_length = sizeof(T),
-        };
+        // Why constexpr functions? Enums are hard to do math on, and
+        // static const doesn't work without -O1 (or greater.) That might
+        // be a bug in g++ but this works just the same.
+        constexpr static T mask(void)
+            { return T(~0); }
+
+        constexpr static uint32_t byte_length(void)
+            { return sizeof(T); }
+
+        constexpr static uint32_t bit_length(void)
+            { return sizeof(T) * 8; }
 
         template<typename U>
         inline static void write_element(void* i_data, T i_value, uint32_t i_offset)
@@ -60,6 +65,6 @@ namespace fapi2
         }
     };
     /// @endcond
-};
+}
 
 #endif
diff --git a/src/ppe/hwpf/plat/include/buffer_traits.H b/src/ppe/hwpf/plat/include/buffer_traits.H
index cfc699b..65fd350 100644
--- a/src/ppe/hwpf/plat/include/buffer_traits.H
+++ b/src/ppe/hwpf/plat/include/buffer_traits.H
@@ -35,17 +35,22 @@
 #include <algorithm>
 #include <buffer_parameters.H>
 
-#ifdef __FAPI2_DEBUG__
-// for debug printing ... can be removed for flight
+#ifdef FAPI2_DEBUG
 #include <iostream>
 #endif
+
+#if !defined(DOXYGEN) && defined(FAPI2_DEBUG)
 #include <iterator>
+#endif
 
 namespace fapi2
 {
     /// @cond
     /// Types representing a container of bits. Used to create
-    /// variable_buffer.
+    /// variable_buffer. container_unit must remain 32-bits
+    /// for now - there will be a lot of code to change if it
+    /// changes. There are assertions helping to enforce this
+    /// in places in the code.
     typedef uint32_t container_unit;
     typedef std::vector<container_unit> bits_container;
 
@@ -59,8 +64,8 @@ namespace fapi2
     class bufferTraits
     {
     public:
-#ifndef DOXYGEN
-#ifdef __FAPI2_DEBUG__
+
+#if !defined(DOXYGEN) && defined(FAPI2_DEBUG)
         ///
         /// @brief Print a container of bits
         /// @param[in] i_data the container of bits
@@ -75,7 +80,6 @@ namespace fapi2
                       << std::dec << std::endl;
         }
 #endif
-#endif
 
         ///
         /// @brief Return the size of the buffer in E units
@@ -87,8 +91,8 @@ namespace fapi2
         constexpr static B size(const T& i_buffer)
             {
                 return (bit_length(i_buffer) +
-                        (parameterTraits<E>::bit_length - 1)) /
-                    parameterTraits<E>::bit_length;
+                        (parameterTraits<E>::bit_length() - 1)) /
+                    parameterTraits<E>::bit_length();
             }
 
         ///
@@ -141,7 +145,8 @@ namespace fapi2
 
         typedef B bits_type;
         typedef T unit_type;
-        enum { bits_per_unit = sizeof(unit_type) * 8 };
+        constexpr static uint32_t bits_per_unit(void)
+            { return sizeof(unit_type) * 8; }
     };
 
     //
@@ -153,8 +158,7 @@ namespace fapi2
     class bufferTraits<bits_container, uint32_t>
     {
     public:
-#ifndef DOXYGEN
-#ifdef __FAPI2_DEBUG__
+#if !defined(DOXYGEN) && defined(FAPI2_DEBUG)
         ///
         /// @brief Print a container of bits
         /// @param[in] i_data the container of bits
@@ -167,7 +171,6 @@ namespace fapi2
             std::cout << std::dec << std::endl;
         }
 #endif
-#endif
 
         ///
         /// @brief Return the size of the buffer in E units
@@ -179,8 +182,8 @@ namespace fapi2
         constexpr static uint32_t size(const bits_container& i_buffer)
             {
                 return (bit_length(i_buffer) +
-                        (parameterTraits<E>::bit_length - 1)) /
-                    parameterTraits<E>::bit_length;
+                        (parameterTraits<E>::bit_length() - 1)) /
+                    parameterTraits<E>::bit_length();
             }
 
         ///
@@ -228,10 +231,11 @@ namespace fapi2
 
         typedef uint32_t bits_type;
         typedef container_unit unit_type;
-        enum { bits_per_unit = sizeof(unit_type) * 8 };
+        constexpr static uint32_t bits_per_unit(void)
+            { return sizeof(unit_type) * 8; }
     };
     /// @endcond
-};
+}
 
 
 
diff --git a/src/ppe/hwpf/plat/include/fapi2.H b/src/ppe/hwpf/plat/include/fapi2.H
index 17d3d59..e98871f 100644
--- a/src/ppe/hwpf/plat/include/fapi2.H
+++ b/src/ppe/hwpf/plat/include/fapi2.H
@@ -51,14 +51,15 @@
 #include <utils.H>
 
 
+
 // In turn includes the needed generated headers (hwp_ffd_classes, etc.)
 #include <error_scope.H>
-//#include <set_sbe_error.H>      // Generated file  mb empty file addCopyright.pl does not like empty files
-#include <fapi2AttributeService.H>
-#include <fapi2AttributeIds.H>      // Generated file
+#include <set_sbe_error.H>      // Generated file
+#include <plat_attributes.H>
+#include <plat_target_utils.H>
 
 
-// #include <hwp_executor.H> // mb empty file addCopyright.pl does not like empty files
+#include <hwp_executor.H>
 
 // Block of headers not currently in fapi2
 #ifdef FAPI2_MISSING_HEADERS
diff --git a/src/ppe/hwpf/plat/include/fapi2AttributeService.H b/src/ppe/hwpf/plat/include/fapi2AttributeService.H
new file mode 100644
index 0000000..64bda25
--- /dev/null
+++ b/src/ppe/hwpf/plat/include/fapi2AttributeService.H
@@ -0,0 +1,151 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwpf/plat/include/fapi2AttributeService.H $           */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file fapi2AttributeService.H
+///
+/// @brief Defines the FAPI_ATTR_GET and FAPI_ATTR_SET macros that a user
+/// calls to get/set attributes and a check function that the macros use to
+/// verify correct usage
+///
+
+#ifndef FAPI2ATTRIBUTESERVICE_H_
+#define FAPI2ATTRIBUTESERVICE_H_
+#include <stdint.h>
+//#include <attribute_ids.H>
+#include <fapi2AttributeIds.H>
+#include <target.H>
+#include <target_types.H>
+//#include <plat_attribute_service.H>
+#include <fapi2PlatAttributeService.H>
+
+/// @brief Macros called by user to get/set attributes for FAPI2 targets
+///
+/// Code must have a reference to a FAPI2 Target and an attribute ID (from
+/// XML file):
+///   fapi2::ReturnCode l_rc;
+///   fapi2::Target<target type>& l_target = ????;
+///          Ex: Target<TARGET_TYPE_PROC_CHIP>& l_target = ????;
+///
+/// To get a copy of an integer attribute and set the attribute
+///   uint64_t l_val = 0;
+///   l_rc = FAPI_ATTR_GET(<ID>, l_target, l_val);
+///   l_rc = FAPI_ATTR_SET(<ID>, l_target, l_val);
+///
+/// To get a copy of an integer array attribute and set the attribute
+///   uint32_t l_pVal[4] = {0};
+///   l_rc = FAPI_ATTR_GET(<ID>, l_target, l_pVal);
+///   l_rc = FAPI_ATTR_SET(<ID>, l_target, l_pVal);
+///
+/// A priveleged attribute is one that a HWP should not generally access,
+/// examples include ATTR_NAME and ATTR_EC, where usage can lead to a non
+/// data-driven design. A privileged attribute can be accessed with
+/// FAPI_ATTR_GET_PRIVILEGED and FAPI_ATTR_SET_PRIVILEGED
+///
+/// The non-PRIVILEGED macros first call a template function (compiler will
+/// optimize out) that will cause a compile failure if the attribute is
+/// privileged, they then call a PRIVILEGED macro to get/set the attribute
+///
+/// The PRIVILEGED macros call a template function (compiler will optimize out)
+/// that will cause a compile failure if the ID is not valid or VAL is not the
+/// correct type.
+//
+
+#define FAPI_ATTR_GET(ID, TARGET, VAL) \
+    (fapi2::failIfPrivileged<ID##_Privileged>(), \
+     fapi2::checkIdType<ID##_Type>(ID, VAL), \
+     ID##_GETMACRO(ID, TARGET, VAL))
+
+#define FAPI_ATTR_SET(ID, TARGET, VAL) \
+    (fapi2::failIfPrivileged<ID##_Privileged>(), \
+     fapi2::checkIdType<ID##_Type>(ID, VAL), \
+     ID##_SETMACRO(ID, TARGET, VAL))
+
+#define FAPI_ATTR_GET_PRIVILEGED(ID, TARGET, VAL) \
+    (fapi2::checkIdType<ID##_Type>(ID, VAL), \
+     ID##_GETMACRO(ID, TARGET, VAL))
+
+#define FAPI_ATTR_SET_PRIVILEGED(ID, TARGET, VAL) \
+    (fapi2::checkIdType<ID##_Type>(ID, VAL), \
+     ID##_SETMACRO(ID, TARGET, VAL))
+
+namespace fapi2
+{
+
+///
+/// @brief Get an InitFile attribute for FAPI2
+///
+/// This function gets a copy of an attribute. In the case of an array attribute,
+/// The value in the specified index is retrieved. This should be used by the
+/// InitFile HWP only, that HWP processes a binary InitFile and therefore needs
+/// to read a variable ID of a variable data type. Standard HWPs should use the
+/// FAPI2_ATTR_GET macro which automatically checks the type for correct usage.
+///
+/// If there are ever attributes with more than 4 dimensions then this function
+/// will need to be updated.
+///
+/// @Tparam K template parameter, passed in target.
+/// @param[in]  i_id          AttributeID
+/// @param[in]  i_target      Reference to fapi2::Target (can be NULL for system)
+/// @param[out] o_val         Reference to uint64_t where attribute value is set
+/// @param[in]  i_arrayIndex1 If array attribute then index1
+/// @param[in]  i_arrayIndex2 If at least 2D array attribute then index2
+/// @param[in]  i_arrayIndex3 If at least 3D array attribute then index3
+/// @param[in]  i_arrayIndex4 If at least 4D array attribute then index4
+///
+/// @return ReturnCode. Zero if success
+///
+template< TargetType K >
+ReturnCode getInitFileAttr(const AttributeId i_id,
+                           const Target<K>& i_target,
+                           uint64_t & o_val,
+                           const uint32_t i_arrayIndex1 = 0,
+                           const uint32_t i_arrayIndex2 = 0,
+                           const uint32_t i_arrayIndex3 = 0,
+                           const uint32_t i_arrayIndex4 = 0);
+
+/**
+ * @brief Check the ID and TYPE
+ *
+ * This is called by FAPI code to check at compile time that a FAPI attribute
+ * access is using the correct data type and a valid AttributeId
+ */
+template<typename T> inline void checkIdType(AttributeId, T &) {}
+
+/**
+ * @brief Fail if attribute privileged
+ *
+ * This is called by FAPI code to check at compile time that a standard FAPI
+ * attribute access (FAPI_ATTR_GET) is not accessing a privileged attribute
+ */
+class ErrorAccessingPrivilegedAttribute;
+template<const bool PRIVILEGED> void failIfPrivileged()
+{
+   ErrorAccessingPrivilegedAttribute();
+}
+template <> inline void failIfPrivileged<false>() {}
+
+}
+
+#endif // FAPI2ATTRIBUTESERVICE_H_
diff --git a/src/ppe/hwpf/plat/include/fapi2_hw_access.H b/src/ppe/hwpf/plat/include/fapi2_hw_access.H
new file mode 100644
index 0000000..ee973bc
--- /dev/null
+++ b/src/ppe/hwpf/plat/include/fapi2_hw_access.H
@@ -0,0 +1,464 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwpf/plat/include/fapi2_hw_access.H $                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file fapi2_hw_access.H
+/// @brief Common file that defines the hardware access functions that
+/// platform code must implement.
+///
+
+#ifndef _FAPI2_COMMON_HWACCESS_H_
+#define _FAPI2_COMMON_HWACCESS_H_
+
+#ifdef FAPI_SUPPORT_SPY_AS_ENUM
+#include <spy_ids.H>
+typedef uint64_t spyId_t;
+#endif
+
+#include <stdint.h>
+//#include <thread>
+#include <buffer.H>
+
+// variable_buffer isn't supported on PPE
+#ifndef __PPE__
+#include <variable_buffer.H>
+#endif
+
+#include <return_code.H>
+#include <target.H>
+#include <hw_access_def.H>
+#include <plat_hw_access.H>
+
+#ifdef FAPI_SUPPORT_MULTI_SCOM
+#include <multi_scom.H>
+#endif
+
+namespace fapi2
+{
+    //--------------------------------------------------------------------------
+    // PIB Error Functions
+    //--------------------------------------------------------------------------
+
+    /// @brief Sets the PIB error mask - platform dependant
+    /// @param[in]  i_mask     The new error mask
+    inline void setPIBErrorMask(uint8_t i_mask);
+
+    /// @brief Gets the PIB error mask - platform dependant
+    /// @return uint8_t The current PIB error mask
+    inline uint8_t getPIBErrorMask(void);
+
+    //--------------------------------------------------------------------------
+    // Operational Mode Error Functions
+    //--------------------------------------------------------------------------
+
+    /// @brief Sets the operational mode
+    /// @param[in]  i_mode     The new mode
+    inline void setOpMode(const OpModes i_mode);
+
+    /// @brief Gets the operational mode
+    /// @return the operational mode
+    inline OpModes getOpMode(void);
+
+    //--------------------------------------------------------------------------
+    // HW Communication Functions
+    //--------------------------------------------------------------------------
+
+    /// @brief Reads a SCOM register from a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target     HW target to operate on.
+    /// @param[in]  i_address    SCOM register address to read from.
+    /// @param[out] o_data       Buffer that holds data read from HW target.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline void getScom(const Target<K>& i_target, const uint64_t i_address,
+                              buffer<uint64_t>& o_data);
+
+    /// @brief Writes a SCOM register on a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target     HW target to operate on.
+    /// @param[in] i_address    SCOM register address to write to.
+    /// @param[in] i_data       Buffer that holds data to write into address.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline void putScom(const Target<K>& i_target, const uint64_t i_address,
+                              const buffer<uint64_t> i_data);
+
+    /// @brief Writes a SCOM register under mask on a chip
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target     HW target to operate on.
+    /// @param[in] i_address    SCOM register address to write to.
+    /// @param[in] i_data       Buffer that holds data to write into address.
+    /// @param[in] i_mask       Buffer that holds the mask value.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline void putScomUnderMask(const Target<K>& i_target,
+                                       const uint64_t i_address,
+                                       const buffer<uint64_t> i_data,
+                                       const buffer<uint64_t> i_mask);
+
+    /// @brief Reads a CFAM register from a chip.
+    ///        CFAM register is 32-bit wide.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target  HW target to operate on.
+    /// @param[in]  i_address CFAM register address to read from.
+    /// @param[out] o_data    Buffer that holds data read from HW target.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode getCfamRegister(const Target<K>& i_target,
+                                      const uint32_t i_address,
+                                      buffer<uint32_t>& o_data);
+
+    /// @brief Writes a CFAM register on a chip.
+    ///        CFAM register is 32-bit wide.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target  HW target to operate on.
+    /// @param[in] i_address CFAM register address to write to.
+    /// @param[in] i_data    Buffer that holds data to write into address.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode putCfamRegister(const Target<K>& i_target,
+                                      const uint32_t i_address,
+                                      const buffer<uint32_t> i_data);
+
+    /// @brief Read-modify-write a CFAM register on a chip.
+    ///        CFAM register is 32-bit wide.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target     HW target to operate on.
+    /// @param[in] i_address    CFAM register address to modify.
+    /// @param[in] i_data       Buffer that holds data to be modified.
+    /// @param[in] i_modifyMode The modify mode (or/and/xor).
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode modifyCfamRegister(const Target<K>& i_target,
+                                         const uint32_t i_address,
+                                         const buffer<uint32_t> i_data,
+                                         const ChipOpModifyMode i_modifyMode);
+
+    // variable_buffer isn't supported on PPE
+#ifndef __PPE__
+    /// @brief Reads a ring from a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target   Target to operate on.
+    /// @param[in]  i_address  Ring address to read from.
+    /// @param[out] o_data     Buffer that holds data read from HW target.
+    /// @param[in]  i_ringMode Ring operation mode.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode getRing(const Target<K>& i_target,
+                              const scanRingId_t i_address,
+                              variable_buffer& o_data,
+                              const RingMode i_ringMode = 0);
+
+    /// @brief Writes a ring to a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target   Target to operate on.
+    /// @param[in] i_address  Ring address to write to.
+    /// @param[in] i_data     Buffer that contains RS4 compressed ring data
+    ///                       to write into address
+    /// @param[in] i_ringMode Ring operation mode.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode putRing(const Target<K>& i_target,
+                              const scanRingId_t i_address,
+                              const variable_buffer& i_data,
+                              const RingMode i_ringMode = 0);
+
+
+    /// @brief Read-modify-write a ring on a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target     Target to operate on.
+    /// @param[in] i_address    Ring address to modify.
+    /// @param[in] i_data       Buffer that contains RS4 compressed ring data
+    ///                         to be modified.
+    /// @param[in] i_modifyMode The modify mode (or/and/xor)
+    /// @param[in] i_ringMode   Ring operation mode.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode modifyRing(const Target<K>& i_target,
+                                 const scanRingId_t i_address,
+                                 const variable_buffer& i_data,
+                                 const ChipOpModifyMode i_modifyMode,
+                                 const RingMode i_ringMode = 0);
+#endif
+
+#ifdef FAPI_SUPPORT_MULTI_SCOM
+    /// @brief Performs a multiple SCOM operation
+    ///        This interface performs multiple SCOM operations on a chip in the
+    ///        order specified by the input MultiScom object.
+    ///        See fapiMultiScom.H for details of how to populate the MultiScom
+    ///        object with SCOM operations.
+    ///
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]     i_target Target to operate on.
+    /// @param[in,out] io_multiScomObj Reference to a MultiScom object,
+    ///                                pre-populated with SingleScomInfo entries
+    ///                                to perform multiple SCOMs on input target
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note   This is a synchronous interface and would return after all the
+    ///         SCOM operations are completed or on the first failed operation
+    ///
+    /// @note   SCOMs will be performed in the order they were added to the
+    ///         input MultiScom object
+    ///
+    /// @note   In case of errors, the platform code is responsible to collect
+    ///         and add all the required error info and FFDC into the error data
+    ///         for debugging
+    ///
+    /// @note   If the SCOM operations added are specific to a processor chip,
+    ///         then the FSI Shift Engine configured in scatter-gather DMA mode
+    ///         extension would be used to execute the SCOM operations in a
+    ///         performance optimize mode. In this mode, the special
+    ///         SCOM_BULK_READ_MODE and SCOM_BULK_WRITE_MODE operations are
+    ///         supported that allow a large bulk of SCOM access (in multiple of
+    ///         64 bits) for targets that support auto-increment. The
+    ///         SCOM_WRITE_UNDER_MASK operation is not supported in this mode
+    ///
+    /// @note   If the SCOM operations added are specific to a memory buffer
+    ///         chip, then the regular SCOM engine is used to execute the SCOM
+    ///         operations. SCOM_WRITE_UNDER_MASK operation is supported in
+    ///         this mode, but the special SCOM_BULK_READ_MODE and
+    ///         SCOM_BULK_WRITE_MODE operations are not supported due to
+    ///         hardware limitations.
+    ///
+    template< TargetType K >
+    fapi2::ReturnCode multiScom (const Target<K>& i_target,
+                                 MultiScom&  io_multiScomObj);
+#endif
+
+    // --------------------------------------------------------------------------
+    // NOTE:
+    // Implement platform Spy access functions if platform supports them.
+    // --------------------------------------------------------------------------
+
+    // variable_buffer isn't supported on PPE
+#ifndef __PPE__
+    /// @brief Reads a spy from a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target   Target to operate on.
+    /// @param[in]  i_spyId    Id of the spy whose data to be read.
+    /// @param[out] o_data     Buffer that holds data read from HW target.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note:  The string version is only supported for cronus.
+    ///
+    ///         The fapi design to support both FSP and cronus use of get and
+    ///         put spy functions is dependant on the SPY names being expanded
+    ///         to resemble a valid C identifier. This design places some
+    ///         restrictions on the SPY names which can be used.
+    ///
+    ///         1. if the spy name contains a # procedure writers should replace
+    ///         it with an __P__ for example -
+    ///
+    ///         ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+    ///         becomes
+    ///         ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS
+    ///
+    ///         2. if the spy name has a number following a "." it must have an
+    ///         underscore prepended to the number.
+    ///
+    ///         EH.TPCHIP.2KX100_ARY_CLK_EDGES_DLY
+    ///         becomes
+    ///         EH.TPCHIP._2KX100_ARY_CLK_EDGES_DLY
+    ///
+    ///         Example SPY name:
+    ///         The hardware procedure should call the function like:
+    ///
+    ///          ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+    ///
+    ///          fapi2::ReturnCode rc = fapiGetSpy( targ,
+    ///                  ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS, data );
+    ///
+    /// @note The ID is not in quotes the fapi code will handle adding
+    ///       the quotes for the cronus environment
+#if defined(FAPI_SUPPORT_SPY_AS_ENUM) || defined(DOXYGEN)
+
+#define FAPI_GET_SPY(TARGET, ID, DATA) fapi2::getSpy(TARGET, FAPI_SPY_NAMES::ID.value, DATA)
+
+    template< TargetType K >
+    inline ReturnCode getSpy(const Target<K>& i_target,
+                             const spyId_t i_spyId,
+                             variable_buffer& o_data);
+#endif
+
+#if defined(FAPI_SUPPORT_SPY_AS_STRING) || defined(DOXYGEN)
+
+#define FAPI_GET_SPY(TARGET, ID, DATA) fapi2::getSpy(TARGET, #ID, DATA)
+
+    template< TargetType K >
+    inline ReturnCode getSpy(const Target<K>& i_target,
+                             const char * const i_spyId,
+                             variable_buffer& o_data);
+#endif
+
+    /// @brief Writes a spy on a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target   Target to operate on.
+    /// @param[in]  i_spyId    Id of the spy to write data to.
+    /// @param[out] i_data     Buffer that holds data to write into spy.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note:  The string version is only supported for cronus.
+    ///
+    ///         The fapi design to support both FSP and cronus use of get and
+    ///         put spy functions is dependent on the SPY names being expanded
+    ///         to resemble a valid C identifier. This design places some
+    ///         restrictions on the SPY names which can be used.
+    ///
+    ///         1. if the spy name contains a # procedure writers should replace
+    ///         is with an __P__ for example -
+    ///
+    ///         ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+    ///         becomes
+    ///         ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS
+    ///
+    ///         2. if the spy name has a number following a "." it must have an
+    ///         underscore prepended to the number.
+    ///
+    ///         EH.TPCHIP.2KX100_ARY_CLK_EDGES_DLY
+    ///         becomes
+    ///         EH.TPCHIP._2KX100_ARY_CLK_EDGES_DLY
+    ///
+    ///         Example SPY name:
+    ///         The hardware procedure should call the function like:
+    ///
+    ///          ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+    ///
+    ///          fapi2::ReturnCode rc = fapiPutSpy( targ,
+    ///                  ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS, data );
+    ///
+    /// @note The ID is not in quotes the fapi code will handle adding
+    ///         the quotes for the cronus environment
+    ///
+#if defined(FAPI_SUPPORT_SPY_AS_ENUM) || defined(DOXYGEN)
+
+#define FAPI_PUT_SPY(TARGET, ID, DATA) fapi2::putSpy(TARGET, FAPI_SPY_NAMES::ID.value, DATA)
+
+    template< TargetType K >
+    inline ReturnCode putSpy(const Target<K>& i_target,
+                             const spyId_t i_spyId,
+                             variable_buffer& i_data);
+#endif
+
+#if defined(FAPI_SUPPORT_SPY_AS_STRING) || defined(DOXYGEN)
+
+#define FAPI_PUT_SPY(TARGET, ID, DATA) fapi2::putSpy(TARGET, #ID, DATA)
+
+    template< TargetType K >
+    inline ReturnCode putSpy(const Target<K>& i_target,
+                             const char* const i_spyId,
+                             variable_buffer& i_data);
+#endif
+
+    /// @brief Writes spy data into a buffer holding ring data image
+    ///        This API is used by L2/L3 repair to put column repair data
+    ///        into a ring buffer image.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target Target to operate on.
+    /// @param[in]  i_spyId  Id of the spy.
+    /// @param[in]  i_data   Buffer that holds spy data to write into ring
+    ///                      image.
+    /// @param[out] o_data   Buffer that holds updated ring image.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note:  The string version is only supported for cronus.
+    ///
+    ///         The fapi design to support both FSP and cronus use of get and
+    ///         put spy functions is dependent on the SPY names being expanded
+    ///         to resemble a valid C identifier. This design places some
+    ///         restrictions on the SPY names which can be used.
+    ///
+    ///         See fapiPutSpy for details on spy id specifics.
+    ///
+#if defined(FAPI_SUPPORT_SPY_AS_ENUM) || defined(DOXYGEN)
+
+#define FAPI_PUT_SPY_IMAGE(TARGET, ID, DATA1, DATA2)                    \
+    fapi2::putSpyImage(TARGET, FAPI_SPY_NAMES::ID.value,                \
+                       DATA1, DATA2)
+
+    template< TargetType K >
+    inline ReturnCode putSpyImage(const Target<K>& i_target,
+                                  const spyId_t i_spyId,
+                                  const variable_buffer& i_data,
+                                  variable_buffer& o_imageData);
+#endif
+
+#if defined(FAPI_SUPPORT_SPY_AS_STRING) || defined(DOXYGEN)
+
+#define FAPI_PUT_SPY_IMAGE(TARGET, ID, DATA1, DATA2) \
+    fapi2::putSpyImage(TARGET, #ID, DATA1,DATA2)
+
+    template< TargetType K >
+    inline ReturnCode putSpyImage(const Target<K>& i_target,
+                                  const char* const i_spyId,
+                                  const variable_buffer& i_data,
+                                  variable_buffer& o_imageData);
+#endif
+
+    /// @brief Reads spy data from a ring image buffer
+    /// @param[in]   i_target      Target to operate on
+    /// @param[in]   i_spyId       The spy's id
+    /// @param[out]  o_data        Buffer that holds data read from ring image.
+    /// @param[in]   i_imageData   Buffer that holds ring image to read data
+    ///                            from.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note:  The string version is only supported for cronus.
+    ///
+    ///         The fapi design to support both FSP and cronus use of get and
+    ///         put spy functions is dependent on the SPY names being expanded
+    ///         to resemble a valid C identifier. This design places some
+    ///         restrictions on the SPY names which can be used.
+    ///
+    ///         See fapiPutSpy for details on spy id specifics.
+    ///
+#if defined(FAPI_SUPPORT_SPY_AS_ENUM) || defined(DOXYGEN)
+
+#define FAPI_GET_SPY_IMAGE(TARGET, ID, DATA1, DATA2)    \
+    fapi2:getSpyImage(TARGET, FAPI_SPY_NAMES::ID.value, \
+                      DATA1, DATA2)
+
+    template< TargetType K >
+    inline ReturnCode getSpyImage(const Target<K>& i_target,
+                                  const spyId_t i_spyId,
+                                  variable_buffer& o_data,
+                                  const variable_buffer& i_imageData);
+#endif
+
+#if defined(FAPI_SUPPORT_SPY_AS_STRING) || defined(DOXYGEN)
+
+#define FAPI_GET_SPY_IMAGE(TARGET, ID, DATA1, DATA2) \
+    fapi2::getSpyImage(TARGET, #ID, DATA1,DATA2)
+
+    template< TargetType K >
+    inline ReturnCode getSpyImage(const Target<K>& i_target,
+                                  const char * const i_spyId,
+                                  variable_buffer& o_data,
+                                  const variable_buffer& i_imageData);
+#endif
+
+#endif // PPE
+};
+
+#endif // _FAPI2_HWACCESS_H_
diff --git a/src/ppe/hwpf/plat/include/fapi2_target.H b/src/ppe/hwpf/plat/include/fapi2_target.H
new file mode 100644
index 0000000..dfb0efd
--- /dev/null
+++ b/src/ppe/hwpf/plat/include/fapi2_target.H
@@ -0,0 +1,586 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwpf/plat/include/fapi2_target.H $                    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file fapi2_target.H
+/// @brief Common definitions for fapi2 targets
+///
+
+#ifndef __FAPI2_COMMON_TARGET__
+#define __FAPI2_COMMON_TARGET__
+
+#include <stdint.h>
+#include <vector>
+#include <target_types.H>
+#include <target_states.H>
+#include <plat_target.H>
+
+namespace fapi2
+{
+
+
+    ///
+    /// @brief Typedef for chiplet number values
+    ///
+    typedef uint8_t ChipletNumber_t;
+
+    ///
+    /// @brief Class representing a FAPI2 Target
+    /// @tparam K the type (Kind) of target
+    /// @tparam V the type of the target's Value
+    /// @remark TargetLite targets are uint64_t, Targets
+    /// are uintptr_t (void*).
+    ///
+    /// Assuming there are representations of a processor,
+    /// a membuf and a system here are some examples:
+    /// @code
+    /// #define PROCESSOR_CHIP_A 0xFFFF0000
+    /// #define MEMBUF_CHIP_B    0x0000FFFF
+    /// #define SYSTEM_C         0x0000AAAA
+    /// @endcode
+    ///
+    /// * To define a target:
+    /// @code
+    /// fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> A(PROCESSOR_CHIP_A);
+    /// fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> C(SYSTEM_C);
+    /// fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP> B(MEMBUF_CHIP_B);
+    /// @endcode
+    ///
+    /// * Functions which take composite target types
+    /// @code
+    /// void takesProcOrMembuf(
+    /// const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP |
+    ///                     fapi2::TARGET_TYPE_MEMBUF_CHIP>& V );
+    ///
+    /// void takesAny(const fapi2::Target<fapi2::TARGET_TYPE_ALL>& V );
+    ///
+    /// @endcode
+    ///
+    /// * Traversing the target "tree"
+    /// @code
+    /// fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> A(PROCESSOR_CHIP_A);
+    ///
+    /// // Get A's parent
+    /// A.getParent<fapi2::TARGET_TYPE_SYSTEM>();
+    ///
+    /// // Get the 0x53'd core
+    /// fapi2::getTarget<fapi2::TARGET_TYPE_CORE>(0x53);
+    ///
+    /// // Get all *my* present/functional children which are cores
+    /// A.getChildren<fapi2::TARGET_TYPE_CORE>();
+    ///
+    /// // Get all of the the cores relative to my base target
+    /// fapi2::getChildren<fapi2::TARGET_TYPE_CORE>();
+    /// @endcode
+    ///
+    /// * Invalid casts
+    /// @code
+    /// // Can't cast to a specialized target
+    /// fapi2::Target<fapi2::TARGET_TYPE_NONE> D(MEMBUF_CHIP_B);
+    /// takesProcOrMembuf( D );
+    ///
+    /// // Not one of the shared types
+    /// fapi2::Target<fapi2::TARGET_TYPE_ABUS_ENDPOINT> E;
+    /// takesProcOrMembuf( E );
+    /// @endcode
+    template<TargetType K, typename V = plat_target_handle_t>
+    class Target
+    {
+    public:
+
+        ///
+        /// @brief Create a Target, with a value
+        /// @param[in] Value the value (i.e., specific element this
+        /// target represents, or pointer)
+        /// @note Platforms can mangle the value and K to get a
+        /// single uint64_t in value which represents all the information
+        /// they might need. value( K | V ), for example
+        ///
+        Target(V Value);
+        
+//               Target(V Value):
+//            iv_handle(Value)
+//        {}
+
+        ///
+        /// @brief Assignment Operator.
+        /// @param[in] i_right Reference to Target to assign from.
+        /// @return Reference to 'this' Target
+        ///
+        Target& operator=(const Target& i_right);
+
+        ///
+        /// @brief Equality Comparison Operator
+        /// @param[in] i_right Reference to Target to compare.
+        /// @return bool. True if equal.
+        /// @note Platforms need to define this so that the physical
+        /// targets are determined to be equivilent rather than just the handles
+        ///
+        bool operator==(const Target& i_right) const;
+
+        ///
+        /// @brief Inquality Comparison Operator
+        /// @param[in] i_right Reference to Target to compare.
+        /// @return bool. True if not equal.
+        /// @note Platforms need to define this so that the physical
+        /// targets are determined to be equivilent rather than just the handles
+        ///
+        bool operator!=(const Target& i_right) const;
+
+        ///
+        /// @brief Get the handle.
+        /// @return V The target's handle, or value
+        ///
+        V get(void) const
+        {
+            return this->iv_handle.value;
+        }
+
+        ///
+        /// @brief Get the handle as a V
+        /// @return V The target's handle, or value
+        ///
+        inline operator V() const
+        {
+            return this->iv_handle.value;
+        }
+
+        ///
+        /// @brief Get a target's value
+        /// @return V The target's handle, or value
+        ///
+        inline V& operator()(void)
+        {
+            return this->iv_handle.value;
+        }
+
+        ///
+        /// @brief Get the target type
+        /// @return The type of target represented by this target
+        ///
+        inline TargetType getType(void) const
+        {
+            return iv_type;
+        }
+
+        ///
+        /// @brief Get this target's immediate parent
+        /// @tparam T The type of the parent
+        /// @return Target<T> a target representing the parent
+        ///
+        template< TargetType T >
+        inline Target<T> getParent(void) const;
+
+        ///
+        /// @brief Is this target a chip?
+        /// @return Return true if this target is a chip, false otherwise
+        ///
+        inline constexpr bool isChip(void) const
+        {
+//            return ( (K == TARGET_TYPE_PROC_CHIP) ||
+//                     (K == TARGET_TYPE_MEMBUF_CHIP) );
+            
+           return ( (K == TARGET_TYPE_PROC_CHIP) );
+        }
+
+        ///
+        /// @brief Is this target a chiplet?
+        /// @return Return true if this target is a chiplet, false otherwise
+        ///
+        inline constexpr bool isChiplet(void) const
+        {
+           return ( (K == TARGET_TYPE_EX) ||
+//                    (K == TARGET_TYPE_MBA) ||
+                    (K == TARGET_TYPE_MCS) ||
+//                     (K == TARGET_TYPE_XBUS) ||
+//                     (K == TARGET_TYPE_ABUS) ||
+//                     (K == TARGET_TYPE_L4) ||
+                    (K == TARGET_TYPE_CORE) ||
+                    (K == TARGET_TYPE_EQ) ||
+//                     (K == TARGET_TYPE_MCA) ||
+//                     (K == TARGET_TYPE_MCBIST) ||
+//                     (K == TARGET_TYPE_MI) ||
+//                     (K == TARGET_TYPE_DMI) ||
+//                     (K == TARGET_TYPE_OBUS) ||
+//                     (K == TARGET_TYPE_NV) ||
+//                     (K == TARGET_TYPE_SBE) ||
+//                     (K == TARGET_TYPE_PPE) ||
+//                    (K == TARGET_TYPE_PERV) ||
+                    (K == TARGET_TYPE_PERV) );
+//                    (K == TARGET_TYPE_PEC) ||
+//                    (K == TARGET_TYPE_PHB) );
+        }
+
+        ///
+        /// @brief Get this target's children
+        /// @tparam T The type of the parent
+        /// @param[in] i_state The desired TargetState of the children
+        /// @return std::vector<Target<T> > a vector of present/functional
+        /// children
+        /// @warning The children of EX's (cores) are expected to be returned
+        /// in order. That is, core 0 is std::vector[0].
+        ///
+        template< TargetType T>
+        inline std::vector<Target<T> >
+        getChildren(const TargetState i_state = TARGET_STATE_FUNCTIONAL) const;
+
+        ///
+        /// @brief Get the target at the other end of a bus - dimm included
+        /// @tparam T The type of the parent
+        /// @param[in] i_state The desired TargetState of the children
+        /// @return Target<T> a target representing the thing on the other end
+        /// @note Can be easily changed to a vector if needed
+        ///
+        template<TargetType T>
+        inline Target<T>
+        getOtherEnd(const TargetState i_state = TARGET_STATE_FUNCTIONAL) const;
+
+        ///
+        /// @brief Copy from a Target<O> to a Target<K>
+        /// @tparam O the target type of the other
+        ///
+        template<TargetType O>
+        inline Target( const Target<O>& Other ):
+            Target<K, V>(Other.get())
+        {
+            // In case of recursion depth failure, use -ftemplate-depth=
+            static_assert( (K & O) != 0,
+                           "unable to cast Target, no shared types");
+
+            static_assert( bitCount<K>::count >= bitCount<O>::count,
+                           "unable to cast to specialized Target");
+        }
+
+#ifdef __PPE__
+       
+        ///                                                               
+        /// @brief Get the target present setting                         
+        /// @return Bool whether present                                  
+        ///                                                               
+        inline bool getPresent(void) const                                
+        {                                                                 
+            return (this->iv_handle.fields.present ? true : false);       
+        }                                                                 
+
+        ///                                                               
+        /// @brief Get the target functional setting                      
+        /// @return Bool whether functional                               
+        ///                                                               
+        inline bool getFunctional(void) const                             
+        {                                                                 
+            return (this->iv_handle.fields.functional ? true : false);    
+        }                                                                 
+
+        ///                                                               
+        /// @brief Set the target present setting                         
+        /// @return Bool whether present                                  
+        ///                                                               
+        inline void setPresent(void) const                                
+        {                                                                 
+            this->iv_handle.fields.present = 1;                           
+            return;                                                       
+        }                                                                 
+
+        ///                                                               
+        /// @brief Set the target functional setting                      
+        /// @return Bool whether functional                               
+        ///                                                               
+        inline void setFunctional(void) const                             
+        {                                                                 
+            this->iv_handle.fields.functional = 1;                        
+            return;                                                       
+        }                                                                 
+
+
+        /// Need to optimize PPE Target resoulution in a cheap manner
+        /// Brian:  not sure if the this is the place for this as
+        ///  this is plaform specific.
+
+        ///
+        /// @brief Get address overlay to reduce runtime processing
+        /// @return Overlay as a type V
+        ///
+        inline V getAddressOverlay(void) const
+        {
+            return this->iv_handle.fields.address_overlay;
+        }
+
+        ///
+        /// @brief Get target number
+        /// @return Overlay as a type V
+        ///
+        inline uint32_t getTargetNumber(void) const
+        {
+            return static_cast<uint32_t>(this->iv_handle.fields.type_target_num);
+        }
+        
+        ///
+        /// @brief Get target type directly from the handle
+        /// @return Overlay as a type V
+        ///
+        inline TargetTypes_t getTargetType(void) const
+        {
+            return static_cast<TargetTypes_t>(this->iv_handle.fields.type);
+        }
+        
+        ///
+        /// @brief Get chiplet number from the handle
+        /// @return ChipletNumber_t Chiplet Number
+        ///
+        inline ChipletNumber_t getChipletNumber(void) const
+        {
+            return static_cast<ChipletNumber_t>(this->iv_handle.fields.chiplet_num);
+        }
+        
+#endif
+
+
+    private:
+        // Don't use enums here as it makes it hard to assign
+        // in the platform target cast constructor.
+        static const TargetType iv_type = K;
+
+        union iv_handle {
+            V value;
+            struct {
+#ifdef _BIG_ENDIAN
+                V chiplet_num       : 8;
+                V type_target_num   : 8;
+                V type              : 8;
+                V _reserved_b6      : 6;
+                V present           : 1;
+                V functional        : 1;
+                V address_overlay   : 32;
+#else
+                V address_overlay   : 32;
+                V functional        : 1;
+                V present           : 1;
+                V _reserved_b6      : 6;
+                V type              : 8;
+                V type_target_num   : 8;
+                V chiplet_num       : 8;
+#endif
+            } fields;
+            // Union Constructor
+//            iv_handle(V i_value = 0):value(i_value) {}
+        } iv_handle;
+    };
+    
+    // EX threads map to CORE threads:
+    // t0 / t2 / t4 / t6 fused = t0 / t1 / t2 / t3 normal (c0)
+    // t1 / t3 / t5 / t7 fused = t0 / t1 / t2 / t3 normal (c1)
+    // So when splitting the EX, we need to map from EX threads
+    // to CORE threads.
+
+    ///
+    /// @brief Given a normal core thread id, translate this to
+    /// a fused core thread id. (normal to fused)
+    /// @param[in] the ordinal number of the normal core this thread belongs to
+    /// @param[in] a normal core thread id - 0, ..., 3
+    /// @return the fused core thread id
+    ///
+    inline uint8_t thread_id_n2f(const uint8_t i_ordinal, const uint8_t i_thread_id)
+    {
+        return (i_thread_id << 1) | i_ordinal;
+    }
+
+    ///
+    /// @brief Given a fused core thread id, translate this to
+    /// a normal core thread id. (fused to normal)
+    /// @param[in] a fused core thread id - 0, ..., 7
+    /// @return the normal core thread id
+    ///
+    inline uint8_t thread_id_f2n(const uint8_t i_thread_id)
+    {
+        return i_thread_id >> 1;
+    }
+
+    ///
+    /// @brief Given a normal core thread id, translate this to a
+    /// normal core bitset.
+    /// @param[in] a normal core thread id - 0, ..., 3
+    /// @return the normal core bitset
+    /// @note to got from a fused core id to a normal core bitset,
+    /// translate from a fused core thread id first.
+    ///
+    inline uint8_t thread_id2bitset(const uint8_t i_thread_id)
+    {
+        // 0xff means "set all bits"
+        static const uint8_t all_threads  = 0xff;
+        static const uint8_t all_normal_threads_bitset = 0x0f;
+
+        if (i_thread_id == all_threads)
+        {
+            return all_normal_threads_bitset;
+        }
+
+        // A thread_id is really just bit index.
+        return (1 << (4 - i_thread_id - 1));
+    }
+
+    ///
+    /// @brief Given a bitset of normal core thread ids, translate this to
+    /// a bit mask of fused core thread id. (normal to fused)
+    /// @param[in] the ordinal number of the normal core this thread belongs to
+    /// @param[in] a normal core thread bitset - b0000, ..., b1111
+    /// @return the corresponding fused core bitset
+    ///
+    inline uint8_t thread_bitset_n2f(const uint8_t i_ordinal, const uint8_t i_threads)
+    {
+        // Since we only have 4 bits I think this is better than a shift-type solution
+        // for interleaving bits
+        static uint8_t core_map[] = {
+            0b00000000, // b0000
+            0b00000010, // b0001
+            0b00001000, // b0010
+            0b00001010, // b0011
+            0b00100000, // b0100
+            0b00100010, // b0101
+            0b00101000, // b0110
+            0b00101010, // b0111
+            0b10000000, // b1000
+            0b10000010, // b1001
+            0b10001000, // b1010
+            0b10001010, // b1011
+            0b10100000, // b1100
+            0b10100010, // b1101
+            0b10101000, // b1110
+            0b10101010, // b1111
+        };
+
+        return core_map[i_threads] >> i_ordinal;
+    }
+
+    ///
+    /// @brief Given a fused core thread bitset, translate this to
+    /// a normal core thread bitset. (fused to normal)
+    /// @param[in] the ordinal number of the normal core this thread belongs to
+    /// @param[in] a fused core thread bitset - b00000000, ..., b11111111
+    /// @return the corresponding normal core bitset
+    ///
+    inline uint8_t thread_bitset_f2n(const uint8_t i_ordinal, const uint8_t i_threads)
+    {
+        uint8_t normal_set = 0;
+
+        // core 0 is the left-most bit in the pair
+        uint8_t pair_mask = (i_ordinal == 0) ? 0x2 : 0x1;
+
+        // For each bit which can be set in the normal core bit_set ...
+        for( auto i = 0; i <= 3; ++i )
+        {
+            // ... grab the two fused bits which represent it ...
+            // ... and mask off the bit in the pair which represents this normal core ...
+            // (the << 1 shifts the masks over as we walk the pairs of bits)
+            uint8_t bits = (((3 << (i << 1)) & i_threads) & (pair_mask << (i << 1)));
+
+            // ... if either bit is set, set the corresponding bit in
+            // the normal core bitset.
+            normal_set |= (bits != 0) << i;
+        }
+        return normal_set;
+    }
+
+    ///
+    /// @brief Return the string interpretation of this target
+    /// @tparam T The type of the target
+    /// @param[in] i_target Target<T>
+    /// @param[in] i_buffer buffer to write in to
+    /// @param[in] i_bsize size of the buffer
+    /// @return void
+    /// @post The contents of the buffer is replaced with the string
+    /// representation of the target
+    ///
+    template< TargetType T >
+    inline void toString(const Target<T>& i_target, char* i_buffer, size_t i_bsize);
+
+    ///
+    /// @brief Return the string interpretation of this target
+    /// @tparam T The type of the target
+    /// @tparam B The type of the buffer
+    /// @param[in] A pointer to the Target<T>
+    /// @param[in] i_buffer buffer to write in to
+    /// @param[in] i_bsize size of the buffer
+    /// @return void
+    /// @post The contents of the buffer is replaced with the string
+    /// representation of the target
+    ///
+    template< TargetType T >
+    inline void toString(const Target<T>* i_target, char* i_buffer, size_t i_bsize);
+
+    ///
+    /// @brief Get an enumerated target of a specific type
+    /// @tparam T The type of the target
+    /// @param[in] Ordinal representing the ordinal number of
+    /// the desired target
+    /// @return Target<T> the target requested
+    ///
+    template<TargetType T>
+    inline Target<T> getTarget(uint64_t Ordinal);
+
+    // Why has the been removed? For starters, the API name
+    // is probably wrong as it's already been confused with
+    // Target::getChildren(). And if I'm going to change it
+    // I really want to see if we need it. I'm still not
+    // clear on whether we're alloing this traversal or not.
+#if 0
+    ///
+    /// @brief Get the base target's children
+    /// @tparam T The type of the target
+    /// @return std::vector<Target<T> > a vector of present/functional
+    /// children
+    ///
+    template<TargetType T>
+    inline std::vector<Target<T> > getChildren()
+    {
+        // For testing
+        return {Target<T>(), Target<T>()};
+    }
+#endif
+
+    ///
+    /// @brief Return the string interpretation of this target
+    /// @tparam T The type of the target
+    /// @tparam B The type of the buffer
+    /// @param[in] i_target Target<T>
+    /// @param[in] i_buffer buffer
+    /// @return void
+    /// @post The contents of the buffer is replaced with the string
+    /// representation of the target
+    ///
+    template<TargetType T, typename B>
+    inline void toString(const Target<T>& i_target, B& i_buffer);
+
+    ///
+    /// @brief Check if the target is of a type, or in a type subset.
+    /// @tparam K the TargetType to check
+    /// @tparam T TargetType or TargetType composite to check against
+    /// @return True, iff K is a proper T
+    ///
+    template< TargetType K, TargetType T >
+    inline constexpr bool is_same(void)
+    { return (K & T) != 0; }
+
+
+}
+#endif
diff --git a/src/ppe/hwpf/plat/include/hw_access.H b/src/ppe/hwpf/plat/include/hw_access.H
index 758f035..5be9fa0 100644
--- a/src/ppe/hwpf/plat/include/hw_access.H
+++ b/src/ppe/hwpf/plat/include/hw_access.H
@@ -38,6 +38,7 @@
 #include <variable_buffer.H>
 #endif
 
+#include <utils.H>
 #include <plat_hw_access.H>
 #include <fapi2_hw_access.H>
 
@@ -59,7 +60,6 @@ namespace fapi2
     /// @return uint8_t The current PIB error mask
     uint8_t getPIBErrorMask(void)
     {
-        uint8_t o_pib_mask;
         PLAT_GET_PIB_ERROR_MASK(o_pib_mask);
         return o_pib_mask;
     }
@@ -103,11 +103,7 @@ namespace fapi2
     inline void getScom(const Target<K>& i_target, const uint64_t i_address,
                        buffer<uint64_t>& o_data)
     {
-      //   PLAT_GETSCOM(i_target,
-//                     (uint32_t)(i_address & BITS(40,24)),
-//                     &(o_data()));
-                    
-//        fapi2::ReturnCode l_rc;
+
         PLAT_GETSCOM(current_err,
                      i_target,
                     (uint32_t)(i_address & BITS(40,24)),
@@ -123,12 +119,13 @@ namespace fapi2
     /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
     template< TargetType K >
     inline void putScom(const Target<K>& i_target, const uint64_t i_address,
-                       buffer<uint64_t>& i_data)
+                       buffer<uint64_t> i_data)
     {
 
-        PLAT_PUTSCOM(i_target,
+        PLAT_PUTSCOM(current_err,
+                    i_target,
                     (uint32_t)(i_address & BITS(40,24)),
-                    &(i_data()));
+                    i_data());
     }
 
     /// @brief Read-modify-write a SCOM register on a chip
@@ -141,12 +138,13 @@ namespace fapi2
     template< TargetType K >
     inline void modifyScom( const Target<K>& i_target,
                             const uint64_t i_address,
-                            const buffer<uint64_t>& i_data,
+                            const buffer<uint64_t> i_data,
                             const ChipOpModifyMode i_modifyMode)
     {
         fapi2::buffer<uint64_t> l_modifyDataBuffer;
         
-        PLAT_GETSCOM(i_target,
+        PLAT_GETSCOM(current_err,
+                     i_target,
                      (uint32_t)(i_address & BITS(40,24)),
                      &(l_modifyDataBuffer()));
 
@@ -165,9 +163,10 @@ namespace fapi2
             l_modifyDataBuffer ^= i_data;
         }
 
-        PLAT_PUTSCOM(i_target,
+        PLAT_PUTSCOM(current_err,
+                     i_target,
                      (uint32_t)(i_address & BITS(40,24)),
-                     &(l_modifyDataBuffer())); 
+                     l_modifyDataBuffer()); 
         return;
     }
 
@@ -181,16 +180,17 @@ namespace fapi2
     template< TargetType K >
     inline void putScomUnderMask(const Target<K>& i_target,
                                  const uint64_t i_address,
-                                 buffer<uint64_t>& i_data,
-                                 buffer<uint64_t>& i_mask)
+                                 buffer<uint64_t> i_data,
+                                 buffer<uint64_t> i_mask)
     {
         fapi2::buffer<uint64_t> l_modifyDataBuffer = i_data;
 
         l_modifyDataBuffer &= i_mask;
         
-        PLAT_PUTSCOM(i_target,
+        PLAT_PUTSCOM(current_err,
+                    i_target,
                     (uint32_t)(i_address & BITS(40,24)),
-                    &(l_modifyDataBuffer()));
+                    l_modifyDataBuffer());
         return;
     }
           
diff --git a/src/ppe/hwpf/plat/include/plat_attributes.H b/src/ppe/hwpf/plat/include/plat_attributes.H
new file mode 100644
index 0000000..1e3caf1
--- /dev/null
+++ b/src/ppe/hwpf/plat/include/plat_attributes.H
@@ -0,0 +1,36 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwpf/plat/include/plat_attributes.H $                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file plat_attributes.H
+ * @brief Platform specific attribute headers
+ */
+
+#ifndef __PLAT_ATTTRIBUTE_H__
+#define __PLAT_ATTTRIBUTE_H__
+
+#include <fapi2AttributeService.H>
+#include <fapi2AttributeIds.H>      // Generated file
+
+#endif  // __PLAT_ATTTRIBUTE_H__
diff --git a/src/ppe/hwpf/plat/include/plat_error_scope.H b/src/ppe/hwpf/plat/include/plat_error_scope.H
new file mode 100644
index 0000000..45ce05f
--- /dev/null
+++ b/src/ppe/hwpf/plat/include/plat_error_scope.H
@@ -0,0 +1,65 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwpf/plat/include/plat_error_scope.H $                */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file plat_error_scope.H
+ * @brief platform definitions which create a scope for automatic error handling
+ */
+
+#ifndef __FAPI2_PLAT_ERROR_SCOPE__
+#define __FAPI2_PLAT_ERROR_SCOPE__
+
+/// @cond
+#define PLAT_FAPI_TRY_NO_TRACE( __operation__ )                         \
+    (__operation__) 
+
+#define PLAT_FAPI_TRY_TRACE( __operation__, ... )                       \
+    FAPI_DBG(__VA_ARGS));                                               \
+    (__operation__) 
+    
+///
+/// @brief Assert a conditional is true.
+/// If it is not, the FFDC gathering function is called and the
+/// trace is output as a FAPI error trace.
+/// @param[in] __conditional__ the condition to assert
+/// @param[in] __ffdc__ the FFDC gathering function
+/// @param[in] ... varargs, as input to FAPI_ERR
+///
+#define PLAT_FAPI_ASSERT( __conditional__, __ffdc__, ... )      \
+    if (! (__conditional__))                                    \
+    {                                                           \
+        (__ffdc__).execute();                                   \
+        FAPI_ERR(__VA_ARGS__);                                  \
+        goto fapi_try_exit;                                     \
+    }
+    
+    
+///
+/// @brief Temporary macro for error label until all are removed.
+/// @todo REMOVE this in time.
+#define FAPI_CLEANUP()   \
+fapi_try_exit:
+/// @endcond
+
+#endif
diff --git a/src/ppe/hwpf/plat/include/plat_hw_access.H b/src/ppe/hwpf/plat/include/plat_hw_access.H
index 429ceff..3d2a63e 100644
--- a/src/ppe/hwpf/plat/include/plat_hw_access.H
+++ b/src/ppe/hwpf/plat/include/plat_hw_access.H
@@ -75,8 +75,8 @@ asm volatile \
     PPE_LVDX(_m_base.getAddressOverlay(), (uint32_t)(_m_offset & BITS(40,24)), _m_data)
     
 /// PutScom
-#define PLAT_PUTSCOM(_m_base, _m_offset, _m_data) \
-    PPE_STVDX(_m_rc, _m_base.getAddressOverlay(), (uint32_t)(_m_offset & BITS(40,24)), _m_data)
+#define PLAT_PUTSCOM(_m_rc, _m_base, _m_offset, _m_data) \
+    PPE_STVDX(_m_base.getAddressOverlay(), (uint32_t)(_m_offset & BITS(40,24)), _m_data)
     
 /// ModifyScom
 #define PLAT_MODSCOM(_m_base, _m_offset, _m_data, _m_mode) \
diff --git a/src/ppe/hwpf/plat/include/plat_target.H b/src/ppe/hwpf/plat/include/plat_target.H
index a9c1866..d307ab2 100644
--- a/src/ppe/hwpf/plat/include/plat_target.H
+++ b/src/ppe/hwpf/plat/include/plat_target.H
@@ -30,6 +30,8 @@
 #ifndef __FAPI2_PLAT_TARGET__
 #define __FAPI2_PLAT_TARGET__
 
+#include <return_code.H>
+
 //
 // Define what a platform handle looks like. For Hostboot,
 // for example, this might be a void*. For the SBE, this
@@ -38,6 +40,6 @@
 namespace fapi2
 {
     typedef uint64_t plat_target_handle_t;
-}
 
+} 
 #endif
diff --git a/src/ppe/hwpf/plat/include/plat_target_parms.H b/src/ppe/hwpf/plat/include/plat_target_parms.H
index 2c724a3..aa8eb74 100644
--- a/src/ppe/hwpf/plat/include/plat_target_parms.H
+++ b/src/ppe/hwpf/plat/include/plat_target_parms.H
@@ -30,33 +30,42 @@
 #ifndef __FAPI2_PPE_TARGET_PARMS__
 #define __FAPI2_PPE_TARGET_PARMS__
 
+#include "fapi_sbe_common.H"
 
-#ifndef __ASSEMBLER__
 
-const uint64_t CHIPLET_COUNT        = 0x38;
+CONST_UINT32_T(CHIP_TARGET_OFFSET,      0);
+CONST_UINT32_T(CHIP_TARGET_COUNT ,      1);
 
-const uint64_t CHIP_TARGET_COUNT    = 1;
-const uint64_t CHIP_TARGET_OFFSET   = 0;
 
-const uint64_t PERV_TARGET_OFFSET   = CHIP_TARGET_OFFSET + CHIP_TARGET_COUNT;
-const uint64_t PERV_CHIPLET_OFFSET  = 0x1; 
-const uint64_t PERV_TARGET_COUNT    = 15;
+CONST_UINT32_T(PERV_TARGET_OFFSET, CHIP_TARGET_OFFSET + CHIP_TARGET_COUNT);
+CONST_UINT32_T(PERV_CHIPLET_OFFSET,     0x1); 
+CONST_UINT32_T(PERV_TARGET_COUNT,       15);
 
-const uint64_t EQ_TARGET_OFFSET     = PERV_TARGET_OFFSET + PERV_TARGET_COUNT;
-const uint64_t EQ_CHIPLET_OFFSET    = 0x10;  
-const uint64_t EQ_TARGET_COUNT      = 6; 
+CONST_UINT32_T(EQ_TARGET_OFFSET, PERV_TARGET_OFFSET + PERV_TARGET_COUNT);
+CONST_UINT32_T(EQ_CHIPLET_OFFSET,       0x10);  
+CONST_UINT32_T(EQ_TARGET_COUNT,         6); 
 
-const uint64_t CORE_TARGET_OFFSET   = EQ_TARGET_OFFSET + EQ_TARGET_COUNT; 
-const uint64_t CORE_CHIPLET_OFFSET  = 0x20;
-const uint64_t CORE_TARGET_COUNT    = 24;
+CONST_UINT32_T(CORE_TARGET_OFFSET, EQ_TARGET_OFFSET + EQ_TARGET_COUNT); 
+CONST_UINT32_T(CORE_CHIPLET_OFFSET,     0x20);
+CONST_UINT32_T(CORE_TARGET_COUNT,       24);
 
-const uint64_t EX_TARGET_OFFSET     = CORE_TARGET_OFFSET + CORE_TARGET_COUNT;
-const uint64_t EX_CHIPLET_OFFSET    = 0x10;  
-const uint64_t EX_TARGET_COUNT      = 12;
+CONST_UINT32_T(MCS_TARGET_OFFSET, CORE_TARGET_OFFSET + CORE_TARGET_COUNT);
+CONST_UINT32_T(MCS_CHIPLET_OFFSET,      0x7);  
+CONST_UINT32_T(MCS_TARGET_COUNT,        2);
 
+CONST_UINT32_T(EX_TARGET_OFFSET, MCS_TARGET_OFFSET + MCS_TARGET_COUNT); 
+CONST_UINT32_T(EX_CHIPLET_OFFSET,       0x10);  
+CONST_UINT32_T(EX_TARGET_COUNT,         12);
 
-const uint64_t TARGET_COUNT         = EX_TARGET_OFFSET + EX_TARGET_COUNT;
 
-#endif
+//CONST_UINT32_T(TARGET_COUNT, EX_TARGET_OFFSET + EX_TARGET_COUNT);
+
+CONST_UINT32_T(TARGET_COUNT,            CHIP_TARGET_COUNT +
+                                        PERV_TARGET_COUNT +
+                                        EQ_TARGET_COUNT +
+                                        CORE_TARGET_COUNT +
+                                        MCS_TARGET_COUNT +
+                                        EX_TARGET_COUNT);
+                                        
 
 #endif  // __FAPI2_PPE_TARGET_PARMS__
diff --git a/src/ppe/hwpf/plat/include/plat_target_utils.H b/src/ppe/hwpf/plat/include/plat_target_utils.H
new file mode 100644
index 0000000..dc60cc9
--- /dev/null
+++ b/src/ppe/hwpf/plat/include/plat_target_utils.H
@@ -0,0 +1,48 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/hwpf/plat/include/plat_target_utils.H $               */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file plat_target_util.H
+ * @brief platform utility definitions for fapi2 targets
+ */
+
+#ifndef __FAPI2_PLAT_TARGET_UTIL__
+#define __FAPI2_PLAT_TARGET_UTIL__
+
+//
+// Platform Utility functions..
+//
+namespace fapi2
+{
+
+    /// @brief Function to initialize the G_targets vector based on partial good
+    ///      attributes
+    ReturnCode plat_TargetsInit();
+    
+    /// @brief Function to initialize the G_targets vector based on partial good
+    ///      attributes
+    Target<TARGET_TYPE_PROC_CHIP> plat_getChipTarget();
+
+} 
+#endif
diff --git a/src/ppe/hwpf/plat/include/plat_trace.H b/src/ppe/hwpf/plat/include/plat_trace.H
index d656d60..16a99ca 100644
--- a/src/ppe/hwpf/plat/include/plat_trace.H
+++ b/src/ppe/hwpf/plat/include/plat_trace.H
@@ -38,6 +38,15 @@
 #include <stdio.h>
 #include <stdint.h>
 
+// @todo  update these headers with extern "C" in a future commit
+//        or not and leave this just as it is.
+extern "C" 
+{
+#include "pk.h"
+#include <pk_trace.h>
+#include "trac_interface.h"
+}
+
 // Why not a #define, why is this in the fapi2 namespace?
 // To prevent problems with Cronus and the fapi1 definitions.
 namespace fapi2
@@ -47,9 +56,16 @@ namespace fapi2
 
 // Information traces (go into fast trace buffer that can wrap often)
 #define FAPI_TRACE(_id_, _fmt_, _args_...)                              \
-    printf("%s: %s:%d ", _id_, __func__, __LINE__);                     \
-    printf(_fmt_, ##_args_);                                            \
-    printf("\n")
+    PK_TRACE(_fmt_, ##_args_);
+
+
+/*  The following is a desirous trace entry but the second line has a
+    compilation issue that is unresolved
+    
+#define FAPI_TRACE(_id_, _fmt_, _args_...)                              \
+    PK_TRACE("%s: %s:%d ", _id_, __FUNCTION__, __LINE__);               \
+    PK_TRACE(_fmt_, ##_args_);
+*/
 
 #define FAPI_INF(_fmt_, _args_...) FAPI_TRACE("inf", _fmt_, ##_args_)
 
diff --git a/src/ppe/hwpf/plat/include/return_code.H b/src/ppe/hwpf/plat/include/return_code.H
index 67aa0ab..7735602 100644
--- a/src/ppe/hwpf/plat/include/return_code.H
+++ b/src/ppe/hwpf/plat/include/return_code.H
@@ -31,90 +31,24 @@
 #define __FAPI2_RETURN_CODE__
 
 #include <stdint.h>
+#include <return_code_defs.H>
 
-// Remove this for platforms which don't support FFDC
-//#include <ffdc.H>
-
-///
-/// @brief Set HWP Error macro
-///
-/// This macro should be used by a HWP to create an error. The ReturnCode's
-/// internal return code is set and any error information in the Error XML file
-/// is added to the ReturnCode
-///
-#define FAPI_SET_HWP_ERROR(RC, ERROR) \
-    RC._setHwpError(fapi2::ERROR); \
-    ERROR##_CALL_FUNCS_TO_COLLECT_FFDC(RC); \
-    ERROR##_CALL_FUNCS_TO_COLLECT_REG_FFDC(RC); \
-    ERROR##_ADD_ERROR_INFO(RC)
-
-///
-/// @brief Add info to HWP Error macro
-///
-/// This macro should be used by an FFDC HWP to add error information from an
-/// Error XML file to an existing error.
-///
-#define FAPI_ADD_INFO_TO_HWP_ERROR(RC, ERROR) \
-    ERROR##_CALL_FUNCS_TO_COLLECT_FFDC(RC); \
-    ERROR##_CALL_FUNCS_TO_COLLECT_REG_FFDC(RC); \
-    ERROR##_ADD_ERROR_INFO(RC)
+#ifndef FAPI2_NO_FFDC
+  #include <ffdc.H>
+#endif
 
 namespace fapi2
 {
     ///
-    /// @brief Enumeration of return codes
-    ///
-    enum ReturnCodes
-    {
-        ///< Success
-        FAPI2_RC_SUCCESS = 0,
-
-        // Flag bits indicating which code generated the error.
-        FAPI2_RC_FAPI2_MASK = 0x04000000, ///< FAPI2 mask
-        FAPI2_RC_PLAT_MASK =  0x02000000, ///< Platform mask
-        FAPI2_RC_HWP_MASK =   0x00000000, ///< HWP mask
-
-        //
-        // FAPI generated return codes
-        //
-
-        FAPI2_RC_INVALID_ATTR_GET            = FAPI2_RC_FAPI2_MASK | 0x01,
-        ///< Initfile requested an attribute with an invalid attribute ID
-
-        FAPI2_RC_INVALID_CHIP_EC_FEATURE_GET = FAPI2_RC_FAPI2_MASK | 0x02,
-        ///< HWP requested a chip EC feature with an invalid attribute ID
-
-        FAPI2_RC_INVALID_MULTISCOM_LENGTH    = FAPI2_RC_FAPI2_MASK | 0x03,
-        ///< Invalid multiscom parameters
-
-        FAPI2_RC_INVALID_PARAMETER           = FAPI2_RC_FAPI2_MASK | 0x04,
-        ///< Invalid parameters to a FAPI2 function
-
-        FAPI2_RC_OVERFLOW                    = FAPI2_RC_FAPI2_MASK | 0x05,
-        ///< Overflow condition, typically a buffer operation
-
-        //
-        // PLAT generated return codes. Additional details may be contained in
-        // ReturnCode platData (this can only be looked at by PLAT code)
-        //
-
-        FAPI2_RC_PLAT_ERR_SEE_DATA   = FAPI2_RC_PLAT_MASK | 0x01,
-        ///< Generic platform error
-
-        FAPI2_RC_PLAT_ERR_ADU_LOCKED = FAPI2_RC_PLAT_MASK | 0x02,
-        ///< Operation to AlterDisplay unit failed because it is locked
-
-        FAPI2_RC_PLAT_NOT_SUPPORTED_AT_RUNTIME = FAPI2_RC_PLAT_MASK | 0x03,
-        ///< Operation not supported by HB runtime
-    };
-
-
-    ///
     /// @brief Class representing a FAPI2 ReturnCode
     ///
-    /// @note Remove the inheritance relationship with FirstFailureData if
-    /// the platform doesn't support FFDC.
+    // Remove the inheritance relationship with FirstFailureData if
+    // the platform doesn't support FFDC.
+#ifdef FAPI2_NO_FFDC
     class ReturnCode
+#else
+    class ReturnCode : public FirstFailureData<ReturnCode>
+#endif
     {
     public:
 
@@ -122,7 +56,7 @@ namespace fapi2
         /// @brief Constructor.
         /// @param[in] i_rc the rc to set
         ///
-        ReturnCode(const uint32_t i_rc = FAPI2_RC_SUCCESS):
+        ReturnCode(const uint64_t i_rc = FAPI2_RC_SUCCESS):
             iv_rc(i_rc)
             {};
 
@@ -130,7 +64,7 @@ namespace fapi2
         /// @brief integral type conversion function. Returns the error code
         /// @return The error code
         ///
-        inline operator uint32_t() const { return iv_rc; }
+        inline operator uint64_t() const { return iv_rc; }
 
         ///
         /// @brief Returns true iff iv_rc == SUCCESS
@@ -141,47 +75,34 @@ namespace fapi2
         ///
         /// @brief Assignement operator
         ///
-        inline ReturnCode& operator=(const uint32_t& rhs)
-            {
-                iv_rc = rhs;
-                return *this;
-            }
-
+#ifdef DOXYGEN
+        inline ReturnCode& operator=(const uint64_t& rhs)
         inline ReturnCode& operator=(const ReturnCodes& rhs)
-            {
-                iv_rc = rhs;
-                return *this;
-            }
+#endif
 
-        inline bool operator==(const uint32_t& rhs) const
+        inline bool operator==(const uint64_t& rhs) const
             { return rhs == iv_rc; }
 
         inline bool operator==(const ReturnCodes& rhs) const
             { return rhs == iv_rc; }
 
-        inline bool operator!=(const uint32_t& rhs) const
+        inline bool operator!=(const uint64_t& rhs) const
             { return rhs != iv_rc; }
 
         inline bool operator!=(const ReturnCodes& rhs) const
             { return rhs != iv_rc; }
-        
-        ReturnCode& insertPIBcode(const uint32_t& pibrc) 
-            {
-                iv_rc = FAPI2_RC_PLAT_MASK | pibrc;
-                return *this;
-            }
 
     private:
-        uint32_t iv_rc;
+        uint64_t iv_rc;
     };
 
     /// This implementation assumes no exception handling and leverages thread-local
     /// storage. For platforms without thread support, a global variable will
     /// suffice for the error state.
-    extern thread_local ReturnCode current_err;      /// the current error state
-    extern thread_local uint32_t pib_error_mask;     /// the pib mask
-    extern thread_local uint32_t operational_state;  /// the operational mode
-
-};
+//    extern thread_local ReturnCode current_err;      /// the current error state
+    extern ReturnCode current_err;      /// the current error state
+    extern thread_local uint64_t pib_error_mask;     /// the pib mask
+    extern thread_local uint64_t operational_state;  /// the operational mode
+}
 
 #endif
diff --git a/src/ppe/hwpf/plat/include/target.H b/src/ppe/hwpf/plat/include/target.H
index c23b43e..f37ef6c 100644
--- a/src/ppe/hwpf/plat/include/target.H
+++ b/src/ppe/hwpf/plat/include/target.H
@@ -24,530 +24,381 @@
 /* IBM_PROLOG_END_TAG                                                     */
 /**
  * @file target.H
- * @brief definitions for fapi2 targets
+ * @brief platform specializations for fapi2 targets
  */
 
 #ifndef __FAPI2_TARGET__
 #define __FAPI2_TARGET__
 
-#include <stdint.h>
-//#include <vector>
-#include <target_types.H>
+#include <plat_target.H>
+#include <plat_target_parms.H>
+#include <fapi2_target.H>
+#include <plat_trace.H>
 #include <utils.H>
-#include "plat_target_parms.H"
-
-#define MC_ENABLE   0x1 << 6
-#define MC_WRITE    5
-#define MC_READ_OR  0
-#define MC_READ_AND 1
-
-#define EX_ADDRESS_MASK 0x0000FF00
-
-#ifdef __ASSEMBLER__
-
-#ifndef ULL
-#define ULL(x) x
-#endif
-
-#else
-
-#ifndef ULL
-#define ULL(x) x##ull
-
-#endif
-
-#endif // __ASSEMBLER
-
-/// Create a multi-bit mask of \a n bits starting at bit \a b
-#define BITS(b, n) ((ULL(0xffffffffffffffff) << (64 - (n))) >> (b))
-
-/// Create a single bit mask at bit \a b
-#define BIT(b) BITS((b), 1)
+#include <stdio.h>
+#include <stdint.h>
+#include <vector>
 
+extern "C"
+{
+    extern std::vector<fapi2::plat_target_handle_t> G_vec_targets;
+}
 
 namespace fapi2
 {
+    /// @brief Create a Target, with a value
+    /// @param[in] Value the value (i.e., specific element this
+    /// target represents, or pointer)
+    /// @note Platforms can mangle the value and K to get a
+    /// single uint64_t in value which represents all the information
+    /// they might need. value( K | V ), for example
     ///
-    /// @brief Class representing a FAPI2 Target
-    /// @tparam K the type (Kind) of target
-    /// @tparam V the type of the target's Value
-    /// @remark TargetLite targets are uint64_t, Targets
-    /// are uintptr_t (void*).
-    ///
-    /// Assuming there are representations of a processor,
-    /// a membuf and a system here are some examples:
-    /// @code
-    /// #define PROCESSOR_CHIP_A 0xFFFF0000
-    /// #define MEMBUF_CHIP_B    0x0000FFFF
-    /// #define SYSTEM_C         0x0000AAAA
-    /// @endcode
-    ///
-    /// * To define a target:
-    /// @code
-    /// fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> A(PROCESSOR_CHIP_A);
-    /// fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> C(SYSTEM_C);
-    /// fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP> B(MEMBUF_CHIP_B);
-    /// @endcode
-    ///
-    /// * Functions which take composite target types
-    /// @code
-    /// void takesProcOrMembuf(
-    /// const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP |
-    ///                     fapi2::TARGET_TYPE_MEMBUF_CHIP>& V );
-    ///
-    /// void takesAny(const fapi2::Target<fapi2::TARGET_TYPE_ALL>& V );
-    ///
-    /// @endcode
-    ///
-    /// * Traversing the target "tree"
-    /// @code
-    /// fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> A(PROCESSOR_CHIP_A);
-    ///
-    /// // Get A's parent
-    /// A.getParent<fapi2::TARGET_TYPE_SYSTEM>();
-    ///
-    /// // Get the 0x53'd core
-    /// fapi2::getTarget<fapi2::TARGET_TYPE_CORE>(0x53);
-    ///
-    /// // Get all *my* present/functional children which are cores
-    /// A.getChildren<fapi2::TARGET_TYPE_CORE>();
-    ///
-    /// // Get all of the the cores relative to my base target
-    /// fapi2::getChildren<fapi2::TARGET_TYPE_CORE>();
-    /// @endcode
-    ///
-    /// * Invalid casts
-    /// @code
-    /// // Can't cast to a specialized target
-    /// fapi2::Target<fapi2::TARGET_TYPE_NONE> D(MEMBUF_CHIP_B);
-    /// takesProcOrMembuf( D );
-    ///
-    /// // Not one of the shared types
-    /// fapi2::Target<fapi2::TARGET_TYPE_ABUS_ENDPOINT> E;
-    /// takesProcOrMembuf( E );
-    /// @endcode
-    template<TargetType K, typename V = uint64_t>
-    class Target
+    template<TargetType K, typename V>
+    Target<K, V>::Target(V Value)
     {
-    public:     
-       
-        ///
-        /// @brief Create a Target, with a value
-        /// @param[in] V the value (i.e., specific element this
-        /// target represents, or pointer)
-        /// @note Platforms can mangle the value and K to get a
-        /// single uint64_t in value which represents all the information
-        /// they might need. value( K | V ), for example
-        ///
-        
-        /// Default constructor is basically a TARGET_TYPE_ALL
-        Target()
+        static_assert( ((K == TARGET_TYPE_CORE) &
+                            (K == TARGET_TYPE_EQ)       ) != true,
+            "TARGET_TYPE_CORE and TARGET_TYPE_EQ cannot be specified at the same time");
+
+        this->iv_handle.value = 0;
+        if(K & TARGET_TYPE_PROC_CHIP)
         {
             this->iv_handle.fields.chiplet_num = 0;
-//            this->iv_address.fields.chiplet_num = this->iv_handle.fields.chiplet_num;             
+            this->iv_handle.fields.type = TARGET_TYPE_PROC_CHIP;
+            this->iv_handle.fields.type_target_num = 0;
         }
-        
-        Target( V Value )
-        {
-            static_assert( ((K == TARGET_TYPE_CORE) &
-                                (K == TARGET_TYPE_EQ)       ) != true,
-                "TARGET_TYPE_CORE and TARGET_TYPE_EQ cannot be specified at the same time");
-            
-            if(K & TARGET_TYPE_PROC_CHIP)
-            {
-                this->iv_handle.fields.chiplet_num = Value;
-                this->iv_handle.fields.type = TARGET_TYPE_PROC_CHIP;
-                this->iv_handle.fields.type_target_num = Value;  // TODO:  check this
-//                this->iv_address.fields.chiplet_num = Value;
-            }
-
-            if(K & TARGET_TYPE_PERV)
-            {
-                this->iv_handle.fields.chiplet_num = Value;
-                this->iv_handle.fields.type = TARGET_TYPE_PERV | TARGET_TYPE_PROC_CHIP; 
-                this->iv_handle.fields.type_target_num = Value;  // TODO:  check this
-//                this->iv_address.fields.chiplet_num = this->iv_handle.fields.chiplet_num;
-            }
 
-            if(K & TARGET_TYPE_CORE)
-            {
-                /*
-                if (Value > CORE_CHIPLET_COUNT)
-                {
-                   PK_TRACE("Chiplet number is greater than CORE_CHIPLET_COUNT");
-                   return -1;
-                }
-                */
-                this->iv_handle.fields.chiplet_num = Value + CORE_CHIPLET_OFFSET;
-                this->iv_handle.fields.type = TARGET_TYPE_CORE;
-                this->iv_handle.fields.type_target_num = Value;
-//                this->iv_address.fields.chiplet_num = this->iv_handle.fields.chiplet_num;
-            }
+        if(K & TARGET_TYPE_PERV)
+        {
+            this->iv_handle.fields.chiplet_num = Value;
+            this->iv_handle.fields.type = TARGET_TYPE_PERV;
+            this->iv_handle.fields.type_target_num = Value;
+        }
 
-            if(K & TARGET_TYPE_EQ)
-            {
-                this->iv_handle.fields.chiplet_num = Value + EQ_CHIPLET_OFFSET;
-                this->iv_handle.fields.type = TARGET_TYPE_EQ;
-                this->iv_handle.fields.type_target_num = Value;
-//                this->iv_address.fields.chiplet_num = this->iv_handle.fields.chiplet_num;
-            }
-            
-            if(K & TARGET_TYPE_EX)
-            {                                           
-                               
-                this->iv_handle.fields.chiplet_num = (Value / 2) + EX_CHIPLET_OFFSET;               
-                this->iv_handle.fields.type = TARGET_TYPE_EX;
-                this->iv_handle.fields.type_target_num = Value;
-//                this->iv_address.fields.chiplet_num = this->iv_handle.fields.chiplet_num;
-            }
-            
-            if(K & TARGET_TYPE_EQ_MC_WRITE)
-            {
-                this->iv_handle.fields.chiplet_num =  
-                                (((MC_ENABLE) | 
-                                 ((MC_WRITE << 3) | (Value & 0x07))) &
-                                  BITS(57,7));
-                this->iv_handle.fields.type = TARGET_TYPE_EQ_MC_WRITE;
-//                this->iv_address.fields.chiplet_num = this->iv_handle.fields.chiplet_num;              
-            }
-            
-            if(K & TARGET_TYPE_EQ_MC_READOR)
-            {
-                this->iv_handle.fields.chiplet_num = 
-                               (((MC_ENABLE) | 
-                                ((MC_READ_OR << 3) | (Value & 0x07))) &
-                                 BITS(57,7));
-                this->iv_handle.fields.type = TARGET_TYPE_EQ_MC_READOR;
-//                this->iv_address.fields.chiplet_num = this->iv_handle.fields.chiplet_num;                
-            }
-            
-            if(K & TARGET_TYPE_EQ_MC_READAND)
-            {
-                this->iv_handle.fields.chiplet_num = 
-                                (((MC_ENABLE) | 
-                                 ((MC_READ_AND << 3) | (Value & 0x07))) &
-                                  BITS(57,7));
-                this->iv_handle.fields.type = TARGET_TYPE_EQ_MC_READAND;
-//                this->iv_address.fields.chiplet_num = this->iv_handle.fields.chiplet_num;               
-            }
-            
-            if(K & TARGET_TYPE_CORE_MC_WRITE)
-            {
-                this->iv_handle.fields.chiplet_num = 
-                                (((MC_ENABLE) | 
-                                 ((MC_WRITE << 3) | (Value & 0x07))) &
-                                 BITS(57,7));
-                this->iv_handle.fields.type = TARGET_TYPE_CORE_MC_WRITE;
-//                this->iv_address.fields.chiplet_num = this->iv_handle.fields.chiplet_num;
-            }
- 
-            if(K & TARGET_TYPE_CORE_MC_READOR)
-            {
-                this->iv_handle.fields.chiplet_num = 
-                                (((MC_ENABLE) | 
-                                 ((MC_READ_OR << 3) | (Value & 0x07))) &
-                                 BITS(57,7));
-                this->iv_handle.fields.type = TARGET_TYPE_CORE_MC_READOR;
-//                this->iv_address.fields.chiplet_num = this->iv_handle.fields.chiplet_num;
-            }
- 
-            if(K & TARGET_TYPE_CORE_MC_READAND)
-            {
-                this->iv_handle.fields.chiplet_num = 
-                                (((MC_ENABLE) | 
-                                 ((MC_READ_AND << 3) | (Value & 0x07))) &
-                                  BITS(57,7));
-                this->iv_handle.fields.type = TARGET_TYPE_CORE_MC_READAND;
-//                this->iv_address.fields.chiplet_num = this->iv_handle.fields.chiplet_num;               
-            }
-            
-            if(K == TARGET_TYPE_ALL)
+        if(K & TARGET_TYPE_CORE)
+        {
+            /*
+            if (Value > CORE_CHIPLET_COUNT)
             {
-                this->iv_handle.fields.chiplet_num = Value;
-                this->iv_handle.fields.type = TARGET_TYPE_ALL;
-//                this->iv_address.fields.chiplet_num = this->iv_handle.fields.chiplet_num;
+               PK_TRACE("Chiplet number is greater than CORE_CHIPLET_COUNT");
+               return -1;
             }
-            
-//             if(K == TARGET_TYPE_ADDRESS)
-//             {
-//                 this->iv_handle.fields.chiplet_num = Value;
-//                 this->iv_address.fields.chiplet_num = this->iv_handle.fields.chiplet_num;
-//             }
-        }          
-
-        ///
-        /// @brief Assignment Operator.
-        /// @param[in] i_right Reference to Target to assign from.
-        /// @return Reference to 'this' Target
-        ///
-        Target<K,V>& operator=(const Target<K,V>& i_right)
-        {
-            this->iv_handle.value = i_right->iv_handle.value;
-            this->iv_addresss.value = i_right->iv_address.value;
-            return *this;
-        }     
-        
-        ///
-        /// @brief Equality Comparison Operator
-        /// @param[in] i_right Reference to Target to compare.
-        /// @return bool. True if equal.
-        ///
-        bool operator==(const Target<K,V>& i_right) const
-        {
-            if (this->iv_handle.value == i_right->iv_handle.value)
-                return true;
-            else
-                return false;
+            */
+            this->iv_handle.fields.chiplet_num = Value + CORE_CHIPLET_OFFSET;
+            this->iv_handle.fields.type = TARGET_TYPE_CORE | TARGET_TYPE_PERV;
+            this->iv_handle.fields.type_target_num = Value;
         }
-        ///
-        /// @brief Inquality Comparison Operator
-        /// @param[in] i_right Reference to Target to compare.
-        /// @return bool. True if equal.
-        ///
-        bool operator!=(const Target<K,V>& i_right) const
+
+        if(K & TARGET_TYPE_EQ)
         {
-            if (this->iv_handle.value != i_right->iv_handle.value)
-                return true;
-            else
-                return false;
+            this->iv_handle.fields.chiplet_num = Value + EQ_CHIPLET_OFFSET;
+            this->iv_handle.fields.type = TARGET_TYPE_EQ | TARGET_TYPE_PERV;
+            this->iv_handle.fields.type_target_num = Value;
         }
 
-        ///
-        /// @brief Get the handle.
-        /// @return V The target's handle, or value
-        ///
-        V get(void) const
-         {
-            return this->iv_handle.value;
-        }
- 
-        ///
-        /// @brief Get the handle as a V
-        /// @return V The target's handle, or value
-        ///
-        operator V() const
+        if(K & TARGET_TYPE_EX)
         {
-            return this->iv_handle.value;
+
+            this->iv_handle.fields.chiplet_num = (Value / 2) + EX_CHIPLET_OFFSET;
+            this->iv_handle.fields.type = TARGET_TYPE_EX | TARGET_TYPE_PERV;
+            this->iv_handle.fields.type_target_num = Value;
         }
-        
-        ///
-        /// @brief Get a target's value
-        /// @return V The target's handle, or value
-        ///
-        V& operator()(void)
+
+        if(K & TARGET_TYPE_MCS)
         {
-            return *this->iv_handle;
+
+            this->iv_handle.fields.chiplet_num = Value + MCS_CHIPLET_OFFSET;
+            this->iv_handle.fields.type = TARGET_TYPE_MCS | TARGET_TYPE_PERV;
+            this->iv_handle.fields.type_target_num = Value;
         }
 
-        ///
-        /// @brief Get the target type
-        /// @return The type of target represented by this target
-        ///
-        TargetType getType(void) const
+//         if(K & TARGET_TYPE_EQ_MC_WRITE)
+//         {
+//             this->iv_handle.fields.chiplet_num =
+//                             (((MC_ENABLE) |
+//                              ((MC_WRITE << 3) | (Value & 0x07))) &
+//                               BITS(57,7));
+//             this->iv_handle.fields.type = TARGET_TYPE_EQ_MC_WRITE;
+//         }
+//
+//         if(K & TARGET_TYPE_EQ_MC_READOR)
+//         {
+//             this->iv_handle.fields.chiplet_num =
+//                            (((MC_ENABLE) |
+//                             ((MC_READ_OR << 3) | (Value & 0x07))) &
+//                              BITS(57,7));
+//             this->iv_handle.fields.type = TARGET_TYPE_EQ_MC_READOR;
+//         }
+//
+//         if(K & TARGET_TYPE_EQ_MC_READAND)
+//         {
+//             this->iv_handle.fields.chiplet_num =
+//                             (((MC_ENABLE) |
+//                              ((MC_READ_AND << 3) | (Value & 0x07))) &
+//                               BITS(57,7));
+//             this->iv_handle.fields.type = TARGET_TYPE_EQ_MC_READAND;
+//         }
+//
+//         if(K & TARGET_TYPE_CORE_MC_WRITE)
+//         {
+//             this->iv_handle.fields.chiplet_num =
+//                             (((MC_ENABLE) |
+//                              ((MC_WRITE << 3) | (Value & 0x07))) &
+//                              BITS(57,7));
+//             this->iv_handle.fields.type = TARGET_TYPE_CORE_MC_WRITE;
+//         }
+//
+//         if(K & TARGET_TYPE_CORE_MC_READOR)
+//         {
+//             this->iv_handle.fields.chiplet_num =
+//                             (((MC_ENABLE) |
+//                              ((MC_READ_OR << 3) | (Value & 0x07))) &
+//                              BITS(57,7));
+//             this->iv_handle.fields.type = TARGET_TYPE_CORE_MC_READOR;
+//         }
+//
+//         if(K & TARGET_TYPE_CORE_MC_READAND)
+//         {
+//             this->iv_handle.fields.chiplet_num =
+//                             (((MC_ENABLE) |
+//                              ((MC_READ_AND << 3) | (Value & 0x07))) &
+//                               BITS(57,7));
+//             this->iv_handle.fields.type = TARGET_TYPE_CORE_MC_READAND;
+//         }
+
+        if(K == TARGET_TYPE_ALL)
         {
-            return (TargetType)this->iv_handle.fields.type;
+            this->iv_handle.fields.chiplet_num = Value;
+            this->iv_handle.fields.type = TARGET_TYPE_ALL;
         }
-        
-        ///
-        /// @brief Get address overlay to reduce runtime processing
-        /// @return Overlay as a type V
-        ///
-        V getAddressOverlay(void) const
+        this->iv_handle.fields.present = 1;
+        this->iv_handle.fields.functional = 1;
+        this->iv_handle.fields.address_overlay =
+                (this->iv_handle.fields.chiplet_num << 24);
+
+    }
+
+    ///
+    /// @brief Assignment Operator.
+    /// @param[in] i_right Reference to Target to assign from.
+    /// @return Reference to 'this' Target
+    ///
+    template<TargetType K, typename V>
+    Target<K, V>& Target<K, V>::operator=(const Target& i_right)
         {
-            return this->iv_handle.fields.address_overlay;
+            this->iv_handle.value = i_right->iv_handle.value;
+            return *this;
         }
+    ///
+    /// @brief Equality Comparison Operator
+    /// @param[in] i_right Reference to Target to compare.
+    /// @return bool. True if equal.
+    /// @note Platforms need to define this so that the physical
+    /// targets are determined to be equivilent rather than just the handles
+    ///
+    template<TargetType K, typename V>
+    bool Target<K, V>::operator==(const Target& i_right) const
+    {
+        if (this->iv_handle.value == i_right->iv_handle.value)
+            return true;
+        else
+            return false;
+    }
+
+    ///
+    /// @brief Inquality Comparison Operator
+    /// @param[in] i_right Reference to Target to compare.
+    /// @return bool. True if not equal.
+    /// @note Platforms need to define this so that the physical
+    /// targets are determined to be equivilent rather than just the handles
+    ///
+    template<TargetType K, typename V>
+    bool Target<K, V>::operator!=(const Target& i_right) const
+    {
+        if (this->iv_handle.value != i_right->iv_handle.value)
+            return true;
+        else
+            return false;
+    }
+
+    ///
+    /// @brief Get this target's immediate parent
+    /// @tparam T The type of the parent
+    /// @return Target<T> a target representing the parent
+    ///
+    template<TargetType K, typename V>
+    template<TargetType T>
+    inline Target<T> Target<K, V>::getParent(void) const
+    {
+        return this->iv_handle.value;
+    }
+
+    ///
+    /// @brief Get this target's children
+    /// @tparam T The type of the parent
+    /// @param[in] i_state The desired TargetState of the children
+    /// @return std::vector<Target<T> > a vector of present/functional
+    /// children
+    /// @warning The children of EX's (cores) are expected to be returned
+    /// in order. That is, core 0 is std::vector[0].
+    ///
+    template<TargetType K, typename V>
+    template< TargetType T>
+    inline std::vector<Target<T> >
+    Target<K, V>::getChildren(const TargetState i_state) const
+    {
+#define INVALID_CHILD(PARENT, CHILD) \
+        static_assert(!((K == PARENT) && (T == CHILD)), \
+                  #CHILD " is not a child of " #PARENT );
+
+        // invalid children for proc
+//        INVALID_CHILD(fapi2::TARGET_TYPE_PROC_CHIP, fapi2::TARGET_TYPE_NONE)
+//        INVALID_CHILD(fapi2::TARGET_TYPE_PROC_CHIP, fapi2::TARGET_TYPE_SYSTEM)
+//        INVALID_CHILD(fapi2::TARGET_TYPE_PROC_CHIP, fapi2::TARGET_TYPE_DIMM)
+//        INVALID_CHILD(fapi2::TARGET_TYPE_PROC_CHIP, fapi2::TARGET_TYPE_PROC_CHIP)
+//        INVALID_CHILD(fapi2::TARGET_TYPE_PROC_CHIP, fapi2::TARGET_TYPE_MEMBUF_CHIP)
+//        INVALID_CHILD(fapi2::TARGET_TYPE_PROC_CHIP, fapi2::TARGET_TYPE_MBA)
+#undef INVALID_CHILD
+
+#define INVALID_PARENT(PARENT) \
+        static_assert(!((K == PARENT)), \
+                  #PARENT "is not supported on PPE platforms");
+
+        // invalid parents
+//         INVALID_PARENT(fapi2::TARGET_TYPE_SYSTEM)
+//         INVALID_PARENT(fapi2::TARGET_TYPE_MEMBUF_CHIP)
+//         INVALID_PARENT(fapi2::TARGET_TYPE_L4)
+//         INVALID_PARENT(fapi2::TARGET_TYPE_DIMM)
+//         INVALID_PARENT(fapi2::TARGET_TYPE_MCA)
+//         INVALID_PARENT(fapi2::TARGET_TYPE_MBA)
+//         INVALID_PARENT(fapi2::TARGET_TYPE_MI)
+//         INVALID_PARENT(fapi2::TARGET_TYPE_MCBIST)
+//         INVALID_PARENT(fapi2::TARGET_TYPE_DMI)
+#undef INVALID_PARENT
+
+        // valid children for EQ
+        // EQ -> CORE
+        // EQ -> EX
+        static_assert(!((K == fapi2::TARGET_TYPE_EQ) &&
+                        (T != fapi2::TARGET_TYPE_CORE) &&
+                        (T != fapi2::TARGET_TYPE_EX)),
+                      "improper child of fapi2::TARGET_TYPE_EQ");
+
+        // valid children for EX
+        // EX -> CORE
+        static_assert(!((K == fapi2::TARGET_TYPE_EX) &&
+                        (T != fapi2::TARGET_TYPE_CORE)),
+                      "improper child of fapi2::TARGET_TYPE_EX");
+
+        // Nimbus Memory
+        // valid children for MCS
+        // MCS -> MCA
+//         static_assert(!((K == fapi2::TARGET_TYPE_MCS) &&
+//                         (T != fapi2::TARGET_TYPE_MCA)),
+//                       "improper child of fapi2::TARGET_TYPE_MCS");
+
+
+        std::vector<fapi2::plat_target_handle_t>::iterator l_iter;
+        FAPI_DBG("getChildren: initializing children vector");
+        std::vector<Target<T> > l_children;
         
         
-#if 0
-        ///
-        /// @brief Get this target's immediate parent
-        /// @tparam T The type of the parent
-        /// @return Target<T> a target representing the parent
-        ///
-        template<TargetType T>
-        Target<T,V> getParent(void) const
-            {
-                static_assert((T & ~(TARGET_TYPE_PROC_CHIP | TARGET_TYPE_PERV) != 0),
-                "Only TARGET_TYPE_PROC_CHIP and TARGET_TYPE_PERV parent types supported"); 
-                
-                static_assert( ((((T & TARGET_TYPE_PROC_CHIP) == 0) &
-                                  (T & TARGET_TYPE_PERV     ) == 0)   ),
-                "Either TARGET_TYPE_PROC_CHIP or TARGET_TYPE_PERV parent type must be specified");                 
-            }
+       
+        uint32_t c = 0;
+        for (l_iter = G_vec_targets.begin(); l_iter != G_vec_targets.end(); ++l_iter)
+        {
 
-        ///
-        /// @brief Get this target's children
-        /// @tparam T The type of the parent
-        /// @return std::vector<Target<T> > a vector of present/functional
-        /// children
-        ///
-        template< TargetType T>
-        std::vector<Target<T,V> > getChildren(void) const
+            Target<T> * l_temp =  reinterpret_cast< Target<T>* >(l_iter);
+            if (((*l_temp).getTargetType() & T) == T)
             {
-                static_assert( ((T & ~TARGET_TYPE_PROC_CHIP) != 0 ) != true,
-                "Only TARGET_TYPE_CHIP and TARGET_TYPE_EQ child types supported");
-                 
-                if(K & TARGET_TYPE_PROC_CHIP)
+                switch (i_state)
                 {
-                    std::vector<Target<T,V> chip_children(CHIPLET_COUNT);
-                    for (int i = 0; i < CHIPLET_COUNT; i++)
-                    {
-                        if (this->iv_handle.fields.type == TARGET_TYPE_PROC_CHIP  & 
-                            this->iv_handle.fields.present = 1    &
-                            this->iv_handle.fields.functional = 1  )
-                        {                        
-                            chip_children.push_back(this->iv_handle)
+                    case TARGET_STATE_PRESENT:                
+                        if ((*l_temp).getPresent())
+                        {
+                            l_children.push_back((*l_temp));
+//                            FAPI_DBG("Pushing getChildren present 0x%08X", (uint32_t)(((*l_temp)).get()>>32));
+                        }
+                        break;
+                    case TARGET_STATE_FUNCTIONAL:
+                        if ((*l_temp).getFunctional())
+                        {
+                            l_children.push_back((*l_temp));
+//                            FAPI_DBG("Pushing getChildren functional 0x%08X", (uint32_t)(((*l_temp)).get()>>32));
                         }
-                    }
-                    return chip_children;
+                        break;
+                    default:
+                        FAPI_ERR("Coming error ASSERT for illegal i_state = %u", i_state);
                 }
-
-                if(K & TARGET_TYPE_PERV)
-                {
-                    this->iv_handle.fields.chiplet_num = Value;
-                    // this->iv_handle.fields.type_perv = 1;
-                    this->iv_handle.fields.type_target_num = 0;
-                }    
-
-           }
-
-        ///
-        /// @brief Get the target at the other end of a bus - dimm included
-        /// @tparam T The type of the parent
-        /// @return Target<T> a target representing the thing on the other end
-        /// @note Can be easily changed to a vector if needed
-        ///
-        template<TargetType T>
-        Target<T,K> getOtherEnd(void) const
-            {
-               static_assert( false, "getOtherEnd() is not supported on PPE platforms");
             }
-#endif
+            ++c;
+        }
 
-        ///
-        /// @brief Copy from a Target<O> to a Target<K>
-        /// @tparam O the target type of the other
-        ///
-        template<TargetType O>
-        Target<K,V>( const Target<O>& Other ):
-            Target<K,V>(Other.get())
-        {
-            static_assert( (K & O) != 0,
-                           "unable to cast Target, no shared types");
+        return l_children;
+    }
 
-            static_assert( bitCount<K>::count >= bitCount<O>::count,
-                           "unable to cast to specialized Target");
-        }
+    ///
+    /// @brief Get the target at the other end of a bus - dimm included
+    /// @tparam T The type of the parent
+    /// @param[in] i_state The desired TargetState of the children
+    /// @return Target<T> a target representing the thing on the other end
+    /// @note Can be easily changed to a vector if needed
+    ///
+    template<TargetType K, typename V>
+    template<TargetType T>
+    inline Target<T>
+    Target<K, V>::getOtherEnd(const TargetState i_state) const
+    {
+//        static_assert( false, "getOtherEnd() is not supported on PPE platforms");
+    }
 
-    private:
-
-//         union {
-//             V value;
-//             struct {
-// #ifdef _BIG_ENDIAN  
-//                 V chiplet_num       : 8;  
-//                 V _reserved_b24     : 24;        
-// #else       
-//                 V _reserved_b24     : 24;        
-//                 V chiplet_num       : 8;
-// #endif                     
-//             } fields;
-//             
-//         } iv_address;
-//         
-        union {
-            V value;
-            struct {
-#ifdef _BIG_ENDIAN  
-                V chiplet_num       : 8;  
-                V type_target_num   : 8;      
-                V type              : 8; 
-                V _reserved_b6      : 6; 
-                V present           : 1;
-                V functional        : 1;
-                V address_overlay   : 32;
-#else
-                V address_overlay   : 32;
-                V functional        : 1;
-                V present           : 1;
-                V _reserved_b6      : 6;
-                V type              : 8;      
-                V type_target_num   : 8;
-                V chiplet_num       : 8;
-#endif                     
-            } fields;
-        } iv_handle ;
-        
-//      uint64_t iv_present_children;
-//      uint64_t iv_functional_children;       
 
-    };
-    
+    ///
+    /// @brief Return the string interpretation of this target
+    /// @tparam T The type of the target
+    /// @param[in] i_target Target<T>
+    /// @param[in] i_buffer buffer to write in to
+    /// @param[in] i_bsize size of the buffer
+    /// @return void
+    /// @post The contents of the buffer is replaced with the string
+    /// representation of the target
+    ///
+    template< TargetType T >
+    inline void toString(const Target<T>& i_target, char* i_buffer, size_t i_bsize)
+    {
+        snprintf(i_buffer, i_bsize, "Target 0x%lx/0x%x", i_target.get(), T);
+    }
 
-#if 0
     ///
     /// @brief Return the string interpretation of this target
     /// @tparam T The type of the target
     /// @tparam B The type of the buffer
-    /// @param[in] The Target<T>
-    /// @param[in] The buffer
+    /// @param[in] A pointer to the Target<T>
+    /// @param[in] i_buffer buffer to write in to
+    /// @param[in] i_bsize size of the buffer
     /// @return void
     /// @post The contents of the buffer is replaced with the string
     /// representation of the target
     ///
-    template<TargetType T, typename B>
-    void toString(const Target<T>& i_target, B& i_buffer)
+    template< TargetType T >
+    inline void toString(const Target<T>* i_target, char* i_buffer, size_t i_bsize)
     {
-        static_assert( false, "toString is not supported on PPE platforms");
+        snprintf(i_buffer, i_bsize, "Target 0x%lx/0x%x", i_target->get(), T);
     }
 
     ///
     /// @brief Get an enumerated target of a specific type
     /// @tparam T The type of the target
-    /// @param[in] uint64_t representing the ordinal number of
+    /// @param[in] Ordinal representing the ordinal number of
     /// the desired target
     /// @return Target<T> the target requested
     ///
     template<TargetType T>
-    Target<T> getTarget(uint64_t Ordinal)
+    inline Target<T> getTarget(uint64_t Ordinal)
     {
         // For testing
         return Target<T>(Ordinal);
     }
-#endif
-    // Why has the been removed? For starters, the API name
-    // is probably wrong as it's already been confused with
-    // Target::getChildren(). And if I'm going to change it
-    // I really want to see if we need it. I'm still not
-    // clear on whether we're alloing this traversal or not.
-#if 0
-    ///
-    /// @brief Get the base target's children
-    /// @tparam T The type of the target
-    /// @return std::vector<Target<T> > a vector of present/functional
-    /// children
-    ///
-    template<TargetType T>
-    std::vector<Target<T> > getChildren()
-    {
-        // For testing
-        return {Target<T>(), Target<T>()};
-    }
-#endif
-
-    ///
-    /// @brief Check if the target is of a type, or in a type subset.
-    /// @tparam K the TargetType to check
-    /// @tparam T TargetType or TargetType composite to check against
-    /// @return True, iff K is a proper T
-    ///
-    template< TargetType K, TargetType T >
-    constexpr bool is_same(void)
-    { return (K & T) != 0; }
-        
-    
-
+}
 
-};
-//#include "plat_ppe_targets_hold.H"
 #endif
diff --git a/src/ppe/hwpf/plat/include/target_types.H b/src/ppe/hwpf/plat/include/target_types.H
index 11c48ed..05aff0e 100644
--- a/src/ppe/hwpf/plat/include/target_types.H
+++ b/src/ppe/hwpf/plat/include/target_types.H
@@ -36,6 +36,7 @@
 /// FAPI namespace
 namespace fapi2
 {
+
     ///
     /// @enum fapi::TargetType
     /// @brief Types, kinds, of targets
@@ -51,60 +52,45 @@ namespace fapi2
         TARGET_TYPE_EX                = 0x02, ///< Ex type
         TARGET_TYPE_CORE              = 0x04, ///< Core type
         TARGET_TYPE_EQ                = 0x08, ///< EQ type
-        TARGET_TYPE_PERV              = 0x10, ///< Pervasive type
-        TARGET_TYPE_EQ_MC_WRITE       = 0x20, ///< EQ Multicast Type
-        TARGET_TYPE_EQ_MC_READAND     = 0x21, ///< EQ Multicast Read AND Type
-        TARGET_TYPE_EQ_MC_READOR      = 0x22, ///< EQ Multicast Read OR Type
-        TARGET_TYPE_CORE_MC_WRITE     = 0x23, ///< Core Multicast Type
-        TARGET_TYPE_CORE_MC_READAND   = 0x24, ///< Core Multicast Read AND Type
-        TARGET_TYPE_CORE_MC_READOR    = 0x25, ///< Core Multicast Read OR Type
-        TARGET_TYPE_CME_CORE0         = 0x40, ///< CME Core0 (CME only)
-        TARGET_TYPE_CME_CORE1         = 0x41, ///< CME Core1 (CME only)
+        TARGET_TYPE_MCS               = 0x10, ///< MCS type
+        TARGET_TYPE_PERV              = 0x20, ///< Pervasive type
+        TARGET_TYPE_MCAST             = 0x80, ///< Multicast type
+
         TARGET_TYPE_ALL               = 0xFF, ///< Any/All types
-    
-    
-//         TARGET_TYPE_NONE              = 0x00000000, ///< No type
-//         TARGET_TYPE_SYSTEM            = 0x00000001, ///< System type
-//         TARGET_TYPE_DIMM              = 0x00000002, ///< DIMM type
-//         TARGET_TYPE_PROC_CHIP         = 0x00000004, ///< Processor type
-//         TARGET_TYPE_MEMBUF_CHIP       = 0x00000008, ///< Membuf type
-//         TARGET_TYPE_EX                = 0x00000010, ///< Ex type
-//         TARGET_TYPE_MBA               = 0x00000020, ///< MBA type
-//         TARGET_TYPE_MCS               = 0x00000040, ///< MCS type
-//         TARGET_TYPE_XBUS              = 0x00000080, ///< XBUS type
-//         TARGET_TYPE_ABUS              = 0x00000100, ///< ABUS type
-//         TARGET_TYPE_L4                = 0x00000200, ///< L4 type
-//         TARGET_TYPE_CORE              = 0x00000400, ///< Core type
-//         TARGET_TYPE_EQ                = 0x00000800, ///< EQ type
-//         TARGET_TYPE_MCA               = 0x00001000, ///< MCA type
-//         TARGET_TYPE_MCBIST            = 0x00002000, ///< MCBIST type
-//         TARGET_TYPE_MIA               = 0x00004000, ///< MIA type
-//         TARGET_TYPE_MIS               = 0x00008000, ///< MIS type
-//         TARGET_TYPE_DMI               = 0x00010000, ///< DMI type
-//         TARGET_TYPE_OBUS              = 0x00020000, ///< OBUS type
-//         TARGET_TYPE_NV                = 0x00040000, ///< NV bus type
-//         TARGET_TYPE_SBE               = 0x00080000, ///< SBE type
-//         TARGET_TYPE_PPE               = 0x00100000, ///< PPE type
-//         TARGET_TYPE_PERV              = 0x00200000, ///< Pervasive type
-//         TARGET_TYPE_PEC               = 0x00400000, ///< PEC type
-//         TARGET_TYPE_PHB               = 0x00800000, ///< PHB type     
-//         TARGET_TYPE_EQ_MC_WRITE       = 0x01000000, ///< EQ Multicast Type
-//         TARGET_TYPE_EQ_MC_READAND     = 0x02000000, ///< EQ Multicast Read AND Type
-//         TARGET_TYPE_EQ_MC_READOR      = 0x04000000, ///< EQ Multicast Read OR Type
-//         TARGET_TYPE_CORE_MC_WRITE     = 0x08000000, ///< Core Multicast Type
-//         TARGET_TYPE_CORE_MC_READAND   = 0x10000000, ///< Core Multicast Read AND Type
-//         TARGET_TYPE_CORE_MC_READOR    = 0x20000000, ///< Core Multicast Read OR Type
-//         TARGET_TYPE_CME_CORE0         = 0x40000000, ///< CME Core0 (CME only)
-//         TARGET_TYPE_CME_CORE1         = 0x80000000, ///< CME Core1 (CME only)
-//         TARGET_TYPE_ADDRESS           = 0xAAAAAAAA, ///< Address Overlay Type
-//         TARGET_TYPE_ALL               = 0xFFFFFFFF, ///< Any/All types
-    };
 
+        // The following are actually illegal targets on PPE platforms    
+//         TARGET_TYPE_SYSTEM            = 0xFE, ///< System type
+//         TARGET_TYPE_DIMM              = 0xFD, ///< DIMM type
+//         TARGET_TYPE_MEMBUF_CHIP       = 0xFC, ///< Membuf type
+//         TARGET_TYPE_MBA               = 0xFB, ///< MBA type
+//         TARGET_TYPE_XBUS              = 0xFA, ///< XBUS type
+//         TARGET_TYPE_ABUS              = 0xF9, ///< ABUS type
+//         TARGET_TYPE_L4                = 0xF8, ///< L4 type
+//         TARGET_TYPE_MCA               = 0xF7, ///< MCA type
+//         TARGET_TYPE_MCBIST            = 0xF6, ///< MCBIST type
+//         TARGET_TYPE_MIA               = 0xF5, ///< MIA type
+//         TARGET_TYPE_MIS               = 0xF4, ///< MIS type
+//         TARGET_TYPE_DMI               = 0xF3, ///< DMI type
+//         TARGET_TYPE_OBUS              = 0xF2, ///< OBUS type
+//         TARGET_TYPE_NV                = 0xF1, ///< NV bus type
+//         TARGET_TYPE_SBE               = 0xF0, ///< SBE type
+//         TARGET_TYPE_PPE               = 0xEF, ///< PPE type
+//         TARGET_TYPE_PEC               = 0xEE, ///< PEC type
+//         TARGET_TYPE_PHB               = 0xED, ///< PHB type  
+//         TARGET_TYPE_MI                = 0xEC, ///< MI type  
 
-     /**
-      * @brief Typedef used when passing multiple TargetType values
-      */
-     typedef uint8_t TargetTypes_t;
+        // Mappings to target types found in the error xml files
+        TARGET_TYPE_EX_CHIPLET    = TARGET_TYPE_EX,
+//        TARGET_TYPE_MBA_CHIPLET   = TARGET_TYPE_MBA,
+        TARGET_TYPE_MCS_CHIPLET   = TARGET_TYPE_MCS,
+//        TARGET_TYPE_XBUS_ENDPOINT = TARGET_TYPE_XBUS,
+//        TARGET_TYPE_ABUS_ENDPOINT = TARGET_TYPE_ABUS,
+    };
+    
+    ///
+    /// @brief Typedef used when passing multiple TargetType values
+    ///
+    typedef uint8_t TargetTypes_t;           
 
     /// @cond
     constexpr TargetType operator|(TargetType x, TargetType y)
diff --git a/src/ppe/hwpf/plat/include/utils.H b/src/ppe/hwpf/plat/include/utils.H
index 8fb74cb..c78466e 100644
--- a/src/ppe/hwpf/plat/include/utils.H
+++ b/src/ppe/hwpf/plat/include/utils.H
@@ -52,5 +52,30 @@
 /// Create a single bit mask at bit \a b
 #define BIT(b) BITS((b), 1)
 
+#ifdef _BIG_ENDIAN
+
+#define revle16(x) x
+#define revle32(x) x
+#define revle64(x) x
+
+#else
+
+uint16_t revle16(uint16_t i_x);
+uint32_t revle32(uint32_t i_x);
+uint64_t revle64(uint64_t i_x);
+
+#endif
+
+namespace fapi2
+{
+    /// @brief Delay this thread.
+    /// @param[in] i_nanoSeconds    nanoseconds to sleep
+    /// @param[in] i_simCycles      count of Awan cycles to advance
+    /// @return ReturnCode. Zero on success, else platform specified error.
+    inline ReturnCode delay(uint64_t i_nanoSeconds, uint64_t i_simCycles)
+    {
+        return FAPI2_RC_SUCCESS;
+    }
+}
 
 #endif // FAPI2_UTILS_H_
diff --git a/src/ppe/hwpf/plat/src/fapi2ppefiles.mk b/src/ppe/hwpf/plat/src/fapi2ppefiles.mk
index 3adeec6..8fcacd9 100644
--- a/src/ppe/hwpf/plat/src/fapi2ppefiles.mk
+++ b/src/ppe/hwpf/plat/src/fapi2ppefiles.mk
@@ -42,10 +42,13 @@
 ##########################################################################
 
 
-FAPI2-C-SOURCES +=  fapi2PlatAttributeService.C \
-                    plat_utils.C
+FAPI2-CPP-SOURCES +=  fapi2PlatAttributeService.C
+FAPI2-CPP-SOURCES +=  target.C
+FAPI2-CPP-SOURCES +=  plat_utils.C
+
 
 FAPI2-S-SOURCES =
 
-FAPI2LIB_OBJECTS += $(FAPI2-C-SOURCES:.C=.o) $(FAPI2-S-SOURCES:.S=.o)
+FAPI2LIB_OBJECTS += $(FAPI2-CPP-SOURCES:.C=.o) 
+FAPI2LIB_OBJECTS += $(FAPI2-S-SOURCES:.S=.o)
 
diff --git a/src/ppe/hwpf/plat/src/plat_utils.C b/src/ppe/hwpf/plat/src/plat_utils.C
index 2b6773a..3d79c21 100644
--- a/src/ppe/hwpf/plat/src/plat_utils.C
+++ b/src/ppe/hwpf/plat/src/plat_utils.C
@@ -22,6 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+
 /**
  *  @file plat_utils.C
  *  @brief Implements fapi2 common utilities
@@ -30,6 +31,8 @@
 #include <stdint.h>
 #include <plat_trace.H>
 #include <return_code.H>
+
+#ifndef __PPE__
 #include <error_info.H>
 
 namespace fapi2
@@ -76,7 +79,7 @@ namespace fapi2
                      (*i)->iv_procedure, (*i)->iv_calloutPriority);
         }
 
-        FAPI_DBG("busCallouts: %lu", ei->iv_busCallouts.size());
+e         FAPI_DBG("busCallouts: %lu", ei->iv_busCallouts.size());
         for( auto i = ei->iv_busCallouts.begin(); i != ei->iv_busCallouts.end();
              ++i )
         {
@@ -135,3 +138,77 @@ namespace fapi2
         return FAPI2_RC_SUCCESS;
     }
 };
+
+
+/// Byte-reverse a 16-bit integer if on a little-endian machine
+
+uint16_t
+revle16(uint16_t i_x)
+{
+    uint16_t rx;
+
+#ifndef _BIG_ENDIAN
+    uint8_t *pix = (uint8_t*)(&i_x);
+    uint8_t *prx = (uint8_t*)(&rx);
+
+    prx[0] = pix[1];
+    prx[1] = pix[0];
+#else
+    rx = i_x;
+#endif
+
+    return rx;
+}
+
+#endif
+
+/// Byte-reverse a 32-bit integer if on a little-endian machine
+
+uint32_t
+revle32(uint32_t i_x)
+{
+    uint32_t rx;
+
+#ifndef _BIG_ENDIAN
+    uint8_t *pix = (uint8_t*)(&i_x);
+    uint8_t *prx = (uint8_t*)(&rx);
+
+    prx[0] = pix[3];
+    prx[1] = pix[2];
+    prx[2] = pix[1];
+    prx[3] = pix[0];
+#else
+    rx = i_x;
+#endif
+
+    return rx;
+}
+
+
+/// Byte-reverse a 64-bit integer if on a little-endian machine
+
+uint64_t
+revle64(const uint64_t i_x)
+{
+    uint64_t rx;
+
+#ifndef _BIG_ENDIAN
+    uint8_t *pix = (uint8_t*)(&i_x);
+    uint8_t *prx = (uint8_t*)(&rx);
+
+    prx[0] = pix[7];
+    prx[1] = pix[6];
+    prx[2] = pix[5];
+    prx[3] = pix[4];
+    prx[4] = pix[3];
+    prx[5] = pix[2];
+    prx[6] = pix[1];
+    prx[7] = pix[0];
+#else
+    rx = i_x;
+#endif
+
+    return rx;
+}
+
+
diff --git a/src/ppe/hwpf/plat/src/target.C b/src/ppe/hwpf/plat/src/target.C
index 2439a3f..37b5d14 100644
--- a/src/ppe/hwpf/plat/src/target.C
+++ b/src/ppe/hwpf/plat/src/target.C
@@ -24,12 +24,150 @@
 /* IBM_PROLOG_END_TAG                                                     */
 
 #include <target.H>
+#include <new>
+#include <utility> // For move
+// Global Vector containing ALL targets.  This structure is referenced by
+// fapi2::getChildren to produce the resultant returned vector from that
+// call.
+std::vector<fapi2::plat_target_handle_t> G_vec_targets;
 
 namespace fapi2
 {
-    std::vector Target::getChildren(void) const     
 
-};
+    #ifndef __noRC__
+    ReturnCode current_err;
+    #endif
+
+    /// @brief Function to initialize the G_targets vector based on partial good
+    ///      attributes ///  this will move to plat_target.H formally
+    fapi2::ReturnCode plat_TargetsInit()
+    {
+
+        // This is workaround. Currently we do not have code to initialise
+        // global objects. So initializing global objects against using local
+        // initialized object
+        std::vector<fapi2::plat_target_handle_t> targets1;
+        G_vec_targets = std::move(targets1);
+        std::vector<fapi2::plat_target_handle_t>::iterator tgt_iter;
+        uint32_t l_beginning_offset;
+
+        FAPI_DBG("Platform target initialization.  Target Count = %u", TARGET_COUNT);
+        // Initialize all entries to NULL
+        for (uint32_t i = 0; i < TARGET_COUNT; ++i)
+        {
+            G_vec_targets.push_back((fapi2::plat_target_handle_t)0x0);
+            FAPI_DBG("Nulling G_vec_targets[%u] hi value=0x%08X",
+                        i, (uint32_t)(G_vec_targets.at(i)>>32));
+    //        FAPI_DBG("Nulling G_vec_targets[%u] lo value=0x%08X",
+    //                    i, (uint32_t)(G_vec_targets.at(i)&0x00000000ffffffffull));
+        }
+         FAPI_DBG("Vector size: %u", G_vec_targets.size());
+
+        // Chip Target is the first one
+        FAPI_DBG("Chip Target info: CHIP_TARGET_OFFSET %u CHIP_TARGET_COUNT %u ",
+                      CHIP_TARGET_OFFSET,CHIP_TARGET_COUNT);
+
+
+        l_beginning_offset = CHIP_TARGET_OFFSET;
+        FAPI_DBG("Chip beginning offset =%u", l_beginning_offset);
+        for (uint32_t i = 0; i < CHIP_TARGET_COUNT; ++i)
+        {
+            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> target_name((fapi2::plat_target_handle_t)i);
+            G_vec_targets.at(l_beginning_offset+i) = revle64((fapi2::plat_target_handle_t)(target_name.get()));
+    //         FAPI_DBG("Chip Target initialization: %u G_vec_targets[%u] value=0x%08X",
+    //                     i,
+    //                    (l_beginning_offset+i),
+    //                    (uint32_t)(G_vec_targets.at(l_beginning_offset+i)>>32));
+        }
+
+        // Chip Level Pervasive Targets
+        FAPI_DBG("Pervasive Target info: PERV_TARGET_OFFSET %u PERV_TARGET_COUNT %u",
+                      PERV_TARGET_OFFSET, PERV_TARGET_COUNT);
+
+        l_beginning_offset = PERV_TARGET_OFFSET;
+        FAPI_DBG("Perv beginning offset =%u", l_beginning_offset);
+        for (uint32_t i = 0; i < PERV_TARGET_COUNT; ++i)
+        {
+            fapi2::Target<fapi2::TARGET_TYPE_PERV> target_name((fapi2::plat_target_handle_t)i);
+            FAPI_DBG("target_name hi word = 0x%08X", (uint32_t)(target_name.get()>>32));
+
+            G_vec_targets.at(l_beginning_offset+i) = revle64((fapi2::plat_target_handle_t)(target_name.get()));
+    //         FAPI_DBG("Pervasive Target initialization: %u G_vec_targets[%u] value=0x%08X",
+    //                     i,
+    //                    (l_beginning_offset+i),
+    //                    (uint32_t)(G_vec_targets.at(l_beginning_offset+i)>>32));
+        }
 
+        // Cache (EQ) Targets
+        FAPI_DBG("EQ Target info: EQ_TARGET_OFFSET %u EQ_TARGET_COUNT %u",
+                      EQ_TARGET_OFFSET,  EQ_TARGET_COUNT);
+        l_beginning_offset = EQ_TARGET_OFFSET;
+        FAPI_DBG("EQ beginning offset =%u", l_beginning_offset);
+        for (uint32_t i = 0; i < EQ_TARGET_COUNT; ++i)
+        {
+            fapi2::Target<fapi2::TARGET_TYPE_EQ> target_name((fapi2::plat_target_handle_t)i);
+            FAPI_DBG("target_name hi word = 0x%08X", (uint32_t)(target_name.get()>>32));
+            G_vec_targets.at(l_beginning_offset+i) = revle64((fapi2::plat_target_handle_t)(target_name.get()));
+    //         FAPI_DBG("EQ Target initialization: %u G_vec_targets[%u] value=%16llX",
+    //                      i,
+    //                    (l_beginning_offset+i),
+    //                    revle64((uint64_t)G_vec_targets[l_beginning_offset+i]));
+        }
 
+        // Core (EC) Targets
+        FAPI_DBG("Core Target info: CORE_TARGET_OFFSET %u CORE_TARGET_COUNT %u",
+                      CORE_TARGET_OFFSET, CORE_TARGET_COUNT);
+
+        l_beginning_offset = CORE_TARGET_OFFSET;
+        FAPI_DBG("Core beginning offset =%u", l_beginning_offset);
+        for (uint32_t i = 0; i < CORE_TARGET_COUNT; ++i)
+        {
+            fapi2::Target<fapi2::TARGET_TYPE_CORE> target_name((fapi2::plat_target_handle_t)i);
+            FAPI_DBG("target_name hi word = 0x%08X", (uint32_t)(target_name.get()>>32));
+            G_vec_targets.at(l_beginning_offset+i) = revle64((fapi2::plat_target_handle_t)(target_name.get()));
+    //         FAPI_DBG("Core Target initialization: %u G_vec_targets[%u] value=0x%08X",
+    //                     i,
+    //                    (l_beginning_offset+i),
+    //                    (uint32_t)(G_vec_targets.at(l_beginning_offset+i)>>32));
+        }
+
+        // Memroy Controller Synchronous (MCS) Targets
+        FAPI_DBG("MCS Target info: MCS_TARGET_OFFSET %u MCS_TARGET_COUNT %u",
+                      MCS_TARGET_OFFSET, MCS_TARGET_COUNT);
+
+        l_beginning_offset = MCS_TARGET_OFFSET;
+        FAPI_DBG("MCS beginning offset =%u", l_beginning_offset);
+        for (uint32_t i = 0; i < MCS_TARGET_COUNT; ++i)
+        {
+            fapi2::Target<fapi2::TARGET_TYPE_MCS> target_name((fapi2::plat_target_handle_t)i);
+            FAPI_DBG("target_name hi word = 0x%08X", (uint32_t)(target_name.get()>>32));
+            G_vec_targets.at(l_beginning_offset+i) = revle64((fapi2::plat_target_handle_t)(target_name.get()));
+    //         FAPI_DBG("MCS Target initialization: %u G_vec_targets[%u] value=0x%08X",
+    //                     i,
+    //                    (l_beginning_offset+i),
+    //                    (uint32_t)(G_vec_targets.at(l_beginning_offset+i)>>32));
+        }
+
+        // Trace all entries
+        uint32_t c = 0;
+        for (tgt_iter = G_vec_targets.begin(); tgt_iter != G_vec_targets.end(); ++tgt_iter)
+        {
+            FAPI_DBG("Trace hi word G_vec_targets[%u] value=%08X",
+                       c, (uint32_t)((*tgt_iter)>>32));
+            ++c;
+        }
+
+        return fapi2::current_err;
+    }
+
+    /// @brief Function to initialize the G_targets vector based on partial good
+    ///        attributes
+    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> plat_getChipTarget()
+    {
+
+        // Get the chip specific target
+        return ((fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>)G_vec_targets.at(0));
+    }   
+
+};
 
diff --git a/src/ppe/importtemp/common/include/const_common.H b/src/ppe/importtemp/common/include/const_common.H
new file mode 100644
index 0000000..21ae5fc
--- /dev/null
+++ b/src/ppe/importtemp/common/include/const_common.H
@@ -0,0 +1,110 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/common/include/const_common.H $            */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+
+/*! \brief These are macros used for the scom_addresses.H
+ *
+ *  Provides macro defintions for defining scom constants
+ *  for assembly and C
+ *
+ */
+
+// - HWP metadata
+
+///
+/// @file const_common.H
+/// @brief These are macros used for the scom_addresses.H
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: ? <?>
+// *HWP Team: SoA
+// *HWP Level: 1
+// *HWP Consumed by: XX:XX
+
+
+#ifndef __CONST_COMMON_H
+#define __CONST_COMMON_H
+
+#if defined __ASSEMBLER__
+
+//This probably won't work :(
+//  Not sure you can do .set for the same name.
+//  If so, it probably takes the last one, which would be the incorrect one
+//#define FIXREG8(name, expr, unit, meth, newexpr) .set name, (newexpr)
+//#define FIXREG32(name, expr, unit, meth, newexpr) .set name, (newexpr)
+//#define FIXREG64(name, expr, unit, meth, newexpr) .set name, (newexpr)
+//
+//#define CONST_UINT8_T(name, expr, unit, meth) .set name, (expr)
+//#define CONST_UINT32_T(name, expr, unit, meth) .set name, (expr)
+//#define CONST_UINT64_T(name, expr, unit, meth) .set name, (expr)
+
+#define RULL(x) x
+
+#elif defined __cplusplus
+
+#include <stdint.h>
+
+template <typename T, uint64_t UNIT, uint64_t METH, T REG >
+struct has_fixup
+{
+    static const T value = T(0);
+};
+
+template <typename T, uint64_t UNIT, uint64_t METH, T REG, uint64_t FLD >
+struct has_fixfld
+{
+    static const uint8_t value = 255;
+};
+
+
+#define FIXREG8(name, expr, unit, meth, newexpr) template<> struct has_fixup<uint8_t,unit,meth,expr> { static const uint8_t value = newexpr; };
+#define FIXREG32(name, expr, unit, meth, newexpr) template<> struct has_fixup<uint32_t,unit,meth,expr> { static const uint32_t value = newexpr; };
+#define FIXREG64(name, expr, unit, meth, newexpr) template<> struct has_fixup<uint64_t,unit,meth,expr> { static const uint64_t value = newexpr; };
+
+#define REG8(name, expr, unit, meth) static const uint8_t name = has_fixup<uint8_t,unit,meth,expr>::value ? has_fixup<uint8_t,unit,meth,expr>::value : expr;
+#define REG32(name, expr, unit, meth) static const uint32_t name = has_fixup<uint32_t,unit,meth,expr>::value ? has_fixup<uint32_t,unit,meth,expr>::value : expr;
+#define REG64(name, expr, unit, meth) static const uint64_t name = has_fixup<uint64_t,unit,meth,expr>::value ? has_fixup<uint64_t,unit,meth,expr>::value : expr;
+
+#define FIXREG8_FLD(name, expr, unit, meth, fld, newexpr) template<> struct has_fixfld<uint8_t,unit,meth,expr,fld> { static const uint8_t value = newexpr; };
+#define FIXREG32_FLD(name, expr, unit, meth, fld, newexpr) template<> struct has_fixfld<uint32_t,unit,meth,expr,fld> { static const uint32_t value = newexpr; };
+#define FIXREG64_FLD(name, expr, unit, meth, fld, newexpr) template<> struct has_fixfld<uint64_t,unit,meth,expr,fld> { static const uint64_t value = newexpr; };
+
+#define REG8_FLD(name, expr, unit, meth, fld) static const uint8_t name = has_fixfld<uint8_t,unit,meth,expr,fld>::value != 255 ? has_fixfld<uint8_t,unit,meth,expr,fld>::value : expr;
+#define REG32_FLD(name, expr, unit, meth, fld) static const uint8_t name = has_fixfld<uint32_t,unit,meth,expr,fld>::value != 255 ? has_fixfld<uint32_t,unit,meth,expr,fld>::value : expr;
+#define REG64_FLD(name, expr, unit, meth, fld) static const uint8_t name = has_fixfld<uint64_t,unit,meth,expr,fld>::value != 255 ? has_fixfld<uint64_t,unit,meth,expr,fld>::value : expr;
+
+#define RULL(x) x##ull
+
+#else // C code
+
+// CONST_UINT[8,3,64]_T() can't be used in C code/headers; Use
+//
+//     #define <symbol> <value> [ or ULL(<value>) for 64-bit constants
+
+#define RULL(x) x##ull
+
+#endif  // __ASSEMBLER__
+
+#endif  // __CONST_COMMON_H
diff --git a/src/ppe/importtemp/common/include/misc_scom_addresses.H b/src/ppe/importtemp/common/include/misc_scom_addresses.H
new file mode 100644
index 0000000..fec1871
--- /dev/null
+++ b/src/ppe/importtemp/common/include/misc_scom_addresses.H
@@ -0,0 +1,10259 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/common/include/misc_scom_addresses.H $     */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file misc_scom_addresses.H
+/// @brief  Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+/*---------------------------------------------------------------
+ *
+ *---------------------------------------------------------------
+ *
+ *  Issues:
+ *    MC regs with same address.        HW323435 (matteo)
+ *         Duplicate IOM registers.          HW320456 (designers)
+ *    OSC/perv regs same address.       HW323437
+ *    TOD reg same address.             HW323439
+ *    PHB registers need fixed.         HW320416  ( all regs commented out now )
+ *    IO0 registers need fixed.         HW320437
+ *
+ * Closed
+ *    PB.PB_PPE registers need fixed.   HW320435
+ *    EX05 registers need fixed.        HW320427  (9020) - L2 ring id's are incorrect
+ *    IOFPPE registers need fixed.      HW320424  (9020) - Investigate NULL scope
+ *    PEC addresses are wrong.          HW322598  (9020)
+ *    MC registers need fixed.          HW320433
+ *    VA.VA_NORTH registers need fixed. HW320436
+ *
+ * Format:
+ *
+ *  <UNIT>_<SUBUNIT>_<INSTANCE>_<REGISTER>_<ACCESS/TYPE>
+ *
+ *  Notes: Subunits are only added to make names unique when
+ *  there are name collisions.
+ *  Only units with more than one instance has instance numbers.
+ *  If there is only one, the instance number is omitted.
+ *
+ *  Instance numbers are chiplet id's for the PERV unit.  The
+ *  chiplet id's are mapped to their name and used instead of
+ *  instance numbers.  See bellow.
+ *
+ *  For registers with a single access type the type and access
+ *  methods are omitted.
+ *
+ *  For access types where all bits have the same access methods, the
+ *  access method is appended to the name.  If the access methods
+ *  are different for some bits, the access type is appended to the
+ *  name _SCOM instead of _RO.  The _RW(X) access method is omitted
+ *  and assumed to be default.
+ *
+ *  Valid units / subunits
+ *    PU                    : No unit chip level
+ *        MCD0[0..1]        : mcd subunit
+ *        PIB2OPB[0..1]     : PIB2OPB subunit
+ *        OTPROM[0..1]      : otprom subunit
+ *        NPU               : common npu subunit
+ *        NPU[0..2]         : Npu stacks 0 to 2
+ *          CTL             : Npu CTL subunit
+ *          DAT             : Npu DAT subunit
+ *          SM[0..3]        : Npu SM subunits
+ *          NTL[0..1]       : Npu NTL subunit
+ *    PERV                  : Pervasive
+ *        FSI2PIB           : subunit
+ *        FSISHIFT          : subunit
+ *        FSII2C            : subunit
+ *        FSB               : subunit
+ *    EX                    : Ex unit (1/2 quad, 2 cores)
+ *        L2                : L2 subunit
+ *        L3                : L3 subunit
+ *    PEC                   : PCI Pec unit
+ *        STACK0            : subunit
+ *        STACK1            : subunit
+ *        STACK2            : subunit
+ *    C                     : core
+ *    EQ                    : quad
+ *    OBUS                  : obus
+ *    CAPP                  : capp
+ *    MCBIST                : mcbist
+ *    MCA                   : mca
+ *    NVBUS                 : (not implemented yet)
+ *    PHB                   : (not implemented yet)
+ *    MI                    : (not implemented yet)
+ *    DMI                   : (not implemented yet)
+ *    MCS                   : (not implemented yet)
+ *    OCC                   : (not implemented yet)
+ *    PPE                   : (not implemented yet)
+ *    SBE                   : (not implemented yet)
+ *    XBUS                  : (not implemented yet)
+ *
+ * Pervasive instance names follow chiplet id.
+ *
+ * Instance/  | Chiplet
+ * Chiplet    | name
+ * -----------+-----------
+ * 0x00       | PIB
+ * 0x01       | TP
+ * 0x02       | N0
+ * 0x03       | N1
+ * 0x04       | N2
+ * 0x05       | N3
+ * 0x06       | XB
+ * 0x07       | MC01
+ * 0x08       | MC23
+ * 0x09       | OB0
+ * 0x0A       | OB1
+ * 0x0B       | OB2
+ * 0x0C       | OB3
+ * 0x0D       | PCI0
+ * 0x0E       | PCI1
+ * 0x0F       | PCI2
+ * 0x10       | EP00
+ * 0x11       | EP01
+ * 0x12       | EP02
+ * 0x13       | EP03
+ * 0x14       | EP04
+ * 0x15       | EP05
+ * 0x20       | EC00
+ * 0x21       | EC01
+ * 0x22       | EC02
+ * 0x23       | EC03
+ * 0x24       | EC04
+ * 0x25       | EC05
+ * 0x26       | EC06
+ * 0x27       | EC07
+ * 0x28       | EC08
+ * 0x29       | EC09
+ * 0x2A       | EC10
+ * 0x2B       | EC11
+ * 0x2C       | EC12
+ * 0x2D       | EC13
+ * 0x2E       | EC14
+ * 0x2F       | EC15
+ * 0x30       | EC16
+ * 0x31       | EC17
+ * 0x32       | EC18
+ * 0x33       | EC19
+ * 0x34       | EC20
+ * 0x35       | EC21
+ * 0x36       | EC22
+ * 0x37       | EC23
+ *
+ *
+ *---------------------------------------------------------------
+ *
+ * NOTES:
+ *
+ * there is a SPR ring that goes around the chip with an
+ * address(0:9)/tid(0:1) (thread id)/mfspr_data(0:63) and return mfspr_data_v/mfspr_data(0:63)
+ *
+ *    Add PU_<SUBUNITS>  (only if there are conflicts on these registers)
+ *       0x0001XXXX OTPROM
+ *       0x0002XXXX FSIM0
+ *       0x0003XXXX FSIM1
+ *       0x0004XXXX TOD
+ *       0x0005XXXX FSI_MBOX
+ *       0x0006XXXX OCI_BRIDGE
+ *       0x0007XXXX SPI_ADC
+ *       0x0008XXXX PIBMEM
+ *       0x0009XXXX ADU
+ *       0x000AXXXX I2CM
+ *       0x000BXXXX SBE_FIFO
+ *       0x000DXXXX PSU
+ *       0x000EXXXX SBE
+ *
+ * 0x0000100A for FSI2PIB  => PERV_FSI2PIB
+ * 0x00000Cxx for FSISHIFT =>  PERV_FSISHIFT
+ * 0x000018xx for FSI I2C =>  PERV_FSII2C
+ * 0x000024xx for FSI SBEFIFO => PERV_FSB
+ *
+ * 0x00000400 PEEK_TABLE
+ * 0x00000800 FSI_SLAVE
+ * 0x00000C00 FSI_SHIFT
+ * 0x00001000 FSI2PIB
+ * 0x00001400 FSI_SCRATCHPAD
+ * 0x00001800 FSI_I2CM
+ * 0x00002400 FSI_SBE_FIFO
+ *
+ * address fields
+ * 0xCCRPxxxx
+ *
+ * CC=chiplet
+ * R=always 0?
+ * P=port
+ *   0=gpregs
+ *   1=normal unit scom ring (exclude)
+ *   3=clock controller
+ *   4=firs
+ *   5=cpm
+ *
+ * =============================================================================
+ * Compiling
+ *
+ * Precompile the header to save time on subsquent compiles:
+ * g++ -I. -c scom_addresses.H
+ *
+ * Use these options to help reduce the binary size
+ * g++ -I. -Os -fdata-sections -ffunction-sections <file>.C -o <output> -Wl,--gc-sections
+ *
+ *
+ *---------------------------------------------------------------
+ */
+
+#include <const_common.H>
+
+
+#ifndef __MISC_SCOM_ADDRESSES_H
+#define __MISC_SCOM_ADDRESSES_H
+
+
+#include <scom_template_consts.H>
+#include <misc_scom_addresses_fixes.H>
+
+
+REG64( PU_ADDR_0_HASH_FUNCTION_REG                             ,
+       RULL(0x02011141), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADDR_10_HASH_FUNCTION_REG                            ,
+       RULL(0x0201114B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADDR_1_HASH_FUNCTION_REG                             ,
+       RULL(0x02011142), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADDR_2_HASH_FUNCTION_REG                             ,
+       RULL(0x02011143), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADDR_3_HASH_FUNCTION_REG                             ,
+       RULL(0x02011144), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADDR_4_HASH_FUNCTION_REG                             ,
+       RULL(0x02011145), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADDR_5_HASH_FUNCTION_REG                             ,
+       RULL(0x02011146), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADDR_6_HASH_FUNCTION_REG                             ,
+       RULL(0x02011147), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADDR_7_HASH_FUNCTION_REG                             ,
+       RULL(0x02011148), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADDR_8_HASH_FUNCTION_REG                             ,
+       RULL(0x02011149), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADDR_9_HASH_FUNCTION_REG                             ,
+       RULL(0x0201114A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADS_XSCOM_CMD_REG                                    ,
+       RULL(0x0502281C), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_ADU_HANG_DIV_REG                                     ,
+       RULL(0x05022850), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ALTD_ADDR_REG                                        ,
+       RULL(0x05022800), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_ALTD_CMD_REG                                         ,
+       RULL(0x05022801), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_ALTD_DATA_REG                                        ,
+       RULL(0x05022804), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ALTD_OPTION_REG                                      ,
+       RULL(0x05022802), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_ALTD_STATUS_REG                                      ,
+       RULL(0x05022803), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM0_ATS_CKSW                                     ,
+       RULL(0x05011305), SH_UNT_PU_NPU_SM0, SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM1_ATS_CTRL                                     ,
+       RULL(0x05011325), SH_UNT_PU_NPU_SM1, SH_ACS_SCOM      );
+
+REG64( PU_BANK0_MCD_BOT                                        ,
+       RULL(0x0301140C), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_MCD1_BANK0_MCD_BOT                                   ,
+       RULL(0x0301100C), SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_BANK0_MCD_CHA                                        ,
+       RULL(0x0301140D), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_MCD1_BANK0_MCD_CHA                                   ,
+       RULL(0x0301100D), SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_BANK0_MCD_CMD                                        ,
+       RULL(0x0301140E), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_MCD1_BANK0_MCD_CMD                                   ,
+       RULL(0x0301100E), SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_BANK0_MCD_REC                                        ,
+       RULL(0x03011410), SH_UNT          , SH_ACS_SCOM      );
+REG64( PU_MCD1_BANK0_MCD_REC                                   ,
+       RULL(0x03011010), SH_UNT_PU_MCD1  , SH_ACS_SCOM      );
+
+REG64( PU_BANK0_MCD_RW                                         ,
+       RULL(0x0301140F), SH_UNT          , SH_ACS_SCOM      );
+REG64( PU_MCD1_BANK0_MCD_RW                                    ,
+       RULL(0x0301100F), SH_UNT_PU_MCD1  , SH_ACS_SCOM      );
+
+REG64( PU_BANK0_MCD_STR                                        ,
+       RULL(0x0301140B), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_MCD1_BANK0_MCD_STR                                   ,
+       RULL(0x0301100B), SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_BANK0_MCD_TOP                                        ,
+       RULL(0x0301140A), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_MCD1_BANK0_MCD_TOP                                   ,
+       RULL(0x0301100A), SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_BANK0_MCD_VGC                                        ,
+       RULL(0x03011411), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_MCD1_BANK0_MCD_VGC                                   ,
+       RULL(0x03011011), SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW   );
+
+REG64( PEC_0_STACK0_BARE_REG                                   ,
+       RULL(0x04010C55), SH_UNT_PEC_0_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK1_BARE_REG                                   ,
+       RULL(0x04010C95), SH_UNT_PEC_0_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK2_BARE_REG                                   ,
+       RULL(0x04010CD5), SH_UNT_PEC_0_STACK2, SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK0_BARE_REG                                   ,
+       RULL(0x04011055), SH_UNT_PEC_1_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK1_BARE_REG                                   ,
+       RULL(0x04011095), SH_UNT_PEC_1_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK2_BARE_REG                                   ,
+       RULL(0x040110D5), SH_UNT_PEC_1_STACK2, SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK0_BARE_REG                                   ,
+       RULL(0x04011455), SH_UNT_PEC_2_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK1_BARE_REG                                   ,
+       RULL(0x04011495), SH_UNT_PEC_2_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK2_BARE_REG                                   ,
+       RULL(0x040114D5), SH_UNT_PEC_2_STACK2, SH_ACS_SCOM_RW   );
+REG64( PEC_STACK0_BARE_REG                                     ,
+       RULL(0x04010C55), SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_STACK1_BARE_REG                                     ,
+       RULL(0x04010C95), SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_STACK2_BARE_REG                                     ,
+       RULL(0x04010CD5), SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW   );
+
+REG64( PU_BCDE_CTL_OCI                                         ,
+       RULL(0x40020080), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_BCDE_CTL_SCOM                                        ,
+       RULL(0x05016850), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_BCDE_OCIBAR_OCI                                      ,
+       RULL(0x400200A0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_BCDE_OCIBAR_SCOM                                     ,
+       RULL(0x05016854), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_BCDE_PBADR_OCI                                       ,
+       RULL(0x40020098), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_BCDE_PBADR_SCOM                                      ,
+       RULL(0x05016853), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_BCDE_SET_OCI                                         ,
+       RULL(0x40020088), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_BCDE_SET_SCOM                                        ,
+       RULL(0x05016851), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_BCDE_STAT_OCI                                        ,
+       RULL(0x40020090), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_BCDE_STAT_SCOM                                       ,
+       RULL(0x05016852), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_BCUE_CTL_OCI                                         ,
+       RULL(0x400200A8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_BCUE_CTL_SCOM                                        ,
+       RULL(0x05016855), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_BCUE_OCIBAR_OCI                                      ,
+       RULL(0x400200C8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_BCUE_OCIBAR_SCOM                                     ,
+       RULL(0x05016859), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_BCUE_PBADR_OCI                                       ,
+       RULL(0x400200C0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_BCUE_PBADR_SCOM                                      ,
+       RULL(0x05016858), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_BCUE_SET_OCI                                         ,
+       RULL(0x400200B0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_BCUE_SET_SCOM                                        ,
+       RULL(0x05016856), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_BCUE_STAT_OCI                                        ,
+       RULL(0x400200B8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_BCUE_STAT_SCOM                                       ,
+       RULL(0x05016857), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_NPU0_CTL_BDF2PE_00_CONFIG                            ,
+       RULL(0x0501108A), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_BDF2PE_00_CONFIG                            ,
+       RULL(0x0501118A), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_BDF2PE_00_CONFIG                            ,
+       RULL(0x0501128A), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_BDF2PE_01_CONFIG                            ,
+       RULL(0x0501108B), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_BDF2PE_01_CONFIG                            ,
+       RULL(0x0501118B), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_BDF2PE_01_CONFIG                            ,
+       RULL(0x0501128B), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_BDF2PE_02_CONFIG                            ,
+       RULL(0x0501108C), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_BDF2PE_02_CONFIG                            ,
+       RULL(0x0501118C), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_BDF2PE_02_CONFIG                            ,
+       RULL(0x0501128C), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_BDF2PE_10_CONFIG                            ,
+       RULL(0x0501108D), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_BDF2PE_10_CONFIG                            ,
+       RULL(0x0501118D), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_BDF2PE_10_CONFIG                            ,
+       RULL(0x0501128D), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_BDF2PE_11_CONFIG                            ,
+       RULL(0x0501108E), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_BDF2PE_11_CONFIG                            ,
+       RULL(0x0501118E), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_BDF2PE_11_CONFIG                            ,
+       RULL(0x0501128E), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_BDF2PE_12_CONFIG                            ,
+       RULL(0x0501108F), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_BDF2PE_12_CONFIG                            ,
+       RULL(0x0501118F), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_BDF2PE_12_CONFIG                            ,
+       RULL(0x0501128F), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CERR_ECC_HOLD                                   ,
+       RULL(0x050110A4), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_CERR_ECC_HOLD                                   ,
+       RULL(0x050111A4), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_CERR_ECC_HOLD                                   ,
+       RULL(0x050112A4), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CERR_ECC_MASK                                   ,
+       RULL(0x050110A5), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_CERR_ECC_MASK                                   ,
+       RULL(0x050111A5), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_CERR_ECC_MASK                                   ,
+       RULL(0x050112A5), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CERR_LOG_HOLD                                   ,
+       RULL(0x050110A8), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_CERR_LOG_HOLD                                   ,
+       RULL(0x050111A8), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_CERR_LOG_HOLD                                   ,
+       RULL(0x050112A8), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CERR_LOG_MASK                                   ,
+       RULL(0x050110A9), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_CERR_LOG_MASK                                   ,
+       RULL(0x050111A9), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_CERR_LOG_MASK                                   ,
+       RULL(0x050112A9), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CERR_PTY_HOLD                                   ,
+       RULL(0x050110A6), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_CERR_PTY_HOLD                                   ,
+       RULL(0x050111A6), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_CERR_PTY_HOLD                                   ,
+       RULL(0x050112A6), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CERR_PTY_MASK                                   ,
+       RULL(0x050110A7), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_CERR_PTY_MASK                                   ,
+       RULL(0x050111A7), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_CERR_PTY_MASK                                   ,
+       RULL(0x050112A7), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PEC_0_STACK0_CERR_RPT0_REG                              ,
+       RULL(0x04010C4A), SH_UNT_PEC_0_STACK0, SH_ACS_SCOM_RO   );
+REG64( PEC_0_STACK1_CERR_RPT0_REG                              ,
+       RULL(0x04010C8A), SH_UNT_PEC_0_STACK1, SH_ACS_SCOM_RO   );
+REG64( PEC_0_STACK2_CERR_RPT0_REG                              ,
+       RULL(0x04010CCA), SH_UNT_PEC_0_STACK2, SH_ACS_SCOM_RO   );
+REG64( PEC_1_STACK0_CERR_RPT0_REG                              ,
+       RULL(0x0401104A), SH_UNT_PEC_1_STACK0, SH_ACS_SCOM_RO   );
+REG64( PEC_1_STACK1_CERR_RPT0_REG                              ,
+       RULL(0x0401108A), SH_UNT_PEC_1_STACK1, SH_ACS_SCOM_RO   );
+REG64( PEC_1_STACK2_CERR_RPT0_REG                              ,
+       RULL(0x040110CA), SH_UNT_PEC_1_STACK2, SH_ACS_SCOM_RO   );
+REG64( PEC_2_STACK0_CERR_RPT0_REG                              ,
+       RULL(0x0401144A), SH_UNT_PEC_2_STACK0, SH_ACS_SCOM_RO   );
+REG64( PEC_2_STACK1_CERR_RPT0_REG                              ,
+       RULL(0x0401148A), SH_UNT_PEC_2_STACK1, SH_ACS_SCOM_RO   );
+REG64( PEC_2_STACK2_CERR_RPT0_REG                              ,
+       RULL(0x040114CA), SH_UNT_PEC_2_STACK2, SH_ACS_SCOM_RO   );
+REG64( PEC_STACK0_CERR_RPT0_REG                                ,
+       RULL(0x04010C4A), SH_UNT_PEC_STACK0, SH_ACS_SCOM_RO   );
+REG64( PEC_STACK1_CERR_RPT0_REG                                ,
+       RULL(0x04010C8A), SH_UNT_PEC_STACK1, SH_ACS_SCOM_RO   );
+REG64( PEC_STACK2_CERR_RPT0_REG                                ,
+       RULL(0x04010CCA), SH_UNT_PEC_STACK2, SH_ACS_SCOM_RO   );
+
+REG64( PEC_0_STACK0_CERR_RPT1_REG                              ,
+       RULL(0x04010C4B), SH_UNT_PEC_0_STACK0, SH_ACS_SCOM_RO   );
+REG64( PEC_0_STACK1_CERR_RPT1_REG                              ,
+       RULL(0x04010C8B), SH_UNT_PEC_0_STACK1, SH_ACS_SCOM_RO   );
+REG64( PEC_0_STACK2_CERR_RPT1_REG                              ,
+       RULL(0x04010CCB), SH_UNT_PEC_0_STACK2, SH_ACS_SCOM_RO   );
+REG64( PEC_1_STACK0_CERR_RPT1_REG                              ,
+       RULL(0x0401104B), SH_UNT_PEC_1_STACK0, SH_ACS_SCOM_RO   );
+REG64( PEC_1_STACK1_CERR_RPT1_REG                              ,
+       RULL(0x0401108B), SH_UNT_PEC_1_STACK1, SH_ACS_SCOM_RO   );
+REG64( PEC_1_STACK2_CERR_RPT1_REG                              ,
+       RULL(0x040110CB), SH_UNT_PEC_1_STACK2, SH_ACS_SCOM_RO   );
+REG64( PEC_2_STACK0_CERR_RPT1_REG                              ,
+       RULL(0x0401144B), SH_UNT_PEC_2_STACK0, SH_ACS_SCOM_RO   );
+REG64( PEC_2_STACK1_CERR_RPT1_REG                              ,
+       RULL(0x0401148B), SH_UNT_PEC_2_STACK1, SH_ACS_SCOM_RO   );
+REG64( PEC_2_STACK2_CERR_RPT1_REG                              ,
+       RULL(0x040114CB), SH_UNT_PEC_2_STACK2, SH_ACS_SCOM_RO   );
+REG64( PEC_STACK0_CERR_RPT1_REG                                ,
+       RULL(0x04010C4B), SH_UNT_PEC_STACK0, SH_ACS_SCOM_RO   );
+REG64( PEC_STACK1_CERR_RPT1_REG                                ,
+       RULL(0x04010C8B), SH_UNT_PEC_STACK1, SH_ACS_SCOM_RO   );
+REG64( PEC_STACK2_CERR_RPT1_REG                                ,
+       RULL(0x04010CCB), SH_UNT_PEC_STACK2, SH_ACS_SCOM_RO   );
+
+REG64( PU_PIB2OPB0_CMD_WRDAT                                   ,
+       RULL(0x00020000), SH_UNT_PU_PIB2OPB0, SH_ACS_SCOM      );
+REG64( PU_PIB2OPB1_CMD_WRDAT                                   ,
+       RULL(0x00020010), SH_UNT_PU_PIB2OPB1, SH_ACS_SCOM      );
+
+REG64( PU_CME0_CME_LCL_DBG_PPE                                 ,
+       RULL(0x109010120), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME0_CME_LCL_DBG_PPE1                                ,
+       RULL(0x109010138), SH_UNT_PU_CME0  , SH_ACS_PPE1      );
+REG64( PU_CME0_CME_LCL_DBG_PPE2                                ,
+       RULL(0x109010130), SH_UNT_PU_CME0  , SH_ACS_PPE2      );
+REG64( PU_CME1_CME_LCL_DBG_PPE                                 ,
+       RULL(0x109020120), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_DBG_PPE1                                ,
+       RULL(0x109020138), SH_UNT_PU_CME1  , SH_ACS_PPE1      );
+REG64( PU_CME1_CME_LCL_DBG_PPE2                                ,
+       RULL(0x109020130), SH_UNT_PU_CME1  , SH_ACS_PPE2      );
+REG64( PU_CME2_CME_LCL_DBG_PPE                                 ,
+       RULL(0x10A010120), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_DBG_PPE1                                ,
+       RULL(0x10A010138), SH_UNT_PU_CME2  , SH_ACS_PPE1      );
+REG64( PU_CME2_CME_LCL_DBG_PPE2                                ,
+       RULL(0x10A010130), SH_UNT_PU_CME2  , SH_ACS_PPE2      );
+REG64( PU_CME3_CME_LCL_DBG_PPE                                 ,
+       RULL(0x10A020120), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_DBG_PPE1                                ,
+       RULL(0x10A020138), SH_UNT_PU_CME3  , SH_ACS_PPE1      );
+REG64( PU_CME3_CME_LCL_DBG_PPE2                                ,
+       RULL(0x10A020130), SH_UNT_PU_CME3  , SH_ACS_PPE2      );
+REG64( PU_CME4_CME_LCL_DBG_PPE                                 ,
+       RULL(0x10B010120), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_DBG_PPE1                                ,
+       RULL(0x10B010138), SH_UNT_PU_CME4  , SH_ACS_PPE1      );
+REG64( PU_CME4_CME_LCL_DBG_PPE2                                ,
+       RULL(0x10B010130), SH_UNT_PU_CME4  , SH_ACS_PPE2      );
+REG64( PU_CME5_CME_LCL_DBG_PPE                                 ,
+       RULL(0x10B020120), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_DBG_PPE1                                ,
+       RULL(0x10B020138), SH_UNT_PU_CME5  , SH_ACS_PPE1      );
+REG64( PU_CME5_CME_LCL_DBG_PPE2                                ,
+       RULL(0x10B020130), SH_UNT_PU_CME5  , SH_ACS_PPE2      );
+REG64( PU_CME6_CME_LCL_DBG_PPE                                 ,
+       RULL(0x10C010120), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_DBG_PPE1                                ,
+       RULL(0x10C010138), SH_UNT_PU_CME6  , SH_ACS_PPE1      );
+REG64( PU_CME6_CME_LCL_DBG_PPE2                                ,
+       RULL(0x10C010130), SH_UNT_PU_CME6  , SH_ACS_PPE2      );
+REG64( PU_CME7_CME_LCL_DBG_PPE                                 ,
+       RULL(0x10C020120), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_DBG_PPE1                                ,
+       RULL(0x10C020138), SH_UNT_PU_CME7  , SH_ACS_PPE1      );
+REG64( PU_CME7_CME_LCL_DBG_PPE2                                ,
+       RULL(0x10C020130), SH_UNT_PU_CME7  , SH_ACS_PPE2      );
+REG64( PU_CME8_CME_LCL_DBG_PPE                                 ,
+       RULL(0x10D010120), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_DBG_PPE1                                ,
+       RULL(0x10D010138), SH_UNT_PU_CME8  , SH_ACS_PPE1      );
+REG64( PU_CME8_CME_LCL_DBG_PPE2                                ,
+       RULL(0x10D010130), SH_UNT_PU_CME8  , SH_ACS_PPE2      );
+REG64( PU_CME9_CME_LCL_DBG_PPE                                 ,
+       RULL(0x10D020120), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_DBG_PPE1                                ,
+       RULL(0x10D020138), SH_UNT_PU_CME9  , SH_ACS_PPE1      );
+REG64( PU_CME9_CME_LCL_DBG_PPE2                                ,
+       RULL(0x10D020130), SH_UNT_PU_CME9  , SH_ACS_PPE2      );
+REG64( PU_CME10_CME_LCL_DBG_PPE                                ,
+       RULL(0x10E010120), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_DBG_PPE1                               ,
+       RULL(0x10E010138), SH_UNT_PU_CME10 , SH_ACS_PPE1      );
+REG64( PU_CME10_CME_LCL_DBG_PPE2                               ,
+       RULL(0x10E010130), SH_UNT_PU_CME10 , SH_ACS_PPE2      );
+REG64( PU_CME11_CME_LCL_DBG_PPE                                ,
+       RULL(0x10E020120), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_DBG_PPE1                               ,
+       RULL(0x10E020138), SH_UNT_PU_CME11 , SH_ACS_PPE1      );
+REG64( PU_CME11_CME_LCL_DBG_PPE2                               ,
+       RULL(0x10E020130), SH_UNT_PU_CME11 , SH_ACS_PPE2      );
+
+REG64( PU_CME0_CME_LCL_EIMR_PPE                                ,
+       RULL(0x109010020), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME0_CME_LCL_EIMR_PPE1                               ,
+       RULL(0x109010038), SH_UNT_PU_CME0  , SH_ACS_PPE1      );
+REG64( PU_CME0_CME_LCL_EIMR_PPE2                               ,
+       RULL(0x109010030), SH_UNT_PU_CME0  , SH_ACS_PPE2      );
+REG64( PU_CME1_CME_LCL_EIMR_PPE                                ,
+       RULL(0x109020020), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_EIMR_PPE1                               ,
+       RULL(0x109020038), SH_UNT_PU_CME1  , SH_ACS_PPE1      );
+REG64( PU_CME1_CME_LCL_EIMR_PPE2                               ,
+       RULL(0x109020030), SH_UNT_PU_CME1  , SH_ACS_PPE2      );
+REG64( PU_CME2_CME_LCL_EIMR_PPE                                ,
+       RULL(0x10A010020), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_EIMR_PPE1                               ,
+       RULL(0x10A010038), SH_UNT_PU_CME2  , SH_ACS_PPE1      );
+REG64( PU_CME2_CME_LCL_EIMR_PPE2                               ,
+       RULL(0x10A010030), SH_UNT_PU_CME2  , SH_ACS_PPE2      );
+REG64( PU_CME3_CME_LCL_EIMR_PPE                                ,
+       RULL(0x10A020020), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_EIMR_PPE1                               ,
+       RULL(0x10A020038), SH_UNT_PU_CME3  , SH_ACS_PPE1      );
+REG64( PU_CME3_CME_LCL_EIMR_PPE2                               ,
+       RULL(0x10A020030), SH_UNT_PU_CME3  , SH_ACS_PPE2      );
+REG64( PU_CME4_CME_LCL_EIMR_PPE                                ,
+       RULL(0x10B010020), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_EIMR_PPE1                               ,
+       RULL(0x10B010038), SH_UNT_PU_CME4  , SH_ACS_PPE1      );
+REG64( PU_CME4_CME_LCL_EIMR_PPE2                               ,
+       RULL(0x10B010030), SH_UNT_PU_CME4  , SH_ACS_PPE2      );
+REG64( PU_CME5_CME_LCL_EIMR_PPE                                ,
+       RULL(0x10B020020), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_EIMR_PPE1                               ,
+       RULL(0x10B020038), SH_UNT_PU_CME5  , SH_ACS_PPE1      );
+REG64( PU_CME5_CME_LCL_EIMR_PPE2                               ,
+       RULL(0x10B020030), SH_UNT_PU_CME5  , SH_ACS_PPE2      );
+REG64( PU_CME6_CME_LCL_EIMR_PPE                                ,
+       RULL(0x10C010020), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_EIMR_PPE1                               ,
+       RULL(0x10C010038), SH_UNT_PU_CME6  , SH_ACS_PPE1      );
+REG64( PU_CME6_CME_LCL_EIMR_PPE2                               ,
+       RULL(0x10C010030), SH_UNT_PU_CME6  , SH_ACS_PPE2      );
+REG64( PU_CME7_CME_LCL_EIMR_PPE                                ,
+       RULL(0x10C020020), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_EIMR_PPE1                               ,
+       RULL(0x10C020038), SH_UNT_PU_CME7  , SH_ACS_PPE1      );
+REG64( PU_CME7_CME_LCL_EIMR_PPE2                               ,
+       RULL(0x10C020030), SH_UNT_PU_CME7  , SH_ACS_PPE2      );
+REG64( PU_CME8_CME_LCL_EIMR_PPE                                ,
+       RULL(0x10D010020), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_EIMR_PPE1                               ,
+       RULL(0x10D010038), SH_UNT_PU_CME8  , SH_ACS_PPE1      );
+REG64( PU_CME8_CME_LCL_EIMR_PPE2                               ,
+       RULL(0x10D010030), SH_UNT_PU_CME8  , SH_ACS_PPE2      );
+REG64( PU_CME9_CME_LCL_EIMR_PPE                                ,
+       RULL(0x10D020020), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_EIMR_PPE1                               ,
+       RULL(0x10D020038), SH_UNT_PU_CME9  , SH_ACS_PPE1      );
+REG64( PU_CME9_CME_LCL_EIMR_PPE2                               ,
+       RULL(0x10D020030), SH_UNT_PU_CME9  , SH_ACS_PPE2      );
+REG64( PU_CME10_CME_LCL_EIMR_PPE                               ,
+       RULL(0x10E010020), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_EIMR_PPE1                              ,
+       RULL(0x10E010038), SH_UNT_PU_CME10 , SH_ACS_PPE1      );
+REG64( PU_CME10_CME_LCL_EIMR_PPE2                              ,
+       RULL(0x10E010030), SH_UNT_PU_CME10 , SH_ACS_PPE2      );
+REG64( PU_CME11_CME_LCL_EIMR_PPE                               ,
+       RULL(0x10E020020), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_EIMR_PPE1                              ,
+       RULL(0x10E020038), SH_UNT_PU_CME11 , SH_ACS_PPE1      );
+REG64( PU_CME11_CME_LCL_EIMR_PPE2                              ,
+       RULL(0x10E020030), SH_UNT_PU_CME11 , SH_ACS_PPE2      );
+
+REG64( PU_CME0_CME_LCL_EINR_PPE                                ,
+       RULL(0x1090100A0), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_EINR_PPE                                ,
+       RULL(0x1090200A0), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_EINR_PPE                                ,
+       RULL(0x10A0100A0), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_EINR_PPE                                ,
+       RULL(0x10A0200A0), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_EINR_PPE                                ,
+       RULL(0x10B0100A0), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_EINR_PPE                                ,
+       RULL(0x10B0200A0), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_EINR_PPE                                ,
+       RULL(0x10C0100A0), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_EINR_PPE                                ,
+       RULL(0x10C0200A0), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_EINR_PPE                                ,
+       RULL(0x10D0100A0), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_EINR_PPE                                ,
+       RULL(0x10D0200A0), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_EINR_PPE                               ,
+       RULL(0x10E0100A0), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_EINR_PPE                               ,
+       RULL(0x10E0200A0), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_LCL_EIPR_PPE                                ,
+       RULL(0x109010040), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME0_CME_LCL_EIPR_PPE1                               ,
+       RULL(0x109010058), SH_UNT_PU_CME0  , SH_ACS_PPE1      );
+REG64( PU_CME0_CME_LCL_EIPR_PPE2                               ,
+       RULL(0x109010050), SH_UNT_PU_CME0  , SH_ACS_PPE2      );
+REG64( PU_CME1_CME_LCL_EIPR_PPE                                ,
+       RULL(0x109020040), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_EIPR_PPE1                               ,
+       RULL(0x109020058), SH_UNT_PU_CME1  , SH_ACS_PPE1      );
+REG64( PU_CME1_CME_LCL_EIPR_PPE2                               ,
+       RULL(0x109020050), SH_UNT_PU_CME1  , SH_ACS_PPE2      );
+REG64( PU_CME2_CME_LCL_EIPR_PPE                                ,
+       RULL(0x10A010040), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_EIPR_PPE1                               ,
+       RULL(0x10A010058), SH_UNT_PU_CME2  , SH_ACS_PPE1      );
+REG64( PU_CME2_CME_LCL_EIPR_PPE2                               ,
+       RULL(0x10A010050), SH_UNT_PU_CME2  , SH_ACS_PPE2      );
+REG64( PU_CME3_CME_LCL_EIPR_PPE                                ,
+       RULL(0x10A020040), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_EIPR_PPE1                               ,
+       RULL(0x10A020058), SH_UNT_PU_CME3  , SH_ACS_PPE1      );
+REG64( PU_CME3_CME_LCL_EIPR_PPE2                               ,
+       RULL(0x10A020050), SH_UNT_PU_CME3  , SH_ACS_PPE2      );
+REG64( PU_CME4_CME_LCL_EIPR_PPE                                ,
+       RULL(0x10B010040), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_EIPR_PPE1                               ,
+       RULL(0x10B010058), SH_UNT_PU_CME4  , SH_ACS_PPE1      );
+REG64( PU_CME4_CME_LCL_EIPR_PPE2                               ,
+       RULL(0x10B010050), SH_UNT_PU_CME4  , SH_ACS_PPE2      );
+REG64( PU_CME5_CME_LCL_EIPR_PPE                                ,
+       RULL(0x10B020040), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_EIPR_PPE1                               ,
+       RULL(0x10B020058), SH_UNT_PU_CME5  , SH_ACS_PPE1      );
+REG64( PU_CME5_CME_LCL_EIPR_PPE2                               ,
+       RULL(0x10B020050), SH_UNT_PU_CME5  , SH_ACS_PPE2      );
+REG64( PU_CME6_CME_LCL_EIPR_PPE                                ,
+       RULL(0x10C010040), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_EIPR_PPE1                               ,
+       RULL(0x10C010058), SH_UNT_PU_CME6  , SH_ACS_PPE1      );
+REG64( PU_CME6_CME_LCL_EIPR_PPE2                               ,
+       RULL(0x10C010050), SH_UNT_PU_CME6  , SH_ACS_PPE2      );
+REG64( PU_CME7_CME_LCL_EIPR_PPE                                ,
+       RULL(0x10C020040), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_EIPR_PPE1                               ,
+       RULL(0x10C020058), SH_UNT_PU_CME7  , SH_ACS_PPE1      );
+REG64( PU_CME7_CME_LCL_EIPR_PPE2                               ,
+       RULL(0x10C020050), SH_UNT_PU_CME7  , SH_ACS_PPE2      );
+REG64( PU_CME8_CME_LCL_EIPR_PPE                                ,
+       RULL(0x10D010040), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_EIPR_PPE1                               ,
+       RULL(0x10D010058), SH_UNT_PU_CME8  , SH_ACS_PPE1      );
+REG64( PU_CME8_CME_LCL_EIPR_PPE2                               ,
+       RULL(0x10D010050), SH_UNT_PU_CME8  , SH_ACS_PPE2      );
+REG64( PU_CME9_CME_LCL_EIPR_PPE                                ,
+       RULL(0x10D020040), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_EIPR_PPE1                               ,
+       RULL(0x10D020058), SH_UNT_PU_CME9  , SH_ACS_PPE1      );
+REG64( PU_CME9_CME_LCL_EIPR_PPE2                               ,
+       RULL(0x10D020050), SH_UNT_PU_CME9  , SH_ACS_PPE2      );
+REG64( PU_CME10_CME_LCL_EIPR_PPE                               ,
+       RULL(0x10E010040), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_EIPR_PPE1                              ,
+       RULL(0x10E010058), SH_UNT_PU_CME10 , SH_ACS_PPE1      );
+REG64( PU_CME10_CME_LCL_EIPR_PPE2                              ,
+       RULL(0x10E010050), SH_UNT_PU_CME10 , SH_ACS_PPE2      );
+REG64( PU_CME11_CME_LCL_EIPR_PPE                               ,
+       RULL(0x10E020040), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_EIPR_PPE1                              ,
+       RULL(0x10E020058), SH_UNT_PU_CME11 , SH_ACS_PPE1      );
+REG64( PU_CME11_CME_LCL_EIPR_PPE2                              ,
+       RULL(0x10E020050), SH_UNT_PU_CME11 , SH_ACS_PPE2      );
+
+REG64( PU_CME0_CME_LCL_EISR_PPE                                ,
+       RULL(0x109010000), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME0_CME_LCL_EISR_PPE1                               ,
+       RULL(0x109010018), SH_UNT_PU_CME0  , SH_ACS_PPE1      );
+REG64( PU_CME0_CME_LCL_EISR_PPE2                               ,
+       RULL(0x109010010), SH_UNT_PU_CME0  , SH_ACS_PPE2      );
+REG64( PU_CME1_CME_LCL_EISR_PPE                                ,
+       RULL(0x109020000), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_EISR_PPE1                               ,
+       RULL(0x109020018), SH_UNT_PU_CME1  , SH_ACS_PPE1      );
+REG64( PU_CME1_CME_LCL_EISR_PPE2                               ,
+       RULL(0x109020010), SH_UNT_PU_CME1  , SH_ACS_PPE2      );
+REG64( PU_CME2_CME_LCL_EISR_PPE                                ,
+       RULL(0x10A010000), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_EISR_PPE1                               ,
+       RULL(0x10A010018), SH_UNT_PU_CME2  , SH_ACS_PPE1      );
+REG64( PU_CME2_CME_LCL_EISR_PPE2                               ,
+       RULL(0x10A010010), SH_UNT_PU_CME2  , SH_ACS_PPE2      );
+REG64( PU_CME3_CME_LCL_EISR_PPE                                ,
+       RULL(0x10A020000), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_EISR_PPE1                               ,
+       RULL(0x10A020018), SH_UNT_PU_CME3  , SH_ACS_PPE1      );
+REG64( PU_CME3_CME_LCL_EISR_PPE2                               ,
+       RULL(0x10A020010), SH_UNT_PU_CME3  , SH_ACS_PPE2      );
+REG64( PU_CME4_CME_LCL_EISR_PPE                                ,
+       RULL(0x10B010000), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_EISR_PPE1                               ,
+       RULL(0x10B010018), SH_UNT_PU_CME4  , SH_ACS_PPE1      );
+REG64( PU_CME4_CME_LCL_EISR_PPE2                               ,
+       RULL(0x10B010010), SH_UNT_PU_CME4  , SH_ACS_PPE2      );
+REG64( PU_CME5_CME_LCL_EISR_PPE                                ,
+       RULL(0x10B020000), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_EISR_PPE1                               ,
+       RULL(0x10B020018), SH_UNT_PU_CME5  , SH_ACS_PPE1      );
+REG64( PU_CME5_CME_LCL_EISR_PPE2                               ,
+       RULL(0x10B020010), SH_UNT_PU_CME5  , SH_ACS_PPE2      );
+REG64( PU_CME6_CME_LCL_EISR_PPE                                ,
+       RULL(0x10C010000), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_EISR_PPE1                               ,
+       RULL(0x10C010018), SH_UNT_PU_CME6  , SH_ACS_PPE1      );
+REG64( PU_CME6_CME_LCL_EISR_PPE2                               ,
+       RULL(0x10C010010), SH_UNT_PU_CME6  , SH_ACS_PPE2      );
+REG64( PU_CME7_CME_LCL_EISR_PPE                                ,
+       RULL(0x10C020000), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_EISR_PPE1                               ,
+       RULL(0x10C020018), SH_UNT_PU_CME7  , SH_ACS_PPE1      );
+REG64( PU_CME7_CME_LCL_EISR_PPE2                               ,
+       RULL(0x10C020010), SH_UNT_PU_CME7  , SH_ACS_PPE2      );
+REG64( PU_CME8_CME_LCL_EISR_PPE                                ,
+       RULL(0x10D010000), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_EISR_PPE1                               ,
+       RULL(0x10D010018), SH_UNT_PU_CME8  , SH_ACS_PPE1      );
+REG64( PU_CME8_CME_LCL_EISR_PPE2                               ,
+       RULL(0x10D010010), SH_UNT_PU_CME8  , SH_ACS_PPE2      );
+REG64( PU_CME9_CME_LCL_EISR_PPE                                ,
+       RULL(0x10D020000), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_EISR_PPE1                               ,
+       RULL(0x10D020018), SH_UNT_PU_CME9  , SH_ACS_PPE1      );
+REG64( PU_CME9_CME_LCL_EISR_PPE2                               ,
+       RULL(0x10D020010), SH_UNT_PU_CME9  , SH_ACS_PPE2      );
+REG64( PU_CME10_CME_LCL_EISR_PPE                               ,
+       RULL(0x10E010000), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_EISR_PPE1                              ,
+       RULL(0x10E010018), SH_UNT_PU_CME10 , SH_ACS_PPE1      );
+REG64( PU_CME10_CME_LCL_EISR_PPE2                              ,
+       RULL(0x10E010010), SH_UNT_PU_CME10 , SH_ACS_PPE2      );
+REG64( PU_CME11_CME_LCL_EISR_PPE                               ,
+       RULL(0x10E020000), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_EISR_PPE1                              ,
+       RULL(0x10E020018), SH_UNT_PU_CME11 , SH_ACS_PPE1      );
+REG64( PU_CME11_CME_LCL_EISR_PPE2                              ,
+       RULL(0x10E020010), SH_UNT_PU_CME11 , SH_ACS_PPE2      );
+
+REG64( PU_CME0_CME_LCL_EISTR_PPE                               ,
+       RULL(0x109010080), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_EISTR_PPE                               ,
+       RULL(0x109020080), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_EISTR_PPE                               ,
+       RULL(0x10A010080), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_EISTR_PPE                               ,
+       RULL(0x10A020080), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_EISTR_PPE                               ,
+       RULL(0x10B010080), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_EISTR_PPE                               ,
+       RULL(0x10B020080), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_EISTR_PPE                               ,
+       RULL(0x10C010080), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_EISTR_PPE                               ,
+       RULL(0x10C020080), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_EISTR_PPE                               ,
+       RULL(0x10D010080), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_EISTR_PPE                               ,
+       RULL(0x10D020080), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_EISTR_PPE                              ,
+       RULL(0x10E010080), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_EISTR_PPE                              ,
+       RULL(0x10E020080), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_LCL_EITR_PPE                                ,
+       RULL(0x109010060), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME0_CME_LCL_EITR_PPE1                               ,
+       RULL(0x109010078), SH_UNT_PU_CME0  , SH_ACS_PPE1      );
+REG64( PU_CME0_CME_LCL_EITR_PPE2                               ,
+       RULL(0x109010070), SH_UNT_PU_CME0  , SH_ACS_PPE2      );
+REG64( PU_CME1_CME_LCL_EITR_PPE                                ,
+       RULL(0x109020060), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_EITR_PPE1                               ,
+       RULL(0x109020078), SH_UNT_PU_CME1  , SH_ACS_PPE1      );
+REG64( PU_CME1_CME_LCL_EITR_PPE2                               ,
+       RULL(0x109020070), SH_UNT_PU_CME1  , SH_ACS_PPE2      );
+REG64( PU_CME2_CME_LCL_EITR_PPE                                ,
+       RULL(0x10A010060), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_EITR_PPE1                               ,
+       RULL(0x10A010078), SH_UNT_PU_CME2  , SH_ACS_PPE1      );
+REG64( PU_CME2_CME_LCL_EITR_PPE2                               ,
+       RULL(0x10A010070), SH_UNT_PU_CME2  , SH_ACS_PPE2      );
+REG64( PU_CME3_CME_LCL_EITR_PPE                                ,
+       RULL(0x10A020060), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_EITR_PPE1                               ,
+       RULL(0x10A020078), SH_UNT_PU_CME3  , SH_ACS_PPE1      );
+REG64( PU_CME3_CME_LCL_EITR_PPE2                               ,
+       RULL(0x10A020070), SH_UNT_PU_CME3  , SH_ACS_PPE2      );
+REG64( PU_CME4_CME_LCL_EITR_PPE                                ,
+       RULL(0x10B010060), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_EITR_PPE1                               ,
+       RULL(0x10B010078), SH_UNT_PU_CME4  , SH_ACS_PPE1      );
+REG64( PU_CME4_CME_LCL_EITR_PPE2                               ,
+       RULL(0x10B010070), SH_UNT_PU_CME4  , SH_ACS_PPE2      );
+REG64( PU_CME5_CME_LCL_EITR_PPE                                ,
+       RULL(0x10B020060), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_EITR_PPE1                               ,
+       RULL(0x10B020078), SH_UNT_PU_CME5  , SH_ACS_PPE1      );
+REG64( PU_CME5_CME_LCL_EITR_PPE2                               ,
+       RULL(0x10B020070), SH_UNT_PU_CME5  , SH_ACS_PPE2      );
+REG64( PU_CME6_CME_LCL_EITR_PPE                                ,
+       RULL(0x10C010060), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_EITR_PPE1                               ,
+       RULL(0x10C010078), SH_UNT_PU_CME6  , SH_ACS_PPE1      );
+REG64( PU_CME6_CME_LCL_EITR_PPE2                               ,
+       RULL(0x10C010070), SH_UNT_PU_CME6  , SH_ACS_PPE2      );
+REG64( PU_CME7_CME_LCL_EITR_PPE                                ,
+       RULL(0x10C020060), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_EITR_PPE1                               ,
+       RULL(0x10C020078), SH_UNT_PU_CME7  , SH_ACS_PPE1      );
+REG64( PU_CME7_CME_LCL_EITR_PPE2                               ,
+       RULL(0x10C020070), SH_UNT_PU_CME7  , SH_ACS_PPE2      );
+REG64( PU_CME8_CME_LCL_EITR_PPE                                ,
+       RULL(0x10D010060), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_EITR_PPE1                               ,
+       RULL(0x10D010078), SH_UNT_PU_CME8  , SH_ACS_PPE1      );
+REG64( PU_CME8_CME_LCL_EITR_PPE2                               ,
+       RULL(0x10D010070), SH_UNT_PU_CME8  , SH_ACS_PPE2      );
+REG64( PU_CME9_CME_LCL_EITR_PPE                                ,
+       RULL(0x10D020060), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_EITR_PPE1                               ,
+       RULL(0x10D020078), SH_UNT_PU_CME9  , SH_ACS_PPE1      );
+REG64( PU_CME9_CME_LCL_EITR_PPE2                               ,
+       RULL(0x10D020070), SH_UNT_PU_CME9  , SH_ACS_PPE2      );
+REG64( PU_CME10_CME_LCL_EITR_PPE                               ,
+       RULL(0x10E010060), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_EITR_PPE1                              ,
+       RULL(0x10E010078), SH_UNT_PU_CME10 , SH_ACS_PPE1      );
+REG64( PU_CME10_CME_LCL_EITR_PPE2                              ,
+       RULL(0x10E010070), SH_UNT_PU_CME10 , SH_ACS_PPE2      );
+REG64( PU_CME11_CME_LCL_EITR_PPE                               ,
+       RULL(0x10E020060), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_EITR_PPE1                              ,
+       RULL(0x10E020078), SH_UNT_PU_CME11 , SH_ACS_PPE1      );
+REG64( PU_CME11_CME_LCL_EITR_PPE2                              ,
+       RULL(0x10E020070), SH_UNT_PU_CME11 , SH_ACS_PPE2      );
+
+REG64( PU_CME0_CME_LCL_ICCR_PPE                                ,
+       RULL(0x109010700), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME0_CME_LCL_ICCR_PPE1                               ,
+       RULL(0x109010718), SH_UNT_PU_CME0  , SH_ACS_PPE1      );
+REG64( PU_CME0_CME_LCL_ICCR_PPE2                               ,
+       RULL(0x109010710), SH_UNT_PU_CME0  , SH_ACS_PPE2      );
+REG64( PU_CME1_CME_LCL_ICCR_PPE                                ,
+       RULL(0x109020700), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_ICCR_PPE1                               ,
+       RULL(0x109020718), SH_UNT_PU_CME1  , SH_ACS_PPE1      );
+REG64( PU_CME1_CME_LCL_ICCR_PPE2                               ,
+       RULL(0x109020710), SH_UNT_PU_CME1  , SH_ACS_PPE2      );
+REG64( PU_CME2_CME_LCL_ICCR_PPE                                ,
+       RULL(0x10A010700), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_ICCR_PPE1                               ,
+       RULL(0x10A010718), SH_UNT_PU_CME2  , SH_ACS_PPE1      );
+REG64( PU_CME2_CME_LCL_ICCR_PPE2                               ,
+       RULL(0x10A010710), SH_UNT_PU_CME2  , SH_ACS_PPE2      );
+REG64( PU_CME3_CME_LCL_ICCR_PPE                                ,
+       RULL(0x10A020700), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_ICCR_PPE1                               ,
+       RULL(0x10A020718), SH_UNT_PU_CME3  , SH_ACS_PPE1      );
+REG64( PU_CME3_CME_LCL_ICCR_PPE2                               ,
+       RULL(0x10A020710), SH_UNT_PU_CME3  , SH_ACS_PPE2      );
+REG64( PU_CME4_CME_LCL_ICCR_PPE                                ,
+       RULL(0x10B010700), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_ICCR_PPE1                               ,
+       RULL(0x10B010718), SH_UNT_PU_CME4  , SH_ACS_PPE1      );
+REG64( PU_CME4_CME_LCL_ICCR_PPE2                               ,
+       RULL(0x10B010710), SH_UNT_PU_CME4  , SH_ACS_PPE2      );
+REG64( PU_CME5_CME_LCL_ICCR_PPE                                ,
+       RULL(0x10B020700), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_ICCR_PPE1                               ,
+       RULL(0x10B020718), SH_UNT_PU_CME5  , SH_ACS_PPE1      );
+REG64( PU_CME5_CME_LCL_ICCR_PPE2                               ,
+       RULL(0x10B020710), SH_UNT_PU_CME5  , SH_ACS_PPE2      );
+REG64( PU_CME6_CME_LCL_ICCR_PPE                                ,
+       RULL(0x10C010700), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_ICCR_PPE1                               ,
+       RULL(0x10C010718), SH_UNT_PU_CME6  , SH_ACS_PPE1      );
+REG64( PU_CME6_CME_LCL_ICCR_PPE2                               ,
+       RULL(0x10C010710), SH_UNT_PU_CME6  , SH_ACS_PPE2      );
+REG64( PU_CME7_CME_LCL_ICCR_PPE                                ,
+       RULL(0x10C020700), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_ICCR_PPE1                               ,
+       RULL(0x10C020718), SH_UNT_PU_CME7  , SH_ACS_PPE1      );
+REG64( PU_CME7_CME_LCL_ICCR_PPE2                               ,
+       RULL(0x10C020710), SH_UNT_PU_CME7  , SH_ACS_PPE2      );
+REG64( PU_CME8_CME_LCL_ICCR_PPE                                ,
+       RULL(0x10D010700), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_ICCR_PPE1                               ,
+       RULL(0x10D010718), SH_UNT_PU_CME8  , SH_ACS_PPE1      );
+REG64( PU_CME8_CME_LCL_ICCR_PPE2                               ,
+       RULL(0x10D010710), SH_UNT_PU_CME8  , SH_ACS_PPE2      );
+REG64( PU_CME9_CME_LCL_ICCR_PPE                                ,
+       RULL(0x10D020700), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_ICCR_PPE1                               ,
+       RULL(0x10D020718), SH_UNT_PU_CME9  , SH_ACS_PPE1      );
+REG64( PU_CME9_CME_LCL_ICCR_PPE2                               ,
+       RULL(0x10D020710), SH_UNT_PU_CME9  , SH_ACS_PPE2      );
+REG64( PU_CME10_CME_LCL_ICCR_PPE                               ,
+       RULL(0x10E010700), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_ICCR_PPE1                              ,
+       RULL(0x10E010718), SH_UNT_PU_CME10 , SH_ACS_PPE1      );
+REG64( PU_CME10_CME_LCL_ICCR_PPE2                              ,
+       RULL(0x10E010710), SH_UNT_PU_CME10 , SH_ACS_PPE2      );
+REG64( PU_CME11_CME_LCL_ICCR_PPE                               ,
+       RULL(0x10E020700), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_ICCR_PPE1                              ,
+       RULL(0x10E020718), SH_UNT_PU_CME11 , SH_ACS_PPE1      );
+REG64( PU_CME11_CME_LCL_ICCR_PPE2                              ,
+       RULL(0x10E020710), SH_UNT_PU_CME11 , SH_ACS_PPE2      );
+
+REG64( PU_CME0_CME_LCL_ICRR_PPE                                ,
+       RULL(0x109010740), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_ICRR_PPE                                ,
+       RULL(0x109020740), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_ICRR_PPE                                ,
+       RULL(0x10A010740), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_ICRR_PPE                                ,
+       RULL(0x10A020740), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_ICRR_PPE                                ,
+       RULL(0x10B010740), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_ICRR_PPE                                ,
+       RULL(0x10B020740), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_ICRR_PPE                                ,
+       RULL(0x10C010740), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_ICRR_PPE                                ,
+       RULL(0x10C020740), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_ICRR_PPE                                ,
+       RULL(0x10D010740), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_ICRR_PPE                                ,
+       RULL(0x10D020740), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_ICRR_PPE                               ,
+       RULL(0x10E010740), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_ICRR_PPE                               ,
+       RULL(0x10E020740), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_LCL_ICSR_PPE                                ,
+       RULL(0x109010720), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_ICSR_PPE                                ,
+       RULL(0x109020720), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_ICSR_PPE                                ,
+       RULL(0x10A010720), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_ICSR_PPE                                ,
+       RULL(0x10A020720), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_ICSR_PPE                                ,
+       RULL(0x10B010720), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_ICSR_PPE                                ,
+       RULL(0x10B020720), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_ICSR_PPE                                ,
+       RULL(0x10C010720), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_ICSR_PPE                                ,
+       RULL(0x10C020720), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_ICSR_PPE                                ,
+       RULL(0x10D010720), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_ICSR_PPE                                ,
+       RULL(0x10D020720), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_ICSR_PPE                               ,
+       RULL(0x10E010720), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_ICSR_PPE                               ,
+       RULL(0x10E020720), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_LCL_LMCR_PPE                                ,
+       RULL(0x1090101A0), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_LMCR_PPE                                ,
+       RULL(0x1090201A0), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_LMCR_PPE                                ,
+       RULL(0x10A0101A0), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_LMCR_PPE                                ,
+       RULL(0x10A0201A0), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_LMCR_PPE                                ,
+       RULL(0x10B0101A0), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_LMCR_PPE                                ,
+       RULL(0x10B0201A0), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_LMCR_PPE                                ,
+       RULL(0x10C0101A0), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_LMCR_PPE                                ,
+       RULL(0x10C0201A0), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_LMCR_PPE                                ,
+       RULL(0x10D0101A0), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_LMCR_PPE                                ,
+       RULL(0x10D0201A0), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_LMCR_PPE                               ,
+       RULL(0x10E0101A0), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_LMCR_PPE                               ,
+       RULL(0x10E0201A0), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_LCL_PECESR0_PPE                             ,
+       RULL(0x109010280), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_PECESR0_PPE                             ,
+       RULL(0x109020280), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_PECESR0_PPE                             ,
+       RULL(0x10A010280), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_PECESR0_PPE                             ,
+       RULL(0x10A020280), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_PECESR0_PPE                             ,
+       RULL(0x10B010280), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_PECESR0_PPE                             ,
+       RULL(0x10B020280), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_PECESR0_PPE                             ,
+       RULL(0x10C010280), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_PECESR0_PPE                             ,
+       RULL(0x10C020280), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_PECESR0_PPE                             ,
+       RULL(0x10D010280), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_PECESR0_PPE                             ,
+       RULL(0x10D020280), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_PECESR0_PPE                            ,
+       RULL(0x10E010280), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_PECESR0_PPE                            ,
+       RULL(0x10E020280), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_LCL_PECESR1_PPE                             ,
+       RULL(0x1090102A0), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_PECESR1_PPE                             ,
+       RULL(0x1090202A0), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_PECESR1_PPE                             ,
+       RULL(0x10A0102A0), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_PECESR1_PPE                             ,
+       RULL(0x10A0202A0), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_PECESR1_PPE                             ,
+       RULL(0x10B0102A0), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_PECESR1_PPE                             ,
+       RULL(0x10B0202A0), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_PECESR1_PPE                             ,
+       RULL(0x10C0102A0), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_PECESR1_PPE                             ,
+       RULL(0x10C0202A0), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_PECESR1_PPE                             ,
+       RULL(0x10D0102A0), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_PECESR1_PPE                             ,
+       RULL(0x10D0202A0), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_PECESR1_PPE                            ,
+       RULL(0x10E0102A0), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_PECESR1_PPE                            ,
+       RULL(0x10E0202A0), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_LCL_SISR_PPE                                ,
+       RULL(0x109010520), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_SISR_PPE                                ,
+       RULL(0x109020520), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_SISR_PPE                                ,
+       RULL(0x10A010520), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_SISR_PPE                                ,
+       RULL(0x10A020520), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_SISR_PPE                                ,
+       RULL(0x10B010520), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_SISR_PPE                                ,
+       RULL(0x10B020520), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_SISR_PPE                                ,
+       RULL(0x10C010520), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_SISR_PPE                                ,
+       RULL(0x10C020520), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_SISR_PPE                                ,
+       RULL(0x10D010520), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_SISR_PPE                                ,
+       RULL(0x10D020520), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_SISR_PPE                               ,
+       RULL(0x10E010520), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_SISR_PPE                               ,
+       RULL(0x10E020520), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_LCL_TSEL_PPE                                ,
+       RULL(0x109010100), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_TSEL_PPE                                ,
+       RULL(0x109020100), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_TSEL_PPE                                ,
+       RULL(0x10A010100), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_TSEL_PPE                                ,
+       RULL(0x10A020100), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_TSEL_PPE                                ,
+       RULL(0x10B010100), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_TSEL_PPE                                ,
+       RULL(0x10B020100), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_TSEL_PPE                                ,
+       RULL(0x10C010100), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_TSEL_PPE                                ,
+       RULL(0x10C020100), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_TSEL_PPE                                ,
+       RULL(0x10D010100), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_TSEL_PPE                                ,
+       RULL(0x10D020100), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_TSEL_PPE                               ,
+       RULL(0x10E010100), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_TSEL_PPE                               ,
+       RULL(0x10E020100), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_AFSR_PPE                               ,
+       RULL(0x109010160), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_AFSR_PPE                               ,
+       RULL(0x109020160), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_AFSR_PPE                               ,
+       RULL(0x10A010160), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_AFSR_PPE                               ,
+       RULL(0x10A020160), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_AFSR_PPE                               ,
+       RULL(0x10B010160), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_AFSR_PPE                               ,
+       RULL(0x10B020160), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_AFSR_PPE                               ,
+       RULL(0x10C010160), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_AFSR_PPE                               ,
+       RULL(0x10C020160), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_AFSR_PPE                               ,
+       RULL(0x10D010160), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_AFSR_PPE                               ,
+       RULL(0x10D020160), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_AFSR_PPE                              ,
+       RULL(0x10E010160), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_AFSR_PPE                              ,
+       RULL(0x10E020160), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_AFTR_PPE                               ,
+       RULL(0x109010180), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_AFTR_PPE                               ,
+       RULL(0x109020180), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_AFTR_PPE                               ,
+       RULL(0x10A010180), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_AFTR_PPE                               ,
+       RULL(0x10A020180), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_AFTR_PPE                               ,
+       RULL(0x10B010180), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_AFTR_PPE                               ,
+       RULL(0x10B020180), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_AFTR_PPE                               ,
+       RULL(0x10C010180), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_AFTR_PPE                               ,
+       RULL(0x10C020180), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_AFTR_PPE                               ,
+       RULL(0x10D010180), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_AFTR_PPE                               ,
+       RULL(0x10D020180), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_AFTR_PPE                              ,
+       RULL(0x10E010180), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_AFTR_PPE                              ,
+       RULL(0x10E020180), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_BCECSR_PPE                             ,
+       RULL(0x1090101F0), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_BCECSR_PPE                             ,
+       RULL(0x1090201F0), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_BCECSR_PPE                             ,
+       RULL(0x10A0101F0), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_BCECSR_PPE                             ,
+       RULL(0x10A0201F0), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_BCECSR_PPE                             ,
+       RULL(0x10B0101F0), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_BCECSR_PPE                             ,
+       RULL(0x10B0201F0), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_BCECSR_PPE                             ,
+       RULL(0x10C0101F0), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_BCECSR_PPE                             ,
+       RULL(0x10C0201F0), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_BCECSR_PPE                             ,
+       RULL(0x10D0101F0), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_BCECSR_PPE                             ,
+       RULL(0x10D0201F0), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_BCECSR_PPE                            ,
+       RULL(0x10E0101F0), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_BCECSR_PPE                            ,
+       RULL(0x10E0201F0), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_FLAGS_PPE                              ,
+       RULL(0x109010400), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME0_CME_SCOM_FLAGS_PPE1                             ,
+       RULL(0x109010418), SH_UNT_PU_CME0  , SH_ACS_PPE1      );
+REG64( PU_CME0_CME_SCOM_FLAGS_PPE2                             ,
+       RULL(0x109010410), SH_UNT_PU_CME0  , SH_ACS_PPE2      );
+REG64( PU_CME1_CME_SCOM_FLAGS_PPE                              ,
+       RULL(0x109020400), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_FLAGS_PPE1                             ,
+       RULL(0x109020418), SH_UNT_PU_CME1  , SH_ACS_PPE1      );
+REG64( PU_CME1_CME_SCOM_FLAGS_PPE2                             ,
+       RULL(0x109020410), SH_UNT_PU_CME1  , SH_ACS_PPE2      );
+REG64( PU_CME2_CME_SCOM_FLAGS_PPE                              ,
+       RULL(0x10A010400), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_FLAGS_PPE1                             ,
+       RULL(0x10A010418), SH_UNT_PU_CME2  , SH_ACS_PPE1      );
+REG64( PU_CME2_CME_SCOM_FLAGS_PPE2                             ,
+       RULL(0x10A010410), SH_UNT_PU_CME2  , SH_ACS_PPE2      );
+REG64( PU_CME3_CME_SCOM_FLAGS_PPE                              ,
+       RULL(0x10A020400), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_FLAGS_PPE1                             ,
+       RULL(0x10A020418), SH_UNT_PU_CME3  , SH_ACS_PPE1      );
+REG64( PU_CME3_CME_SCOM_FLAGS_PPE2                             ,
+       RULL(0x10A020410), SH_UNT_PU_CME3  , SH_ACS_PPE2      );
+REG64( PU_CME4_CME_SCOM_FLAGS_PPE                              ,
+       RULL(0x10B010400), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_FLAGS_PPE1                             ,
+       RULL(0x10B010418), SH_UNT_PU_CME4  , SH_ACS_PPE1      );
+REG64( PU_CME4_CME_SCOM_FLAGS_PPE2                             ,
+       RULL(0x10B010410), SH_UNT_PU_CME4  , SH_ACS_PPE2      );
+REG64( PU_CME5_CME_SCOM_FLAGS_PPE                              ,
+       RULL(0x10B020400), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_FLAGS_PPE1                             ,
+       RULL(0x10B020418), SH_UNT_PU_CME5  , SH_ACS_PPE1      );
+REG64( PU_CME5_CME_SCOM_FLAGS_PPE2                             ,
+       RULL(0x10B020410), SH_UNT_PU_CME5  , SH_ACS_PPE2      );
+REG64( PU_CME6_CME_SCOM_FLAGS_PPE                              ,
+       RULL(0x10C010400), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_FLAGS_PPE1                             ,
+       RULL(0x10C010418), SH_UNT_PU_CME6  , SH_ACS_PPE1      );
+REG64( PU_CME6_CME_SCOM_FLAGS_PPE2                             ,
+       RULL(0x10C010410), SH_UNT_PU_CME6  , SH_ACS_PPE2      );
+REG64( PU_CME7_CME_SCOM_FLAGS_PPE                              ,
+       RULL(0x10C020400), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_FLAGS_PPE1                             ,
+       RULL(0x10C020418), SH_UNT_PU_CME7  , SH_ACS_PPE1      );
+REG64( PU_CME7_CME_SCOM_FLAGS_PPE2                             ,
+       RULL(0x10C020410), SH_UNT_PU_CME7  , SH_ACS_PPE2      );
+REG64( PU_CME8_CME_SCOM_FLAGS_PPE                              ,
+       RULL(0x10D010400), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_FLAGS_PPE1                             ,
+       RULL(0x10D010418), SH_UNT_PU_CME8  , SH_ACS_PPE1      );
+REG64( PU_CME8_CME_SCOM_FLAGS_PPE2                             ,
+       RULL(0x10D010410), SH_UNT_PU_CME8  , SH_ACS_PPE2      );
+REG64( PU_CME9_CME_SCOM_FLAGS_PPE                              ,
+       RULL(0x10D020400), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_FLAGS_PPE1                             ,
+       RULL(0x10D020418), SH_UNT_PU_CME9  , SH_ACS_PPE1      );
+REG64( PU_CME9_CME_SCOM_FLAGS_PPE2                             ,
+       RULL(0x10D020410), SH_UNT_PU_CME9  , SH_ACS_PPE2      );
+REG64( PU_CME10_CME_SCOM_FLAGS_PPE                             ,
+       RULL(0x10E010400), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_FLAGS_PPE1                            ,
+       RULL(0x10E010418), SH_UNT_PU_CME10 , SH_ACS_PPE1      );
+REG64( PU_CME10_CME_SCOM_FLAGS_PPE2                            ,
+       RULL(0x10E010410), SH_UNT_PU_CME10 , SH_ACS_PPE2      );
+REG64( PU_CME11_CME_SCOM_FLAGS_PPE                             ,
+       RULL(0x10E020400), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_FLAGS_PPE1                            ,
+       RULL(0x10E020418), SH_UNT_PU_CME11 , SH_ACS_PPE1      );
+REG64( PU_CME11_CME_SCOM_FLAGS_PPE2                            ,
+       RULL(0x10E020410), SH_UNT_PU_CME11 , SH_ACS_PPE2      );
+
+REG64( PU_CME0_CME_SCOM_PMCRS0_PPE                             ,
+       RULL(0x109010240), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PMCRS0_PPE                             ,
+       RULL(0x109020240), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PMCRS0_PPE                             ,
+       RULL(0x10A010240), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PMCRS0_PPE                             ,
+       RULL(0x10A020240), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PMCRS0_PPE                             ,
+       RULL(0x10B010240), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PMCRS0_PPE                             ,
+       RULL(0x10B020240), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PMCRS0_PPE                             ,
+       RULL(0x10C010240), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PMCRS0_PPE                             ,
+       RULL(0x10C020240), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PMCRS0_PPE                             ,
+       RULL(0x10D010240), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PMCRS0_PPE                             ,
+       RULL(0x10D020240), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PMCRS0_PPE                            ,
+       RULL(0x10E010240), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PMCRS0_PPE                            ,
+       RULL(0x10E020240), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PMCRS1_PPE                             ,
+       RULL(0x109010260), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PMCRS1_PPE                             ,
+       RULL(0x109020260), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PMCRS1_PPE                             ,
+       RULL(0x10A010260), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PMCRS1_PPE                             ,
+       RULL(0x10A020260), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PMCRS1_PPE                             ,
+       RULL(0x10B010260), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PMCRS1_PPE                             ,
+       RULL(0x10B020260), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PMCRS1_PPE                             ,
+       RULL(0x10C010260), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PMCRS1_PPE                             ,
+       RULL(0x10C020260), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PMCRS1_PPE                             ,
+       RULL(0x10D010260), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PMCRS1_PPE                             ,
+       RULL(0x10D020260), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PMCRS1_PPE                            ,
+       RULL(0x10E010260), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PMCRS1_PPE                            ,
+       RULL(0x10E020260), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PMSRS0_PPE                             ,
+       RULL(0x109010200), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PMSRS0_PPE                             ,
+       RULL(0x109020200), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PMSRS0_PPE                             ,
+       RULL(0x10A010200), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PMSRS0_PPE                             ,
+       RULL(0x10A020200), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PMSRS0_PPE                             ,
+       RULL(0x10B010200), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PMSRS0_PPE                             ,
+       RULL(0x10B020200), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PMSRS0_PPE                             ,
+       RULL(0x10C010200), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PMSRS0_PPE                             ,
+       RULL(0x10C020200), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PMSRS0_PPE                             ,
+       RULL(0x10D010200), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PMSRS0_PPE                             ,
+       RULL(0x10D020200), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PMSRS0_PPE                            ,
+       RULL(0x10E010200), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PMSRS0_PPE                            ,
+       RULL(0x10E020200), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PMSRS1_PPE                             ,
+       RULL(0x109010220), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PMSRS1_PPE                             ,
+       RULL(0x109020220), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PMSRS1_PPE                             ,
+       RULL(0x10A010220), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PMSRS1_PPE                             ,
+       RULL(0x10A020220), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PMSRS1_PPE                             ,
+       RULL(0x10B010220), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PMSRS1_PPE                             ,
+       RULL(0x10B020220), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PMSRS1_PPE                             ,
+       RULL(0x10C010220), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PMSRS1_PPE                             ,
+       RULL(0x10C020220), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PMSRS1_PPE                             ,
+       RULL(0x10D010220), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PMSRS1_PPE                             ,
+       RULL(0x10D020220), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PMSRS1_PPE                            ,
+       RULL(0x10E010220), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PMSRS1_PPE                            ,
+       RULL(0x10E020220), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PSCRS00_PPE                            ,
+       RULL(0x109010300), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PSCRS00_PPE                            ,
+       RULL(0x109020300), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PSCRS00_PPE                            ,
+       RULL(0x10A010300), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PSCRS00_PPE                            ,
+       RULL(0x10A020300), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PSCRS00_PPE                            ,
+       RULL(0x10B010300), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PSCRS00_PPE                            ,
+       RULL(0x10B020300), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PSCRS00_PPE                            ,
+       RULL(0x10C010300), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PSCRS00_PPE                            ,
+       RULL(0x10C020300), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PSCRS00_PPE                            ,
+       RULL(0x10D010300), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PSCRS00_PPE                            ,
+       RULL(0x10D020300), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PSCRS00_PPE                           ,
+       RULL(0x10E010300), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PSCRS00_PPE                           ,
+       RULL(0x10E020300), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PSCRS01_PPE                            ,
+       RULL(0x109010320), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PSCRS01_PPE                            ,
+       RULL(0x109020320), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PSCRS01_PPE                            ,
+       RULL(0x10A010320), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PSCRS01_PPE                            ,
+       RULL(0x10A020320), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PSCRS01_PPE                            ,
+       RULL(0x10B010320), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PSCRS01_PPE                            ,
+       RULL(0x10B020320), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PSCRS01_PPE                            ,
+       RULL(0x10C010320), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PSCRS01_PPE                            ,
+       RULL(0x10C020320), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PSCRS01_PPE                            ,
+       RULL(0x10D010320), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PSCRS01_PPE                            ,
+       RULL(0x10D020320), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PSCRS01_PPE                           ,
+       RULL(0x10E010320), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PSCRS01_PPE                           ,
+       RULL(0x10E020320), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PSCRS02_PPE                            ,
+       RULL(0x109010340), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PSCRS02_PPE                            ,
+       RULL(0x109020340), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PSCRS02_PPE                            ,
+       RULL(0x10A010340), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PSCRS02_PPE                            ,
+       RULL(0x10A020340), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PSCRS02_PPE                            ,
+       RULL(0x10B010340), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PSCRS02_PPE                            ,
+       RULL(0x10B020340), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PSCRS02_PPE                            ,
+       RULL(0x10C010340), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PSCRS02_PPE                            ,
+       RULL(0x10C020340), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PSCRS02_PPE                            ,
+       RULL(0x10D010340), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PSCRS02_PPE                            ,
+       RULL(0x10D020340), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PSCRS02_PPE                           ,
+       RULL(0x10E010340), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PSCRS02_PPE                           ,
+       RULL(0x10E020340), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PSCRS03_PPE                            ,
+       RULL(0x109010360), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PSCRS03_PPE                            ,
+       RULL(0x109020360), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PSCRS03_PPE                            ,
+       RULL(0x10A010360), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PSCRS03_PPE                            ,
+       RULL(0x10A020360), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PSCRS03_PPE                            ,
+       RULL(0x10B010360), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PSCRS03_PPE                            ,
+       RULL(0x10B020360), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PSCRS03_PPE                            ,
+       RULL(0x10C010360), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PSCRS03_PPE                            ,
+       RULL(0x10C020360), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PSCRS03_PPE                            ,
+       RULL(0x10D010360), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PSCRS03_PPE                            ,
+       RULL(0x10D020360), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PSCRS03_PPE                           ,
+       RULL(0x10E010360), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PSCRS03_PPE                           ,
+       RULL(0x10E020360), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PSCRS10_PPE                            ,
+       RULL(0x109010380), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PSCRS10_PPE                            ,
+       RULL(0x109020380), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PSCRS10_PPE                            ,
+       RULL(0x10A010380), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PSCRS10_PPE                            ,
+       RULL(0x10A020380), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PSCRS10_PPE                            ,
+       RULL(0x10B010380), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PSCRS10_PPE                            ,
+       RULL(0x10B020380), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PSCRS10_PPE                            ,
+       RULL(0x10C010380), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PSCRS10_PPE                            ,
+       RULL(0x10C020380), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PSCRS10_PPE                            ,
+       RULL(0x10D010380), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PSCRS10_PPE                            ,
+       RULL(0x10D020380), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PSCRS10_PPE                           ,
+       RULL(0x10E010380), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PSCRS10_PPE                           ,
+       RULL(0x10E020380), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PSCRS11_PPE                            ,
+       RULL(0x1090103A0), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PSCRS11_PPE                            ,
+       RULL(0x1090203A0), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PSCRS11_PPE                            ,
+       RULL(0x10A0103A0), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PSCRS11_PPE                            ,
+       RULL(0x10A0203A0), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PSCRS11_PPE                            ,
+       RULL(0x10B0103A0), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PSCRS11_PPE                            ,
+       RULL(0x10B0203A0), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PSCRS11_PPE                            ,
+       RULL(0x10C0103A0), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PSCRS11_PPE                            ,
+       RULL(0x10C0203A0), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PSCRS11_PPE                            ,
+       RULL(0x10D0103A0), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PSCRS11_PPE                            ,
+       RULL(0x10D0203A0), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PSCRS11_PPE                           ,
+       RULL(0x10E0103A0), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PSCRS11_PPE                           ,
+       RULL(0x10E0203A0), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PSCRS12_PPE                            ,
+       RULL(0x1090103C0), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PSCRS12_PPE                            ,
+       RULL(0x1090203C0), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PSCRS12_PPE                            ,
+       RULL(0x10A0103C0), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PSCRS12_PPE                            ,
+       RULL(0x10A0203C0), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PSCRS12_PPE                            ,
+       RULL(0x10B0103C0), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PSCRS12_PPE                            ,
+       RULL(0x10B0203C0), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PSCRS12_PPE                            ,
+       RULL(0x10C0103C0), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PSCRS12_PPE                            ,
+       RULL(0x10C0203C0), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PSCRS12_PPE                            ,
+       RULL(0x10D0103C0), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PSCRS12_PPE                            ,
+       RULL(0x10D0203C0), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PSCRS12_PPE                           ,
+       RULL(0x10E0103C0), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PSCRS12_PPE                           ,
+       RULL(0x10E0203C0), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PSCRS13_PPE                            ,
+       RULL(0x1090103E0), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PSCRS13_PPE                            ,
+       RULL(0x1090203E0), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PSCRS13_PPE                            ,
+       RULL(0x10A0103E0), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PSCRS13_PPE                            ,
+       RULL(0x10A0203E0), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PSCRS13_PPE                            ,
+       RULL(0x10B0103E0), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PSCRS13_PPE                            ,
+       RULL(0x10B0203E0), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PSCRS13_PPE                            ,
+       RULL(0x10C0103E0), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PSCRS13_PPE                            ,
+       RULL(0x10C0203E0), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PSCRS13_PPE                            ,
+       RULL(0x10D0103E0), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PSCRS13_PPE                            ,
+       RULL(0x10D0203E0), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PSCRS13_PPE                           ,
+       RULL(0x10E0103E0), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PSCRS13_PPE                           ,
+       RULL(0x10E0203E0), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_QFMR_PPE                               ,
+       RULL(0x109010140), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_QFMR_PPE                               ,
+       RULL(0x109020140), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_QFMR_PPE                               ,
+       RULL(0x10A010140), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_QFMR_PPE                               ,
+       RULL(0x10A020140), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_QFMR_PPE                               ,
+       RULL(0x10B010140), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_QFMR_PPE                               ,
+       RULL(0x10B020140), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_QFMR_PPE                               ,
+       RULL(0x10C010140), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_QFMR_PPE                               ,
+       RULL(0x10C020140), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_QFMR_PPE                               ,
+       RULL(0x10D010140), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_QFMR_PPE                               ,
+       RULL(0x10D020140), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_QFMR_PPE                              ,
+       RULL(0x10E010140), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_QFMR_PPE                              ,
+       RULL(0x10E020140), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_SICR_PPE                               ,
+       RULL(0x109010500), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME0_CME_SCOM_SICR_PPE1                              ,
+       RULL(0x109010518), SH_UNT_PU_CME0  , SH_ACS_PPE1      );
+REG64( PU_CME0_CME_SCOM_SICR_PPE2                              ,
+       RULL(0x109010510), SH_UNT_PU_CME0  , SH_ACS_PPE2      );
+REG64( PU_CME1_CME_SCOM_SICR_PPE                               ,
+       RULL(0x109020500), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_SICR_PPE1                              ,
+       RULL(0x109020518), SH_UNT_PU_CME1  , SH_ACS_PPE1      );
+REG64( PU_CME1_CME_SCOM_SICR_PPE2                              ,
+       RULL(0x109020510), SH_UNT_PU_CME1  , SH_ACS_PPE2      );
+REG64( PU_CME2_CME_SCOM_SICR_PPE                               ,
+       RULL(0x10A010500), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_SICR_PPE1                              ,
+       RULL(0x10A010518), SH_UNT_PU_CME2  , SH_ACS_PPE1      );
+REG64( PU_CME2_CME_SCOM_SICR_PPE2                              ,
+       RULL(0x10A010510), SH_UNT_PU_CME2  , SH_ACS_PPE2      );
+REG64( PU_CME3_CME_SCOM_SICR_PPE                               ,
+       RULL(0x10A020500), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_SICR_PPE1                              ,
+       RULL(0x10A020518), SH_UNT_PU_CME3  , SH_ACS_PPE1      );
+REG64( PU_CME3_CME_SCOM_SICR_PPE2                              ,
+       RULL(0x10A020510), SH_UNT_PU_CME3  , SH_ACS_PPE2      );
+REG64( PU_CME4_CME_SCOM_SICR_PPE                               ,
+       RULL(0x10B010500), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_SICR_PPE1                              ,
+       RULL(0x10B010518), SH_UNT_PU_CME4  , SH_ACS_PPE1      );
+REG64( PU_CME4_CME_SCOM_SICR_PPE2                              ,
+       RULL(0x10B010510), SH_UNT_PU_CME4  , SH_ACS_PPE2      );
+REG64( PU_CME5_CME_SCOM_SICR_PPE                               ,
+       RULL(0x10B020500), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_SICR_PPE1                              ,
+       RULL(0x10B020518), SH_UNT_PU_CME5  , SH_ACS_PPE1      );
+REG64( PU_CME5_CME_SCOM_SICR_PPE2                              ,
+       RULL(0x10B020510), SH_UNT_PU_CME5  , SH_ACS_PPE2      );
+REG64( PU_CME6_CME_SCOM_SICR_PPE                               ,
+       RULL(0x10C010500), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_SICR_PPE1                              ,
+       RULL(0x10C010518), SH_UNT_PU_CME6  , SH_ACS_PPE1      );
+REG64( PU_CME6_CME_SCOM_SICR_PPE2                              ,
+       RULL(0x10C010510), SH_UNT_PU_CME6  , SH_ACS_PPE2      );
+REG64( PU_CME7_CME_SCOM_SICR_PPE                               ,
+       RULL(0x10C020500), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_SICR_PPE1                              ,
+       RULL(0x10C020518), SH_UNT_PU_CME7  , SH_ACS_PPE1      );
+REG64( PU_CME7_CME_SCOM_SICR_PPE2                              ,
+       RULL(0x10C020510), SH_UNT_PU_CME7  , SH_ACS_PPE2      );
+REG64( PU_CME8_CME_SCOM_SICR_PPE                               ,
+       RULL(0x10D010500), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_SICR_PPE1                              ,
+       RULL(0x10D010518), SH_UNT_PU_CME8  , SH_ACS_PPE1      );
+REG64( PU_CME8_CME_SCOM_SICR_PPE2                              ,
+       RULL(0x10D010510), SH_UNT_PU_CME8  , SH_ACS_PPE2      );
+REG64( PU_CME9_CME_SCOM_SICR_PPE                               ,
+       RULL(0x10D020500), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_SICR_PPE1                              ,
+       RULL(0x10D020518), SH_UNT_PU_CME9  , SH_ACS_PPE1      );
+REG64( PU_CME9_CME_SCOM_SICR_PPE2                              ,
+       RULL(0x10D020510), SH_UNT_PU_CME9  , SH_ACS_PPE2      );
+REG64( PU_CME10_CME_SCOM_SICR_PPE                              ,
+       RULL(0x10E010500), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_SICR_PPE1                             ,
+       RULL(0x10E010518), SH_UNT_PU_CME10 , SH_ACS_PPE1      );
+REG64( PU_CME10_CME_SCOM_SICR_PPE2                             ,
+       RULL(0x10E010510), SH_UNT_PU_CME10 , SH_ACS_PPE2      );
+REG64( PU_CME11_CME_SCOM_SICR_PPE                              ,
+       RULL(0x10E020500), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_SICR_PPE1                             ,
+       RULL(0x10E020518), SH_UNT_PU_CME11 , SH_ACS_PPE1      );
+REG64( PU_CME11_CME_SCOM_SICR_PPE2                             ,
+       RULL(0x10E020510), SH_UNT_PU_CME11 , SH_ACS_PPE2      );
+
+REG64( PU_CME0_CME_SCOM_SRTCH0_PPE                             ,
+       RULL(0x109010420), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_SRTCH0_PPE                             ,
+       RULL(0x109020420), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_SRTCH0_PPE                             ,
+       RULL(0x10A010420), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_SRTCH0_PPE                             ,
+       RULL(0x10A020420), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_SRTCH0_PPE                             ,
+       RULL(0x10B010420), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_SRTCH0_PPE                             ,
+       RULL(0x10B020420), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_SRTCH0_PPE                             ,
+       RULL(0x10C010420), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_SRTCH0_PPE                             ,
+       RULL(0x10C020420), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_SRTCH0_PPE                             ,
+       RULL(0x10D010420), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_SRTCH0_PPE                             ,
+       RULL(0x10D020420), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_SRTCH0_PPE                            ,
+       RULL(0x10E010420), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_SRTCH0_PPE                            ,
+       RULL(0x10E020420), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_SRTCH1_PPE                             ,
+       RULL(0x109010440), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_SRTCH1_PPE                             ,
+       RULL(0x109020440), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_SRTCH1_PPE                             ,
+       RULL(0x10A010440), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_SRTCH1_PPE                             ,
+       RULL(0x10A020440), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_SRTCH1_PPE                             ,
+       RULL(0x10B010440), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_SRTCH1_PPE                             ,
+       RULL(0x10B020440), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_SRTCH1_PPE                             ,
+       RULL(0x10C010440), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_SRTCH1_PPE                             ,
+       RULL(0x10C020440), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_SRTCH1_PPE                             ,
+       RULL(0x10D010440), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_SRTCH1_PPE                             ,
+       RULL(0x10D020440), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_SRTCH1_PPE                            ,
+       RULL(0x10E010440), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_SRTCH1_PPE                            ,
+       RULL(0x10E020440), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_VDSR_PPE                               ,
+       RULL(0x109010640), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_VDSR_PPE                               ,
+       RULL(0x109020640), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_VDSR_PPE                               ,
+       RULL(0x10A010640), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_VDSR_PPE                               ,
+       RULL(0x10A020640), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_VDSR_PPE                               ,
+       RULL(0x10B010640), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_VDSR_PPE                               ,
+       RULL(0x10B020640), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_VDSR_PPE                               ,
+       RULL(0x10C010640), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_VDSR_PPE                               ,
+       RULL(0x10C020640), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_VDSR_PPE                               ,
+       RULL(0x10D010640), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_VDSR_PPE                               ,
+       RULL(0x10D020640), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_VDSR_PPE                              ,
+       RULL(0x10E010640), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_VDSR_PPE                              ,
+       RULL(0x10E020640), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_VTSR0_PPE                              ,
+       RULL(0x109010600), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_VTSR0_PPE                              ,
+       RULL(0x109020600), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_VTSR0_PPE                              ,
+       RULL(0x10A010600), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_VTSR0_PPE                              ,
+       RULL(0x10A020600), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_VTSR0_PPE                              ,
+       RULL(0x10B010600), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_VTSR0_PPE                              ,
+       RULL(0x10B020600), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_VTSR0_PPE                              ,
+       RULL(0x10C010600), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_VTSR0_PPE                              ,
+       RULL(0x10C020600), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_VTSR0_PPE                              ,
+       RULL(0x10D010600), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_VTSR0_PPE                              ,
+       RULL(0x10D020600), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_VTSR0_PPE                             ,
+       RULL(0x10E010600), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_VTSR0_PPE                             ,
+       RULL(0x10E020600), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_VTSR1_PPE                              ,
+       RULL(0x109010620), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_VTSR1_PPE                              ,
+       RULL(0x109020620), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_VTSR1_PPE                              ,
+       RULL(0x10A010620), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_VTSR1_PPE                              ,
+       RULL(0x10A020620), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_VTSR1_PPE                              ,
+       RULL(0x10B010620), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_VTSR1_PPE                              ,
+       RULL(0x10B020620), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_VTSR1_PPE                              ,
+       RULL(0x10C010620), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_VTSR1_PPE                              ,
+       RULL(0x10C020620), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_VTSR1_PPE                              ,
+       RULL(0x10D010620), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_VTSR1_PPE                              ,
+       RULL(0x10D020620), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_VTSR1_PPE                             ,
+       RULL(0x10E010620), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_VTSR1_PPE                             ,
+       RULL(0x10E020620), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_XIPCBMD0_PPE                           ,
+       RULL(0x109010580), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_XIPCBMD0_PPE                           ,
+       RULL(0x109020580), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_XIPCBMD0_PPE                           ,
+       RULL(0x10A010580), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_XIPCBMD0_PPE                           ,
+       RULL(0x10A020580), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_XIPCBMD0_PPE                           ,
+       RULL(0x10B010580), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_XIPCBMD0_PPE                           ,
+       RULL(0x10B020580), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_XIPCBMD0_PPE                           ,
+       RULL(0x10C010580), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_XIPCBMD0_PPE                           ,
+       RULL(0x10C020580), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_XIPCBMD0_PPE                           ,
+       RULL(0x10D010580), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_XIPCBMD0_PPE                           ,
+       RULL(0x10D020580), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_XIPCBMD0_PPE                          ,
+       RULL(0x10E010580), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_XIPCBMD0_PPE                          ,
+       RULL(0x10E020580), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_XIPCBMD1_PPE                           ,
+       RULL(0x1090105A0), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_XIPCBMD1_PPE                           ,
+       RULL(0x1090205A0), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_XIPCBMD1_PPE                           ,
+       RULL(0x10A0105A0), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_XIPCBMD1_PPE                           ,
+       RULL(0x10A0205A0), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_XIPCBMD1_PPE                           ,
+       RULL(0x10B0105A0), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_XIPCBMD1_PPE                           ,
+       RULL(0x10B0205A0), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_XIPCBMD1_PPE                           ,
+       RULL(0x10C0105A0), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_XIPCBMD1_PPE                           ,
+       RULL(0x10C0205A0), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_XIPCBMD1_PPE                           ,
+       RULL(0x10D0105A0), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_XIPCBMD1_PPE                           ,
+       RULL(0x10D0205A0), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_XIPCBMD1_PPE                          ,
+       RULL(0x10E0105A0), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_XIPCBMD1_PPE                          ,
+       RULL(0x10E0205A0), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_XIPCBMI0_PPE                           ,
+       RULL(0x1090105C0), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_XIPCBMI0_PPE                           ,
+       RULL(0x1090205C0), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_XIPCBMI0_PPE                           ,
+       RULL(0x10A0105C0), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_XIPCBMI0_PPE                           ,
+       RULL(0x10A0205C0), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_XIPCBMI0_PPE                           ,
+       RULL(0x10B0105C0), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_XIPCBMI0_PPE                           ,
+       RULL(0x10B0205C0), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_XIPCBMI0_PPE                           ,
+       RULL(0x10C0105C0), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_XIPCBMI0_PPE                           ,
+       RULL(0x10C0205C0), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_XIPCBMI0_PPE                           ,
+       RULL(0x10D0105C0), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_XIPCBMI0_PPE                           ,
+       RULL(0x10D0205C0), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_XIPCBMI0_PPE                          ,
+       RULL(0x10E0105C0), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_XIPCBMI0_PPE                          ,
+       RULL(0x10E0205C0), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_XIPCBMI1_PPE                           ,
+       RULL(0x1090105E0), SH_UNT_PU_CME0  , SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_XIPCBMI1_PPE                           ,
+       RULL(0x1090205E0), SH_UNT_PU_CME1  , SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_XIPCBMI1_PPE                           ,
+       RULL(0x10A0105E0), SH_UNT_PU_CME2  , SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_XIPCBMI1_PPE                           ,
+       RULL(0x10A0205E0), SH_UNT_PU_CME3  , SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_XIPCBMI1_PPE                           ,
+       RULL(0x10B0105E0), SH_UNT_PU_CME4  , SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_XIPCBMI1_PPE                           ,
+       RULL(0x10B0205E0), SH_UNT_PU_CME5  , SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_XIPCBMI1_PPE                           ,
+       RULL(0x10C0105E0), SH_UNT_PU_CME6  , SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_XIPCBMI1_PPE                           ,
+       RULL(0x10C0205E0), SH_UNT_PU_CME7  , SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_XIPCBMI1_PPE                           ,
+       RULL(0x10D0105E0), SH_UNT_PU_CME8  , SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_XIPCBMI1_PPE                           ,
+       RULL(0x10D0205E0), SH_UNT_PU_CME9  , SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_XIPCBMI1_PPE                          ,
+       RULL(0x10E0105E0), SH_UNT_PU_CME10 , SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_XIPCBMI1_PPE                          ,
+       RULL(0x10E0205E0), SH_UNT_PU_CME11 , SH_ACS_PPE       );
+
+REG64( PU_COMMAND_REGISTER                                     ,
+       RULL(0x00010000), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_COMMAND_REGISTER_B                                   ,
+       RULL(0x000A0005), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_COMMAND_REGISTER_C                                   ,
+       RULL(0x000A1005), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_COMMAND_REGISTER_D                                   ,
+       RULL(0x000A2005), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_COMMAND_REGISTER_E                                   ,
+       RULL(0x000A3005), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_CONFIG0                                     ,
+       RULL(0x05011080), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CONFIG0                                     ,
+       RULL(0x05011180), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CONFIG0                                     ,
+       RULL(0x05011280), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_CONFIG0                                     ,
+       RULL(0x05011000), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CONFIG0                                     ,
+       RULL(0x05011020), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CONFIG0                                     ,
+       RULL(0x05011040), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CONFIG0                                     ,
+       RULL(0x05011060), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CONFIG0                                     ,
+       RULL(0x05011100), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CONFIG0                                     ,
+       RULL(0x05011120), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CONFIG0                                     ,
+       RULL(0x05011140), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CONFIG0                                     ,
+       RULL(0x05011160), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CONFIG0                                     ,
+       RULL(0x05011200), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CONFIG0                                     ,
+       RULL(0x05011220), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CONFIG0                                     ,
+       RULL(0x05011240), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CONFIG0                                     ,
+       RULL(0x05011260), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_CONFIG1                                     ,
+       RULL(0x05011081), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU0_DAT_CONFIG1                                     ,
+       RULL(0x050110B0), SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CONFIG1                                     ,
+       RULL(0x05011181), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU1_DAT_CONFIG1                                     ,
+       RULL(0x050111B0), SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM      );
+REG64( PU_NPU2_DAT_CONFIG1                                     ,
+       RULL(0x050112B0), SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CONFIG1                                     ,
+       RULL(0x05011281), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU0_NTL0_CONFIG1                                    ,
+       RULL(0x050110D0), SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU0_NTL1_CONFIG1                                    ,
+       RULL(0x050110F0), SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_CONFIG1                                     ,
+       RULL(0x05011001), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CONFIG1                                     ,
+       RULL(0x05011021), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CONFIG1                                     ,
+       RULL(0x05011041), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CONFIG1                                     ,
+       RULL(0x05011061), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_NTL0_CONFIG1                                    ,
+       RULL(0x050111D0), SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU1_NTL1_CONFIG1                                    ,
+       RULL(0x050111F0), SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CONFIG1                                     ,
+       RULL(0x05011101), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CONFIG1                                     ,
+       RULL(0x05011121), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CONFIG1                                     ,
+       RULL(0x05011141), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CONFIG1                                     ,
+       RULL(0x05011161), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_CONFIG1                                    ,
+       RULL(0x050112D0), SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_CONFIG1                                    ,
+       RULL(0x050112F0), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CONFIG1                                     ,
+       RULL(0x05011201), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CONFIG1                                     ,
+       RULL(0x05011221), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CONFIG1                                     ,
+       RULL(0x05011241), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CONFIG1                                     ,
+       RULL(0x05011261), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_CONFIG2                                     ,
+       RULL(0x05011082), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CONFIG2                                     ,
+       RULL(0x05011182), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CONFIG2                                     ,
+       RULL(0x05011282), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU0_NTL0_CONFIG2                                    ,
+       RULL(0x050110C0), SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU0_NTL1_CONFIG2                                    ,
+       RULL(0x050110E0), SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_CONFIG2                                     ,
+       RULL(0x05011002), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CONFIG2                                     ,
+       RULL(0x05011022), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CONFIG2                                     ,
+       RULL(0x05011042), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CONFIG2                                     ,
+       RULL(0x05011062), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_NTL0_CONFIG2                                    ,
+       RULL(0x050111C0), SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU1_NTL1_CONFIG2                                    ,
+       RULL(0x050111E0), SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CONFIG2                                     ,
+       RULL(0x05011102), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CONFIG2                                     ,
+       RULL(0x05011122), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CONFIG2                                     ,
+       RULL(0x05011142), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CONFIG2                                     ,
+       RULL(0x05011162), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_CONFIG2                                    ,
+       RULL(0x050112C0), SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_CONFIG2                                    ,
+       RULL(0x050112E0), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CONFIG2                                     ,
+       RULL(0x05011202), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CONFIG2                                     ,
+       RULL(0x05011222), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CONFIG2                                     ,
+       RULL(0x05011242), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CONFIG2                                     ,
+       RULL(0x05011262), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_CONFIG3                                     ,
+       RULL(0x05011083), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CONFIG3                                     ,
+       RULL(0x05011183), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CONFIG3                                     ,
+       RULL(0x05011283), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU0_NTL0_CONFIG3                                    ,
+       RULL(0x050110C1), SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU0_NTL1_CONFIG3                                    ,
+       RULL(0x050110E1), SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_CONFIG3                                     ,
+       RULL(0x05011003), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CONFIG3                                     ,
+       RULL(0x05011023), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CONFIG3                                     ,
+       RULL(0x05011043), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CONFIG3                                     ,
+       RULL(0x05011063), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_NTL0_CONFIG3                                    ,
+       RULL(0x050111C1), SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU1_NTL1_CONFIG3                                    ,
+       RULL(0x050111E1), SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CONFIG3                                     ,
+       RULL(0x05011103), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CONFIG3                                     ,
+       RULL(0x05011123), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CONFIG3                                     ,
+       RULL(0x05011143), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CONFIG3                                     ,
+       RULL(0x05011163), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_CONFIG3                                    ,
+       RULL(0x050112C1), SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_CONFIG3                                    ,
+       RULL(0x050112E1), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CONFIG3                                     ,
+       RULL(0x05011203), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CONFIG3                                     ,
+       RULL(0x05011223), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CONFIG3                                     ,
+       RULL(0x05011243), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CONFIG3                                     ,
+       RULL(0x05011263), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PU_CONTROL_REGISTER_B                                   ,
+       RULL(0x000A0000), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_CONTROL_REGISTER_C                                   ,
+       RULL(0x000A1000), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_CONTROL_REGISTER_D                                   ,
+       RULL(0x000A2000), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_CONTROL_REGISTER_E                                   ,
+       RULL(0x000A3000), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PEC_0_STACK0_CQSTAT_REG                                 ,
+       RULL(0x04010C4C), SH_UNT_PEC_0_STACK0, SH_ACS_SCOM_RO   );
+REG64( PEC_0_STACK1_CQSTAT_REG                                 ,
+       RULL(0x04010C8C), SH_UNT_PEC_0_STACK1, SH_ACS_SCOM_RO   );
+REG64( PEC_0_STACK2_CQSTAT_REG                                 ,
+       RULL(0x04010CCC), SH_UNT_PEC_0_STACK2, SH_ACS_SCOM_RO   );
+REG64( PEC_1_STACK0_CQSTAT_REG                                 ,
+       RULL(0x0401104C), SH_UNT_PEC_1_STACK0, SH_ACS_SCOM_RO   );
+REG64( PEC_1_STACK1_CQSTAT_REG                                 ,
+       RULL(0x0401108C), SH_UNT_PEC_1_STACK1, SH_ACS_SCOM_RO   );
+REG64( PEC_1_STACK2_CQSTAT_REG                                 ,
+       RULL(0x040110CC), SH_UNT_PEC_1_STACK2, SH_ACS_SCOM_RO   );
+REG64( PEC_2_STACK0_CQSTAT_REG                                 ,
+       RULL(0x0401144C), SH_UNT_PEC_2_STACK0, SH_ACS_SCOM_RO   );
+REG64( PEC_2_STACK1_CQSTAT_REG                                 ,
+       RULL(0x0401148C), SH_UNT_PEC_2_STACK1, SH_ACS_SCOM_RO   );
+REG64( PEC_2_STACK2_CQSTAT_REG                                 ,
+       RULL(0x040114CC), SH_UNT_PEC_2_STACK2, SH_ACS_SCOM_RO   );
+REG64( PEC_STACK0_CQSTAT_REG                                   ,
+       RULL(0x04010C4C), SH_UNT_PEC_STACK0, SH_ACS_SCOM_RO   );
+REG64( PEC_STACK1_CQSTAT_REG                                   ,
+       RULL(0x04010C8C), SH_UNT_PEC_STACK1, SH_ACS_SCOM_RO   );
+REG64( PEC_STACK2_CQSTAT_REG                                   ,
+       RULL(0x04010CCC), SH_UNT_PEC_STACK2, SH_ACS_SCOM_RO   );
+
+REG64( PU_PIB2OPB0_CRSIC                                       ,
+       RULL(0x00020005), SH_UNT_PU_PIB2OPB0, SH_ACS_SCOM_WCLEAR );
+REG64( PU_PIB2OPB1_CRSIC                                       ,
+       RULL(0x00020015), SH_UNT_PU_PIB2OPB1, SH_ACS_SCOM_WCLEAR );
+
+REG64( PU_PIB2OPB0_CRSIM                                       ,
+       RULL(0x00020006), SH_UNT_PU_PIB2OPB0, SH_ACS_SCOM_RW   );
+REG64( PU_PIB2OPB1_CRSIM                                       ,
+       RULL(0x00020016), SH_UNT_PU_PIB2OPB1, SH_ACS_SCOM_RW   );
+
+REG64( PU_PIB2OPB0_CRSIS                                       ,
+       RULL(0x00020007), SH_UNT_PU_PIB2OPB0, SH_ACS_SCOM_RO   );
+REG64( PU_PIB2OPB1_CRSIS                                       ,
+       RULL(0x00020017), SH_UNT_PU_PIB2OPB1, SH_ACS_SCOM_RO   );
+
+REG64( PU_NPU0_CTL_CTLSM_HOLD0                                 ,
+       RULL(0x05011097), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CTLSM_HOLD0                                 ,
+       RULL(0x05011197), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CTLSM_HOLD0                                 ,
+       RULL(0x05011297), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_CTLSM_HOLD1                                 ,
+       RULL(0x05011098), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CTLSM_HOLD1                                 ,
+       RULL(0x05011198), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CTLSM_HOLD1                                 ,
+       RULL(0x05011298), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_CTLSM_MASK0                                 ,
+       RULL(0x05011099), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CTLSM_MASK0                                 ,
+       RULL(0x05011199), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CTLSM_MASK0                                 ,
+       RULL(0x05011299), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_CTLSM_MASK1                                 ,
+       RULL(0x0501109A), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CTLSM_MASK1                                 ,
+       RULL(0x0501119A), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CTLSM_MASK1                                 ,
+       RULL(0x0501129A), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_CTL_HOLD                                    ,
+       RULL(0x0501109B), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CTL_HOLD                                    ,
+       RULL(0x0501119B), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CTL_HOLD                                    ,
+       RULL(0x0501129B), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_CTL_MASK                                    ,
+       RULL(0x0501109C), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CTL_MASK                                    ,
+       RULL(0x0501119C), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CTL_MASK                                    ,
+       RULL(0x0501129C), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM      );
+
+REG64( PU_DATA0TO7_REGISTER_B                                  ,
+       RULL(0x000A0003), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_DATA0TO7_REGISTER_C                                  ,
+       RULL(0x000A1003), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_DATA0TO7_REGISTER_D                                  ,
+       RULL(0x000A2003), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_DATA0TO7_REGISTER_E                                  ,
+       RULL(0x000A3003), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_DATA8TO15_REGISTER_B                                 ,
+       RULL(0x000A0001), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_DATA8TO15_REGISTER_C                                 ,
+       RULL(0x000A1001), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_DATA8TO15_REGISTER_D                                 ,
+       RULL(0x000A2001), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_DATA8TO15_REGISTER_E                                 ,
+       RULL(0x000A3001), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_DATATAG_0_HASH_FUNCTION_REG                          ,
+       RULL(0x0201114C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_DATATAG_1_HASH_FUNCTION_REG                          ,
+       RULL(0x0201114D), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_DATATAG_2_HASH_FUNCTION_REG                          ,
+       RULL(0x0201114E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_DATATAG_3_HASH_FUNCTION_REG                          ,
+       RULL(0x0201114F), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_DATATAG_4_HASH_FUNCTION_REG                          ,
+       RULL(0x02011150), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_DATATAG_5_HASH_FUNCTION_REG                          ,
+       RULL(0x02011151), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_DATA_REGISTER                                        ,
+       RULL(0x00010003), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NPU_DAT_DA_ADDR                                      ,
+       RULL(0x050113BE), SH_UNT_PU_NPU_DAT, SH_ACS_SCOM      );
+
+REG64( PU_NPU_DAT_DA_DATA                                      ,
+       RULL(0x050113BF), SH_UNT_PU_NPU_DAT, SH_ACS_SCOM_RW   );
+
+REG64( PU_NPU0_CTL_DEBUG0_CONFIG                               ,
+       RULL(0x05011088), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU0_DAT_DEBUG0_CONFIG                               ,
+       RULL(0x050110B4), SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_DEBUG0_CONFIG                               ,
+       RULL(0x05011188), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU1_DAT_DEBUG0_CONFIG                               ,
+       RULL(0x050111B4), SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM      );
+REG64( PU_NPU2_DAT_DEBUG0_CONFIG                               ,
+       RULL(0x050112B4), SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_DEBUG0_CONFIG                               ,
+       RULL(0x05011288), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_DEBUG0_CONFIG                               ,
+       RULL(0x05011008), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_DEBUG0_CONFIG                               ,
+       RULL(0x05011028), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_DEBUG0_CONFIG                               ,
+       RULL(0x05011048), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_DEBUG0_CONFIG                               ,
+       RULL(0x05011068), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_DEBUG0_CONFIG                               ,
+       RULL(0x05011108), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_DEBUG0_CONFIG                               ,
+       RULL(0x05011128), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_DEBUG0_CONFIG                               ,
+       RULL(0x05011148), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_DEBUG0_CONFIG                               ,
+       RULL(0x05011168), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_DEBUG0_CONFIG                               ,
+       RULL(0x05011208), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_DEBUG0_CONFIG                               ,
+       RULL(0x05011228), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_DEBUG0_CONFIG                               ,
+       RULL(0x05011248), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_DEBUG0_CONFIG                               ,
+       RULL(0x05011268), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU_SM2_DEBUG0_CONFIG                                ,
+       RULL(0x05011346), SH_UNT_PU_NPU_SM2, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_DEBUG1_CONFIG                               ,
+       RULL(0x05011089), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU0_DAT_DEBUG1_CONFIG                               ,
+       RULL(0x050110B5), SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_DEBUG1_CONFIG                               ,
+       RULL(0x05011189), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU1_DAT_DEBUG1_CONFIG                               ,
+       RULL(0x050111B5), SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM      );
+REG64( PU_NPU2_DAT_DEBUG1_CONFIG                               ,
+       RULL(0x050112B5), SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_DEBUG1_CONFIG                               ,
+       RULL(0x05011289), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_DEBUG1_CONFIG                               ,
+       RULL(0x05011009), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_DEBUG1_CONFIG                               ,
+       RULL(0x05011029), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_DEBUG1_CONFIG                               ,
+       RULL(0x05011049), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_DEBUG1_CONFIG                               ,
+       RULL(0x05011069), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_DEBUG1_CONFIG                               ,
+       RULL(0x05011109), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_DEBUG1_CONFIG                               ,
+       RULL(0x05011129), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_DEBUG1_CONFIG                               ,
+       RULL(0x05011149), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_DEBUG1_CONFIG                               ,
+       RULL(0x05011169), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_DEBUG1_CONFIG                               ,
+       RULL(0x05011209), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_DEBUG1_CONFIG                               ,
+       RULL(0x05011229), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_DEBUG1_CONFIG                               ,
+       RULL(0x05011249), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_DEBUG1_CONFIG                               ,
+       RULL(0x05011269), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU_SM2_DEBUG1_CONFIG                                ,
+       RULL(0x05011347), SH_UNT_PU_NPU_SM2, SH_ACS_SCOM      );
+
+REG64( PU_NPU_CTL_DEBUG_CONFIG                                 ,
+       RULL(0x05011380), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM      );
+
+REG64( PU_DISABLE_FORCE_PFET_OFF                               ,
+       RULL(0x0001000D), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_DISPALT_CTRL                                    ,
+       RULL(0x050110AC), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_DISPALT_CTRL                                    ,
+       RULL(0x050111AC), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_DISPALT_CTRL                                    ,
+       RULL(0x050112AC), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_DISPALT_DAT0                                    ,
+       RULL(0x050110AD), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_DISPALT_DAT0                                    ,
+       RULL(0x050111AD), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_DISPALT_DAT0                                    ,
+       RULL(0x050112AD), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_DISPALT_DAT1                                    ,
+       RULL(0x050110AE), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_DISPALT_DAT1                                    ,
+       RULL(0x050111AE), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_DISPALT_DAT1                                    ,
+       RULL(0x050112AE), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_DISPALT_STAT_ECC                                ,
+       RULL(0x050110AF), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_DISPALT_STAT_ECC                                ,
+       RULL(0x050111AF), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_DISPALT_STAT_ECC                                ,
+       RULL(0x050112AF), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_DMA_UP_ADDR                                          ,
+       RULL(0x05012914), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_DMA_VAS_MMIO_BAR                                     ,
+       RULL(0x0201105E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PEC_DRPPRICTL_REG                                       ,
+       RULL(0x04010C01), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_DRPPRICTL_REG                                     ,
+       RULL(0x04010C01), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_DRPPRICTL_REG                                     ,
+       RULL(0x04011001), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_DRPPRICTL_REG                                     ,
+       RULL(0x04011401), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( PU_NPU0_ECC_CONFIG                                      ,
+       RULL(0x050110A2), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_ECC_CONFIG                                      ,
+       RULL(0x050111A2), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_ECC_CONFIG                                      ,
+       RULL(0x050112A2), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_ECC_COUNT                                       ,
+       RULL(0x050110A3), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_ECC_COUNT                                       ,
+       RULL(0x050111A3), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_ECC_COUNT                                       ,
+       RULL(0x050112A3), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_ECC_ERRINJ                                      ,
+       RULL(0x050110A1), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_ECC_ERRINJ                                      ,
+       RULL(0x050111A1), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_ECC_ERRINJ                                      ,
+       RULL(0x050112A1), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART0_REGISTER                          ,
+       RULL(0x00018000), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART0_REGISTER                          ,
+       RULL(0x00018040), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART10_REGISTER                         ,
+       RULL(0x0001800A), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART10_REGISTER                         ,
+       RULL(0x0001804A), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART11_REGISTER                         ,
+       RULL(0x0001800B), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART11_REGISTER                         ,
+       RULL(0x0001804B), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART12_REGISTER                         ,
+       RULL(0x0001800C), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART12_REGISTER                         ,
+       RULL(0x0001804C), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART13_REGISTER                         ,
+       RULL(0x0001800D), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART13_REGISTER                         ,
+       RULL(0x0001804D), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART14_REGISTER                         ,
+       RULL(0x0001800E), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART14_REGISTER                         ,
+       RULL(0x0001804E), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART15_REGISTER                         ,
+       RULL(0x0001800F), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART15_REGISTER                         ,
+       RULL(0x0001804F), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART16_REGISTER                         ,
+       RULL(0x00018010), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART16_REGISTER                         ,
+       RULL(0x00018050), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART17_REGISTER                         ,
+       RULL(0x00018011), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART17_REGISTER                         ,
+       RULL(0x00018051), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART18_REGISTER                         ,
+       RULL(0x00018012), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART18_REGISTER                         ,
+       RULL(0x00018052), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART19_REGISTER                         ,
+       RULL(0x00018013), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART19_REGISTER                         ,
+       RULL(0x00018053), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART1_REGISTER                          ,
+       RULL(0x00018001), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART1_REGISTER                          ,
+       RULL(0x00018041), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART20_REGISTER                         ,
+       RULL(0x00018014), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART20_REGISTER                         ,
+       RULL(0x00018054), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART21_REGISTER                         ,
+       RULL(0x00018015), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART21_REGISTER                         ,
+       RULL(0x00018055), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART22_REGISTER                         ,
+       RULL(0x00018016), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART22_REGISTER                         ,
+       RULL(0x00018056), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART23_REGISTER                         ,
+       RULL(0x00018017), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART23_REGISTER                         ,
+       RULL(0x00018057), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART24_REGISTER                         ,
+       RULL(0x00018018), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART24_REGISTER                         ,
+       RULL(0x00018058), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART25_REGISTER                         ,
+       RULL(0x00018019), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART25_REGISTER                         ,
+       RULL(0x00018059), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART26_REGISTER                         ,
+       RULL(0x0001801A), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART26_REGISTER                         ,
+       RULL(0x0001805A), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART27_REGISTER                         ,
+       RULL(0x0001801B), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART27_REGISTER                         ,
+       RULL(0x0001805B), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART28_REGISTER                         ,
+       RULL(0x0001801C), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART28_REGISTER                         ,
+       RULL(0x0001805C), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART29_REGISTER                         ,
+       RULL(0x0001801D), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART29_REGISTER                         ,
+       RULL(0x0001805D), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART2_REGISTER                          ,
+       RULL(0x00018002), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART2_REGISTER                          ,
+       RULL(0x00018042), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART30_REGISTER                         ,
+       RULL(0x0001801E), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART30_REGISTER                         ,
+       RULL(0x0001805E), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART31_REGISTER                         ,
+       RULL(0x0001801F), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART31_REGISTER                         ,
+       RULL(0x0001805F), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART32_REGISTER                         ,
+       RULL(0x00018020), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART32_REGISTER                         ,
+       RULL(0x00018060), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART33_REGISTER                         ,
+       RULL(0x00018021), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART33_REGISTER                         ,
+       RULL(0x00018061), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART34_REGISTER                         ,
+       RULL(0x00018022), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART34_REGISTER                         ,
+       RULL(0x00018062), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART35_REGISTER                         ,
+       RULL(0x00018023), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART35_REGISTER                         ,
+       RULL(0x00018063), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART36_REGISTER                         ,
+       RULL(0x00018024), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART36_REGISTER                         ,
+       RULL(0x00018064), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART37_REGISTER                         ,
+       RULL(0x00018025), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART37_REGISTER                         ,
+       RULL(0x00018065), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART38_REGISTER                         ,
+       RULL(0x00018026), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART38_REGISTER                         ,
+       RULL(0x00018066), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART39_REGISTER                         ,
+       RULL(0x00018027), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART39_REGISTER                         ,
+       RULL(0x00018067), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART3_REGISTER                          ,
+       RULL(0x00018003), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART3_REGISTER                          ,
+       RULL(0x00018043), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART40_REGISTER                         ,
+       RULL(0x00018028), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART40_REGISTER                         ,
+       RULL(0x00018068), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART41_REGISTER                         ,
+       RULL(0x00018029), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART41_REGISTER                         ,
+       RULL(0x00018069), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART42_REGISTER                         ,
+       RULL(0x0001802A), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART42_REGISTER                         ,
+       RULL(0x0001806A), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART43_REGISTER                         ,
+       RULL(0x0001802B), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART43_REGISTER                         ,
+       RULL(0x0001806B), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART44_REGISTER                         ,
+       RULL(0x0001802C), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART44_REGISTER                         ,
+       RULL(0x0001806C), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART45_REGISTER                         ,
+       RULL(0x0001802D), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART45_REGISTER                         ,
+       RULL(0x0001806D), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART46_REGISTER                         ,
+       RULL(0x0001802E), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART46_REGISTER                         ,
+       RULL(0x0001806E), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART47_REGISTER                         ,
+       RULL(0x0001802F), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART47_REGISTER                         ,
+       RULL(0x0001806F), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART48_REGISTER                         ,
+       RULL(0x00018030), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART48_REGISTER                         ,
+       RULL(0x00018070), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART49_REGISTER                         ,
+       RULL(0x00018031), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART49_REGISTER                         ,
+       RULL(0x00018071), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART4_REGISTER                          ,
+       RULL(0x00018004), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART4_REGISTER                          ,
+       RULL(0x00018044), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART50_REGISTER                         ,
+       RULL(0x00018032), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART50_REGISTER                         ,
+       RULL(0x00018072), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART51_REGISTER                         ,
+       RULL(0x00018033), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART51_REGISTER                         ,
+       RULL(0x00018073), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART52_REGISTER                         ,
+       RULL(0x00018034), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART52_REGISTER                         ,
+       RULL(0x00018074), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART53_REGISTER                         ,
+       RULL(0x00018035), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART53_REGISTER                         ,
+       RULL(0x00018075), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART54_REGISTER                         ,
+       RULL(0x00018036), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART54_REGISTER                         ,
+       RULL(0x00018076), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART55_REGISTER                         ,
+       RULL(0x00018037), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART55_REGISTER                         ,
+       RULL(0x00018077), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART56_REGISTER                         ,
+       RULL(0x00018038), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART56_REGISTER                         ,
+       RULL(0x00018078), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART57_REGISTER                         ,
+       RULL(0x00018039), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART57_REGISTER                         ,
+       RULL(0x00018079), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART58_REGISTER                         ,
+       RULL(0x0001803A), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART58_REGISTER                         ,
+       RULL(0x0001807A), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART59_REGISTER                         ,
+       RULL(0x0001803B), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART59_REGISTER                         ,
+       RULL(0x0001807B), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART5_REGISTER                          ,
+       RULL(0x00018005), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART5_REGISTER                          ,
+       RULL(0x00018045), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART60_REGISTER                         ,
+       RULL(0x0001803C), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART60_REGISTER                         ,
+       RULL(0x0001807C), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART61_REGISTER                         ,
+       RULL(0x0001803D), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART61_REGISTER                         ,
+       RULL(0x0001807D), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART62_REGISTER                         ,
+       RULL(0x0001803E), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART62_REGISTER                         ,
+       RULL(0x0001807E), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART63_REGISTER                         ,
+       RULL(0x0001803F), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART63_REGISTER                         ,
+       RULL(0x0001807F), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART6_REGISTER                          ,
+       RULL(0x00018006), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART6_REGISTER                          ,
+       RULL(0x00018046), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART7_REGISTER                          ,
+       RULL(0x00018007), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART7_REGISTER                          ,
+       RULL(0x00018047), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART8_REGISTER                          ,
+       RULL(0x00018008), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART8_REGISTER                          ,
+       RULL(0x00018048), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART9_REGISTER                          ,
+       RULL(0x00018009), SH_UNT_PU_OTPROM0, SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART9_REGISTER                          ,
+       RULL(0x00018049), SH_UNT_PU_OTPROM1, SH_ACS_SCOM      );
+
+REG64( PU_EECNT_REG                                            ,
+       RULL(0x05012809), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EFT_HI_PRIOR_RCV_FIFO_ASB                            ,
+       RULL(0x020110C6), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EFT_HI_PRIOR_RCV_FIFO_BAR                            ,
+       RULL(0x020110C0), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EFT_HI_PRIOR_RCV_FIFO_CNTL                           ,
+       RULL(0x020110C3), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EFT_LO_PRIOR_RCV_FIFO_ASB                            ,
+       RULL(0x020110CF), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EFT_LO_PRIOR_RCV_FIFO_BAR                            ,
+       RULL(0x020110C9), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EFT_LO_PRIOR_RCV_FIFO_CNTL                           ,
+       RULL(0x020110CC), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EFT_MAX_BYTE_CNT                                     ,
+       RULL(0x02011059), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_EHHCA_FIR_ACTION0_REG                                ,
+       RULL(0x05012986), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_EHHCA_FIR_ACTION1_REG                                ,
+       RULL(0x05012987), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_EHHCA_FIR_MASK_REG                                   ,
+       RULL(0x05012983), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_EHHCA_FIR_MASK_REG_AND                               ,
+       RULL(0x05012984), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_EHHCA_FIR_MASK_REG_OR                                ,
+       RULL(0x05012985), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_EHHCA_FIR_REG                                        ,
+       RULL(0x05012980), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_EHHCA_FIR_REG_AND                                    ,
+       RULL(0x05012981), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_EHHCA_FIR_REG_OR                                     ,
+       RULL(0x05012982), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_NPU0_SM0_EPSILON_CONFIG                              ,
+       RULL(0x05011004), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_EPSILON_CONFIG                              ,
+       RULL(0x05011024), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_EPSILON_CONFIG                              ,
+       RULL(0x05011044), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_EPSILON_CONFIG                              ,
+       RULL(0x05011064), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_EPSILON_CONFIG                              ,
+       RULL(0x05011104), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_EPSILON_CONFIG                              ,
+       RULL(0x05011124), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_EPSILON_CONFIG                              ,
+       RULL(0x05011144), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_EPSILON_CONFIG                              ,
+       RULL(0x05011164), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_EPSILON_CONFIG                              ,
+       RULL(0x05011204), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_EPSILON_CONFIG                              ,
+       RULL(0x05011224), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_EPSILON_CONFIG                              ,
+       RULL(0x05011244), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_EPSILON_CONFIG                              ,
+       RULL(0x05011264), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PU_ERAT_STATUS_CONTROL                                  ,
+       RULL(0x020110D6), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_NTL0_ERROR1                                     ,
+       RULL(0x050110C4), SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU0_NTL1_ERROR1                                     ,
+       RULL(0x050110E4), SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_ERROR1                                      ,
+       RULL(0x05011014), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_ERROR1                                      ,
+       RULL(0x05011034), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_ERROR1                                      ,
+       RULL(0x05011054), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_ERROR1                                      ,
+       RULL(0x05011074), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_NTL0_ERROR1                                     ,
+       RULL(0x050111C4), SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU1_NTL1_ERROR1                                     ,
+       RULL(0x050111E4), SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_ERROR1                                      ,
+       RULL(0x05011114), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_ERROR1                                      ,
+       RULL(0x05011134), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_ERROR1                                      ,
+       RULL(0x05011154), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_ERROR1                                      ,
+       RULL(0x05011174), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_ERROR1                                     ,
+       RULL(0x050112C4), SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_ERROR1                                     ,
+       RULL(0x050112E4), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_ERROR1                                      ,
+       RULL(0x05011214), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_ERROR1                                      ,
+       RULL(0x05011234), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_ERROR1                                      ,
+       RULL(0x05011254), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_ERROR1                                      ,
+       RULL(0x05011274), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_ERROR2                                      ,
+       RULL(0x05011096), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_ERROR2                                      ,
+       RULL(0x05011196), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_ERROR2                                      ,
+       RULL(0x05011296), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU0_NTL0_ERROR2                                     ,
+       RULL(0x050110C6), SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU0_NTL1_ERROR2                                     ,
+       RULL(0x050110E6), SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_ERROR2                                      ,
+       RULL(0x05011016), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_ERROR2                                      ,
+       RULL(0x05011036), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_ERROR2                                      ,
+       RULL(0x05011056), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_ERROR2                                      ,
+       RULL(0x05011076), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_NTL0_ERROR2                                     ,
+       RULL(0x050111C6), SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU1_NTL1_ERROR2                                     ,
+       RULL(0x050111E6), SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_ERROR2                                      ,
+       RULL(0x05011116), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_ERROR2                                      ,
+       RULL(0x05011136), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_ERROR2                                      ,
+       RULL(0x05011156), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_ERROR2                                      ,
+       RULL(0x05011176), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_ERROR2                                     ,
+       RULL(0x050112C6), SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_ERROR2                                     ,
+       RULL(0x050112E6), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_ERROR2                                      ,
+       RULL(0x05011216), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_ERROR2                                      ,
+       RULL(0x05011236), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_ERROR2                                      ,
+       RULL(0x05011256), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_ERROR2                                      ,
+       RULL(0x05011276), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PU_ESB_CI_BASE                                          ,
+       RULL(0x05012916), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_ESB_NOTIFY                                           ,
+       RULL(0x05012917), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EXPORT_REGL_CTRL                                     ,
+       RULL(0x0001000E), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EXTENDED_STATUS_B                                    ,
+       RULL(0x000A000C), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EXTENDED_STATUS_C                                    ,
+       RULL(0x000A100C), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EXTENDED_STATUS_D                                    ,
+       RULL(0x000A200C), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EXTENDED_STATUS_E                                    ,
+       RULL(0x000A300C), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FIFO1_REGISTER_READ_B                                ,
+       RULL(0x000A0004), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FIFO1_REGISTER_READ_C                                ,
+       RULL(0x000A1004), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FIFO1_REGISTER_READ_D                                ,
+       RULL(0x000A2004), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FIFO1_REGISTER_READ_E                                ,
+       RULL(0x000A3004), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FIFO4_REGISTER_READ_B                                ,
+       RULL(0x000A0012), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FIFO4_REGISTER_READ_C                                ,
+       RULL(0x000A1012), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FIFO4_REGISTER_READ_D                                ,
+       RULL(0x000A2012), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FIFO4_REGISTER_READ_E                                ,
+       RULL(0x000A3012), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FIR_ACTION0_REG                                      ,
+       RULL(0x04011806), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOP0_FIR_ACTION0_REG                                 ,
+       RULL(0x0D010C06), SH_UNT_PU_IOP0  , SH_ACS_SCOM_RO   );
+REG64( PU_IOP1_FIR_ACTION0_REG                                 ,
+       RULL(0x0E010C06), SH_UNT_PU_IOP1  , SH_ACS_SCOM_RO   );
+REG64( PU_IOP2_FIR_ACTION0_REG                                 ,
+       RULL(0x0F010C06), SH_UNT_PU_IOP2  , SH_ACS_SCOM_RO   );
+REG64( PU_NPU_CTL_FIR_ACTION0_REG                              ,
+       RULL(0x05011786), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM_RW   );
+
+REG64( PU_FIR_ACTION1_REG                                      ,
+       RULL(0x04011807), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOP0_FIR_ACTION1_REG                                 ,
+       RULL(0x0D010C07), SH_UNT_PU_IOP0  , SH_ACS_SCOM_RO   );
+REG64( PU_IOP1_FIR_ACTION1_REG                                 ,
+       RULL(0x0E010C07), SH_UNT_PU_IOP1  , SH_ACS_SCOM_RO   );
+REG64( PU_IOP2_FIR_ACTION1_REG                                 ,
+       RULL(0x0F010C07), SH_UNT_PU_IOP2  , SH_ACS_SCOM_RO   );
+REG64( PU_NPU_CTL_FIR_ACTION1_REG                              ,
+       RULL(0x05011787), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM_RW   );
+
+REG64( PU_FIR_MASK_REG                                         ,
+       RULL(0x04011803), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_FIR_MASK_REG_AND                                     ,
+       RULL(0x04011804), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_FIR_MASK_REG_OR                                      ,
+       RULL(0x04011805), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_IOP0_FIR_MASK_REG                                    ,
+       RULL(0x0D010C03), SH_UNT_PU_IOP0  , SH_ACS_SCOM_RW   );
+REG64( PU_IOP0_FIR_MASK_REG_AND                                ,
+       RULL(0x0D010C04), SH_UNT_PU_IOP0  , SH_ACS_SCOM1_AND );
+REG64( PU_IOP0_FIR_MASK_REG_OR                                 ,
+       RULL(0x0D010C05), SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR  );
+REG64( PU_IOP1_FIR_MASK_REG                                    ,
+       RULL(0x0E010C03), SH_UNT_PU_IOP1  , SH_ACS_SCOM_RW   );
+REG64( PU_IOP1_FIR_MASK_REG_AND                                ,
+       RULL(0x0E010C04), SH_UNT_PU_IOP1  , SH_ACS_SCOM1_AND );
+REG64( PU_IOP1_FIR_MASK_REG_OR                                 ,
+       RULL(0x0E010C05), SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR  );
+REG64( PU_IOP2_FIR_MASK_REG                                    ,
+       RULL(0x0F010C03), SH_UNT_PU_IOP2  , SH_ACS_SCOM_RW   );
+REG64( PU_IOP2_FIR_MASK_REG_AND                                ,
+       RULL(0x0F010C04), SH_UNT_PU_IOP2  , SH_ACS_SCOM1_AND );
+REG64( PU_IOP2_FIR_MASK_REG_OR                                 ,
+       RULL(0x0F010C05), SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR  );
+REG64( PU_NPU_CTL_FIR_MASK_REG                                 ,
+       RULL(0x05011783), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM_RW   );
+REG64( PU_NPU_CTL_FIR_MASK_REG_AND                             ,
+       RULL(0x05011784), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM1_AND );
+REG64( PU_NPU_CTL_FIR_MASK_REG_OR                              ,
+       RULL(0x05011785), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR  );
+
+REG64( PU_FIR_MASK_REGISTER                                    ,
+       RULL(0x00088008), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FIR_REG                                              ,
+       RULL(0x04011800), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_FIR_REG_AND                                          ,
+       RULL(0x04011801), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_FIR_REG_OR                                           ,
+       RULL(0x04011802), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_NPU_CTL_FIR_REG                                      ,
+       RULL(0x05011780), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM_RW   );
+REG64( PU_NPU_CTL_FIR_REG_AND                                  ,
+       RULL(0x05011781), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM1_AND );
+REG64( PU_NPU_CTL_FIR_REG_OR                                   ,
+       RULL(0x05011782), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR  );
+
+REG64( PU_IOP0_FIR_STATUS_REG                                  ,
+       RULL(0x0D010C00), SH_UNT_PU_IOP0  , SH_ACS_SCOM_RW   );
+REG64( PU_IOP0_FIR_STATUS_REG_AND                              ,
+       RULL(0x0D010C01), SH_UNT_PU_IOP0  , SH_ACS_SCOM1_AND );
+REG64( PU_IOP0_FIR_STATUS_REG_OR                               ,
+       RULL(0x0D010C02), SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR  );
+REG64( PU_IOP1_FIR_STATUS_REG                                  ,
+       RULL(0x0E010C00), SH_UNT_PU_IOP1  , SH_ACS_SCOM_RW   );
+REG64( PU_IOP1_FIR_STATUS_REG_AND                              ,
+       RULL(0x0E010C01), SH_UNT_PU_IOP1  , SH_ACS_SCOM1_AND );
+REG64( PU_IOP1_FIR_STATUS_REG_OR                               ,
+       RULL(0x0E010C02), SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR  );
+REG64( PU_IOP2_FIR_STATUS_REG                                  ,
+       RULL(0x0F010C00), SH_UNT_PU_IOP2  , SH_ACS_SCOM_RW   );
+REG64( PU_IOP2_FIR_STATUS_REG_AND                              ,
+       RULL(0x0F010C01), SH_UNT_PU_IOP2  , SH_ACS_SCOM1_AND );
+REG64( PU_IOP2_FIR_STATUS_REG_OR                               ,
+       RULL(0x0F010C02), SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_FIR_WOF_REG                                          ,
+       RULL(0x04011808), SH_UNT          , SH_ACS_SCOM_WCLRREG );
+REG64( PU_IOP0_FIR_WOF_REG                                     ,
+       RULL(0x0D010C08), SH_UNT_PU_IOP0  , SH_ACS_SCOM_WCLRREG );
+REG64( PU_IOP1_FIR_WOF_REG                                     ,
+       RULL(0x0E010C08), SH_UNT_PU_IOP1  , SH_ACS_SCOM_WCLRREG );
+REG64( PU_IOP2_FIR_WOF_REG                                     ,
+       RULL(0x0F010C08), SH_UNT_PU_IOP2  , SH_ACS_SCOM_WCLRREG );
+REG64( PU_NPU_CTL_FIR_WOF_REG                                  ,
+       RULL(0x05011788), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_FMU_FORCE_OP_REG                                     ,
+       RULL(0x01020003), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FMU_MODE_REG                                         ,
+       RULL(0x01020000), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FMU_OSC_CNTR1_REG                                    ,
+       RULL(0x01020001), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FMU_OSC_CNTR2_REG                                    ,
+       RULL(0x01020002), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FMU_PULSE_GEN_REG                                    ,
+       RULL(0x01020001), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_FORCE_ECC_REG                                        ,
+       RULL(0x0502280D), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_FSB_DOWNFIFO_DATA_IN                                 ,
+       RULL(0x000B0010), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_FSB_DOWNFIFO_REQ_RESET                               ,
+       RULL(0x000B0013), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_FSB_DOWNFIFO_SIG_EOT                                 ,
+       RULL(0x000B0012), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_FSB_DOWNFIFO_STATUS                                  ,
+       RULL(0x000B0011), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FSB_UPFIFO_ACK_EOT                                   ,
+       RULL(0x000B0005), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_FSB_UPFIFO_DATA_OUT                                  ,
+       RULL(0x000B0000), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_FSB_UPFIFO_RESET                                     ,
+       RULL(0x000B0004), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_FSB_UPFIFO_STATUS                                    ,
+       RULL(0x000B0001), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SM0_GENID_BAR                                   ,
+       RULL(0x05011019), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_GENID_BAR                                   ,
+       RULL(0x05011039), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_GENID_BAR                                   ,
+       RULL(0x05011059), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_GENID_BAR                                   ,
+       RULL(0x05011079), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_GENID_BAR                                   ,
+       RULL(0x05011119), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_GENID_BAR                                   ,
+       RULL(0x05011139), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_GENID_BAR                                   ,
+       RULL(0x05011159), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_GENID_BAR                                   ,
+       RULL(0x05011179), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_GENID_BAR                                   ,
+       RULL(0x05011219), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_GENID_BAR                                   ,
+       RULL(0x05011239), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_GENID_BAR                                   ,
+       RULL(0x05011259), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_GENID_BAR                                   ,
+       RULL(0x05011279), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PU_GPE0_GPEDBG_OCI                                      ,
+       RULL(0xC0000010), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_GPEDBG_SCOM                                     ,
+       RULL(0x00060002), SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE1_GPEDBG_OCI                                      ,
+       RULL(0xC0010010), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_GPEDBG_SCOM                                     ,
+       RULL(0x00062002), SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE2_GPEDBG_OCI                                      ,
+       RULL(0xC0020010), SH_UNT_PU_GPE2  , SH_ACS_OCI       );
+REG64( PU_GPE2_GPEDBG_SCOM                                     ,
+       RULL(0x00064002), SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE3_GPEDBG_OCI                                      ,
+       RULL(0xC0030010), SH_UNT_PU_GPE3  , SH_ACS_OCI       );
+REG64( PU_GPE3_GPEDBG_SCOM                                     ,
+       RULL(0x00066002), SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_GPEIVPR_OCI                                     ,
+       RULL(0xC0000008), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_GPEIVPR_SCOM                                    ,
+       RULL(0x00060001), SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE1_GPEIVPR_OCI                                     ,
+       RULL(0xC0010008), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_GPEIVPR_SCOM                                    ,
+       RULL(0x00062001), SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE2_GPEIVPR_OCI                                     ,
+       RULL(0xC0020008), SH_UNT_PU_GPE2  , SH_ACS_OCI       );
+REG64( PU_GPE2_GPEIVPR_SCOM                                    ,
+       RULL(0x00064001), SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE3_GPEIVPR_OCI                                     ,
+       RULL(0xC0030008), SH_UNT_PU_GPE3  , SH_ACS_OCI       );
+REG64( PU_GPE3_GPEIVPR_SCOM                                    ,
+       RULL(0x00066001), SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_GPEMACR_OCI                                     ,
+       RULL(0xC0000020), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_GPEMACR_SCOM                                    ,
+       RULL(0x00060004), SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE1_GPEMACR_OCI                                     ,
+       RULL(0xC0010020), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_GPEMACR_SCOM                                    ,
+       RULL(0x00062004), SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE2_GPEMACR_OCI                                     ,
+       RULL(0xC0020020), SH_UNT_PU_GPE2  , SH_ACS_OCI       );
+REG64( PU_GPE2_GPEMACR_SCOM                                    ,
+       RULL(0x00064004), SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE3_GPEMACR_OCI                                     ,
+       RULL(0xC0030020), SH_UNT_PU_GPE3  , SH_ACS_OCI       );
+REG64( PU_GPE3_GPEMACR_SCOM                                    ,
+       RULL(0x00066004), SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_GPESTR_OCI                                      ,
+       RULL(0xC0000018), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_GPESTR_SCOM                                     ,
+       RULL(0x00060003), SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE1_GPESTR_OCI                                      ,
+       RULL(0xC0010018), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_GPESTR_SCOM                                     ,
+       RULL(0x00062003), SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE2_GPESTR_OCI                                      ,
+       RULL(0xC0020018), SH_UNT_PU_GPE2  , SH_ACS_OCI       );
+REG64( PU_GPE2_GPESTR_SCOM                                     ,
+       RULL(0x00064003), SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE3_GPESTR_OCI                                      ,
+       RULL(0xC0030018), SH_UNT_PU_GPE3  , SH_ACS_OCI       );
+REG64( PU_GPE3_GPESTR_SCOM                                     ,
+       RULL(0x00066003), SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_GPETSEL_OCI                                     ,
+       RULL(0xC0000000), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_GPETSEL_SCOM                                    ,
+       RULL(0x00060000), SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE1_GPETSEL_OCI                                     ,
+       RULL(0xC0010000), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_GPETSEL_SCOM                                    ,
+       RULL(0x00062000), SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE2_GPETSEL_OCI                                     ,
+       RULL(0xC0020000), SH_UNT_PU_GPE2  , SH_ACS_OCI       );
+REG64( PU_GPE2_GPETSEL_SCOM                                    ,
+       RULL(0x00064000), SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE3_GPETSEL_OCI                                     ,
+       RULL(0xC0030000), SH_UNT_PU_GPE3  , SH_ACS_OCI       );
+REG64( PU_GPE3_GPETSEL_SCOM                                    ,
+       RULL(0x00066000), SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_GPEXIEDR_OCI                                    ,
+       RULL(0xC0000118), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_GPEXIEDR_SCOM                                   ,
+       RULL(0x00060023), SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE1_GPEXIEDR_OCI                                    ,
+       RULL(0xC0010118), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_GPEXIEDR_SCOM                                   ,
+       RULL(0x00062023), SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE2_GPEXIEDR_OCI                                    ,
+       RULL(0xC0020118), SH_UNT_PU_GPE2  , SH_ACS_OCI       );
+REG64( PU_GPE2_GPEXIEDR_SCOM                                   ,
+       RULL(0x00064023), SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE3_GPEXIEDR_OCI                                    ,
+       RULL(0xC0030118), SH_UNT_PU_GPE3  , SH_ACS_OCI       );
+REG64( PU_GPE3_GPEXIEDR_SCOM                                   ,
+       RULL(0x00066023), SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_GPEXIIAR_OCI                                    ,
+       RULL(0xC0000128), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_GPEXIIAR_SCOM                                   ,
+       RULL(0x00060025), SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE1_GPEXIIAR_OCI                                    ,
+       RULL(0xC0010128), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_GPEXIIAR_SCOM                                   ,
+       RULL(0x00062025), SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE2_GPEXIIAR_OCI                                    ,
+       RULL(0xC0020128), SH_UNT_PU_GPE2  , SH_ACS_OCI       );
+REG64( PU_GPE2_GPEXIIAR_SCOM                                   ,
+       RULL(0x00064025), SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE3_GPEXIIAR_OCI                                    ,
+       RULL(0xC0030128), SH_UNT_PU_GPE3  , SH_ACS_OCI       );
+REG64( PU_GPE3_GPEXIIAR_SCOM                                   ,
+       RULL(0x00066025), SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_GPEXIIR_OCI                                     ,
+       RULL(0xC0000120), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_GPEXIIR_SCOM                                    ,
+       RULL(0x00060024), SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE1_GPEXIIR_OCI                                     ,
+       RULL(0xC0010120), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_GPEXIIR_SCOM                                    ,
+       RULL(0x00062024), SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE2_GPEXIIR_OCI                                     ,
+       RULL(0xC0020120), SH_UNT_PU_GPE2  , SH_ACS_OCI       );
+REG64( PU_GPE2_GPEXIIR_SCOM                                    ,
+       RULL(0x00064024), SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE3_GPEXIIR_OCI                                     ,
+       RULL(0xC0030120), SH_UNT_PU_GPE3  , SH_ACS_OCI       );
+REG64( PU_GPE3_GPEXIIR_SCOM                                    ,
+       RULL(0x00066024), SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_GPEXISPRG0_OCI                                  ,
+       RULL(0xC0000110), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_GPEXISPRG0_SCOM                                 ,
+       RULL(0x00060022), SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE1_GPEXISPRG0_OCI                                  ,
+       RULL(0xC0010110), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_GPEXISPRG0_SCOM                                 ,
+       RULL(0x00062022), SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE2_GPEXISPRG0_OCI                                  ,
+       RULL(0xC0020110), SH_UNT_PU_GPE2  , SH_ACS_OCI       );
+REG64( PU_GPE2_GPEXISPRG0_SCOM                                 ,
+       RULL(0x00064022), SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE3_GPEXISPRG0_OCI                                  ,
+       RULL(0xC0030110), SH_UNT_PU_GPE3  , SH_ACS_OCI       );
+REG64( PU_GPE3_GPEXISPRG0_SCOM                                 ,
+       RULL(0x00066022), SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_GPEXIXCR_OCI                                    ,
+       RULL(0xC0000100), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_GPEXIXCR_SCOM                                   ,
+       RULL(0x00060020), SH_UNT_PU_GPE0  , SH_ACS_SCOM_WO   );
+REG64( PU_GPE1_GPEXIXCR_OCI                                    ,
+       RULL(0xC0010100), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_GPEXIXCR_SCOM                                   ,
+       RULL(0x00062020), SH_UNT_PU_GPE1  , SH_ACS_SCOM_WO   );
+REG64( PU_GPE2_GPEXIXCR_OCI                                    ,
+       RULL(0xC0020100), SH_UNT_PU_GPE2  , SH_ACS_OCI       );
+REG64( PU_GPE2_GPEXIXCR_SCOM                                   ,
+       RULL(0x00064020), SH_UNT_PU_GPE2  , SH_ACS_SCOM_WO   );
+REG64( PU_GPE3_GPEXIXCR_OCI                                    ,
+       RULL(0xC0030100), SH_UNT_PU_GPE3  , SH_ACS_OCI       );
+REG64( PU_GPE3_GPEXIXCR_SCOM                                   ,
+       RULL(0x00066020), SH_UNT_PU_GPE3  , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE0_GPEXIXSR_OCI                                    ,
+       RULL(0xC0000108), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_GPEXIXSR_SCOM                                   ,
+       RULL(0x00060021), SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE1_GPEXIXSR_OCI                                    ,
+       RULL(0xC0010108), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_GPEXIXSR_SCOM                                   ,
+       RULL(0x00062021), SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE2_GPEXIXSR_OCI                                    ,
+       RULL(0xC0020108), SH_UNT_PU_GPE2  , SH_ACS_OCI       );
+REG64( PU_GPE2_GPEXIXSR_SCOM                                   ,
+       RULL(0x00064021), SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE3_GPEXIXSR_OCI                                    ,
+       RULL(0xC0030108), SH_UNT_PU_GPE3  , SH_ACS_OCI       );
+REG64( PU_GPE3_GPEXIXSR_SCOM                                   ,
+       RULL(0x00066021), SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO   );
+
+REG64( PU_NPU0_SM0_GPU0_BAR                                    ,
+       RULL(0x0501100B), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_GPU0_BAR                                    ,
+       RULL(0x0501102B), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_GPU0_BAR                                    ,
+       RULL(0x0501104B), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_GPU0_BAR                                    ,
+       RULL(0x0501106B), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_GPU0_BAR                                    ,
+       RULL(0x0501110B), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_GPU0_BAR                                    ,
+       RULL(0x0501112B), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_GPU0_BAR                                    ,
+       RULL(0x0501114B), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_GPU0_BAR                                    ,
+       RULL(0x0501116B), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_GPU0_BAR                                    ,
+       RULL(0x0501120B), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_GPU0_BAR                                    ,
+       RULL(0x0501122B), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_GPU0_BAR                                    ,
+       RULL(0x0501124B), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_GPU0_BAR                                    ,
+       RULL(0x0501126B), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SM0_GPU1_BAR                                    ,
+       RULL(0x0501100C), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_GPU1_BAR                                    ,
+       RULL(0x0501102C), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_GPU1_BAR                                    ,
+       RULL(0x0501104C), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_GPU1_BAR                                    ,
+       RULL(0x0501106C), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_GPU1_BAR                                    ,
+       RULL(0x0501110C), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_GPU1_BAR                                    ,
+       RULL(0x0501112C), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_GPU1_BAR                                    ,
+       RULL(0x0501114C), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_GPU1_BAR                                    ,
+       RULL(0x0501116C), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_GPU1_BAR                                    ,
+       RULL(0x0501120C), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_GPU1_BAR                                    ,
+       RULL(0x0501122C), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_GPU1_BAR                                    ,
+       RULL(0x0501124C), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_GPU1_BAR                                    ,
+       RULL(0x0501126C), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PU_GZIP_CONTROL_REG                                     ,
+       RULL(0x02011140), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GZIP_ERRRPT_HOLD_REG                                 ,
+       RULL(0x02011152), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB                           ,
+       RULL(0x020110C8), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GZIP_HI_PRIOR_RCV_FIFO_BAR                           ,
+       RULL(0x020110C2), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL                          ,
+       RULL(0x020110C5), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB                           ,
+       RULL(0x020110D1), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GZIP_LO_PRIOR_RCV_FIFO_BAR                           ,
+       RULL(0x020110CB), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL                          ,
+       RULL(0x020110CE), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GZIP_MAX_BYTE_CNT                                    ,
+       RULL(0x0201105B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_HCA_BAR                                              ,
+       RULL(0x0501298A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_HCA_COUNT_BAR                                        ,
+       RULL(0x0501298B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_HCA_DROP                                             ,
+       RULL(0x05012991), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_HCA_FLUSH                                            ,
+       RULL(0x05012990), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_HCA_MIRROR_BAR                                       ,
+       RULL(0x05012993), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_HCA_MODES                                            ,
+       RULL(0x0501298F), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_HCA_REF_BAR                                          ,
+       RULL(0x0501298E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_HCA_RESET                                            ,
+       RULL(0x05012992), SH_UNT          , SH_ACS_SCOM_W    );
+
+REG64( PU_NPU0_SM0_HIGH_WATER                                  ,
+       RULL(0x05011012), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_HIGH_WATER                                  ,
+       RULL(0x05011032), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_HIGH_WATER                                  ,
+       RULL(0x05011052), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_HIGH_WATER                                  ,
+       RULL(0x05011072), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_HIGH_WATER                                  ,
+       RULL(0x05011112), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_HIGH_WATER                                  ,
+       RULL(0x05011132), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_HIGH_WATER                                  ,
+       RULL(0x05011152), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_HIGH_WATER                                  ,
+       RULL(0x05011172), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_HIGH_WATER                                  ,
+       RULL(0x05011212), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_HIGH_WATER                                  ,
+       RULL(0x05011232), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_HIGH_WATER                                  ,
+       RULL(0x05011252), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_HIGH_WATER                                  ,
+       RULL(0x05011272), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PU_HTM0_HTM_CFG                                         ,
+       RULL(0x05012888), SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW   );
+REG64( PU_HTM1_HTM_CFG                                         ,
+       RULL(0x050128C8), SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_HTM0_HTM_CTRL                                        ,
+       RULL(0x05012885), SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW   );
+REG64( PU_HTM1_HTM_CTRL                                        ,
+       RULL(0x050128C5), SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_HTM0_HTM_FILT                                        ,
+       RULL(0x05012886), SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW   );
+REG64( PU_HTM1_HTM_FILT                                        ,
+       RULL(0x050128C6), SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_HTM0_HTM_FLEX                                        ,
+       RULL(0x05012889), SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW   );
+REG64( PU_HTM1_HTM_FLEX                                        ,
+       RULL(0x050128C9), SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_HTM0_HTM_LAST                                        ,
+       RULL(0x05012883), SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO   );
+REG64( PU_HTM1_HTM_LAST                                        ,
+       RULL(0x050128C3), SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO   );
+
+REG64( PU_HTM0_HTM_MEM                                         ,
+       RULL(0x05012881), SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW   );
+REG64( PU_HTM1_HTM_MEM                                         ,
+       RULL(0x050128C1), SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_HTM0_HTM_MODE                                        ,
+       RULL(0x05012880), SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW   );
+REG64( PU_HTM1_HTM_MODE                                        ,
+       RULL(0x050128C0), SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_HTM0_HTM_STAT                                        ,
+       RULL(0x05012882), SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO   );
+REG64( PU_HTM1_HTM_STAT                                        ,
+       RULL(0x050128C2), SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO   );
+
+REG64( PU_HTM0_HTM_TRIG                                        ,
+       RULL(0x05012884), SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW   );
+REG64( PU_HTM1_HTM_TRIG                                        ,
+       RULL(0x050128C4), SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_HTM0_HTM_TTYPEFILT                                   ,
+       RULL(0x05012887), SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW   );
+REG64( PU_HTM1_HTM_TTYPEFILT                                   ,
+       RULL(0x050128C7), SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_I2C_BUSY_REGISTER_B                                  ,
+       RULL(0x000A000E), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_I2C_BUSY_REGISTER_C                                  ,
+       RULL(0x000A100E), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_I2C_BUSY_REGISTER_D                                  ,
+       RULL(0x000A200E), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_I2C_BUSY_REGISTER_E                                  ,
+       RULL(0x000A300E), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_ERR_B                                      ,
+       RULL(0x000A000C), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_IMM_RESET_ERR_C                                      ,
+       RULL(0x000A100C), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_IMM_RESET_ERR_D                                      ,
+       RULL(0x000A200C), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_IMM_RESET_ERR_E                                      ,
+       RULL(0x000A300C), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_IMM_RESET_I2C_B                                      ,
+       RULL(0x000A000B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_I2C_C                                      ,
+       RULL(0x000A100B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_I2C_D                                      ,
+       RULL(0x000A200B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_I2C_E                                      ,
+       RULL(0x000A300B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_S_SCL_B                                    ,
+       RULL(0x000A000F), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_S_SCL_C                                    ,
+       RULL(0x000A100F), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_S_SCL_D                                    ,
+       RULL(0x000A200F), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_S_SCL_E                                    ,
+       RULL(0x000A300F), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_S_SDA_B                                    ,
+       RULL(0x000A0011), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_S_SDA_C                                    ,
+       RULL(0x000A1011), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_S_SDA_D                                    ,
+       RULL(0x000A2011), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_S_SDA_E                                    ,
+       RULL(0x000A3011), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_SET_S_SCL_B                                      ,
+       RULL(0x000A000D), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_SET_S_SCL_C                                      ,
+       RULL(0x000A100D), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_SET_S_SCL_D                                      ,
+       RULL(0x000A200D), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_SET_S_SCL_E                                      ,
+       RULL(0x000A300D), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_SET_S_SDA_B                                      ,
+       RULL(0x000A0010), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_SET_S_SDA_C                                      ,
+       RULL(0x000A1010), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_SET_S_SDA_D                                      ,
+       RULL(0x000A2010), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_SET_S_SDA_E                                      ,
+       RULL(0x000A3010), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPTS_B                                         ,
+       RULL(0x000A000A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPTS_C                                         ,
+       RULL(0x000A100A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPTS_D                                         ,
+       RULL(0x000A200A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPTS_E                                         ,
+       RULL(0x000A300A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPT_COND_B                                     ,
+       RULL(0x000A0009), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPT_COND_C                                     ,
+       RULL(0x000A1009), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPT_COND_D                                     ,
+       RULL(0x000A2009), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPT_COND_E                                     ,
+       RULL(0x000A3009), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPT_MASK_REGISTER_B_WO                         ,
+       RULL(0x000A0008), SH_UNT          , SH_ACS_SCOM_WO   );
+REG64( PU_INTERRUPT_MASK_REGISTER_B_OR                         ,
+       RULL(0x000A0009), SH_UNT          , SH_ACS_SCOM1_OR  );
+REG64( PU_INTERRUPT_MASK_REGISTER_B_AND                        ,
+       RULL(0x000A000A), SH_UNT          , SH_ACS_SCOM2_AND );
+
+REG64( PU_INTERRUPT_MASK_REGISTER_C_WO                         ,
+       RULL(0x000A1008), SH_UNT          , SH_ACS_SCOM_WO   );
+REG64( PU_INTERRUPT_MASK_REGISTER_C_OR                         ,
+       RULL(0x000A1009), SH_UNT          , SH_ACS_SCOM1_OR  );
+REG64( PU_INTERRUPT_MASK_REGISTER_C_AND                        ,
+       RULL(0x000A100A), SH_UNT          , SH_ACS_SCOM2_AND );
+
+REG64( PU_INTERRUPT_MASK_REGISTER_D_WO                         ,
+       RULL(0x000A2008), SH_UNT          , SH_ACS_SCOM_WO   );
+REG64( PU_INTERRUPT_MASK_REGISTER_D_OR                         ,
+       RULL(0x000A2009), SH_UNT          , SH_ACS_SCOM1_OR  );
+REG64( PU_INTERRUPT_MASK_REGISTER_D_AND                        ,
+       RULL(0x000A200A), SH_UNT          , SH_ACS_SCOM2_AND );
+
+REG64( PU_INTERRUPT_MASK_REGISTER_E_WO                         ,
+       RULL(0x000A3008), SH_UNT          , SH_ACS_SCOM_WO   );
+REG64( PU_INTERRUPT_MASK_REGISTER_E_OR                         ,
+       RULL(0x000A3009), SH_UNT          , SH_ACS_SCOM1_OR  );
+REG64( PU_INTERRUPT_MASK_REGISTER_E_AND                        ,
+       RULL(0x000A300A), SH_UNT          , SH_ACS_SCOM2_AND );
+
+REG64( PU_INTERRUPT_MASK_REGISTER_READ_B                       ,
+       RULL(0x000A0008), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPT_MASK_REGISTER_READ_C                       ,
+       RULL(0x000A1008), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPT_MASK_REGISTER_READ_D                       ,
+       RULL(0x000A2008), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPT_MASK_REGISTER_READ_E                       ,
+       RULL(0x000A3008), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NMMU_INT_CQ_AIB_CTL                                  ,
+       RULL(0x05013022), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NMMU_INT_CQ_CFG_LDQ                                  ,
+       RULL(0x05013026), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW   );
+
+REG64( PU_NMMU_INT_CQ_CFG_PB_GEN                               ,
+       RULL(0x0501300A), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NMMU_INT_CQ_CFG_STQ1                                 ,
+       RULL(0x05013024), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW   );
+
+REG64( PU_NMMU_INT_CQ_CFG_STQ2                                 ,
+       RULL(0x05013025), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW   );
+
+REG64( PU_NMMU_INT_CQ_CNPM_SEL                                 ,
+       RULL(0x0501300F), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW   );
+
+REG64( PU_NMMU_INT_CQ_ERR_INFO0                                ,
+       RULL(0x0501303A), SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART );
+
+REG64( PU_NMMU_INT_CQ_ERR_INFO1                                ,
+       RULL(0x0501303B), SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART );
+
+REG64( PU_NMMU_INT_CQ_ERR_INFO2                                ,
+       RULL(0x0501303C), SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART );
+
+REG64( PU_NMMU_INT_CQ_ERR_INFO3                                ,
+       RULL(0x0501303D), SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART );
+
+REG64( PU_NMMU_INT_CQ_ERR_RPT_HOLD                             ,
+       RULL(0x05013039), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO   );
+
+REG64( PU_NMMU_INT_CQ_IC_BAR                                   ,
+       RULL(0x05013010), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW   );
+
+REG64( PU_NMMU_INT_CQ_MSGSND                                   ,
+       RULL(0x0501300B), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW   );
+
+REG64( PU_NMMU_INT_CQ_PBI_CTL                                  ,
+       RULL(0x05013020), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NMMU_INT_CQ_PBO_CTL                                  ,
+       RULL(0x05013021), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NMMU_INT_CQ_PC_BAR                                   ,
+       RULL(0x05013016), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW   );
+
+REG64( PU_NMMU_INT_CQ_PC_BARM                                  ,
+       RULL(0x05013017), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW   );
+
+REG64( PU_NMMU_INT_CQ_PMC_0                                    ,
+       RULL(0x05013028), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO   );
+
+REG64( PU_NMMU_INT_CQ_PMC_1                                    ,
+       RULL(0x05013029), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO   );
+
+REG64( PU_NMMU_INT_CQ_PMC_2                                    ,
+       RULL(0x0501302A), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO   );
+
+REG64( PU_NMMU_INT_CQ_PMC_3                                    ,
+       RULL(0x0501302B), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO   );
+
+REG64( PU_NMMU_INT_CQ_PMC_4                                    ,
+       RULL(0x0501302C), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO   );
+
+REG64( PU_NMMU_INT_CQ_PMC_5                                    ,
+       RULL(0x0501302D), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO   );
+
+REG64( PU_NMMU_INT_CQ_PMC_6                                    ,
+       RULL(0x0501302E), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO   );
+
+REG64( PU_NMMU_INT_CQ_PMC_7                                    ,
+       RULL(0x0501302F), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO   );
+
+REG64( PU_NMMU_INT_CQ_PM_CTL                                   ,
+       RULL(0x05013027), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NMMU_INT_CQ_RST_CTL                                  ,
+       RULL(0x05013023), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NMMU_INT_CQ_SWI_RSP                                  ,
+       RULL(0x05013009), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO   );
+
+REG64( PU_NMMU_INT_CQ_TM1_BAR                                  ,
+       RULL(0x05013012), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW   );
+
+REG64( PU_NMMU_INT_CQ_TM2_BAR                                  ,
+       RULL(0x05013014), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW   );
+
+REG64( PU_NMMU_INT_CQ_VC_BAR                                   ,
+       RULL(0x05013018), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW   );
+
+REG64( PU_NMMU_INT_CQ_VC_BARM                                  ,
+       RULL(0x05013019), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_AIB_MAX_CMD_CRD_REG                           ,
+       RULL(0x05013129), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_AIB_MAX_DAT_CRD_REG                           ,
+       RULL(0x0501312A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_CRD_INIT_TIMER                                ,
+       RULL(0x05013128), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_GEN_CFG                                       ,
+       RULL(0x0501312B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_INDIR0_REG                                    ,
+       RULL(0x05013103), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_INDIR1_REG                                    ,
+       RULL(0x05013104), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_INDIR2_REG                                    ,
+       RULL(0x05013105), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_INDIR3_REG                                    ,
+       RULL(0x05013106), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_MMIO_ARB_CFG                                  ,
+       RULL(0x05013125), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_PCMD_ARB_CFG                                  ,
+       RULL(0x05013120), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_REGS_ERR_CFG_REG0                             ,
+       RULL(0x05013130), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_REGS_ERR_CFG_REG1                             ,
+       RULL(0x05013131), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_REGS_FATAL_ERR                                ,
+       RULL(0x05013133), SH_UNT          , SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_PC_REGS_INFO_ERR                                 ,
+       RULL(0x05013134), SH_UNT          , SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_PC_REGS_RECOV_ERR                                ,
+       RULL(0x05013135), SH_UNT          , SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_PC_REGS_WOF_ERR                                  ,
+       RULL(0x05013132), SH_UNT          , SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_PC_REGS_WOF_ERR_DETAIL                           ,
+       RULL(0x05013136), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_PC_TCTXT_CFG_REG                                 ,
+       RULL(0x05013100), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_THRD_EN_REG0                                  ,
+       RULL(0x05013101), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_THRD_EN_REG1                                  ,
+       RULL(0x05013102), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VRQ_ARB_CFG                                   ,
+       RULL(0x05013123), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VRQ_CRD_CFG                                   ,
+       RULL(0x05013124), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VRQ_PEND_CFG                                  ,
+       RULL(0x05013122), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VRQ_QUE_CFG                                   ,
+       RULL(0x05013121), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VSD_TABLE_ADDR                                ,
+       RULL(0x0501312C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_AIB_TIMEOUT                                   ,
+       RULL(0x0501322B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_AIB_TX_CMD_PRIORITY                           ,
+       RULL(0x0501323D), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_AIB_TX_ORDERING_TAG_1                         ,
+       RULL(0x0501322C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_AIB_TX_ORDERING_TAG_2                         ,
+       RULL(0x0501322D), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_ATX_INIT_CREDIT_COUNT                         ,
+       RULL(0x0501323C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_ATX_PERF_EVENT_SEL_1                          ,
+       RULL(0x05013240), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_ATX_PERF_EVENT_SEL_2                          ,
+       RULL(0x05013241), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_ATX_PERF_EVENT_SEL_3                          ,
+       RULL(0x05013242), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_AT_MACRO_KILL                                 ,
+       RULL(0x0501323E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_AT_MACRO_KILL_MASK                            ,
+       RULL(0x0501323F), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_ADDITIONAL_PERF_1                         ,
+       RULL(0x05013253), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_VC_EQC_ADDITIONAL_PERF_2                         ,
+       RULL(0x05013254), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_VC_EQC_CACHE_EN                                  ,
+       RULL(0x05013211), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_CACHE_WATCH_DATA0                         ,
+       RULL(0x05013216), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_CACHE_WATCH_DATA1                         ,
+       RULL(0x05013217), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_CACHE_WATCH_DATA2                         ,
+       RULL(0x05013218), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_CACHE_WATCH_DATA3                         ,
+       RULL(0x05013219), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_CACHE_WATCH_SPEC                          ,
+       RULL(0x05013215), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INT_VC_EQC_CONFIG                                    ,
+       RULL(0x05013214), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_DEBUG                                     ,
+       RULL(0x0501321A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_PERF_EVENT_SEL_1                          ,
+       RULL(0x05013250), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_PERF_EVENT_SEL_2                          ,
+       RULL(0x05013251), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_PERF_EVENT_SEL_3                          ,
+       RULL(0x05013252), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_SCRUB_MASK                                ,
+       RULL(0x05013213), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_SCRUB_TRIG                                ,
+       RULL(0x05013212), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQD_BLOCK_MODE                                ,
+       RULL(0x05013204), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_ERR_CFG_G0R0                                  ,
+       RULL(0x05013270), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_ERR_CFG_G0R1                                  ,
+       RULL(0x05013271), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_ERR_CFG_G1R0                                  ,
+       RULL(0x05013272), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_ERR_CFG_G1R1                                  ,
+       RULL(0x05013273), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_FATAL_ERR_G0                                  ,
+       RULL(0x05013278), SH_UNT          , SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_VC_FATAL_ERR_G1                                  ,
+       RULL(0x0501327B), SH_UNT          , SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_VC_GLOBAL_CONFIG                                 ,
+       RULL(0x05013200), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_INFO_ERR_G0                                   ,
+       RULL(0x0501327A), SH_UNT          , SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_VC_INFO_ERR_G1                                   ,
+       RULL(0x0501327D), SH_UNT          , SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_VC_IRQ_CONFIG_0                                  ,
+       RULL(0x05013208), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INT_VC_IRQ_CONFIG_1                                  ,
+       RULL(0x05013209), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INT_VC_IRQ_CONFIG_2                                  ,
+       RULL(0x0501320A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INT_VC_IRQ_CONFIG_3                                  ,
+       RULL(0x0501320B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INT_VC_IRQ_CONFIG_4                                  ,
+       RULL(0x0501320C), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INT_VC_IRQ_CONFIG_5                                  ,
+       RULL(0x0501320D), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INT_VC_IRQ_PERF_EVENT_SEL_0                          ,
+       RULL(0x05013268), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IRQ_PERF_EVENT_SEL_1                          ,
+       RULL(0x05013269), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IRQ_PERF_EVENT_SEL_2                          ,
+       RULL(0x0501326A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IRQ_PERF_EVENT_SEL_3                          ,
+       RULL(0x0501326B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IRQ_PERF_EVENT_SEL_4                          ,
+       RULL(0x0501326C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IRQ_PERF_EVENT_SEL_5                          ,
+       RULL(0x0501326D), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IRQ_TO_EQC_CREDITS                            ,
+       RULL(0x0501320E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVC_ADDITIONAL_PERF                           ,
+       RULL(0x0501325B), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_VC_IVC_CACHE_EN                                  ,
+       RULL(0x05013221), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVC_CACHE_WATCH_ADDR                          ,
+       RULL(0x05013225), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVC_CACHE_WATCH_DATA                          ,
+       RULL(0x05013226), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_VC_IVC_DEBUG                                     ,
+       RULL(0x0501322A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVC_HASH_1                                    ,
+       RULL(0x05013227), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVC_HASH_2                                    ,
+       RULL(0x05013228), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVC_HASH_3                                    ,
+       RULL(0x05013229), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVC_PERF_EVENT_SEL_1                          ,
+       RULL(0x05013258), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVC_PERF_EVENT_SEL_2                          ,
+       RULL(0x05013259), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVC_PERF_EVENT_SEL_3                          ,
+       RULL(0x0501325A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVC_SCRUB_MASK                                ,
+       RULL(0x05013223), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVC_SCRUB_TRIG                                ,
+       RULL(0x05013222), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVE_ISB_BLOCK_MODE                            ,
+       RULL(0x05013203), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_LBS6_DEBUG                                    ,
+       RULL(0x05013206), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD                  ,
+       RULL(0x05013210), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA                       ,
+       RULL(0x0501323B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD                       ,
+       RULL(0x05013220), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD                       ,
+       RULL(0x05013230), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_RECOV_ERR_G0                                  ,
+       RULL(0x05013279), SH_UNT          , SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_VC_RECOV_ERR_G1                                  ,
+       RULL(0x0501327C), SH_UNT          , SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_VC_SBC_ADDITIONAL_PERF                           ,
+       RULL(0x05013263), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_VC_SBC_CACHE_EN                                  ,
+       RULL(0x05013231), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_SBC_CACHE_WATCH_ADDR                          ,
+       RULL(0x05013235), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_SBC_CACHE_WATCH_DATA                          ,
+       RULL(0x05013236), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_VC_SBC_CONFIG                                    ,
+       RULL(0x05013234), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_SBC_DEBUG                                     ,
+       RULL(0x0501323A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_SBC_PERF_EVENT_SEL_1                          ,
+       RULL(0x05013260), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_SBC_PERF_EVENT_SEL_2                          ,
+       RULL(0x05013261), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_SBC_PERF_EVENT_SEL_3                          ,
+       RULL(0x05013262), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_SBC_SCRUB_MASK                                ,
+       RULL(0x05013233), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_SBC_SCRUB_TRIG                                ,
+       RULL(0x05013232), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_VPS_BLOCK_MODE                                ,
+       RULL(0x05013205), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_VSD_TABLE_ADDR                                ,
+       RULL(0x05013201), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_WOF_ERR_G0                                    ,
+       RULL(0x05013274), SH_UNT          , SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_VC_WOF_ERR_G0_DETAIL                             ,
+       RULL(0x05013275), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_VC_WOF_ERR_G1                                    ,
+       RULL(0x05013276), SH_UNT          , SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_VC_WOF_ERR_G1_DETAIL                             ,
+       RULL(0x05013277), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_NPU_SM1_IODA_ADDR                                    ,
+       RULL(0x05011321), SH_UNT_PU_NPU_SM1, SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM1_IODA_DAT0                                    ,
+       RULL(0x05011322), SH_UNT_PU_NPU_SM1, SH_ACS_SCOM      );
+
+REG64( PU_IO_DATA_REG                                          ,
+       RULL(0x05022830), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_IVT_OFFSET                                           ,
+       RULL(0x05012918), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GPE6_JTG_PIB_OJCFG                                   ,
+       RULL(0x0006D004), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE6_JTG_PIB_OJCFG_CLEAR                             ,
+       RULL(0x0006D005), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_JTG_PIB_OJCFG_OR                                ,
+       RULL(0x0006D006), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE6_JTG_PIB_OJFRST                                  ,
+       RULL(0x0006D007), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+
+REG64( PU_GPE6_JTG_PIB_OJIC_SCOM                               ,
+       RULL(0x0006D008), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+REG64( PU_GPE6_JTG_PIB_OJIC_SCOM1                              ,
+       RULL(0x0006D009), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_JTG_PIB_OJIC_SCOM2                              ,
+       RULL(0x0006D00A), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE6_JTG_PIB_OJSTAT                                  ,
+       RULL(0x0006D00B), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+
+REG64( PU_GPE6_JTG_PIB_OJTDI                                   ,
+       RULL(0x0006D00C), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE6_JTG_PIB_OJTDO                                   ,
+       RULL(0x0006D00D), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_NPU_CTL_LCO_CONFIG                                   ,
+       RULL(0x05011382), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_NTL0_LOW_PWR                                    ,
+       RULL(0x050110C2), SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU0_NTL1_LOW_PWR                                    ,
+       RULL(0x050110E2), SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU1_NTL0_LOW_PWR                                    ,
+       RULL(0x050111C2), SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU1_NTL1_LOW_PWR                                    ,
+       RULL(0x050111E2), SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_LOW_PWR                                    ,
+       RULL(0x050112C2), SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_LOW_PWR                                    ,
+       RULL(0x050112E2), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SM0_LOW_WATER                                   ,
+       RULL(0x05011011), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_LOW_WATER                                   ,
+       RULL(0x05011031), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_LOW_WATER                                   ,
+       RULL(0x05011051), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_LOW_WATER                                   ,
+       RULL(0x05011071), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_LOW_WATER                                   ,
+       RULL(0x05011111), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_LOW_WATER                                   ,
+       RULL(0x05011131), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_LOW_WATER                                   ,
+       RULL(0x05011151), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_LOW_WATER                                   ,
+       RULL(0x05011171), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_LOW_WATER                                   ,
+       RULL(0x05011211), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_LOW_WATER                                   ,
+       RULL(0x05011231), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_LOW_WATER                                   ,
+       RULL(0x05011251), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_LOW_WATER                                   ,
+       RULL(0x05011271), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PU_LPC_BASE_REG                                         ,
+       RULL(0x05022840), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_LPC_CMD_REG                                          ,
+       RULL(0x05022841), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_LPC_DATA_REG                                         ,
+       RULL(0x05022842), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PEC_0_STACK0_LSIBAR_REG                                 ,
+       RULL(0x04010C54), SH_UNT_PEC_0_STACK0, SH_ACS_SCOM      );
+REG64( PEC_0_STACK1_LSIBAR_REG                                 ,
+       RULL(0x04010C94), SH_UNT_PEC_0_STACK1, SH_ACS_SCOM      );
+REG64( PEC_0_STACK2_LSIBAR_REG                                 ,
+       RULL(0x04010CD4), SH_UNT_PEC_0_STACK2, SH_ACS_SCOM      );
+REG64( PEC_1_STACK0_LSIBAR_REG                                 ,
+       RULL(0x04011054), SH_UNT_PEC_1_STACK0, SH_ACS_SCOM      );
+REG64( PEC_1_STACK1_LSIBAR_REG                                 ,
+       RULL(0x04011094), SH_UNT_PEC_1_STACK1, SH_ACS_SCOM      );
+REG64( PEC_1_STACK2_LSIBAR_REG                                 ,
+       RULL(0x040110D4), SH_UNT_PEC_1_STACK2, SH_ACS_SCOM      );
+REG64( PEC_2_STACK0_LSIBAR_REG                                 ,
+       RULL(0x04011454), SH_UNT_PEC_2_STACK0, SH_ACS_SCOM      );
+REG64( PEC_2_STACK1_LSIBAR_REG                                 ,
+       RULL(0x04011494), SH_UNT_PEC_2_STACK1, SH_ACS_SCOM      );
+REG64( PEC_2_STACK2_LSIBAR_REG                                 ,
+       RULL(0x040114D4), SH_UNT_PEC_2_STACK2, SH_ACS_SCOM      );
+REG64( PEC_STACK0_LSIBAR_REG                                   ,
+       RULL(0x04010C54), SH_UNT_PEC_STACK0, SH_ACS_SCOM      );
+REG64( PEC_STACK1_LSIBAR_REG                                   ,
+       RULL(0x04010C94), SH_UNT_PEC_STACK1, SH_ACS_SCOM      );
+REG64( PEC_STACK2_LSIBAR_REG                                   ,
+       RULL(0x04010CD4), SH_UNT_PEC_STACK2, SH_ACS_SCOM      );
+
+REG64( PU_PIB2OPB0_LSTAT                                       ,
+       RULL(0x00020002), SH_UNT_PU_PIB2OPB0, SH_ACS_SCOM_RO   );
+REG64( PU_PIB2OPB1_LSTAT                                       ,
+       RULL(0x00020012), SH_UNT_PU_PIB2OPB1, SH_ACS_SCOM_RO   );
+
+REG64( PU_NPU0_NTL0_MASK1                                      ,
+       RULL(0x050110C5), SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU0_NTL1_MASK1                                      ,
+       RULL(0x050110E5), SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_MASK1                                       ,
+       RULL(0x05011013), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_MASK1                                       ,
+       RULL(0x05011033), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_MASK1                                       ,
+       RULL(0x05011053), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_MASK1                                       ,
+       RULL(0x05011073), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_NTL0_MASK1                                      ,
+       RULL(0x050111C5), SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU1_NTL1_MASK1                                      ,
+       RULL(0x050111E5), SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_MASK1                                       ,
+       RULL(0x05011113), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_MASK1                                       ,
+       RULL(0x05011133), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_MASK1                                       ,
+       RULL(0x05011153), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_MASK1                                       ,
+       RULL(0x05011173), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_MASK1                                      ,
+       RULL(0x050112C5), SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_MASK1                                      ,
+       RULL(0x050112E5), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_MASK1                                       ,
+       RULL(0x05011213), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_MASK1                                       ,
+       RULL(0x05011233), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_MASK1                                       ,
+       RULL(0x05011253), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_MASK1                                       ,
+       RULL(0x05011273), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_MASK2                                       ,
+       RULL(0x05011095), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_MASK2                                       ,
+       RULL(0x05011195), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_MASK2                                       ,
+       RULL(0x05011295), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU0_NTL0_MASK2                                      ,
+       RULL(0x050110C7), SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU0_NTL1_MASK2                                      ,
+       RULL(0x050110E7), SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_MASK2                                       ,
+       RULL(0x05011015), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_MASK2                                       ,
+       RULL(0x05011035), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_MASK2                                       ,
+       RULL(0x05011055), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_MASK2                                       ,
+       RULL(0x05011075), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_NTL0_MASK2                                      ,
+       RULL(0x050111C7), SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU1_NTL1_MASK2                                      ,
+       RULL(0x050111E7), SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_MASK2                                       ,
+       RULL(0x05011115), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_MASK2                                       ,
+       RULL(0x05011135), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_MASK2                                       ,
+       RULL(0x05011155), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_MASK2                                       ,
+       RULL(0x05011175), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_MASK2                                      ,
+       RULL(0x050112C7), SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_MASK2                                      ,
+       RULL(0x050112E7), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_MASK2                                       ,
+       RULL(0x05011215), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_MASK2                                       ,
+       RULL(0x05011235), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_MASK2                                       ,
+       RULL(0x05011255), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_MASK2                                       ,
+       RULL(0x05011275), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SM0_MAX_BAR                                     ,
+       RULL(0x0501100F), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_MAX_BAR                                     ,
+       RULL(0x0501102F), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_MAX_BAR                                     ,
+       RULL(0x0501104F), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_MAX_BAR                                     ,
+       RULL(0x0501106F), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_MAX_BAR                                     ,
+       RULL(0x0501110F), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_MAX_BAR                                     ,
+       RULL(0x0501112F), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_MAX_BAR                                     ,
+       RULL(0x0501114F), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_MAX_BAR                                     ,
+       RULL(0x0501116F), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_MAX_BAR                                     ,
+       RULL(0x0501120F), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_MAX_BAR                                     ,
+       RULL(0x0501122F), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_MAX_BAR                                     ,
+       RULL(0x0501124F), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_MAX_BAR                                     ,
+       RULL(0x0501126F), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PU_MCD_DBG                                              ,
+       RULL(0x03011413), SH_UNT          , SH_ACS_SCOM      );
+REG64( PU_MCD1_MCD_DBG                                         ,
+       RULL(0x03011013), SH_UNT_PU_MCD1  , SH_ACS_SCOM      );
+
+REG64( PU_MCD_ECAP                                             ,
+       RULL(0x03011412), SH_UNT          , SH_ACS_SCOM      );
+REG64( PU_MCD1_MCD_ECAP                                        ,
+       RULL(0x03011012), SH_UNT_PU_MCD1  , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_MIB_XIDCAC_OCI                                  ,
+       RULL(0xC00000D0), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_MIB_XIDCAC_SCOM                                 ,
+       RULL(0x0006001A), SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE1_MIB_XIDCAC_OCI                                  ,
+       RULL(0xC00100D0), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_MIB_XIDCAC_SCOM                                 ,
+       RULL(0x0006201A), SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE2_MIB_XIDCAC_OCI                                  ,
+       RULL(0xC00200D0), SH_UNT_PU_GPE2  , SH_ACS_OCI       );
+REG64( PU_GPE2_MIB_XIDCAC_SCOM                                 ,
+       RULL(0x0006401A), SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE3_MIB_XIDCAC_OCI                                  ,
+       RULL(0xC00300D0), SH_UNT_PU_GPE3  , SH_ACS_OCI       );
+REG64( PU_GPE3_MIB_XIDCAC_SCOM                                 ,
+       RULL(0x0006601A), SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO   );
+
+REG64( PU_MIB_XIICAC                                           ,
+       RULL(0x000E0009), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_MIB_XIICAC                                      ,
+       RULL(0x00060019), SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE1_MIB_XIICAC                                      ,
+       RULL(0x00062019), SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE2_MIB_XIICAC                                      ,
+       RULL(0x00064019), SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE3_MIB_XIICAC                                      ,
+       RULL(0x00066019), SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO   );
+
+REG64( PU_MIB_XIMEM                                            ,
+       RULL(0x000E0007), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_MIB_XIMEM                                       ,
+       RULL(0x00060017), SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE1_MIB_XIMEM                                       ,
+       RULL(0x00062017), SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE2_MIB_XIMEM                                       ,
+       RULL(0x00064017), SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE3_MIB_XIMEM                                       ,
+       RULL(0x00066017), SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO   );
+
+REG64( PU_MIB_XISGB                                            ,
+       RULL(0x000E0008), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_MIB_XISGB                                       ,
+       RULL(0x00060018), SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE1_MIB_XISGB                                       ,
+       RULL(0x00062018), SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE2_MIB_XISGB                                       ,
+       RULL(0x00064018), SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE3_MIB_XISGB                                       ,
+       RULL(0x00066018), SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO   );
+
+REG64( PU_MIB_XISIB                                            ,
+       RULL(0x000E0006), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_MIB_XISIB                                       ,
+       RULL(0x00060016), SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE1_MIB_XISIB                                       ,
+       RULL(0x00062016), SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE2_MIB_XISIB                                       ,
+       RULL(0x00064016), SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE3_MIB_XISIB                                       ,
+       RULL(0x00066016), SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO   );
+
+REG64( PEC_0_STACK0_MMIOBAR0_MASK_REG                          ,
+       RULL(0x04010C4F), SH_UNT_PEC_0_STACK0, SH_ACS_SCOM      );
+REG64( PEC_0_STACK1_MMIOBAR0_MASK_REG                          ,
+       RULL(0x04010C8F), SH_UNT_PEC_0_STACK1, SH_ACS_SCOM      );
+REG64( PEC_0_STACK2_MMIOBAR0_MASK_REG                          ,
+       RULL(0x04010CCF), SH_UNT_PEC_0_STACK2, SH_ACS_SCOM      );
+REG64( PEC_1_STACK0_MMIOBAR0_MASK_REG                          ,
+       RULL(0x0401104F), SH_UNT_PEC_1_STACK0, SH_ACS_SCOM      );
+REG64( PEC_1_STACK1_MMIOBAR0_MASK_REG                          ,
+       RULL(0x0401108F), SH_UNT_PEC_1_STACK1, SH_ACS_SCOM      );
+REG64( PEC_1_STACK2_MMIOBAR0_MASK_REG                          ,
+       RULL(0x040110CF), SH_UNT_PEC_1_STACK2, SH_ACS_SCOM      );
+REG64( PEC_2_STACK0_MMIOBAR0_MASK_REG                          ,
+       RULL(0x0401144F), SH_UNT_PEC_2_STACK0, SH_ACS_SCOM      );
+REG64( PEC_2_STACK1_MMIOBAR0_MASK_REG                          ,
+       RULL(0x0401148F), SH_UNT_PEC_2_STACK1, SH_ACS_SCOM      );
+REG64( PEC_2_STACK2_MMIOBAR0_MASK_REG                          ,
+       RULL(0x040114CF), SH_UNT_PEC_2_STACK2, SH_ACS_SCOM      );
+REG64( PEC_STACK0_MMIOBAR0_MASK_REG                            ,
+       RULL(0x04010C4F), SH_UNT_PEC_STACK0, SH_ACS_SCOM      );
+REG64( PEC_STACK1_MMIOBAR0_MASK_REG                            ,
+       RULL(0x04010C8F), SH_UNT_PEC_STACK1, SH_ACS_SCOM      );
+REG64( PEC_STACK2_MMIOBAR0_MASK_REG                            ,
+       RULL(0x04010CCF), SH_UNT_PEC_STACK2, SH_ACS_SCOM      );
+
+REG64( PEC_0_STACK0_MMIOBAR0_REG                               ,
+       RULL(0x04010C4E), SH_UNT_PEC_0_STACK0, SH_ACS_SCOM      );
+REG64( PEC_0_STACK1_MMIOBAR0_REG                               ,
+       RULL(0x04010C8E), SH_UNT_PEC_0_STACK1, SH_ACS_SCOM      );
+REG64( PEC_0_STACK2_MMIOBAR0_REG                               ,
+       RULL(0x04010CCE), SH_UNT_PEC_0_STACK2, SH_ACS_SCOM      );
+REG64( PEC_1_STACK0_MMIOBAR0_REG                               ,
+       RULL(0x0401104E), SH_UNT_PEC_1_STACK0, SH_ACS_SCOM      );
+REG64( PEC_1_STACK1_MMIOBAR0_REG                               ,
+       RULL(0x0401108E), SH_UNT_PEC_1_STACK1, SH_ACS_SCOM      );
+REG64( PEC_1_STACK2_MMIOBAR0_REG                               ,
+       RULL(0x040110CE), SH_UNT_PEC_1_STACK2, SH_ACS_SCOM      );
+REG64( PEC_2_STACK0_MMIOBAR0_REG                               ,
+       RULL(0x0401144E), SH_UNT_PEC_2_STACK0, SH_ACS_SCOM      );
+REG64( PEC_2_STACK1_MMIOBAR0_REG                               ,
+       RULL(0x0401148E), SH_UNT_PEC_2_STACK1, SH_ACS_SCOM      );
+REG64( PEC_2_STACK2_MMIOBAR0_REG                               ,
+       RULL(0x040114CE), SH_UNT_PEC_2_STACK2, SH_ACS_SCOM      );
+REG64( PEC_STACK0_MMIOBAR0_REG                                 ,
+       RULL(0x04010C4E), SH_UNT_PEC_STACK0, SH_ACS_SCOM      );
+REG64( PEC_STACK1_MMIOBAR0_REG                                 ,
+       RULL(0x04010C8E), SH_UNT_PEC_STACK1, SH_ACS_SCOM      );
+REG64( PEC_STACK2_MMIOBAR0_REG                                 ,
+       RULL(0x04010CCE), SH_UNT_PEC_STACK2, SH_ACS_SCOM      );
+
+REG64( PEC_0_STACK0_MMIOBAR1_MASK_REG                          ,
+       RULL(0x04010C51), SH_UNT_PEC_0_STACK0, SH_ACS_SCOM      );
+REG64( PEC_0_STACK1_MMIOBAR1_MASK_REG                          ,
+       RULL(0x04010C91), SH_UNT_PEC_0_STACK1, SH_ACS_SCOM      );
+REG64( PEC_0_STACK2_MMIOBAR1_MASK_REG                          ,
+       RULL(0x04010CD1), SH_UNT_PEC_0_STACK2, SH_ACS_SCOM      );
+REG64( PEC_1_STACK0_MMIOBAR1_MASK_REG                          ,
+       RULL(0x04011051), SH_UNT_PEC_1_STACK0, SH_ACS_SCOM      );
+REG64( PEC_1_STACK1_MMIOBAR1_MASK_REG                          ,
+       RULL(0x04011091), SH_UNT_PEC_1_STACK1, SH_ACS_SCOM      );
+REG64( PEC_1_STACK2_MMIOBAR1_MASK_REG                          ,
+       RULL(0x040110D1), SH_UNT_PEC_1_STACK2, SH_ACS_SCOM      );
+REG64( PEC_2_STACK0_MMIOBAR1_MASK_REG                          ,
+       RULL(0x04011451), SH_UNT_PEC_2_STACK0, SH_ACS_SCOM      );
+REG64( PEC_2_STACK1_MMIOBAR1_MASK_REG                          ,
+       RULL(0x04011491), SH_UNT_PEC_2_STACK1, SH_ACS_SCOM      );
+REG64( PEC_2_STACK2_MMIOBAR1_MASK_REG                          ,
+       RULL(0x040114D1), SH_UNT_PEC_2_STACK2, SH_ACS_SCOM      );
+REG64( PEC_STACK0_MMIOBAR1_MASK_REG                            ,
+       RULL(0x04010C51), SH_UNT_PEC_STACK0, SH_ACS_SCOM      );
+REG64( PEC_STACK1_MMIOBAR1_MASK_REG                            ,
+       RULL(0x04010C91), SH_UNT_PEC_STACK1, SH_ACS_SCOM      );
+REG64( PEC_STACK2_MMIOBAR1_MASK_REG                            ,
+       RULL(0x04010CD1), SH_UNT_PEC_STACK2, SH_ACS_SCOM      );
+
+REG64( PEC_0_STACK0_MMIOBAR1_REG                               ,
+       RULL(0x04010C50), SH_UNT_PEC_0_STACK0, SH_ACS_SCOM      );
+REG64( PEC_0_STACK1_MMIOBAR1_REG                               ,
+       RULL(0x04010C90), SH_UNT_PEC_0_STACK1, SH_ACS_SCOM      );
+REG64( PEC_0_STACK2_MMIOBAR1_REG                               ,
+       RULL(0x04010CD0), SH_UNT_PEC_0_STACK2, SH_ACS_SCOM      );
+REG64( PEC_1_STACK0_MMIOBAR1_REG                               ,
+       RULL(0x04011050), SH_UNT_PEC_1_STACK0, SH_ACS_SCOM      );
+REG64( PEC_1_STACK1_MMIOBAR1_REG                               ,
+       RULL(0x04011090), SH_UNT_PEC_1_STACK1, SH_ACS_SCOM      );
+REG64( PEC_1_STACK2_MMIOBAR1_REG                               ,
+       RULL(0x040110D0), SH_UNT_PEC_1_STACK2, SH_ACS_SCOM      );
+REG64( PEC_2_STACK0_MMIOBAR1_REG                               ,
+       RULL(0x04011450), SH_UNT_PEC_2_STACK0, SH_ACS_SCOM      );
+REG64( PEC_2_STACK1_MMIOBAR1_REG                               ,
+       RULL(0x04011490), SH_UNT_PEC_2_STACK1, SH_ACS_SCOM      );
+REG64( PEC_2_STACK2_MMIOBAR1_REG                               ,
+       RULL(0x040114D0), SH_UNT_PEC_2_STACK2, SH_ACS_SCOM      );
+REG64( PEC_STACK0_MMIOBAR1_REG                                 ,
+       RULL(0x04010C50), SH_UNT_PEC_STACK0, SH_ACS_SCOM      );
+REG64( PEC_STACK1_MMIOBAR1_REG                                 ,
+       RULL(0x04010C90), SH_UNT_PEC_STACK1, SH_ACS_SCOM      );
+REG64( PEC_STACK2_MMIOBAR1_REG                                 ,
+       RULL(0x04010CD0), SH_UNT_PEC_STACK2, SH_ACS_SCOM      );
+
+REG64( PU_MM_CFG_NMMU_CTL_MISC                                 ,
+       RULL(0x05012C49), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_MM_CFG_NMMU_CTL_SLB                                  ,
+       RULL(0x05012C4A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_MM_CFG_NMMU_CTL_SM                                   ,
+       RULL(0x05012C48), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_MM_CFG_NMMU_CTL_TLB                                  ,
+       RULL(0x05012C4B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_MM_CFG_NMMU_XLAT_CTL_REG0                            ,
+       RULL(0x05012C40), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_MM_CFG_NMMU_XLAT_CTL_REG1                            ,
+       RULL(0x05012C41), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_MM_CFG_NMMU_XLAT_CTL_REG2                            ,
+       RULL(0x05012C42), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_MM_NMMU_DBG_MODE                                     ,
+       RULL(0x05012C4F), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_MM_NMMU_ERR_INJ                                      ,
+       RULL(0x05012C4E), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_MM_NMMU_ERR_LOG                                      ,
+       RULL(0x05012C4D), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_MM_NMMU_FIR                                          ,
+       RULL(0x05012C4C), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_MODE_REGISTER                                        ,
+       RULL(0x00010008), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_MODE_REGISTER_B                                      ,
+       RULL(0x000A0006), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_MODE_REGISTER_C                                      ,
+       RULL(0x000A1006), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_MODE_REGISTER_D                                      ,
+       RULL(0x000A2006), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_MODE_REGISTER_E                                      ,
+       RULL(0x000A3006), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PEC_0_STACK0_MSIBAR_REG                                 ,
+       RULL(0x04010C53), SH_UNT_PEC_0_STACK0, SH_ACS_SCOM      );
+REG64( PEC_0_STACK1_MSIBAR_REG                                 ,
+       RULL(0x04010C93), SH_UNT_PEC_0_STACK1, SH_ACS_SCOM      );
+REG64( PEC_0_STACK2_MSIBAR_REG                                 ,
+       RULL(0x04010CD3), SH_UNT_PEC_0_STACK2, SH_ACS_SCOM      );
+REG64( PEC_1_STACK0_MSIBAR_REG                                 ,
+       RULL(0x04011053), SH_UNT_PEC_1_STACK0, SH_ACS_SCOM      );
+REG64( PEC_1_STACK1_MSIBAR_REG                                 ,
+       RULL(0x04011093), SH_UNT_PEC_1_STACK1, SH_ACS_SCOM      );
+REG64( PEC_1_STACK2_MSIBAR_REG                                 ,
+       RULL(0x040110D3), SH_UNT_PEC_1_STACK2, SH_ACS_SCOM      );
+REG64( PEC_2_STACK0_MSIBAR_REG                                 ,
+       RULL(0x04011453), SH_UNT_PEC_2_STACK0, SH_ACS_SCOM      );
+REG64( PEC_2_STACK1_MSIBAR_REG                                 ,
+       RULL(0x04011493), SH_UNT_PEC_2_STACK1, SH_ACS_SCOM      );
+REG64( PEC_2_STACK2_MSIBAR_REG                                 ,
+       RULL(0x040114D3), SH_UNT_PEC_2_STACK2, SH_ACS_SCOM      );
+REG64( PEC_STACK0_MSIBAR_REG                                   ,
+       RULL(0x04010C53), SH_UNT_PEC_STACK0, SH_ACS_SCOM      );
+REG64( PEC_STACK1_MSIBAR_REG                                   ,
+       RULL(0x04010C93), SH_UNT_PEC_STACK1, SH_ACS_SCOM      );
+REG64( PEC_STACK2_MSIBAR_REG                                   ,
+       RULL(0x04010CD3), SH_UNT_PEC_STACK2, SH_ACS_SCOM      );
+
+REG64( PU_NPU_CTL_NDLMUX_CONFIG                                ,
+       RULL(0x05011383), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SM0_NDT0_BAR                                    ,
+       RULL(0x0501100D), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_NDT0_BAR                                    ,
+       RULL(0x0501102D), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_NDT0_BAR                                    ,
+       RULL(0x0501104D), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_NDT0_BAR                                    ,
+       RULL(0x0501106D), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_NDT0_BAR                                    ,
+       RULL(0x0501110D), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_NDT0_BAR                                    ,
+       RULL(0x0501112D), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_NDT0_BAR                                    ,
+       RULL(0x0501114D), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_NDT0_BAR                                    ,
+       RULL(0x0501116D), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_NDT0_BAR                                    ,
+       RULL(0x0501120D), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_NDT0_BAR                                    ,
+       RULL(0x0501122D), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_NDT0_BAR                                    ,
+       RULL(0x0501124D), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_NDT0_BAR                                    ,
+       RULL(0x0501126D), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SM0_NDT1_BAR                                    ,
+       RULL(0x0501100E), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_NDT1_BAR                                    ,
+       RULL(0x0501102E), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_NDT1_BAR                                    ,
+       RULL(0x0501104E), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_NDT1_BAR                                    ,
+       RULL(0x0501106E), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_NDT1_BAR                                    ,
+       RULL(0x0501110E), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_NDT1_BAR                                    ,
+       RULL(0x0501112E), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_NDT1_BAR                                    ,
+       RULL(0x0501114E), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_NDT1_BAR                                    ,
+       RULL(0x0501116E), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_NDT1_BAR                                    ,
+       RULL(0x0501120E), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_NDT1_BAR                                    ,
+       RULL(0x0501122E), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_NDT1_BAR                                    ,
+       RULL(0x0501124E), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_NDT1_BAR                                    ,
+       RULL(0x0501126E), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PEC_NESTTRC_REG                                         ,
+       RULL(0x04010C03), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_NESTTRC_REG                                       ,
+       RULL(0x04010C03), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_NESTTRC_REG                                       ,
+       RULL(0x04011003), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_NESTTRC_REG                                       ,
+       RULL(0x04011403), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( PEC_0_STACK0_NFIRACTION0_REG                            ,
+       RULL(0x04010C46), SH_UNT_PEC_0_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK1_NFIRACTION0_REG                            ,
+       RULL(0x04010C86), SH_UNT_PEC_0_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK2_NFIRACTION0_REG                            ,
+       RULL(0x04010CC6), SH_UNT_PEC_0_STACK2, SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK0_NFIRACTION0_REG                            ,
+       RULL(0x04011046), SH_UNT_PEC_1_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK1_NFIRACTION0_REG                            ,
+       RULL(0x04011086), SH_UNT_PEC_1_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK2_NFIRACTION0_REG                            ,
+       RULL(0x040110C6), SH_UNT_PEC_1_STACK2, SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK0_NFIRACTION0_REG                            ,
+       RULL(0x04011446), SH_UNT_PEC_2_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK1_NFIRACTION0_REG                            ,
+       RULL(0x04011486), SH_UNT_PEC_2_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK2_NFIRACTION0_REG                            ,
+       RULL(0x040114C6), SH_UNT_PEC_2_STACK2, SH_ACS_SCOM_RW   );
+REG64( PEC_STACK0_NFIRACTION0_REG                              ,
+       RULL(0x04010C46), SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_STACK1_NFIRACTION0_REG                              ,
+       RULL(0x04010C86), SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_STACK2_NFIRACTION0_REG                              ,
+       RULL(0x04010CC6), SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW   );
+
+REG64( PEC_0_STACK0_NFIRACTION1_REG                            ,
+       RULL(0x04010C47), SH_UNT_PEC_0_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK1_NFIRACTION1_REG                            ,
+       RULL(0x04010C87), SH_UNT_PEC_0_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK2_NFIRACTION1_REG                            ,
+       RULL(0x04010CC7), SH_UNT_PEC_0_STACK2, SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK0_NFIRACTION1_REG                            ,
+       RULL(0x04011047), SH_UNT_PEC_1_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK1_NFIRACTION1_REG                            ,
+       RULL(0x04011087), SH_UNT_PEC_1_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK2_NFIRACTION1_REG                            ,
+       RULL(0x040110C7), SH_UNT_PEC_1_STACK2, SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK0_NFIRACTION1_REG                            ,
+       RULL(0x04011447), SH_UNT_PEC_2_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK1_NFIRACTION1_REG                            ,
+       RULL(0x04011487), SH_UNT_PEC_2_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK2_NFIRACTION1_REG                            ,
+       RULL(0x040114C7), SH_UNT_PEC_2_STACK2, SH_ACS_SCOM_RW   );
+REG64( PEC_STACK0_NFIRACTION1_REG                              ,
+       RULL(0x04010C47), SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_STACK1_NFIRACTION1_REG                              ,
+       RULL(0x04010C87), SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_STACK2_NFIRACTION1_REG                              ,
+       RULL(0x04010CC7), SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW   );
+
+REG64( PEC_0_STACK0_NFIRMASK_REG                               ,
+       RULL(0x04010C43), SH_UNT_PEC_0_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK0_NFIRMASK_REG_AND                           ,
+       RULL(0x04010C44), SH_UNT_PEC_0_STACK0, SH_ACS_SCOM1_AND );
+REG64( PEC_0_STACK0_NFIRMASK_REG_OR                            ,
+       RULL(0x04010C45), SH_UNT_PEC_0_STACK0, SH_ACS_SCOM2_OR  );
+REG64( PEC_0_STACK1_NFIRMASK_REG                               ,
+       RULL(0x04010C83), SH_UNT_PEC_0_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK1_NFIRMASK_REG_AND                           ,
+       RULL(0x04010C84), SH_UNT_PEC_0_STACK1, SH_ACS_SCOM1_AND );
+REG64( PEC_0_STACK1_NFIRMASK_REG_OR                            ,
+       RULL(0x04010C85), SH_UNT_PEC_0_STACK1, SH_ACS_SCOM2_OR  );
+REG64( PEC_0_STACK2_NFIRMASK_REG                               ,
+       RULL(0x04010CC3), SH_UNT_PEC_0_STACK2, SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK2_NFIRMASK_REG_AND                           ,
+       RULL(0x04010CC4), SH_UNT_PEC_0_STACK2, SH_ACS_SCOM1_AND );
+REG64( PEC_0_STACK2_NFIRMASK_REG_OR                            ,
+       RULL(0x04010CC5), SH_UNT_PEC_0_STACK2, SH_ACS_SCOM2_OR  );
+REG64( PEC_1_STACK0_NFIRMASK_REG                               ,
+       RULL(0x04011043), SH_UNT_PEC_1_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK0_NFIRMASK_REG_AND                           ,
+       RULL(0x04011044), SH_UNT_PEC_1_STACK0, SH_ACS_SCOM1_AND );
+REG64( PEC_1_STACK0_NFIRMASK_REG_OR                            ,
+       RULL(0x04011045), SH_UNT_PEC_1_STACK0, SH_ACS_SCOM2_OR  );
+REG64( PEC_1_STACK1_NFIRMASK_REG                               ,
+       RULL(0x04011083), SH_UNT_PEC_1_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK1_NFIRMASK_REG_AND                           ,
+       RULL(0x04011084), SH_UNT_PEC_1_STACK1, SH_ACS_SCOM1_AND );
+REG64( PEC_1_STACK1_NFIRMASK_REG_OR                            ,
+       RULL(0x04011085), SH_UNT_PEC_1_STACK1, SH_ACS_SCOM2_OR  );
+REG64( PEC_1_STACK2_NFIRMASK_REG                               ,
+       RULL(0x040110C3), SH_UNT_PEC_1_STACK2, SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK2_NFIRMASK_REG_AND                           ,
+       RULL(0x040110C4), SH_UNT_PEC_1_STACK2, SH_ACS_SCOM1_AND );
+REG64( PEC_1_STACK2_NFIRMASK_REG_OR                            ,
+       RULL(0x040110C5), SH_UNT_PEC_1_STACK2, SH_ACS_SCOM2_OR  );
+REG64( PEC_2_STACK0_NFIRMASK_REG                               ,
+       RULL(0x04011443), SH_UNT_PEC_2_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK0_NFIRMASK_REG_AND                           ,
+       RULL(0x04011444), SH_UNT_PEC_2_STACK0, SH_ACS_SCOM1_AND );
+REG64( PEC_2_STACK0_NFIRMASK_REG_OR                            ,
+       RULL(0x04011445), SH_UNT_PEC_2_STACK0, SH_ACS_SCOM2_OR  );
+REG64( PEC_2_STACK1_NFIRMASK_REG                               ,
+       RULL(0x04011483), SH_UNT_PEC_2_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK1_NFIRMASK_REG_AND                           ,
+       RULL(0x04011484), SH_UNT_PEC_2_STACK1, SH_ACS_SCOM1_AND );
+REG64( PEC_2_STACK1_NFIRMASK_REG_OR                            ,
+       RULL(0x04011485), SH_UNT_PEC_2_STACK1, SH_ACS_SCOM2_OR  );
+REG64( PEC_2_STACK2_NFIRMASK_REG                               ,
+       RULL(0x040114C3), SH_UNT_PEC_2_STACK2, SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK2_NFIRMASK_REG_AND                           ,
+       RULL(0x040114C4), SH_UNT_PEC_2_STACK2, SH_ACS_SCOM1_AND );
+REG64( PEC_2_STACK2_NFIRMASK_REG_OR                            ,
+       RULL(0x040114C5), SH_UNT_PEC_2_STACK2, SH_ACS_SCOM2_OR  );
+REG64( PEC_STACK0_NFIRMASK_REG                                 ,
+       RULL(0x04010C43), SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_STACK0_NFIRMASK_REG_AND                             ,
+       RULL(0x04010C44), SH_UNT_PEC_STACK0, SH_ACS_SCOM1_AND );
+REG64( PEC_STACK0_NFIRMASK_REG_OR                              ,
+       RULL(0x04010C45), SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR  );
+REG64( PEC_STACK1_NFIRMASK_REG                                 ,
+       RULL(0x04010C83), SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_STACK1_NFIRMASK_REG_AND                             ,
+       RULL(0x04010C84), SH_UNT_PEC_STACK1, SH_ACS_SCOM1_AND );
+REG64( PEC_STACK1_NFIRMASK_REG_OR                              ,
+       RULL(0x04010C85), SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR  );
+REG64( PEC_STACK2_NFIRMASK_REG                                 ,
+       RULL(0x04010CC3), SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW   );
+REG64( PEC_STACK2_NFIRMASK_REG_AND                             ,
+       RULL(0x04010CC4), SH_UNT_PEC_STACK2, SH_ACS_SCOM1_AND );
+REG64( PEC_STACK2_NFIRMASK_REG_OR                              ,
+       RULL(0x04010CC5), SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR  );
+
+REG64( PEC_0_STACK0_NFIRWOF_REG                                ,
+       RULL(0x04010C48), SH_UNT_PEC_0_STACK0, SH_ACS_SCOM_WCLRREG );
+REG64( PEC_0_STACK1_NFIRWOF_REG                                ,
+       RULL(0x04010C88), SH_UNT_PEC_0_STACK1, SH_ACS_SCOM_WCLRREG );
+REG64( PEC_0_STACK2_NFIRWOF_REG                                ,
+       RULL(0x04010CC8), SH_UNT_PEC_0_STACK2, SH_ACS_SCOM_WCLRREG );
+REG64( PEC_1_STACK0_NFIRWOF_REG                                ,
+       RULL(0x04011048), SH_UNT_PEC_1_STACK0, SH_ACS_SCOM_WCLRREG );
+REG64( PEC_1_STACK1_NFIRWOF_REG                                ,
+       RULL(0x04011088), SH_UNT_PEC_1_STACK1, SH_ACS_SCOM_WCLRREG );
+REG64( PEC_1_STACK2_NFIRWOF_REG                                ,
+       RULL(0x040110C8), SH_UNT_PEC_1_STACK2, SH_ACS_SCOM_WCLRREG );
+REG64( PEC_2_STACK0_NFIRWOF_REG                                ,
+       RULL(0x04011448), SH_UNT_PEC_2_STACK0, SH_ACS_SCOM_WCLRREG );
+REG64( PEC_2_STACK1_NFIRWOF_REG                                ,
+       RULL(0x04011488), SH_UNT_PEC_2_STACK1, SH_ACS_SCOM_WCLRREG );
+REG64( PEC_2_STACK2_NFIRWOF_REG                                ,
+       RULL(0x040114C8), SH_UNT_PEC_2_STACK2, SH_ACS_SCOM_WCLRREG );
+REG64( PEC_STACK0_NFIRWOF_REG                                  ,
+       RULL(0x04010C48), SH_UNT_PEC_STACK0, SH_ACS_SCOM_WCLRREG );
+REG64( PEC_STACK1_NFIRWOF_REG                                  ,
+       RULL(0x04010C88), SH_UNT_PEC_STACK1, SH_ACS_SCOM_WCLRREG );
+REG64( PEC_STACK2_NFIRWOF_REG                                  ,
+       RULL(0x04010CC8), SH_UNT_PEC_STACK2, SH_ACS_SCOM_WCLRREG );
+
+REG64( PEC_0_STACK0_NFIR_REG                                   ,
+       RULL(0x04010C40), SH_UNT_PEC_0_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK0_NFIR_REG_AND                               ,
+       RULL(0x04010C41), SH_UNT_PEC_0_STACK0, SH_ACS_SCOM1_AND );
+REG64( PEC_0_STACK0_NFIR_REG_OR                                ,
+       RULL(0x04010C42), SH_UNT_PEC_0_STACK0, SH_ACS_SCOM2_OR  );
+REG64( PEC_0_STACK1_NFIR_REG                                   ,
+       RULL(0x04010C80), SH_UNT_PEC_0_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK1_NFIR_REG_AND                               ,
+       RULL(0x04010C81), SH_UNT_PEC_0_STACK1, SH_ACS_SCOM1_AND );
+REG64( PEC_0_STACK1_NFIR_REG_OR                                ,
+       RULL(0x04010C82), SH_UNT_PEC_0_STACK1, SH_ACS_SCOM2_OR  );
+REG64( PEC_0_STACK2_NFIR_REG                                   ,
+       RULL(0x04010CC0), SH_UNT_PEC_0_STACK2, SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK2_NFIR_REG_AND                               ,
+       RULL(0x04010CC1), SH_UNT_PEC_0_STACK2, SH_ACS_SCOM1_AND );
+REG64( PEC_0_STACK2_NFIR_REG_OR                                ,
+       RULL(0x04010CC2), SH_UNT_PEC_0_STACK2, SH_ACS_SCOM2_OR  );
+REG64( PEC_1_STACK0_NFIR_REG                                   ,
+       RULL(0x04011040), SH_UNT_PEC_1_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK0_NFIR_REG_AND                               ,
+       RULL(0x04011041), SH_UNT_PEC_1_STACK0, SH_ACS_SCOM1_AND );
+REG64( PEC_1_STACK0_NFIR_REG_OR                                ,
+       RULL(0x04011042), SH_UNT_PEC_1_STACK0, SH_ACS_SCOM2_OR  );
+REG64( PEC_1_STACK1_NFIR_REG                                   ,
+       RULL(0x04011080), SH_UNT_PEC_1_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK1_NFIR_REG_AND                               ,
+       RULL(0x04011081), SH_UNT_PEC_1_STACK1, SH_ACS_SCOM1_AND );
+REG64( PEC_1_STACK1_NFIR_REG_OR                                ,
+       RULL(0x04011082), SH_UNT_PEC_1_STACK1, SH_ACS_SCOM2_OR  );
+REG64( PEC_1_STACK2_NFIR_REG                                   ,
+       RULL(0x040110C0), SH_UNT_PEC_1_STACK2, SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK2_NFIR_REG_AND                               ,
+       RULL(0x040110C1), SH_UNT_PEC_1_STACK2, SH_ACS_SCOM1_AND );
+REG64( PEC_1_STACK2_NFIR_REG_OR                                ,
+       RULL(0x040110C2), SH_UNT_PEC_1_STACK2, SH_ACS_SCOM2_OR  );
+REG64( PEC_2_STACK0_NFIR_REG                                   ,
+       RULL(0x04011440), SH_UNT_PEC_2_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK0_NFIR_REG_AND                               ,
+       RULL(0x04011441), SH_UNT_PEC_2_STACK0, SH_ACS_SCOM1_AND );
+REG64( PEC_2_STACK0_NFIR_REG_OR                                ,
+       RULL(0x04011442), SH_UNT_PEC_2_STACK0, SH_ACS_SCOM2_OR  );
+REG64( PEC_2_STACK1_NFIR_REG                                   ,
+       RULL(0x04011480), SH_UNT_PEC_2_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK1_NFIR_REG_AND                               ,
+       RULL(0x04011481), SH_UNT_PEC_2_STACK1, SH_ACS_SCOM1_AND );
+REG64( PEC_2_STACK1_NFIR_REG_OR                                ,
+       RULL(0x04011482), SH_UNT_PEC_2_STACK1, SH_ACS_SCOM2_OR  );
+REG64( PEC_2_STACK2_NFIR_REG                                   ,
+       RULL(0x040114C0), SH_UNT_PEC_2_STACK2, SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK2_NFIR_REG_AND                               ,
+       RULL(0x040114C1), SH_UNT_PEC_2_STACK2, SH_ACS_SCOM1_AND );
+REG64( PEC_2_STACK2_NFIR_REG_OR                                ,
+       RULL(0x040114C2), SH_UNT_PEC_2_STACK2, SH_ACS_SCOM2_OR  );
+REG64( PEC_STACK0_NFIR_REG                                     ,
+       RULL(0x04010C40), SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_STACK0_NFIR_REG_AND                                 ,
+       RULL(0x04010C41), SH_UNT_PEC_STACK0, SH_ACS_SCOM1_AND );
+REG64( PEC_STACK0_NFIR_REG_OR                                  ,
+       RULL(0x04010C42), SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR  );
+REG64( PEC_STACK1_NFIR_REG                                     ,
+       RULL(0x04010C80), SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_STACK1_NFIR_REG_AND                                 ,
+       RULL(0x04010C81), SH_UNT_PEC_STACK1, SH_ACS_SCOM1_AND );
+REG64( PEC_STACK1_NFIR_REG_OR                                  ,
+       RULL(0x04010C82), SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR  );
+REG64( PEC_STACK2_NFIR_REG                                     ,
+       RULL(0x04010CC0), SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW   );
+REG64( PEC_STACK2_NFIR_REG_AND                                 ,
+       RULL(0x04010CC1), SH_UNT_PEC_STACK2, SH_ACS_SCOM1_AND );
+REG64( PEC_STACK2_NFIR_REG_OR                                  ,
+       RULL(0x04010CC2), SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR  );
+
+REG64( PU_NOTRUST_BAR0                                         ,
+       RULL(0x05015F40), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NOTRUST_BAR0MASK                                     ,
+       RULL(0x05015F42), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NOTRUST_BAR1                                         ,
+       RULL(0x05015F41), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NOTRUST_BAR1MASK                                     ,
+       RULL(0x05015F43), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM0_NPU_AT_ECC                                   ,
+       RULL(0x05011300), SH_UNT_PU_NPU_SM0, SH_ACS_SCOM      );
+
+REG64( PU_NXCQ_PB_MODE_REG                                     ,
+       RULL(0x02011095), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_AS_CMD_CFG                                        ,
+       RULL(0x05012C21), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_COP_CFG                                           ,
+       RULL(0x05012C0F), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_CQ_FIR_ACTION0_REG                                ,
+       RULL(0x02011086), SH_UNT          , SH_ACS_SCOM_RW   ); //DUPS: 05012C06,
+
+REG64( PU_NX_CQ_FIR_ACTION1_REG                                ,
+       RULL(0x02011087), SH_UNT          , SH_ACS_SCOM_RW   ); //DUPS: 05012C07,
+
+REG64( PU_NX_CQ_FIR_MASK_REG                                   ,
+       RULL(0x02011083), SH_UNT          , SH_ACS_SCOM_RW   ); //DUPS: 05012C03,
+REG64( PU_NX_CQ_FIR_MASK_REG_AND                               ,
+       RULL(0x02011084), SH_UNT          , SH_ACS_SCOM1_AND ); //DUPS: 05012C04,
+REG64( PU_NX_CQ_FIR_MASK_REG_OR                                ,
+       RULL(0x02011085), SH_UNT          , SH_ACS_SCOM2_OR  ); //DUPS: 05012C05,
+
+REG64( PU_NX_CQ_FIR_REG                                        ,
+       RULL(0x02011080), SH_UNT          , SH_ACS_SCOM_RW   ); //DUPS: 05012C00,
+REG64( PU_NX_CQ_FIR_REG_AND                                    ,
+       RULL(0x02011081), SH_UNT          , SH_ACS_SCOM1_AND ); //DUPS: 05012C01,
+REG64( PU_NX_CQ_FIR_REG_OR                                     ,
+       RULL(0x02011082), SH_UNT          , SH_ACS_SCOM2_OR  ); //DUPS: 05012C02,
+
+REG64( PU_NX_CQ_FIR_WOF_REG                                    ,
+       RULL(0x02011088), SH_UNT          , SH_ACS_SCOM_WCLRREG ); //DUPS: 05012C08,
+
+REG64( PU_NX_DEBUGMUX_CTRL                                     ,
+       RULL(0x0201110A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_NX_DEBUG_SNAPSHOT_0                                  ,
+       RULL(0x020110A4), SH_UNT          , SH_ACS_SCOM      ); //DUPS: 05012C24,
+
+REG64( PU_NX_DEBUG_SNAPSHOT_1                                  ,
+       RULL(0x020110A5), SH_UNT          , SH_ACS_SCOM      ); //DUPS: 05012C25,
+
+REG64( PU_NX_DMA_ENG_FIR                                       ,
+       RULL(0x02011100), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_NX_DMA_ENG_FIR_AND                                   ,
+       RULL(0x02011101), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_NX_DMA_ENG_FIR_OR                                    ,
+       RULL(0x02011102), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_NX_DMA_ENG_FIR_ACTION0                               ,
+       RULL(0x02011106), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_NX_DMA_ENG_FIR_ACTION1                               ,
+       RULL(0x02011107), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_NX_DMA_ENG_FIR_MASK                                  ,
+       RULL(0x02011103), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_NX_DMA_ENG_FIR_MASK_AND                              ,
+       RULL(0x02011104), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_NX_DMA_ENG_FIR_MASK_OR                               ,
+       RULL(0x02011105), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_NX_DMA_ENG_FIR_WOF                                   ,
+       RULL(0x02011108), SH_UNT          , SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_NX_EPSILON_COUNTER_VALUE                             ,
+       RULL(0x0201109D), SH_UNT          , SH_ACS_SCOM      ); //DUPS: 05012C1D,
+
+REG64( PU_NX_ERRORINJ_CTRL                                     ,
+       RULL(0x0201110C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_NX_FOREIGN_F_BAR0                                    ,
+       RULL(0x05012C1B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_NX_FOREIGN_F_BAR1                                    ,
+       RULL(0x05012C1C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_NX_FOREIGN_L_BAR0                                    ,
+       RULL(0x05012C19), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_NX_FOREIGN_L_BAR1                                    ,
+       RULL(0x05012C1A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_NX_GROUP_BAR0                                        ,
+       RULL(0x05012C17), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_NX_GROUP_BAR1                                        ,
+       RULL(0x05012C18), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_NX_ICS_CFG_REG                                       ,
+       RULL(0x05012C13), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_ICS_CFG_REG2                                      ,
+       RULL(0x05012C14), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_MISC_CONTROL_REG                                  ,
+       RULL(0x020110A8), SH_UNT          , SH_ACS_SCOM      ); //DUPS: 05012C28,
+
+REG64( PU_NX_MMIO_BAR                                          ,
+       RULL(0x0201108D), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_NODAL_BAR0                                        ,
+       RULL(0x05012C15), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_NX_NODAL_BAR1                                        ,
+       RULL(0x05012C16), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_NX_PB_DEBUG_REG                                      ,
+       RULL(0x02011090), SH_UNT          , SH_ACS_SCOM      ); //DUPS: 05012C10,
+
+REG64( PU_NX_PB_ECC_REG                                        ,
+       RULL(0x02011091), SH_UNT          , SH_ACS_SCOM      ); //DUPS: 05012C11,
+
+REG64( PU_NX_PB_ERR_RPT_0                                      ,
+       RULL(0x020110A2), SH_UNT          , SH_ACS_SCOM      ); //DUPS: 05012C22,
+
+REG64( PU_NX_PB_ERR_RPT_1                                      ,
+       RULL(0x020110A1), SH_UNT          , SH_ACS_SCOM      ); //DUPS: 05012C23,
+
+REG64( PU_NX_PMU0_CONTROL_REG                                  ,
+       RULL(0x020110A6), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_PMU0_COUNTER_REG                                  ,
+       RULL(0x020110A7), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_PMU1_CONTROL_REG                                  ,
+       RULL(0x020110A9), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_PMU1_COUNTER_REG                                  ,
+       RULL(0x020110AA), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_PMU_CONTROL_REG                                   ,
+       RULL(0x05012C26), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_PMU_COUNTER_REG                                   ,
+       RULL(0x05012C27), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_RNG_BYPASS                                        ,
+       RULL(0x020110E4), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_RNG_CFG                                           ,
+       RULL(0x020110E0), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_RNG_RDELAY                                        ,
+       RULL(0x020110E5), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_RNG_RESET                                         ,
+       RULL(0x020110E6), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_RNG_ST0                                           ,
+       RULL(0x020110E1), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_RNG_ST1                                           ,
+       RULL(0x020110E2), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_RNG_ST2                                           ,
+       RULL(0x020110E3), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_TRIGGER_CTRL                                      ,
+       RULL(0x0201110B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_CCSR_OCI                                ,
+       RULL(0xC0060480), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_OCB_OCI_CCSR_OCI1                               ,
+       RULL(0xC0060488), SH_UNT_PU_GPE0  , SH_ACS_OCI1      );
+REG64( PU_GPE0_OCB_OCI_CCSR_OCI2                               ,
+       RULL(0xC0060490), SH_UNT_PU_GPE0  , SH_ACS_OCI2      );
+REG64( PU_GPE6_OCB_OCI_CCSR                                    ,
+       RULL(0x0006C090), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE6_OCB_OCI_CCSR_CLEAR                              ,
+       RULL(0x0006C091), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_OCI_CCSR_OR                                 ,
+       RULL(0x0006C092), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE0_OCB_OCI_G0ISR0_OCI                              ,
+       RULL(0xC0060320), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_G0ISR0                                  ,
+       RULL(0x0006C064), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_OCB_OCI_G0ISR1_OCI                              ,
+       RULL(0xC00603A0), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_G0ISR1                                  ,
+       RULL(0x0006C074), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_OCB_OCI_G1ISR0_OCI                              ,
+       RULL(0xC0060328), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_G1ISR0                                  ,
+       RULL(0x0006C065), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_OCB_OCI_G1ISR1_OCI                              ,
+       RULL(0xC00603A8), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_G1ISR1                                  ,
+       RULL(0x0006C075), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_OCB_OCI_G2ISR0_OCI                              ,
+       RULL(0xC0060330), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_G2ISR0                                  ,
+       RULL(0x0006C066), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_OCB_OCI_G2ISR1_OCI                              ,
+       RULL(0xC00603B0), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_G2ISR1                                  ,
+       RULL(0x0006C076), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_OCB_OCI_G3ISR0_OCI                              ,
+       RULL(0xC0060338), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_G3ISR0                                  ,
+       RULL(0x0006C067), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_OCB_OCI_G3ISR1_OCI                              ,
+       RULL(0xC00603B8), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_G3ISR1                                  ,
+       RULL(0x0006C077), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE1_OCB_OCI_O2SCMD0A_OCI                            ,
+       RULL(0xC0063838), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SCMD0A                                ,
+       RULL(0x0006C707), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SCMD0B_OCI                            ,
+       RULL(0xC00638B8), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SCMD0B                                ,
+       RULL(0x0006C717), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SCMD1A_OCI                            ,
+       RULL(0xC0063938), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SCMD1A                                ,
+       RULL(0x0006C727), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SCMD1B_OCI                            ,
+       RULL(0xC00639B8), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SCMD1B                                ,
+       RULL(0x0006C737), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SCTRL10A_OCI                          ,
+       RULL(0xC0063810), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SCTRL10A                              ,
+       RULL(0x0006C702), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SCTRL10B_OCI                          ,
+       RULL(0xC0063890), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SCTRL10B                              ,
+       RULL(0x0006C712), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SCTRL11A_OCI                          ,
+       RULL(0xC0063910), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SCTRL11A                              ,
+       RULL(0x0006C722), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SCTRL11B_OCI                          ,
+       RULL(0xC0063990), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SCTRL11B                              ,
+       RULL(0x0006C732), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SCTRL20A_OCI                          ,
+       RULL(0xC0063818), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SCTRL20A                              ,
+       RULL(0x0006C703), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SCTRL20B_OCI                          ,
+       RULL(0xC0063898), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SCTRL20B                              ,
+       RULL(0x0006C713), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SCTRL21A_OCI                          ,
+       RULL(0xC0063918), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SCTRL21A                              ,
+       RULL(0x0006C723), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SCTRL21B_OCI                          ,
+       RULL(0xC0063998), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SCTRL21B                              ,
+       RULL(0x0006C733), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SCTRLF0A_OCI                          ,
+       RULL(0xC0063800), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SCTRLF0A                              ,
+       RULL(0x0006C700), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SCTRLF0B_OCI                          ,
+       RULL(0xC0063880), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SCTRLF0B                              ,
+       RULL(0x0006C710), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SCTRLF1A_OCI                          ,
+       RULL(0xC0063900), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SCTRLF1A                              ,
+       RULL(0x0006C720), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SCTRLF1B_OCI                          ,
+       RULL(0xC0063980), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SCTRLF1B                              ,
+       RULL(0x0006C730), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SCTRLS0A_OCI                          ,
+       RULL(0xC0063808), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SCTRLS0A                              ,
+       RULL(0x0006C701), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SCTRLS0B_OCI                          ,
+       RULL(0xC0063888), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SCTRLS0B                              ,
+       RULL(0x0006C711), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SCTRLS1A_OCI                          ,
+       RULL(0xC0063908), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SCTRLS1A                              ,
+       RULL(0x0006C721), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SCTRLS1B_OCI                          ,
+       RULL(0xC0063988), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SCTRLS1B                              ,
+       RULL(0x0006C731), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SRD0A_OCI                             ,
+       RULL(0xC0063848), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SRD0A                                 ,
+       RULL(0x0006C709), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE1_OCB_OCI_O2SRD0B_OCI                             ,
+       RULL(0xC00638C8), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SRD0B                                 ,
+       RULL(0x0006C719), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE1_OCB_OCI_O2SRD1A_OCI                             ,
+       RULL(0xC0063948), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SRD1A                                 ,
+       RULL(0x0006C729), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE1_OCB_OCI_O2SRD1B_OCI                             ,
+       RULL(0xC00639C8), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SRD1B                                 ,
+       RULL(0x0006C739), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE1_OCB_OCI_O2SST0A_OCI                             ,
+       RULL(0xC0063830), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SST0A                                 ,
+       RULL(0x0006C706), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE1_OCB_OCI_O2SST0B_OCI                             ,
+       RULL(0xC00638B0), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SST0B                                 ,
+       RULL(0x0006C716), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE1_OCB_OCI_O2SST1A_OCI                             ,
+       RULL(0xC0063930), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SST1A                                 ,
+       RULL(0x0006C726), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE1_OCB_OCI_O2SST1B_OCI                             ,
+       RULL(0xC00639B0), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SST1B                                 ,
+       RULL(0x0006C736), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE1_OCB_OCI_O2SWD0A_OCI                             ,
+       RULL(0xC0063840), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SWD0A                                 ,
+       RULL(0x0006C708), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SWD0B_OCI                             ,
+       RULL(0xC00638C0), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SWD0B                                 ,
+       RULL(0x0006C718), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SWD1A_OCI                             ,
+       RULL(0xC0063940), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SWD1A                                 ,
+       RULL(0x0006C728), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_OCB_OCI_O2SWD1B_OCI                             ,
+       RULL(0xC00639C0), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_O2SWD1B                                 ,
+       RULL(0x0006C738), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCBLWCR0_OCI                            ,
+       RULL(0xC0061040), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBLWCR0                                ,
+       RULL(0x0006C208), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCBLWCR1_OCI                            ,
+       RULL(0xC00610C0), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBLWCR1                                ,
+       RULL(0x0006C218), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCBLWCR2_OCI                            ,
+       RULL(0xC0061140), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBLWCR2                                ,
+       RULL(0x0006C228), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCBLWCR3_OCI                            ,
+       RULL(0xC00611C0), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBLWCR3                                ,
+       RULL(0x0006C238), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCBLWSBR0_OCI                           ,
+       RULL(0xC0061060), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBLWSBR0                               ,
+       RULL(0x0006C20C), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCBLWSBR1_OCI                           ,
+       RULL(0xC00610E0), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBLWSBR1                               ,
+       RULL(0x0006C21C), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCBLWSBR2_OCI                           ,
+       RULL(0xC0061160), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBLWSBR2                               ,
+       RULL(0x0006C22C), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCBLWSBR3_OCI                           ,
+       RULL(0xC00611E0), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBLWSBR3                               ,
+       RULL(0x0006C23C), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCBLWSR0_OCI                            ,
+       RULL(0xC0061050), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBLWSR0                                ,
+       RULL(0x0006C20A), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_OCB_OCI_OCBLWSR1_OCI                            ,
+       RULL(0xC00610D0), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBLWSR1                                ,
+       RULL(0x0006C21A), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_OCB_OCI_OCBLWSR2_OCI                            ,
+       RULL(0xC0061150), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBLWSR2                                ,
+       RULL(0x0006C22A), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_OCB_OCI_OCBLWSR3_OCI                            ,
+       RULL(0xC00611D0), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBLWSR3                                ,
+       RULL(0x0006C23A), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_OCB_OCI_OCBSES0_OCI                             ,
+       RULL(0xC0061030), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSES0                                 ,
+       RULL(0x0006C206), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCBSES1_OCI                             ,
+       RULL(0xC00610B0), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSES1                                 ,
+       RULL(0x0006C216), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCBSES2_OCI                             ,
+       RULL(0xC0061130), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSES2                                 ,
+       RULL(0x0006C226), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCBSES3_OCI                             ,
+       RULL(0xC00611B0), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSES3                                 ,
+       RULL(0x0006C236), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCBSHBR0_OCI                            ,
+       RULL(0xC0061018), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSHBR0                                ,
+       RULL(0x0006C203), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCBSHBR1_OCI                            ,
+       RULL(0xC0061098), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSHBR1                                ,
+       RULL(0x0006C213), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCBSHBR2_OCI                            ,
+       RULL(0xC0061118), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSHBR2                                ,
+       RULL(0x0006C223), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCBSHBR3_OCI                            ,
+       RULL(0xC0061198), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSHBR3                                ,
+       RULL(0x0006C233), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCBSHCS0_OCI                            ,
+       RULL(0xC0061020), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSHCS0                                ,
+       RULL(0x0006C204), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_OCB_OCI_OCBSHCS1_OCI                            ,
+       RULL(0xC00610A0), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSHCS1                                ,
+       RULL(0x0006C214), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_OCB_OCI_OCBSHCS2_OCI                            ,
+       RULL(0xC0061120), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSHCS2                                ,
+       RULL(0x0006C224), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_OCB_OCI_OCBSHCS3_OCI                            ,
+       RULL(0xC00611A0), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSHCS3                                ,
+       RULL(0x0006C234), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_OCB_OCI_OCBSHI0_OCI                             ,
+       RULL(0xC0061028), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSHI0                                 ,
+       RULL(0x0006C205), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_OCB_OCI_OCBSHI1_OCI                             ,
+       RULL(0xC00610A8), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSHI1                                 ,
+       RULL(0x0006C215), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_OCB_OCI_OCBSHI2_OCI                             ,
+       RULL(0xC0061128), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSHI2                                 ,
+       RULL(0x0006C225), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_OCB_OCI_OCBSHI3_OCI                             ,
+       RULL(0xC00611A8), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSHI3                                 ,
+       RULL(0x0006C235), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_OCB_OCI_OCBSLBR0_OCI                            ,
+       RULL(0xC0061000), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSLBR0                                ,
+       RULL(0x0006C200), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCBSLBR1_OCI                            ,
+       RULL(0xC0061080), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSLBR1                                ,
+       RULL(0x0006C210), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCBSLBR2_OCI                            ,
+       RULL(0xC0061100), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSLBR2                                ,
+       RULL(0x0006C220), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCBSLBR3_OCI                            ,
+       RULL(0xC0061180), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSLBR3                                ,
+       RULL(0x0006C230), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCBSLCS0_OCI                            ,
+       RULL(0xC0061008), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSLCS0                                ,
+       RULL(0x0006C201), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_OCB_OCI_OCBSLCS1_OCI                            ,
+       RULL(0xC0061088), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSLCS1                                ,
+       RULL(0x0006C211), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_OCB_OCI_OCBSLCS2_OCI                            ,
+       RULL(0xC0061108), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSLCS2                                ,
+       RULL(0x0006C221), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_OCB_OCI_OCBSLCS3_OCI                            ,
+       RULL(0xC0061188), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSLCS3                                ,
+       RULL(0x0006C231), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_OCB_OCI_OCBSLI0_OCI                             ,
+       RULL(0xC0061010), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSLI0                                 ,
+       RULL(0x0006C202), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_OCB_OCI_OCBSLI1_OCI                             ,
+       RULL(0xC0061090), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSLI1                                 ,
+       RULL(0x0006C212), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_OCB_OCI_OCBSLI2_OCI                             ,
+       RULL(0xC0061110), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSLI2                                 ,
+       RULL(0x0006C222), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_OCB_OCI_OCBSLI3_OCI                             ,
+       RULL(0xC0061190), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCBSLI3                                 ,
+       RULL(0x0006C232), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_OCB_OCI_OCCFLG_OCI                              ,
+       RULL(0xC0060450), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_OCB_OCI_OCCFLG_OCI1                             ,
+       RULL(0xC0060458), SH_UNT_PU_GPE0  , SH_ACS_OCI1      );
+REG64( PU_GPE0_OCB_OCI_OCCFLG_OCI2                             ,
+       RULL(0xC0060460), SH_UNT_PU_GPE0  , SH_ACS_OCI2      );
+REG64( PU_GPE6_OCB_OCI_OCCFLG                                  ,
+       RULL(0x0006C08A), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE6_OCB_OCI_OCCFLG_CLEAR                            ,
+       RULL(0x0006C08B), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_OCI_OCCFLG_OR                               ,
+       RULL(0x0006C08C), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE0_OCB_OCI_OCCHBR_OCI                              ,
+       RULL(0xC0060478), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCCHBR                                  ,
+       RULL(0x0006C08F), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCCMISC_OCI                             ,
+       RULL(0xC0060400), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_OCB_OCI_OCCMISC_OCI1                            ,
+       RULL(0xC0060408), SH_UNT_PU_GPE0  , SH_ACS_OCI1      );
+REG64( PU_GPE0_OCB_OCI_OCCMISC_OCI2                            ,
+       RULL(0xC0060410), SH_UNT_PU_GPE0  , SH_ACS_OCI2      );
+REG64( PU_GPE6_OCB_OCI_OCCMISC_SCOM                            ,
+       RULL(0x0006C080), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+REG64( PU_GPE6_OCB_OCI_OCCMISC_SCOM1                           ,
+       RULL(0x0006C081), SH_UNT_PU_GPE6  , SH_ACS_SCOM1     );
+REG64( PU_GPE6_OCB_OCI_OCCMISC_SCOM2                           ,
+       RULL(0x0006C082), SH_UNT_PU_GPE6  , SH_ACS_SCOM2     );
+
+REG64( PU_GPE0_OCB_OCI_OCCS0_OCI                               ,
+       RULL(0xC0060430), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCCS0                                   ,
+       RULL(0x0006C086), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCCS1_OCI                               ,
+       RULL(0xC0060438), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCCS1                                   ,
+       RULL(0x0006C087), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCCS2_OCI                               ,
+       RULL(0xC0060440), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCCS2                                   ,
+       RULL(0x0006C088), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCICFG_OCI                              ,
+       RULL(0xC0060428), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCICFG                                  ,
+       RULL(0x0006C085), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OCISR0_OCI                              ,
+       RULL(0xC0060308), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCISR0                                  ,
+       RULL(0x0006C061), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_OCB_OCI_OCISR1_OCI                              ,
+       RULL(0xC0060388), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OCISR1                                  ,
+       RULL(0x0006C071), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_OCB_OCI_ODISR0_OCI                              ,
+       RULL(0xC0060318), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_ODISR0                                  ,
+       RULL(0x0006C063), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_OCB_OCI_ODISR1_OCI                              ,
+       RULL(0xC0060398), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_ODISR1                                  ,
+       RULL(0x0006C073), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_OCB_OCI_OEHDR_OCI                               ,
+       RULL(0xC0060420), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OEHDR                                   ,
+       RULL(0x0006C084), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_OCB_OCI_OHTMCR_OCI                              ,
+       RULL(0xC0060418), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OHTMCR                                  ,
+       RULL(0x0006C083), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_OCB_OCI_OIEPR0_OCI                              ,
+       RULL(0xC0060060), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_OCB_OCI_OIEPR0_OCI1                             ,
+       RULL(0xC0060068), SH_UNT_PU_GPE0  , SH_ACS_OCI1      );
+REG64( PU_GPE0_OCB_OCI_OIEPR0_OCI2                             ,
+       RULL(0xC0060070), SH_UNT_PU_GPE0  , SH_ACS_OCI2      );
+REG64( PU_GPE6_OCB_OCI_OIEPR0                                  ,
+       RULL(0x0006C00C), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE6_OCB_OCI_OIEPR0_CLEAR                            ,
+       RULL(0x0006C00D), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_OCI_OIEPR0_OR                               ,
+       RULL(0x0006C00E), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE0_OCB_OCI_OIEPR1_OCI                              ,
+       RULL(0xC0060160), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_OCB_OCI_OIEPR1_OCI1                             ,
+       RULL(0xC0060168), SH_UNT_PU_GPE0  , SH_ACS_OCI1      );
+REG64( PU_GPE0_OCB_OCI_OIEPR1_OCI2                             ,
+       RULL(0xC0060170), SH_UNT_PU_GPE0  , SH_ACS_OCI2      );
+REG64( PU_GPE6_OCB_OCI_OIEPR1                                  ,
+       RULL(0x0006C02C), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE6_OCB_OCI_OIEPR1_CLEAR                            ,
+       RULL(0x0006C02D), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_OCI_OIEPR1_OR                               ,
+       RULL(0x0006C02E), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE0_OCB_OCI_OIMR0_OCI                               ,
+       RULL(0xC0060020), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_OCB_OCI_OIMR0_OCI1                              ,
+       RULL(0xC0060028), SH_UNT_PU_GPE0  , SH_ACS_OCI1      );
+REG64( PU_GPE0_OCB_OCI_OIMR0_OCI2                              ,
+       RULL(0xC0060030), SH_UNT_PU_GPE0  , SH_ACS_OCI2      );
+REG64( PU_GPE6_OCB_OCI_OIMR0                                   ,
+       RULL(0x0006C004), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE6_OCB_OCI_OIMR0_CLEAR                             ,
+       RULL(0x0006C005), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_OCI_OIMR0_OR                                ,
+       RULL(0x0006C006), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE0_OCB_OCI_OIMR1_OCI                               ,
+       RULL(0xC0060120), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_OCB_OCI_OIMR1_OCI1                              ,
+       RULL(0xC0060128), SH_UNT_PU_GPE0  , SH_ACS_OCI1      );
+REG64( PU_GPE0_OCB_OCI_OIMR1_OCI2                              ,
+       RULL(0xC0060130), SH_UNT_PU_GPE0  , SH_ACS_OCI2      );
+REG64( PU_GPE6_OCB_OCI_OIMR1                                   ,
+       RULL(0x0006C024), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE6_OCB_OCI_OIMR1_CLEAR                             ,
+       RULL(0x0006C025), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_OCI_OIMR1_OR                                ,
+       RULL(0x0006C026), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE0_OCB_OCI_OIRR0A_OCI                              ,
+       RULL(0xC0060200), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_OCB_OCI_OIRR0A_OCI1                             ,
+       RULL(0xC0060208), SH_UNT_PU_GPE0  , SH_ACS_OCI1      );
+REG64( PU_GPE0_OCB_OCI_OIRR0A_OCI2                             ,
+       RULL(0xC0060210), SH_UNT_PU_GPE0  , SH_ACS_OCI2      );
+REG64( PU_GPE6_OCB_OCI_OIRR0A                                  ,
+       RULL(0x0006C040), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE6_OCB_OCI_OIRR0A_CLEAR                            ,
+       RULL(0x0006C041), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_OCI_OIRR0A_OR                               ,
+       RULL(0x0006C042), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE0_OCB_OCI_OIRR0B_OCI                              ,
+       RULL(0xC0060220), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_OCB_OCI_OIRR0B_OCI1                             ,
+       RULL(0xC0060228), SH_UNT_PU_GPE0  , SH_ACS_OCI1      );
+REG64( PU_GPE0_OCB_OCI_OIRR0B_OCI2                             ,
+       RULL(0xC0060230), SH_UNT_PU_GPE0  , SH_ACS_OCI2      );
+REG64( PU_GPE6_OCB_OCI_OIRR0B                                  ,
+       RULL(0x0006C044), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE6_OCB_OCI_OIRR0B_CLEAR                            ,
+       RULL(0x0006C045), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_OCI_OIRR0B_OR                               ,
+       RULL(0x0006C046), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE0_OCB_OCI_OIRR0C_OCI                              ,
+       RULL(0xC0060240), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_OCB_OCI_OIRR0C_OCI1                             ,
+       RULL(0xC0060248), SH_UNT_PU_GPE0  , SH_ACS_OCI1      );
+REG64( PU_GPE0_OCB_OCI_OIRR0C_OCI2                             ,
+       RULL(0xC0060250), SH_UNT_PU_GPE0  , SH_ACS_OCI2      );
+REG64( PU_GPE6_OCB_OCI_OIRR0C                                  ,
+       RULL(0x0006C048), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE6_OCB_OCI_OIRR0C_CLEAR                            ,
+       RULL(0x0006C049), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_OCI_OIRR0C_OR                               ,
+       RULL(0x0006C04A), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE0_OCB_OCI_OIRR1A_OCI                              ,
+       RULL(0xC0060280), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_OCB_OCI_OIRR1A_OCI1                             ,
+       RULL(0xC0060288), SH_UNT_PU_GPE0  , SH_ACS_OCI1      );
+REG64( PU_GPE0_OCB_OCI_OIRR1A_OCI2                             ,
+       RULL(0xC0060290), SH_UNT_PU_GPE0  , SH_ACS_OCI2      );
+REG64( PU_GPE6_OCB_OCI_OIRR1A                                  ,
+       RULL(0x0006C050), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE6_OCB_OCI_OIRR1A_CLEAR                            ,
+       RULL(0x0006C051), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_OCI_OIRR1A_OR                               ,
+       RULL(0x0006C052), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE0_OCB_OCI_OIRR1B_OCI                              ,
+       RULL(0xC00602A0), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_OCB_OCI_OIRR1B_OCI1                             ,
+       RULL(0xC00602A8), SH_UNT_PU_GPE0  , SH_ACS_OCI1      );
+REG64( PU_GPE0_OCB_OCI_OIRR1B_OCI2                             ,
+       RULL(0xC00602B0), SH_UNT_PU_GPE0  , SH_ACS_OCI2      );
+REG64( PU_GPE6_OCB_OCI_OIRR1B                                  ,
+       RULL(0x0006C054), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE6_OCB_OCI_OIRR1B_CLEAR                            ,
+       RULL(0x0006C055), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_OCI_OIRR1B_OR                               ,
+       RULL(0x0006C056), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE0_OCB_OCI_OIRR1C_OCI                              ,
+       RULL(0xC00602C0), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_OCB_OCI_OIRR1C_OCI1                             ,
+       RULL(0xC00602C8), SH_UNT_PU_GPE0  , SH_ACS_OCI1      );
+REG64( PU_GPE0_OCB_OCI_OIRR1C_OCI2                             ,
+       RULL(0xC00602D0), SH_UNT_PU_GPE0  , SH_ACS_OCI2      );
+REG64( PU_GPE6_OCB_OCI_OIRR1C                                  ,
+       RULL(0x0006C058), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE6_OCB_OCI_OIRR1C_CLEAR                            ,
+       RULL(0x0006C059), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_OCI_OIRR1C_OR                               ,
+       RULL(0x0006C05A), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE0_OCB_OCI_OISR0_OCI                               ,
+       RULL(0xC0060000), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_OCB_OCI_OISR0_OCI1                              ,
+       RULL(0xC0060008), SH_UNT_PU_GPE0  , SH_ACS_OCI1      );
+REG64( PU_GPE0_OCB_OCI_OISR0_OCI2                              ,
+       RULL(0xC0060010), SH_UNT_PU_GPE0  , SH_ACS_OCI2      );
+REG64( PU_GPE6_OCB_OCI_OISR0_RO                                ,
+       RULL(0x0006C000), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OISR0_CLEAR                             ,
+       RULL(0x0006C001), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_OCI_OISR0_OR                                ,
+       RULL(0x0006C002), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE0_OCB_OCI_OISR1_OCI                               ,
+       RULL(0xC0060100), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_OCB_OCI_OISR1_OCI1                              ,
+       RULL(0xC0060108), SH_UNT_PU_GPE0  , SH_ACS_OCI1      );
+REG64( PU_GPE0_OCB_OCI_OISR1_OCI2                              ,
+       RULL(0xC0060110), SH_UNT_PU_GPE0  , SH_ACS_OCI2      );
+REG64( PU_GPE6_OCB_OCI_OISR1_RO                                ,
+       RULL(0x0006C020), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OISR1_CLEAR                             ,
+       RULL(0x0006C021), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_OCI_OISR1_OR                                ,
+       RULL(0x0006C022), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE0_OCB_OCI_OITR0_OCI                               ,
+       RULL(0xC0060040), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_OCB_OCI_OITR0_OCI1                              ,
+       RULL(0xC0060048), SH_UNT_PU_GPE0  , SH_ACS_OCI1      );
+REG64( PU_GPE0_OCB_OCI_OITR0_OCI2                              ,
+       RULL(0xC0060050), SH_UNT_PU_GPE0  , SH_ACS_OCI2      );
+REG64( PU_GPE6_OCB_OCI_OITR0                                   ,
+       RULL(0x0006C008), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE6_OCB_OCI_OITR0_CLEAR                             ,
+       RULL(0x0006C009), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_OCI_OITR0_OR                                ,
+       RULL(0x0006C00A), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE0_OCB_OCI_OITR1_OCI                               ,
+       RULL(0xC0060140), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_OCB_OCI_OITR1_OCI1                              ,
+       RULL(0xC0060148), SH_UNT_PU_GPE0  , SH_ACS_OCI1      );
+REG64( PU_GPE0_OCB_OCI_OITR1_OCI2                              ,
+       RULL(0xC0060150), SH_UNT_PU_GPE0  , SH_ACS_OCI2      );
+REG64( PU_GPE6_OCB_OCI_OITR1                                   ,
+       RULL(0x0006C028), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE6_OCB_OCI_OITR1_CLEAR                             ,
+       RULL(0x0006C029), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_OCI_OITR1_OR                                ,
+       RULL(0x0006C02A), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE0_OCB_OCI_ONISR0_OCI                              ,
+       RULL(0xC0060300), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_ONISR0                                  ,
+       RULL(0x0006C060), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_OCB_OCI_ONISR1_OCI                              ,
+       RULL(0xC0060380), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_ONISR1                                  ,
+       RULL(0x0006C070), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C0_OCI                             ,
+       RULL(0xC0062000), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C0_OCI1                            ,
+       RULL(0xC0062800), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C0_SCOM                            ,
+       RULL(0x0006C400), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C0_SCOM1                           ,
+       RULL(0x0006C500), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C1_OCI                             ,
+       RULL(0xC0062008), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C1_OCI1                            ,
+       RULL(0xC0062808), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C1_SCOM                            ,
+       RULL(0x0006C401), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C1_SCOM1                           ,
+       RULL(0x0006C501), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C10_OCI                            ,
+       RULL(0xC0062050), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C10_OCI1                           ,
+       RULL(0xC0062850), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C10_SCOM                           ,
+       RULL(0x0006C40A), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C10_SCOM1                          ,
+       RULL(0x0006C50A), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C11_OCI                            ,
+       RULL(0xC0062058), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C11_OCI1                           ,
+       RULL(0xC0062858), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C11_SCOM                           ,
+       RULL(0x0006C40B), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C11_SCOM1                          ,
+       RULL(0x0006C50B), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C12_OCI                            ,
+       RULL(0xC0062060), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C12_OCI1                           ,
+       RULL(0xC0062860), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C12_SCOM                           ,
+       RULL(0x0006C40C), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C12_SCOM1                          ,
+       RULL(0x0006C50C), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C13_OCI                            ,
+       RULL(0xC0062068), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C13_OCI1                           ,
+       RULL(0xC0062868), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C13_SCOM                           ,
+       RULL(0x0006C40D), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C13_SCOM1                          ,
+       RULL(0x0006C50D), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C14_OCI                            ,
+       RULL(0xC0062070), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C14_OCI1                           ,
+       RULL(0xC0062870), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C14_SCOM                           ,
+       RULL(0x0006C40E), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C14_SCOM1                          ,
+       RULL(0x0006C50E), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C15_OCI                            ,
+       RULL(0xC0062078), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C15_OCI1                           ,
+       RULL(0xC0062878), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C15_SCOM                           ,
+       RULL(0x0006C40F), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C15_SCOM1                          ,
+       RULL(0x0006C50F), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C16_OCI                            ,
+       RULL(0xC0062080), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C16_OCI1                           ,
+       RULL(0xC0062880), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C16_SCOM                           ,
+       RULL(0x0006C410), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C16_SCOM1                          ,
+       RULL(0x0006C510), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C17_OCI                            ,
+       RULL(0xC0062088), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C17_OCI1                           ,
+       RULL(0xC0062888), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C17_SCOM                           ,
+       RULL(0x0006C411), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C17_SCOM1                          ,
+       RULL(0x0006C511), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C18_OCI                            ,
+       RULL(0xC0062090), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C18_OCI1                           ,
+       RULL(0xC0062890), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C18_SCOM                           ,
+       RULL(0x0006C412), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C18_SCOM1                          ,
+       RULL(0x0006C512), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C19_OCI                            ,
+       RULL(0xC0062098), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C19_OCI1                           ,
+       RULL(0xC0062898), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C19_SCOM                           ,
+       RULL(0x0006C413), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C19_SCOM1                          ,
+       RULL(0x0006C513), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C2_OCI                             ,
+       RULL(0xC0062010), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C2_OCI1                            ,
+       RULL(0xC0062810), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C2_SCOM                            ,
+       RULL(0x0006C402), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C2_SCOM1                           ,
+       RULL(0x0006C502), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C20_OCI                            ,
+       RULL(0xC00620A0), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C20_OCI1                           ,
+       RULL(0xC00628A0), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C20_SCOM                           ,
+       RULL(0x0006C414), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C20_SCOM1                          ,
+       RULL(0x0006C514), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C21_OCI                            ,
+       RULL(0xC00620A8), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C21_OCI1                           ,
+       RULL(0xC00628A8), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C21_SCOM                           ,
+       RULL(0x0006C415), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C21_SCOM1                          ,
+       RULL(0x0006C515), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C22_OCI                            ,
+       RULL(0xC00620B0), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C22_OCI1                           ,
+       RULL(0xC00628B0), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C22_SCOM                           ,
+       RULL(0x0006C416), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C22_SCOM1                          ,
+       RULL(0x0006C516), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C23_OCI                            ,
+       RULL(0xC00620B8), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C23_OCI1                           ,
+       RULL(0xC00628B8), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C23_SCOM                           ,
+       RULL(0x0006C417), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C23_SCOM1                          ,
+       RULL(0x0006C517), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C3_OCI                             ,
+       RULL(0xC0062018), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C3_OCI1                            ,
+       RULL(0xC0062818), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C3_SCOM                            ,
+       RULL(0x0006C403), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C3_SCOM1                           ,
+       RULL(0x0006C503), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C4_OCI                             ,
+       RULL(0xC0062020), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C4_OCI1                            ,
+       RULL(0xC0062820), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C4_SCOM                            ,
+       RULL(0x0006C404), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C4_SCOM1                           ,
+       RULL(0x0006C504), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C5_OCI                             ,
+       RULL(0xC0062028), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C5_OCI1                            ,
+       RULL(0xC0062828), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C5_SCOM                            ,
+       RULL(0x0006C405), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C5_SCOM1                           ,
+       RULL(0x0006C505), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C6_OCI                             ,
+       RULL(0xC0062030), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C6_OCI1                            ,
+       RULL(0xC0062830), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C6_SCOM                            ,
+       RULL(0x0006C406), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C6_SCOM1                           ,
+       RULL(0x0006C506), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C7_OCI                             ,
+       RULL(0xC0062038), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C7_OCI1                            ,
+       RULL(0xC0062838), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C7_SCOM                            ,
+       RULL(0x0006C407), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C7_SCOM1                           ,
+       RULL(0x0006C507), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C8_OCI                             ,
+       RULL(0xC0062040), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C8_OCI1                            ,
+       RULL(0xC0062840), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C8_SCOM                            ,
+       RULL(0x0006C408), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C8_SCOM1                           ,
+       RULL(0x0006C508), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0C9_OCI                             ,
+       RULL(0xC0062048), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0C9_OCI1                            ,
+       RULL(0xC0062848), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0C9_SCOM                            ,
+       RULL(0x0006C409), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0C9_SCOM1                           ,
+       RULL(0x0006C509), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT0PRA_OCI                            ,
+       RULL(0xC0063000), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT0PRA_OCI1                           ,
+       RULL(0xC0063008), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT0PRA_RO                             ,
+       RULL(0x0006C600), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT0PRA_CLEAR                          ,
+       RULL(0x0006C601), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C0_OCI                             ,
+       RULL(0xC0062100), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C0_OCI1                            ,
+       RULL(0xC0062900), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C0_SCOM                            ,
+       RULL(0x0006C420), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C0_SCOM1                           ,
+       RULL(0x0006C520), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C1_OCI                             ,
+       RULL(0xC0062108), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C1_OCI1                            ,
+       RULL(0xC0062908), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C1_SCOM                            ,
+       RULL(0x0006C421), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C1_SCOM1                           ,
+       RULL(0x0006C521), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C10_OCI                            ,
+       RULL(0xC0062150), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C10_OCI1                           ,
+       RULL(0xC0062950), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C10_SCOM                           ,
+       RULL(0x0006C42A), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C10_SCOM1                          ,
+       RULL(0x0006C52A), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C11_OCI                            ,
+       RULL(0xC0062158), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C11_OCI1                           ,
+       RULL(0xC0062958), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C11_SCOM                           ,
+       RULL(0x0006C42B), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C11_SCOM1                          ,
+       RULL(0x0006C52B), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C12_OCI                            ,
+       RULL(0xC0062160), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C12_OCI1                           ,
+       RULL(0xC0062960), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C12_SCOM                           ,
+       RULL(0x0006C42C), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C12_SCOM1                          ,
+       RULL(0x0006C52C), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C13_OCI                            ,
+       RULL(0xC0062168), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C13_OCI1                           ,
+       RULL(0xC0062968), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C13_SCOM                           ,
+       RULL(0x0006C42D), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C13_SCOM1                          ,
+       RULL(0x0006C52D), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C14_OCI                            ,
+       RULL(0xC0062170), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C14_OCI1                           ,
+       RULL(0xC0062970), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C14_SCOM                           ,
+       RULL(0x0006C42E), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C14_SCOM1                          ,
+       RULL(0x0006C52E), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C15_OCI                            ,
+       RULL(0xC0062178), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C15_OCI1                           ,
+       RULL(0xC0062978), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C15_SCOM                           ,
+       RULL(0x0006C42F), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C15_SCOM1                          ,
+       RULL(0x0006C52F), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C16_OCI                            ,
+       RULL(0xC0062180), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C16_OCI1                           ,
+       RULL(0xC0062980), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C16_SCOM                           ,
+       RULL(0x0006C430), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C16_SCOM1                          ,
+       RULL(0x0006C530), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C17_OCI                            ,
+       RULL(0xC0062188), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C17_OCI1                           ,
+       RULL(0xC0062988), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C17_SCOM                           ,
+       RULL(0x0006C431), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C17_SCOM1                          ,
+       RULL(0x0006C531), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C18_OCI                            ,
+       RULL(0xC0062190), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C18_OCI1                           ,
+       RULL(0xC0062990), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C18_SCOM                           ,
+       RULL(0x0006C432), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C18_SCOM1                          ,
+       RULL(0x0006C532), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C19_OCI                            ,
+       RULL(0xC0062198), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C19_OCI1                           ,
+       RULL(0xC0062998), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C19_SCOM                           ,
+       RULL(0x0006C433), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C19_SCOM1                          ,
+       RULL(0x0006C533), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C2_OCI                             ,
+       RULL(0xC0062110), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C2_OCI1                            ,
+       RULL(0xC0062910), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C2_SCOM                            ,
+       RULL(0x0006C422), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C2_SCOM1                           ,
+       RULL(0x0006C522), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C20_OCI                            ,
+       RULL(0xC00621A0), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C20_OCI1                           ,
+       RULL(0xC00629A0), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C20_SCOM                           ,
+       RULL(0x0006C434), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C20_SCOM1                          ,
+       RULL(0x0006C534), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C21_OCI                            ,
+       RULL(0xC00621A8), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C21_OCI1                           ,
+       RULL(0xC00629A8), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C21_SCOM                           ,
+       RULL(0x0006C435), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C21_SCOM1                          ,
+       RULL(0x0006C535), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C22_OCI                            ,
+       RULL(0xC00621B0), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C22_OCI1                           ,
+       RULL(0xC00629B0), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C22_SCOM                           ,
+       RULL(0x0006C436), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C22_SCOM1                          ,
+       RULL(0x0006C536), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C23_OCI                            ,
+       RULL(0xC00621B8), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C23_OCI1                           ,
+       RULL(0xC00629B8), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C23_SCOM                           ,
+       RULL(0x0006C437), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C23_SCOM1                          ,
+       RULL(0x0006C537), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C3_OCI                             ,
+       RULL(0xC0062118), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C3_OCI1                            ,
+       RULL(0xC0062918), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C3_SCOM                            ,
+       RULL(0x0006C423), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C3_SCOM1                           ,
+       RULL(0x0006C523), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C4_OCI                             ,
+       RULL(0xC0062120), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C4_OCI1                            ,
+       RULL(0xC0062920), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C4_SCOM                            ,
+       RULL(0x0006C424), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C4_SCOM1                           ,
+       RULL(0x0006C524), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C5_OCI                             ,
+       RULL(0xC0062128), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C5_OCI1                            ,
+       RULL(0xC0062928), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C5_SCOM                            ,
+       RULL(0x0006C425), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C5_SCOM1                           ,
+       RULL(0x0006C525), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C6_OCI                             ,
+       RULL(0xC0062130), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C6_OCI1                            ,
+       RULL(0xC0062930), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C6_SCOM                            ,
+       RULL(0x0006C426), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C6_SCOM1                           ,
+       RULL(0x0006C526), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C7_OCI                             ,
+       RULL(0xC0062138), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C7_OCI1                            ,
+       RULL(0xC0062938), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C7_SCOM                            ,
+       RULL(0x0006C427), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C7_SCOM1                           ,
+       RULL(0x0006C527), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C8_OCI                             ,
+       RULL(0xC0062140), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C8_OCI1                            ,
+       RULL(0xC0062940), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C8_SCOM                            ,
+       RULL(0x0006C428), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C8_SCOM1                           ,
+       RULL(0x0006C528), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1C9_OCI                             ,
+       RULL(0xC0062148), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1C9_OCI1                            ,
+       RULL(0xC0062948), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1C9_SCOM                            ,
+       RULL(0x0006C429), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1C9_SCOM1                           ,
+       RULL(0x0006C529), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT1PRA_OCI                            ,
+       RULL(0xC0063100), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT1PRA_OCI1                           ,
+       RULL(0xC0063108), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT1PRA_RO                             ,
+       RULL(0x0006C620), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT1PRA_CLEAR                          ,
+       RULL(0x0006C621), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C0_OCI                             ,
+       RULL(0xC0062200), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C0_OCI1                            ,
+       RULL(0xC0062A00), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C0_SCOM                            ,
+       RULL(0x0006C440), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C0_SCOM1                           ,
+       RULL(0x0006C540), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C1_OCI                             ,
+       RULL(0xC0062208), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C1_OCI1                            ,
+       RULL(0xC0062A08), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C1_SCOM                            ,
+       RULL(0x0006C441), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C1_SCOM1                           ,
+       RULL(0x0006C541), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C10_OCI                            ,
+       RULL(0xC0062250), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C10_OCI1                           ,
+       RULL(0xC0062A50), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C10_SCOM                           ,
+       RULL(0x0006C44A), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C10_SCOM1                          ,
+       RULL(0x0006C54A), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C11_OCI                            ,
+       RULL(0xC0062258), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C11_OCI1                           ,
+       RULL(0xC0062A58), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C11_SCOM                           ,
+       RULL(0x0006C44B), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C11_SCOM1                          ,
+       RULL(0x0006C54B), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C12_OCI                            ,
+       RULL(0xC0062260), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C12_OCI1                           ,
+       RULL(0xC0062A60), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C12_SCOM                           ,
+       RULL(0x0006C44C), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C12_SCOM1                          ,
+       RULL(0x0006C54C), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C13_OCI                            ,
+       RULL(0xC0062268), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C13_OCI1                           ,
+       RULL(0xC0062A68), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C13_SCOM                           ,
+       RULL(0x0006C44D), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C13_SCOM1                          ,
+       RULL(0x0006C54D), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C14_OCI                            ,
+       RULL(0xC0062270), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C14_OCI1                           ,
+       RULL(0xC0062A70), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C14_SCOM                           ,
+       RULL(0x0006C44E), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C14_SCOM1                          ,
+       RULL(0x0006C54E), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C15_OCI                            ,
+       RULL(0xC0062278), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C15_OCI1                           ,
+       RULL(0xC0062A78), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C15_SCOM                           ,
+       RULL(0x0006C44F), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C15_SCOM1                          ,
+       RULL(0x0006C54F), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C16_OCI                            ,
+       RULL(0xC0062280), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C16_OCI1                           ,
+       RULL(0xC0062A80), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C16_SCOM                           ,
+       RULL(0x0006C450), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C16_SCOM1                          ,
+       RULL(0x0006C550), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C17_OCI                            ,
+       RULL(0xC0062288), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C17_OCI1                           ,
+       RULL(0xC0062A88), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C17_SCOM                           ,
+       RULL(0x0006C451), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C17_SCOM1                          ,
+       RULL(0x0006C551), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C18_OCI                            ,
+       RULL(0xC0062290), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C18_OCI1                           ,
+       RULL(0xC0062A90), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C18_SCOM                           ,
+       RULL(0x0006C452), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C18_SCOM1                          ,
+       RULL(0x0006C552), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C19_OCI                            ,
+       RULL(0xC0062298), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C19_OCI1                           ,
+       RULL(0xC0062A98), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C19_SCOM                           ,
+       RULL(0x0006C453), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C19_SCOM1                          ,
+       RULL(0x0006C553), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C2_OCI                             ,
+       RULL(0xC0062210), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C2_OCI1                            ,
+       RULL(0xC0062A10), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C2_SCOM                            ,
+       RULL(0x0006C442), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C2_SCOM1                           ,
+       RULL(0x0006C542), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C20_OCI                            ,
+       RULL(0xC00622A0), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C20_OCI1                           ,
+       RULL(0xC0062AA0), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C20_SCOM                           ,
+       RULL(0x0006C454), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C20_SCOM1                          ,
+       RULL(0x0006C554), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C21_OCI                            ,
+       RULL(0xC00622A8), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C21_OCI1                           ,
+       RULL(0xC0062AA8), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C21_SCOM                           ,
+       RULL(0x0006C455), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C21_SCOM1                          ,
+       RULL(0x0006C555), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C22_OCI                            ,
+       RULL(0xC00622B0), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C22_OCI1                           ,
+       RULL(0xC0062AB0), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C22_SCOM                           ,
+       RULL(0x0006C456), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C22_SCOM1                          ,
+       RULL(0x0006C556), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C23_OCI                            ,
+       RULL(0xC00622B8), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C23_OCI1                           ,
+       RULL(0xC0062AB8), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C23_SCOM                           ,
+       RULL(0x0006C457), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C23_SCOM1                          ,
+       RULL(0x0006C557), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C3_OCI                             ,
+       RULL(0xC0062218), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C3_OCI1                            ,
+       RULL(0xC0062A18), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C3_SCOM                            ,
+       RULL(0x0006C443), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C3_SCOM1                           ,
+       RULL(0x0006C543), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C4_OCI                             ,
+       RULL(0xC0062220), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C4_OCI1                            ,
+       RULL(0xC0062A20), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C4_SCOM                            ,
+       RULL(0x0006C444), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C4_SCOM1                           ,
+       RULL(0x0006C544), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C5_OCI                             ,
+       RULL(0xC0062228), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C5_OCI1                            ,
+       RULL(0xC0062A28), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C5_SCOM                            ,
+       RULL(0x0006C445), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C5_SCOM1                           ,
+       RULL(0x0006C545), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C6_OCI                             ,
+       RULL(0xC0062230), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C6_OCI1                            ,
+       RULL(0xC0062A30), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C6_SCOM                            ,
+       RULL(0x0006C446), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C6_SCOM1                           ,
+       RULL(0x0006C546), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C7_OCI                             ,
+       RULL(0xC0062238), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C7_OCI1                            ,
+       RULL(0xC0062A38), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C7_SCOM                            ,
+       RULL(0x0006C447), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C7_SCOM1                           ,
+       RULL(0x0006C547), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C8_OCI                             ,
+       RULL(0xC0062240), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C8_OCI1                            ,
+       RULL(0xC0062A40), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C8_SCOM                            ,
+       RULL(0x0006C448), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C8_SCOM1                           ,
+       RULL(0x0006C548), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2C9_OCI                             ,
+       RULL(0xC0062248), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2C9_OCI1                            ,
+       RULL(0xC0062A48), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2C9_SCOM                            ,
+       RULL(0x0006C449), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2C9_SCOM1                           ,
+       RULL(0x0006C549), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT2PRA_OCI                            ,
+       RULL(0xC0063200), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT2PRA_OCI1                           ,
+       RULL(0xC0063208), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT2PRA_RO                             ,
+       RULL(0x0006C640), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT2PRA_CLEAR                          ,
+       RULL(0x0006C641), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C0_OCI                             ,
+       RULL(0xC0062300), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C0_OCI1                            ,
+       RULL(0xC0062B00), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C0_SCOM                            ,
+       RULL(0x0006C460), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C0_SCOM1                           ,
+       RULL(0x0006C560), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C1_OCI                             ,
+       RULL(0xC0062308), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C1_OCI1                            ,
+       RULL(0xC0062B08), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C1_SCOM                            ,
+       RULL(0x0006C461), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C1_SCOM1                           ,
+       RULL(0x0006C561), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C10_OCI                            ,
+       RULL(0xC0062350), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C10_OCI1                           ,
+       RULL(0xC0062B50), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C10_SCOM                           ,
+       RULL(0x0006C46A), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C10_SCOM1                          ,
+       RULL(0x0006C56A), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C11_OCI                            ,
+       RULL(0xC0062358), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C11_OCI1                           ,
+       RULL(0xC0062B58), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C11_SCOM                           ,
+       RULL(0x0006C46B), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C11_SCOM1                          ,
+       RULL(0x0006C56B), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C12_OCI                            ,
+       RULL(0xC0062360), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C12_OCI1                           ,
+       RULL(0xC0062B60), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C12_SCOM                           ,
+       RULL(0x0006C46C), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C12_SCOM1                          ,
+       RULL(0x0006C56C), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C13_OCI                            ,
+       RULL(0xC0062368), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C13_OCI1                           ,
+       RULL(0xC0062B68), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C13_SCOM                           ,
+       RULL(0x0006C46D), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C13_SCOM1                          ,
+       RULL(0x0006C56D), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C14_OCI                            ,
+       RULL(0xC0062370), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C14_OCI1                           ,
+       RULL(0xC0062B70), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C14_SCOM                           ,
+       RULL(0x0006C46E), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C14_SCOM1                          ,
+       RULL(0x0006C56E), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C15_OCI                            ,
+       RULL(0xC0062378), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C15_OCI1                           ,
+       RULL(0xC0062B78), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C15_SCOM                           ,
+       RULL(0x0006C46F), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C15_SCOM1                          ,
+       RULL(0x0006C56F), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C16_OCI                            ,
+       RULL(0xC0062380), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C16_OCI1                           ,
+       RULL(0xC0062B80), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C16_SCOM                           ,
+       RULL(0x0006C470), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C16_SCOM1                          ,
+       RULL(0x0006C570), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C17_OCI                            ,
+       RULL(0xC0062388), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C17_OCI1                           ,
+       RULL(0xC0062B88), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C17_SCOM                           ,
+       RULL(0x0006C471), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C17_SCOM1                          ,
+       RULL(0x0006C571), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C18_OCI                            ,
+       RULL(0xC0062390), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C18_OCI1                           ,
+       RULL(0xC0062B90), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C18_SCOM                           ,
+       RULL(0x0006C472), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C18_SCOM1                          ,
+       RULL(0x0006C572), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C19_OCI                            ,
+       RULL(0xC0062398), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C19_OCI1                           ,
+       RULL(0xC0062B98), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C19_SCOM                           ,
+       RULL(0x0006C473), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C19_SCOM1                          ,
+       RULL(0x0006C573), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C2_OCI                             ,
+       RULL(0xC0062310), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C2_OCI1                            ,
+       RULL(0xC0062B10), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C2_SCOM                            ,
+       RULL(0x0006C462), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C2_SCOM1                           ,
+       RULL(0x0006C562), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C20_OCI                            ,
+       RULL(0xC00623A0), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C20_OCI1                           ,
+       RULL(0xC0062BA0), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C20_SCOM                           ,
+       RULL(0x0006C474), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C20_SCOM1                          ,
+       RULL(0x0006C574), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C21_OCI                            ,
+       RULL(0xC00623A8), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C21_OCI1                           ,
+       RULL(0xC0062BA8), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C21_SCOM                           ,
+       RULL(0x0006C475), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C21_SCOM1                          ,
+       RULL(0x0006C575), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C22_OCI                            ,
+       RULL(0xC00623B0), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C22_OCI1                           ,
+       RULL(0xC0062BB0), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C22_SCOM                           ,
+       RULL(0x0006C476), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C22_SCOM1                          ,
+       RULL(0x0006C576), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C23_OCI                            ,
+       RULL(0xC00623B8), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C23_OCI1                           ,
+       RULL(0xC0062BB8), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C23_SCOM                           ,
+       RULL(0x0006C477), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C23_SCOM1                          ,
+       RULL(0x0006C577), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C3_OCI                             ,
+       RULL(0xC0062318), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C3_OCI1                            ,
+       RULL(0xC0062B18), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C3_SCOM                            ,
+       RULL(0x0006C463), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C3_SCOM1                           ,
+       RULL(0x0006C563), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C4_OCI                             ,
+       RULL(0xC0062320), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C4_OCI1                            ,
+       RULL(0xC0062B20), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C4_SCOM                            ,
+       RULL(0x0006C464), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C4_SCOM1                           ,
+       RULL(0x0006C564), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C5_OCI                             ,
+       RULL(0xC0062328), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C5_OCI1                            ,
+       RULL(0xC0062B28), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C5_SCOM                            ,
+       RULL(0x0006C465), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C5_SCOM1                           ,
+       RULL(0x0006C565), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C6_OCI                             ,
+       RULL(0xC0062330), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C6_OCI1                            ,
+       RULL(0xC0062B30), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C6_SCOM                            ,
+       RULL(0x0006C466), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C6_SCOM1                           ,
+       RULL(0x0006C566), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C7_OCI                             ,
+       RULL(0xC0062338), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C7_OCI1                            ,
+       RULL(0xC0062B38), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C7_SCOM                            ,
+       RULL(0x0006C467), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C7_SCOM1                           ,
+       RULL(0x0006C567), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C8_OCI                             ,
+       RULL(0xC0062340), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C8_OCI1                            ,
+       RULL(0xC0062B40), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C8_SCOM                            ,
+       RULL(0x0006C468), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C8_SCOM1                           ,
+       RULL(0x0006C568), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3C9_OCI                             ,
+       RULL(0xC0062348), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3C9_OCI1                            ,
+       RULL(0xC0062B48), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3C9_SCOM                            ,
+       RULL(0x0006C469), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3C9_SCOM1                           ,
+       RULL(0x0006C569), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT3PRA_OCI                            ,
+       RULL(0xC0063300), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT3PRA_OCI1                           ,
+       RULL(0xC0063308), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT3PRA_RO                             ,
+       RULL(0x0006C660), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT3PRA_CLEAR                          ,
+       RULL(0x0006C661), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C0_OCI                             ,
+       RULL(0xC0062400), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C0_OCI1                            ,
+       RULL(0xC0062C00), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C0_SCOM                            ,
+       RULL(0x0006C480), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C0_SCOM1                           ,
+       RULL(0x0006C580), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C1_OCI                             ,
+       RULL(0xC0062408), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C1_OCI1                            ,
+       RULL(0xC0062C08), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C1_SCOM                            ,
+       RULL(0x0006C481), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C1_SCOM1                           ,
+       RULL(0x0006C581), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C10_OCI                            ,
+       RULL(0xC0062450), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C10_OCI1                           ,
+       RULL(0xC0062C50), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C10_SCOM                           ,
+       RULL(0x0006C48A), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C10_SCOM1                          ,
+       RULL(0x0006C58A), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C11_OCI                            ,
+       RULL(0xC0062458), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C11_OCI1                           ,
+       RULL(0xC0062C58), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C11_SCOM                           ,
+       RULL(0x0006C48B), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C11_SCOM1                          ,
+       RULL(0x0006C58B), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C12_OCI                            ,
+       RULL(0xC0062460), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C12_OCI1                           ,
+       RULL(0xC0062C60), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C12_SCOM                           ,
+       RULL(0x0006C48C), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C12_SCOM1                          ,
+       RULL(0x0006C58C), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C13_OCI                            ,
+       RULL(0xC0062468), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C13_OCI1                           ,
+       RULL(0xC0062C68), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C13_SCOM                           ,
+       RULL(0x0006C48D), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C13_SCOM1                          ,
+       RULL(0x0006C58D), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C14_OCI                            ,
+       RULL(0xC0062470), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C14_OCI1                           ,
+       RULL(0xC0062C70), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C14_SCOM                           ,
+       RULL(0x0006C48E), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C14_SCOM1                          ,
+       RULL(0x0006C58E), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C15_OCI                            ,
+       RULL(0xC0062478), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C15_OCI1                           ,
+       RULL(0xC0062C78), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C15_SCOM                           ,
+       RULL(0x0006C48F), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C15_SCOM1                          ,
+       RULL(0x0006C58F), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C16_OCI                            ,
+       RULL(0xC0062480), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C16_OCI1                           ,
+       RULL(0xC0062C80), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C16_SCOM                           ,
+       RULL(0x0006C490), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C16_SCOM1                          ,
+       RULL(0x0006C590), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C17_OCI                            ,
+       RULL(0xC0062488), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C17_OCI1                           ,
+       RULL(0xC0062C88), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C17_SCOM                           ,
+       RULL(0x0006C491), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C17_SCOM1                          ,
+       RULL(0x0006C591), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C18_OCI                            ,
+       RULL(0xC0062490), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C18_OCI1                           ,
+       RULL(0xC0062C90), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C18_SCOM                           ,
+       RULL(0x0006C492), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C18_SCOM1                          ,
+       RULL(0x0006C592), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C19_OCI                            ,
+       RULL(0xC0062498), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C19_OCI1                           ,
+       RULL(0xC0062C98), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C19_SCOM                           ,
+       RULL(0x0006C493), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C19_SCOM1                          ,
+       RULL(0x0006C593), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C2_OCI                             ,
+       RULL(0xC0062410), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C2_OCI1                            ,
+       RULL(0xC0062C10), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C2_SCOM                            ,
+       RULL(0x0006C482), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C2_SCOM1                           ,
+       RULL(0x0006C582), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C20_OCI                            ,
+       RULL(0xC00624A0), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C20_OCI1                           ,
+       RULL(0xC0062CA0), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C20_SCOM                           ,
+       RULL(0x0006C494), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C20_SCOM1                          ,
+       RULL(0x0006C594), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C21_OCI                            ,
+       RULL(0xC00624A8), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C21_OCI1                           ,
+       RULL(0xC0062CA8), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C21_SCOM                           ,
+       RULL(0x0006C495), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C21_SCOM1                          ,
+       RULL(0x0006C595), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C22_OCI                            ,
+       RULL(0xC00624B0), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C22_OCI1                           ,
+       RULL(0xC0062CB0), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C22_SCOM                           ,
+       RULL(0x0006C496), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C22_SCOM1                          ,
+       RULL(0x0006C596), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C23_OCI                            ,
+       RULL(0xC00624B8), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C23_OCI1                           ,
+       RULL(0xC0062CB8), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C23_SCOM                           ,
+       RULL(0x0006C497), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C23_SCOM1                          ,
+       RULL(0x0006C597), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C3_OCI                             ,
+       RULL(0xC0062418), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C3_OCI1                            ,
+       RULL(0xC0062C18), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C3_SCOM                            ,
+       RULL(0x0006C483), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C3_SCOM1                           ,
+       RULL(0x0006C583), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C4_OCI                             ,
+       RULL(0xC0062420), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C4_OCI1                            ,
+       RULL(0xC0062C20), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C4_SCOM                            ,
+       RULL(0x0006C484), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C4_SCOM1                           ,
+       RULL(0x0006C584), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C5_OCI                             ,
+       RULL(0xC0062428), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C5_OCI1                            ,
+       RULL(0xC0062C28), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C5_SCOM                            ,
+       RULL(0x0006C485), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C5_SCOM1                           ,
+       RULL(0x0006C585), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C6_OCI                             ,
+       RULL(0xC0062430), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C6_OCI1                            ,
+       RULL(0xC0062C30), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C6_SCOM                            ,
+       RULL(0x0006C486), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C6_SCOM1                           ,
+       RULL(0x0006C586), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C7_OCI                             ,
+       RULL(0xC0062438), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C7_OCI1                            ,
+       RULL(0xC0062C38), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C7_SCOM                            ,
+       RULL(0x0006C487), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C7_SCOM1                           ,
+       RULL(0x0006C587), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C8_OCI                             ,
+       RULL(0xC0062440), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C8_OCI1                            ,
+       RULL(0xC0062C40), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C8_SCOM                            ,
+       RULL(0x0006C488), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C8_SCOM1                           ,
+       RULL(0x0006C588), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4C9_OCI                             ,
+       RULL(0xC0062448), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4C9_OCI1                            ,
+       RULL(0xC0062C48), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4C9_SCOM                            ,
+       RULL(0x0006C489), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4C9_SCOM1                           ,
+       RULL(0x0006C589), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT4PRA_OCI                            ,
+       RULL(0xC0063400), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT4PRA_OCI1                           ,
+       RULL(0xC0063408), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT4PRA_RO                             ,
+       RULL(0x0006C680), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT4PRA_CLEAR                          ,
+       RULL(0x0006C681), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C0_OCI                             ,
+       RULL(0xC0062500), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C0_OCI1                            ,
+       RULL(0xC0062D00), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C0_SCOM                            ,
+       RULL(0x0006C4A0), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C0_SCOM1                           ,
+       RULL(0x0006C5A0), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C1_OCI                             ,
+       RULL(0xC0062508), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C1_OCI1                            ,
+       RULL(0xC0062D08), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C1_SCOM                            ,
+       RULL(0x0006C4A1), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C1_SCOM1                           ,
+       RULL(0x0006C5A1), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C10_OCI                            ,
+       RULL(0xC0062550), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C10_OCI1                           ,
+       RULL(0xC0062D50), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C10_SCOM                           ,
+       RULL(0x0006C4AA), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C10_SCOM1                          ,
+       RULL(0x0006C5AA), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C11_OCI                            ,
+       RULL(0xC0062558), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C11_OCI1                           ,
+       RULL(0xC0062D58), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C11_SCOM                           ,
+       RULL(0x0006C4AB), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C11_SCOM1                          ,
+       RULL(0x0006C5AB), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C12_OCI                            ,
+       RULL(0xC0062560), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C12_OCI1                           ,
+       RULL(0xC0062D60), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C12_SCOM                           ,
+       RULL(0x0006C4AC), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C12_SCOM1                          ,
+       RULL(0x0006C5AC), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C13_OCI                            ,
+       RULL(0xC0062568), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C13_OCI1                           ,
+       RULL(0xC0062D68), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C13_SCOM                           ,
+       RULL(0x0006C4AD), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C13_SCOM1                          ,
+       RULL(0x0006C5AD), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C14_OCI                            ,
+       RULL(0xC0062570), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C14_OCI1                           ,
+       RULL(0xC0062D70), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C14_SCOM                           ,
+       RULL(0x0006C4AE), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C14_SCOM1                          ,
+       RULL(0x0006C5AE), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C15_OCI                            ,
+       RULL(0xC0062578), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C15_OCI1                           ,
+       RULL(0xC0062D78), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C15_SCOM                           ,
+       RULL(0x0006C4AF), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C15_SCOM1                          ,
+       RULL(0x0006C5AF), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C16_OCI                            ,
+       RULL(0xC0062580), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C16_OCI1                           ,
+       RULL(0xC0062D80), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C16_SCOM                           ,
+       RULL(0x0006C4B0), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C16_SCOM1                          ,
+       RULL(0x0006C5B0), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C17_OCI                            ,
+       RULL(0xC0062588), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C17_OCI1                           ,
+       RULL(0xC0062D88), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C17_SCOM                           ,
+       RULL(0x0006C4B1), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C17_SCOM1                          ,
+       RULL(0x0006C5B1), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C18_OCI                            ,
+       RULL(0xC0062590), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C18_OCI1                           ,
+       RULL(0xC0062D90), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C18_SCOM                           ,
+       RULL(0x0006C4B2), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C18_SCOM1                          ,
+       RULL(0x0006C5B2), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C19_OCI                            ,
+       RULL(0xC0062598), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C19_OCI1                           ,
+       RULL(0xC0062D98), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C19_SCOM                           ,
+       RULL(0x0006C4B3), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C19_SCOM1                          ,
+       RULL(0x0006C5B3), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C2_OCI                             ,
+       RULL(0xC0062510), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C2_OCI1                            ,
+       RULL(0xC0062D10), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C2_SCOM                            ,
+       RULL(0x0006C4A2), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C2_SCOM1                           ,
+       RULL(0x0006C5A2), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C20_OCI                            ,
+       RULL(0xC00625A0), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C20_OCI1                           ,
+       RULL(0xC0062DA0), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C20_SCOM                           ,
+       RULL(0x0006C4B4), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C20_SCOM1                          ,
+       RULL(0x0006C5B4), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C21_OCI                            ,
+       RULL(0xC00625A8), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C21_OCI1                           ,
+       RULL(0xC0062DA8), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C21_SCOM                           ,
+       RULL(0x0006C4B5), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C21_SCOM1                          ,
+       RULL(0x0006C5B5), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C22_OCI                            ,
+       RULL(0xC00625B0), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C22_OCI1                           ,
+       RULL(0xC0062DB0), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C22_SCOM                           ,
+       RULL(0x0006C4B6), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C22_SCOM1                          ,
+       RULL(0x0006C5B6), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C23_OCI                            ,
+       RULL(0xC00625B8), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C23_OCI1                           ,
+       RULL(0xC0062DB8), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C23_SCOM                           ,
+       RULL(0x0006C4B7), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C23_SCOM1                          ,
+       RULL(0x0006C5B7), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C3_OCI                             ,
+       RULL(0xC0062518), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C3_OCI1                            ,
+       RULL(0xC0062D18), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C3_SCOM                            ,
+       RULL(0x0006C4A3), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C3_SCOM1                           ,
+       RULL(0x0006C5A3), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C4_OCI                             ,
+       RULL(0xC0062520), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C4_OCI1                            ,
+       RULL(0xC0062D20), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C4_SCOM                            ,
+       RULL(0x0006C4A4), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C4_SCOM1                           ,
+       RULL(0x0006C5A4), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C5_OCI                             ,
+       RULL(0xC0062528), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C5_OCI1                            ,
+       RULL(0xC0062D28), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C5_SCOM                            ,
+       RULL(0x0006C4A5), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C5_SCOM1                           ,
+       RULL(0x0006C5A5), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C6_OCI                             ,
+       RULL(0xC0062530), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C6_OCI1                            ,
+       RULL(0xC0062D30), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C6_SCOM                            ,
+       RULL(0x0006C4A6), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C6_SCOM1                           ,
+       RULL(0x0006C5A6), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C7_OCI                             ,
+       RULL(0xC0062538), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C7_OCI1                            ,
+       RULL(0xC0062D38), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C7_SCOM                            ,
+       RULL(0x0006C4A7), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C7_SCOM1                           ,
+       RULL(0x0006C5A7), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C8_OCI                             ,
+       RULL(0xC0062540), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C8_OCI1                            ,
+       RULL(0xC0062D40), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C8_SCOM                            ,
+       RULL(0x0006C4A8), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C8_SCOM1                           ,
+       RULL(0x0006C5A8), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5C9_OCI                             ,
+       RULL(0xC0062548), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5C9_OCI1                            ,
+       RULL(0xC0062D48), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5C9_SCOM                            ,
+       RULL(0x0006C4A9), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5C9_SCOM1                           ,
+       RULL(0x0006C5A9), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT5PRA_OCI                            ,
+       RULL(0xC0063500), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT5PRA_OCI1                           ,
+       RULL(0xC0063508), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT5PRA_RO                             ,
+       RULL(0x0006C6A0), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT5PRA_CLEAR                          ,
+       RULL(0x0006C6A1), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+
+REG64( PU_GPE1_OCB_OCI_OPIT6PRB_OCI                            ,
+       RULL(0xC0063600), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT6PRB_OCI1                           ,
+       RULL(0xC0063608), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT6PRB_RO                             ,
+       RULL(0x0006C6C0), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT6PRB_CLEAR                          ,
+       RULL(0x0006C6C1), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+
+REG64( PU_GPE1_OCB_OCI_OPIT6Q0_OCI                             ,
+       RULL(0xC0062600), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT6Q0_OCI1                            ,
+       RULL(0xC0062E00), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT6Q0_SCOM                            ,
+       RULL(0x0006C4C0), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT6Q0_SCOM1                           ,
+       RULL(0x0006C5C0), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT6Q1_OCI                             ,
+       RULL(0xC0062608), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT6Q1_OCI1                            ,
+       RULL(0xC0062E08), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT6Q1_SCOM                            ,
+       RULL(0x0006C4C1), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT6Q1_SCOM1                           ,
+       RULL(0x0006C5C1), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT6Q2_OCI                             ,
+       RULL(0xC0062610), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT6Q2_OCI1                            ,
+       RULL(0xC0062E10), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT6Q2_SCOM                            ,
+       RULL(0x0006C4C2), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT6Q2_SCOM1                           ,
+       RULL(0x0006C5C2), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT6Q3_OCI                             ,
+       RULL(0xC0062618), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT6Q3_OCI1                            ,
+       RULL(0xC0062E18), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT6Q3_SCOM                            ,
+       RULL(0x0006C4C3), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT6Q3_SCOM1                           ,
+       RULL(0x0006C5C3), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT6Q4_OCI                             ,
+       RULL(0xC0062620), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT6Q4_OCI1                            ,
+       RULL(0xC0062E20), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT6Q4_SCOM                            ,
+       RULL(0x0006C4C4), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT6Q4_SCOM1                           ,
+       RULL(0x0006C5C4), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT6Q5_OCI                             ,
+       RULL(0xC0062628), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT6Q5_OCI1                            ,
+       RULL(0xC0062E28), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT6Q5_SCOM                            ,
+       RULL(0x0006C4C5), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT6Q5_SCOM1                           ,
+       RULL(0x0006C5C5), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT7PRB_OCI                            ,
+       RULL(0xC0063700), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT7PRB_OCI1                           ,
+       RULL(0xC0063708), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT7PRB_RO                             ,
+       RULL(0x0006C6E0), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT7PRB_CLEAR                          ,
+       RULL(0x0006C6E1), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+
+REG64( PU_GPE1_OCB_OCI_OPIT7Q0_OCI                             ,
+       RULL(0xC0062700), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT7Q0_OCI1                            ,
+       RULL(0xC0062F00), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT7Q0_SCOM                            ,
+       RULL(0x0006C4E0), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT7Q0_SCOM1                           ,
+       RULL(0x0006C5E0), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT7Q1_OCI                             ,
+       RULL(0xC0062708), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT7Q1_OCI1                            ,
+       RULL(0xC0062F08), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT7Q1_SCOM                            ,
+       RULL(0x0006C4E1), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT7Q1_SCOM1                           ,
+       RULL(0x0006C5E1), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT7Q2_OCI                             ,
+       RULL(0xC0062710), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT7Q2_OCI1                            ,
+       RULL(0xC0062F10), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT7Q2_SCOM                            ,
+       RULL(0x0006C4E2), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT7Q2_SCOM1                           ,
+       RULL(0x0006C5E2), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT7Q3_OCI                             ,
+       RULL(0xC0062718), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT7Q3_OCI1                            ,
+       RULL(0xC0062F18), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT7Q3_SCOM                            ,
+       RULL(0x0006C4E3), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT7Q3_SCOM1                           ,
+       RULL(0x0006C5E3), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT7Q4_OCI                             ,
+       RULL(0xC0062720), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT7Q4_OCI1                            ,
+       RULL(0xC0062F20), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT7Q4_SCOM                            ,
+       RULL(0x0006C4E4), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT7Q4_SCOM1                           ,
+       RULL(0x0006C5E4), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE1_OCB_OCI_OPIT7Q5_OCI                             ,
+       RULL(0xC0062728), SH_UNT_PU_GPE1  , SH_ACS_OCI       );
+REG64( PU_GPE1_OCB_OCI_OPIT7Q5_OCI1                            ,
+       RULL(0xC0062F28), SH_UNT_PU_GPE1  , SH_ACS_OCI1      );
+REG64( PU_GPE6_OCB_OCI_OPIT7Q5_SCOM                            ,
+       RULL(0x0006C4E5), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_OCI_OPIT7Q5_SCOM1                           ,
+       RULL(0x0006C5E5), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO  );
+
+REG64( PU_GPE0_OCB_OCI_OTBR_OCI                                ,
+       RULL(0xC00604F8), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OTBR                                    ,
+       RULL(0x0006C09F), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_OCB_OCI_OTR0_OCI                                ,
+       RULL(0xC0060800), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OTR0                                    ,
+       RULL(0x0006C100), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_OCB_OCI_OTR1_OCI                                ,
+       RULL(0xC0060808), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OTR1                                    ,
+       RULL(0x0006C101), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_OCB_OCI_OUISR0_OCI                              ,
+       RULL(0xC0060310), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OUISR0                                  ,
+       RULL(0x0006C062), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_OCB_OCI_OUISR1_OCI                              ,
+       RULL(0xC0060390), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE6_OCB_OCI_OUISR1                                  ,
+       RULL(0x0006C072), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_OCB_OCI_QCSR_OCI                                ,
+       RULL(0xC00604A0), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_OCB_OCI_QCSR_OCI1                               ,
+       RULL(0xC00604A8), SH_UNT_PU_GPE0  , SH_ACS_OCI1      );
+REG64( PU_GPE0_OCB_OCI_QCSR_OCI2                               ,
+       RULL(0xC00604B0), SH_UNT_PU_GPE0  , SH_ACS_OCI2      );
+REG64( PU_GPE6_OCB_OCI_QCSR                                    ,
+       RULL(0x0006C094), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE6_OCB_OCI_QCSR_CLEAR                              ,
+       RULL(0x0006C095), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_OCI_QCSR_OR                                 ,
+       RULL(0x0006C096), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE0_OCB_OCI_QSSR_OCI                                ,
+       RULL(0xC00604C0), SH_UNT_PU_GPE0  , SH_ACS_OCI       );
+REG64( PU_GPE0_OCB_OCI_QSSR_OCI1                               ,
+       RULL(0xC00604C8), SH_UNT_PU_GPE0  , SH_ACS_OCI1      );
+REG64( PU_GPE0_OCB_OCI_QSSR_OCI2                               ,
+       RULL(0xC00604D0), SH_UNT_PU_GPE0  , SH_ACS_OCI2      );
+REG64( PU_GPE6_OCB_OCI_QSSR                                    ,
+       RULL(0x0006C098), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+REG64( PU_GPE6_OCB_OCI_QSSR_CLEAR                              ,
+       RULL(0x0006C099), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_OCI_QSSR_OR                                 ,
+       RULL(0x0006C09A), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE6_OCB_PIB_OACR                                    ,
+       RULL(0x0006D207), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE6_OCB_PIB_OCBAR0                                  ,
+       RULL(0x0006D010), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE6_OCB_PIB_OCBAR1                                  ,
+       RULL(0x0006D030), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE6_OCB_PIB_OCBAR2                                  ,
+       RULL(0x0006D050), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE6_OCB_PIB_OCBAR3                                  ,
+       RULL(0x0006D070), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE6_OCB_PIB_OCBCSR0_RO                              ,
+       RULL(0x0006D011), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_PIB_OCBCSR0_CLEAR                           ,
+       RULL(0x0006D012), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_PIB_OCBCSR0_OR                              ,
+       RULL(0x0006D013), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE6_OCB_PIB_OCBCSR1_RO                              ,
+       RULL(0x0006D031), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_PIB_OCBCSR1_CLEAR                           ,
+       RULL(0x0006D032), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_PIB_OCBCSR1_OR                              ,
+       RULL(0x0006D033), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE6_OCB_PIB_OCBCSR2_RO                              ,
+       RULL(0x0006D051), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_PIB_OCBCSR2_CLEAR                           ,
+       RULL(0x0006D052), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_PIB_OCBCSR2_OR                              ,
+       RULL(0x0006D053), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE6_OCB_PIB_OCBCSR3_RO                              ,
+       RULL(0x0006D071), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_PIB_OCBCSR3_CLEAR                           ,
+       RULL(0x0006D072), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_PIB_OCBCSR3_OR                              ,
+       RULL(0x0006D073), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE6_OCB_PIB_OCBDR0                                  ,
+       RULL(0x0006D015), SH_UNT_PU_GPE6  , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE6_OCB_PIB_OCBDR1                                  ,
+       RULL(0x0006D035), SH_UNT_PU_GPE6  , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE6_OCB_PIB_OCBDR2                                  ,
+       RULL(0x0006D055), SH_UNT_PU_GPE6  , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE6_OCB_PIB_OCBDR3                                  ,
+       RULL(0x0006D075), SH_UNT_PU_GPE6  , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE6_OCB_PIB_OCBEAR                                  ,
+       RULL(0x0006D210), SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLRPART );
+
+REG64( PU_GPE6_OCB_PIB_OCBESR0                                 ,
+       RULL(0x0006D014), SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_GPE6_OCB_PIB_OCBESR1                                 ,
+       RULL(0x0006D034), SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_GPE6_OCB_PIB_OCBESR2                                 ,
+       RULL(0x0006D054), SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_GPE6_OCB_PIB_OCBESR3                                 ,
+       RULL(0x0006D074), SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_GPE6_OCB_PIB_OCDBG                                   ,
+       RULL(0x0006D003), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE6_OCB_PIB_OCR_RO                                  ,
+       RULL(0x0006D000), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+REG64( PU_GPE6_OCB_PIB_OCR_CLEAR                               ,
+       RULL(0x0006D001), SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR );
+REG64( PU_GPE6_OCB_PIB_OCR_OR                                  ,
+       RULL(0x0006D002), SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_GPE6_OCB_PIB_OEAR                                    ,
+       RULL(0x0006D206), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE6_OCB_PIB_OESR                                    ,
+       RULL(0x0006D204), SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR );
+
+REG64( PU_GPE6_OCB_PIB_OPPCINJ                                 ,
+       RULL(0x0006D111), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE6_OCB_PIB_OREV                                    ,
+       RULL(0x0006D202), SH_UNT_PU_GPE6  , SH_ACS_SCOM      );
+
+REG64( PU_GPE6_OCB_PIB_OSTOEAR                                 ,
+       RULL(0x0006D200), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE6_OCB_PIB_OSTOESR                                 ,
+       RULL(0x0006D201), SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR );
+
+REG64( PU_GPE6_OCB_PIB_OTDCR                                   ,
+       RULL(0x0006D110), SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW   );
+
+REG64( PU_OSCERR_HOLD                                          ,
+       RULL(0x01020019), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_OSCERR_MASK                                          ,
+       RULL(0x0102001A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_OSCERR_MCODE                                         ,
+       RULL(0x0102001B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PBABAR0                                              ,
+       RULL(0x05012B00), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBABAR1                                              ,
+       RULL(0x05012B01), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBABAR2                                              ,
+       RULL(0x05012B02), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBABAR3                                              ,
+       RULL(0x05012B03), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBABARMSK0                                           ,
+       RULL(0x05012B04), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBABARMSK1                                           ,
+       RULL(0x05012B05), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBABARMSK2                                           ,
+       RULL(0x05012B06), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBABARMSK3                                           ,
+       RULL(0x05012B07), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBACFG                                               ,
+       RULL(0x0501284B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBAERRRPT0                                           ,
+       RULL(0x0501284C), SH_UNT          , SH_ACS_SCOM_WCLRPART );
+
+REG64( PU_PBAERRRPT1                                           ,
+       RULL(0x0501284D), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBAERRRPT2                                           ,
+       RULL(0x0501284E), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBAFIR                                               ,
+       RULL(0x05012840), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PBAFIR_AND                                           ,
+       RULL(0x05012841), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PBAFIR_OR                                            ,
+       RULL(0x05012842), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_PBAFIRACT0                                           ,
+       RULL(0x05012846), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBAFIRACT1                                           ,
+       RULL(0x05012847), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBAFIRMASK                                           ,
+       RULL(0x05012843), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PBAFIRMASK_AND                                       ,
+       RULL(0x05012844), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PBAFIRMASK_OR                                        ,
+       RULL(0x05012845), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_PBAIB0_PBAIBHWCFG_REG                                ,
+       RULL(0x0D010802), SH_UNT_PU_PBAIB0, SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB1_PBAIBHWCFG_REG                                ,
+       RULL(0x0E010802), SH_UNT_PU_PBAIB1, SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB2_PBAIBHWCFG_REG                                ,
+       RULL(0x0F010802), SH_UNT_PU_PBAIB2, SH_ACS_SCOM_RW   );
+
+REG64( PU_PBAIB_STACK0_PBAIB_CERR_RPT_REG                      ,
+       RULL(0x0D010841), SH_UNT_PU_PBAIB_STACK0, SH_ACS_SCOM_RO   );
+REG64( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG                      ,
+       RULL(0x0D010881), SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO   );
+REG64( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG                      ,
+       RULL(0x0D0108C1), SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO   );
+REG64( PU_PBAIB_STACK3_PBAIB_CERR_RPT_REG                      ,
+       RULL(0x0E010841), SH_UNT_PU_PBAIB_STACK3, SH_ACS_SCOM_RO   );
+REG64( PU_PBAIB_STACK4_PBAIB_CERR_RPT_REG                      ,
+       RULL(0x0E010881), SH_UNT_PU_PBAIB_STACK4, SH_ACS_SCOM_RO   );
+REG64( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG                      ,
+       RULL(0x0E0108C1), SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO   );
+REG64( PU_PBAIB_STACK6_PBAIB_CERR_RPT_REG                      ,
+       RULL(0x0F010841), SH_UNT_PU_PBAIB_STACK6, SH_ACS_SCOM_RO   );
+REG64( PU_PBAIB_STACK7_PBAIB_CERR_RPT_REG                      ,
+       RULL(0x0F010881), SH_UNT_PU_PBAIB_STACK7, SH_ACS_SCOM_RO   );
+REG64( PU_PBAIB_STACK8_PBAIB_CERR_RPT_REG                      ,
+       RULL(0x0F0108C1), SH_UNT_PU_PBAIB_STACK8, SH_ACS_SCOM_RO   );
+
+REG64( PU_PBAMODE_OCI                                          ,
+       RULL(0x40020000), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAMODE_SCOM                                         ,
+       RULL(0x05016840), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PBAOCCACT                                            ,
+       RULL(0x0501284A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBAPBOCR0_OCI                                        ,
+       RULL(0x400200D0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAPBOCR0_SCOM                                       ,
+       RULL(0x0501685A), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBAPBOCR1_OCI                                        ,
+       RULL(0x400200D8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAPBOCR1_SCOM                                       ,
+       RULL(0x0501685B), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBAPBOCR2_OCI                                        ,
+       RULL(0x400200E0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAPBOCR2_SCOM                                       ,
+       RULL(0x0501685C), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBAPBOCR3_OCI                                        ,
+       RULL(0x400200E8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAPBOCR3_SCOM                                       ,
+       RULL(0x0501685D), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBAPBOCR4_OCI                                        ,
+       RULL(0x400200F0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAPBOCR4_SCOM                                       ,
+       RULL(0x0501685E), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBAPBOCR5_OCI                                        ,
+       RULL(0x400200F8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAPBOCR5_SCOM                                       ,
+       RULL(0x0501685F), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBARBUFVAL0                                          ,
+       RULL(0x05012850), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBARBUFVAL1                                          ,
+       RULL(0x05012851), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBARBUFVAL2                                          ,
+       RULL(0x05012852), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBARBUFVAL3                                          ,
+       RULL(0x05012853), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBARBUFVAL4                                          ,
+       RULL(0x05012854), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBARBUFVAL5                                          ,
+       RULL(0x05012855), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBASLVCTL0_OCI                                       ,
+       RULL(0x40020020), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBASLVCTL0_SCOM                                      ,
+       RULL(0x05016844), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBASLVCTL1_OCI                                       ,
+       RULL(0x40020028), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBASLVCTL1_SCOM                                      ,
+       RULL(0x05016845), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBASLVCTL2_OCI                                       ,
+       RULL(0x40020030), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBASLVCTL2_SCOM                                      ,
+       RULL(0x05016846), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBASLVCTL3_OCI                                       ,
+       RULL(0x40020038), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBASLVCTL3_SCOM                                      ,
+       RULL(0x05016847), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBASLVRST_OCI                                        ,
+       RULL(0x40020008), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBASLVRST_SCOM                                       ,
+       RULL(0x05016841), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PBAWBUFVAL0                                          ,
+       RULL(0x05012858), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBAWBUFVAL1                                          ,
+       RULL(0x05012859), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBAXCFG_OCI                                          ,
+       RULL(0x40020108), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAXCFG_SCOM                                         ,
+       RULL(0x05016861), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PBAXRCVSTAT_OCI                                      ,
+       RULL(0x40020120), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAXRCVSTAT_SCOM                                     ,
+       RULL(0x05016864), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBAXSHBR0_OCI                                        ,
+       RULL(0x40020130), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAXSHBR0_SCOM                                       ,
+       RULL(0x05016866), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBAXSHBR1_OCI                                        ,
+       RULL(0x40020150), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAXSHBR1_SCOM                                       ,
+       RULL(0x0501686A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBAXSHCS0_OCI                                        ,
+       RULL(0x40020138), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAXSHCS0_SCOM                                       ,
+       RULL(0x05016867), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PBAXSHCS1_OCI                                        ,
+       RULL(0x40020158), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAXSHCS1_SCOM                                       ,
+       RULL(0x0501686B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PBAXSNDSTAT_OCI                                      ,
+       RULL(0x40020110), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAXSNDSTAT_SCOM                                     ,
+       RULL(0x05016862), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBAXSNDTX_OCI                                        ,
+       RULL(0x40020100), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAXSNDTX_SCOM                                       ,
+       RULL(0x05016860), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PEC_PBCQEINJ_REG                                        ,
+       RULL(0x04010C02), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_PBCQEINJ_REG                                      ,
+       RULL(0x04010C02), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_PBCQEINJ_REG                                      ,
+       RULL(0x04011002), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_PBCQEINJ_REG                                      ,
+       RULL(0x04011402), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( PEC_PBCQHWCFG_REG                                       ,
+       RULL(0x04010C00), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_PBCQHWCFG_REG                                     ,
+       RULL(0x04010C00), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_PBCQHWCFG_REG                                     ,
+       RULL(0x04011000), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_PBCQHWCFG_REG                                     ,
+       RULL(0x04011400), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( PEC_0_STACK0_PBCQMODE_REG                               ,
+       RULL(0x04010C4D), SH_UNT_PEC_0_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK1_PBCQMODE_REG                               ,
+       RULL(0x04010C8D), SH_UNT_PEC_0_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK2_PBCQMODE_REG                               ,
+       RULL(0x04010CCD), SH_UNT_PEC_0_STACK2, SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK0_PBCQMODE_REG                               ,
+       RULL(0x0401104D), SH_UNT_PEC_1_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK1_PBCQMODE_REG                               ,
+       RULL(0x0401108D), SH_UNT_PEC_1_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK2_PBCQMODE_REG                               ,
+       RULL(0x040110CD), SH_UNT_PEC_1_STACK2, SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK0_PBCQMODE_REG                               ,
+       RULL(0x0401144D), SH_UNT_PEC_2_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK1_PBCQMODE_REG                               ,
+       RULL(0x0401148D), SH_UNT_PEC_2_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK2_PBCQMODE_REG                               ,
+       RULL(0x040114CD), SH_UNT_PEC_2_STACK2, SH_ACS_SCOM_RW   );
+REG64( PEC_STACK0_PBCQMODE_REG                                 ,
+       RULL(0x04010C4D), SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW   );
+REG64( PEC_STACK1_PBCQMODE_REG                                 ,
+       RULL(0x04010C8D), SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW   );
+REG64( PEC_STACK2_PBCQMODE_REG                                 ,
+       RULL(0x04010CCD), SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_00_REG                                   ,
+       RULL(0x05013430), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_01_REG                                   ,
+       RULL(0x05013431), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_10_REG                                   ,
+       RULL(0x05013432), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_11_REG                                   ,
+       RULL(0x05013433), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_20_REG                                   ,
+       RULL(0x05013434), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_21_REG                                   ,
+       RULL(0x05013435), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_30_REG                                   ,
+       RULL(0x05013436), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_31_REG                                   ,
+       RULL(0x05013437), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_40_REG                                   ,
+       RULL(0x05013438), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_41_REG                                   ,
+       RULL(0x05013439), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_50_REG                                   ,
+       RULL(0x0501343A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_51_REG                                   ,
+       RULL(0x0501343B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_CTL_REG                                  ,
+       RULL(0x0501342E), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PBE_MAILBOX_DATA_REG                                 ,
+       RULL(0x0501342F), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBO_MAILBOX_00_REG                                   ,
+       RULL(0x05013830), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBO_MAILBOX_01_REG                                   ,
+       RULL(0x05013831), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBO_MAILBOX_10_REG                                   ,
+       RULL(0x05013832), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBO_MAILBOX_11_REG                                   ,
+       RULL(0x05013833), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBO_MAILBOX_20_REG                                   ,
+       RULL(0x05013834), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBO_MAILBOX_21_REG                                   ,
+       RULL(0x05013835), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBO_MAILBOX_30_REG                                   ,
+       RULL(0x05013836), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBO_MAILBOX_31_REG                                   ,
+       RULL(0x05013837), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBO_MAILBOX_40_REG                                   ,
+       RULL(0x05013838), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBO_MAILBOX_41_REG                                   ,
+       RULL(0x05013839), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBO_MAILBOX_50_REG                                   ,
+       RULL(0x0501383A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBO_MAILBOX_51_REG                                   ,
+       RULL(0x0501383B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBO_MAILBOX_60_REG                                   ,
+       RULL(0x0501383C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBO_MAILBOX_61_REG                                   ,
+       RULL(0x0501383D), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBO_MAILBOX_70_REG                                   ,
+       RULL(0x0501383E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBO_MAILBOX_71_REG                                   ,
+       RULL(0x0501383F), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBO_MAILBOX_CTL_REG                                  ,
+       RULL(0x0501382E), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PBO_MAILBOX_DATA_REG                                 ,
+       RULL(0x0501382F), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_ELINK_DATA_01_CFG_REG                             ,
+       RULL(0x05013410), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_ELINK_DATA_23_CFG_REG                             ,
+       RULL(0x05013411), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_ELINK_DATA_45_CFG_REG                             ,
+       RULL(0x05013412), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_ELINK_DLY_0123_REG                                ,
+       RULL(0x0501340E), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_ELINK_DLY_45_REG                                  ,
+       RULL(0x0501340F), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_ELINK_PMU0                                        ,
+       RULL(0x0501341B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_ELINK_PMU1                                        ,
+       RULL(0x0501341C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_ELINK_PMU2                                        ,
+       RULL(0x0501341D), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_ELINK_PMU3                                        ,
+       RULL(0x0501341E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_ELINK_PMU4                                        ,
+       RULL(0x0501341F), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_ELINK_PMU5                                        ,
+       RULL(0x05013420), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_ELINK_PMU6                                        ,
+       RULL(0x05013421), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_ELINK_PMU7                                        ,
+       RULL(0x05013422), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_ELINK_PMU_CTL_REG                                 ,
+       RULL(0x0501341A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_ELINK_RT_DELAY_CTL_REG                            ,
+       RULL(0x05013419), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PB_ELINK_SYN_01_REG                                  ,
+       RULL(0x05013414), SH_UNT          , SH_ACS_SCOM_WCLEAR );
+
+REG64( PU_PB_ELINK_SYN_23_REG                                  ,
+       RULL(0x05013415), SH_UNT          , SH_ACS_SCOM_WCLEAR );
+
+REG64( PU_PB_ELINK_SYN_45_REG                                  ,
+       RULL(0x05013416), SH_UNT          , SH_ACS_SCOM_WCLEAR );
+
+REG64( PU_PB_EN_DOB_ECC_ERR_REG                                ,
+       RULL(0x05013818), SH_UNT          , SH_ACS_SCOM_RO   ); //DUPS: 05013418,
+
+REG64( PU_PB_FM0123_ERR                                        ,
+       RULL(0x05013825), SH_UNT          , SH_ACS_SCOM_RO   ); //DUPS: 05013425,
+
+REG64( PU_PB_FM4567_ERR                                        ,
+       RULL(0x05013826), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_FM45_ERR                                          ,
+       RULL(0x05013426), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_FP01_CFG                                          ,
+       RULL(0x0501380A), SH_UNT          , SH_ACS_SCOM_RW   ); //DUPS: 0501340A,
+
+REG64( PU_PB_FP23_CFG                                          ,
+       RULL(0x0501380B), SH_UNT          , SH_ACS_SCOM_RW   ); //DUPS: 0501340B,
+
+REG64( PU_PB_FP45_CFG                                          ,
+       RULL(0x0501380C), SH_UNT          , SH_ACS_SCOM_RW   ); //DUPS: 0501340C,
+
+REG64( PU_PB_FP67_CFG                                          ,
+       RULL(0x0501380D), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_IOE_FIR_ACTION0_REG                               ,
+       RULL(0x05013406), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_IOE_FIR_ACTION1_REG                               ,
+       RULL(0x05013407), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_IOE_FIR_MASK_REG                                  ,
+       RULL(0x05013403), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PB_IOE_FIR_MASK_REG_AND                              ,
+       RULL(0x05013404), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PB_IOE_FIR_MASK_REG_OR                               ,
+       RULL(0x05013405), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_PB_IOE_FIR_REG                                       ,
+       RULL(0x05013400), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PB_IOE_FIR_REG_AND                                   ,
+       RULL(0x05013401), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PB_IOE_FIR_REG_OR                                    ,
+       RULL(0x05013402), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_PB_IOO_FIR_ACTION0_REG                               ,
+       RULL(0x05013806), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_IOO_FIR_ACTION1_REG                               ,
+       RULL(0x05013807), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_IOO_FIR_MASK_REG                                  ,
+       RULL(0x05013803), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PB_IOO_FIR_MASK_REG_AND                              ,
+       RULL(0x05013804), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PB_IOO_FIR_MASK_REG_OR                               ,
+       RULL(0x05013805), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_PB_IOO_FIR_REG                                       ,
+       RULL(0x05013800), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PB_IOO_FIR_REG_AND                                   ,
+       RULL(0x05013801), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PB_IOO_FIR_REG_OR                                    ,
+       RULL(0x05013802), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_PB_MISC_CFG                                          ,
+       RULL(0x05013823), SH_UNT          , SH_ACS_SCOM      ); //DUPS: 05013423,
+
+REG64( PU_PB_OLINK_DATA_01_CFG_REG                             ,
+       RULL(0x05013810), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_OLINK_DATA_23_CFG_REG                             ,
+       RULL(0x05013811), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_OLINK_DATA_45_CFG_REG                             ,
+       RULL(0x05013812), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_OLINK_DATA_67_CFG_REG                             ,
+       RULL(0x05013813), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_OLINK_DLY_0123_REG                                ,
+       RULL(0x0501380E), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_OLINK_DLY_4567_REG                                ,
+       RULL(0x0501380F), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_OLINK_PMU0                                        ,
+       RULL(0x0501381B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_OLINK_PMU1                                        ,
+       RULL(0x0501381C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_OLINK_PMU2                                        ,
+       RULL(0x0501381D), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_OLINK_PMU3                                        ,
+       RULL(0x0501381E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_OLINK_PMU4                                        ,
+       RULL(0x0501381F), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_OLINK_PMU5                                        ,
+       RULL(0x05013820), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_OLINK_PMU6                                        ,
+       RULL(0x05013821), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_OLINK_PMU7                                        ,
+       RULL(0x05013822), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_OLINK_PMU_CTL_REG                                 ,
+       RULL(0x0501381A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_OLINK_RT_DELAY_CTL_REG                            ,
+       RULL(0x05013819), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PB_OLINK_SYN_01_REG                                  ,
+       RULL(0x05013814), SH_UNT          , SH_ACS_SCOM_WCLEAR );
+
+REG64( PU_PB_OLINK_SYN_23_REG                                  ,
+       RULL(0x05013815), SH_UNT          , SH_ACS_SCOM_WCLEAR );
+
+REG64( PU_PB_OLINK_SYN_45_REG                                  ,
+       RULL(0x05013816), SH_UNT          , SH_ACS_SCOM_WCLEAR );
+
+REG64( PU_PB_OLINK_SYN_67_REG                                  ,
+       RULL(0x05013817), SH_UNT          , SH_ACS_SCOM_WCLEAR );
+
+REG64( PU_PB_PR0123_ERR                                        ,
+       RULL(0x05013827), SH_UNT          , SH_ACS_SCOM_RO   ); //DUPS: 05013427,
+
+REG64( PU_PB_PR4567_ERR                                        ,
+       RULL(0x05013828), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_PR45_ERR                                          ,
+       RULL(0x05013428), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_TRACE_CFG                                         ,
+       RULL(0x05013824), SH_UNT          , SH_ACS_SCOM_RW   ); //DUPS: 05013424,
+
+REG64( PU_IOP0_PCS_M1_CONTROL_REG                              ,
+       RULL(0x80000C010D010D3F), SH_UNT_PU_IOP0  , SH_ACS_SCOM      );
+REG64( PU_IOP1_PCS_M1_CONTROL_REG                              ,
+       RULL(0x80000C010E010D3F), SH_UNT_PU_IOP1  , SH_ACS_SCOM      );
+REG64( PU_IOP2_PCS_M1_CONTROL_REG                              ,
+       RULL(0x80000C010F010D3F), SH_UNT_PU_IOP2  , SH_ACS_SCOM      );
+
+REG64( PU_IOP0_PCS_M2_CONTROL_REG                              ,
+       RULL(0x80000C020D010E3F), SH_UNT_PU_IOP0  , SH_ACS_SCOM      );
+REG64( PU_IOP1_PCS_M2_CONTROL_REG                              ,
+       RULL(0x80000C020E010E3F), SH_UNT_PU_IOP1  , SH_ACS_SCOM      );
+REG64( PU_IOP2_PCS_M2_CONTROL_REG                              ,
+       RULL(0x80000C020F010E3F), SH_UNT_PU_IOP2  , SH_ACS_SCOM      );
+
+REG64( PU_IOP0_PCS_M3_CONTROL_REG                              ,
+       RULL(0x80000C030D010F3F), SH_UNT_PU_IOP0  , SH_ACS_SCOM      );
+REG64( PU_IOP1_PCS_M3_CONTROL_REG                              ,
+       RULL(0x80000C030E010F3F), SH_UNT_PU_IOP1  , SH_ACS_SCOM      );
+REG64( PU_IOP2_PCS_M3_CONTROL_REG                              ,
+       RULL(0x80000C030F010F3F), SH_UNT_PU_IOP2  , SH_ACS_SCOM      );
+
+REG64( PU_IOP0_PCS_M4_CONTROL_REG                              ,
+       RULL(0x80000C040D01103F), SH_UNT_PU_IOP0  , SH_ACS_SCOM      );
+REG64( PU_IOP1_PCS_M4_CONTROL_REG                              ,
+       RULL(0x80000C040E01103F), SH_UNT_PU_IOP1  , SH_ACS_SCOM      );
+REG64( PU_IOP2_PCS_M4_CONTROL_REG                              ,
+       RULL(0x80000C040F01103F), SH_UNT_PU_IOP2  , SH_ACS_SCOM      );
+
+REG64( PU_IOP0_PCS_SYS_CONTROL_REG                             ,
+       RULL(0x80000C000D010C3F), SH_UNT_PU_IOP0  , SH_ACS_SCOM      );
+REG64( PU_IOP1_PCS_SYS_CONTROL_REG                             ,
+       RULL(0x80000C000E010C3F), SH_UNT_PU_IOP1  , SH_ACS_SCOM      );
+REG64( PU_IOP2_PCS_SYS_CONTROL_REG                             ,
+       RULL(0x80000C000F010C3F), SH_UNT_PU_IOP2  , SH_ACS_SCOM      );
+
+REG64( PU_PBAIB0_PECAPP_CNTL_REG                               ,
+       RULL(0x0D010800), SH_UNT_PU_PBAIB0, SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB1_PECAPP_CNTL_REG                               ,
+       RULL(0x0E010800), SH_UNT_PU_PBAIB1, SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB2_PECAPP_CNTL_REG                               ,
+       RULL(0x0F010800), SH_UNT_PU_PBAIB2, SH_ACS_SCOM_RW   );
+
+REG64( PU_PBAIB0_PECAPP_SEC_BAR                                ,
+       RULL(0x0D010801), SH_UNT_PU_PBAIB0, SH_ACS_SCOM      );
+REG64( PU_PBAIB1_PECAPP_SEC_BAR                                ,
+       RULL(0x0E010801), SH_UNT_PU_PBAIB1, SH_ACS_SCOM      );
+REG64( PU_PBAIB2_PECAPP_SEC_BAR                                ,
+       RULL(0x0F010801), SH_UNT_PU_PBAIB2, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_PERF_CONFIG                                 ,
+       RULL(0x05011087), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_PERF_CONFIG                                 ,
+       RULL(0x05011187), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_PERF_CONFIG                                 ,
+       RULL(0x05011287), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_PERF_CONFIG                                 ,
+       RULL(0x05011007), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_PERF_CONFIG                                 ,
+       RULL(0x05011027), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_PERF_CONFIG                                 ,
+       RULL(0x05011047), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_PERF_CONFIG                                 ,
+       RULL(0x05011067), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_PERF_CONFIG                                 ,
+       RULL(0x05011107), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_PERF_CONFIG                                 ,
+       RULL(0x05011127), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_PERF_CONFIG                                 ,
+       RULL(0x05011147), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_PERF_CONFIG                                 ,
+       RULL(0x05011167), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_PERF_CONFIG                                 ,
+       RULL(0x05011207), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_PERF_CONFIG                                 ,
+       RULL(0x05011227), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_PERF_CONFIG                                 ,
+       RULL(0x05011247), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_PERF_CONFIG                                 ,
+       RULL(0x05011267), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PEC_0_STACK0_PHBBAR_REG                                 ,
+       RULL(0x04010C52), SH_UNT_PEC_0_STACK0, SH_ACS_SCOM      );
+REG64( PEC_0_STACK1_PHBBAR_REG                                 ,
+       RULL(0x04010C92), SH_UNT_PEC_0_STACK1, SH_ACS_SCOM      );
+REG64( PEC_0_STACK2_PHBBAR_REG                                 ,
+       RULL(0x04010CD2), SH_UNT_PEC_0_STACK2, SH_ACS_SCOM      );
+REG64( PEC_1_STACK0_PHBBAR_REG                                 ,
+       RULL(0x04011052), SH_UNT_PEC_1_STACK0, SH_ACS_SCOM      );
+REG64( PEC_1_STACK1_PHBBAR_REG                                 ,
+       RULL(0x04011092), SH_UNT_PEC_1_STACK1, SH_ACS_SCOM      );
+REG64( PEC_1_STACK2_PHBBAR_REG                                 ,
+       RULL(0x040110D2), SH_UNT_PEC_1_STACK2, SH_ACS_SCOM      );
+REG64( PEC_2_STACK0_PHBBAR_REG                                 ,
+       RULL(0x04011452), SH_UNT_PEC_2_STACK0, SH_ACS_SCOM      );
+REG64( PEC_2_STACK1_PHBBAR_REG                                 ,
+       RULL(0x04011492), SH_UNT_PEC_2_STACK1, SH_ACS_SCOM      );
+REG64( PEC_2_STACK2_PHBBAR_REG                                 ,
+       RULL(0x040114D2), SH_UNT_PEC_2_STACK2, SH_ACS_SCOM      );
+REG64( PEC_STACK0_PHBBAR_REG                                   ,
+       RULL(0x04010C52), SH_UNT_PEC_STACK0, SH_ACS_SCOM      );
+REG64( PEC_STACK1_PHBBAR_REG                                   ,
+       RULL(0x04010C92), SH_UNT_PEC_STACK1, SH_ACS_SCOM      );
+REG64( PEC_STACK2_PHBBAR_REG                                   ,
+       RULL(0x04010CD2), SH_UNT_PEC_STACK2, SH_ACS_SCOM      );
+
+REG64( PU_PBAIB_STACK0_PHBRESET_REG                            ,
+       RULL(0x0D010840), SH_UNT_PU_PBAIB_STACK0, SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK1_PHBRESET_REG                            ,
+       RULL(0x0D010880), SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK2_PHBRESET_REG                            ,
+       RULL(0x0D0108C0), SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK3_PHBRESET_REG                            ,
+       RULL(0x0E010840), SH_UNT_PU_PBAIB_STACK3, SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK4_PHBRESET_REG                            ,
+       RULL(0x0E010880), SH_UNT_PU_PBAIB_STACK4, SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK5_PHBRESET_REG                            ,
+       RULL(0x0E0108C0), SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK6_PHBRESET_REG                            ,
+       RULL(0x0F010840), SH_UNT_PU_PBAIB_STACK6, SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK7_PHBRESET_REG                            ,
+       RULL(0x0F010880), SH_UNT_PU_PBAIB_STACK7, SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK8_PHBRESET_REG                            ,
+       RULL(0x0F0108C0), SH_UNT_PU_PBAIB_STACK8, SH_ACS_SCOM_RW   );
+
+REG64( PU_NPU0_SM0_PHY_BAR                                     ,
+       RULL(0x05011010), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_PHY_BAR                                     ,
+       RULL(0x05011030), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_PHY_BAR                                     ,
+       RULL(0x05011050), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_PHY_BAR                                     ,
+       RULL(0x05011070), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_PHY_BAR                                     ,
+       RULL(0x05011110), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_PHY_BAR                                     ,
+       RULL(0x05011130), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_PHY_BAR                                     ,
+       RULL(0x05011150), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_PHY_BAR                                     ,
+       RULL(0x05011170), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_PHY_BAR                                     ,
+       RULL(0x05011210), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_PHY_BAR                                     ,
+       RULL(0x05011230), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_PHY_BAR                                     ,
+       RULL(0x05011250), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_PHY_BAR                                     ,
+       RULL(0x05011270), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PU_PIBMEM_ADDRESS_REGISTER                              ,
+       RULL(0x00088001), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBMEM_ADDRESS_REGISTER_FA                           ,
+       RULL(0x00088007), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBMEM_CONTROL_REGISTER                              ,
+       RULL(0x00088000), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBMEM_REPAIR_REGISTER_0                             ,
+       RULL(0x0008800B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBMEM_REPAIR_REGISTER_1                             ,
+       RULL(0x0008800C), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBMEM_REPAIR_REGISTER_2                             ,
+       RULL(0x0008800D), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBMEM_RESET_REGISTER                                ,
+       RULL(0x00088006), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBMEM_STATUS_REG                                    ,
+       RULL(0x00088005), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIB_CMD_REG                                          ,
+       RULL(0x05022831), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIB_DATA_REG                                         ,
+       RULL(0x05022832), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PIB_RESET_REG                                        ,
+       RULL(0x05022833), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PEC_PMONCTL_REG                                         ,
+       RULL(0x04010C04), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_PMONCTL_REG                                       ,
+       RULL(0x04010C04), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_PMONCTL_REG                                       ,
+       RULL(0x04011004), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_PMONCTL_REG                                       ,
+       RULL(0x04011404), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( PU_PMU_CONTROL_2                                        ,
+       RULL(0x020110D8), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PPE_XIDBGPRO                                         ,
+       RULL(0x000E0005), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_PPE_XIDBGPRO                                    ,
+       RULL(0x00060015), SH_UNT_PU_GPE0  , SH_ACS_SCOM      );
+REG64( PU_GPE1_PPE_XIDBGPRO                                    ,
+       RULL(0x00062015), SH_UNT_PU_GPE1  , SH_ACS_SCOM      );
+REG64( PU_GPE2_PPE_XIDBGPRO                                    ,
+       RULL(0x00064015), SH_UNT_PU_GPE2  , SH_ACS_SCOM      );
+REG64( PU_GPE3_PPE_XIDBGPRO                                    ,
+       RULL(0x00066015), SH_UNT_PU_GPE3  , SH_ACS_SCOM      );
+
+REG64( PU_PPE_XIRAMDBG                                         ,
+       RULL(0x000E0003), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_PPE_XIRAMDBG                                    ,
+       RULL(0x00060013), SH_UNT_PU_GPE0  , SH_ACS_SCOM      );
+REG64( PU_GPE1_PPE_XIRAMDBG                                    ,
+       RULL(0x00062013), SH_UNT_PU_GPE1  , SH_ACS_SCOM      );
+REG64( PU_GPE2_PPE_XIRAMDBG                                    ,
+       RULL(0x00064013), SH_UNT_PU_GPE2  , SH_ACS_SCOM      );
+REG64( PU_GPE3_PPE_XIRAMDBG                                    ,
+       RULL(0x00066013), SH_UNT_PU_GPE3  , SH_ACS_SCOM      );
+
+REG64( PU_PPE_XIRAMEDR                                         ,
+       RULL(0x000E0004), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_PPE_XIRAMEDR                                    ,
+       RULL(0x00060014), SH_UNT_PU_GPE0  , SH_ACS_SCOM      );
+REG64( PU_GPE1_PPE_XIRAMEDR                                    ,
+       RULL(0x00062014), SH_UNT_PU_GPE1  , SH_ACS_SCOM      );
+REG64( PU_GPE2_PPE_XIRAMEDR                                    ,
+       RULL(0x00064014), SH_UNT_PU_GPE2  , SH_ACS_SCOM      );
+REG64( PU_GPE3_PPE_XIRAMEDR                                    ,
+       RULL(0x00066014), SH_UNT_PU_GPE3  , SH_ACS_SCOM      );
+
+REG64( PU_PPE_XIRAMGA                                          ,
+       RULL(0x000E0002), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE0_PPE_XIRAMGA                                     ,
+       RULL(0x00060012), SH_UNT_PU_GPE0  , SH_ACS_SCOM_WO   );
+REG64( PU_GPE1_PPE_XIRAMGA                                     ,
+       RULL(0x00062012), SH_UNT_PU_GPE1  , SH_ACS_SCOM_WO   );
+REG64( PU_GPE2_PPE_XIRAMGA                                     ,
+       RULL(0x00064012), SH_UNT_PU_GPE2  , SH_ACS_SCOM_WO   );
+REG64( PU_GPE3_PPE_XIRAMGA                                     ,
+       RULL(0x00066012), SH_UNT_PU_GPE3  , SH_ACS_SCOM_WO   );
+
+REG64( PU_PPE_XIRAMRA                                          ,
+       RULL(0x000E0001), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE0_PPE_XIRAMRA                                     ,
+       RULL(0x00060011), SH_UNT_PU_GPE0  , SH_ACS_SCOM_WO   );
+REG64( PU_GPE1_PPE_XIRAMRA                                     ,
+       RULL(0x00062011), SH_UNT_PU_GPE1  , SH_ACS_SCOM_WO   );
+REG64( PU_GPE2_PPE_XIRAMRA                                     ,
+       RULL(0x00064011), SH_UNT_PU_GPE2  , SH_ACS_SCOM_WO   );
+REG64( PU_GPE3_PPE_XIRAMRA                                     ,
+       RULL(0x00066011), SH_UNT_PU_GPE3  , SH_ACS_SCOM_WO   );
+
+REG64( PU_PPE_XIXCR                                            ,
+       RULL(0x000E0000), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE0_PPE_XIXCR                                       ,
+       RULL(0x00060010), SH_UNT_PU_GPE0  , SH_ACS_SCOM_WO   );
+REG64( PU_GPE1_PPE_XIXCR                                       ,
+       RULL(0x00062010), SH_UNT_PU_GPE1  , SH_ACS_SCOM_WO   );
+REG64( PU_GPE2_PPE_XIXCR                                       ,
+       RULL(0x00064010), SH_UNT_PU_GPE2  , SH_ACS_SCOM_WO   );
+REG64( PU_GPE3_PPE_XIXCR                                       ,
+       RULL(0x00066010), SH_UNT_PU_GPE3  , SH_ACS_SCOM_WO   );
+
+REG64( PEC_PREDV_REG                                           ,
+       RULL(0x04010C06), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_PREDV_REG                                         ,
+       RULL(0x04010C06), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_PREDV_REG                                         ,
+       RULL(0x04011006), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_PREDV_REG                                         ,
+       RULL(0x04011406), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( PU_PRGM_REGISTER                                        ,
+       RULL(0x00010009), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PROBE_PROTECT_STATUS                                 ,
+       RULL(0x0001000A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSIHB_DEBUG_REG                                      ,
+       RULL(0x05012911), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSIHB_ERROR_MASK_REG                                 ,
+       RULL(0x0501290F), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSIHB_FIR_ACTION0_REG                                ,
+       RULL(0x05012906), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PSIHB_FIR_ACTION1_REG                                ,
+       RULL(0x05012907), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PSIHB_FIR_MASK_REG                                   ,
+       RULL(0x05012903), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PSIHB_FIR_MASK_REG_AND                               ,
+       RULL(0x05012904), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PSIHB_FIR_MASK_REG_OR                                ,
+       RULL(0x05012905), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_PSIHB_FIR_REG                                        ,
+       RULL(0x05012900), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PSIHB_FIR_REG_AND                                    ,
+       RULL(0x05012901), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PSIHB_FIR_REG_OR                                     ,
+       RULL(0x05012902), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_PSIHB_INTERRUPT_CONTROL                              ,
+       RULL(0x05012915), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSIHB_INTERRUPT_STATUS                               ,
+       RULL(0x05012919), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSIHB_STATUS_CTL_REG_SCOM                            ,
+       RULL(0x0501290E), SH_UNT          , SH_ACS_SCOM      );
+REG64( PU_PSIHB_STATUS_CTL_REG_SCOM1                           ,
+       RULL(0x05012912), SH_UNT          , SH_ACS_SCOM1     );
+REG64( PU_PSIHB_STATUS_CTL_REG_SCOM2                           ,
+       RULL(0x05012913), SH_UNT          , SH_ACS_SCOM2     );
+
+REG64( PU_PSI_BRIDGE_BAR_REG                                   ,
+       RULL(0x0501290A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSI_BRIDGE_FSP_BAR_REG                               ,
+       RULL(0x0501290B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSI_FSP_MMR_REG                                      ,
+       RULL(0x0501290C), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSI_TCE_ADDR_REG                                     ,
+       RULL(0x05015F44), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_HOST_SBE_MBOX0_REG                               ,
+       RULL(0x000D0050), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_HOST_SBE_MBOX1_REG                               ,
+       RULL(0x000D0051), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_HOST_SBE_MBOX2_REG                               ,
+       RULL(0x000D0052), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_HOST_SBE_MBOX3_REG                               ,
+       RULL(0x000D0053), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_HOST_SBE_MBOX4_REG                               ,
+       RULL(0x000D0054), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_HOST_SBE_MBOX5_REG                               ,
+       RULL(0x000D0055), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_HOST_SBE_MBOX6_REG                               ,
+       RULL(0x000D0056), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_HOST_SBE_MBOX7_REG                               ,
+       RULL(0x000D0057), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR0_ACTCYCLECNT_REG                           ,
+       RULL(0x000D0023), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR0_CYCLECNT_REG                              ,
+       RULL(0x000D0022), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR0_EVENTCNT_REG                              ,
+       RULL(0x000D0024), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR0_FILTER_REG                                ,
+       RULL(0x000D0021), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR0_MAXCYCLECNT_REG                           ,
+       RULL(0x000D0025), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR0_MINCYCLECNT_REG                           ,
+       RULL(0x000D0026), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR0_STOP_TIMER_REG                            ,
+       RULL(0x000D0020), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR1_ACTCYCLECNT_REG                           ,
+       RULL(0x000D0033), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR1_CYCLECNT_REG                              ,
+       RULL(0x000D0032), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR1_EVENTCNT_REG                              ,
+       RULL(0x000D0034), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR1_FILTER_REG                                ,
+       RULL(0x000D0031), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR1_MAXCYCLECNT_REG                           ,
+       RULL(0x000D0035), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR1_MINCYCLECNT_REG                           ,
+       RULL(0x000D0036), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR1_STOP_TIMER_REG                            ,
+       RULL(0x000D0030), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR2_ACTCYCLECNT_REG                           ,
+       RULL(0x000D0043), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR2_CYCLECNT_REG                              ,
+       RULL(0x000D0042), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR2_EVENTCNT_REG                              ,
+       RULL(0x000D0044), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR2_FILTER_REG                                ,
+       RULL(0x000D0041), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR2_MAXCYCLECNT_REG                           ,
+       RULL(0x000D0045), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR2_MINCYCLECNT_REG                           ,
+       RULL(0x000D0046), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR2_STOP_TIMER_REG                            ,
+       RULL(0x000D0040), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR_CTRL_STATUS_REG                            ,
+       RULL(0x000D0010), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_PIBHIST_2NDLAST_ADDR_TRACE_REG                   ,
+       RULL(0x000D0005), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_PIBHIST_2NDLAST_REQDATA_TRACE_REG                ,
+       RULL(0x000D0006), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_PIBHIST_2NDLAST_RSPDATA_TRACE_REG                ,
+       RULL(0x000D0007), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_PIBHIST_CTRL_STATUS_REG                          ,
+       RULL(0x000D0000), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_PIBHIST_FILTER_REG                               ,
+       RULL(0x000D0001), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_PIBHIST_LAST_ADDR_TRACE_REG                      ,
+       RULL(0x000D0002), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_PIBHIST_LAST_REQDATA_TRACE_REG                   ,
+       RULL(0x000D0003), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_PIBHIST_LAST_RSPDATA_TRACE_REG                   ,
+       RULL(0x000D0004), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_SBE_DOORBELL0_REG                                ,
+       RULL(0x000D0060), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PSU_SBE_DOORBELL0_REG_AND                            ,
+       RULL(0x000D0061), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PSU_SBE_DOORBELL0_REG_OR                             ,
+       RULL(0x000D0062), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_PSU_SBE_DOORBELL1_REG                                ,
+       RULL(0x000D0063), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PSU_SBE_DOORBELL1_REG_AND                            ,
+       RULL(0x000D0064), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PSU_SBE_DOORBELL1_REG_OR                             ,
+       RULL(0x000D0065), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_RCV_ERRLOG0_REG                                      ,
+       RULL(0x05022822), SH_UNT          , SH_ACS_SCOM_WAND );
+
+REG64( PU_RCV_ERRLOG1_REG                                      ,
+       RULL(0x05022823), SH_UNT          , SH_ACS_SCOM_WAND );
+
+REG64( PU_NPU0_SM0_RELAXED_CMD                                 ,
+       RULL(0x05011006), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_RELAXED_CMD                                 ,
+       RULL(0x05011026), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_RELAXED_CMD                                 ,
+       RULL(0x05011046), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_RELAXED_CMD                                 ,
+       RULL(0x05011066), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_RELAXED_CMD                                 ,
+       RULL(0x05011106), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_RELAXED_CMD                                 ,
+       RULL(0x05011126), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_RELAXED_CMD                                 ,
+       RULL(0x05011146), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_RELAXED_CMD                                 ,
+       RULL(0x05011166), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_RELAXED_CMD                                 ,
+       RULL(0x05011206), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_RELAXED_CMD                                 ,
+       RULL(0x05011226), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_RELAXED_CMD                                 ,
+       RULL(0x05011246), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_RELAXED_CMD                                 ,
+       RULL(0x05011266), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SM0_RELAXED_SOURCE                              ,
+       RULL(0x05011005), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_RELAXED_SOURCE                              ,
+       RULL(0x05011025), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_RELAXED_SOURCE                              ,
+       RULL(0x05011045), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_RELAXED_SOURCE                              ,
+       RULL(0x05011065), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_RELAXED_SOURCE                              ,
+       RULL(0x05011105), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_RELAXED_SOURCE                              ,
+       RULL(0x05011125), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_RELAXED_SOURCE                              ,
+       RULL(0x05011145), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_RELAXED_SOURCE                              ,
+       RULL(0x05011165), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_RELAXED_SOURCE                              ,
+       RULL(0x05011205), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_RELAXED_SOURCE                              ,
+       RULL(0x05011225), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_RELAXED_SOURCE                              ,
+       RULL(0x05011245), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_RELAXED_SOURCE                              ,
+       RULL(0x05011265), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PU_PIB2OPB0_RESET                                       ,
+       RULL(0x00020004), SH_UNT_PU_PIB2OPB0, SH_ACS_SCOM      );
+REG64( PU_PIB2OPB1_RESET                                       ,
+       RULL(0x00020014), SH_UNT_PU_PIB2OPB1, SH_ACS_SCOM      );
+
+REG64( PU_RESET_REGISTER_B                                     ,
+       RULL(0x000A0001), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_RESET_REGISTER_C                                     ,
+       RULL(0x000A1001), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_RESET_REGISTER_D                                     ,
+       RULL(0x000A2001), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_RESET_REGISTER_E                                     ,
+       RULL(0x000A3001), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B                 ,
+       RULL(0x000A000D), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C                 ,
+       RULL(0x000A100D), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D                 ,
+       RULL(0x000A200D), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E                 ,
+       RULL(0x000A300D), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_NPU_CTL_RLX_CONFIG                                   ,
+       RULL(0x05011381), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM      );
+
+REG64( PU_RNG_FAILED_INT                                       ,
+       RULL(0x020110E7), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIB2OPB0_RSIC                                        ,
+       RULL(0x00020008), SH_UNT_PU_PIB2OPB0, SH_ACS_SCOM_WCLEAR );
+REG64( PU_PIB2OPB1_RSIC                                        ,
+       RULL(0x00020018), SH_UNT_PU_PIB2OPB1, SH_ACS_SCOM_WCLEAR );
+
+REG64( PU_PIB2OPB0_RSIM                                        ,
+       RULL(0x00020009), SH_UNT_PU_PIB2OPB0, SH_ACS_SCOM_RW   );
+REG64( PU_PIB2OPB1_RSIM                                        ,
+       RULL(0x00020019), SH_UNT_PU_PIB2OPB1, SH_ACS_SCOM_RW   );
+
+REG64( PU_PIB2OPB0_RSIS                                        ,
+       RULL(0x0002000A), SH_UNT_PU_PIB2OPB0, SH_ACS_SCOM_RO   );
+REG64( PU_PIB2OPB1_RSIS                                        ,
+       RULL(0x0002001A), SH_UNT_PU_PIB2OPB1, SH_ACS_SCOM_RO   );
+
+REG64( PU_RX_CH_FSM_REG                                        ,
+       RULL(0x0501280D), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RX_CH_INTADDR_REG                                    ,
+       RULL(0x05012818), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RX_CH_MISC_REG                                       ,
+       RULL(0x0501281B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RX_CTRL_STAT_REG                                     ,
+       RULL(0x05012808), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RX_DBFF_REG0                                         ,
+       RULL(0x05012819), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RX_DBFF_REG1                                         ,
+       RULL(0x0501281A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RX_DF_FSM_REG                                        ,
+       RULL(0x0501280E), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RX_ERROR_REG_WCLEAR                                  ,
+       RULL(0x0501280A), SH_UNT          , SH_ACS_SCOM_WCLEAR );
+REG64( PU_RX_ERROR_REG_OR                                      ,
+       RULL(0x0501280C), SH_UNT          , SH_ACS_SCOM1_OR  );
+
+REG64( PU_RX_ERR_MODE                                          ,
+       RULL(0x0501280F), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RX_MASK_REG                                          ,
+       RULL(0x0501280B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RX_PSI_CNTL                                          ,
+       RULL(0x04011820), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RX_PSI_MODE                                          ,
+       RULL(0x04011821), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RX_PSI_STATUS                                        ,
+       RULL(0x04011822), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SCRATCH0                                        ,
+       RULL(0x050110AB), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_SCRATCH0                                        ,
+       RULL(0x050111AB), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_SCRATCH0                                        ,
+       RULL(0x050112AB), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_DAT_SCRATCH1                                    ,
+       RULL(0x050110BC), SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM      );
+REG64( PU_NPU1_DAT_SCRATCH1                                    ,
+       RULL(0x050111BC), SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM      );
+REG64( PU_NPU2_DAT_SCRATCH1                                    ,
+       RULL(0x050112BC), SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM      );
+REG64( PU_NPU0_NTL0_SCRATCH1                                   ,
+       RULL(0x050110D4), SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU0_NTL1_SCRATCH1                                   ,
+       RULL(0x050110F4), SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU1_NTL0_SCRATCH1                                   ,
+       RULL(0x050111D4), SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU1_NTL1_SCRATCH1                                   ,
+       RULL(0x050111F4), SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_SCRATCH1                                   ,
+       RULL(0x050112D4), SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_SCRATCH1                                   ,
+       RULL(0x050112F4), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_NTL0_SCRATCH2                                   ,
+       RULL(0x050110CC), SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU0_NTL1_SCRATCH2                                   ,
+       RULL(0x050110EC), SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU1_NTL0_SCRATCH2                                   ,
+       RULL(0x050111CC), SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU1_NTL1_SCRATCH2                                   ,
+       RULL(0x050111EC), SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_SCRATCH2                                   ,
+       RULL(0x050112CC), SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_SCRATCH2                                   ,
+       RULL(0x050112EC), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_NTL0_SCRATCH3                                   ,
+       RULL(0x050110CD), SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU0_NTL1_SCRATCH3                                   ,
+       RULL(0x050110ED), SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU1_NTL0_SCRATCH3                                   ,
+       RULL(0x050111CD), SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU1_NTL1_SCRATCH3                                   ,
+       RULL(0x050111ED), SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_SCRATCH3                                   ,
+       RULL(0x050112CD), SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_SCRATCH3                                   ,
+       RULL(0x050112ED), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM      );
+
+REG64( PU_SECURITY_SWITCH_REGISTER_SCOM                        ,
+       RULL(0x00010005), SH_UNT          , SH_ACS_SCOM_WOR  );
+REG64( PU_SECURITY_SWITCH_REGISTER_SCOM1                       ,
+       RULL(0x00010006), SH_UNT          , SH_ACS_SCOM1     );
+
+REG64( PU_SEND_WC_BASE_ADDR                                    ,
+       RULL(0x020110D2), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SM0_SM_HOLD                                     ,
+       RULL(0x05011017), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_SM_HOLD                                     ,
+       RULL(0x05011037), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_SM_HOLD                                     ,
+       RULL(0x05011057), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_SM_HOLD                                     ,
+       RULL(0x05011077), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_SM_HOLD                                     ,
+       RULL(0x05011117), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_SM_HOLD                                     ,
+       RULL(0x05011137), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_SM_HOLD                                     ,
+       RULL(0x05011157), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_SM_HOLD                                     ,
+       RULL(0x05011177), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_SM_HOLD                                     ,
+       RULL(0x05011217), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_SM_HOLD                                     ,
+       RULL(0x05011237), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_SM_HOLD                                     ,
+       RULL(0x05011257), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_SM_HOLD                                     ,
+       RULL(0x05011277), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SM0_SM_MASK                                     ,
+       RULL(0x05011018), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_SM_MASK                                     ,
+       RULL(0x05011038), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_SM_MASK                                     ,
+       RULL(0x05011058), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_SM_MASK                                     ,
+       RULL(0x05011078), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_SM_MASK                                     ,
+       RULL(0x05011118), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_SM_MASK                                     ,
+       RULL(0x05011138), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_SM_MASK                                     ,
+       RULL(0x05011158), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_SM_MASK                                     ,
+       RULL(0x05011178), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_SM_MASK                                     ,
+       RULL(0x05011218), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_SM_MASK                                     ,
+       RULL(0x05011238), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_SM_MASK                                     ,
+       RULL(0x05011258), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_SM_MASK                                     ,
+       RULL(0x05011278), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PU_SND_MODE_REG                                         ,
+       RULL(0x05022821), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SND_STAT_REG                                         ,
+       RULL(0x05022820), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIMPSS_ADC_CTRL_REG0                                ,
+       RULL(0x00070000), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_100NS_REG                                     ,
+       RULL(0x00070028), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_ADC_CMD_REG                                   ,
+       RULL(0x00070004), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_ADC_CTRL_REG1                                 ,
+       RULL(0x00070001), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_ADC_CTRL_REG2                                 ,
+       RULL(0x00070002), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_ADC_RDATA_REG0                                ,
+       RULL(0x00070020), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_ADC_RDATA_REG1                                ,
+       RULL(0x00070021), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_ADC_RDATA_REG2                                ,
+       RULL(0x00070022), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_ADC_RDATA_REG3                                ,
+       RULL(0x00070023), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_ADC_RESET_REGISTER                            ,
+       RULL(0x00070005), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_ADC_STATUS_REG                                ,
+       RULL(0x00070003), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_ADC_WDATA_REG                                 ,
+       RULL(0x00070010), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_P2S_COMMAND_REG                               ,
+       RULL(0x00070044), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_P2S_CTRL_REG0                                 ,
+       RULL(0x00070040), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_P2S_CTRL_REG1                                 ,
+       RULL(0x00070041), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_P2S_CTRL_REG2                                 ,
+       RULL(0x00070042), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_P2S_RDATA_REG                                 ,
+       RULL(0x00070060), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_P2S_RESET_REGISTER                            ,
+       RULL(0x00070045), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_P2S_STATUS_REG                                ,
+       RULL(0x00070043), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_P2S_WDATA_REG                                 ,
+       RULL(0x00070050), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GPE5_SRAM_SRBV0_OCI                                  ,
+       RULL(0xC0050020), SH_UNT_PU_GPE5  , SH_ACS_OCI       );
+REG64( PU_GPE5_SRAM_SRBV0_SCOM                                 ,
+       RULL(0x0006A004), SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE5_SRAM_SRBV1_OCI                                  ,
+       RULL(0xC0050028), SH_UNT_PU_GPE5  , SH_ACS_OCI       );
+REG64( PU_GPE5_SRAM_SRBV1_SCOM                                 ,
+       RULL(0x0006A005), SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE5_SRAM_SRBV2_OCI                                  ,
+       RULL(0xC0050030), SH_UNT_PU_GPE5  , SH_ACS_OCI       );
+REG64( PU_GPE5_SRAM_SRBV2_SCOM                                 ,
+       RULL(0x0006A006), SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE5_SRAM_SRBV3_OCI                                  ,
+       RULL(0xC0050038), SH_UNT_PU_GPE5  , SH_ACS_OCI       );
+REG64( PU_GPE5_SRAM_SRBV3_SCOM                                 ,
+       RULL(0x0006A007), SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE5_SRAM_SRCHSW_OCI                                 ,
+       RULL(0xC0050040), SH_UNT_PU_GPE5  , SH_ACS_OCI       );
+REG64( PU_GPE5_SRAM_SRCHSW_SCOM                                ,
+       RULL(0x0006A008), SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE5_SRAM_SREAR_OCI                                  ,
+       RULL(0xC0050018), SH_UNT_PU_GPE5  , SH_ACS_OCI       );
+REG64( PU_GPE5_SRAM_SREAR_SCOM                                 ,
+       RULL(0x0006A003), SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE5_SRAM_SRMAP_OCI                                  ,
+       RULL(0xC0050010), SH_UNT_PU_GPE5  , SH_ACS_OCI       );
+REG64( PU_GPE5_SRAM_SRMAP_SCOM                                 ,
+       RULL(0x0006A002), SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE5_SRAM_SRMR_OCI                                   ,
+       RULL(0xC0050008), SH_UNT_PU_GPE5  , SH_ACS_OCI       );
+REG64( PU_GPE5_SRAM_SRMR_SCOM                                  ,
+       RULL(0x0006A001), SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW   );
+
+REG64( PU_STATUS_REGISTER                                      ,
+       RULL(0x00010002), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_STATUS_REGISTER_B                                    ,
+       RULL(0x000A0002), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_STATUS_REGISTER_C                                    ,
+       RULL(0x000A1002), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_STATUS_REGISTER_D                                    ,
+       RULL(0x000A2002), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_STATUS_REGISTER_E                                    ,
+       RULL(0x000A3002), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_STATUS_REGISTER_ENGINE_B                             ,
+       RULL(0x000A000B), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_STATUS_REGISTER_ENGINE_C                             ,
+       RULL(0x000A100B), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_STATUS_REGISTER_ENGINE_D                             ,
+       RULL(0x000A200B), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_STATUS_REGISTER_ENGINE_E                             ,
+       RULL(0x000A300B), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_PIB2OPB0_STAT_RDDAT_ERRES                            ,
+       RULL(0x00020001), SH_UNT_PU_PIB2OPB0, SH_ACS_SCOM_RO   );
+REG64( PU_PIB2OPB1_STAT_RDDAT_ERRES                            ,
+       RULL(0x00020011), SH_UNT_PU_PIB2OPB1, SH_ACS_SCOM_RO   );
+
+REG64( PU_SU_CH0_ABORT_CSB                                     ,
+       RULL(0x02011043), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SU_CH1_ABORT_CSB                                     ,
+       RULL(0x02011045), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SU_CH2_ABORT_CSB                                     ,
+       RULL(0x02011047), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SU_CH3_ABORT_CSB                                     ,
+       RULL(0x02011049), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SU_CH4_ABORT_CSB                                     ,
+       RULL(0x0201104B), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SU_CRB_KILL_REQ                                      ,
+       RULL(0x02011053), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_SU_DMA_ERROR_REPORT_0                                ,
+       RULL(0x02011057), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SU_DMA_ERROR_REPORT_1                                ,
+       RULL(0x02011058), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SU_ENGINE_ENABLE                                     ,
+       RULL(0x02011041), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SU_ERAT_ERROR_RPT                                    ,
+       RULL(0x020110D7), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SU_INBOUND_WRITE_CONTROL                             ,
+       RULL(0x02011042), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_SU_MARKER_TRACE_CONTROL                              ,
+       RULL(0x02011056), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_SU_PERFMON_CONTROL_0                                 ,
+       RULL(0x02011054), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_SU_PERFMON_CONTROL_1                                 ,
+       RULL(0x02011055), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_SU_STATUS                                            ,
+       RULL(0x02011040), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SU_UMAC_ERROR_RPT                                    ,
+       RULL(0x020110D3), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SYM_HI_PRIOR_RCV_FIFO_ASB                            ,
+       RULL(0x020110C7), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SYM_HI_PRIOR_RCV_FIFO_BAR                            ,
+       RULL(0x020110C1), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SYM_HI_PRIOR_RCV_FIFO_CNTL                           ,
+       RULL(0x020110C4), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SYM_LO_PRIOR_RCV_FIFO_ASB                            ,
+       RULL(0x020110D0), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SYM_LO_PRIOR_RCV_FIFO_BAR                            ,
+       RULL(0x020110CA), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SYM_LO_PRIOR_RCV_FIFO_CNTL                           ,
+       RULL(0x020110CD), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SYM_MAX_BYTE_CNT                                     ,
+       RULL(0x0201105A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_SYNC_FIR_ACTION0_REG                                 ,
+       RULL(0x050129C6), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SYNC_FIR_ACTION1_REG                                 ,
+       RULL(0x050129C7), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SYNC_FIR_MASK_REG                                    ,
+       RULL(0x050129C3), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_SYNC_FIR_MASK_REG_AND                                ,
+       RULL(0x050129C4), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_SYNC_FIR_MASK_REG_OR                                 ,
+       RULL(0x050129C5), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_SYNC_FIR_REG                                         ,
+       RULL(0x050129C0), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_SYNC_FIR_REG_AND                                     ,
+       RULL(0x050129C1), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_SYNC_FIR_REG_OR                                      ,
+       RULL(0x050129C2), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_NPU_SM1_TCE_KILL                                     ,
+       RULL(0x05011320), SH_UNT_PU_NPU_SM1, SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_SLOW_TRA0_TRACE_HI_DATA_REG                   ,
+       RULL(0x07010400), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG                   ,
+       RULL(0x07010401), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCMC01_SLOW_TRA0_TRACE_TRCTRL_CONFIG                 ,
+       RULL(0x07010402), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_0               ,
+       RULL(0x07010403), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_1               ,
+       RULL(0x07010404), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_2               ,
+       RULL(0x07010405), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_3               ,
+       RULL(0x07010406), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_4               ,
+       RULL(0x07010407), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_5               ,
+       RULL(0x07010408), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9               ,
+       RULL(0x07010409), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_SLOW_TRA0_TRACE_HI_DATA_REG                   ,
+       RULL(0x08010400), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCMC23_SLOW_TRA0_TRACE_LO_DATA_REG                   ,
+       RULL(0x08010401), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCMC23_SLOW_TRA0_TRACE_TRCTRL_CONFIG                 ,
+       RULL(0x08010402), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_0               ,
+       RULL(0x08010403), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_1               ,
+       RULL(0x08010404), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_2               ,
+       RULL(0x08010405), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_3               ,
+       RULL(0x08010406), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_4               ,
+       RULL(0x08010407), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_5               ,
+       RULL(0x08010408), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9               ,
+       RULL(0x08010409), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR0_TRACE_HI_DATA_REG                      ,
+       RULL(0x02010400), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG                      ,
+       RULL(0x02010401), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x02010402), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x02010403), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x02010404), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x02010405), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x02010406), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x02010407), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x02010408), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x02010409), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR1_TRACE_HI_DATA_REG                      ,
+       RULL(0x02010440), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG                      ,
+       RULL(0x02010441), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x02010442), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x02010443), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x02010444), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x02010445), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x02010446), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x02010447), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x02010448), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x02010449), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA1_TRACE_HI_DATA_REG                          ,
+       RULL(0x02010480), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN0_TRA1_TRACE_LO_DATA_REG                          ,
+       RULL(0x02010481), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN0_TRA1_TRACE_TRCTRL_CONFIG                        ,
+       RULL(0x02010482), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_0                      ,
+       RULL(0x02010483), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_1                      ,
+       RULL(0x02010484), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_2                      ,
+       RULL(0x02010485), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_3                      ,
+       RULL(0x02010486), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_4                      ,
+       RULL(0x02010487), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_5                      ,
+       RULL(0x02010488), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9                      ,
+       RULL(0x02010489), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR0_TRACE_HI_DATA_REG                      ,
+       RULL(0x03010400), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG                      ,
+       RULL(0x03010401), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x03010402), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x03010403), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x03010404), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x03010405), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x03010406), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x03010407), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x03010408), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x03010409), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR1_TRACE_HI_DATA_REG                      ,
+       RULL(0x03010440), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG                      ,
+       RULL(0x03010441), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x03010442), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x03010443), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x03010444), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x03010445), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x03010446), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x03010447), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x03010448), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x03010449), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR0_TRACE_HI_DATA_REG                      ,
+       RULL(0x03010480), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG                      ,
+       RULL(0x03010481), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x03010482), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x03010483), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x03010484), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x03010485), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x03010486), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x03010487), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x03010488), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x03010489), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR1_TRACE_HI_DATA_REG                      ,
+       RULL(0x030104C0), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG                      ,
+       RULL(0x030104C1), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x030104C2), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x030104C3), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x030104C4), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x030104C5), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x030104C6), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x030104C7), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x030104C8), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x030104C9), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR0_TRACE_HI_DATA_REG                      ,
+       RULL(0x03010500), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG                      ,
+       RULL(0x03010501), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x03010502), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x03010503), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x03010504), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x03010505), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x03010506), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x03010507), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x03010508), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x03010509), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR1_TRACE_HI_DATA_REG                      ,
+       RULL(0x03010540), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG                      ,
+       RULL(0x03010541), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x03010542), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x03010543), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x03010544), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x03010545), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x03010546), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x03010547), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x03010548), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x03010549), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR0_TRACE_HI_DATA_REG                      ,
+       RULL(0x03010580), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG                      ,
+       RULL(0x03010581), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x03010582), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x03010583), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x03010584), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x03010585), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x03010586), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x03010587), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x03010588), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x03010589), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR1_TRACE_HI_DATA_REG                      ,
+       RULL(0x030105C0), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG                      ,
+       RULL(0x030105C1), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x030105C2), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x030105C3), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x030105C4), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x030105C5), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x030105C6), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x030105C7), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x030105C8), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x030105C9), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR0_TRACE_HI_DATA_REG                      ,
+       RULL(0x03010600), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG                      ,
+       RULL(0x03010601), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x03010602), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x03010603), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x03010604), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x03010605), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x03010606), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x03010607), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x03010608), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x03010609), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR1_TRACE_HI_DATA_REG                      ,
+       RULL(0x03010640), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG                      ,
+       RULL(0x03010641), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x03010642), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x03010643), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x03010644), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x03010645), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x03010646), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x03010647), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x03010648), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x03010649), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR0_TRACE_HI_DATA_REG                      ,
+       RULL(0x04010400), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG                      ,
+       RULL(0x04010401), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x04010402), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x04010403), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x04010404), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x04010405), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x04010406), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x04010407), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x04010408), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x04010409), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR1_TRACE_HI_DATA_REG                      ,
+       RULL(0x04010440), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG                      ,
+       RULL(0x04010441), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x04010442), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x04010443), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x04010444), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x04010445), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x04010446), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x04010447), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x04010448), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x04010449), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR0_TRACE_HI_DATA_REG                      ,
+       RULL(0x05010400), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG                      ,
+       RULL(0x05010401), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x05010402), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x05010403), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x05010404), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x05010405), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x05010406), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x05010407), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x05010408), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x05010409), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR1_TRACE_HI_DATA_REG                      ,
+       RULL(0x05010440), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG                      ,
+       RULL(0x05010441), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x05010442), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x05010443), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x05010444), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x05010445), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x05010446), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x05010447), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x05010448), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x05010449), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR0_TRACE_HI_DATA_REG                      ,
+       RULL(0x05010480), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG                      ,
+       RULL(0x05010481), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x05010482), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x05010483), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x05010484), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x05010485), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x05010486), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x05010487), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x05010488), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x05010489), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR1_TRACE_HI_DATA_REG                      ,
+       RULL(0x050104C0), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG                      ,
+       RULL(0x050104C1), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x050104C2), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x050104C3), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x050104C4), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x050104C5), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x050104C6), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x050104C7), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x050104C8), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x050104C9), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR0_TRACE_HI_DATA_REG                      ,
+       RULL(0x05010500), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG                      ,
+       RULL(0x05010501), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x05010502), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x05010503), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x05010504), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x05010505), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x05010506), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x05010507), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x05010508), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x05010509), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR1_TRACE_HI_DATA_REG                      ,
+       RULL(0x05010540), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG                      ,
+       RULL(0x05010541), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x05010542), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x05010543), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x05010544), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x05010545), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x05010546), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x05010547), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x05010548), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x05010549), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR0_TRACE_HI_DATA_REG                      ,
+       RULL(0x05010580), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG                      ,
+       RULL(0x05010581), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x05010582), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x05010583), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x05010584), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x05010585), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x05010586), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x05010587), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x05010588), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x05010589), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR1_TRACE_HI_DATA_REG                      ,
+       RULL(0x050105C0), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG                      ,
+       RULL(0x050105C1), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x050105C2), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x050105C3), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x050105C4), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x050105C5), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x050105C6), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x050105C7), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x050105C8), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x050105C9), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA4_TRACE_HI_DATA_REG                          ,
+       RULL(0x05010600), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA4_TRACE_LO_DATA_REG                          ,
+       RULL(0x05010601), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA4_TRACE_TRCTRL_CONFIG                        ,
+       RULL(0x05010602), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_0                      ,
+       RULL(0x05010603), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_1                      ,
+       RULL(0x05010604), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_2                      ,
+       RULL(0x05010605), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_3                      ,
+       RULL(0x05010606), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_4                      ,
+       RULL(0x05010607), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_5                      ,
+       RULL(0x05010608), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9                      ,
+       RULL(0x05010609), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR0_TRACE_HI_DATA_REG                      ,
+       RULL(0x05010680), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG                      ,
+       RULL(0x05010681), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x05010682), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x05010683), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x05010684), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x05010685), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x05010686), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x05010687), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x05010688), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x05010689), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR1_TRACE_HI_DATA_REG                      ,
+       RULL(0x050106C0), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG                      ,
+       RULL(0x050106C1), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x050106C2), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x050106C3), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x050106C4), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x050106C5), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x050106C6), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x050106C7), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x050106C8), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x050106C9), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI0_TRA0_TRACE_HI_DATA_REG                        ,
+       RULL(0x0D010400), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCPCI0_TRA0_TRACE_LO_DATA_REG                        ,
+       RULL(0x0D010401), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCPCI0_TRA0_TRACE_TRCTRL_CONFIG                      ,
+       RULL(0x0D010402), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_0                    ,
+       RULL(0x0D010403), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_1                    ,
+       RULL(0x0D010404), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_2                    ,
+       RULL(0x0D010405), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_3                    ,
+       RULL(0x0D010406), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_4                    ,
+       RULL(0x0D010407), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_5                    ,
+       RULL(0x0D010408), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9                    ,
+       RULL(0x0D010409), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI1_TRA0_TRACE_HI_DATA_REG                        ,
+       RULL(0x0E010400), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCPCI1_TRA0_TRACE_LO_DATA_REG                        ,
+       RULL(0x0E010401), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCPCI1_TRA0_TRACE_TRCTRL_CONFIG                      ,
+       RULL(0x0E010402), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_0                    ,
+       RULL(0x0E010403), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_1                    ,
+       RULL(0x0E010404), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_2                    ,
+       RULL(0x0E010405), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_3                    ,
+       RULL(0x0E010406), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_4                    ,
+       RULL(0x0E010407), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_5                    ,
+       RULL(0x0E010408), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9                    ,
+       RULL(0x0E010409), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI2_TRA0_TRACE_HI_DATA_REG                        ,
+       RULL(0x0F010400), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCPCI2_TRA0_TRACE_LO_DATA_REG                        ,
+       RULL(0x0F010401), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCPCI2_TRA0_TRACE_TRCTRL_CONFIG                      ,
+       RULL(0x0F010402), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_0                    ,
+       RULL(0x0F010403), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_1                    ,
+       RULL(0x0F010404), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_2                    ,
+       RULL(0x0F010405), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_3                    ,
+       RULL(0x0F010406), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_4                    ,
+       RULL(0x0F010407), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_5                    ,
+       RULL(0x0F010408), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9                    ,
+       RULL(0x0F010409), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA0_TR0_TRACE_HI_DATA_REG                      ,
+       RULL(0x06010400), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCXB_TRA0_TR0_TRACE_LO_DATA_REG                      ,
+       RULL(0x06010401), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCXB_TRA0_TR0_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x06010402), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x06010403), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x06010404), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x06010405), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x06010406), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x06010407), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x06010408), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x06010409), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA0_TR1_TRACE_HI_DATA_REG                      ,
+       RULL(0x06010440), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCXB_TRA0_TR1_TRACE_LO_DATA_REG                      ,
+       RULL(0x06010441), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCXB_TRA0_TR1_TRACE_TRCTRL_CONFIG                    ,
+       RULL(0x06010442), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_0                  ,
+       RULL(0x06010443), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_1                  ,
+       RULL(0x06010444), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_2                  ,
+       RULL(0x06010445), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_3                  ,
+       RULL(0x06010446), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_4                  ,
+       RULL(0x06010447), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_5                  ,
+       RULL(0x06010448), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9                  ,
+       RULL(0x06010449), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA1_TRACE_HI_DATA_REG                          ,
+       RULL(0x06010480), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCXB_TRA1_TRACE_LO_DATA_REG                          ,
+       RULL(0x06010481), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCXB_TRA1_TRACE_TRCTRL_CONFIG                        ,
+       RULL(0x06010482), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_0                      ,
+       RULL(0x06010483), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_1                      ,
+       RULL(0x06010484), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_2                      ,
+       RULL(0x06010485), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_3                      ,
+       RULL(0x06010486), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_4                      ,
+       RULL(0x06010487), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_5                      ,
+       RULL(0x06010488), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9                      ,
+       RULL(0x06010489), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_TEST_CERR                                       ,
+       RULL(0x050110AA), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_TEST_CERR                                       ,
+       RULL(0x050111AA), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_TEST_CERR                                       ,
+       RULL(0x050112AA), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_TOD_CMD_REG                                          ,
+       RULL(0x0502282A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TOD_DATA_RCV_REG                                     ,
+       RULL(0x05022829), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TOD_DATA_SND_REG                                     ,
+       RULL(0x05022828), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_TPCHIP_TRA0_TR0_TRACE_HI_DATA_REG                    ,
+       RULL(0x01010400), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG                    ,
+       RULL(0x01010401), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG                  ,
+       RULL(0x01010402), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_0                ,
+       RULL(0x01010403), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_1                ,
+       RULL(0x01010404), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_2                ,
+       RULL(0x01010405), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_3                ,
+       RULL(0x01010406), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_4                ,
+       RULL(0x01010407), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_5                ,
+       RULL(0x01010408), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9                ,
+       RULL(0x01010409), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TPCHIP_TRA0_TR1_TRACE_HI_DATA_REG                    ,
+       RULL(0x01010440), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG                    ,
+       RULL(0x01010441), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG                  ,
+       RULL(0x01010442), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_0                ,
+       RULL(0x01010443), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_1                ,
+       RULL(0x01010444), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_2                ,
+       RULL(0x01010445), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_3                ,
+       RULL(0x01010446), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_4                ,
+       RULL(0x01010447), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_5                ,
+       RULL(0x01010448), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9                ,
+       RULL(0x01010449), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TRUST_CONTROL                                        ,
+       RULL(0x05015F45), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PEC_TUNNEL_BAR_REG                                      ,
+       RULL(0x04010C05), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_TUNNEL_BAR_REG                                    ,
+       RULL(0x04010C05), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_TUNNEL_BAR_REG                                    ,
+       RULL(0x04011005), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_TUNNEL_BAR_REG                                    ,
+       RULL(0x04011405), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( PU_TX_CH_FSM_REG                                        ,
+       RULL(0x05012805), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_CH_INTADDR_REG                                    ,
+       RULL(0x05012810), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_CH_MISC_REG                                       ,
+       RULL(0x05012813), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_CTRL_STAT_REG                                     ,
+       RULL(0x05012800), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_DBFF_REG0                                         ,
+       RULL(0x05012811), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_DBFF_REG1                                         ,
+       RULL(0x05012812), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_DF_FSM_REG                                        ,
+       RULL(0x05012806), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_ERROR_REG_WCLEAR                                  ,
+       RULL(0x05012802), SH_UNT          , SH_ACS_SCOM_WCLEAR );
+REG64( PU_TX_ERROR_REG_OR                                      ,
+       RULL(0x05012804), SH_UNT          , SH_ACS_SCOM1_OR  );
+
+REG64( PU_TX_ERR_MODE                                          ,
+       RULL(0x05012807), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_MASK_REG                                          ,
+       RULL(0x05012803), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_PSI_CNTL                                          ,
+       RULL(0x04011830), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_PSI_MODE                                          ,
+       RULL(0x04011831), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_PSI_STATUS                                        ,
+       RULL(0x04011832), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_TO_RT_REG                                         ,
+       RULL(0x05012801), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_UMAC_STATUS_CONTROL                                  ,
+       RULL(0x020110D5), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_VAS_BUFCTL                                           ,
+       RULL(0x0301180C), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_VAS_CQERRRPT                                         ,
+       RULL(0x03011848), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_VAS_DBGCONT                                          ,
+       RULL(0x0301182E), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_VAS_DBGNORTH                                         ,
+       RULL(0x0301182D), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_DBGSOUTH                                         ,
+       RULL(0x0301184C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_DBGTRIG                                          ,
+       RULL(0x0301182F), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_VAS_EGERRRPT                                         ,
+       RULL(0x0301184A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_VAS_ERRINJ                                           ,
+       RULL(0x0301184B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_FIR_ACTION0_REG                                  ,
+       RULL(0x03011806), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_FIR_ACTION1_REG                                  ,
+       RULL(0x03011807), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_FIR_MASK_REG                                     ,
+       RULL(0x03011803), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_VAS_FIR_MASK_REG_AND                                 ,
+       RULL(0x03011804), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_VAS_FIR_MASK_REG_OR                                  ,
+       RULL(0x03011805), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_VAS_FIR_REG                                          ,
+       RULL(0x03011800), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_VAS_FIR_REG_AND                                      ,
+       RULL(0x03011801), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_VAS_FIR_REG_OR                                       ,
+       RULL(0x03011802), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_VAS_FIR_WOF_REG                                      ,
+       RULL(0x03011808), SH_UNT          , SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_VAS_INERRRPT                                         ,
+       RULL(0x0301182B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_VAS_MISCCTL                                          ,
+       RULL(0x0301180D), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_VAS_MMIOCTL                                          ,
+       RULL(0x03011829), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_VAS_MMIODATA                                         ,
+       RULL(0x0301182A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_MMIOECC                                          ,
+       RULL(0x03011831), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_VAS_MMIO_BASE_ADDR                                   ,
+       RULL(0x020110D4), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_VAS_PBCFG0                                           ,
+       RULL(0x0301184D), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_PBCFG1                                           ,
+       RULL(0x0301184E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_PGMIG1                                           ,
+       RULL(0x03011841), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_PGMIG2                                           ,
+       RULL(0x03011842), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_PGMIG3                                           ,
+       RULL(0x03011843), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_PGMIG4                                           ,
+       RULL(0x03011844), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_PGMIG5                                           ,
+       RULL(0x03011845), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_PGMIG6                                           ,
+       RULL(0x03011846), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_PGMIG7                                           ,
+       RULL(0x03011847), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_PMCNTL                                           ,
+       RULL(0x03011830), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_RGERRRPT                                         ,
+       RULL(0x0301182C), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_VAS_RMABAR                                           ,
+       RULL(0x0301180E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_RMABARM                                          ,
+       RULL(0x0301180F), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_SOUTHCTL                                         ,
+       RULL(0x0301184F), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_VAS_UWMBAR                                           ,
+       RULL(0x0301180B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WCBSBAR                                          ,
+       RULL(0x03011840), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WCERRRPT                                         ,
+       RULL(0x03011849), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_VAS_WCMBAR                                           ,
+       RULL(0x0301180A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WCPOIS                                           ,
+       RULL(0x03011828), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON0BAR                                        ,
+       RULL(0x03011810), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON0CMP                                        ,
+       RULL(0x03011820), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON0WID                                        ,
+       RULL(0x03011818), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON1BAR                                        ,
+       RULL(0x03011811), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON1CMP                                        ,
+       RULL(0x03011821), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON1WID                                        ,
+       RULL(0x03011819), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON2BAR                                        ,
+       RULL(0x03011812), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON2CMP                                        ,
+       RULL(0x03011822), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON2WID                                        ,
+       RULL(0x0301181A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON3BAR                                        ,
+       RULL(0x03011813), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON3CMP                                        ,
+       RULL(0x03011823), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON3WID                                        ,
+       RULL(0x0301181B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON4BAR                                        ,
+       RULL(0x03011814), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON4CMP                                        ,
+       RULL(0x03011824), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON4WID                                        ,
+       RULL(0x0301181C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON5BAR                                        ,
+       RULL(0x03011815), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON5CMP                                        ,
+       RULL(0x03011825), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON5WID                                        ,
+       RULL(0x0301181D), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON6BAR                                        ,
+       RULL(0x03011816), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON6CMP                                        ,
+       RULL(0x03011826), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON6WID                                        ,
+       RULL(0x0301181E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON7BAR                                        ,
+       RULL(0x03011817), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON7CMP                                        ,
+       RULL(0x03011827), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON7WID                                        ,
+       RULL(0x0301181F), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_WATCHDOG_HANG_TIMERS_CNTL                            ,
+       RULL(0x0201105C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_WATER_MARK_REGISTER_B                                ,
+       RULL(0x000A0007), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_WATER_MARK_REGISTER_C                                ,
+       RULL(0x000A1007), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_WATER_MARK_REGISTER_D                                ,
+       RULL(0x000A2007), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_WATER_MARK_REGISTER_E                                ,
+       RULL(0x000A3007), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_XSCOM_BASE_REG                                       ,
+       RULL(0x05022810), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_XSCOM_DAT0_REG                                       ,
+       RULL(0x0502281E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_XSCOM_DAT1_REG                                       ,
+       RULL(0x0502281F), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_XSCOM_ERR_REG                                        ,
+       RULL(0x05022813), SH_UNT          , SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_XSCOM_LOG_REG                                        ,
+       RULL(0x05022812), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_XSCOM_MODE_REG                                       ,
+       RULL(0x05022811), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_XSCOM_RCVED_STAT_REG                                 ,
+       RULL(0x05022818), SH_UNT          , SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_NPU0_SM0_XTIMER_CONFIG                               ,
+       RULL(0x0501100A), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_XTIMER_CONFIG                               ,
+       RULL(0x0501102A), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_XTIMER_CONFIG                               ,
+       RULL(0x0501104A), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_XTIMER_CONFIG                               ,
+       RULL(0x0501106A), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_XTIMER_CONFIG                               ,
+       RULL(0x0501110A), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_XTIMER_CONFIG                               ,
+       RULL(0x0501112A), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_XTIMER_CONFIG                               ,
+       RULL(0x0501114A), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_XTIMER_CONFIG                               ,
+       RULL(0x0501116A), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_XTIMER_CONFIG                               ,
+       RULL(0x0501120A), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_XTIMER_CONFIG                               ,
+       RULL(0x0501122A), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_XTIMER_CONFIG                               ,
+       RULL(0x0501124A), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_XTIMER_CONFIG                               ,
+       RULL(0x0501126A), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM2_XTS_CONFIG                                   ,
+       RULL(0x05011344), SH_UNT_PU_NPU_SM2, SH_ACS_SCOM      );
+#endif
+
diff --git a/src/ppe/importtemp/common/include/misc_scom_addresses_fixes.H b/src/ppe/importtemp/common/include/misc_scom_addresses_fixes.H
new file mode 100644
index 0000000..23cceaf
--- /dev/null
+++ b/src/ppe/importtemp/common/include/misc_scom_addresses_fixes.H
@@ -0,0 +1,412 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/common/include/misc_scom_addresses_fixes.H $ */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file misc_scom_addresses_fixes.H
+/// @brief The *scom_addresses.H files are  generated form figtree, but
+///        the figree can be wrong.  This file is included at the end
+///        of scom_addresses.H and allows incorrect constants to be
+///        fixed manually.
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: Infrastructure
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#ifndef __MISC_SCOM_ADDRESSES_FIXES_H
+#define __MISC_SCOM_ADDRESSES_FIXES_H
+
+
+//Example,
+//Copy the whole line from the *scom_addresses.H file.  Then add
+//FIX in front of REG, and add another paramter that is the new
+//corrected value.
+//FIXREG64( PU_ALTD_ADDR_REG,
+//          RULL(0x05022800), SH_UNT, SH_ACS_SCOM,
+//          RULL(0x00090000)
+//        );
+
+// ADU registers
+FIXREG64( PU_ALTD_ADDR_REG,
+          RULL(0x05022800), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00090000)
+        );
+FIXREG64( PU_ALTD_CMD_REG,
+          RULL(0x05022801), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00090001)
+        );
+FIXREG64( PU_ALTD_OPTION_REG,
+          RULL(0x05022802), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00090002)
+        );
+FIXREG64( PU_ALTD_STATUS_REG,
+          RULL(0x05022803), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00090003)
+        );
+FIXREG64( PU_ALTD_DATA_REG,
+          RULL(0x05022804), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00090004)
+        );
+FIXREG64( PU_FORCE_ECC_REG,
+          RULL(0x0502280D), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x0009000D)
+        );
+FIXREG64( PU_XSCOM_BASE_REG,
+          RULL(0x05022810), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00090010)
+        );
+FIXREG64( PU_XSCOM_MODE_REG,
+          RULL(0x05022811), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00090011)
+        );
+FIXREG64( PU_XSCOM_LOG_REG,
+          RULL(0x05022812), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00090012)
+        );
+FIXREG64( PU_XSCOM_ERR_REG,
+          RULL(0x05022813), SH_UNT, SH_ACS_SCOM_WCLRREG,
+          RULL(0x00090013)
+        );
+FIXREG64( PU_XSCOM_RCVED_STAT_REG,
+          RULL(0x05022818), SH_UNT, SH_ACS_SCOM_WCLRREG,
+          RULL(0x00090018)
+        );
+FIXREG64( PU_ADS_XSCOM_CMD_REG,
+          RULL(0x0502281C), SH_UNT, SH_ACS_SCOM,
+          RULL(0x0009001C)
+        );
+FIXREG64( PU_XSCOM_DAT0_REG,
+          RULL(0x0502281E), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x0009001E)
+        );
+FIXREG64( PU_XSCOM_DAT1_REG,
+          RULL(0x0502281F), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x0009001F)
+        );
+FIXREG64( PU_SND_STAT_REG,
+          RULL(0x05022820), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00090020)
+        );
+FIXREG64( PU_SND_MODE_REG,
+          RULL(0x05022821), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00090021)
+        );
+FIXREG64( PU_RCV_ERRLOG0_REG,
+          RULL(0x05022822), SH_UNT, SH_ACS_SCOM_WAND,
+          RULL(0x00090022)
+        );
+FIXREG64( PU_RCV_ERRLOG1_REG,
+          RULL(0x05022823), SH_UNT, SH_ACS_SCOM_WAND,
+          RULL(0x00090023)
+        );
+FIXREG64( PU_TOD_DATA_SND_REG,
+          RULL(0x05022828), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00090028)
+        );
+FIXREG64( PU_TOD_DATA_RCV_REG,
+          RULL(0x05022829), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x00090029)
+        );
+FIXREG64( PU_TOD_CMD_REG,
+          RULL(0x0502282A), SH_UNT, SH_ACS_SCOM,
+          RULL(0x0009002A)
+        );
+FIXREG64( PU_IO_DATA_REG,
+          RULL(0x05022830), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x00090030)
+        );
+FIXREG64( PU_PIB_CMD_REG,
+          RULL(0x05022831), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00090031)
+        );
+FIXREG64( PU_PIB_DATA_REG,
+          RULL(0x05022832), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x00090032)
+        );
+FIXREG64( PU_PIB_RESET_REG,
+          RULL(0x05022833), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00090033)
+        );
+FIXREG64( PU_LPC_BASE_REG,
+          RULL(0x05022840), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00090040)
+        );
+FIXREG64( PU_LPC_CMD_REG,
+          RULL(0x05022841), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00090041)
+        );
+FIXREG64( PU_LPC_DATA_REG,
+          RULL(0x05022842), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x00090042)
+        );
+FIXREG64( PU_ADU_HANG_DIV_REG,
+          RULL(0x05022850), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00090050)
+        );
+
+// PBA registers
+FIXREG64( PU_PBAMODE_OCI,
+          RULL(0x40020000), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020000)
+        );
+FIXREG64( PU_PBAMODE_SCOM,
+          RULL(0x05016840), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00068000)
+        );
+FIXREG64( PU_PBASLVRST_OCI,
+          RULL(0x40020008), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020008)
+        );
+FIXREG64( PU_PBASLVRST_SCOM,
+          RULL(0x05016841), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00068001)
+        );
+FIXREG64( PU_PBASLVCTL0_OCI,
+          RULL(0x40020020), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020020)
+        );
+FIXREG64( PU_PBASLVCTL0_SCOM,
+          RULL(0x05016844), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068004)
+        );
+FIXREG64( PU_PBASLVCTL1_OCI,
+          RULL(0x40020028), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020028)
+        );
+FIXREG64( PU_PBASLVCTL1_SCOM,
+          RULL(0x05016845), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068005)
+        );
+FIXREG64( PU_PBASLVCTL2_OCI,
+          RULL(0x40020030), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020030)
+        );
+FIXREG64( PU_PBASLVCTL2_SCOM,
+          RULL(0x05016846), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068006)
+        );
+FIXREG64( PU_PBASLVCTL3_OCI,
+          RULL(0x40020038), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020038)
+        );
+FIXREG64( PU_PBASLVCTL3_SCOM,
+          RULL(0x05016847), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068007)
+        );
+FIXREG64( PU_BCDE_CTL_OCI,
+          RULL(0x40020080), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020080)
+        );
+FIXREG64( PU_BCDE_CTL_SCOM,
+          RULL(0x05016850), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00068010)
+        );
+FIXREG64( PU_BCDE_SET_OCI,
+          RULL(0x40020088), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020088)
+        );
+FIXREG64( PU_BCDE_SET_SCOM,
+          RULL(0x05016851), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068011)
+        );
+FIXREG64( PU_BCDE_STAT_OCI,
+          RULL(0x40020090), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020090)
+        );
+FIXREG64( PU_BCDE_STAT_SCOM,
+          RULL(0x05016852), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x00068012)
+        );
+FIXREG64( PU_BCDE_PBADR_OCI,
+          RULL(0x40020098), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020098)
+        );
+FIXREG64( PU_BCDE_PBADR_SCOM,
+          RULL(0x05016853), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068013)
+        );
+FIXREG64( PU_BCDE_OCIBAR_OCI,
+          RULL(0x400200A0), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200A0)
+        );
+FIXREG64( PU_BCDE_OCIBAR_SCOM,
+          RULL(0x05016854), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068014)
+        );
+FIXREG64( PU_BCUE_CTL_OCI,
+          RULL(0x400200A8), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200A8)
+        );
+FIXREG64( PU_BCUE_CTL_SCOM,
+          RULL(0x05016855), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00068015)
+        );
+FIXREG64( PU_BCUE_SET_OCI,
+          RULL(0x400200B0), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200B0)
+        );
+FIXREG64( PU_BCUE_SET_SCOM,
+          RULL(0x05016856), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068016)
+        );
+FIXREG64( PU_BCUE_STAT_OCI,
+          RULL(0x400200B8), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200B8)
+        );
+FIXREG64( PU_BCUE_STAT_SCOM,
+          RULL(0x05016857), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x00068017)
+        );
+FIXREG64( PU_BCUE_PBADR_OCI,
+          RULL(0x400200C0), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200C0)
+        );
+FIXREG64( PU_BCUE_PBADR_SCOM,
+          RULL(0x05016858), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068018)
+        );
+FIXREG64( PU_BCUE_OCIBAR_OCI,
+          RULL(0x400200C8), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200C8)
+        );
+FIXREG64( PU_BCUE_OCIBAR_SCOM,
+          RULL(0x05016859), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068019)
+        );
+FIXREG64( PU_PBAPBOCR0_OCI,
+          RULL(0x400200D0), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200D0)
+        );
+FIXREG64( PU_PBAPBOCR0_SCOM,
+          RULL(0x0501685A), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x0006801A)
+        );
+FIXREG64( PU_PBAPBOCR1_OCI,
+          RULL(0x400200D8), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200D8)
+        );
+FIXREG64( PU_PBAPBOCR1_SCOM,
+          RULL(0x0501685B), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x0006801B)
+        );
+FIXREG64( PU_PBAPBOCR2_OCI,
+          RULL(0x400200E0), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200E0)
+        );
+FIXREG64( PU_PBAPBOCR2_SCOM,
+          RULL(0x0501685C), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x0006801C)
+        );
+FIXREG64( PU_PBAPBOCR3_OCI,
+          RULL(0x400200E8), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200E8)
+        );
+FIXREG64( PU_PBAPBOCR3_SCOM,
+          RULL(0x0501685D), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x0006801D)
+        );
+FIXREG64( PU_PBAPBOCR4_OCI,
+          RULL(0x400200F0), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200F0)
+        );
+FIXREG64( PU_PBAPBOCR4_SCOM,
+          RULL(0x0501685E), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x0006801E)
+        );
+FIXREG64( PU_PBAPBOCR5_OCI,
+          RULL(0x400200F8), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200F8)
+        );
+FIXREG64( PU_PBAPBOCR5_SCOM,
+          RULL(0x0501685F), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x0006801F)
+        );
+FIXREG64( PU_PBAXSNDTX_OCI,
+          RULL(0x40020100), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020100)
+        );
+FIXREG64( PU_PBAXSNDTX_SCOM,
+          RULL(0x05016860), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068020)
+        );
+FIXREG64( PU_PBAXCFG_OCI,
+          RULL(0x40020108), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020108)
+        );
+FIXREG64( PU_PBAXCFG_SCOM,
+          RULL(0x05016861), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00068021)
+        );
+FIXREG64( PU_PBAXSNDSTAT_OCI,
+          RULL(0x40020110), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020110)
+        );
+FIXREG64( PU_PBAXSNDSTAT_SCOM,
+          RULL(0x05016862), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x00068022)
+        );
+FIXREG64( PU_PBAXRCVSTAT_OCI,
+          RULL(0x40020120), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020120)
+        );
+FIXREG64( PU_PBAXRCVSTAT_SCOM,
+          RULL(0x05016864), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x00068024)
+        );
+FIXREG64( PU_PBAXSHBR0_OCI,
+          RULL(0x40020130), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020130)
+        );
+FIXREG64( PU_PBAXSHBR0_SCOM,
+          RULL(0x05016866), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068026)
+        );
+FIXREG64( PU_PBAXSHCS0_OCI,
+          RULL(0x40020138), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020138)
+        );
+FIXREG64( PU_PBAXSHCS0_SCOM,
+          RULL(0x05016867), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00068027)
+        );
+FIXREG64( PU_PBAXSHBR1_OCI,
+          RULL(0x40020150), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020150)
+        );
+FIXREG64( PU_PBAXSHBR1_SCOM,
+          RULL(0x0501686A), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x0006802A)
+        );
+FIXREG64( PU_PBAXSHCS1_OCI,
+          RULL(0x40020158), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020158)
+        );
+FIXREG64( PU_PBAXSHCS1_SCOM,
+          RULL(0x0501686B), SH_UNT, SH_ACS_SCOM,
+          RULL(0x0006802B)
+        );
+
+
+#endif
diff --git a/src/ppe/importtemp/common/include/misc_scom_addresses_fld.H b/src/ppe/importtemp/common/include/misc_scom_addresses_fld.H
new file mode 100644
index 0000000..b933de9
--- /dev/null
+++ b/src/ppe/importtemp/common/include/misc_scom_addresses_fld.H
@@ -0,0 +1,45258 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/common/include/misc_scom_addresses_fld.H $ */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file misc_scom_addresses_fld.H
+/// @brief  Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+#ifndef __MISC_SCOM_ADDRESSES_FLD_H
+#define __MISC_SCOM_ADDRESSES_FLD_H
+
+
+#include <scom_template_consts.H>
+#include <misc_scom_addresses_fld_fixes.H>
+
+REG64_FLD( PU_ADDR_0_HASH_FUNCTION_REG_ADDRESS                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_ADDR_0_HASH_FUNCTION_REG_ADDRESS_LEN                 , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_ADDR_10_HASH_FUNCTION_REG_ADDRESS                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_ADDR_10_HASH_FUNCTION_REG_ADDRESS_LEN                , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_ADDR_1_HASH_FUNCTION_REG_ADDRESS                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_ADDR_1_HASH_FUNCTION_REG_ADDRESS_LEN                 , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_ADDR_2_HASH_FUNCTION_REG_ADDRESS                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_ADDR_2_HASH_FUNCTION_REG_ADDRESS_LEN                 , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_ADDR_3_HASH_FUNCTION_REG_ADDRESS                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_ADDR_3_HASH_FUNCTION_REG_ADDRESS_LEN                 , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_ADDR_4_HASH_FUNCTION_REG_ADDRESS                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_ADDR_4_HASH_FUNCTION_REG_ADDRESS_LEN                 , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_ADDR_5_HASH_FUNCTION_REG_ADDRESS                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_ADDR_5_HASH_FUNCTION_REG_ADDRESS_LEN                 , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_ADDR_6_HASH_FUNCTION_REG_ADDRESS                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_ADDR_6_HASH_FUNCTION_REG_ADDRESS_LEN                 , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_ADDR_7_HASH_FUNCTION_REG_ADDRESS                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_ADDR_7_HASH_FUNCTION_REG_ADDRESS_LEN                 , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_ADDR_8_HASH_FUNCTION_REG_ADDRESS                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_ADDR_8_HASH_FUNCTION_REG_ADDRESS_LEN                 , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_ADDR_9_HASH_FUNCTION_REG_ADDRESS                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_ADDR_9_HASH_FUNCTION_REG_ADDRESS_LEN                 , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_ADS_XSCOM_CMD_REG_RNW                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RNW        );
+REG64_FLD( PU_ADS_XSCOM_CMD_REG_SIZE                               , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SIZE       );
+REG64_FLD( PU_ADS_XSCOM_CMD_REG_SIZE_LEN                           , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SIZE_LEN   );
+REG64_FLD( PU_ADS_XSCOM_CMD_REG_ADR                                , 30  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADR        );
+REG64_FLD( PU_ADS_XSCOM_CMD_REG_ADR_LEN                            , 34  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADR_LEN    );
+
+REG64_FLD( PU_ADU_HANG_DIV_REG_DATA                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DATA       );
+REG64_FLD( PU_ADU_HANG_DIV_REG_DATA_LEN                            , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_ADU_HANG_DIV_REG_OPER                                , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_OPER       );
+REG64_FLD( PU_ADU_HANG_DIV_REG_OPER_LEN                            , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_OPER_LEN   );
+
+REG64_FLD( PU_ALTD_ADDR_REG_FBC_ADDRESS                            , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_ADDRESS );
+REG64_FLD( PU_ALTD_ADDR_REG_FBC_ADDRESS_LEN                        , 56  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_ADDRESS_LEN );
+
+REG64_FLD( PU_ALTD_CMD_REG_FBC_START_OP                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_START_OP );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_CLEAR_STATUS                        , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_CLEAR_STATUS );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_RESET_FSM                           , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_RESET_FSM );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_RNW                                 , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_RNW    );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_AXTYPE                              , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_AXTYPE );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_DATA_ONLY                           , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_DATA_ONLY );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_LOCKED                              , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_LOCKED );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_LOCK_ID                             , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_LOCK_ID );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_LOCK_ID_LEN                         , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_LOCK_ID_LEN );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_SCOPE                               , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_SCOPE  );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_SCOPE_LEN                           , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_SCOPE_LEN );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_AUTO_INC                            , 19  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_AUTO_INC );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_DROP_PRIORITY                       , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_DROP_PRIORITY );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_DROP_PRIORITY_MAX                   , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_DROP_PRIORITY_MAX );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_OVERWRITE_PBINIT                    , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_OVERWRITE_PBINIT );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_PIB_DIRECT                          , 23  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_PIB_DIRECT );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_WITH_TM_QUIESCE                     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_WITH_TM_QUIESCE );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_TTYPE                               , 25  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_TTYPE  );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_TTYPE_LEN                           , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_TTYPE_LEN );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_TSIZE                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_TSIZE  );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_TSIZE_LEN                           , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_TSIZE_LEN );
+
+REG64_FLD( PU_ALTD_DATA_REG_FBC                                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FBC        );
+REG64_FLD( PU_ALTD_DATA_REG_FBC_LEN                                , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FBC_LEN    );
+
+REG64_FLD( PU_ALTD_OPTION_REG_FBC_WITH_PRE_QUIESCE                 , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_WITH_PRE_QUIESCE );
+REG64_FLD( PU_ALTD_OPTION_REG_FBC_WITH_PBINIT_LOW_WAIT             , 23  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_WITH_PBINIT_LOW_WAIT );
+REG64_FLD( PU_ALTD_OPTION_REG_FBC_AFTER_QUIESCE_WAIT_COUNT         , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_AFTER_QUIESCE_WAIT_COUNT );
+REG64_FLD( PU_ALTD_OPTION_REG_FBC_AFTER_QUIESCE_WAIT_COUNT_LEN     , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_AFTER_QUIESCE_WAIT_COUNT_LEN );
+REG64_FLD( PU_ALTD_OPTION_REG_FBC_WITH_POST_INIT                   , 51  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_WITH_POST_INIT );
+REG64_FLD( PU_ALTD_OPTION_REG_FBC_BEFORE_INIT_WAIT_COUNT           , 54  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_BEFORE_INIT_WAIT_COUNT );
+REG64_FLD( PU_ALTD_OPTION_REG_FBC_BEFORE_INIT_WAIT_COUNT_LEN       , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_BEFORE_INIT_WAIT_COUNT_LEN );
+
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_WAIT_CMD_ARBIT                   , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_WAIT_CMD_ARBIT );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_ADDR_DONE                        , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_ADDR_DONE );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_DATA_DONE                        , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_DATA_DONE );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_WAIT_RESP                        , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_WAIT_RESP );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_OVERRUN_ERROR                    , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_OVERRUN_ERROR );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_AUTOINC_ERROR                    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_AUTOINC_ERROR );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_COMMAND_ERROR                    , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_COMMAND_ERROR );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_ADDRESS_ERROR                    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_ADDRESS_ERROR );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_PB_OP_HANG_ERR                   , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_PB_OP_HANG_ERR );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_PB_DATA_HANG_ERR                 , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_PB_DATA_HANG_ERR );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_PB_UNEXPECT_CRESP_ERR            , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_PB_UNEXPECT_CRESP_ERR );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_PB_UNEXPECT_DATA_ERR             , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_PB_UNEXPECT_DATA_ERR );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_WAIT_PIB_DIRECT                  , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_WAIT_PIB_DIRECT );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_PIB_DIRECT_DONE                  , 17  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_PIB_DIRECT_DONE );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_PBINIT_MISSING                   , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_PBINIT_MISSING );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_PIB_ERROR                        , 33  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_PIB_ERROR );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_PIB_ERROR_LEN                    , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_PIB_ERROR_LEN );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_ECC_CE                           , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_ECC_CE );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_ECC_UE                           , 49  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_ECC_UE );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_ECC_SUE                          , 50  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_ECC_SUE );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_CRESP_VALUE                      , 59  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_CRESP_VALUE );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_CRESP_VALUE_LEN                  , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_CRESP_VALUE_LEN );
+
+REG64_FLD( PU_NPU_SM0_ATS_CKSW_SPARE                               , 0   ,
+           SH_UNT_PU_NPU_SM0, SH_ACS_SCOM     , SH_FLD_SPARE      );
+REG64_FLD( PU_NPU_SM0_ATS_CKSW_SPARE_LEN                           , 64  ,
+           SH_UNT_PU_NPU_SM0, SH_ACS_SCOM     , SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_NPU_SM1_ATS_CTRL_ARB_STOP                            , 0   ,
+           SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     , SH_FLD_ARB_STOP   );
+REG64_FLD( PU_NPU_SM1_ATS_CTRL_ARB_STALL                           , 1   ,
+           SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     , SH_FLD_ARB_STALL  );
+REG64_FLD( PU_NPU_SM1_ATS_CTRL_TCE_CACHE_DISABLE                   , 2   ,
+           SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     , SH_FLD_TCE_CACHE_DISABLE );
+REG64_FLD( PU_NPU_SM1_ATS_CTRL_TCE_CACHE_1W                        , 3   ,
+           SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     , SH_FLD_TCE_CACHE_1W );
+REG64_FLD( PU_NPU_SM1_ATS_CTRL_CONFIG_BRAZOS                       , 4   ,
+           SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_BRAZOS );
+REG64_FLD( PU_NPU_SM1_ATS_CTRL_SPARE                               , 5   ,
+           SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     , SH_FLD_SPARE      );
+REG64_FLD( PU_NPU_SM1_ATS_CTRL_SPARE_LEN                           , 59  ,
+           SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     , SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_BANK0_MCD_BOT_VALID                                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VALID      );
+REG64_FLD( PU_BANK0_MCD_BOT_CPG                                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CPG        );
+REG64_FLD( PU_BANK0_MCD_BOT_GRP_MBR_ID                             , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GRP_MBR_ID );
+REG64_FLD( PU_BANK0_MCD_BOT_ALWAYS_RTY                             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ALWAYS_RTY );
+REG64_FLD( PU_BANK0_MCD_BOT_GRP_SIZE                               , 13  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GRP_SIZE   );
+REG64_FLD( PU_BANK0_MCD_BOT_GRP_SIZE_LEN                           , 17  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GRP_SIZE_LEN );
+REG64_FLD( PU_BANK0_MCD_BOT_GRP_BASE                               , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GRP_BASE   );
+REG64_FLD( PU_BANK0_MCD_BOT_GRP_BASE_LEN                           , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GRP_BASE_LEN );
+
+REG64_FLD( PU_MCD1_BANK0_MCD_BOT_VALID                             , 0   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_VALID      );
+REG64_FLD( PU_MCD1_BANK0_MCD_BOT_CPG                               , 1   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_CPG        );
+REG64_FLD( PU_MCD1_BANK0_MCD_BOT_GRP_MBR_ID                        , 2   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_GRP_MBR_ID );
+REG64_FLD( PU_MCD1_BANK0_MCD_BOT_ALWAYS_RTY                        , 3   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_ALWAYS_RTY );
+REG64_FLD( PU_MCD1_BANK0_MCD_BOT_GRP_SIZE                          , 13  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_GRP_SIZE   );
+REG64_FLD( PU_MCD1_BANK0_MCD_BOT_GRP_SIZE_LEN                      , 17  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_GRP_SIZE_LEN );
+REG64_FLD( PU_MCD1_BANK0_MCD_BOT_GRP_BASE                          , 33  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_GRP_BASE   );
+REG64_FLD( PU_MCD1_BANK0_MCD_BOT_GRP_BASE_LEN                      , 31  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_GRP_BASE_LEN );
+
+REG64_FLD( PU_BANK0_MCD_CHA_VALID                                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VALID      );
+REG64_FLD( PU_BANK0_MCD_CHA_CPG                                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CPG        );
+REG64_FLD( PU_BANK0_MCD_CHA_GRP_MBR_ID                             , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GRP_MBR_ID );
+REG64_FLD( PU_BANK0_MCD_CHA_ALWAYS_RTY                             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ALWAYS_RTY );
+REG64_FLD( PU_BANK0_MCD_CHA_GRP_SIZE                               , 13  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GRP_SIZE   );
+REG64_FLD( PU_BANK0_MCD_CHA_GRP_SIZE_LEN                           , 17  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GRP_SIZE_LEN );
+REG64_FLD( PU_BANK0_MCD_CHA_GRP_BASE                               , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GRP_BASE   );
+REG64_FLD( PU_BANK0_MCD_CHA_GRP_BASE_LEN                           , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GRP_BASE_LEN );
+
+REG64_FLD( PU_MCD1_BANK0_MCD_CHA_VALID                             , 0   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_VALID      );
+REG64_FLD( PU_MCD1_BANK0_MCD_CHA_CPG                               , 1   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_CPG        );
+REG64_FLD( PU_MCD1_BANK0_MCD_CHA_GRP_MBR_ID                        , 2   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_GRP_MBR_ID );
+REG64_FLD( PU_MCD1_BANK0_MCD_CHA_ALWAYS_RTY                        , 3   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_ALWAYS_RTY );
+REG64_FLD( PU_MCD1_BANK0_MCD_CHA_GRP_SIZE                          , 13  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_GRP_SIZE   );
+REG64_FLD( PU_MCD1_BANK0_MCD_CHA_GRP_SIZE_LEN                      , 17  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_GRP_SIZE_LEN );
+REG64_FLD( PU_MCD1_BANK0_MCD_CHA_GRP_BASE                          , 33  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_GRP_BASE   );
+REG64_FLD( PU_MCD1_BANK0_MCD_CHA_GRP_BASE_LEN                      , 31  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_GRP_BASE_LEN );
+
+REG64_FLD( PU_BANK0_MCD_CMD_CHECK_CMDS                             , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHECK_CMDS );
+REG64_FLD( PU_BANK0_MCD_CMD_CHECK_CMDS_LEN                         , 19  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHECK_CMDS_LEN );
+REG64_FLD( PU_BANK0_MCD_CMD_CHECK_CMDS_EN                          , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHECK_CMDS_EN );
+REG64_FLD( PU_BANK0_MCD_CMD_SET_CMDS                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SET_CMDS   );
+REG64_FLD( PU_BANK0_MCD_CMD_SET_CMDS_LEN                           , 19  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SET_CMDS_LEN );
+REG64_FLD( PU_BANK0_MCD_CMD_SET_CMDS_EN                            , 63  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SET_CMDS_EN );
+
+REG64_FLD( PU_MCD1_BANK0_MCD_CMD_CHECK_CMDS                        , 0   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_CHECK_CMDS );
+REG64_FLD( PU_MCD1_BANK0_MCD_CMD_CHECK_CMDS_LEN                    , 19  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_CHECK_CMDS_LEN );
+REG64_FLD( PU_MCD1_BANK0_MCD_CMD_CHECK_CMDS_EN                     , 31  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_CHECK_CMDS_EN );
+REG64_FLD( PU_MCD1_BANK0_MCD_CMD_SET_CMDS                          , 32  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_SET_CMDS   );
+REG64_FLD( PU_MCD1_BANK0_MCD_CMD_SET_CMDS_LEN                      , 19  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_SET_CMDS_LEN );
+REG64_FLD( PU_MCD1_BANK0_MCD_CMD_SET_CMDS_EN                       , 63  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_SET_CMDS_EN );
+
+REG64_FLD( PU_BANK0_MCD_REC_ENABLE                                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_BANK0_MCD_REC_DONE                                   , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DONE       );
+REG64_FLD( PU_BANK0_MCD_REC_CONTINUOUS                             , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CONTINUOUS );
+REG64_FLD( PU_BANK0_MCD_REC_STATUS                                 , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STATUS     );
+REG64_FLD( PU_BANK0_MCD_REC_PACE                                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PACE       );
+REG64_FLD( PU_BANK0_MCD_REC_PACE_LEN                               , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PACE_LEN   );
+REG64_FLD( PU_BANK0_MCD_REC_ADDR_ERROR                             , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADDR_ERROR );
+REG64_FLD( PU_BANK0_MCD_REC_ADDR                                   , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADDR       );
+REG64_FLD( PU_BANK0_MCD_REC_ADDR_LEN                               , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_BANK0_MCD_REC_RTY_COUNT                              , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RTY_COUNT  );
+REG64_FLD( PU_BANK0_MCD_REC_RTY_COUNT_LEN                          , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RTY_COUNT_LEN );
+REG64_FLD( PU_BANK0_MCD_REC_VG_COUNT                               , 49  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_VG_COUNT   );
+REG64_FLD( PU_BANK0_MCD_REC_VG_COUNT_LEN                           , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_VG_COUNT_LEN );
+
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_ENABLE                            , 0   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_DONE                              , 1   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_DONE       );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_CONTINUOUS                        , 2   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_CONTINUOUS );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_STATUS                            , 5   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_STATUS     );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_PACE                              , 8   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_PACE       );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_PACE_LEN                          , 12  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_PACE_LEN   );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_ADDR_ERROR                        , 20  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_ADDR_ERROR );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_ADDR                              , 21  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_ADDR       );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_ADDR_LEN                          , 15  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_RTY_COUNT                         , 40  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_RTY_COUNT  );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_RTY_COUNT_LEN                     , 4   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_RTY_COUNT_LEN );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_VG_COUNT                          , 49  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_VG_COUNT   );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_VG_COUNT_LEN                      , 15  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_VG_COUNT_LEN );
+
+REG64_FLD( PU_BANK0_MCD_RW_RDWR_ACCESS_EN                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RDWR_ACCESS_EN );
+REG64_FLD( PU_BANK0_MCD_RW_RDWR_WR_ENABLE                          , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RDWR_WR_ENABLE );
+REG64_FLD( PU_BANK0_MCD_RW_RDWR_REQ_PEND                           , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RDWR_REQ_PEND );
+REG64_FLD( PU_BANK0_MCD_RW_RDWR_READ_STATUS                        , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RDWR_READ_STATUS );
+REG64_FLD( PU_BANK0_MCD_RW_RDWR_WRITE_MODE                         , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RDWR_WRITE_MODE );
+REG64_FLD( PU_BANK0_MCD_RW_RDWR_WRITE_STATUS                       , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RDWR_WRITE_STATUS );
+REG64_FLD( PU_BANK0_MCD_RW_RDWR_ADDR                               , 17  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RDWR_ADDR  );
+REG64_FLD( PU_BANK0_MCD_RW_RDWR_ADDR_LEN                           , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RDWR_ADDR_LEN );
+REG64_FLD( PU_BANK0_MCD_RW_RDWR_RDWR_DATA                          , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RDWR_RDWR_DATA );
+REG64_FLD( PU_BANK0_MCD_RW_RDWR_RDWR_DATA_LEN                      , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RDWR_RDWR_DATA_LEN );
+
+REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_ACCESS_EN                     , 0   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_RDWR_ACCESS_EN );
+REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_WR_ENABLE                     , 1   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_RDWR_WR_ENABLE );
+REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_REQ_PEND                      , 3   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_RDWR_REQ_PEND );
+REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_READ_STATUS                   , 4   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_RDWR_READ_STATUS );
+REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_WRITE_MODE                    , 5   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_RDWR_WRITE_MODE );
+REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_WRITE_STATUS                  , 6   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_RDWR_WRITE_STATUS );
+REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_ADDR                          , 17  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_RDWR_ADDR  );
+REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_ADDR_LEN                      , 15  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_RDWR_ADDR_LEN );
+REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_RDWR_DATA                     , 32  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_RDWR_RDWR_DATA );
+REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_RDWR_DATA_LEN                 , 32  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_RDWR_RDWR_DATA_LEN );
+
+REG64_FLD( PU_BANK0_MCD_STR_VALID                                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VALID      );
+REG64_FLD( PU_BANK0_MCD_STR_CPG                                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CPG        );
+REG64_FLD( PU_BANK0_MCD_STR_GRP_MBR_ID                             , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GRP_MBR_ID );
+REG64_FLD( PU_BANK0_MCD_STR_ALWAYS_RTY                             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ALWAYS_RTY );
+REG64_FLD( PU_BANK0_MCD_STR_GRP_SIZE                               , 13  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GRP_SIZE   );
+REG64_FLD( PU_BANK0_MCD_STR_GRP_SIZE_LEN                           , 17  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GRP_SIZE_LEN );
+REG64_FLD( PU_BANK0_MCD_STR_GRP_BASE                               , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GRP_BASE   );
+REG64_FLD( PU_BANK0_MCD_STR_GRP_BASE_LEN                           , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GRP_BASE_LEN );
+
+REG64_FLD( PU_MCD1_BANK0_MCD_STR_VALID                             , 0   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_VALID      );
+REG64_FLD( PU_MCD1_BANK0_MCD_STR_CPG                               , 1   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_CPG        );
+REG64_FLD( PU_MCD1_BANK0_MCD_STR_GRP_MBR_ID                        , 2   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_GRP_MBR_ID );
+REG64_FLD( PU_MCD1_BANK0_MCD_STR_ALWAYS_RTY                        , 3   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_ALWAYS_RTY );
+REG64_FLD( PU_MCD1_BANK0_MCD_STR_GRP_SIZE                          , 13  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_GRP_SIZE   );
+REG64_FLD( PU_MCD1_BANK0_MCD_STR_GRP_SIZE_LEN                      , 17  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_GRP_SIZE_LEN );
+REG64_FLD( PU_MCD1_BANK0_MCD_STR_GRP_BASE                          , 33  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_GRP_BASE   );
+REG64_FLD( PU_MCD1_BANK0_MCD_STR_GRP_BASE_LEN                      , 31  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_GRP_BASE_LEN );
+
+REG64_FLD( PU_BANK0_MCD_TOP_VALID                                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VALID      );
+REG64_FLD( PU_BANK0_MCD_TOP_CPG                                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CPG        );
+REG64_FLD( PU_BANK0_MCD_TOP_GRP_MBR_ID                             , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GRP_MBR_ID );
+REG64_FLD( PU_BANK0_MCD_TOP_ALWAYS_RTY                             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ALWAYS_RTY );
+REG64_FLD( PU_BANK0_MCD_TOP_GRP_SIZE                               , 13  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GRP_SIZE   );
+REG64_FLD( PU_BANK0_MCD_TOP_GRP_SIZE_LEN                           , 17  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GRP_SIZE_LEN );
+REG64_FLD( PU_BANK0_MCD_TOP_GRP_BASE                               , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GRP_BASE   );
+REG64_FLD( PU_BANK0_MCD_TOP_GRP_BASE_LEN                           , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GRP_BASE_LEN );
+
+REG64_FLD( PU_MCD1_BANK0_MCD_TOP_VALID                             , 0   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_VALID      );
+REG64_FLD( PU_MCD1_BANK0_MCD_TOP_CPG                               , 1   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_CPG        );
+REG64_FLD( PU_MCD1_BANK0_MCD_TOP_GRP_MBR_ID                        , 2   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_GRP_MBR_ID );
+REG64_FLD( PU_MCD1_BANK0_MCD_TOP_ALWAYS_RTY                        , 3   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_ALWAYS_RTY );
+REG64_FLD( PU_MCD1_BANK0_MCD_TOP_GRP_SIZE                          , 13  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_GRP_SIZE   );
+REG64_FLD( PU_MCD1_BANK0_MCD_TOP_GRP_SIZE_LEN                      , 17  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_GRP_SIZE_LEN );
+REG64_FLD( PU_MCD1_BANK0_MCD_TOP_GRP_BASE                          , 33  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_GRP_BASE   );
+REG64_FLD( PU_MCD1_BANK0_MCD_TOP_GRP_BASE_LEN                      , 31  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_GRP_BASE_LEN );
+
+REG64_FLD( PU_BANK0_MCD_VGC_AVAIL_GROUPS                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_AVAIL_GROUPS );
+REG64_FLD( PU_BANK0_MCD_VGC_AVAIL_GROUPS_LEN                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_AVAIL_GROUPS_LEN );
+REG64_FLD( PU_BANK0_MCD_VGC_4X4_MODE                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_4X4_MODE   );
+REG64_FLD( PU_BANK0_MCD_VGC_HANG_POLL_ENABLE                       , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HANG_POLL_ENABLE );
+REG64_FLD( PU_BANK0_MCD_VGC_RND_BACKOFF_ENABLE                     , 34  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RND_BACKOFF_ENABLE );
+REG64_FLD( PU_BANK0_MCD_VGC_DROP_PRIORITY_MODE                     , 35  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DROP_PRIORITY_MODE );
+REG64_FLD( PU_BANK0_MCD_VGC_MASK_AGV_DISABLE_MODE                  , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MASK_AGV_DISABLE_MODE );
+REG64_FLD( PU_BANK0_MCD_VGC_XLATE_TO_ADDR_ID_ENABLE                , 37  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_XLATE_TO_ADDR_ID_ENABLE );
+
+REG64_FLD( PU_MCD1_BANK0_MCD_VGC_AVAIL_GROUPS                      , 0   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_AVAIL_GROUPS );
+REG64_FLD( PU_MCD1_BANK0_MCD_VGC_AVAIL_GROUPS_LEN                  , 16  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_AVAIL_GROUPS_LEN );
+REG64_FLD( PU_MCD1_BANK0_MCD_VGC_4X4_MODE                          , 32  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_4X4_MODE   );
+REG64_FLD( PU_MCD1_BANK0_MCD_VGC_HANG_POLL_ENABLE                  , 33  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_HANG_POLL_ENABLE );
+REG64_FLD( PU_MCD1_BANK0_MCD_VGC_RND_BACKOFF_ENABLE                , 34  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_RND_BACKOFF_ENABLE );
+REG64_FLD( PU_MCD1_BANK0_MCD_VGC_DROP_PRIORITY_MODE                , 35  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_DROP_PRIORITY_MODE );
+REG64_FLD( PU_MCD1_BANK0_MCD_VGC_MASK_AGV_DISABLE_MODE             , 36  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_MASK_AGV_DISABLE_MODE );
+REG64_FLD( PU_MCD1_BANK0_MCD_VGC_XLATE_TO_ADDR_ID_ENABLE           , 37  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  , SH_FLD_XLATE_TO_ADDR_ID_ENABLE );
+
+REG64_FLD( PEC_STACK2_BARE_REG_PE_MMIO_BAR0_EN                     , 0   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  , SH_FLD_PE_MMIO_BAR0_EN );
+REG64_FLD( PEC_STACK2_BARE_REG_PE_MMIO_BAR1_EN                     , 1   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  , SH_FLD_PE_MMIO_BAR1_EN );
+REG64_FLD( PEC_STACK2_BARE_REG_PE_PHB_BAR_EN                       , 2   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  , SH_FLD_PE_PHB_BAR_EN );
+REG64_FLD( PEC_STACK2_BARE_REG_PE_MSI_BAR_EN                       , 3   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  , SH_FLD_PE_MSI_BAR_EN );
+REG64_FLD( PEC_STACK2_BARE_REG_PE_LSI_BAR_EN                       , 4   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  , SH_FLD_PE_LSI_BAR_EN );
+
+REG64_FLD( PEC_STACK1_BARE_REG_PE_MMIO_BAR0_EN                     , 0   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  , SH_FLD_PE_MMIO_BAR0_EN );
+REG64_FLD( PEC_STACK1_BARE_REG_PE_MMIO_BAR1_EN                     , 1   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  , SH_FLD_PE_MMIO_BAR1_EN );
+REG64_FLD( PEC_STACK1_BARE_REG_PE_PHB_BAR_EN                       , 2   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  , SH_FLD_PE_PHB_BAR_EN );
+REG64_FLD( PEC_STACK1_BARE_REG_PE_MSI_BAR_EN                       , 3   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  , SH_FLD_PE_MSI_BAR_EN );
+REG64_FLD( PEC_STACK1_BARE_REG_PE_LSI_BAR_EN                       , 4   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  , SH_FLD_PE_LSI_BAR_EN );
+
+REG64_FLD( PEC_STACK0_BARE_REG_PE_MMIO_BAR0_EN                     , 0   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  , SH_FLD_PE_MMIO_BAR0_EN );
+REG64_FLD( PEC_STACK0_BARE_REG_PE_MMIO_BAR1_EN                     , 1   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  , SH_FLD_PE_MMIO_BAR1_EN );
+REG64_FLD( PEC_STACK0_BARE_REG_PE_PHB_BAR_EN                       , 2   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  , SH_FLD_PE_PHB_BAR_EN );
+REG64_FLD( PEC_STACK0_BARE_REG_PE_MSI_BAR_EN                       , 3   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  , SH_FLD_PE_MSI_BAR_EN );
+REG64_FLD( PEC_STACK0_BARE_REG_PE_LSI_BAR_EN                       , 4   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  , SH_FLD_PE_LSI_BAR_EN );
+
+REG64_FLD( PU_BCDE_CTL_STOP                                        , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STOP       );
+REG64_FLD( PU_BCDE_CTL_START                                       , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_START      );
+
+REG64_FLD( PU_BCDE_OCIBAR_ADDR                                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDR       );
+REG64_FLD( PU_BCDE_OCIBAR_ADDR_LEN                                 , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDR_LEN   );
+
+REG64_FLD( PU_BCDE_PBADR_RESERVED_0_1                              , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_0_1 );
+REG64_FLD( PU_BCDE_PBADR_RESERVED_0_1_LEN                          , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_0_1_LEN );
+REG64_FLD( PU_BCDE_PBADR_PB_OFFSET                                 , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_OFFSET  );
+REG64_FLD( PU_BCDE_PBADR_PB_OFFSET_LEN                             , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_OFFSET_LEN );
+REG64_FLD( PU_BCDE_PBADR_RESERVED_25_26                            , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_25_26 );
+REG64_FLD( PU_BCDE_PBADR_RESERVED_25_26_LEN                        , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_25_26_LEN );
+REG64_FLD( PU_BCDE_PBADR_EXTADDR                                   , 27  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EXTADDR    );
+REG64_FLD( PU_BCDE_PBADR_EXTADDR_LEN                               , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EXTADDR_LEN );
+REG64_FLD( PU_BCDE_PBADR_RESERVED_41_42                            , 41  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_41_42 );
+REG64_FLD( PU_BCDE_PBADR_RESERVED_41_42_LEN                        , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_41_42_LEN );
+
+REG64_FLD( PU_BCDE_SET_RESERVED_0_1                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_0_1 );
+REG64_FLD( PU_BCDE_SET_RESERVED_0_1_LEN                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_0_1_LEN );
+REG64_FLD( PU_BCDE_SET_COPY_LENGTH                                 , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COPY_LENGTH );
+REG64_FLD( PU_BCDE_SET_COPY_LENGTH_LEN                             , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COPY_LENGTH_LEN );
+
+REG64_FLD( PU_BCDE_STAT_RUNNING                                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_BCDE_STAT_WAITING                                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WAITING    );
+REG64_FLD( PU_BCDE_STAT_WRCMP                                      , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRCMP      );
+REG64_FLD( PU_BCDE_STAT_WRCMP_LEN                                  , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRCMP_LEN  );
+REG64_FLD( PU_BCDE_STAT_RDCMP                                      , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RDCMP      );
+REG64_FLD( PU_BCDE_STAT_RDCMP_LEN                                  , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RDCMP_LEN  );
+REG64_FLD( PU_BCDE_STAT_DEBUG                                      , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DEBUG      );
+REG64_FLD( PU_BCDE_STAT_DEBUG_LEN                                  , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DEBUG_LEN  );
+REG64_FLD( PU_BCDE_STAT_STOPPED                                    , 29  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_STOPPED    );
+REG64_FLD( PU_BCDE_STAT_ERROR                                      , 30  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ERROR      );
+REG64_FLD( PU_BCDE_STAT_DONE                                       , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DONE       );
+
+REG64_FLD( PU_BCUE_CTL_STOP                                        , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STOP       );
+REG64_FLD( PU_BCUE_CTL_START                                       , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_START      );
+
+REG64_FLD( PU_BCUE_OCIBAR_ADDR                                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDR       );
+REG64_FLD( PU_BCUE_OCIBAR_ADDR_LEN                                 , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDR_LEN   );
+
+REG64_FLD( PU_BCUE_PBADR_RESERVED_0_1                              , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_0_1 );
+REG64_FLD( PU_BCUE_PBADR_RESERVED_0_1_LEN                          , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_0_1_LEN );
+REG64_FLD( PU_BCUE_PBADR_PB_OFFSET                                 , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_OFFSET  );
+REG64_FLD( PU_BCUE_PBADR_PB_OFFSET_LEN                             , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_OFFSET_LEN );
+REG64_FLD( PU_BCUE_PBADR_RESERVED_25_26                            , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_25_26 );
+REG64_FLD( PU_BCUE_PBADR_RESERVED_25_26_LEN                        , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_25_26_LEN );
+REG64_FLD( PU_BCUE_PBADR_EXTADDR                                   , 27  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EXTADDR    );
+REG64_FLD( PU_BCUE_PBADR_EXTADDR_LEN                               , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EXTADDR_LEN );
+REG64_FLD( PU_BCUE_PBADR_RESERVED_41_42                            , 41  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_41_42 );
+REG64_FLD( PU_BCUE_PBADR_RESERVED_41_42_LEN                        , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_41_42_LEN );
+
+REG64_FLD( PU_BCUE_SET_RESERVED_0_1                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_0_1 );
+REG64_FLD( PU_BCUE_SET_RESERVED_0_1_LEN                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_0_1_LEN );
+REG64_FLD( PU_BCUE_SET_COPY_LENGTH                                 , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COPY_LENGTH );
+REG64_FLD( PU_BCUE_SET_COPY_LENGTH_LEN                             , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COPY_LENGTH_LEN );
+
+REG64_FLD( PU_BCUE_STAT_RUNNING                                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_BCUE_STAT_WAITING                                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WAITING    );
+REG64_FLD( PU_BCUE_STAT_WRCMP                                      , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRCMP      );
+REG64_FLD( PU_BCUE_STAT_WRCMP_LEN                                  , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRCMP_LEN  );
+REG64_FLD( PU_BCUE_STAT_RDCMP                                      , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RDCMP      );
+REG64_FLD( PU_BCUE_STAT_RDCMP_LEN                                  , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RDCMP_LEN  );
+REG64_FLD( PU_BCUE_STAT_DEBUG                                      , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DEBUG      );
+REG64_FLD( PU_BCUE_STAT_DEBUG_LEN                                  , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DEBUG_LEN  );
+REG64_FLD( PU_BCUE_STAT_STOPPED                                    , 29  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_STOPPED    );
+REG64_FLD( PU_BCUE_STAT_ERROR                                      , 30  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ERROR      );
+REG64_FLD( PU_BCUE_STAT_DONE                                       , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DONE       );
+
+REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_RESERVED                   , 1   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_RESERVED_LEN               , 3   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_PE                         , 4   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_PE         );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_PE_LEN                     , 4   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_BDF                        , 8   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_BDF        );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_BDF_LEN                    , 16  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_RESERVED                   , 1   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_RESERVED_LEN               , 3   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_PE                         , 4   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_PE         );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_PE_LEN                     , 4   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_BDF                        , 8   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_BDF        );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_BDF_LEN                    , 16  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_RESERVED                   , 1   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_RESERVED_LEN               , 3   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_PE                         , 4   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_PE         );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_PE_LEN                     , 4   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_BDF                        , 8   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_BDF        );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_BDF_LEN                    , 16  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU1_CTL_BDF2PE_01_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_01_CONFIG_RESERVED                   , 1   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_01_CONFIG_RESERVED_LEN               , 3   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_01_CONFIG_PE                         , 4   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_PE         );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_01_CONFIG_PE_LEN                     , 4   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_01_CONFIG_BDF                        , 8   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_BDF        );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_01_CONFIG_BDF_LEN                    , 16  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU0_CTL_BDF2PE_01_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_01_CONFIG_RESERVED                   , 1   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_01_CONFIG_RESERVED_LEN               , 3   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_01_CONFIG_PE                         , 4   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_PE         );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_01_CONFIG_PE_LEN                     , 4   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_01_CONFIG_BDF                        , 8   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_BDF        );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_01_CONFIG_BDF_LEN                    , 16  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU2_CTL_BDF2PE_01_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_01_CONFIG_RESERVED                   , 1   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_01_CONFIG_RESERVED_LEN               , 3   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_01_CONFIG_PE                         , 4   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_PE         );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_01_CONFIG_PE_LEN                     , 4   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_01_CONFIG_BDF                        , 8   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_BDF        );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_01_CONFIG_BDF_LEN                    , 16  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU1_CTL_BDF2PE_02_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_02_CONFIG_RESERVED                   , 1   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_02_CONFIG_RESERVED_LEN               , 3   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_02_CONFIG_PE                         , 4   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_PE         );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_02_CONFIG_PE_LEN                     , 4   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_02_CONFIG_BDF                        , 8   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_BDF        );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_02_CONFIG_BDF_LEN                    , 16  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU0_CTL_BDF2PE_02_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_02_CONFIG_RESERVED                   , 1   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_02_CONFIG_RESERVED_LEN               , 3   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_02_CONFIG_PE                         , 4   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_PE         );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_02_CONFIG_PE_LEN                     , 4   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_02_CONFIG_BDF                        , 8   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_BDF        );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_02_CONFIG_BDF_LEN                    , 16  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU2_CTL_BDF2PE_02_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_02_CONFIG_RESERVED                   , 1   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_02_CONFIG_RESERVED_LEN               , 3   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_02_CONFIG_PE                         , 4   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_PE         );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_02_CONFIG_PE_LEN                     , 4   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_02_CONFIG_BDF                        , 8   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_BDF        );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_02_CONFIG_BDF_LEN                    , 16  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_RESERVED                   , 1   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_RESERVED_LEN               , 3   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_PE                         , 4   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_PE         );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_PE_LEN                     , 4   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_BDF                        , 8   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_BDF        );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_BDF_LEN                    , 16  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_RESERVED                   , 1   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_RESERVED_LEN               , 3   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_PE                         , 4   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_PE         );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_PE_LEN                     , 4   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_BDF                        , 8   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_BDF        );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_BDF_LEN                    , 16  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_RESERVED                   , 1   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_RESERVED_LEN               , 3   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_PE                         , 4   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_PE         );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_PE_LEN                     , 4   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_BDF                        , 8   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_BDF        );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_BDF_LEN                    , 16  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU1_CTL_BDF2PE_11_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_11_CONFIG_RESERVED                   , 1   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_11_CONFIG_RESERVED_LEN               , 3   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_11_CONFIG_PE                         , 4   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_PE         );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_11_CONFIG_PE_LEN                     , 4   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_11_CONFIG_BDF                        , 8   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_BDF        );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_11_CONFIG_BDF_LEN                    , 16  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU0_CTL_BDF2PE_11_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_11_CONFIG_RESERVED                   , 1   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_11_CONFIG_RESERVED_LEN               , 3   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_11_CONFIG_PE                         , 4   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_PE         );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_11_CONFIG_PE_LEN                     , 4   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_11_CONFIG_BDF                        , 8   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_BDF        );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_11_CONFIG_BDF_LEN                    , 16  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU2_CTL_BDF2PE_11_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_11_CONFIG_RESERVED                   , 1   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_11_CONFIG_RESERVED_LEN               , 3   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_11_CONFIG_PE                         , 4   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_PE         );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_11_CONFIG_PE_LEN                     , 4   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_11_CONFIG_BDF                        , 8   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_BDF        );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_11_CONFIG_BDF_LEN                    , 16  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU1_CTL_BDF2PE_12_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_12_CONFIG_RESERVED                   , 1   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_12_CONFIG_RESERVED_LEN               , 3   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_12_CONFIG_PE                         , 4   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_PE         );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_12_CONFIG_PE_LEN                     , 4   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_12_CONFIG_BDF                        , 8   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_BDF        );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_12_CONFIG_BDF_LEN                    , 16  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU0_CTL_BDF2PE_12_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_12_CONFIG_RESERVED                   , 1   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_12_CONFIG_RESERVED_LEN               , 3   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_12_CONFIG_PE                         , 4   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_PE         );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_12_CONFIG_PE_LEN                     , 4   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_12_CONFIG_BDF                        , 8   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_BDF        );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_12_CONFIG_BDF_LEN                    , 16  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU2_CTL_BDF2PE_12_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_12_CONFIG_RESERVED                   , 1   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_12_CONFIG_RESERVED_LEN               , 3   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_12_CONFIG_PE                         , 4   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_PE         );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_12_CONFIG_PE_LEN                     , 4   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_12_CONFIG_BDF                        , 8   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_BDF        );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_12_CONFIG_BDF_LEN                    , 16  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_CE_COUNT_OVER_THRESH        , 9   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_CE_COUNT_OVER_THRESH );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PT_UE                       , 10  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_PT_UE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PT_UE_LEN                   , 4   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_PT_UE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PR_UE                       , 14  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_PR_UE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PR_UE_LEN                   , 4   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_PR_UE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_BR_UE                       , 18  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_BR_UE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_BR_UE_LEN                   , 2   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_BR_UE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_IR_UE                       , 20  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_IR_UE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_IR_UE_LEN                   , 4   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_IR_UE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_OR_UE                       , 24  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_OR_UE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_OR_UE_LEN                   , 4   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_OR_UE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PT_SUE                      , 28  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_PT_SUE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PT_SUE_LEN                  , 4   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_PT_SUE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PR_SUE                      , 32  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_PR_SUE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PR_SUE_LEN                  , 4   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_PR_SUE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_BR_SUE                      , 36  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_BR_SUE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_BR_SUE_LEN                  , 2   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_BR_SUE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_IR_SUE                      , 38  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_IR_SUE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_IR_SUE_LEN                  , 4   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_IR_SUE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_OR_SUE                      , 42  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_OR_SUE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_OR_SUE_LEN                  , 4   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_OR_SUE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PT_CE                       , 46  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_PT_CE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PT_CE_LEN                   , 4   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_PT_CE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PR_CE                       , 50  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_PR_CE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PR_CE_LEN                   , 4   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_PR_CE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_BR_CE                       , 54  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_BR_CE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_BR_CE_LEN                   , 2   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_BR_CE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_IR_CE                       , 56  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_IR_CE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_IR_CE_LEN                   , 4   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_IR_CE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_OR_CE                       , 60  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_OR_CE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_OR_CE_LEN                   , 4   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_OR_CE_LEN );
+
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_CE_COUNT_OVER_THRESH        , 9   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_CE_COUNT_OVER_THRESH );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PT_UE                       , 10  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_PT_UE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PT_UE_LEN                   , 4   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_PT_UE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PR_UE                       , 14  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_PR_UE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PR_UE_LEN                   , 4   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_PR_UE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_BR_UE                       , 18  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_BR_UE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_BR_UE_LEN                   , 2   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_BR_UE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_IR_UE                       , 20  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_IR_UE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_IR_UE_LEN                   , 4   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_IR_UE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_OR_UE                       , 24  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_OR_UE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_OR_UE_LEN                   , 4   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_OR_UE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PT_SUE                      , 28  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_PT_SUE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PT_SUE_LEN                  , 4   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_PT_SUE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PR_SUE                      , 32  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_PR_SUE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PR_SUE_LEN                  , 4   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_PR_SUE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_BR_SUE                      , 36  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_BR_SUE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_BR_SUE_LEN                  , 2   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_BR_SUE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_IR_SUE                      , 38  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_IR_SUE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_IR_SUE_LEN                  , 4   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_IR_SUE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_OR_SUE                      , 42  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_OR_SUE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_OR_SUE_LEN                  , 4   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_OR_SUE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PT_CE                       , 46  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_PT_CE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PT_CE_LEN                   , 4   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_PT_CE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PR_CE                       , 50  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_PR_CE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PR_CE_LEN                   , 4   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_PR_CE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_BR_CE                       , 54  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_BR_CE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_BR_CE_LEN                   , 2   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_BR_CE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_IR_CE                       , 56  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_IR_CE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_IR_CE_LEN                   , 4   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_IR_CE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_OR_CE                       , 60  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_OR_CE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_OR_CE_LEN                   , 4   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_OR_CE_LEN );
+
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_CE_COUNT_OVER_THRESH        , 9   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_CE_COUNT_OVER_THRESH );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PT_UE                       , 10  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_PT_UE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PT_UE_LEN                   , 4   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_PT_UE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PR_UE                       , 14  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_PR_UE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PR_UE_LEN                   , 4   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_PR_UE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_BR_UE                       , 18  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_BR_UE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_BR_UE_LEN                   , 2   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_BR_UE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_IR_UE                       , 20  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_IR_UE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_IR_UE_LEN                   , 4   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_IR_UE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_OR_UE                       , 24  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_OR_UE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_OR_UE_LEN                   , 4   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_OR_UE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PT_SUE                      , 28  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_PT_SUE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PT_SUE_LEN                  , 4   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_PT_SUE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PR_SUE                      , 32  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_PR_SUE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PR_SUE_LEN                  , 4   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_PR_SUE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_BR_SUE                      , 36  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_BR_SUE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_BR_SUE_LEN                  , 2   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_BR_SUE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_IR_SUE                      , 38  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_IR_SUE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_IR_SUE_LEN                  , 4   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_IR_SUE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_OR_SUE                      , 42  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_OR_SUE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_OR_SUE_LEN                  , 4   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_OR_SUE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PT_CE                       , 46  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_PT_CE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PT_CE_LEN                   , 4   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_PT_CE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PR_CE                       , 50  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_PR_CE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PR_CE_LEN                   , 4   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_PR_CE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_BR_CE                       , 54  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_BR_CE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_BR_CE_LEN                   , 2   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_BR_CE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_IR_CE                       , 56  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_IR_CE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_IR_CE_LEN                   , 4   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_IR_CE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_OR_CE                       , 60  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_OR_CE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_OR_CE_LEN                   , 4   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_OR_CE_LEN );
+
+REG64_FLD( PU_NPU0_CERR_ECC_MASK_BITS                              , 9   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_BITS       );
+REG64_FLD( PU_NPU0_CERR_ECC_MASK_BITS_LEN                          , 55  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU1_CERR_ECC_MASK_BITS                              , 9   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_BITS       );
+REG64_FLD( PU_NPU1_CERR_ECC_MASK_BITS_LEN                          , 55  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU2_CERR_ECC_MASK_BITS                              , 9   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_BITS       );
+REG64_FLD( PU_NPU2_CERR_ECC_MASK_BITS_LEN                          , 55  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_AMO_ADDR                    , 60  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_AMO_ADDR );
+REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_PBRX_RTAG                   , 61  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_PBRX_RTAG );
+REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_IBUF_WRITE                  , 62  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_IBUF_WRITE );
+REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_RESERVED                    , 63  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_RESERVED );
+
+REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_AMO_ADDR                    , 60  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_AMO_ADDR );
+REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_PBRX_RTAG                   , 61  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_PBRX_RTAG );
+REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_IBUF_WRITE                  , 62  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_IBUF_WRITE );
+REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_RESERVED                    , 63  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_RESERVED );
+
+REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_AMO_ADDR                    , 60  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_AMO_ADDR );
+REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_PBRX_RTAG                   , 61  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_PBRX_RTAG );
+REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_IBUF_WRITE                  , 62  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_IBUF_WRITE );
+REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_RESERVED                    , 63  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_RESERVED );
+
+REG64_FLD( PU_NPU0_CERR_LOG_MASK_BITS                              , 60  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_BITS       );
+REG64_FLD( PU_NPU0_CERR_LOG_MASK_BITS_LEN                          , 4   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU1_CERR_LOG_MASK_BITS                              , 60  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_BITS       );
+REG64_FLD( PU_NPU1_CERR_LOG_MASK_BITS_LEN                          , 4   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU2_CERR_LOG_MASK_BITS                              , 60  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_BITS       );
+REG64_FLD( PU_NPU2_CERR_LOG_MASK_BITS_LEN                          , 4   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_MISC_STATE                  , 38  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_MISC_STATE );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_MRG_STATE                   , 39  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_MRG_STATE );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_OBUF_STATE                  , 40  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_OBUF_STATE );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_PBTX_STATE                  , 41  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_PBTX_STATE );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_RQIN_STATE                  , 42  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_RQIN_STATE );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_IBUF_STATE                  , 43  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_IBUF_STATE );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_ERRINJ                      , 44  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_ERRINJ );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_PBTX_AMO                    , 45  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_PBTX_AMO );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_PBTX_AMO_LEN                , 4   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_PBTX_AMO_LEN );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_IBRD                        , 49  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_IBRD );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_IBRD_LEN                    , 4   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_IBRD_LEN );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_OBRD                        , 53  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_OBRD );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_OBRD_LEN                    , 4   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_OBRD_LEN );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_BBRD                        , 57  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_BBRD );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_BBRD_LEN                    , 2   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_BBRD_LEN );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_PBRX_RTAG                   , 59  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_PBRX_RTAG );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_ECC_CONFIG                  , 60  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_ECC_CONFIG );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_CONFIG1                     , 61  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_CONFIG1 );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_DEBUG0_CONFIG               , 62  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_DEBUG0_CONFIG );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_DEBUG1_CONFIG               , 63  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_DEBUG1_CONFIG );
+
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_MISC_STATE                  , 38  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_MISC_STATE );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_MRG_STATE                   , 39  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_MRG_STATE );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_OBUF_STATE                  , 40  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_OBUF_STATE );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_PBTX_STATE                  , 41  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_PBTX_STATE );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_RQIN_STATE                  , 42  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_RQIN_STATE );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_IBUF_STATE                  , 43  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_IBUF_STATE );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_ERRINJ                      , 44  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_ERRINJ );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_PBTX_AMO                    , 45  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_PBTX_AMO );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_PBTX_AMO_LEN                , 4   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_PBTX_AMO_LEN );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_IBRD                        , 49  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_IBRD );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_IBRD_LEN                    , 4   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_IBRD_LEN );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_OBRD                        , 53  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_OBRD );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_OBRD_LEN                    , 4   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_OBRD_LEN );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_BBRD                        , 57  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_BBRD );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_BBRD_LEN                    , 2   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_BBRD_LEN );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_PBRX_RTAG                   , 59  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_PBRX_RTAG );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_ECC_CONFIG                  , 60  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_ECC_CONFIG );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_CONFIG1                     , 61  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_CONFIG1 );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_DEBUG0_CONFIG               , 62  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_DEBUG0_CONFIG );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_DEBUG1_CONFIG               , 63  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_DEBUG1_CONFIG );
+
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_MISC_STATE                  , 38  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_MISC_STATE );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_MRG_STATE                   , 39  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_MRG_STATE );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_OBUF_STATE                  , 40  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_OBUF_STATE );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_PBTX_STATE                  , 41  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_PBTX_STATE );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_RQIN_STATE                  , 42  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_RQIN_STATE );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_IBUF_STATE                  , 43  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_IBUF_STATE );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_ERRINJ                      , 44  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_ERRINJ );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_PBTX_AMO                    , 45  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_PBTX_AMO );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_PBTX_AMO_LEN                , 4   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_PBTX_AMO_LEN );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_IBRD                        , 49  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_IBRD );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_IBRD_LEN                    , 4   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_IBRD_LEN );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_OBRD                        , 53  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_OBRD );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_OBRD_LEN                    , 4   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_OBRD_LEN );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_BBRD                        , 57  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_BBRD );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_BBRD_LEN                    , 2   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_BBRD_LEN );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_PBRX_RTAG                   , 59  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_PBRX_RTAG );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_ECC_CONFIG                  , 60  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_ECC_CONFIG );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_CONFIG1                     , 61  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_CONFIG1 );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_DEBUG0_CONFIG               , 62  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_DEBUG0_CONFIG );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_DEBUG1_CONFIG               , 63  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_DEBUG1_CONFIG );
+
+REG64_FLD( PU_NPU0_CERR_PTY_MASK_BITS                              , 38  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_BITS       );
+REG64_FLD( PU_NPU0_CERR_PTY_MASK_BITS_LEN                          , 26  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU1_CERR_PTY_MASK_BITS                              , 38  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_BITS       );
+REG64_FLD( PU_NPU1_CERR_PTY_MASK_BITS_LEN                          , 26  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU2_CERR_PTY_MASK_BITS                              , 38  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_BITS       );
+REG64_FLD( PU_NPU2_CERR_PTY_MASK_BITS_LEN                          , 26  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_PIB2OPB1_CMD_WRDAT_WRITE_NOT_READ                    , 0   ,
+           SH_UNT_PU_PIB2OPB1, SH_ACS_SCOM     , SH_FLD_WRITE_NOT_READ );
+
+REG64_FLD( PU_PIB2OPB0_CMD_WRDAT_WRITE_NOT_READ                    , 0   ,
+           SH_UNT_PU_PIB2OPB0, SH_ACS_SCOM     , SH_FLD_WRITE_NOT_READ );
+
+REG64_FLD( PU_CME4_CME_LCL_DBG_EN                                  , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_EN         );
+REG64_FLD( PU_CME4_CME_LCL_DBG_HALT_ON_XSTOP                       , 1   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME4_CME_LCL_DBG_HALT_ON_TRIG                        , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME4_CME_LCL_DBG_EN_RISCTRACE                        , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_EN_RISCTRACE );
+REG64_FLD( PU_CME4_CME_LCL_DBG_EN_TRACE_FULL_IVA                   , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_EN_TRACE_FULL_IVA );
+REG64_FLD( PU_CME4_CME_LCL_DBG_DIS_TRACE_EXTRA                     , 5   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_EXTRA );
+REG64_FLD( PU_CME4_CME_LCL_DBG_DIS_TRACE_STALL                     , 6   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_STALL );
+REG64_FLD( PU_CME4_CME_LCL_DBG_EN_WIDE_TRACE                       , 7   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_EN_WIDE_TRACE );
+REG64_FLD( PU_CME4_CME_LCL_DBG_SYNC_TIMER_SEL                      , 8   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL );
+REG64_FLD( PU_CME4_CME_LCL_DBG_SYNC_TIMER_SEL_LEN                  , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL_LEN );
+REG64_FLD( PU_CME4_CME_LCL_DBG_FIR_TRIGGER                         , 12  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME4_CME_LCL_DBG_MIB_GPIO                            , 13  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME4_CME_LCL_DBG_MIB_GPIO_LEN                        , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME4_CME_LCL_DBG_HALT_INPUT                          , 16  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_HALT_INPUT );
+
+REG64_FLD( PU_CME3_CME_LCL_DBG_EN                                  , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_EN         );
+REG64_FLD( PU_CME3_CME_LCL_DBG_HALT_ON_XSTOP                       , 1   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME3_CME_LCL_DBG_HALT_ON_TRIG                        , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME3_CME_LCL_DBG_EN_RISCTRACE                        , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_EN_RISCTRACE );
+REG64_FLD( PU_CME3_CME_LCL_DBG_EN_TRACE_FULL_IVA                   , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_EN_TRACE_FULL_IVA );
+REG64_FLD( PU_CME3_CME_LCL_DBG_DIS_TRACE_EXTRA                     , 5   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_EXTRA );
+REG64_FLD( PU_CME3_CME_LCL_DBG_DIS_TRACE_STALL                     , 6   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_STALL );
+REG64_FLD( PU_CME3_CME_LCL_DBG_EN_WIDE_TRACE                       , 7   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_EN_WIDE_TRACE );
+REG64_FLD( PU_CME3_CME_LCL_DBG_SYNC_TIMER_SEL                      , 8   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL );
+REG64_FLD( PU_CME3_CME_LCL_DBG_SYNC_TIMER_SEL_LEN                  , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL_LEN );
+REG64_FLD( PU_CME3_CME_LCL_DBG_FIR_TRIGGER                         , 12  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME3_CME_LCL_DBG_MIB_GPIO                            , 13  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME3_CME_LCL_DBG_MIB_GPIO_LEN                        , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME3_CME_LCL_DBG_HALT_INPUT                          , 16  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_HALT_INPUT );
+
+REG64_FLD( PU_CME11_CME_LCL_DBG_EN                                 , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_EN         );
+REG64_FLD( PU_CME11_CME_LCL_DBG_HALT_ON_XSTOP                      , 1   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME11_CME_LCL_DBG_HALT_ON_TRIG                       , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME11_CME_LCL_DBG_EN_RISCTRACE                       , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_EN_RISCTRACE );
+REG64_FLD( PU_CME11_CME_LCL_DBG_EN_TRACE_FULL_IVA                  , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_EN_TRACE_FULL_IVA );
+REG64_FLD( PU_CME11_CME_LCL_DBG_DIS_TRACE_EXTRA                    , 5   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_EXTRA );
+REG64_FLD( PU_CME11_CME_LCL_DBG_DIS_TRACE_STALL                    , 6   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_STALL );
+REG64_FLD( PU_CME11_CME_LCL_DBG_EN_WIDE_TRACE                      , 7   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_EN_WIDE_TRACE );
+REG64_FLD( PU_CME11_CME_LCL_DBG_SYNC_TIMER_SEL                     , 8   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL );
+REG64_FLD( PU_CME11_CME_LCL_DBG_SYNC_TIMER_SEL_LEN                 , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL_LEN );
+REG64_FLD( PU_CME11_CME_LCL_DBG_FIR_TRIGGER                        , 12  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME11_CME_LCL_DBG_MIB_GPIO                           , 13  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME11_CME_LCL_DBG_MIB_GPIO_LEN                       , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME11_CME_LCL_DBG_HALT_INPUT                         , 16  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_HALT_INPUT );
+
+REG64_FLD( PU_CME2_CME_LCL_DBG_EN                                  , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_EN         );
+REG64_FLD( PU_CME2_CME_LCL_DBG_HALT_ON_XSTOP                       , 1   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME2_CME_LCL_DBG_HALT_ON_TRIG                        , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME2_CME_LCL_DBG_EN_RISCTRACE                        , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_EN_RISCTRACE );
+REG64_FLD( PU_CME2_CME_LCL_DBG_EN_TRACE_FULL_IVA                   , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_EN_TRACE_FULL_IVA );
+REG64_FLD( PU_CME2_CME_LCL_DBG_DIS_TRACE_EXTRA                     , 5   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_EXTRA );
+REG64_FLD( PU_CME2_CME_LCL_DBG_DIS_TRACE_STALL                     , 6   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_STALL );
+REG64_FLD( PU_CME2_CME_LCL_DBG_EN_WIDE_TRACE                       , 7   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_EN_WIDE_TRACE );
+REG64_FLD( PU_CME2_CME_LCL_DBG_SYNC_TIMER_SEL                      , 8   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL );
+REG64_FLD( PU_CME2_CME_LCL_DBG_SYNC_TIMER_SEL_LEN                  , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL_LEN );
+REG64_FLD( PU_CME2_CME_LCL_DBG_FIR_TRIGGER                         , 12  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME2_CME_LCL_DBG_MIB_GPIO                            , 13  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME2_CME_LCL_DBG_MIB_GPIO_LEN                        , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME2_CME_LCL_DBG_HALT_INPUT                          , 16  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_HALT_INPUT );
+
+REG64_FLD( PU_CME5_CME_LCL_DBG_EN                                  , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_EN         );
+REG64_FLD( PU_CME5_CME_LCL_DBG_HALT_ON_XSTOP                       , 1   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME5_CME_LCL_DBG_HALT_ON_TRIG                        , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME5_CME_LCL_DBG_EN_RISCTRACE                        , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_EN_RISCTRACE );
+REG64_FLD( PU_CME5_CME_LCL_DBG_EN_TRACE_FULL_IVA                   , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_EN_TRACE_FULL_IVA );
+REG64_FLD( PU_CME5_CME_LCL_DBG_DIS_TRACE_EXTRA                     , 5   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_EXTRA );
+REG64_FLD( PU_CME5_CME_LCL_DBG_DIS_TRACE_STALL                     , 6   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_STALL );
+REG64_FLD( PU_CME5_CME_LCL_DBG_EN_WIDE_TRACE                       , 7   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_EN_WIDE_TRACE );
+REG64_FLD( PU_CME5_CME_LCL_DBG_SYNC_TIMER_SEL                      , 8   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL );
+REG64_FLD( PU_CME5_CME_LCL_DBG_SYNC_TIMER_SEL_LEN                  , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL_LEN );
+REG64_FLD( PU_CME5_CME_LCL_DBG_FIR_TRIGGER                         , 12  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME5_CME_LCL_DBG_MIB_GPIO                            , 13  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME5_CME_LCL_DBG_MIB_GPIO_LEN                        , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME5_CME_LCL_DBG_HALT_INPUT                          , 16  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_HALT_INPUT );
+
+REG64_FLD( PU_CME9_CME_LCL_DBG_EN                                  , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_EN         );
+REG64_FLD( PU_CME9_CME_LCL_DBG_HALT_ON_XSTOP                       , 1   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME9_CME_LCL_DBG_HALT_ON_TRIG                        , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME9_CME_LCL_DBG_EN_RISCTRACE                        , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_EN_RISCTRACE );
+REG64_FLD( PU_CME9_CME_LCL_DBG_EN_TRACE_FULL_IVA                   , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_EN_TRACE_FULL_IVA );
+REG64_FLD( PU_CME9_CME_LCL_DBG_DIS_TRACE_EXTRA                     , 5   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_EXTRA );
+REG64_FLD( PU_CME9_CME_LCL_DBG_DIS_TRACE_STALL                     , 6   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_STALL );
+REG64_FLD( PU_CME9_CME_LCL_DBG_EN_WIDE_TRACE                       , 7   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_EN_WIDE_TRACE );
+REG64_FLD( PU_CME9_CME_LCL_DBG_SYNC_TIMER_SEL                      , 8   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL );
+REG64_FLD( PU_CME9_CME_LCL_DBG_SYNC_TIMER_SEL_LEN                  , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL_LEN );
+REG64_FLD( PU_CME9_CME_LCL_DBG_FIR_TRIGGER                         , 12  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME9_CME_LCL_DBG_MIB_GPIO                            , 13  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME9_CME_LCL_DBG_MIB_GPIO_LEN                        , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME9_CME_LCL_DBG_HALT_INPUT                          , 16  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_HALT_INPUT );
+
+REG64_FLD( PU_CME6_CME_LCL_DBG_EN                                  , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_EN         );
+REG64_FLD( PU_CME6_CME_LCL_DBG_HALT_ON_XSTOP                       , 1   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME6_CME_LCL_DBG_HALT_ON_TRIG                        , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME6_CME_LCL_DBG_EN_RISCTRACE                        , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_EN_RISCTRACE );
+REG64_FLD( PU_CME6_CME_LCL_DBG_EN_TRACE_FULL_IVA                   , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_EN_TRACE_FULL_IVA );
+REG64_FLD( PU_CME6_CME_LCL_DBG_DIS_TRACE_EXTRA                     , 5   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_EXTRA );
+REG64_FLD( PU_CME6_CME_LCL_DBG_DIS_TRACE_STALL                     , 6   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_STALL );
+REG64_FLD( PU_CME6_CME_LCL_DBG_EN_WIDE_TRACE                       , 7   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_EN_WIDE_TRACE );
+REG64_FLD( PU_CME6_CME_LCL_DBG_SYNC_TIMER_SEL                      , 8   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL );
+REG64_FLD( PU_CME6_CME_LCL_DBG_SYNC_TIMER_SEL_LEN                  , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL_LEN );
+REG64_FLD( PU_CME6_CME_LCL_DBG_FIR_TRIGGER                         , 12  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME6_CME_LCL_DBG_MIB_GPIO                            , 13  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME6_CME_LCL_DBG_MIB_GPIO_LEN                        , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME6_CME_LCL_DBG_HALT_INPUT                          , 16  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_HALT_INPUT );
+
+REG64_FLD( PU_CME10_CME_LCL_DBG_EN                                 , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_EN         );
+REG64_FLD( PU_CME10_CME_LCL_DBG_HALT_ON_XSTOP                      , 1   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME10_CME_LCL_DBG_HALT_ON_TRIG                       , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME10_CME_LCL_DBG_EN_RISCTRACE                       , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_EN_RISCTRACE );
+REG64_FLD( PU_CME10_CME_LCL_DBG_EN_TRACE_FULL_IVA                  , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_EN_TRACE_FULL_IVA );
+REG64_FLD( PU_CME10_CME_LCL_DBG_DIS_TRACE_EXTRA                    , 5   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_EXTRA );
+REG64_FLD( PU_CME10_CME_LCL_DBG_DIS_TRACE_STALL                    , 6   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_STALL );
+REG64_FLD( PU_CME10_CME_LCL_DBG_EN_WIDE_TRACE                      , 7   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_EN_WIDE_TRACE );
+REG64_FLD( PU_CME10_CME_LCL_DBG_SYNC_TIMER_SEL                     , 8   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL );
+REG64_FLD( PU_CME10_CME_LCL_DBG_SYNC_TIMER_SEL_LEN                 , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL_LEN );
+REG64_FLD( PU_CME10_CME_LCL_DBG_FIR_TRIGGER                        , 12  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME10_CME_LCL_DBG_MIB_GPIO                           , 13  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME10_CME_LCL_DBG_MIB_GPIO_LEN                       , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME10_CME_LCL_DBG_HALT_INPUT                         , 16  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_HALT_INPUT );
+
+REG64_FLD( PU_CME8_CME_LCL_DBG_EN                                  , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_EN         );
+REG64_FLD( PU_CME8_CME_LCL_DBG_HALT_ON_XSTOP                       , 1   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME8_CME_LCL_DBG_HALT_ON_TRIG                        , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME8_CME_LCL_DBG_EN_RISCTRACE                        , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_EN_RISCTRACE );
+REG64_FLD( PU_CME8_CME_LCL_DBG_EN_TRACE_FULL_IVA                   , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_EN_TRACE_FULL_IVA );
+REG64_FLD( PU_CME8_CME_LCL_DBG_DIS_TRACE_EXTRA                     , 5   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_EXTRA );
+REG64_FLD( PU_CME8_CME_LCL_DBG_DIS_TRACE_STALL                     , 6   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_STALL );
+REG64_FLD( PU_CME8_CME_LCL_DBG_EN_WIDE_TRACE                       , 7   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_EN_WIDE_TRACE );
+REG64_FLD( PU_CME8_CME_LCL_DBG_SYNC_TIMER_SEL                      , 8   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL );
+REG64_FLD( PU_CME8_CME_LCL_DBG_SYNC_TIMER_SEL_LEN                  , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL_LEN );
+REG64_FLD( PU_CME8_CME_LCL_DBG_FIR_TRIGGER                         , 12  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME8_CME_LCL_DBG_MIB_GPIO                            , 13  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME8_CME_LCL_DBG_MIB_GPIO_LEN                        , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME8_CME_LCL_DBG_HALT_INPUT                          , 16  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_HALT_INPUT );
+
+REG64_FLD( PU_CME1_CME_LCL_DBG_EN                                  , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_EN         );
+REG64_FLD( PU_CME1_CME_LCL_DBG_HALT_ON_XSTOP                       , 1   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME1_CME_LCL_DBG_HALT_ON_TRIG                        , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME1_CME_LCL_DBG_EN_RISCTRACE                        , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_EN_RISCTRACE );
+REG64_FLD( PU_CME1_CME_LCL_DBG_EN_TRACE_FULL_IVA                   , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_EN_TRACE_FULL_IVA );
+REG64_FLD( PU_CME1_CME_LCL_DBG_DIS_TRACE_EXTRA                     , 5   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_EXTRA );
+REG64_FLD( PU_CME1_CME_LCL_DBG_DIS_TRACE_STALL                     , 6   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_STALL );
+REG64_FLD( PU_CME1_CME_LCL_DBG_EN_WIDE_TRACE                       , 7   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_EN_WIDE_TRACE );
+REG64_FLD( PU_CME1_CME_LCL_DBG_SYNC_TIMER_SEL                      , 8   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL );
+REG64_FLD( PU_CME1_CME_LCL_DBG_SYNC_TIMER_SEL_LEN                  , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL_LEN );
+REG64_FLD( PU_CME1_CME_LCL_DBG_FIR_TRIGGER                         , 12  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME1_CME_LCL_DBG_MIB_GPIO                            , 13  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME1_CME_LCL_DBG_MIB_GPIO_LEN                        , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME1_CME_LCL_DBG_HALT_INPUT                          , 16  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_HALT_INPUT );
+
+REG64_FLD( PU_CME0_CME_LCL_DBG_EN                                  , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_EN         );
+REG64_FLD( PU_CME0_CME_LCL_DBG_HALT_ON_XSTOP                       , 1   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME0_CME_LCL_DBG_HALT_ON_TRIG                        , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME0_CME_LCL_DBG_EN_RISCTRACE                        , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_EN_RISCTRACE );
+REG64_FLD( PU_CME0_CME_LCL_DBG_EN_TRACE_FULL_IVA                   , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_EN_TRACE_FULL_IVA );
+REG64_FLD( PU_CME0_CME_LCL_DBG_DIS_TRACE_EXTRA                     , 5   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_EXTRA );
+REG64_FLD( PU_CME0_CME_LCL_DBG_DIS_TRACE_STALL                     , 6   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_STALL );
+REG64_FLD( PU_CME0_CME_LCL_DBG_EN_WIDE_TRACE                       , 7   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_EN_WIDE_TRACE );
+REG64_FLD( PU_CME0_CME_LCL_DBG_SYNC_TIMER_SEL                      , 8   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL );
+REG64_FLD( PU_CME0_CME_LCL_DBG_SYNC_TIMER_SEL_LEN                  , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL_LEN );
+REG64_FLD( PU_CME0_CME_LCL_DBG_FIR_TRIGGER                         , 12  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME0_CME_LCL_DBG_MIB_GPIO                            , 13  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME0_CME_LCL_DBG_MIB_GPIO_LEN                        , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME0_CME_LCL_DBG_HALT_INPUT                          , 16  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_HALT_INPUT );
+
+REG64_FLD( PU_CME7_CME_LCL_DBG_EN                                  , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_EN         );
+REG64_FLD( PU_CME7_CME_LCL_DBG_HALT_ON_XSTOP                       , 1   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME7_CME_LCL_DBG_HALT_ON_TRIG                        , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME7_CME_LCL_DBG_EN_RISCTRACE                        , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_EN_RISCTRACE );
+REG64_FLD( PU_CME7_CME_LCL_DBG_EN_TRACE_FULL_IVA                   , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_EN_TRACE_FULL_IVA );
+REG64_FLD( PU_CME7_CME_LCL_DBG_DIS_TRACE_EXTRA                     , 5   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_EXTRA );
+REG64_FLD( PU_CME7_CME_LCL_DBG_DIS_TRACE_STALL                     , 6   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_DIS_TRACE_STALL );
+REG64_FLD( PU_CME7_CME_LCL_DBG_EN_WIDE_TRACE                       , 7   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_EN_WIDE_TRACE );
+REG64_FLD( PU_CME7_CME_LCL_DBG_SYNC_TIMER_SEL                      , 8   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL );
+REG64_FLD( PU_CME7_CME_LCL_DBG_SYNC_TIMER_SEL_LEN                  , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_SYNC_TIMER_SEL_LEN );
+REG64_FLD( PU_CME7_CME_LCL_DBG_FIR_TRIGGER                         , 12  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME7_CME_LCL_DBG_MIB_GPIO                            , 13  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME7_CME_LCL_DBG_MIB_GPIO_LEN                        , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME7_CME_LCL_DBG_HALT_INPUT                          , 16  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_HALT_INPUT );
+
+REG64_FLD( PU_CME4_CME_LCL_EIMR_INTERRUPT_MASK                     , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME4_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 , 44  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME3_CME_LCL_EIMR_INTERRUPT_MASK                     , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME3_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 , 44  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME11_CME_LCL_EIMR_INTERRUPT_MASK                    , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME11_CME_LCL_EIMR_INTERRUPT_MASK_LEN                , 44  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME2_CME_LCL_EIMR_INTERRUPT_MASK                     , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME2_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 , 44  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME5_CME_LCL_EIMR_INTERRUPT_MASK                     , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME5_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 , 44  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME9_CME_LCL_EIMR_INTERRUPT_MASK                     , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME9_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 , 44  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME6_CME_LCL_EIMR_INTERRUPT_MASK                     , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME6_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 , 44  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME10_CME_LCL_EIMR_INTERRUPT_MASK                    , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME10_CME_LCL_EIMR_INTERRUPT_MASK_LEN                , 44  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME8_CME_LCL_EIMR_INTERRUPT_MASK                     , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME8_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 , 44  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME1_CME_LCL_EIMR_INTERRUPT_MASK                     , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME1_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 , 44  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME0_CME_LCL_EIMR_INTERRUPT_MASK                     , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME0_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 , 44  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME7_CME_LCL_EIMR_INTERRUPT_MASK                     , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME7_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 , 44  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME4_CME_LCL_EINR_INTERRUPT_INPUT                    , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME4_CME_LCL_EINR_INTERRUPT_INPUT_LEN                , 44  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME3_CME_LCL_EINR_INTERRUPT_INPUT                    , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME3_CME_LCL_EINR_INTERRUPT_INPUT_LEN                , 44  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME11_CME_LCL_EINR_INTERRUPT_INPUT                   , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME11_CME_LCL_EINR_INTERRUPT_INPUT_LEN               , 44  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME2_CME_LCL_EINR_INTERRUPT_INPUT                    , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME2_CME_LCL_EINR_INTERRUPT_INPUT_LEN                , 44  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME5_CME_LCL_EINR_INTERRUPT_INPUT                    , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME5_CME_LCL_EINR_INTERRUPT_INPUT_LEN                , 44  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME9_CME_LCL_EINR_INTERRUPT_INPUT                    , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME9_CME_LCL_EINR_INTERRUPT_INPUT_LEN                , 44  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME6_CME_LCL_EINR_INTERRUPT_INPUT                    , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME6_CME_LCL_EINR_INTERRUPT_INPUT_LEN                , 44  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME10_CME_LCL_EINR_INTERRUPT_INPUT                   , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME10_CME_LCL_EINR_INTERRUPT_INPUT_LEN               , 44  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME8_CME_LCL_EINR_INTERRUPT_INPUT                    , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME8_CME_LCL_EINR_INTERRUPT_INPUT_LEN                , 44  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME1_CME_LCL_EINR_INTERRUPT_INPUT                    , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME1_CME_LCL_EINR_INTERRUPT_INPUT_LEN                , 44  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME0_CME_LCL_EINR_INTERRUPT_INPUT                    , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME0_CME_LCL_EINR_INTERRUPT_INPUT_LEN                , 44  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME7_CME_LCL_EINR_INTERRUPT_INPUT                    , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME7_CME_LCL_EINR_INTERRUPT_INPUT_LEN                , 44  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME4_CME_LCL_EIPR_INTERRUPT_POLARITY                 , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME4_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             , 44  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME3_CME_LCL_EIPR_INTERRUPT_POLARITY                 , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME3_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             , 44  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME11_CME_LCL_EIPR_INTERRUPT_POLARITY                , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME11_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN            , 44  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME2_CME_LCL_EIPR_INTERRUPT_POLARITY                 , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME2_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             , 44  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME5_CME_LCL_EIPR_INTERRUPT_POLARITY                 , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME5_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             , 44  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME9_CME_LCL_EIPR_INTERRUPT_POLARITY                 , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME9_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             , 44  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME6_CME_LCL_EIPR_INTERRUPT_POLARITY                 , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME6_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             , 44  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME10_CME_LCL_EIPR_INTERRUPT_POLARITY                , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME10_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN            , 44  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME8_CME_LCL_EIPR_INTERRUPT_POLARITY                 , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME8_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             , 44  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME1_CME_LCL_EIPR_INTERRUPT_POLARITY                 , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME1_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             , 44  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME0_CME_LCL_EIPR_INTERRUPT_POLARITY                 , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME0_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             , 44  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME7_CME_LCL_EIPR_INTERRUPT_POLARITY                 , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME7_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             , 44  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME4_CME_LCL_EISR_DEBUGGER                           , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME4_CME_LCL_EISR_DEBUG_TRIGGER                      , 1   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME4_CME_LCL_EISR_QUAD_CHECKSTOP                     , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME4_CME_LCL_EISR_PVREF_FAIL                         , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME4_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME4_CME_LCL_EISR_CORE_CHECKSTOP                     , 5   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME4_CME_LCL_EISR_SPARE_6_7                          , 6   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_SPARE_6_7  );
+REG64_FLD( PU_CME4_CME_LCL_EISR_SPARE_6_7_LEN                      , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_SPARE_6_7_LEN );
+REG64_FLD( PU_CME4_CME_LCL_EISR_BCE_BUSY_HIGH                      , 8   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME4_CME_LCL_EISR_BCE_TIMEOUT                        , 9   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL3_C0                       , 10  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL3_C1                       , 11  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_PC_INTR_PENDING_C0                 , 12  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_PC_INTR_PENDING_C1                 , 13  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  , 14  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  , 15  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_REG_WAKEUP_C0                      , 16  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_REG_WAKEUP_C1                      , 17  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL2_C0                       , 18  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL2_C1                       , 19  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              , 20  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              , 21  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_L2_PURGE_DONE                      , 22  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME4_CME_LCL_EISR_NCU_PURGE_DONE                     , 23  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME4_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 , 24  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 , 25  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_BCE_BUSY_LOW                       , 26  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME4_CME_LCL_EISR_SPARE_27_28                        , 27  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_SPARE_27_28 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_SPARE_27_28_LEN                    , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_SPARE_27_28_LEN );
+REG64_FLD( PU_CME4_CME_LCL_EISR_COMM_RECVD                         , 29  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME4_CME_LCL_EISR_COMM_SEND_ACK                      , 30  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME4_CME_LCL_EISR_COMM_SEND_NACK                     , 31  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME4_CME_LCL_EISR_SPARE_32_33                        , 32  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_SPARE_32_33_LEN                    , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME4_CME_LCL_EISR_PMCR_UPDATE_C0                     , 34  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_PMCR_UPDATE_C1                     , 35  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL0_C0                       , 36  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL0_C1                       , 37  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_SPARE_38_39                        , 38  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_SPARE_38_39 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_SPARE_38_39_LEN                    , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_SPARE_38_39_LEN );
+REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL1_C0                       , 40  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL1_C1                       , 41  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_RESERVED_42_43                     , 42  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_RESERVED_42_43_LEN                 , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME3_CME_LCL_EISR_DEBUGGER                           , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME3_CME_LCL_EISR_DEBUG_TRIGGER                      , 1   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME3_CME_LCL_EISR_QUAD_CHECKSTOP                     , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME3_CME_LCL_EISR_PVREF_FAIL                         , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME3_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME3_CME_LCL_EISR_CORE_CHECKSTOP                     , 5   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME3_CME_LCL_EISR_SPARE_6_7                          , 6   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_SPARE_6_7  );
+REG64_FLD( PU_CME3_CME_LCL_EISR_SPARE_6_7_LEN                      , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_SPARE_6_7_LEN );
+REG64_FLD( PU_CME3_CME_LCL_EISR_BCE_BUSY_HIGH                      , 8   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME3_CME_LCL_EISR_BCE_TIMEOUT                        , 9   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL3_C0                       , 10  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL3_C1                       , 11  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_PC_INTR_PENDING_C0                 , 12  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_PC_INTR_PENDING_C1                 , 13  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  , 14  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  , 15  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_REG_WAKEUP_C0                      , 16  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_REG_WAKEUP_C1                      , 17  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL2_C0                       , 18  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL2_C1                       , 19  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              , 20  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              , 21  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_L2_PURGE_DONE                      , 22  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME3_CME_LCL_EISR_NCU_PURGE_DONE                     , 23  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME3_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 , 24  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 , 25  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_BCE_BUSY_LOW                       , 26  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME3_CME_LCL_EISR_SPARE_27_28                        , 27  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_SPARE_27_28 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_SPARE_27_28_LEN                    , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_SPARE_27_28_LEN );
+REG64_FLD( PU_CME3_CME_LCL_EISR_COMM_RECVD                         , 29  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME3_CME_LCL_EISR_COMM_SEND_ACK                      , 30  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME3_CME_LCL_EISR_COMM_SEND_NACK                     , 31  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME3_CME_LCL_EISR_SPARE_32_33                        , 32  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_SPARE_32_33_LEN                    , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME3_CME_LCL_EISR_PMCR_UPDATE_C0                     , 34  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_PMCR_UPDATE_C1                     , 35  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL0_C0                       , 36  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL0_C1                       , 37  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_SPARE_38_39                        , 38  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_SPARE_38_39 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_SPARE_38_39_LEN                    , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_SPARE_38_39_LEN );
+REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL1_C0                       , 40  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL1_C1                       , 41  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_RESERVED_42_43                     , 42  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_RESERVED_42_43_LEN                 , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME11_CME_LCL_EISR_DEBUGGER                          , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME11_CME_LCL_EISR_DEBUG_TRIGGER                     , 1   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME11_CME_LCL_EISR_QUAD_CHECKSTOP                    , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME11_CME_LCL_EISR_PVREF_FAIL                        , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME11_CME_LCL_EISR_OCC_HEARTBEAT_LOST                , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME11_CME_LCL_EISR_CORE_CHECKSTOP                    , 5   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME11_CME_LCL_EISR_SPARE_6_7                         , 6   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_SPARE_6_7  );
+REG64_FLD( PU_CME11_CME_LCL_EISR_SPARE_6_7_LEN                     , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_SPARE_6_7_LEN );
+REG64_FLD( PU_CME11_CME_LCL_EISR_BCE_BUSY_HIGH                     , 8   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME11_CME_LCL_EISR_BCE_TIMEOUT                       , 9   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL3_C0                      , 10  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL3_C1                      , 11  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_PC_INTR_PENDING_C0                , 12  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_PC_INTR_PENDING_C1                , 13  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_SPECIAL_WAKEUP_C0                 , 14  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_SPECIAL_WAKEUP_C1                 , 15  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_REG_WAKEUP_C0                     , 16  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_REG_WAKEUP_C1                     , 17  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL2_C0                      , 18  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL2_C1                      , 19  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0             , 20  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1             , 21  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_L2_PURGE_DONE                     , 22  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME11_CME_LCL_EISR_NCU_PURGE_DONE                    , 23  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME11_CME_LCL_EISR_CHTM_PURGE_DONE_C0                , 24  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_CHTM_PURGE_DONE_C1                , 25  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_BCE_BUSY_LOW                      , 26  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME11_CME_LCL_EISR_SPARE_27_28                       , 27  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_SPARE_27_28 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_SPARE_27_28_LEN                   , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_SPARE_27_28_LEN );
+REG64_FLD( PU_CME11_CME_LCL_EISR_COMM_RECVD                        , 29  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME11_CME_LCL_EISR_COMM_SEND_ACK                     , 30  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME11_CME_LCL_EISR_COMM_SEND_NACK                    , 31  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME11_CME_LCL_EISR_SPARE_32_33                       , 32  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_SPARE_32_33_LEN                   , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME11_CME_LCL_EISR_PMCR_UPDATE_C0                    , 34  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_PMCR_UPDATE_C1                    , 35  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL0_C0                      , 36  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL0_C1                      , 37  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_SPARE_38_39                       , 38  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_SPARE_38_39 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_SPARE_38_39_LEN                   , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_SPARE_38_39_LEN );
+REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL1_C0                      , 40  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL1_C1                      , 41  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_RESERVED_42_43                    , 42  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_RESERVED_42_43_LEN                , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME2_CME_LCL_EISR_DEBUGGER                           , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME2_CME_LCL_EISR_DEBUG_TRIGGER                      , 1   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME2_CME_LCL_EISR_QUAD_CHECKSTOP                     , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME2_CME_LCL_EISR_PVREF_FAIL                         , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME2_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME2_CME_LCL_EISR_CORE_CHECKSTOP                     , 5   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME2_CME_LCL_EISR_SPARE_6_7                          , 6   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_SPARE_6_7  );
+REG64_FLD( PU_CME2_CME_LCL_EISR_SPARE_6_7_LEN                      , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_SPARE_6_7_LEN );
+REG64_FLD( PU_CME2_CME_LCL_EISR_BCE_BUSY_HIGH                      , 8   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME2_CME_LCL_EISR_BCE_TIMEOUT                        , 9   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL3_C0                       , 10  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL3_C1                       , 11  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_PC_INTR_PENDING_C0                 , 12  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_PC_INTR_PENDING_C1                 , 13  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  , 14  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  , 15  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_REG_WAKEUP_C0                      , 16  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_REG_WAKEUP_C1                      , 17  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL2_C0                       , 18  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL2_C1                       , 19  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              , 20  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              , 21  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_L2_PURGE_DONE                      , 22  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME2_CME_LCL_EISR_NCU_PURGE_DONE                     , 23  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME2_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 , 24  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 , 25  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_BCE_BUSY_LOW                       , 26  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME2_CME_LCL_EISR_SPARE_27_28                        , 27  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_SPARE_27_28 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_SPARE_27_28_LEN                    , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_SPARE_27_28_LEN );
+REG64_FLD( PU_CME2_CME_LCL_EISR_COMM_RECVD                         , 29  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME2_CME_LCL_EISR_COMM_SEND_ACK                      , 30  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME2_CME_LCL_EISR_COMM_SEND_NACK                     , 31  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME2_CME_LCL_EISR_SPARE_32_33                        , 32  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_SPARE_32_33_LEN                    , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME2_CME_LCL_EISR_PMCR_UPDATE_C0                     , 34  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_PMCR_UPDATE_C1                     , 35  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL0_C0                       , 36  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL0_C1                       , 37  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_SPARE_38_39                        , 38  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_SPARE_38_39 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_SPARE_38_39_LEN                    , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_SPARE_38_39_LEN );
+REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL1_C0                       , 40  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL1_C1                       , 41  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_RESERVED_42_43                     , 42  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_RESERVED_42_43_LEN                 , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME5_CME_LCL_EISR_DEBUGGER                           , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME5_CME_LCL_EISR_DEBUG_TRIGGER                      , 1   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME5_CME_LCL_EISR_QUAD_CHECKSTOP                     , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME5_CME_LCL_EISR_PVREF_FAIL                         , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME5_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME5_CME_LCL_EISR_CORE_CHECKSTOP                     , 5   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME5_CME_LCL_EISR_SPARE_6_7                          , 6   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_SPARE_6_7  );
+REG64_FLD( PU_CME5_CME_LCL_EISR_SPARE_6_7_LEN                      , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_SPARE_6_7_LEN );
+REG64_FLD( PU_CME5_CME_LCL_EISR_BCE_BUSY_HIGH                      , 8   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME5_CME_LCL_EISR_BCE_TIMEOUT                        , 9   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL3_C0                       , 10  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL3_C1                       , 11  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_PC_INTR_PENDING_C0                 , 12  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_PC_INTR_PENDING_C1                 , 13  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  , 14  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  , 15  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_REG_WAKEUP_C0                      , 16  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_REG_WAKEUP_C1                      , 17  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL2_C0                       , 18  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL2_C1                       , 19  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              , 20  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              , 21  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_L2_PURGE_DONE                      , 22  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME5_CME_LCL_EISR_NCU_PURGE_DONE                     , 23  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME5_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 , 24  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 , 25  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_BCE_BUSY_LOW                       , 26  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME5_CME_LCL_EISR_SPARE_27_28                        , 27  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_SPARE_27_28 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_SPARE_27_28_LEN                    , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_SPARE_27_28_LEN );
+REG64_FLD( PU_CME5_CME_LCL_EISR_COMM_RECVD                         , 29  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME5_CME_LCL_EISR_COMM_SEND_ACK                      , 30  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME5_CME_LCL_EISR_COMM_SEND_NACK                     , 31  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME5_CME_LCL_EISR_SPARE_32_33                        , 32  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_SPARE_32_33_LEN                    , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME5_CME_LCL_EISR_PMCR_UPDATE_C0                     , 34  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_PMCR_UPDATE_C1                     , 35  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL0_C0                       , 36  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL0_C1                       , 37  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_SPARE_38_39                        , 38  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_SPARE_38_39 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_SPARE_38_39_LEN                    , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_SPARE_38_39_LEN );
+REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL1_C0                       , 40  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL1_C1                       , 41  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_RESERVED_42_43                     , 42  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_RESERVED_42_43_LEN                 , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME9_CME_LCL_EISR_DEBUGGER                           , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME9_CME_LCL_EISR_DEBUG_TRIGGER                      , 1   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME9_CME_LCL_EISR_QUAD_CHECKSTOP                     , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME9_CME_LCL_EISR_PVREF_FAIL                         , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME9_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME9_CME_LCL_EISR_CORE_CHECKSTOP                     , 5   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME9_CME_LCL_EISR_SPARE_6_7                          , 6   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_SPARE_6_7  );
+REG64_FLD( PU_CME9_CME_LCL_EISR_SPARE_6_7_LEN                      , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_SPARE_6_7_LEN );
+REG64_FLD( PU_CME9_CME_LCL_EISR_BCE_BUSY_HIGH                      , 8   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME9_CME_LCL_EISR_BCE_TIMEOUT                        , 9   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL3_C0                       , 10  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL3_C1                       , 11  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_PC_INTR_PENDING_C0                 , 12  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_PC_INTR_PENDING_C1                 , 13  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  , 14  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  , 15  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_REG_WAKEUP_C0                      , 16  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_REG_WAKEUP_C1                      , 17  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL2_C0                       , 18  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL2_C1                       , 19  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              , 20  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              , 21  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_L2_PURGE_DONE                      , 22  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME9_CME_LCL_EISR_NCU_PURGE_DONE                     , 23  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME9_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 , 24  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 , 25  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_BCE_BUSY_LOW                       , 26  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME9_CME_LCL_EISR_SPARE_27_28                        , 27  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_SPARE_27_28 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_SPARE_27_28_LEN                    , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_SPARE_27_28_LEN );
+REG64_FLD( PU_CME9_CME_LCL_EISR_COMM_RECVD                         , 29  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME9_CME_LCL_EISR_COMM_SEND_ACK                      , 30  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME9_CME_LCL_EISR_COMM_SEND_NACK                     , 31  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME9_CME_LCL_EISR_SPARE_32_33                        , 32  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_SPARE_32_33_LEN                    , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME9_CME_LCL_EISR_PMCR_UPDATE_C0                     , 34  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_PMCR_UPDATE_C1                     , 35  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL0_C0                       , 36  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL0_C1                       , 37  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_SPARE_38_39                        , 38  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_SPARE_38_39 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_SPARE_38_39_LEN                    , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_SPARE_38_39_LEN );
+REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL1_C0                       , 40  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL1_C1                       , 41  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_RESERVED_42_43                     , 42  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_RESERVED_42_43_LEN                 , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME6_CME_LCL_EISR_DEBUGGER                           , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME6_CME_LCL_EISR_DEBUG_TRIGGER                      , 1   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME6_CME_LCL_EISR_QUAD_CHECKSTOP                     , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME6_CME_LCL_EISR_PVREF_FAIL                         , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME6_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME6_CME_LCL_EISR_CORE_CHECKSTOP                     , 5   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME6_CME_LCL_EISR_SPARE_6_7                          , 6   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_SPARE_6_7  );
+REG64_FLD( PU_CME6_CME_LCL_EISR_SPARE_6_7_LEN                      , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_SPARE_6_7_LEN );
+REG64_FLD( PU_CME6_CME_LCL_EISR_BCE_BUSY_HIGH                      , 8   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME6_CME_LCL_EISR_BCE_TIMEOUT                        , 9   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL3_C0                       , 10  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL3_C1                       , 11  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_PC_INTR_PENDING_C0                 , 12  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_PC_INTR_PENDING_C1                 , 13  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  , 14  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  , 15  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_REG_WAKEUP_C0                      , 16  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_REG_WAKEUP_C1                      , 17  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL2_C0                       , 18  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL2_C1                       , 19  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              , 20  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              , 21  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_L2_PURGE_DONE                      , 22  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME6_CME_LCL_EISR_NCU_PURGE_DONE                     , 23  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME6_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 , 24  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 , 25  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_BCE_BUSY_LOW                       , 26  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME6_CME_LCL_EISR_SPARE_27_28                        , 27  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_SPARE_27_28 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_SPARE_27_28_LEN                    , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_SPARE_27_28_LEN );
+REG64_FLD( PU_CME6_CME_LCL_EISR_COMM_RECVD                         , 29  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME6_CME_LCL_EISR_COMM_SEND_ACK                      , 30  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME6_CME_LCL_EISR_COMM_SEND_NACK                     , 31  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME6_CME_LCL_EISR_SPARE_32_33                        , 32  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_SPARE_32_33_LEN                    , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME6_CME_LCL_EISR_PMCR_UPDATE_C0                     , 34  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_PMCR_UPDATE_C1                     , 35  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL0_C0                       , 36  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL0_C1                       , 37  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_SPARE_38_39                        , 38  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_SPARE_38_39 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_SPARE_38_39_LEN                    , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_SPARE_38_39_LEN );
+REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL1_C0                       , 40  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL1_C1                       , 41  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_RESERVED_42_43                     , 42  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_RESERVED_42_43_LEN                 , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME10_CME_LCL_EISR_DEBUGGER                          , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME10_CME_LCL_EISR_DEBUG_TRIGGER                     , 1   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME10_CME_LCL_EISR_QUAD_CHECKSTOP                    , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME10_CME_LCL_EISR_PVREF_FAIL                        , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME10_CME_LCL_EISR_OCC_HEARTBEAT_LOST                , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME10_CME_LCL_EISR_CORE_CHECKSTOP                    , 5   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME10_CME_LCL_EISR_SPARE_6_7                         , 6   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_SPARE_6_7  );
+REG64_FLD( PU_CME10_CME_LCL_EISR_SPARE_6_7_LEN                     , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_SPARE_6_7_LEN );
+REG64_FLD( PU_CME10_CME_LCL_EISR_BCE_BUSY_HIGH                     , 8   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME10_CME_LCL_EISR_BCE_TIMEOUT                       , 9   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL3_C0                      , 10  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL3_C1                      , 11  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_PC_INTR_PENDING_C0                , 12  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_PC_INTR_PENDING_C1                , 13  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_SPECIAL_WAKEUP_C0                 , 14  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_SPECIAL_WAKEUP_C1                 , 15  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_REG_WAKEUP_C0                     , 16  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_REG_WAKEUP_C1                     , 17  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL2_C0                      , 18  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL2_C1                      , 19  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0             , 20  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1             , 21  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_L2_PURGE_DONE                     , 22  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME10_CME_LCL_EISR_NCU_PURGE_DONE                    , 23  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME10_CME_LCL_EISR_CHTM_PURGE_DONE_C0                , 24  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_CHTM_PURGE_DONE_C1                , 25  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_BCE_BUSY_LOW                      , 26  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME10_CME_LCL_EISR_SPARE_27_28                       , 27  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_SPARE_27_28 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_SPARE_27_28_LEN                   , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_SPARE_27_28_LEN );
+REG64_FLD( PU_CME10_CME_LCL_EISR_COMM_RECVD                        , 29  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME10_CME_LCL_EISR_COMM_SEND_ACK                     , 30  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME10_CME_LCL_EISR_COMM_SEND_NACK                    , 31  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME10_CME_LCL_EISR_SPARE_32_33                       , 32  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_SPARE_32_33_LEN                   , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME10_CME_LCL_EISR_PMCR_UPDATE_C0                    , 34  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_PMCR_UPDATE_C1                    , 35  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL0_C0                      , 36  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL0_C1                      , 37  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_SPARE_38_39                       , 38  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_SPARE_38_39 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_SPARE_38_39_LEN                   , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_SPARE_38_39_LEN );
+REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL1_C0                      , 40  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL1_C1                      , 41  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_RESERVED_42_43                    , 42  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_RESERVED_42_43_LEN                , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME8_CME_LCL_EISR_DEBUGGER                           , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME8_CME_LCL_EISR_DEBUG_TRIGGER                      , 1   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME8_CME_LCL_EISR_QUAD_CHECKSTOP                     , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME8_CME_LCL_EISR_PVREF_FAIL                         , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME8_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME8_CME_LCL_EISR_CORE_CHECKSTOP                     , 5   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME8_CME_LCL_EISR_SPARE_6_7                          , 6   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_SPARE_6_7  );
+REG64_FLD( PU_CME8_CME_LCL_EISR_SPARE_6_7_LEN                      , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_SPARE_6_7_LEN );
+REG64_FLD( PU_CME8_CME_LCL_EISR_BCE_BUSY_HIGH                      , 8   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME8_CME_LCL_EISR_BCE_TIMEOUT                        , 9   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL3_C0                       , 10  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL3_C1                       , 11  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_PC_INTR_PENDING_C0                 , 12  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_PC_INTR_PENDING_C1                 , 13  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  , 14  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  , 15  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_REG_WAKEUP_C0                      , 16  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_REG_WAKEUP_C1                      , 17  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL2_C0                       , 18  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL2_C1                       , 19  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              , 20  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              , 21  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_L2_PURGE_DONE                      , 22  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME8_CME_LCL_EISR_NCU_PURGE_DONE                     , 23  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME8_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 , 24  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 , 25  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_BCE_BUSY_LOW                       , 26  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME8_CME_LCL_EISR_SPARE_27_28                        , 27  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_SPARE_27_28 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_SPARE_27_28_LEN                    , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_SPARE_27_28_LEN );
+REG64_FLD( PU_CME8_CME_LCL_EISR_COMM_RECVD                         , 29  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME8_CME_LCL_EISR_COMM_SEND_ACK                      , 30  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME8_CME_LCL_EISR_COMM_SEND_NACK                     , 31  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME8_CME_LCL_EISR_SPARE_32_33                        , 32  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_SPARE_32_33_LEN                    , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME8_CME_LCL_EISR_PMCR_UPDATE_C0                     , 34  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_PMCR_UPDATE_C1                     , 35  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL0_C0                       , 36  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL0_C1                       , 37  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_SPARE_38_39                        , 38  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_SPARE_38_39 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_SPARE_38_39_LEN                    , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_SPARE_38_39_LEN );
+REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL1_C0                       , 40  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL1_C1                       , 41  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_RESERVED_42_43                     , 42  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_RESERVED_42_43_LEN                 , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME1_CME_LCL_EISR_DEBUGGER                           , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME1_CME_LCL_EISR_DEBUG_TRIGGER                      , 1   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME1_CME_LCL_EISR_QUAD_CHECKSTOP                     , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME1_CME_LCL_EISR_PVREF_FAIL                         , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME1_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME1_CME_LCL_EISR_CORE_CHECKSTOP                     , 5   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME1_CME_LCL_EISR_SPARE_6_7                          , 6   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_SPARE_6_7  );
+REG64_FLD( PU_CME1_CME_LCL_EISR_SPARE_6_7_LEN                      , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_SPARE_6_7_LEN );
+REG64_FLD( PU_CME1_CME_LCL_EISR_BCE_BUSY_HIGH                      , 8   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME1_CME_LCL_EISR_BCE_TIMEOUT                        , 9   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL3_C0                       , 10  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL3_C1                       , 11  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_PC_INTR_PENDING_C0                 , 12  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_PC_INTR_PENDING_C1                 , 13  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  , 14  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  , 15  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_REG_WAKEUP_C0                      , 16  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_REG_WAKEUP_C1                      , 17  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL2_C0                       , 18  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL2_C1                       , 19  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              , 20  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              , 21  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_L2_PURGE_DONE                      , 22  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME1_CME_LCL_EISR_NCU_PURGE_DONE                     , 23  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME1_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 , 24  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 , 25  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_BCE_BUSY_LOW                       , 26  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME1_CME_LCL_EISR_SPARE_27_28                        , 27  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_SPARE_27_28 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_SPARE_27_28_LEN                    , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_SPARE_27_28_LEN );
+REG64_FLD( PU_CME1_CME_LCL_EISR_COMM_RECVD                         , 29  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME1_CME_LCL_EISR_COMM_SEND_ACK                      , 30  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME1_CME_LCL_EISR_COMM_SEND_NACK                     , 31  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME1_CME_LCL_EISR_SPARE_32_33                        , 32  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_SPARE_32_33_LEN                    , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME1_CME_LCL_EISR_PMCR_UPDATE_C0                     , 34  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_PMCR_UPDATE_C1                     , 35  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL0_C0                       , 36  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL0_C1                       , 37  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_SPARE_38_39                        , 38  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_SPARE_38_39 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_SPARE_38_39_LEN                    , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_SPARE_38_39_LEN );
+REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL1_C0                       , 40  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL1_C1                       , 41  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_RESERVED_42_43                     , 42  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_RESERVED_42_43_LEN                 , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME0_CME_LCL_EISR_DEBUGGER                           , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME0_CME_LCL_EISR_DEBUG_TRIGGER                      , 1   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME0_CME_LCL_EISR_QUAD_CHECKSTOP                     , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME0_CME_LCL_EISR_PVREF_FAIL                         , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME0_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME0_CME_LCL_EISR_CORE_CHECKSTOP                     , 5   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME0_CME_LCL_EISR_SPARE_6_7                          , 6   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_SPARE_6_7  );
+REG64_FLD( PU_CME0_CME_LCL_EISR_SPARE_6_7_LEN                      , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_SPARE_6_7_LEN );
+REG64_FLD( PU_CME0_CME_LCL_EISR_BCE_BUSY_HIGH                      , 8   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME0_CME_LCL_EISR_BCE_TIMEOUT                        , 9   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL3_C0                       , 10  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL3_C1                       , 11  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_PC_INTR_PENDING_C0                 , 12  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_PC_INTR_PENDING_C1                 , 13  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  , 14  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  , 15  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_REG_WAKEUP_C0                      , 16  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_REG_WAKEUP_C1                      , 17  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL2_C0                       , 18  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL2_C1                       , 19  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              , 20  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              , 21  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_L2_PURGE_DONE                      , 22  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME0_CME_LCL_EISR_NCU_PURGE_DONE                     , 23  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME0_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 , 24  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 , 25  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_BCE_BUSY_LOW                       , 26  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME0_CME_LCL_EISR_SPARE_27_28                        , 27  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_SPARE_27_28 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_SPARE_27_28_LEN                    , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_SPARE_27_28_LEN );
+REG64_FLD( PU_CME0_CME_LCL_EISR_COMM_RECVD                         , 29  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME0_CME_LCL_EISR_COMM_SEND_ACK                      , 30  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME0_CME_LCL_EISR_COMM_SEND_NACK                     , 31  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME0_CME_LCL_EISR_SPARE_32_33                        , 32  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_SPARE_32_33_LEN                    , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME0_CME_LCL_EISR_PMCR_UPDATE_C0                     , 34  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_PMCR_UPDATE_C1                     , 35  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL0_C0                       , 36  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL0_C1                       , 37  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_SPARE_38_39                        , 38  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_SPARE_38_39 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_SPARE_38_39_LEN                    , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_SPARE_38_39_LEN );
+REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL1_C0                       , 40  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL1_C1                       , 41  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_RESERVED_42_43                     , 42  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_RESERVED_42_43_LEN                 , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME7_CME_LCL_EISR_DEBUGGER                           , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME7_CME_LCL_EISR_DEBUG_TRIGGER                      , 1   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME7_CME_LCL_EISR_QUAD_CHECKSTOP                     , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME7_CME_LCL_EISR_PVREF_FAIL                         , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME7_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME7_CME_LCL_EISR_CORE_CHECKSTOP                     , 5   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME7_CME_LCL_EISR_SPARE_6_7                          , 6   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_SPARE_6_7  );
+REG64_FLD( PU_CME7_CME_LCL_EISR_SPARE_6_7_LEN                      , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_SPARE_6_7_LEN );
+REG64_FLD( PU_CME7_CME_LCL_EISR_BCE_BUSY_HIGH                      , 8   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME7_CME_LCL_EISR_BCE_TIMEOUT                        , 9   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL3_C0                       , 10  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL3_C1                       , 11  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_PC_INTR_PENDING_C0                 , 12  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_PC_INTR_PENDING_C1                 , 13  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  , 14  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  , 15  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_REG_WAKEUP_C0                      , 16  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_REG_WAKEUP_C1                      , 17  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL2_C0                       , 18  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL2_C1                       , 19  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              , 20  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              , 21  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_L2_PURGE_DONE                      , 22  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME7_CME_LCL_EISR_NCU_PURGE_DONE                     , 23  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME7_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 , 24  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 , 25  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_BCE_BUSY_LOW                       , 26  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME7_CME_LCL_EISR_SPARE_27_28                        , 27  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_SPARE_27_28 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_SPARE_27_28_LEN                    , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_SPARE_27_28_LEN );
+REG64_FLD( PU_CME7_CME_LCL_EISR_COMM_RECVD                         , 29  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME7_CME_LCL_EISR_COMM_SEND_ACK                      , 30  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME7_CME_LCL_EISR_COMM_SEND_NACK                     , 31  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME7_CME_LCL_EISR_SPARE_32_33                        , 32  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_SPARE_32_33_LEN                    , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME7_CME_LCL_EISR_PMCR_UPDATE_C0                     , 34  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_PMCR_UPDATE_C1                     , 35  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL0_C0                       , 36  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL0_C1                       , 37  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_SPARE_38_39                        , 38  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_SPARE_38_39 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_SPARE_38_39_LEN                    , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_SPARE_38_39_LEN );
+REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL1_C0                       , 40  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL1_C1                       , 41  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_RESERVED_42_43                     , 42  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_RESERVED_42_43_LEN                 , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME4_CME_LCL_EITR_INTERRUPT_TYPE                     , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME4_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 , 44  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME3_CME_LCL_EITR_INTERRUPT_TYPE                     , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME3_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 , 44  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME11_CME_LCL_EITR_INTERRUPT_TYPE                    , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME11_CME_LCL_EITR_INTERRUPT_TYPE_LEN                , 44  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME2_CME_LCL_EITR_INTERRUPT_TYPE                     , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME2_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 , 44  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME5_CME_LCL_EITR_INTERRUPT_TYPE                     , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME5_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 , 44  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME9_CME_LCL_EITR_INTERRUPT_TYPE                     , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME9_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 , 44  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME6_CME_LCL_EITR_INTERRUPT_TYPE                     , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME6_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 , 44  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME10_CME_LCL_EITR_INTERRUPT_TYPE                    , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME10_CME_LCL_EITR_INTERRUPT_TYPE_LEN                , 44  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME8_CME_LCL_EITR_INTERRUPT_TYPE                     , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME8_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 , 44  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME1_CME_LCL_EITR_INTERRUPT_TYPE                     , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME1_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 , 44  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME0_CME_LCL_EITR_INTERRUPT_TYPE                     , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME0_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 , 44  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME7_CME_LCL_EITR_INTERRUPT_TYPE                     , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME7_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 , 44  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME4_CME_LCL_ICCR_COMM_ACK                           , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME4_CME_LCL_ICCR_COMM_NACK                          , 1   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_COMM_NACK  );
+
+REG64_FLD( PU_CME3_CME_LCL_ICCR_COMM_ACK                           , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME3_CME_LCL_ICCR_COMM_NACK                          , 1   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_COMM_NACK  );
+
+REG64_FLD( PU_CME11_CME_LCL_ICCR_COMM_ACK                          , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME11_CME_LCL_ICCR_COMM_NACK                         , 1   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_COMM_NACK  );
+
+REG64_FLD( PU_CME2_CME_LCL_ICCR_COMM_ACK                           , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME2_CME_LCL_ICCR_COMM_NACK                          , 1   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_COMM_NACK  );
+
+REG64_FLD( PU_CME5_CME_LCL_ICCR_COMM_ACK                           , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME5_CME_LCL_ICCR_COMM_NACK                          , 1   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_COMM_NACK  );
+
+REG64_FLD( PU_CME9_CME_LCL_ICCR_COMM_ACK                           , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME9_CME_LCL_ICCR_COMM_NACK                          , 1   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_COMM_NACK  );
+
+REG64_FLD( PU_CME6_CME_LCL_ICCR_COMM_ACK                           , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME6_CME_LCL_ICCR_COMM_NACK                          , 1   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_COMM_NACK  );
+
+REG64_FLD( PU_CME10_CME_LCL_ICCR_COMM_ACK                          , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME10_CME_LCL_ICCR_COMM_NACK                         , 1   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_COMM_NACK  );
+
+REG64_FLD( PU_CME8_CME_LCL_ICCR_COMM_ACK                           , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME8_CME_LCL_ICCR_COMM_NACK                          , 1   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_COMM_NACK  );
+
+REG64_FLD( PU_CME1_CME_LCL_ICCR_COMM_ACK                           , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME1_CME_LCL_ICCR_COMM_NACK                          , 1   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_COMM_NACK  );
+
+REG64_FLD( PU_CME0_CME_LCL_ICCR_COMM_ACK                           , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME0_CME_LCL_ICCR_COMM_NACK                          , 1   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_COMM_NACK  );
+
+REG64_FLD( PU_CME7_CME_LCL_ICCR_COMM_ACK                           , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME7_CME_LCL_ICCR_COMM_NACK                          , 1   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_COMM_NACK  );
+
+REG64_FLD( PU_CME4_CME_LCL_ICRR_COMM_RECV                          , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME4_CME_LCL_ICRR_COMM_RECV_LEN                      , 32  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME3_CME_LCL_ICRR_COMM_RECV                          , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME3_CME_LCL_ICRR_COMM_RECV_LEN                      , 32  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME11_CME_LCL_ICRR_COMM_RECV                         , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME11_CME_LCL_ICRR_COMM_RECV_LEN                     , 32  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME2_CME_LCL_ICRR_COMM_RECV                          , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME2_CME_LCL_ICRR_COMM_RECV_LEN                      , 32  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME5_CME_LCL_ICRR_COMM_RECV                          , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME5_CME_LCL_ICRR_COMM_RECV_LEN                      , 32  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME9_CME_LCL_ICRR_COMM_RECV                          , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME9_CME_LCL_ICRR_COMM_RECV_LEN                      , 32  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME6_CME_LCL_ICRR_COMM_RECV                          , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME6_CME_LCL_ICRR_COMM_RECV_LEN                      , 32  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME10_CME_LCL_ICRR_COMM_RECV                         , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME10_CME_LCL_ICRR_COMM_RECV_LEN                     , 32  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME8_CME_LCL_ICRR_COMM_RECV                          , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME8_CME_LCL_ICRR_COMM_RECV_LEN                      , 32  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME1_CME_LCL_ICRR_COMM_RECV                          , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME1_CME_LCL_ICRR_COMM_RECV_LEN                      , 32  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME0_CME_LCL_ICRR_COMM_RECV                          , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME0_CME_LCL_ICRR_COMM_RECV_LEN                      , 32  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME7_CME_LCL_ICRR_COMM_RECV                          , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME7_CME_LCL_ICRR_COMM_RECV_LEN                      , 32  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME4_CME_LCL_ICSR_COMM_SEND                          , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME4_CME_LCL_ICSR_COMM_SEND_LEN                      , 32  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME3_CME_LCL_ICSR_COMM_SEND                          , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME3_CME_LCL_ICSR_COMM_SEND_LEN                      , 32  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME11_CME_LCL_ICSR_COMM_SEND                         , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME11_CME_LCL_ICSR_COMM_SEND_LEN                     , 32  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME2_CME_LCL_ICSR_COMM_SEND                          , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME2_CME_LCL_ICSR_COMM_SEND_LEN                      , 32  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME5_CME_LCL_ICSR_COMM_SEND                          , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME5_CME_LCL_ICSR_COMM_SEND_LEN                      , 32  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME9_CME_LCL_ICSR_COMM_SEND                          , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME9_CME_LCL_ICSR_COMM_SEND_LEN                      , 32  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME6_CME_LCL_ICSR_COMM_SEND                          , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME6_CME_LCL_ICSR_COMM_SEND_LEN                      , 32  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME10_CME_LCL_ICSR_COMM_SEND                         , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME10_CME_LCL_ICSR_COMM_SEND_LEN                     , 32  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME8_CME_LCL_ICSR_COMM_SEND                          , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME8_CME_LCL_ICSR_COMM_SEND_LEN                      , 32  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME1_CME_LCL_ICSR_COMM_SEND                          , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME1_CME_LCL_ICSR_COMM_SEND_LEN                      , 32  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME0_CME_LCL_ICSR_COMM_SEND                          , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME0_CME_LCL_ICSR_COMM_SEND_LEN                      , 32  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME7_CME_LCL_ICSR_COMM_SEND                          , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME7_CME_LCL_ICSR_COMM_SEND_LEN                      , 32  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME4_CME_LCL_LMCR_RESET_IMPRECISE_QERR               , 32  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME4_CME_LCL_LMCR_SET_ECC_INJECT_ERR                 , 33  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME4_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE    , 34  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME4_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE    , 35  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME4_CME_LCL_LMCR_FENCE_EISR                         , 36  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_FENCE_EISR );
+
+REG64_FLD( PU_CME3_CME_LCL_LMCR_RESET_IMPRECISE_QERR               , 32  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME3_CME_LCL_LMCR_SET_ECC_INJECT_ERR                 , 33  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME3_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE    , 34  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME3_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE    , 35  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME3_CME_LCL_LMCR_FENCE_EISR                         , 36  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_FENCE_EISR );
+
+REG64_FLD( PU_CME11_CME_LCL_LMCR_RESET_IMPRECISE_QERR              , 32  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME11_CME_LCL_LMCR_SET_ECC_INJECT_ERR                , 33  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME11_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE   , 34  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME11_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE   , 35  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME11_CME_LCL_LMCR_FENCE_EISR                        , 36  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_FENCE_EISR );
+
+REG64_FLD( PU_CME2_CME_LCL_LMCR_RESET_IMPRECISE_QERR               , 32  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME2_CME_LCL_LMCR_SET_ECC_INJECT_ERR                 , 33  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME2_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE    , 34  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME2_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE    , 35  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME2_CME_LCL_LMCR_FENCE_EISR                         , 36  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_FENCE_EISR );
+
+REG64_FLD( PU_CME5_CME_LCL_LMCR_RESET_IMPRECISE_QERR               , 32  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME5_CME_LCL_LMCR_SET_ECC_INJECT_ERR                 , 33  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME5_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE    , 34  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME5_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE    , 35  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME5_CME_LCL_LMCR_FENCE_EISR                         , 36  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_FENCE_EISR );
+
+REG64_FLD( PU_CME9_CME_LCL_LMCR_RESET_IMPRECISE_QERR               , 32  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME9_CME_LCL_LMCR_SET_ECC_INJECT_ERR                 , 33  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME9_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE    , 34  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME9_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE    , 35  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME9_CME_LCL_LMCR_FENCE_EISR                         , 36  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_FENCE_EISR );
+
+REG64_FLD( PU_CME6_CME_LCL_LMCR_RESET_IMPRECISE_QERR               , 32  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME6_CME_LCL_LMCR_SET_ECC_INJECT_ERR                 , 33  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME6_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE    , 34  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME6_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE    , 35  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME6_CME_LCL_LMCR_FENCE_EISR                         , 36  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_FENCE_EISR );
+
+REG64_FLD( PU_CME10_CME_LCL_LMCR_RESET_IMPRECISE_QERR              , 32  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME10_CME_LCL_LMCR_SET_ECC_INJECT_ERR                , 33  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME10_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE   , 34  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME10_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE   , 35  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME10_CME_LCL_LMCR_FENCE_EISR                        , 36  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_FENCE_EISR );
+
+REG64_FLD( PU_CME8_CME_LCL_LMCR_RESET_IMPRECISE_QERR               , 32  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME8_CME_LCL_LMCR_SET_ECC_INJECT_ERR                 , 33  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME8_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE    , 34  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME8_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE    , 35  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME8_CME_LCL_LMCR_FENCE_EISR                         , 36  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_FENCE_EISR );
+
+REG64_FLD( PU_CME1_CME_LCL_LMCR_RESET_IMPRECISE_QERR               , 32  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME1_CME_LCL_LMCR_SET_ECC_INJECT_ERR                 , 33  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME1_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE    , 34  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME1_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE    , 35  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME1_CME_LCL_LMCR_FENCE_EISR                         , 36  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_FENCE_EISR );
+
+REG64_FLD( PU_CME0_CME_LCL_LMCR_RESET_IMPRECISE_QERR               , 32  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME0_CME_LCL_LMCR_SET_ECC_INJECT_ERR                 , 33  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME0_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE    , 34  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME0_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE    , 35  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME0_CME_LCL_LMCR_FENCE_EISR                         , 36  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_FENCE_EISR );
+
+REG64_FLD( PU_CME7_CME_LCL_LMCR_RESET_IMPRECISE_QERR               , 32  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME7_CME_LCL_LMCR_SET_ECC_INJECT_ERR                 , 33  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME7_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE    , 34  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME7_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE    , 35  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME7_CME_LCL_LMCR_FENCE_EISR                         , 36  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_FENCE_EISR );
+
+REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T0                     , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 , 6   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T1                     , 8   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 , 6   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T2                     , 16  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 , 6   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T3                     , 24  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 , 6   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME4_CME_LCL_PECESR0_USE_PECE                        , 32  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME4_CME_LCL_PECESR0_USE_PECE_LEN                    , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME4_CME_LCL_PECESR0_PC_FUSED_CORE_MODE              , 36  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T0                     , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 , 6   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T1                     , 8   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 , 6   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T2                     , 16  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 , 6   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T3                     , 24  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 , 6   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME3_CME_LCL_PECESR0_USE_PECE                        , 32  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME3_CME_LCL_PECESR0_USE_PECE_LEN                    , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME3_CME_LCL_PECESR0_PC_FUSED_CORE_MODE              , 36  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T0                    , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T0_LEN                , 6   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T1                    , 8   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T1_LEN                , 6   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T2                    , 16  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T2_LEN                , 6   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T3                    , 24  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T3_LEN                , 6   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME11_CME_LCL_PECESR0_USE_PECE                       , 32  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME11_CME_LCL_PECESR0_USE_PECE_LEN                   , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME11_CME_LCL_PECESR0_PC_FUSED_CORE_MODE             , 36  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T0                     , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 , 6   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T1                     , 8   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 , 6   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T2                     , 16  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 , 6   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T3                     , 24  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 , 6   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME2_CME_LCL_PECESR0_USE_PECE                        , 32  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME2_CME_LCL_PECESR0_USE_PECE_LEN                    , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME2_CME_LCL_PECESR0_PC_FUSED_CORE_MODE              , 36  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T0                     , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 , 6   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T1                     , 8   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 , 6   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T2                     , 16  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 , 6   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T3                     , 24  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 , 6   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME5_CME_LCL_PECESR0_USE_PECE                        , 32  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME5_CME_LCL_PECESR0_USE_PECE_LEN                    , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME5_CME_LCL_PECESR0_PC_FUSED_CORE_MODE              , 36  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T0                     , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 , 6   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T1                     , 8   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 , 6   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T2                     , 16  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 , 6   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T3                     , 24  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 , 6   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME9_CME_LCL_PECESR0_USE_PECE                        , 32  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME9_CME_LCL_PECESR0_USE_PECE_LEN                    , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME9_CME_LCL_PECESR0_PC_FUSED_CORE_MODE              , 36  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T0                     , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 , 6   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T1                     , 8   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 , 6   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T2                     , 16  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 , 6   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T3                     , 24  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 , 6   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME6_CME_LCL_PECESR0_USE_PECE                        , 32  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME6_CME_LCL_PECESR0_USE_PECE_LEN                    , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME6_CME_LCL_PECESR0_PC_FUSED_CORE_MODE              , 36  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T0                    , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T0_LEN                , 6   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T1                    , 8   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T1_LEN                , 6   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T2                    , 16  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T2_LEN                , 6   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T3                    , 24  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T3_LEN                , 6   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME10_CME_LCL_PECESR0_USE_PECE                       , 32  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME10_CME_LCL_PECESR0_USE_PECE_LEN                   , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME10_CME_LCL_PECESR0_PC_FUSED_CORE_MODE             , 36  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T0                     , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 , 6   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T1                     , 8   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 , 6   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T2                     , 16  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 , 6   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T3                     , 24  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 , 6   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME8_CME_LCL_PECESR0_USE_PECE                        , 32  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME8_CME_LCL_PECESR0_USE_PECE_LEN                    , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME8_CME_LCL_PECESR0_PC_FUSED_CORE_MODE              , 36  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T0                     , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 , 6   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T1                     , 8   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 , 6   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T2                     , 16  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 , 6   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T3                     , 24  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 , 6   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME1_CME_LCL_PECESR0_USE_PECE                        , 32  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME1_CME_LCL_PECESR0_USE_PECE_LEN                    , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME1_CME_LCL_PECESR0_PC_FUSED_CORE_MODE              , 36  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T0                     , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 , 6   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T1                     , 8   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 , 6   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T2                     , 16  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 , 6   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T3                     , 24  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 , 6   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME0_CME_LCL_PECESR0_USE_PECE                        , 32  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME0_CME_LCL_PECESR0_USE_PECE_LEN                    , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME0_CME_LCL_PECESR0_PC_FUSED_CORE_MODE              , 36  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T0                     , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 , 6   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T1                     , 8   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 , 6   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T2                     , 16  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 , 6   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T3                     , 24  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 , 6   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME7_CME_LCL_PECESR0_USE_PECE                        , 32  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME7_CME_LCL_PECESR0_USE_PECE_LEN                    , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME7_CME_LCL_PECESR0_PC_FUSED_CORE_MODE              , 36  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T0                     , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 , 6   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T1                     , 8   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 , 6   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T2                     , 16  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 , 6   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T3                     , 24  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 , 6   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME4_CME_LCL_PECESR1_USE_PECE                        , 32  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME4_CME_LCL_PECESR1_USE_PECE_LEN                    , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME4_CME_LCL_PECESR1_PC_FUSED_CORE_MODE              , 36  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T0                     , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 , 6   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T1                     , 8   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 , 6   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T2                     , 16  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 , 6   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T3                     , 24  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 , 6   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME3_CME_LCL_PECESR1_USE_PECE                        , 32  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME3_CME_LCL_PECESR1_USE_PECE_LEN                    , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME3_CME_LCL_PECESR1_PC_FUSED_CORE_MODE              , 36  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T0                    , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T0_LEN                , 6   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T1                    , 8   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T1_LEN                , 6   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T2                    , 16  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T2_LEN                , 6   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T3                    , 24  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T3_LEN                , 6   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME11_CME_LCL_PECESR1_USE_PECE                       , 32  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME11_CME_LCL_PECESR1_USE_PECE_LEN                   , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME11_CME_LCL_PECESR1_PC_FUSED_CORE_MODE             , 36  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T0                     , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 , 6   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T1                     , 8   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 , 6   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T2                     , 16  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 , 6   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T3                     , 24  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 , 6   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME2_CME_LCL_PECESR1_USE_PECE                        , 32  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME2_CME_LCL_PECESR1_USE_PECE_LEN                    , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME2_CME_LCL_PECESR1_PC_FUSED_CORE_MODE              , 36  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T0                     , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 , 6   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T1                     , 8   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 , 6   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T2                     , 16  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 , 6   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T3                     , 24  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 , 6   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME5_CME_LCL_PECESR1_USE_PECE                        , 32  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME5_CME_LCL_PECESR1_USE_PECE_LEN                    , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME5_CME_LCL_PECESR1_PC_FUSED_CORE_MODE              , 36  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T0                     , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 , 6   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T1                     , 8   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 , 6   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T2                     , 16  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 , 6   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T3                     , 24  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 , 6   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME9_CME_LCL_PECESR1_USE_PECE                        , 32  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME9_CME_LCL_PECESR1_USE_PECE_LEN                    , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME9_CME_LCL_PECESR1_PC_FUSED_CORE_MODE              , 36  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T0                     , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 , 6   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T1                     , 8   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 , 6   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T2                     , 16  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 , 6   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T3                     , 24  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 , 6   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME6_CME_LCL_PECESR1_USE_PECE                        , 32  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME6_CME_LCL_PECESR1_USE_PECE_LEN                    , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME6_CME_LCL_PECESR1_PC_FUSED_CORE_MODE              , 36  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T0                    , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T0_LEN                , 6   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T1                    , 8   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T1_LEN                , 6   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T2                    , 16  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T2_LEN                , 6   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T3                    , 24  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T3_LEN                , 6   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME10_CME_LCL_PECESR1_USE_PECE                       , 32  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME10_CME_LCL_PECESR1_USE_PECE_LEN                   , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME10_CME_LCL_PECESR1_PC_FUSED_CORE_MODE             , 36  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T0                     , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 , 6   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T1                     , 8   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 , 6   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T2                     , 16  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 , 6   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T3                     , 24  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 , 6   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME8_CME_LCL_PECESR1_USE_PECE                        , 32  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME8_CME_LCL_PECESR1_USE_PECE_LEN                    , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME8_CME_LCL_PECESR1_PC_FUSED_CORE_MODE              , 36  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T0                     , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 , 6   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T1                     , 8   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 , 6   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T2                     , 16  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 , 6   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T3                     , 24  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 , 6   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME1_CME_LCL_PECESR1_USE_PECE                        , 32  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME1_CME_LCL_PECESR1_USE_PECE_LEN                    , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME1_CME_LCL_PECESR1_PC_FUSED_CORE_MODE              , 36  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T0                     , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 , 6   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T1                     , 8   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 , 6   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T2                     , 16  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 , 6   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T3                     , 24  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 , 6   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME0_CME_LCL_PECESR1_USE_PECE                        , 32  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME0_CME_LCL_PECESR1_USE_PECE_LEN                    , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME0_CME_LCL_PECESR1_PC_FUSED_CORE_MODE              , 36  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T0                     , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 , 6   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T1                     , 8   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 , 6   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T2                     , 16  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 , 6   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T3                     , 24  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 , 6   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME7_CME_LCL_PECESR1_USE_PECE                        , 32  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME7_CME_LCL_PECESR1_USE_PECE_LEN                    , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_USE_PECE_LEN );
+REG64_FLD( PU_CME7_CME_LCL_PECESR1_PC_FUSED_CORE_MODE              , 36  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PC_FUSED_CORE_MODE );
+
+REG64_FLD( PU_CME4_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PC_INSTR_RUNNING_C0                , 1   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_C0                        , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_C0_LEN                    , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME4_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                , 8   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_SPARE_9                            , 9   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_SPARE_9    );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PCBMUX_GRANT_C0                    , 10  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PCBMUX_GRANT_C1                    , 11  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               , 12  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                , 16  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PC_INSTR_RUNNING_C1                , 17  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 , 18  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 , 19  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_C1                        , 20  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_C1_LEN                    , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME4_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                , 24  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_SPARE_25_27                        , 25  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_SPARE_25_27 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_SPARE_25_27_LEN                    , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_SPARE_25_27_LEN );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               , 28  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+
+REG64_FLD( PU_CME3_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PC_INSTR_RUNNING_C0                , 1   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_C0                        , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_C0_LEN                    , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME3_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                , 8   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_SPARE_9                            , 9   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_SPARE_9    );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PCBMUX_GRANT_C0                    , 10  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PCBMUX_GRANT_C1                    , 11  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               , 12  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                , 16  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PC_INSTR_RUNNING_C1                , 17  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 , 18  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 , 19  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_C1                        , 20  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_C1_LEN                    , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME3_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                , 24  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_SPARE_25_27                        , 25  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_SPARE_25_27 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_SPARE_25_27_LEN                    , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_SPARE_25_27_LEN );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               , 28  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+
+REG64_FLD( PU_CME11_CME_LCL_SISR_PC_UNMASKED_ATTN_C0               , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PC_INSTR_RUNNING_C0               , 1   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_ALL_HV_C0                , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_ACTIVE_C0                , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_C0                       , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_C0_LEN                   , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME11_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0               , 8   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_SPARE_9                           , 9   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_SPARE_9    );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PCBMUX_GRANT_C0                   , 10  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PCBMUX_GRANT_C1                   , 11  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C0              , 12  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN          , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PC_UNMASKED_ATTN_C1               , 16  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PC_INSTR_RUNNING_C1               , 17  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_ALL_HV_C1                , 18  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_ACTIVE_C1                , 19  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_C1                       , 20  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_C1_LEN                   , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME11_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1               , 24  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_SPARE_25_27                       , 25  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_SPARE_25_27 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_SPARE_25_27_LEN                   , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_SPARE_25_27_LEN );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C1              , 28  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN          , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+
+REG64_FLD( PU_CME2_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PC_INSTR_RUNNING_C0                , 1   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_C0                        , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_C0_LEN                    , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME2_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                , 8   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_SPARE_9                            , 9   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_SPARE_9    );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PCBMUX_GRANT_C0                    , 10  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PCBMUX_GRANT_C1                    , 11  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               , 12  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                , 16  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PC_INSTR_RUNNING_C1                , 17  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 , 18  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 , 19  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_C1                        , 20  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_C1_LEN                    , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME2_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                , 24  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_SPARE_25_27                        , 25  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_SPARE_25_27 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_SPARE_25_27_LEN                    , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_SPARE_25_27_LEN );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               , 28  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+
+REG64_FLD( PU_CME5_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PC_INSTR_RUNNING_C0                , 1   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_C0                        , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_C0_LEN                    , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME5_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                , 8   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_SPARE_9                            , 9   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_SPARE_9    );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PCBMUX_GRANT_C0                    , 10  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PCBMUX_GRANT_C1                    , 11  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               , 12  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                , 16  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PC_INSTR_RUNNING_C1                , 17  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 , 18  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 , 19  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_C1                        , 20  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_C1_LEN                    , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME5_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                , 24  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_SPARE_25_27                        , 25  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_SPARE_25_27 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_SPARE_25_27_LEN                    , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_SPARE_25_27_LEN );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               , 28  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+
+REG64_FLD( PU_CME9_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PC_INSTR_RUNNING_C0                , 1   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_C0                        , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_C0_LEN                    , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME9_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                , 8   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_SPARE_9                            , 9   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_SPARE_9    );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PCBMUX_GRANT_C0                    , 10  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PCBMUX_GRANT_C1                    , 11  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               , 12  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                , 16  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PC_INSTR_RUNNING_C1                , 17  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 , 18  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 , 19  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_C1                        , 20  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_C1_LEN                    , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME9_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                , 24  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_SPARE_25_27                        , 25  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_SPARE_25_27 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_SPARE_25_27_LEN                    , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_SPARE_25_27_LEN );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               , 28  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+
+REG64_FLD( PU_CME6_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PC_INSTR_RUNNING_C0                , 1   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_C0                        , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_C0_LEN                    , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME6_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                , 8   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_SPARE_9                            , 9   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_SPARE_9    );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PCBMUX_GRANT_C0                    , 10  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PCBMUX_GRANT_C1                    , 11  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               , 12  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                , 16  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PC_INSTR_RUNNING_C1                , 17  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 , 18  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 , 19  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_C1                        , 20  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_C1_LEN                    , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME6_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                , 24  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_SPARE_25_27                        , 25  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_SPARE_25_27 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_SPARE_25_27_LEN                    , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_SPARE_25_27_LEN );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               , 28  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+
+REG64_FLD( PU_CME10_CME_LCL_SISR_PC_UNMASKED_ATTN_C0               , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PC_INSTR_RUNNING_C0               , 1   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_ALL_HV_C0                , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_ACTIVE_C0                , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_C0                       , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_C0_LEN                   , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME10_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0               , 8   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_SPARE_9                           , 9   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_SPARE_9    );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PCBMUX_GRANT_C0                   , 10  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PCBMUX_GRANT_C1                   , 11  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C0              , 12  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN          , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PC_UNMASKED_ATTN_C1               , 16  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PC_INSTR_RUNNING_C1               , 17  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_ALL_HV_C1                , 18  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_ACTIVE_C1                , 19  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_C1                       , 20  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_C1_LEN                   , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME10_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1               , 24  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_SPARE_25_27                       , 25  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_SPARE_25_27 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_SPARE_25_27_LEN                   , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_SPARE_25_27_LEN );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C1              , 28  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN          , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+
+REG64_FLD( PU_CME8_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PC_INSTR_RUNNING_C0                , 1   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_C0                        , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_C0_LEN                    , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME8_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                , 8   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_SPARE_9                            , 9   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_SPARE_9    );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PCBMUX_GRANT_C0                    , 10  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PCBMUX_GRANT_C1                    , 11  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               , 12  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                , 16  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PC_INSTR_RUNNING_C1                , 17  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 , 18  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 , 19  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_C1                        , 20  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_C1_LEN                    , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME8_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                , 24  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_SPARE_25_27                        , 25  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_SPARE_25_27 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_SPARE_25_27_LEN                    , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_SPARE_25_27_LEN );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               , 28  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+
+REG64_FLD( PU_CME1_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PC_INSTR_RUNNING_C0                , 1   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_C0                        , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_C0_LEN                    , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME1_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                , 8   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_SPARE_9                            , 9   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_SPARE_9    );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PCBMUX_GRANT_C0                    , 10  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PCBMUX_GRANT_C1                    , 11  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               , 12  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                , 16  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PC_INSTR_RUNNING_C1                , 17  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 , 18  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 , 19  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_C1                        , 20  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_C1_LEN                    , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME1_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                , 24  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_SPARE_25_27                        , 25  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_SPARE_25_27 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_SPARE_25_27_LEN                    , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_SPARE_25_27_LEN );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               , 28  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+
+REG64_FLD( PU_CME0_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PC_INSTR_RUNNING_C0                , 1   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_C0                        , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_C0_LEN                    , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME0_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                , 8   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_SPARE_9                            , 9   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_SPARE_9    );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PCBMUX_GRANT_C0                    , 10  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PCBMUX_GRANT_C1                    , 11  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               , 12  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                , 16  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PC_INSTR_RUNNING_C1                , 17  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 , 18  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 , 19  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_C1                        , 20  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_C1_LEN                    , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME0_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                , 24  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_SPARE_25_27                        , 25  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_SPARE_25_27 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_SPARE_25_27_LEN                    , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_SPARE_25_27_LEN );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               , 28  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+
+REG64_FLD( PU_CME7_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PC_INSTR_RUNNING_C0                , 1   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_C0                        , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_C0_LEN                    , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME7_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                , 8   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_SPARE_9                            , 9   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_SPARE_9    );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PCBMUX_GRANT_C0                    , 10  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PCBMUX_GRANT_C1                    , 11  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               , 12  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                , 16  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PC_INSTR_RUNNING_C1                , 17  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 , 18  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 , 19  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_C1                        , 20  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_C1_LEN                    , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME7_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                , 24  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_ALLOW_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_SPARE_25_27                        , 25  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_SPARE_25_27 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_SPARE_25_27_LEN                    , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_SPARE_25_27_LEN );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               , 28  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+
+REG64_FLD( PU_CME4_CME_LCL_TSEL_FIT_SEL                            , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME4_CME_LCL_TSEL_FIT_SEL_LEN                        , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME4_CME_LCL_TSEL_WATCHDOG_SEL                       , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME4_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME3_CME_LCL_TSEL_FIT_SEL                            , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME3_CME_LCL_TSEL_FIT_SEL_LEN                        , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME3_CME_LCL_TSEL_WATCHDOG_SEL                       , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME3_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME11_CME_LCL_TSEL_FIT_SEL                           , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME11_CME_LCL_TSEL_FIT_SEL_LEN                       , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME11_CME_LCL_TSEL_WATCHDOG_SEL                      , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME11_CME_LCL_TSEL_WATCHDOG_SEL_LEN                  , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME2_CME_LCL_TSEL_FIT_SEL                            , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME2_CME_LCL_TSEL_FIT_SEL_LEN                        , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME2_CME_LCL_TSEL_WATCHDOG_SEL                       , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME2_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME5_CME_LCL_TSEL_FIT_SEL                            , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME5_CME_LCL_TSEL_FIT_SEL_LEN                        , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME5_CME_LCL_TSEL_WATCHDOG_SEL                       , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME5_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME9_CME_LCL_TSEL_FIT_SEL                            , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME9_CME_LCL_TSEL_FIT_SEL_LEN                        , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME9_CME_LCL_TSEL_WATCHDOG_SEL                       , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME9_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME6_CME_LCL_TSEL_FIT_SEL                            , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME6_CME_LCL_TSEL_FIT_SEL_LEN                        , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME6_CME_LCL_TSEL_WATCHDOG_SEL                       , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME6_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME10_CME_LCL_TSEL_FIT_SEL                           , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME10_CME_LCL_TSEL_FIT_SEL_LEN                       , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME10_CME_LCL_TSEL_WATCHDOG_SEL                      , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME10_CME_LCL_TSEL_WATCHDOG_SEL_LEN                  , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME8_CME_LCL_TSEL_FIT_SEL                            , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME8_CME_LCL_TSEL_FIT_SEL_LEN                        , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME8_CME_LCL_TSEL_WATCHDOG_SEL                       , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME8_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME1_CME_LCL_TSEL_FIT_SEL                            , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME1_CME_LCL_TSEL_FIT_SEL_LEN                        , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME1_CME_LCL_TSEL_WATCHDOG_SEL                       , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME1_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME0_CME_LCL_TSEL_FIT_SEL                            , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME0_CME_LCL_TSEL_FIT_SEL_LEN                        , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME0_CME_LCL_TSEL_WATCHDOG_SEL                       , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME0_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME7_CME_LCL_TSEL_FIT_SEL                            , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME7_CME_LCL_TSEL_FIT_SEL_LEN                        , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME7_CME_LCL_TSEL_WATCHDOG_SEL                       , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME7_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME4_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             , 20  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  , 32  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME4_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_AFSR_SAMPLE_VALID                      , 63  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME3_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME3_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             , 20  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  , 32  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME3_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_AFSR_SAMPLE_VALID                      , 63  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME11_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME11_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN            , 20  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                 , 32  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME11_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN             , 20  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_AFSR_SAMPLE_VALID                     , 63  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME2_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME2_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             , 20  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  , 32  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME2_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_AFSR_SAMPLE_VALID                      , 63  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME5_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME5_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             , 20  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  , 32  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME5_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_AFSR_SAMPLE_VALID                      , 63  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME9_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME9_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             , 20  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  , 32  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME9_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_AFSR_SAMPLE_VALID                      , 63  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME6_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME6_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             , 20  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  , 32  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME6_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_AFSR_SAMPLE_VALID                      , 63  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME10_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME10_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN            , 20  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                 , 32  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME10_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN             , 20  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_AFSR_SAMPLE_VALID                     , 63  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME8_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME8_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             , 20  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  , 32  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME8_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_AFSR_SAMPLE_VALID                      , 63  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME1_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME1_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             , 20  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  , 32  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME1_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_AFSR_SAMPLE_VALID                      , 63  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME0_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME0_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             , 20  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  , 32  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME0_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_AFSR_SAMPLE_VALID                      , 63  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME7_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME7_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             , 20  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  , 32  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME7_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_AFSR_SAMPLE_VALID                      , 63  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME4_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME4_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  , 32  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME4_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME3_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  , 32  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME3_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                 , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME11_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN             , 20  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                 , 32  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME11_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN             , 20  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME2_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  , 32  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME2_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME5_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  , 32  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME5_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME9_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  , 32  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME9_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME6_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  , 32  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME6_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                 , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME10_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN             , 20  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                 , 32  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME10_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN             , 20  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME8_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  , 32  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME8_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME1_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  , 32  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME1_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME0_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  , 32  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME0_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME7_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  , 32  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME7_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              , 20  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_BUSY                            , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_BUSY       );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_ERROR                           , 1   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_ERROR      );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_RNW                             , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_RNW        );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_BARSEL                          , 5   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_BARSEL     );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_PRIORITY                        , 6   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_INJECT_ERR                      , 7   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_TYPE                            , 13  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_TYPE       );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_TYPE_LEN                        , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_NUM_BLOCKS                      , 17  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  , 11  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_SBASE                           , 28  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_SBASE      );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_SBASE_LEN                       , 12  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_MBASE                           , 42  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_MBASE      );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_MBASE_LEN                       , 22  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_BUSY                            , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_BUSY       );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_ERROR                           , 1   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_ERROR      );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_RNW                             , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_RNW        );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_BARSEL                          , 5   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_BARSEL     );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_PRIORITY                        , 6   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_INJECT_ERR                      , 7   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_TYPE                            , 13  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_TYPE       );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_TYPE_LEN                        , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_NUM_BLOCKS                      , 17  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  , 11  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_SBASE                           , 28  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_SBASE      );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_SBASE_LEN                       , 12  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_MBASE                           , 42  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_MBASE      );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_MBASE_LEN                       , 22  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_BUSY                           , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_BUSY       );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_ERROR                          , 1   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_ERROR      );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_RNW                            , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_RNW        );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_BARSEL                         , 5   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_BARSEL     );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_PRIORITY                       , 6   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_INJECT_ERR                     , 7   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_TYPE                           , 13  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_TYPE       );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_TYPE_LEN                       , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_NUM_BLOCKS                     , 17  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                 , 11  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_SBASE                          , 28  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_SBASE      );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_SBASE_LEN                      , 12  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_MBASE                          , 42  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_MBASE      );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_MBASE_LEN                      , 22  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_BUSY                            , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_BUSY       );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_ERROR                           , 1   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_ERROR      );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_RNW                             , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_RNW        );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_BARSEL                          , 5   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_BARSEL     );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_PRIORITY                        , 6   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_INJECT_ERR                      , 7   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_TYPE                            , 13  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_TYPE       );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_TYPE_LEN                        , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_NUM_BLOCKS                      , 17  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  , 11  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_SBASE                           , 28  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_SBASE      );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_SBASE_LEN                       , 12  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_MBASE                           , 42  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_MBASE      );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_MBASE_LEN                       , 22  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_BUSY                            , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_BUSY       );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_ERROR                           , 1   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_ERROR      );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_RNW                             , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_RNW        );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_BARSEL                          , 5   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_BARSEL     );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_PRIORITY                        , 6   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_INJECT_ERR                      , 7   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_TYPE                            , 13  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_TYPE       );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_TYPE_LEN                        , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_NUM_BLOCKS                      , 17  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  , 11  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_SBASE                           , 28  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_SBASE      );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_SBASE_LEN                       , 12  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_MBASE                           , 42  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_MBASE      );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_MBASE_LEN                       , 22  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_BUSY                            , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_BUSY       );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_ERROR                           , 1   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_ERROR      );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_RNW                             , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_RNW        );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_BARSEL                          , 5   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_BARSEL     );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_PRIORITY                        , 6   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_INJECT_ERR                      , 7   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_TYPE                            , 13  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_TYPE       );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_TYPE_LEN                        , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_NUM_BLOCKS                      , 17  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  , 11  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_SBASE                           , 28  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_SBASE      );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_SBASE_LEN                       , 12  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_MBASE                           , 42  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_MBASE      );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_MBASE_LEN                       , 22  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_BUSY                            , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_BUSY       );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_ERROR                           , 1   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_ERROR      );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_RNW                             , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_RNW        );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_BARSEL                          , 5   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_BARSEL     );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_PRIORITY                        , 6   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_INJECT_ERR                      , 7   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_TYPE                            , 13  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_TYPE       );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_TYPE_LEN                        , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_NUM_BLOCKS                      , 17  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  , 11  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_SBASE                           , 28  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_SBASE      );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_SBASE_LEN                       , 12  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_MBASE                           , 42  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_MBASE      );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_MBASE_LEN                       , 22  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_BUSY                           , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_BUSY       );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_ERROR                          , 1   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_ERROR      );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_RNW                            , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_RNW        );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_BARSEL                         , 5   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_BARSEL     );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_PRIORITY                       , 6   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_INJECT_ERR                     , 7   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_TYPE                           , 13  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_TYPE       );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_TYPE_LEN                       , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_NUM_BLOCKS                     , 17  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                 , 11  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_SBASE                          , 28  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_SBASE      );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_SBASE_LEN                      , 12  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_MBASE                          , 42  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_MBASE      );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_MBASE_LEN                      , 22  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_BUSY                            , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_BUSY       );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_ERROR                           , 1   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_ERROR      );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_RNW                             , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_RNW        );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_BARSEL                          , 5   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_BARSEL     );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_PRIORITY                        , 6   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_INJECT_ERR                      , 7   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_TYPE                            , 13  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_TYPE       );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_TYPE_LEN                        , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_NUM_BLOCKS                      , 17  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  , 11  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_SBASE                           , 28  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_SBASE      );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_SBASE_LEN                       , 12  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_MBASE                           , 42  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_MBASE      );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_MBASE_LEN                       , 22  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_BUSY                            , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_BUSY       );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_ERROR                           , 1   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_ERROR      );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_RNW                             , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_RNW        );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_BARSEL                          , 5   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_BARSEL     );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_PRIORITY                        , 6   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_INJECT_ERR                      , 7   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_TYPE                            , 13  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_TYPE       );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_TYPE_LEN                        , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_NUM_BLOCKS                      , 17  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  , 11  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_SBASE                           , 28  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_SBASE      );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_SBASE_LEN                       , 12  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_MBASE                           , 42  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_MBASE      );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_MBASE_LEN                       , 22  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_BUSY                            , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_BUSY       );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_ERROR                           , 1   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_ERROR      );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_RNW                             , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_RNW        );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_BARSEL                          , 5   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_BARSEL     );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_PRIORITY                        , 6   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_INJECT_ERR                      , 7   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_TYPE                            , 13  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_TYPE       );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_TYPE_LEN                        , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_NUM_BLOCKS                      , 17  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  , 11  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_SBASE                           , 28  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_SBASE      );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_SBASE_LEN                       , 12  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_MBASE                           , 42  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_MBASE      );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_MBASE_LEN                       , 22  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_BUSY                            , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_BUSY       );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_ERROR                           , 1   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_ERROR      );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_RNW                             , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_RNW        );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_BARSEL                          , 5   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_BARSEL     );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_PRIORITY                        , 6   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_INJECT_ERR                      , 7   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_TYPE                            , 13  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_TYPE       );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_TYPE_LEN                        , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_NUM_BLOCKS                      , 17  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  , 11  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_SBASE                           , 28  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_SBASE      );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_SBASE_LEN                       , 12  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_MBASE                           , 42  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_MBASE      );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_MBASE_LEN                       , 22  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME4_CME_SCOM_FLAGS_DATA                             , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_DATA       );
+REG64_FLD( PU_CME4_CME_SCOM_FLAGS_DATA_LEN                         , 32  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME3_CME_SCOM_FLAGS_DATA                             , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_DATA       );
+REG64_FLD( PU_CME3_CME_SCOM_FLAGS_DATA_LEN                         , 32  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME11_CME_SCOM_FLAGS_DATA                            , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_DATA       );
+REG64_FLD( PU_CME11_CME_SCOM_FLAGS_DATA_LEN                        , 32  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME2_CME_SCOM_FLAGS_DATA                             , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_DATA       );
+REG64_FLD( PU_CME2_CME_SCOM_FLAGS_DATA_LEN                         , 32  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME5_CME_SCOM_FLAGS_DATA                             , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_DATA       );
+REG64_FLD( PU_CME5_CME_SCOM_FLAGS_DATA_LEN                         , 32  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME9_CME_SCOM_FLAGS_DATA                             , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_DATA       );
+REG64_FLD( PU_CME9_CME_SCOM_FLAGS_DATA_LEN                         , 32  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME6_CME_SCOM_FLAGS_DATA                             , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_DATA       );
+REG64_FLD( PU_CME6_CME_SCOM_FLAGS_DATA_LEN                         , 32  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME10_CME_SCOM_FLAGS_DATA                            , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_DATA       );
+REG64_FLD( PU_CME10_CME_SCOM_FLAGS_DATA_LEN                        , 32  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME8_CME_SCOM_FLAGS_DATA                             , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_DATA       );
+REG64_FLD( PU_CME8_CME_SCOM_FLAGS_DATA_LEN                         , 32  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME1_CME_SCOM_FLAGS_DATA                             , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_DATA       );
+REG64_FLD( PU_CME1_CME_SCOM_FLAGS_DATA_LEN                         , 32  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME0_CME_SCOM_FLAGS_DATA                             , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_DATA       );
+REG64_FLD( PU_CME0_CME_SCOM_FLAGS_DATA_LEN                         , 32  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME7_CME_SCOM_FLAGS_DATA                             , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_DATA       );
+REG64_FLD( PU_CME7_CME_SCOM_FLAGS_DATA_LEN                         , 32  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME4_CME_SCOM_PMCRS0_DATA                            , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME4_CME_SCOM_PMCRS0_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME3_CME_SCOM_PMCRS0_DATA                            , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME3_CME_SCOM_PMCRS0_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME11_CME_SCOM_PMCRS0_DATA                           , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME11_CME_SCOM_PMCRS0_DATA_LEN                       , 64  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME2_CME_SCOM_PMCRS0_DATA                            , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME2_CME_SCOM_PMCRS0_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME5_CME_SCOM_PMCRS0_DATA                            , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME5_CME_SCOM_PMCRS0_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME9_CME_SCOM_PMCRS0_DATA                            , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME9_CME_SCOM_PMCRS0_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME6_CME_SCOM_PMCRS0_DATA                            , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME6_CME_SCOM_PMCRS0_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME10_CME_SCOM_PMCRS0_DATA                           , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME10_CME_SCOM_PMCRS0_DATA_LEN                       , 64  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME8_CME_SCOM_PMCRS0_DATA                            , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME8_CME_SCOM_PMCRS0_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME1_CME_SCOM_PMCRS0_DATA                            , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME1_CME_SCOM_PMCRS0_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME0_CME_SCOM_PMCRS0_DATA                            , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME0_CME_SCOM_PMCRS0_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME7_CME_SCOM_PMCRS0_DATA                            , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME7_CME_SCOM_PMCRS0_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME4_CME_SCOM_PMCRS1_DATA                            , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME4_CME_SCOM_PMCRS1_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME3_CME_SCOM_PMCRS1_DATA                            , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME3_CME_SCOM_PMCRS1_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME11_CME_SCOM_PMCRS1_DATA                           , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME11_CME_SCOM_PMCRS1_DATA_LEN                       , 64  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME2_CME_SCOM_PMCRS1_DATA                            , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME2_CME_SCOM_PMCRS1_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME5_CME_SCOM_PMCRS1_DATA                            , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME5_CME_SCOM_PMCRS1_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME9_CME_SCOM_PMCRS1_DATA                            , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME9_CME_SCOM_PMCRS1_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME6_CME_SCOM_PMCRS1_DATA                            , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME6_CME_SCOM_PMCRS1_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME10_CME_SCOM_PMCRS1_DATA                           , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME10_CME_SCOM_PMCRS1_DATA_LEN                       , 64  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME8_CME_SCOM_PMCRS1_DATA                            , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME8_CME_SCOM_PMCRS1_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME1_CME_SCOM_PMCRS1_DATA                            , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME1_CME_SCOM_PMCRS1_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME0_CME_SCOM_PMCRS1_DATA                            , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME0_CME_SCOM_PMCRS1_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME7_CME_SCOM_PMCRS1_DATA                            , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME7_CME_SCOM_PMCRS1_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME4_CME_SCOM_PMSRS0_DATA                            , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME4_CME_SCOM_PMSRS0_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME3_CME_SCOM_PMSRS0_DATA                            , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME3_CME_SCOM_PMSRS0_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME11_CME_SCOM_PMSRS0_DATA                           , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME11_CME_SCOM_PMSRS0_DATA_LEN                       , 64  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME2_CME_SCOM_PMSRS0_DATA                            , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME2_CME_SCOM_PMSRS0_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME5_CME_SCOM_PMSRS0_DATA                            , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME5_CME_SCOM_PMSRS0_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME9_CME_SCOM_PMSRS0_DATA                            , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME9_CME_SCOM_PMSRS0_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME6_CME_SCOM_PMSRS0_DATA                            , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME6_CME_SCOM_PMSRS0_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME10_CME_SCOM_PMSRS0_DATA                           , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME10_CME_SCOM_PMSRS0_DATA_LEN                       , 64  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME8_CME_SCOM_PMSRS0_DATA                            , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME8_CME_SCOM_PMSRS0_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME1_CME_SCOM_PMSRS0_DATA                            , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME1_CME_SCOM_PMSRS0_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME0_CME_SCOM_PMSRS0_DATA                            , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME0_CME_SCOM_PMSRS0_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME7_CME_SCOM_PMSRS0_DATA                            , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME7_CME_SCOM_PMSRS0_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME4_CME_SCOM_PMSRS1_DATA                            , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME4_CME_SCOM_PMSRS1_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME3_CME_SCOM_PMSRS1_DATA                            , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME3_CME_SCOM_PMSRS1_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME11_CME_SCOM_PMSRS1_DATA                           , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME11_CME_SCOM_PMSRS1_DATA_LEN                       , 64  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME2_CME_SCOM_PMSRS1_DATA                            , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME2_CME_SCOM_PMSRS1_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME5_CME_SCOM_PMSRS1_DATA                            , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME5_CME_SCOM_PMSRS1_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME9_CME_SCOM_PMSRS1_DATA                            , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME9_CME_SCOM_PMSRS1_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME6_CME_SCOM_PMSRS1_DATA                            , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME6_CME_SCOM_PMSRS1_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME10_CME_SCOM_PMSRS1_DATA                           , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME10_CME_SCOM_PMSRS1_DATA_LEN                       , 64  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME8_CME_SCOM_PMSRS1_DATA                            , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME8_CME_SCOM_PMSRS1_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME1_CME_SCOM_PMSRS1_DATA                            , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME1_CME_SCOM_PMSRS1_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME0_CME_SCOM_PMSRS1_DATA                            , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME0_CME_SCOM_PMSRS1_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME7_CME_SCOM_PMSRS1_DATA                            , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME7_CME_SCOM_PMSRS1_DATA_LEN                        , 64  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_SPARE0                         , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_SPARE0                         , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_SPARE0                        , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N         , 1   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N         , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N            , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N        , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE          , 8   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE           , 9   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE        , 10  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE               , 11  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE               , 12  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE               , 13  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N     , 14  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N         , 16  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N        , 20  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_SPARE0                         , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_SPARE0                         , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_SPARE0                         , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_SPARE0                         , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_SPARE0                        , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N         , 1   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N         , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N            , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N        , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE          , 8   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE           , 9   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE        , 10  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE               , 11  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE               , 12  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE               , 13  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N     , 14  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N         , 16  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N        , 20  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_SPARE0                         , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_SPARE0                         , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_SPARE0                         , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_SPARE0                         , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_SPARE0                         , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_SPARE0                         , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_SPARE0                        , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N         , 1   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N         , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N            , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N        , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE          , 8   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE           , 9   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE        , 10  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE               , 11  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE               , 12  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE               , 13  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N     , 14  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N         , 16  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N        , 20  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_SPARE0                         , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_SPARE0                         , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_SPARE0                         , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_SPARE0                         , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_SPARE0                        , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N         , 1   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N         , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N            , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N        , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE          , 8   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE           , 9   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE        , 10  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE               , 11  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE               , 12  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE               , 13  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N     , 14  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N         , 16  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N        , 20  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_SPARE0                         , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_SPARE0                         , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_SPARE0                         , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_SPARE0                         , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_SPARE0                         , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_SPARE0                         , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_SPARE0                        , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N         , 1   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N         , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N            , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N        , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE          , 8   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE           , 9   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE        , 10  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE               , 11  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE               , 12  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE               , 13  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N     , 14  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N         , 16  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N        , 20  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_SPARE0                         , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_SPARE0                         , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_SPARE0                         , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_SPARE0                         , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_SPARE0                        , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N         , 1   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N         , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N            , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N        , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE          , 8   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE           , 9   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE        , 10  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE               , 11  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE               , 12  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE               , 13  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N     , 14  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N         , 16  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N        , 20  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_SPARE0                         , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_SPARE0                         , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_SPARE0                         , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_SPARE0                         , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_SPARE0                         , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_SPARE0                         , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_SPARE0                        , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N         , 1   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N         , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N            , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N        , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE          , 8   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE           , 9   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE        , 10  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE               , 11  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE               , 12  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE               , 13  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N     , 14  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N         , 16  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N        , 20  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_SPARE0                         , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_SPARE0                         , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_SPARE0                         , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_SPARE0                         , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_SPARE0                        , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N         , 1   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N         , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N            , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N        , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE          , 8   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE           , 9   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE        , 10  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE               , 11  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE               , 12  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE               , 13  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N     , 14  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N         , 16  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N        , 20  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_SPARE0                         , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_SPARE0                         , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_SPARE0                         , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_SPARE0                         , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_SPARE0                         , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_SPARE0                         , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_SPARE0                        , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N         , 1   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N         , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N            , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N        , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE          , 8   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE           , 9   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE        , 10  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE               , 11  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE               , 12  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE               , 13  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N     , 14  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N         , 16  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N        , 20  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_SPARE0                         , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_SPARE0                         , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_SPARE0                         , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_SPARE0                         , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_SPARE0                        , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N         , 1   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N         , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N            , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N        , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE          , 8   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE           , 9   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE        , 10  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE               , 11  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE               , 12  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE               , 13  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N     , 14  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N         , 16  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N        , 20  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_SPARE0                         , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_SPARE0                         , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_SPARE0                         , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_SPARE0                         , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_SPARE0                         , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_SPARE0                         , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_SPARE0                        , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N         , 1   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N         , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N            , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N        , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE          , 8   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE           , 9   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE        , 10  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE               , 11  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE               , 12  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE               , 13  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N     , 14  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N         , 16  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N        , 20  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_SPARE0                         , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_SPARE0                         , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_SPARE0                         , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_SPARE0                         , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_SPARE0                        , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N         , 1   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N         , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N            , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N        , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE          , 8   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE           , 9   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE        , 10  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE               , 11  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE               , 12  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE               , 13  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N     , 14  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N         , 16  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N        , 20  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_SPARE0                         , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_SPARE0                         , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_SPARE0                         , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_SPARE0                         , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_SPARE0                         , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_SPARE0                         , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_SPARE0                        , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N         , 1   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N         , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N            , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N        , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE          , 8   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE           , 9   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE        , 10  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE               , 11  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE               , 12  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE               , 13  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N     , 14  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N         , 16  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N        , 20  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_SPARE0                         , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_SPARE0                         , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_SPARE0                         , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_SPARE0                         , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_SPARE0                        , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N         , 1   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N         , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N            , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N        , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE          , 8   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE           , 9   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE        , 10  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE               , 11  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE               , 12  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE               , 13  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N     , 14  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N         , 16  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N        , 20  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_SPARE0                         , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_SPARE0                         , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_SPARE0                         , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_SPARE0                         , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_SPARE0                         , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_SPARE0                         , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_SPARE0                        , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N         , 1   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N         , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N            , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N        , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE          , 8   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE           , 9   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE        , 10  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE               , 11  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE               , 12  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE               , 13  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N     , 14  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N         , 16  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N        , 20  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_SPARE0                         , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_SPARE0                         , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_SPARE0                         , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_SPARE0                         , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_SPARE0                        , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N         , 1   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N         , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N            , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N        , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE          , 8   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE           , 9   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE        , 10  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE               , 11  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE               , 12  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE               , 13  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N     , 14  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N         , 16  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N        , 20  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN    , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_SPARE0                         , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_SPARE0                         , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_SPARE0                         , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_SPARE0                         , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_SPARE0     );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          , 1   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           , 8   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            , 9   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         , 10  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                , 11  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                , 12  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                , 13  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      , 14  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          , 16  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         , 20  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_QFMR_TIMEBASE                          , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME4_CME_SCOM_QFMR_TIMEBASE_LEN                      , 32  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_QFMR_CYCLES                            , 32  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_CYCLES     );
+REG64_FLD( PU_CME4_CME_SCOM_QFMR_CYCLES_LEN                        , 32  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_QFMR_TIMEBASE                          , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME3_CME_SCOM_QFMR_TIMEBASE_LEN                      , 32  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_QFMR_CYCLES                            , 32  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_CYCLES     );
+REG64_FLD( PU_CME3_CME_SCOM_QFMR_CYCLES_LEN                        , 32  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_QFMR_TIMEBASE                         , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME11_CME_SCOM_QFMR_TIMEBASE_LEN                     , 32  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_QFMR_CYCLES                           , 32  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_CYCLES     );
+REG64_FLD( PU_CME11_CME_SCOM_QFMR_CYCLES_LEN                       , 32  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_QFMR_TIMEBASE                          , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME2_CME_SCOM_QFMR_TIMEBASE_LEN                      , 32  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_QFMR_CYCLES                            , 32  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_CYCLES     );
+REG64_FLD( PU_CME2_CME_SCOM_QFMR_CYCLES_LEN                        , 32  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_QFMR_TIMEBASE                          , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME5_CME_SCOM_QFMR_TIMEBASE_LEN                      , 32  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_QFMR_CYCLES                            , 32  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_CYCLES     );
+REG64_FLD( PU_CME5_CME_SCOM_QFMR_CYCLES_LEN                        , 32  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_QFMR_TIMEBASE                          , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME9_CME_SCOM_QFMR_TIMEBASE_LEN                      , 32  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_QFMR_CYCLES                            , 32  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_CYCLES     );
+REG64_FLD( PU_CME9_CME_SCOM_QFMR_CYCLES_LEN                        , 32  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_QFMR_TIMEBASE                          , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME6_CME_SCOM_QFMR_TIMEBASE_LEN                      , 32  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_QFMR_CYCLES                            , 32  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_CYCLES     );
+REG64_FLD( PU_CME6_CME_SCOM_QFMR_CYCLES_LEN                        , 32  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_QFMR_TIMEBASE                         , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME10_CME_SCOM_QFMR_TIMEBASE_LEN                     , 32  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_QFMR_CYCLES                           , 32  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_CYCLES     );
+REG64_FLD( PU_CME10_CME_SCOM_QFMR_CYCLES_LEN                       , 32  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_QFMR_TIMEBASE                          , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME8_CME_SCOM_QFMR_TIMEBASE_LEN                      , 32  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_QFMR_CYCLES                            , 32  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_CYCLES     );
+REG64_FLD( PU_CME8_CME_SCOM_QFMR_CYCLES_LEN                        , 32  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_QFMR_TIMEBASE                          , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME1_CME_SCOM_QFMR_TIMEBASE_LEN                      , 32  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_QFMR_CYCLES                            , 32  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_CYCLES     );
+REG64_FLD( PU_CME1_CME_SCOM_QFMR_CYCLES_LEN                        , 32  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_QFMR_TIMEBASE                          , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME0_CME_SCOM_QFMR_TIMEBASE_LEN                      , 32  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_QFMR_CYCLES                            , 32  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_CYCLES     );
+REG64_FLD( PU_CME0_CME_SCOM_QFMR_CYCLES_LEN                        , 32  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_QFMR_TIMEBASE                          , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME7_CME_SCOM_QFMR_TIMEBASE_LEN                      , 32  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_QFMR_CYCLES                            , 32  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_CYCLES     );
+REG64_FLD( PU_CME7_CME_SCOM_QFMR_CYCLES_LEN                        , 32  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PC_ENTRY_ACK_C0                   , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0            , 1   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PC_WAKEUP_C0                      , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C0 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PCBMUX_REQ_C0                     , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_4_5                      , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_4_5_LEN                  , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          , 6   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           , 7   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_8_11                     , 8   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_8_11_LEN                 , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PC_ENTRY_ACK_C1                   , 12  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1            , 13  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PC_WAKEUP_C1                      , 14  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C1 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PCBMUX_REQ_C1                     , 15  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_16_17                    , 16  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_16_17_LEN                , 2   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          , 18  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           , 19  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_20_23                    , 20  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_20_23_LEN                , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_PURGE                          , 24  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_PURGE_ABORT                    , 25  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED26                        , 26  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_RESERVED26 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 , 27  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_NCU_PURGE                         , 28  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_NCU_PURGE_ABORT                   , 29  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_CHTM_PURGE_C0                     , 30  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_CHTM_PURGE_C1                     , 31  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_HMI_REQUEST_C0                    , 32  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_HMI_REQUEST_C1                    , 33  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  , 34  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  , 35  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_36_39                    , 36  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_36_39_LEN                , 4   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PC_ENTRY_ACK_C0                   , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0            , 1   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PC_WAKEUP_C0                      , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C0 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PCBMUX_REQ_C0                     , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_4_5                      , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_4_5_LEN                  , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          , 6   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           , 7   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_8_11                     , 8   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_8_11_LEN                 , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PC_ENTRY_ACK_C1                   , 12  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1            , 13  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PC_WAKEUP_C1                      , 14  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C1 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PCBMUX_REQ_C1                     , 15  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_16_17                    , 16  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_16_17_LEN                , 2   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          , 18  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           , 19  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_20_23                    , 20  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_20_23_LEN                , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_PURGE                          , 24  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_PURGE_ABORT                    , 25  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED26                        , 26  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_RESERVED26 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 , 27  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_NCU_PURGE                         , 28  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_NCU_PURGE_ABORT                   , 29  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_CHTM_PURGE_C0                     , 30  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_CHTM_PURGE_C1                     , 31  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_HMI_REQUEST_C0                    , 32  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_HMI_REQUEST_C1                    , 33  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  , 34  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  , 35  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_36_39                    , 36  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_36_39_LEN                , 4   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PC_ENTRY_ACK_C0                  , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0           , 1   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PC_WAKEUP_C0                     , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C0 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PCBMUX_REQ_C0                    , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_4_5                     , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_4_5_LEN                 , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0         , 6   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0          , 7   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_8_11                    , 8   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_8_11_LEN                , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PC_ENTRY_ACK_C1                  , 12  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1           , 13  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PC_WAKEUP_C1                     , 14  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C1 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PCBMUX_REQ_C1                    , 15  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_16_17                   , 16  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_16_17_LEN               , 2   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1         , 18  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1          , 19  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_20_23                   , 20  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_20_23_LEN               , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_PURGE                         , 24  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_PURGE_ABORT                   , 25  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED26                       , 26  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_RESERVED26 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                , 27  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_NCU_PURGE                        , 28  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_NCU_PURGE_ABORT                  , 29  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_CHTM_PURGE_C0                    , 30  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_CHTM_PURGE_C1                    , 31  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_HMI_REQUEST_C0                   , 32  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_HMI_REQUEST_C1                   , 33  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PPM_SPARE_OUT_C0                 , 34  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PPM_SPARE_OUT_C1                 , 35  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_36_39                   , 36  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_36_39_LEN               , 4   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PC_ENTRY_ACK_C0                   , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0            , 1   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PC_WAKEUP_C0                      , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C0 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PCBMUX_REQ_C0                     , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_4_5                      , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_4_5_LEN                  , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          , 6   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           , 7   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_8_11                     , 8   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_8_11_LEN                 , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PC_ENTRY_ACK_C1                   , 12  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1            , 13  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PC_WAKEUP_C1                      , 14  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C1 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PCBMUX_REQ_C1                     , 15  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_16_17                    , 16  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_16_17_LEN                , 2   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          , 18  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           , 19  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_20_23                    , 20  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_20_23_LEN                , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_PURGE                          , 24  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_PURGE_ABORT                    , 25  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED26                        , 26  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_RESERVED26 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 , 27  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_NCU_PURGE                         , 28  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_NCU_PURGE_ABORT                   , 29  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_CHTM_PURGE_C0                     , 30  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_CHTM_PURGE_C1                     , 31  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_HMI_REQUEST_C0                    , 32  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_HMI_REQUEST_C1                    , 33  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  , 34  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  , 35  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_36_39                    , 36  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_36_39_LEN                , 4   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PC_ENTRY_ACK_C0                   , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0            , 1   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PC_WAKEUP_C0                      , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C0 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PCBMUX_REQ_C0                     , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_4_5                      , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_4_5_LEN                  , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          , 6   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           , 7   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_8_11                     , 8   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_8_11_LEN                 , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PC_ENTRY_ACK_C1                   , 12  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1            , 13  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PC_WAKEUP_C1                      , 14  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C1 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PCBMUX_REQ_C1                     , 15  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_16_17                    , 16  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_16_17_LEN                , 2   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          , 18  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           , 19  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_20_23                    , 20  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_20_23_LEN                , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_PURGE                          , 24  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_PURGE_ABORT                    , 25  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED26                        , 26  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_RESERVED26 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 , 27  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_NCU_PURGE                         , 28  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_NCU_PURGE_ABORT                   , 29  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_CHTM_PURGE_C0                     , 30  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_CHTM_PURGE_C1                     , 31  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_HMI_REQUEST_C0                    , 32  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_HMI_REQUEST_C1                    , 33  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  , 34  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  , 35  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_36_39                    , 36  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_36_39_LEN                , 4   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PC_ENTRY_ACK_C0                   , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0            , 1   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PC_WAKEUP_C0                      , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C0 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PCBMUX_REQ_C0                     , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_4_5                      , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_4_5_LEN                  , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          , 6   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           , 7   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_8_11                     , 8   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_8_11_LEN                 , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PC_ENTRY_ACK_C1                   , 12  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1            , 13  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PC_WAKEUP_C1                      , 14  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C1 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PCBMUX_REQ_C1                     , 15  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_16_17                    , 16  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_16_17_LEN                , 2   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          , 18  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           , 19  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_20_23                    , 20  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_20_23_LEN                , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_PURGE                          , 24  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_PURGE_ABORT                    , 25  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED26                        , 26  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_RESERVED26 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 , 27  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_NCU_PURGE                         , 28  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_NCU_PURGE_ABORT                   , 29  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_CHTM_PURGE_C0                     , 30  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_CHTM_PURGE_C1                     , 31  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_HMI_REQUEST_C0                    , 32  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_HMI_REQUEST_C1                    , 33  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  , 34  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  , 35  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_36_39                    , 36  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_36_39_LEN                , 4   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PC_ENTRY_ACK_C0                   , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0            , 1   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PC_WAKEUP_C0                      , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C0 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PCBMUX_REQ_C0                     , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_4_5                      , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_4_5_LEN                  , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          , 6   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           , 7   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_8_11                     , 8   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_8_11_LEN                 , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PC_ENTRY_ACK_C1                   , 12  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1            , 13  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PC_WAKEUP_C1                      , 14  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C1 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PCBMUX_REQ_C1                     , 15  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_16_17                    , 16  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_16_17_LEN                , 2   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          , 18  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           , 19  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_20_23                    , 20  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_20_23_LEN                , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_PURGE                          , 24  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_PURGE_ABORT                    , 25  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED26                        , 26  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_RESERVED26 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 , 27  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_NCU_PURGE                         , 28  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_NCU_PURGE_ABORT                   , 29  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_CHTM_PURGE_C0                     , 30  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_CHTM_PURGE_C1                     , 31  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_HMI_REQUEST_C0                    , 32  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_HMI_REQUEST_C1                    , 33  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  , 34  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  , 35  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_36_39                    , 36  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_36_39_LEN                , 4   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PC_ENTRY_ACK_C0                  , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0           , 1   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PC_WAKEUP_C0                     , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C0 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PCBMUX_REQ_C0                    , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_4_5                     , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_4_5_LEN                 , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0         , 6   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0          , 7   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_8_11                    , 8   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_8_11_LEN                , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PC_ENTRY_ACK_C1                  , 12  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1           , 13  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PC_WAKEUP_C1                     , 14  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C1 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PCBMUX_REQ_C1                    , 15  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_16_17                   , 16  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_16_17_LEN               , 2   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1         , 18  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1          , 19  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_20_23                   , 20  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_20_23_LEN               , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_PURGE                         , 24  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_PURGE_ABORT                   , 25  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED26                       , 26  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_RESERVED26 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                , 27  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_NCU_PURGE                        , 28  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_NCU_PURGE_ABORT                  , 29  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_CHTM_PURGE_C0                    , 30  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_CHTM_PURGE_C1                    , 31  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_HMI_REQUEST_C0                   , 32  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_HMI_REQUEST_C1                   , 33  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PPM_SPARE_OUT_C0                 , 34  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PPM_SPARE_OUT_C1                 , 35  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_36_39                   , 36  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_36_39_LEN               , 4   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PC_ENTRY_ACK_C0                   , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0            , 1   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PC_WAKEUP_C0                      , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C0 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PCBMUX_REQ_C0                     , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_4_5                      , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_4_5_LEN                  , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          , 6   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           , 7   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_8_11                     , 8   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_8_11_LEN                 , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PC_ENTRY_ACK_C1                   , 12  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1            , 13  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PC_WAKEUP_C1                      , 14  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C1 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PCBMUX_REQ_C1                     , 15  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_16_17                    , 16  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_16_17_LEN                , 2   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          , 18  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           , 19  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_20_23                    , 20  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_20_23_LEN                , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_PURGE                          , 24  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_PURGE_ABORT                    , 25  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED26                        , 26  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_RESERVED26 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 , 27  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_NCU_PURGE                         , 28  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_NCU_PURGE_ABORT                   , 29  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_CHTM_PURGE_C0                     , 30  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_CHTM_PURGE_C1                     , 31  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_HMI_REQUEST_C0                    , 32  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_HMI_REQUEST_C1                    , 33  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  , 34  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  , 35  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_36_39                    , 36  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_36_39_LEN                , 4   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PC_ENTRY_ACK_C0                   , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0            , 1   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PC_WAKEUP_C0                      , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C0 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PCBMUX_REQ_C0                     , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_4_5                      , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_4_5_LEN                  , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          , 6   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           , 7   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_8_11                     , 8   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_8_11_LEN                 , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PC_ENTRY_ACK_C1                   , 12  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1            , 13  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PC_WAKEUP_C1                      , 14  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C1 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PCBMUX_REQ_C1                     , 15  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_16_17                    , 16  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_16_17_LEN                , 2   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          , 18  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           , 19  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_20_23                    , 20  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_20_23_LEN                , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_PURGE                          , 24  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_PURGE_ABORT                    , 25  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED26                        , 26  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_RESERVED26 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 , 27  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_NCU_PURGE                         , 28  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_NCU_PURGE_ABORT                   , 29  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_CHTM_PURGE_C0                     , 30  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_CHTM_PURGE_C1                     , 31  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_HMI_REQUEST_C0                    , 32  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_HMI_REQUEST_C1                    , 33  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  , 34  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  , 35  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_36_39                    , 36  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_36_39_LEN                , 4   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PC_ENTRY_ACK_C0                   , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0            , 1   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PC_WAKEUP_C0                      , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C0 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PCBMUX_REQ_C0                     , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_4_5                      , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_4_5_LEN                  , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          , 6   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           , 7   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_8_11                     , 8   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_8_11_LEN                 , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PC_ENTRY_ACK_C1                   , 12  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1            , 13  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PC_WAKEUP_C1                      , 14  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C1 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PCBMUX_REQ_C1                     , 15  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_16_17                    , 16  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_16_17_LEN                , 2   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          , 18  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           , 19  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_20_23                    , 20  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_20_23_LEN                , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_PURGE                          , 24  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_PURGE_ABORT                    , 25  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED26                        , 26  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_RESERVED26 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 , 27  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_NCU_PURGE                         , 28  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_NCU_PURGE_ABORT                   , 29  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_CHTM_PURGE_C0                     , 30  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_CHTM_PURGE_C1                     , 31  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_HMI_REQUEST_C0                    , 32  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_HMI_REQUEST_C1                    , 33  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  , 34  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  , 35  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_36_39                    , 36  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_36_39_LEN                , 4   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PC_ENTRY_ACK_C0                   , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0            , 1   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PC_WAKEUP_C0                      , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C0 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PCBMUX_REQ_C0                     , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_4_5                      , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_4_5_LEN                  , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_RESERVED_4_5_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          , 6   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           , 7   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_8_11                     , 8   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_8_11_LEN                 , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_RESERVED_8_11_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PC_ENTRY_ACK_C1                   , 12  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_PC_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1            , 13  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_PC_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PC_WAKEUP_C1                      , 14  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_PC_WAKEUP_C1 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PCBMUX_REQ_C1                     , 15  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_16_17                    , 16  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_16_17_LEN                , 2   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_RESERVED_16_17_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          , 18  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           , 19  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_20_23                    , 20  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_20_23_LEN                , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_RESERVED_20_23_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_PURGE                          , 24  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_PURGE_ABORT                    , 25  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED26                        , 26  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_RESERVED26 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 , 27  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_NCU_PURGE                         , 28  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_NCU_PURGE_ABORT                   , 29  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_CHTM_PURGE_C0                     , 30  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_CHTM_PURGE_C1                     , 31  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_HMI_REQUEST_C0                    , 32  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_HMI_REQUEST_C1                    , 33  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  , 34  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  , 35  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_36_39                    , 36  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_36_39_LEN                , 4   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE2     , SH_FLD_RESERVED_36_39_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_SRTCH0_DATA                            , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME4_CME_SCOM_SRTCH0_DATA_LEN                        , 32  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME3_CME_SCOM_SRTCH0_DATA                            , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME3_CME_SCOM_SRTCH0_DATA_LEN                        , 32  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME11_CME_SCOM_SRTCH0_DATA                           , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME11_CME_SCOM_SRTCH0_DATA_LEN                       , 32  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME2_CME_SCOM_SRTCH0_DATA                            , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME2_CME_SCOM_SRTCH0_DATA_LEN                        , 32  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME5_CME_SCOM_SRTCH0_DATA                            , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME5_CME_SCOM_SRTCH0_DATA_LEN                        , 32  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME9_CME_SCOM_SRTCH0_DATA                            , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME9_CME_SCOM_SRTCH0_DATA_LEN                        , 32  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME6_CME_SCOM_SRTCH0_DATA                            , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME6_CME_SCOM_SRTCH0_DATA_LEN                        , 32  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME10_CME_SCOM_SRTCH0_DATA                           , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME10_CME_SCOM_SRTCH0_DATA_LEN                       , 32  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME8_CME_SCOM_SRTCH0_DATA                            , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME8_CME_SCOM_SRTCH0_DATA_LEN                        , 32  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME1_CME_SCOM_SRTCH0_DATA                            , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME1_CME_SCOM_SRTCH0_DATA_LEN                        , 32  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME0_CME_SCOM_SRTCH0_DATA                            , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME0_CME_SCOM_SRTCH0_DATA_LEN                        , 32  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME7_CME_SCOM_SRTCH0_DATA                            , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME7_CME_SCOM_SRTCH0_DATA_LEN                        , 32  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME4_CME_SCOM_SRTCH1_DATA                            , 0   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME4_CME_SCOM_SRTCH1_DATA_LEN                        , 32  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME3_CME_SCOM_SRTCH1_DATA                            , 0   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME3_CME_SCOM_SRTCH1_DATA_LEN                        , 32  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME11_CME_SCOM_SRTCH1_DATA                           , 0   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME11_CME_SCOM_SRTCH1_DATA_LEN                       , 32  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME2_CME_SCOM_SRTCH1_DATA                            , 0   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME2_CME_SCOM_SRTCH1_DATA_LEN                        , 32  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME5_CME_SCOM_SRTCH1_DATA                            , 0   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME5_CME_SCOM_SRTCH1_DATA_LEN                        , 32  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME9_CME_SCOM_SRTCH1_DATA                            , 0   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME9_CME_SCOM_SRTCH1_DATA_LEN                        , 32  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME6_CME_SCOM_SRTCH1_DATA                            , 0   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME6_CME_SCOM_SRTCH1_DATA_LEN                        , 32  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME10_CME_SCOM_SRTCH1_DATA                           , 0   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME10_CME_SCOM_SRTCH1_DATA_LEN                       , 32  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME8_CME_SCOM_SRTCH1_DATA                            , 0   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME8_CME_SCOM_SRTCH1_DATA_LEN                        , 32  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME1_CME_SCOM_SRTCH1_DATA                            , 0   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME1_CME_SCOM_SRTCH1_DATA_LEN                        , 32  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME0_CME_SCOM_SRTCH1_DATA                            , 0   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME0_CME_SCOM_SRTCH1_DATA_LEN                        , 32  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME7_CME_SCOM_SRTCH1_DATA                            , 0   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_DATA       );
+REG64_FLD( PU_CME7_CME_SCOM_SRTCH1_DATA_LEN                        , 32  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       , 1   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            , 5   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            , 9   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            , 13  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            , 17  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            , 21  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        , 33  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             , 37  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             , 41  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             , 45  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             , 49  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             , 53  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       , 1   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            , 5   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            , 9   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            , 13  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            , 17  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            , 21  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        , 33  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             , 37  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             , 41  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             , 45  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             , 49  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             , 53  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY      , 1   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN  , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA           , 5   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN       , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA           , 9   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN       , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA           , 13  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN       , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA           , 17  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN       , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA           , 21  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN       , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY       , 33  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN   , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA            , 37  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA            , 41  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA            , 45  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA            , 49  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA            , 53  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       , 1   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            , 5   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            , 9   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            , 13  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            , 17  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            , 21  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        , 33  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             , 37  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             , 41  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             , 45  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             , 49  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             , 53  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       , 1   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            , 5   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            , 9   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            , 13  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            , 17  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            , 21  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        , 33  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             , 37  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             , 41  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             , 45  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             , 49  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             , 53  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       , 1   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            , 5   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            , 9   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            , 13  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            , 17  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            , 21  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        , 33  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             , 37  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             , 41  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             , 45  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             , 49  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             , 53  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       , 1   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            , 5   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            , 9   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            , 13  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            , 17  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            , 21  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        , 33  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             , 37  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             , 41  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             , 45  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             , 49  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             , 53  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY      , 1   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN  , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA           , 5   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN       , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA           , 9   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN       , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA           , 13  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN       , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA           , 17  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN       , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA           , 21  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN       , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY       , 33  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN   , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA            , 37  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA            , 41  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA            , 45  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA            , 49  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA            , 53  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       , 1   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            , 5   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            , 9   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            , 13  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            , 17  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            , 21  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        , 33  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             , 37  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             , 41  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             , 45  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             , 49  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             , 53  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       , 1   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            , 5   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            , 9   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            , 13  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            , 17  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            , 21  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        , 33  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             , 37  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             , 41  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             , 45  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             , 49  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             , 53  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       , 1   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            , 5   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            , 9   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            , 13  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            , 17  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            , 21  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        , 33  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             , 37  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             , 41  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             , 45  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             , 49  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             , 53  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       , 1   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            , 5   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            , 9   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            , 13  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            , 17  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            , 21  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        , 33  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             , 37  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             , 41  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             , 45  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             , 49  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             , 53  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         , 3   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR              , 8   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME4_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN          , 24  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR              , 40  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME4_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN          , 24  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR              , 8   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME3_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN          , 24  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR              , 40  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME3_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN          , 24  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR             , 8   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME11_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN         , 24  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR             , 40  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME11_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN         , 24  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR              , 8   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME2_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN          , 24  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR              , 40  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME2_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN          , 24  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR              , 8   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME5_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN          , 24  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR              , 40  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME5_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN          , 24  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR              , 8   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME9_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN          , 24  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR              , 40  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME9_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN          , 24  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR              , 8   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME6_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN          , 24  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR              , 40  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME6_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN          , 24  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR             , 8   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME10_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN         , 24  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR             , 40  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME10_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN         , 24  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR              , 8   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME8_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN          , 24  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR              , 40  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME8_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN          , 24  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR              , 8   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME1_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN          , 24  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR              , 40  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME1_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN          , 24  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR              , 8   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME0_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN          , 24  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR              , 40  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME0_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN          , 24  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR              , 8   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME7_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN          , 24  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR              , 40  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME7_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN          , 24  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR                 , 8   ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME4_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN             , 24  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR                 , 40  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME4_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN             , 24  ,
+           SH_UNT_PU_CME4  , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR                 , 8   ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME3_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN             , 24  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR                 , 40  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME3_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN             , 24  ,
+           SH_UNT_PU_CME3  , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR                , 8   ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME11_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN            , 24  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR                , 40  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME11_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN            , 24  ,
+           SH_UNT_PU_CME11 , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR                 , 8   ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME2_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN             , 24  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR                 , 40  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME2_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN             , 24  ,
+           SH_UNT_PU_CME2  , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR                 , 8   ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME5_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN             , 24  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR                 , 40  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME5_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN             , 24  ,
+           SH_UNT_PU_CME5  , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR                 , 8   ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME9_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN             , 24  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR                 , 40  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME9_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN             , 24  ,
+           SH_UNT_PU_CME9  , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR                 , 8   ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME6_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN             , 24  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR                 , 40  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME6_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN             , 24  ,
+           SH_UNT_PU_CME6  , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR                , 8   ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME10_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN            , 24  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR                , 40  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME10_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN            , 24  ,
+           SH_UNT_PU_CME10 , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR                 , 8   ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME8_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN             , 24  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR                 , 40  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME8_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN             , 24  ,
+           SH_UNT_PU_CME8  , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR                 , 8   ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME1_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN             , 24  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR                 , 40  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME1_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN             , 24  ,
+           SH_UNT_PU_CME1  , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR                 , 8   ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME0_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN             , 24  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR                 , 40  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME0_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN             , 24  ,
+           SH_UNT_PU_CME0  , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR                 , 8   ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME7_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN             , 24  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR                 , 40  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME7_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN             , 24  ,
+           SH_UNT_PU_CME7  , SH_ACS_PPE      , SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_BIT_WITHSTART               , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMD_REG_BIT_WITHSTART );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_BIT_WITHADDR                , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMD_REG_BIT_WITHADDR );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_BIT_READCONT                , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMD_REG_BIT_READCONT );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_BIT_WITHSTOP                , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMD_REG_BIT_WITHSTOP );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_LENGTH                      , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMD_REG_LENGTH );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_LENGTH_LEN                  , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMD_REG_LENGTH_LEN );
+REG32_FLD( PU_COMMAND_REGISTER_UNUSED_8_14                         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED_8_14 );
+REG32_FLD( PU_COMMAND_REGISTER_UNUSED_8_14_LEN                     , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED_8_14_LEN );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_BIT_RNW                     , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMD_REG_BIT_RNW );
+REG32_FLD( PU_COMMAND_REGISTER_UNUSED_16_22                        , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED_16_22 );
+REG32_FLD( PU_COMMAND_REGISTER_UNUSED_16_22_LEN                    , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED_16_22_LEN );
+REG32_FLD( PU_COMMAND_REGISTER_REG_ADDR_LEN                        , 23  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REG_ADDR_LEN );
+REG32_FLD( PU_COMMAND_REGISTER_REG_ADDR_LEN_LEN                    , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REG_ADDR_LEN_LEN );
+REG32_FLD( PU_COMMAND_REGISTER_UNUSED_26_31                        , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED_26_31 );
+REG32_FLD( PU_COMMAND_REGISTER_UNUSED_26_31_LEN                    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED_26_31_LEN );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_1                      , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMD_REG_ADDR_1 );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_1_LEN                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMD_REG_ADDR_1_LEN );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_2                      , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMD_REG_ADDR_2 );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_2_LEN                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMD_REG_ADDR_2_LEN );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_3                      , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMD_REG_ADDR_3 );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_3_LEN                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMD_REG_ADDR_3_LEN );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_4                      , 56  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMD_REG_ADDR_4 );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_4_LEN                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMD_REG_ADDR_4_LEN );
+
+REG64_FLD( PU_COMMAND_REGISTER_B_WITH_START_0                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WITH_START_0 );
+REG64_FLD( PU_COMMAND_REGISTER_B_WITH_ADDRESS_0                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WITH_ADDRESS_0 );
+REG64_FLD( PU_COMMAND_REGISTER_B_READ_CONTINUE_0                   , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_READ_CONTINUE_0 );
+REG64_FLD( PU_COMMAND_REGISTER_B_WITH_STOP_0                       , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WITH_STOP_0 );
+REG64_FLD( PU_COMMAND_REGISTER_B_NOT_USED_0                        , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NOT_USED_0 );
+REG64_FLD( PU_COMMAND_REGISTER_B_NOT_USED_0_LEN                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NOT_USED_0_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_B_DEVICE_ADDRESS_0                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DEVICE_ADDRESS_0 );
+REG64_FLD( PU_COMMAND_REGISTER_B_DEVICE_ADDRESS_0_LEN              , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DEVICE_ADDRESS_0_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_B_READ_NOT_WRITE_0                  , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_READ_NOT_WRITE_0 );
+REG64_FLD( PU_COMMAND_REGISTER_B_LENGTH_IN_BYTES_0                 , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LENGTH_IN_BYTES_0 );
+REG64_FLD( PU_COMMAND_REGISTER_B_LENGTH_IN_BYTES_0_LEN             , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LENGTH_IN_BYTES_0_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_B_PEEK_DATA1_0                      , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_COMMAND_REGISTER_B_PEEK_DATA1_0_LEN                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_B_LBUS_PARITY_ERR1_0                , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_COMMAND_REGISTER_C_WITH_START_1                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WITH_START_1 );
+REG64_FLD( PU_COMMAND_REGISTER_C_WITH_ADDRESS_1                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WITH_ADDRESS_1 );
+REG64_FLD( PU_COMMAND_REGISTER_C_READ_CONTINUE_1                   , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_READ_CONTINUE_1 );
+REG64_FLD( PU_COMMAND_REGISTER_C_WITH_STOP_1                       , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WITH_STOP_1 );
+REG64_FLD( PU_COMMAND_REGISTER_C_NOT_USED_1                        , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NOT_USED_1 );
+REG64_FLD( PU_COMMAND_REGISTER_C_NOT_USED_1_LEN                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NOT_USED_1_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_C_DEVICE_ADDRESS_1                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DEVICE_ADDRESS_1 );
+REG64_FLD( PU_COMMAND_REGISTER_C_DEVICE_ADDRESS_1_LEN              , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DEVICE_ADDRESS_1_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_C_READ_NOT_WRITE_1                  , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_READ_NOT_WRITE_1 );
+REG64_FLD( PU_COMMAND_REGISTER_C_LENGTH_IN_BYTES_1                 , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LENGTH_IN_BYTES_1 );
+REG64_FLD( PU_COMMAND_REGISTER_C_LENGTH_IN_BYTES_1_LEN             , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LENGTH_IN_BYTES_1_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_C_PEEK_DATA1_1                      , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_COMMAND_REGISTER_C_PEEK_DATA1_1_LEN                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_C_LBUS_PARITY_ERR1_1                , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_COMMAND_REGISTER_D_WITH_START_2                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WITH_START_2 );
+REG64_FLD( PU_COMMAND_REGISTER_D_WITH_ADDRESS_2                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WITH_ADDRESS_2 );
+REG64_FLD( PU_COMMAND_REGISTER_D_READ_CONTINUE_2                   , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_READ_CONTINUE_2 );
+REG64_FLD( PU_COMMAND_REGISTER_D_WITH_STOP_2                       , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WITH_STOP_2 );
+REG64_FLD( PU_COMMAND_REGISTER_D_NOT_USED_2                        , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NOT_USED_2 );
+REG64_FLD( PU_COMMAND_REGISTER_D_NOT_USED_2_LEN                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NOT_USED_2_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_D_DEVICE_ADDRESS_2                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DEVICE_ADDRESS_2 );
+REG64_FLD( PU_COMMAND_REGISTER_D_DEVICE_ADDRESS_2_LEN              , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DEVICE_ADDRESS_2_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_D_READ_NOT_WRITE_2                  , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_READ_NOT_WRITE_2 );
+REG64_FLD( PU_COMMAND_REGISTER_D_LENGTH_IN_BYTES_2                 , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LENGTH_IN_BYTES_2 );
+REG64_FLD( PU_COMMAND_REGISTER_D_LENGTH_IN_BYTES_2_LEN             , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LENGTH_IN_BYTES_2_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_D_PEEK_DATA1_2                      , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_COMMAND_REGISTER_D_PEEK_DATA1_2_LEN                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_D_LBUS_PARITY_ERR1_2                , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_COMMAND_REGISTER_E_WITH_START_3                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WITH_START_3 );
+REG64_FLD( PU_COMMAND_REGISTER_E_WITH_ADDRESS_3                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WITH_ADDRESS_3 );
+REG64_FLD( PU_COMMAND_REGISTER_E_READ_CONTINUE_3                   , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_READ_CONTINUE_3 );
+REG64_FLD( PU_COMMAND_REGISTER_E_WITH_STOP_3                       , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WITH_STOP_3 );
+REG64_FLD( PU_COMMAND_REGISTER_E_NOT_USED_3                        , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NOT_USED_3 );
+REG64_FLD( PU_COMMAND_REGISTER_E_NOT_USED_3_LEN                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NOT_USED_3_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_E_DEVICE_ADDRESS_3                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DEVICE_ADDRESS_3 );
+REG64_FLD( PU_COMMAND_REGISTER_E_DEVICE_ADDRESS_3_LEN              , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DEVICE_ADDRESS_3_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_E_READ_NOT_WRITE_3                  , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_READ_NOT_WRITE_3 );
+REG64_FLD( PU_COMMAND_REGISTER_E_LENGTH_IN_BYTES_3                 , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LENGTH_IN_BYTES_3 );
+REG64_FLD( PU_COMMAND_REGISTER_E_LENGTH_IN_BYTES_3_LEN             , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LENGTH_IN_BYTES_3_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_E_PEEK_DATA1_3                      , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_COMMAND_REGISTER_E_PEEK_DATA1_3_LEN                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_E_LBUS_PARITY_ERR1_3                , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG1_RESERVED1                   , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_G                    , 7   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_LN                   , 8   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_SKIP_G                       , 9   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG1_RESERVED2                   , 16  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RESERVED4                    , 22  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MACH_CORRENAB                , 23  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_RESERVED3                           , 41  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_RESERVED3_LEN                       , 23  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG1_RESERVED1                   , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_DISABLE_G                    , 7   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_DISABLE_LN                   , 8   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_SKIP_G                       , 9   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG1_RESERVED2                   , 16  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RESERVED4                    , 22  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MACH_CORRENAB                , 23  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_RESERVED3                           , 41  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_RESERVED3_LEN                       , 23  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG1_RESERVED1                   , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_G                    , 7   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_LN                   , 8   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_SKIP_G                       , 9   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG1_RESERVED2                   , 16  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RESERVED4                    , 22  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MACH_CORRENAB                , 23  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_RESERVED3                           , 41  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_RESERVED3_LEN                       , 23  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG1_RESERVED1                   , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_DISABLE_G                    , 7   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_DISABLE_LN                   , 8   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_SKIP_G                       , 9   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG1_RESERVED2                   , 16  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RESERVED4                    , 22  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MACH_CORRENAB                , 23  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_RESERVED3                           , 41  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_RESERVED3_LEN                       , 23  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG1_RESERVED1                   , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_G                    , 7   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_LN                   , 8   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_SKIP_G                       , 9   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG1_RESERVED2                   , 16  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RESERVED4                    , 22  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MACH_CORRENAB                , 23  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_RESERVED3                           , 41  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_RESERVED3_LEN                       , 23  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG1_RESERVED1                   , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_DISABLE_G                    , 7   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_DISABLE_LN                   , 8   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_SKIP_G                       , 9   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG1_RESERVED2                   , 16  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RESERVED4                    , 22  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MACH_CORRENAB                , 23  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_RESERVED3                           , 41  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_RESERVED3_LEN                       , 23  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG1_RESERVED1                   , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_DISABLE_G                    , 7   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_DISABLE_LN                   , 8   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_SKIP_G                       , 9   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG1_RESERVED2                   , 16  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RESERVED4                    , 22  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MACH_CORRENAB                , 23  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_RESERVED3                           , 41  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_RESERVED3_LEN                       , 23  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED0                   , 0   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED0 );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED1                   , 1   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED1_LEN               , 3   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_GEN_HEAD_DELAY               , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_GEN_HEAD_DELAY );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_GEN_HEAD_DELAY_LEN           , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_GEN_HEAD_DELAY_LEN );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_DIV2_COUNT_AT_EXP      , 10  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_DIV2_COUNT_AT_EXP );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_DIV2_COUNT_AT_EXP      , 11  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_DIV2_COUNT_AT_EXP );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_DIS_DYN_ADJ            , 12  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_DIS_DYN_ADJ );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_DIS_DYN_ADJ            , 13  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_DIS_DYN_ADJ );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_DIS_DYN_LVL_ADJ        , 14  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_DIS_DYN_LVL_ADJ );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_DIS_DYN_LVL_ADJ        , 15  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_DIS_DYN_LVL_ADJ );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_THRESH1                , 16  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_THRESH1 );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_THRESH1_LEN            , 6   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_THRESH1_LEN );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_THRESH2                , 22  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_THRESH2 );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_THRESH2_LEN            , 6   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_THRESH2_LEN );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_THRESH1                , 28  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_THRESH1 );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_THRESH1_LEN            , 6   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_THRESH1_LEN );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_THRESH2                , 34  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_THRESH2 );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_THRESH2_LEN            , 6   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_THRESH2_LEN );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_MAX_LEVEL              , 40  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_MAX_LEVEL );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_MAX_LEVEL_LEN          , 4   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_MAX_LEVEL_LEN );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_MAX_LEVEL              , 44  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_MAX_LEVEL );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_MAX_LEVEL_LEN          , 4   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_MAX_LEVEL_LEN );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_BRAZOS_MODE                  , 48  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED2                   , 49  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED2_LEN               , 15  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG1_RESERVED1                   , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_G                    , 7   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_LN                   , 8   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_SKIP_G                       , 9   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG1_RESERVED2                   , 16  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RESERVED4                    , 22  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MACH_CORRENAB                , 23  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_RESERVED3                           , 41  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_RESERVED3_LEN                       , 23  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG1_RESERVED1                   , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_DISABLE_G                    , 7   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_DISABLE_LN                   , 8   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_SKIP_G                       , 9   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG1_RESERVED2                   , 16  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RESERVED4                    , 22  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MACH_CORRENAB                , 23  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_RESERVED3                           , 41  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_RESERVED3_LEN                       , 23  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG1_RESERVED1                   , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_G                    , 7   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_LN                   , 8   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_SKIP_G                       , 9   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG1_RESERVED2                   , 16  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RESERVED4                    , 22  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MACH_CORRENAB                , 23  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_RESERVED3                           , 41  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_RESERVED3_LEN                       , 23  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED0                   , 0   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED0 );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED1                   , 1   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED1_LEN               , 3   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_GEN_HEAD_DELAY               , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_GEN_HEAD_DELAY );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_GEN_HEAD_DELAY_LEN           , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_GEN_HEAD_DELAY_LEN );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_DIV2_COUNT_AT_EXP      , 10  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_DIV2_COUNT_AT_EXP );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_DIV2_COUNT_AT_EXP      , 11  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_DIV2_COUNT_AT_EXP );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_DIS_DYN_ADJ            , 12  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_DIS_DYN_ADJ );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_DIS_DYN_ADJ            , 13  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_DIS_DYN_ADJ );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_DIS_DYN_LVL_ADJ        , 14  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_DIS_DYN_LVL_ADJ );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_DIS_DYN_LVL_ADJ        , 15  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_DIS_DYN_LVL_ADJ );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_THRESH1                , 16  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_THRESH1 );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_THRESH1_LEN            , 6   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_THRESH1_LEN );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_THRESH2                , 22  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_THRESH2 );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_THRESH2_LEN            , 6   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_THRESH2_LEN );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_THRESH1                , 28  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_THRESH1 );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_THRESH1_LEN            , 6   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_THRESH1_LEN );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_THRESH2                , 34  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_THRESH2 );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_THRESH2_LEN            , 6   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_THRESH2_LEN );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_MAX_LEVEL              , 40  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_MAX_LEVEL );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_MAX_LEVEL_LEN          , 4   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_MAX_LEVEL_LEN );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_MAX_LEVEL              , 44  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_MAX_LEVEL );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_MAX_LEVEL_LEN          , 4   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_MAX_LEVEL_LEN );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_BRAZOS_MODE                  , 48  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED2                   , 49  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED2_LEN               , 15  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED0                   , 0   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED0 );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED1                   , 1   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED1_LEN               , 3   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_GEN_HEAD_DELAY               , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_GEN_HEAD_DELAY );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_GEN_HEAD_DELAY_LEN           , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_GEN_HEAD_DELAY_LEN );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_DIV2_COUNT_AT_EXP      , 10  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_DIV2_COUNT_AT_EXP );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_DIV2_COUNT_AT_EXP      , 11  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_DIV2_COUNT_AT_EXP );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_DIS_DYN_ADJ            , 12  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_DIS_DYN_ADJ );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_DIS_DYN_ADJ            , 13  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_DIS_DYN_ADJ );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_DIS_DYN_LVL_ADJ        , 14  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_DIS_DYN_LVL_ADJ );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_DIS_DYN_LVL_ADJ        , 15  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_DIS_DYN_LVL_ADJ );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_THRESH1                , 16  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_THRESH1 );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_THRESH1_LEN            , 6   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_THRESH1_LEN );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_THRESH2                , 22  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_THRESH2 );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_THRESH2_LEN            , 6   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_THRESH2_LEN );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_THRESH1                , 28  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_THRESH1 );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_THRESH1_LEN            , 6   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_THRESH1_LEN );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_THRESH2                , 34  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_THRESH2 );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_THRESH2_LEN            , 6   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_THRESH2_LEN );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_MAX_LEVEL              , 40  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_MAX_LEVEL );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_MAX_LEVEL_LEN          , 4   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_MAX_LEVEL_LEN );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_MAX_LEVEL              , 44  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_MAX_LEVEL );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_MAX_LEVEL_LEN          , 4   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_MAX_LEVEL_LEN );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_BRAZOS_MODE                  , 48  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED2                   , 49  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED2_LEN               , 15  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG1_RESERVED1                   , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_G                    , 7   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_LN                   , 8   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_SKIP_G                       , 9   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG1_RESERVED2                   , 16  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RESERVED4                    , 22  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MACH_CORRENAB                , 23  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_RESERVED3                           , 41  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_RESERVED3_LEN                       , 23  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG1_RESERVED1                   , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_DISABLE_G                    , 7   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_DISABLE_LN                   , 8   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_SKIP_G                       , 9   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG1_RESERVED2                   , 16  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RESERVED4                    , 22  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MACH_CORRENAB                , 23  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_RESERVED3                           , 41  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_RESERVED3_LEN                       , 23  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN        , 4   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN );
+REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN    , 4   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN );
+REG64_FLD( PU_NPU1_SM2_CONFIG1_RESERVED                            , 8   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU1_SM2_CONFIG1_RESERVED_LEN                        , 56  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU1_NTL0_CONFIG1_COMPRESSED_RSP_ENA                 , 0   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_COMPRESSED_RSP_ENA );
+REG64_FLD( PU_NPU1_NTL0_CONFIG1_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_NTL0_CONFIG1_RESERVED1_LEN                      , 3   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_NTL0_CONFIG1_CREQ_AE_ALWAYS                     , 4   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_CREQ_AE_ALWAYS );
+REG64_FLD( PU_NPU1_NTL0_CONFIG1_DGD_AE_ALWAYS                      , 5   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_DGD_AE_ALWAYS );
+REG64_FLD( PU_NPU1_NTL0_CONFIG1_RSP_AE_ALWAYS                      , 6   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_RSP_AE_ALWAYS );
+REG64_FLD( PU_NPU1_NTL0_CONFIG1_RESERVED2                          , 7   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU1_NTL0_CONFIG1_RESERVED2_LEN                      , 57  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN        , 4   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN );
+REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN    , 4   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN );
+REG64_FLD( PU_NPU1_SM3_CONFIG1_RESERVED                            , 8   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU1_SM3_CONFIG1_RESERVED_LEN                        , 56  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU1_NTL1_CONFIG1_COMPRESSED_RSP_ENA                 , 0   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_COMPRESSED_RSP_ENA );
+REG64_FLD( PU_NPU1_NTL1_CONFIG1_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_NTL1_CONFIG1_RESERVED1_LEN                      , 3   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_NTL1_CONFIG1_CREQ_AE_ALWAYS                     , 4   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_CREQ_AE_ALWAYS );
+REG64_FLD( PU_NPU1_NTL1_CONFIG1_DGD_AE_ALWAYS                      , 5   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_DGD_AE_ALWAYS );
+REG64_FLD( PU_NPU1_NTL1_CONFIG1_RSP_AE_ALWAYS                      , 6   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_RSP_AE_ALWAYS );
+REG64_FLD( PU_NPU1_NTL1_CONFIG1_RESERVED2                          , 7   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU1_NTL1_CONFIG1_RESERVED2_LEN                      , 57  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU2_NTL1_CONFIG1_COMPRESSED_RSP_ENA                 , 0   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_COMPRESSED_RSP_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG1_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL1_CONFIG1_RESERVED1_LEN                      , 3   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL1_CONFIG1_CREQ_AE_ALWAYS                     , 4   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_CREQ_AE_ALWAYS );
+REG64_FLD( PU_NPU2_NTL1_CONFIG1_DGD_AE_ALWAYS                      , 5   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_DGD_AE_ALWAYS );
+REG64_FLD( PU_NPU2_NTL1_CONFIG1_RSP_AE_ALWAYS                      , 6   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_RSP_AE_ALWAYS );
+REG64_FLD( PU_NPU2_NTL1_CONFIG1_RESERVED2                          , 7   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_NTL1_CONFIG1_RESERVED2_LEN                      , 57  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN        , 4   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN );
+REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN    , 4   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN );
+REG64_FLD( PU_NPU1_SM1_CONFIG1_RESERVED                            , 8   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU1_SM1_CONFIG1_RESERVED_LEN                        , 56  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU0_NTL1_CONFIG1_COMPRESSED_RSP_ENA                 , 0   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_COMPRESSED_RSP_ENA );
+REG64_FLD( PU_NPU0_NTL1_CONFIG1_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_NTL1_CONFIG1_RESERVED1_LEN                      , 3   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_NTL1_CONFIG1_CREQ_AE_ALWAYS                     , 4   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_CREQ_AE_ALWAYS );
+REG64_FLD( PU_NPU0_NTL1_CONFIG1_DGD_AE_ALWAYS                      , 5   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_DGD_AE_ALWAYS );
+REG64_FLD( PU_NPU0_NTL1_CONFIG1_RSP_AE_ALWAYS                      , 6   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_RSP_AE_ALWAYS );
+REG64_FLD( PU_NPU0_NTL1_CONFIG1_RESERVED2                          , 7   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU0_NTL1_CONFIG1_RESERVED2_LEN                      , 57  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN        , 4   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN );
+REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN    , 4   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN );
+REG64_FLD( PU_NPU0_SM2_CONFIG1_RESERVED                            , 8   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU0_SM2_CONFIG1_RESERVED_LEN                        , 56  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU0_CTL_CONFIG1_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_CTL_CONFIG1_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN        , 4   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN );
+REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN    , 4   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN );
+REG64_FLD( PU_NPU0_SM1_CONFIG1_RESERVED                            , 8   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU0_SM1_CONFIG1_RESERVED_LEN                        , 56  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU2_DAT_CONFIG1_MGR_CREDIT                          , 0   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_MGR_CREDIT );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_MGR_CREDIT_LEN                      , 2   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_MGR_CREDIT_LEN );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_PBTX_NBUF                       , 2   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_MRG_PBTX_NBUF );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_PBTX_NBUF_LEN                   , 3   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_MRG_PBTX_NBUF_LEN );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_RDBF_NBUF                       , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_MRG_RDBF_NBUF );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_RDBF_NBUF_LEN                   , 4   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_MRG_RDBF_NBUF_LEN );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_IBWR_NBUF                       , 9   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_MRG_IBWR_NBUF );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_IBWR_NBUF_LEN                   , 4   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_MRG_IBWR_NBUF_LEN );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_IBRD_NBUF                       , 13  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_MRG_IBRD_NBUF );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_IBRD_NBUF_LEN                   , 3   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_MRG_IBRD_NBUF_LEN );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_BBRD_NBUF                       , 16  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_MRG_BBRD_NBUF );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_BBRD_NBUF_LEN                   , 3   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_MRG_BBRD_NBUF_LEN );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_OBRD_NBUF                       , 19  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_MRG_OBRD_NBUF );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_OBRD_NBUF_LEN                   , 3   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_MRG_OBRD_NBUF_LEN );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_CR_DIS                          , 22  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_MRG_CR_DIS );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_CTLW_CR_DIS                     , 23  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_MRG_CTLW_CR_DIS );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_NTLR_PAUSE_THRESH                   , 24  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_NTLR_PAUSE_THRESH );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_NTLR_PAUSE_THRESH_LEN               , 2   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_NTLR_PAUSE_THRESH_LEN );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_CTLR_HP_THRESH                      , 26  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_CTLR_HP_THRESH );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_CTLR_HP_THRESH_LEN                  , 2   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_CTLR_HP_THRESH_LEN );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_NTLW_PAUSE_THRESH                   , 28  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_NTLW_PAUSE_THRESH );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_NTLW_PAUSE_THRESH_LEN               , 2   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_NTLW_PAUSE_THRESH_LEN );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_CTLW_HP_THRESH                      , 30  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_CTLW_HP_THRESH );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_CTLW_HP_THRESH_LEN                  , 2   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_CTLW_HP_THRESH_LEN );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_PBTX_REDUCE_RTAG                    , 32  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_PBTX_REDUCE_RTAG );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_PBTX_DELAY_BDONE                    , 33  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_PBTX_DELAY_BDONE );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_PBTX_FLIP_IMIN_BIG                  , 34  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_PBTX_FLIP_IMIN_BIG );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_PBTX_FLIP_IMIN_LITTLE               , 35  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_PBTX_FLIP_IMIN_LITTLE );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_ALU_SAFE_LATENCY                    , 36  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_ALU_SAFE_LATENCY );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_ALU_FLIP_ENDIAN_BIG                 , 37  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_ALU_FLIP_ENDIAN_BIG );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_ALU_FLIP_ENDIAN_LITTLE              , 38  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_ALU_FLIP_ENDIAN_LITTLE );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_RESERVED1                           , 39  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_DAT_CONFIG1_RESERVED1_LEN                       , 25  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU0_DAT_CONFIG1_MGR_CREDIT                          , 0   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_MGR_CREDIT );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_MGR_CREDIT_LEN                      , 2   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_MGR_CREDIT_LEN );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_PBTX_NBUF                       , 2   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_MRG_PBTX_NBUF );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_PBTX_NBUF_LEN                   , 3   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_MRG_PBTX_NBUF_LEN );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_RDBF_NBUF                       , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_MRG_RDBF_NBUF );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_RDBF_NBUF_LEN                   , 4   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_MRG_RDBF_NBUF_LEN );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_IBWR_NBUF                       , 9   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_MRG_IBWR_NBUF );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_IBWR_NBUF_LEN                   , 4   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_MRG_IBWR_NBUF_LEN );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_IBRD_NBUF                       , 13  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_MRG_IBRD_NBUF );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_IBRD_NBUF_LEN                   , 3   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_MRG_IBRD_NBUF_LEN );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_BBRD_NBUF                       , 16  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_MRG_BBRD_NBUF );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_BBRD_NBUF_LEN                   , 3   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_MRG_BBRD_NBUF_LEN );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_OBRD_NBUF                       , 19  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_MRG_OBRD_NBUF );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_OBRD_NBUF_LEN                   , 3   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_MRG_OBRD_NBUF_LEN );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_CR_DIS                          , 22  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_MRG_CR_DIS );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_CTLW_CR_DIS                     , 23  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_MRG_CTLW_CR_DIS );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_NTLR_PAUSE_THRESH                   , 24  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_NTLR_PAUSE_THRESH );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_NTLR_PAUSE_THRESH_LEN               , 2   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_NTLR_PAUSE_THRESH_LEN );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_CTLR_HP_THRESH                      , 26  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_CTLR_HP_THRESH );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_CTLR_HP_THRESH_LEN                  , 2   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_CTLR_HP_THRESH_LEN );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_NTLW_PAUSE_THRESH                   , 28  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_NTLW_PAUSE_THRESH );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_NTLW_PAUSE_THRESH_LEN               , 2   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_NTLW_PAUSE_THRESH_LEN );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_CTLW_HP_THRESH                      , 30  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_CTLW_HP_THRESH );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_CTLW_HP_THRESH_LEN                  , 2   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_CTLW_HP_THRESH_LEN );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_PBTX_REDUCE_RTAG                    , 32  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_PBTX_REDUCE_RTAG );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_PBTX_DELAY_BDONE                    , 33  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_PBTX_DELAY_BDONE );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_PBTX_FLIP_IMIN_BIG                  , 34  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_PBTX_FLIP_IMIN_BIG );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_PBTX_FLIP_IMIN_LITTLE               , 35  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_PBTX_FLIP_IMIN_LITTLE );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_ALU_SAFE_LATENCY                    , 36  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_ALU_SAFE_LATENCY );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_ALU_FLIP_ENDIAN_BIG                 , 37  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_ALU_FLIP_ENDIAN_BIG );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_ALU_FLIP_ENDIAN_LITTLE              , 38  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_ALU_FLIP_ENDIAN_LITTLE );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_RESERVED1                           , 39  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_DAT_CONFIG1_RESERVED1_LEN                       , 25  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU0_NTL0_CONFIG1_COMPRESSED_RSP_ENA                 , 0   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_COMPRESSED_RSP_ENA );
+REG64_FLD( PU_NPU0_NTL0_CONFIG1_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_NTL0_CONFIG1_RESERVED1_LEN                      , 3   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_NTL0_CONFIG1_CREQ_AE_ALWAYS                     , 4   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_CREQ_AE_ALWAYS );
+REG64_FLD( PU_NPU0_NTL0_CONFIG1_DGD_AE_ALWAYS                      , 5   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_DGD_AE_ALWAYS );
+REG64_FLD( PU_NPU0_NTL0_CONFIG1_RSP_AE_ALWAYS                      , 6   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_RSP_AE_ALWAYS );
+REG64_FLD( PU_NPU0_NTL0_CONFIG1_RESERVED2                          , 7   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU0_NTL0_CONFIG1_RESERVED2_LEN                      , 57  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN        , 4   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN );
+REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN    , 4   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN );
+REG64_FLD( PU_NPU0_SM0_CONFIG1_RESERVED                            , 8   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU0_SM0_CONFIG1_RESERVED_LEN                        , 56  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU2_NTL0_CONFIG1_COMPRESSED_RSP_ENA                 , 0   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_COMPRESSED_RSP_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG1_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL0_CONFIG1_RESERVED1_LEN                      , 3   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL0_CONFIG1_CREQ_AE_ALWAYS                     , 4   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_CREQ_AE_ALWAYS );
+REG64_FLD( PU_NPU2_NTL0_CONFIG1_DGD_AE_ALWAYS                      , 5   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_DGD_AE_ALWAYS );
+REG64_FLD( PU_NPU2_NTL0_CONFIG1_RSP_AE_ALWAYS                      , 6   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_RSP_AE_ALWAYS );
+REG64_FLD( PU_NPU2_NTL0_CONFIG1_RESERVED2                          , 7   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_NTL0_CONFIG1_RESERVED2_LEN                      , 57  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN        , 4   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN );
+REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN    , 4   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN );
+REG64_FLD( PU_NPU2_SM3_CONFIG1_RESERVED                            , 8   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_SM3_CONFIG1_RESERVED_LEN                        , 56  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN        , 4   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN );
+REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN    , 4   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN );
+REG64_FLD( PU_NPU0_SM3_CONFIG1_RESERVED                            , 8   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU0_SM3_CONFIG1_RESERVED_LEN                        , 56  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN        , 4   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN );
+REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN    , 4   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN );
+REG64_FLD( PU_NPU2_SM2_CONFIG1_RESERVED                            , 8   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_SM2_CONFIG1_RESERVED_LEN                        , 56  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU1_CTL_CONFIG1_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_CTL_CONFIG1_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN        , 4   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN );
+REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN    , 4   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN );
+REG64_FLD( PU_NPU2_SM1_CONFIG1_RESERVED                            , 8   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_SM1_CONFIG1_RESERVED_LEN                        , 56  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN        , 4   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN );
+REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN    , 4   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN );
+REG64_FLD( PU_NPU2_SM0_CONFIG1_RESERVED                            , 8   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_SM0_CONFIG1_RESERVED_LEN                        , 56  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU2_CTL_CONFIG1_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_CTL_CONFIG1_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN        , 4   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN );
+REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN    , 4   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN );
+REG64_FLD( PU_NPU1_SM0_CONFIG1_RESERVED                            , 8   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU1_SM0_CONFIG1_RESERVED_LEN                        , 56  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU1_DAT_CONFIG1_MGR_CREDIT                          , 0   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_MGR_CREDIT );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_MGR_CREDIT_LEN                      , 2   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_MGR_CREDIT_LEN );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_PBTX_NBUF                       , 2   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_MRG_PBTX_NBUF );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_PBTX_NBUF_LEN                   , 3   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_MRG_PBTX_NBUF_LEN );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_RDBF_NBUF                       , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_MRG_RDBF_NBUF );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_RDBF_NBUF_LEN                   , 4   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_MRG_RDBF_NBUF_LEN );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_IBWR_NBUF                       , 9   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_MRG_IBWR_NBUF );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_IBWR_NBUF_LEN                   , 4   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_MRG_IBWR_NBUF_LEN );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_IBRD_NBUF                       , 13  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_MRG_IBRD_NBUF );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_IBRD_NBUF_LEN                   , 3   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_MRG_IBRD_NBUF_LEN );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_BBRD_NBUF                       , 16  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_MRG_BBRD_NBUF );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_BBRD_NBUF_LEN                   , 3   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_MRG_BBRD_NBUF_LEN );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_OBRD_NBUF                       , 19  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_MRG_OBRD_NBUF );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_OBRD_NBUF_LEN                   , 3   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_MRG_OBRD_NBUF_LEN );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_CR_DIS                          , 22  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_MRG_CR_DIS );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_CTLW_CR_DIS                     , 23  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_MRG_CTLW_CR_DIS );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_NTLR_PAUSE_THRESH                   , 24  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_NTLR_PAUSE_THRESH );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_NTLR_PAUSE_THRESH_LEN               , 2   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_NTLR_PAUSE_THRESH_LEN );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_CTLR_HP_THRESH                      , 26  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_CTLR_HP_THRESH );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_CTLR_HP_THRESH_LEN                  , 2   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_CTLR_HP_THRESH_LEN );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_NTLW_PAUSE_THRESH                   , 28  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_NTLW_PAUSE_THRESH );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_NTLW_PAUSE_THRESH_LEN               , 2   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_NTLW_PAUSE_THRESH_LEN );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_CTLW_HP_THRESH                      , 30  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_CTLW_HP_THRESH );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_CTLW_HP_THRESH_LEN                  , 2   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_CTLW_HP_THRESH_LEN );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_PBTX_REDUCE_RTAG                    , 32  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_PBTX_REDUCE_RTAG );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_PBTX_DELAY_BDONE                    , 33  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_PBTX_DELAY_BDONE );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_PBTX_FLIP_IMIN_BIG                  , 34  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_PBTX_FLIP_IMIN_BIG );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_PBTX_FLIP_IMIN_LITTLE               , 35  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_PBTX_FLIP_IMIN_LITTLE );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_ALU_SAFE_LATENCY                    , 36  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_ALU_SAFE_LATENCY );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_ALU_FLIP_ENDIAN_BIG                 , 37  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_ALU_FLIP_ENDIAN_BIG );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_ALU_FLIP_ENDIAN_LITTLE              , 38  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_ALU_FLIP_ENDIAN_LITTLE );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_RESERVED1                           , 39  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_DAT_CONFIG1_RESERVED1_LEN                       , 25  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU1_SM2_CONFIG2_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM2_CONFIG2_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_BRICK_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_BRICK_ENABLE );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_RSP_CTL_CRED_SINGLE_ENA            , 1   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_RSP_CTL_CRED_SINGLE_ENA );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_CREQ_BE_128                        , 2   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_CREQ_BE_128 );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_DGD_BE_128                         , 3   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_DGD_BE_128 );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_WR_SPLIT_UT0_ENA                   , 4   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_WR_SPLIT_UT0_ENA );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_WR_SPLIT_UT1_ENA                   , 5   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_WR_SPLIT_UT1_ENA );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_BRICK_DEBUG_MODE                   , 6   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_BRICK_DEBUG_MODE );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_RESERVED1                          , 7   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_RESERVED1_LEN                      , 3   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_CAM256_MAX_CNT                     , 10  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_CAM256_MAX_CNT );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_CAM256_MAX_CNT_LEN                 , 6   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_CAM256_MAX_CNT_LEN );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_NDL_RX_PARITY_ENA                  , 16  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_NDL_RX_PARITY_ENA );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_NDL_TX_PARITY_ENA                  , 17  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_NDL_TX_PARITY_ENA );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_NDL_PRI_PARITY_ENA                 , 18  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_NDL_PRI_PARITY_ENA );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_RESERVED2                          , 19  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_HDR_ARR_ECC_CORR_ENA               , 20  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_HDR_ARR_ECC_CORR_ENA );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_DAT_ARR_ECC_CORR_ENA               , 21  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_DAT_ARR_ECC_CORR_ENA );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_TX_DATA_ECC_CORR_ENA               , 22  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_TX_DATA_ECC_CORR_ENA );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_RESERVED3                          , 23  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_PARITY_ERROR_SUE_ENA               , 24  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_PARITY_ERROR_SUE_ENA );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_DATA_POISON_SUE_ENA                , 25  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_DATA_POISON_SUE_ENA );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_HDR_ARR_ECC_SUE_ENA                , 26  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_HDR_ARR_ECC_SUE_ENA );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_DAT_ARR_ECC_SUE_ENA                , 27  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_DAT_ARR_ECC_SUE_ENA );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_TX_ECC_DATA_POISON_ENA             , 28  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_TX_ECC_DATA_POISON_ENA );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_RESERVED4                          , 29  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED4  );
+REG64_FLD( PU_NPU1_NTL0_CONFIG2_RESERVED4_LEN                      , 35  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED4_LEN );
+
+REG64_FLD( PU_NPU1_SM3_CONFIG2_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM3_CONFIG2_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_BRICK_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_BRICK_ENABLE );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_RSP_CTL_CRED_SINGLE_ENA            , 1   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_RSP_CTL_CRED_SINGLE_ENA );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_CREQ_BE_128                        , 2   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_CREQ_BE_128 );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_DGD_BE_128                         , 3   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_DGD_BE_128 );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_WR_SPLIT_UT0_ENA                   , 4   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_WR_SPLIT_UT0_ENA );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_WR_SPLIT_UT1_ENA                   , 5   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_WR_SPLIT_UT1_ENA );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_BRICK_DEBUG_MODE                   , 6   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_BRICK_DEBUG_MODE );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_RESERVED1                          , 7   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_RESERVED1_LEN                      , 3   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_CAM256_MAX_CNT                     , 10  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_CAM256_MAX_CNT );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_CAM256_MAX_CNT_LEN                 , 6   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_CAM256_MAX_CNT_LEN );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_NDL_RX_PARITY_ENA                  , 16  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_NDL_RX_PARITY_ENA );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_NDL_TX_PARITY_ENA                  , 17  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_NDL_TX_PARITY_ENA );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_NDL_PRI_PARITY_ENA                 , 18  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_NDL_PRI_PARITY_ENA );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_RESERVED2                          , 19  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_HDR_ARR_ECC_CORR_ENA               , 20  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_HDR_ARR_ECC_CORR_ENA );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_DAT_ARR_ECC_CORR_ENA               , 21  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_DAT_ARR_ECC_CORR_ENA );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_TX_DATA_ECC_CORR_ENA               , 22  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_TX_DATA_ECC_CORR_ENA );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_RESERVED3                          , 23  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_PARITY_ERROR_SUE_ENA               , 24  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_PARITY_ERROR_SUE_ENA );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_DATA_POISON_SUE_ENA                , 25  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_DATA_POISON_SUE_ENA );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_HDR_ARR_ECC_SUE_ENA                , 26  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_HDR_ARR_ECC_SUE_ENA );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_DAT_ARR_ECC_SUE_ENA                , 27  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_DAT_ARR_ECC_SUE_ENA );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_TX_ECC_DATA_POISON_ENA             , 28  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_TX_ECC_DATA_POISON_ENA );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_RESERVED4                          , 29  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED4  );
+REG64_FLD( PU_NPU1_NTL1_CONFIG2_RESERVED4_LEN                      , 35  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED4_LEN );
+
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_BRICK_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_BRICK_ENABLE );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_RSP_CTL_CRED_SINGLE_ENA            , 1   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_RSP_CTL_CRED_SINGLE_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_CREQ_BE_128                        , 2   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_CREQ_BE_128 );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_DGD_BE_128                         , 3   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_DGD_BE_128 );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_WR_SPLIT_UT0_ENA                   , 4   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_WR_SPLIT_UT0_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_WR_SPLIT_UT1_ENA                   , 5   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_WR_SPLIT_UT1_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_BRICK_DEBUG_MODE                   , 6   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_BRICK_DEBUG_MODE );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED1                          , 7   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED1_LEN                      , 3   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_CAM256_MAX_CNT                     , 10  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_CAM256_MAX_CNT );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_CAM256_MAX_CNT_LEN                 , 6   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_CAM256_MAX_CNT_LEN );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_NDL_RX_PARITY_ENA                  , 16  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_NDL_RX_PARITY_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_NDL_TX_PARITY_ENA                  , 17  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_NDL_TX_PARITY_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_NDL_PRI_PARITY_ENA                 , 18  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_NDL_PRI_PARITY_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED2                          , 19  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_HDR_ARR_ECC_CORR_ENA               , 20  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_HDR_ARR_ECC_CORR_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_DAT_ARR_ECC_CORR_ENA               , 21  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_DAT_ARR_ECC_CORR_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_TX_DATA_ECC_CORR_ENA               , 22  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_TX_DATA_ECC_CORR_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED3                          , 23  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_PARITY_ERROR_SUE_ENA               , 24  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_PARITY_ERROR_SUE_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_DATA_POISON_SUE_ENA                , 25  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_DATA_POISON_SUE_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_HDR_ARR_ECC_SUE_ENA                , 26  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_HDR_ARR_ECC_SUE_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_DAT_ARR_ECC_SUE_ENA                , 27  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_DAT_ARR_ECC_SUE_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_TX_ECC_DATA_POISON_ENA             , 28  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_TX_ECC_DATA_POISON_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED4                          , 29  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED4  );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED4_LEN                      , 35  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED4_LEN );
+
+REG64_FLD( PU_NPU1_SM1_CONFIG2_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM1_CONFIG2_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_BRICK_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_BRICK_ENABLE );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_RSP_CTL_CRED_SINGLE_ENA            , 1   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_RSP_CTL_CRED_SINGLE_ENA );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_CREQ_BE_128                        , 2   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_CREQ_BE_128 );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_DGD_BE_128                         , 3   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_DGD_BE_128 );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_WR_SPLIT_UT0_ENA                   , 4   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_WR_SPLIT_UT0_ENA );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_WR_SPLIT_UT1_ENA                   , 5   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_WR_SPLIT_UT1_ENA );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_BRICK_DEBUG_MODE                   , 6   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_BRICK_DEBUG_MODE );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_RESERVED1                          , 7   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_RESERVED1_LEN                      , 3   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_CAM256_MAX_CNT                     , 10  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_CAM256_MAX_CNT );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_CAM256_MAX_CNT_LEN                 , 6   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_CAM256_MAX_CNT_LEN );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_NDL_RX_PARITY_ENA                  , 16  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_NDL_RX_PARITY_ENA );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_NDL_TX_PARITY_ENA                  , 17  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_NDL_TX_PARITY_ENA );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_NDL_PRI_PARITY_ENA                 , 18  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_NDL_PRI_PARITY_ENA );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_RESERVED2                          , 19  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_HDR_ARR_ECC_CORR_ENA               , 20  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_HDR_ARR_ECC_CORR_ENA );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_DAT_ARR_ECC_CORR_ENA               , 21  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_DAT_ARR_ECC_CORR_ENA );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_TX_DATA_ECC_CORR_ENA               , 22  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_TX_DATA_ECC_CORR_ENA );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_RESERVED3                          , 23  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_PARITY_ERROR_SUE_ENA               , 24  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_PARITY_ERROR_SUE_ENA );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_DATA_POISON_SUE_ENA                , 25  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_DATA_POISON_SUE_ENA );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_HDR_ARR_ECC_SUE_ENA                , 26  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_HDR_ARR_ECC_SUE_ENA );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_DAT_ARR_ECC_SUE_ENA                , 27  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_DAT_ARR_ECC_SUE_ENA );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_TX_ECC_DATA_POISON_ENA             , 28  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_TX_ECC_DATA_POISON_ENA );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_RESERVED4                          , 29  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED4  );
+REG64_FLD( PU_NPU0_NTL1_CONFIG2_RESERVED4_LEN                      , 35  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED4_LEN );
+
+REG64_FLD( PU_NPU0_SM2_CONFIG2_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM2_CONFIG2_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_CTL_CONFIG2_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_CTL_CONFIG2_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM1_CONFIG2_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM1_CONFIG2_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_BRICK_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_BRICK_ENABLE );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_RSP_CTL_CRED_SINGLE_ENA            , 1   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_RSP_CTL_CRED_SINGLE_ENA );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_CREQ_BE_128                        , 2   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_CREQ_BE_128 );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_DGD_BE_128                         , 3   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_DGD_BE_128 );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_WR_SPLIT_UT0_ENA                   , 4   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_WR_SPLIT_UT0_ENA );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_WR_SPLIT_UT1_ENA                   , 5   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_WR_SPLIT_UT1_ENA );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_BRICK_DEBUG_MODE                   , 6   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_BRICK_DEBUG_MODE );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_RESERVED1                          , 7   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_RESERVED1_LEN                      , 3   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_CAM256_MAX_CNT                     , 10  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_CAM256_MAX_CNT );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_CAM256_MAX_CNT_LEN                 , 6   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_CAM256_MAX_CNT_LEN );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_NDL_RX_PARITY_ENA                  , 16  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_NDL_RX_PARITY_ENA );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_NDL_TX_PARITY_ENA                  , 17  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_NDL_TX_PARITY_ENA );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_NDL_PRI_PARITY_ENA                 , 18  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_NDL_PRI_PARITY_ENA );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_RESERVED2                          , 19  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_HDR_ARR_ECC_CORR_ENA               , 20  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_HDR_ARR_ECC_CORR_ENA );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_DAT_ARR_ECC_CORR_ENA               , 21  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_DAT_ARR_ECC_CORR_ENA );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_TX_DATA_ECC_CORR_ENA               , 22  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_TX_DATA_ECC_CORR_ENA );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_RESERVED3                          , 23  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_PARITY_ERROR_SUE_ENA               , 24  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_PARITY_ERROR_SUE_ENA );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_DATA_POISON_SUE_ENA                , 25  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_DATA_POISON_SUE_ENA );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_HDR_ARR_ECC_SUE_ENA                , 26  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_HDR_ARR_ECC_SUE_ENA );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_DAT_ARR_ECC_SUE_ENA                , 27  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_DAT_ARR_ECC_SUE_ENA );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_TX_ECC_DATA_POISON_ENA             , 28  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_TX_ECC_DATA_POISON_ENA );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_RESERVED4                          , 29  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED4  );
+REG64_FLD( PU_NPU0_NTL0_CONFIG2_RESERVED4_LEN                      , 35  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED4_LEN );
+
+REG64_FLD( PU_NPU0_SM0_CONFIG2_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM0_CONFIG2_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_BRICK_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_BRICK_ENABLE );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_RSP_CTL_CRED_SINGLE_ENA            , 1   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_RSP_CTL_CRED_SINGLE_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_CREQ_BE_128                        , 2   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_CREQ_BE_128 );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_DGD_BE_128                         , 3   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_DGD_BE_128 );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_WR_SPLIT_UT0_ENA                   , 4   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_WR_SPLIT_UT0_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_WR_SPLIT_UT1_ENA                   , 5   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_WR_SPLIT_UT1_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_BRICK_DEBUG_MODE                   , 6   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_BRICK_DEBUG_MODE );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED1                          , 7   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED1_LEN                      , 3   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_CAM256_MAX_CNT                     , 10  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_CAM256_MAX_CNT );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_CAM256_MAX_CNT_LEN                 , 6   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_CAM256_MAX_CNT_LEN );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_NDL_RX_PARITY_ENA                  , 16  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_NDL_RX_PARITY_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_NDL_TX_PARITY_ENA                  , 17  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_NDL_TX_PARITY_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_NDL_PRI_PARITY_ENA                 , 18  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_NDL_PRI_PARITY_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED2                          , 19  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_HDR_ARR_ECC_CORR_ENA               , 20  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_HDR_ARR_ECC_CORR_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_DAT_ARR_ECC_CORR_ENA               , 21  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_DAT_ARR_ECC_CORR_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_TX_DATA_ECC_CORR_ENA               , 22  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_TX_DATA_ECC_CORR_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED3                          , 23  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_PARITY_ERROR_SUE_ENA               , 24  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_PARITY_ERROR_SUE_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_DATA_POISON_SUE_ENA                , 25  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_DATA_POISON_SUE_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_HDR_ARR_ECC_SUE_ENA                , 26  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_HDR_ARR_ECC_SUE_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_DAT_ARR_ECC_SUE_ENA                , 27  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_DAT_ARR_ECC_SUE_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_TX_ECC_DATA_POISON_ENA             , 28  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_TX_ECC_DATA_POISON_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED4                          , 29  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED4  );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED4_LEN                      , 35  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED4_LEN );
+
+REG64_FLD( PU_NPU2_SM3_CONFIG2_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM3_CONFIG2_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM3_CONFIG2_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM3_CONFIG2_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM2_CONFIG2_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM2_CONFIG2_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_CTL_CONFIG2_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_CTL_CONFIG2_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM1_CONFIG2_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM1_CONFIG2_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM0_CONFIG2_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM0_CONFIG2_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_CTL_CONFIG2_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_CTL_CONFIG2_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM0_CONFIG2_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM0_CONFIG2_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM2_CONFIG3_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM2_CONFIG3_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_NTL0_CONFIG3_RESERVED1                          , 0   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_NTL0_CONFIG3_RESERVED1_LEN                      , 64  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU1_SM3_CONFIG3_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM3_CONFIG3_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_NTL1_CONFIG3_RESERVED1                          , 0   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_NTL1_CONFIG3_RESERVED1_LEN                      , 64  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU2_NTL1_CONFIG3_RESERVED1                          , 0   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL1_CONFIG3_RESERVED1_LEN                      , 64  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU1_SM1_CONFIG3_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM1_CONFIG3_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_NTL1_CONFIG3_RESERVED1                          , 0   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_NTL1_CONFIG3_RESERVED1_LEN                      , 64  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU0_SM2_CONFIG3_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM2_CONFIG3_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_CTL_CONFIG3_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_CTL_CONFIG3_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM1_CONFIG3_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM1_CONFIG3_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_NTL0_CONFIG3_RESERVED1                          , 0   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_NTL0_CONFIG3_RESERVED1_LEN                      , 64  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU0_SM0_CONFIG3_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM0_CONFIG3_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_NTL0_CONFIG3_RESERVED1                          , 0   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL0_CONFIG3_RESERVED1_LEN                      , 64  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU2_SM3_CONFIG3_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM3_CONFIG3_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM3_CONFIG3_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM3_CONFIG3_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM2_CONFIG3_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM2_CONFIG3_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_CTL_CONFIG3_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_CTL_CONFIG3_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM1_CONFIG3_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM1_CONFIG3_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM0_CONFIG3_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM0_CONFIG3_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_CTL_CONFIG3_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_CTL_CONFIG3_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM0_CONFIG3_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM0_CONFIG3_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_WITHSTART_0      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_WITHADDR_0       , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_READCONT_0       , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_BIT_READCONT_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_WITHSTOP_0       , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_LENGTH_0             , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_LENGTH_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_LENGTH_0_LEN         , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_LENGTH_0_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_ADDR_0               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_ADDR_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_ADDR_0_LEN           , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_ADDR_0_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_RNW_0            , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_BIT_RNW_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_SPEED_0              , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_SPEED_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_SPEED_0_LEN          , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_SPEED_0_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_PORT_NUMBER_0        , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_PORT_NUMBER_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_PORT_NUMBER_0_LEN    , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_PORT_NUMBER_0_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_B_REG_ADDR_LEN_0                    , 23  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REG_ADDR_LEN_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_REG_ADDR_LEN_0_LEN                , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REG_ADDR_LEN_0_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_B_ENH_MODE_0                        , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENH_MODE_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_ECC_ENABLE_0                      , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_ENABLE_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_ECCCHK_DISABLE_0                  , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECCCHK_DISABLE_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_UNUSED_0                          , 29  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED_0   );
+REG64_FLD( PU_CONTROL_REGISTER_B_UNUSED_0_LEN                      , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED_0_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_1_0             , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_1_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_1_0_LEN         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_1_0_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_2_0             , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_2_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_2_0_LEN         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_2_0_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_3_0             , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_3_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_3_0_LEN         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_3_0_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_4_0             , 56  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_4_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_4_0_LEN         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_4_0_LEN );
+
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_WITHSTART_1      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_WITHADDR_1       , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_READCONT_1       , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_BIT_READCONT_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_WITHSTOP_1       , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_LENGTH_1             , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_LENGTH_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_LENGTH_1_LEN         , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_LENGTH_1_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_ADDR_1               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_ADDR_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_ADDR_1_LEN           , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_ADDR_1_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_RNW_1            , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_BIT_RNW_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_SPEED_1              , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_SPEED_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_SPEED_1_LEN          , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_SPEED_1_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_PORT_NUMBER_1        , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_PORT_NUMBER_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_PORT_NUMBER_1_LEN    , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_PORT_NUMBER_1_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_C_REG_ADDR_LEN_1                    , 23  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REG_ADDR_LEN_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_REG_ADDR_LEN_1_LEN                , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REG_ADDR_LEN_1_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_C_ENH_MODE_1                        , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENH_MODE_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_ECC_ENABLE_1                      , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_ENABLE_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_ECCCHK_DISABLE_1                  , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECCCHK_DISABLE_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_UNUSED_1                          , 29  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED_1   );
+REG64_FLD( PU_CONTROL_REGISTER_C_UNUSED_1_LEN                      , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED_1_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_1_1             , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_1_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_1_1_LEN         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_1_1_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_2_1             , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_2_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_2_1_LEN         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_2_1_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_3_1             , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_3_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_3_1_LEN         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_3_1_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_4_1             , 56  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_4_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_4_1_LEN         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_4_1_LEN );
+
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_WITHSTART_2      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_WITHADDR_2       , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_READCONT_2       , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_BIT_READCONT_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_WITHSTOP_2       , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_LENGTH_2             , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_LENGTH_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_LENGTH_2_LEN         , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_LENGTH_2_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_ADDR_2               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_ADDR_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_ADDR_2_LEN           , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_ADDR_2_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_RNW_2            , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_BIT_RNW_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_SPEED_2              , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_SPEED_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_SPEED_2_LEN          , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_SPEED_2_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_PORT_NUMBER_2        , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_PORT_NUMBER_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_PORT_NUMBER_2_LEN    , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_PORT_NUMBER_2_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_D_REG_ADDR_LEN_2                    , 23  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REG_ADDR_LEN_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_REG_ADDR_LEN_2_LEN                , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REG_ADDR_LEN_2_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_D_ENH_MODE_2                        , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENH_MODE_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_ECC_ENABLE_2                      , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_ENABLE_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_ECCCHK_DISABLE_2                  , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECCCHK_DISABLE_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_UNUSED_2                          , 29  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED_2   );
+REG64_FLD( PU_CONTROL_REGISTER_D_UNUSED_2_LEN                      , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED_2_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_1_2             , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_1_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_1_2_LEN         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_1_2_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_2_2             , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_2_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_2_2_LEN         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_2_2_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_3_2             , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_3_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_3_2_LEN         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_3_2_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_4_2             , 56  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_4_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_4_2_LEN         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_4_2_LEN );
+
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_WITHSTART_3      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_WITHADDR_3       , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_READCONT_3       , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_BIT_READCONT_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_WITHSTOP_3       , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_LENGTH_3             , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_LENGTH_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_LENGTH_3_LEN         , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_LENGTH_3_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_ADDR_3               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_ADDR_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_ADDR_3_LEN           , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_ADDR_3_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_RNW_3            , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_BIT_RNW_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_SPEED_3              , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_SPEED_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_SPEED_3_LEN          , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_SPEED_3_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_PORT_NUMBER_3        , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_PORT_NUMBER_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_PORT_NUMBER_3_LEN    , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_PORT_NUMBER_3_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_E_REG_ADDR_LEN_3                    , 23  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REG_ADDR_LEN_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_REG_ADDR_LEN_3_LEN                , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REG_ADDR_LEN_3_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_E_ENH_MODE_3                        , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENH_MODE_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_ECC_ENABLE_3                      , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_ENABLE_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_ECCCHK_DISABLE_3                  , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECCCHK_DISABLE_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_UNUSED_3                          , 29  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED_3   );
+REG64_FLD( PU_CONTROL_REGISTER_E_UNUSED_3_LEN                      , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED_3_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_1_3             , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_1_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_1_3_LEN         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_1_3_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_2_3             , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_2_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_2_3_LEN         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_2_3_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_3_3             , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_3_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_3_3_LEN         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_3_3_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_4_3             , 56  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_4_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_4_3_LEN         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_CNTR_REG_DATA_4_3_LEN );
+
+REG64_FLD( PEC_STACK2_CQSTAT_REG_PE_INBOUND_ACTIVE                 , 0   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM_RO  , SH_FLD_PE_INBOUND_ACTIVE );
+REG64_FLD( PEC_STACK2_CQSTAT_REG_PE_OUTBOUND_ACTIVE                , 1   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM_RO  , SH_FLD_PE_OUTBOUND_ACTIVE );
+
+REG64_FLD( PEC_STACK1_CQSTAT_REG_PE_INBOUND_ACTIVE                 , 0   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM_RO  , SH_FLD_PE_INBOUND_ACTIVE );
+REG64_FLD( PEC_STACK1_CQSTAT_REG_PE_OUTBOUND_ACTIVE                , 1   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM_RO  , SH_FLD_PE_OUTBOUND_ACTIVE );
+
+REG64_FLD( PEC_STACK0_CQSTAT_REG_PE_INBOUND_ACTIVE                 , 0   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM_RO  , SH_FLD_PE_INBOUND_ACTIVE );
+REG64_FLD( PEC_STACK0_CQSTAT_REG_PE_OUTBOUND_ACTIVE                , 1   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM_RO  , SH_FLD_PE_OUTBOUND_ACTIVE );
+
+REG64_FLD( PU_NPU1_CTL_CTLSM_HOLD0_IDIAL                           , 0   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_CTL_CTLSM_HOLD0_IDIAL_LEN                       , 50  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_CTL_CTLSM_HOLD0_IDIAL                           , 0   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_CTL_CTLSM_HOLD0_IDIAL_LEN                       , 50  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_CTL_CTLSM_HOLD0_IDIAL                           , 0   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_CTL_CTLSM_HOLD0_IDIAL_LEN                       , 50  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_CTL_CTLSM_HOLD1_IDIAL                           , 0   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_CTL_CTLSM_HOLD1_IDIAL_LEN                       , 50  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_CTL_CTLSM_HOLD1_IDIAL                           , 0   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_CTL_CTLSM_HOLD1_IDIAL_LEN                       , 50  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_CTL_CTLSM_HOLD1_IDIAL                           , 0   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_CTL_CTLSM_HOLD1_IDIAL_LEN                       , 50  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_CTL_CTLSM_MASK0_IDIAL                           , 0   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_CTL_CTLSM_MASK0_IDIAL_LEN                       , 50  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_CTL_CTLSM_MASK0_IDIAL                           , 0   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_CTL_CTLSM_MASK0_IDIAL_LEN                       , 50  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_CTL_CTLSM_MASK0_IDIAL                           , 0   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_CTL_CTLSM_MASK0_IDIAL_LEN                       , 50  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_CTL_CTLSM_MASK1_IDIAL                           , 0   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_CTL_CTLSM_MASK1_IDIAL_LEN                       , 50  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_CTL_CTLSM_MASK1_IDIAL                           , 0   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_CTL_CTLSM_MASK1_IDIAL_LEN                       , 50  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_CTL_CTLSM_MASK1_IDIAL                           , 0   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_CTL_CTLSM_MASK1_IDIAL_LEN                       , 50  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_CTL_CTL_HOLD_IDIAL                              , 0   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_CTL_CTL_HOLD_IDIAL_LEN                          , 20  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_CTL_CTL_HOLD_IDIAL                              , 0   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_CTL_CTL_HOLD_IDIAL_LEN                          , 20  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_CTL_CTL_HOLD_IDIAL                              , 0   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_CTL_CTL_HOLD_IDIAL_LEN                          , 20  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_CTL_CTL_MASK_IDIAL                              , 0   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_CTL_CTL_MASK_IDIAL_LEN                          , 20  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_CTL_CTL_MASK_IDIAL                              , 0   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_CTL_CTL_MASK_IDIAL_LEN                          , 20  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_CTL_CTL_MASK_IDIAL                              , 0   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_CTL_CTL_MASK_IDIAL_LEN                          , 20  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_DATA0TO7_REGISTER_B_PIB_0                            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_0      );
+REG64_FLD( PU_DATA0TO7_REGISTER_B_PIB_0_LEN                        , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_0_LEN  );
+
+REG64_FLD( PU_DATA0TO7_REGISTER_C_PIB_1                            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_1      );
+REG64_FLD( PU_DATA0TO7_REGISTER_C_PIB_1_LEN                        , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_1_LEN  );
+
+REG64_FLD( PU_DATA0TO7_REGISTER_D_PIB_2                            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_2      );
+REG64_FLD( PU_DATA0TO7_REGISTER_D_PIB_2_LEN                        , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_2_LEN  );
+
+REG64_FLD( PU_DATA0TO7_REGISTER_E_PIB_3                            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_3      );
+REG64_FLD( PU_DATA0TO7_REGISTER_E_PIB_3_LEN                        , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_3_LEN  );
+
+REG64_FLD( PU_DATA8TO15_REGISTER_B_PIB_0                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_0      );
+REG64_FLD( PU_DATA8TO15_REGISTER_B_PIB_0_LEN                       , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_0_LEN  );
+
+REG64_FLD( PU_DATA8TO15_REGISTER_C_PIB_1                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_1      );
+REG64_FLD( PU_DATA8TO15_REGISTER_C_PIB_1_LEN                       , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_1_LEN  );
+
+REG64_FLD( PU_DATA8TO15_REGISTER_D_PIB_2                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_2      );
+REG64_FLD( PU_DATA8TO15_REGISTER_D_PIB_2_LEN                       , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_2_LEN  );
+
+REG64_FLD( PU_DATA8TO15_REGISTER_E_PIB_3                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_3      );
+REG64_FLD( PU_DATA8TO15_REGISTER_E_PIB_3_LEN                       , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_3_LEN  );
+
+REG64_FLD( PU_DATATAG_0_HASH_FUNCTION_REG_FUNCTION                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FUNCTION   );
+REG64_FLD( PU_DATATAG_0_HASH_FUNCTION_REG_FUNCTION_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FUNCTION_LEN );
+
+REG64_FLD( PU_DATATAG_1_HASH_FUNCTION_REG_FUNCTION                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FUNCTION   );
+REG64_FLD( PU_DATATAG_1_HASH_FUNCTION_REG_FUNCTION_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FUNCTION_LEN );
+
+REG64_FLD( PU_DATATAG_2_HASH_FUNCTION_REG_FUNCTION                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FUNCTION   );
+REG64_FLD( PU_DATATAG_2_HASH_FUNCTION_REG_FUNCTION_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FUNCTION_LEN );
+
+REG64_FLD( PU_DATATAG_3_HASH_FUNCTION_REG_FUNCTION                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FUNCTION   );
+REG64_FLD( PU_DATATAG_3_HASH_FUNCTION_REG_FUNCTION_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FUNCTION_LEN );
+
+REG64_FLD( PU_DATATAG_4_HASH_FUNCTION_REG_FUNCTION                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FUNCTION   );
+REG64_FLD( PU_DATATAG_4_HASH_FUNCTION_REG_FUNCTION_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FUNCTION_LEN );
+
+REG64_FLD( PU_DATATAG_5_HASH_FUNCTION_REG_FUNCTION                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FUNCTION   );
+REG64_FLD( PU_DATATAG_5_HASH_FUNCTION_REG_FUNCTION_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FUNCTION_LEN );
+
+REG64_FLD( PU_DATA_REGISTER_OTP                                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OTP        );
+REG64_FLD( PU_DATA_REGISTER_OTP_LEN                                , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OTP_LEN    );
+
+REG64_FLD( PU_NPU_DAT_DA_ADDR_MISC                                 , 0   ,
+           SH_UNT_PU_NPU_DAT, SH_ACS_SCOM     , SH_FLD_MISC       );
+REG64_FLD( PU_NPU_DAT_DA_ADDR_MISC_LEN                             , 64  ,
+           SH_UNT_PU_NPU_DAT, SH_ACS_SCOM     , SH_FLD_MISC_LEN   );
+
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD0                           , 0   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD0_LEN                       , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD1                           , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD1_LEN                       , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD2                           , 10  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD2_LEN                       , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD3                           , 15  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD3_LEN                       , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD4                           , 20  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD4_LEN                       , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD5                           , 25  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD5_LEN                       , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD6                           , 30  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD6_LEN                       , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD7                           , 35  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD7_LEN                       , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD8                           , 40  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD8_LEN                       , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD9                           , 45  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD9_LEN                       , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD10                          , 50  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD10_LEN                      , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_RESERVED1                      , 55  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_RESERVED1_LEN                  , 8   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_ACT                            , 63  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD0                           , 0   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD0_LEN                       , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD1                           , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD1_LEN                       , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD2                           , 10  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD2_LEN                       , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD3                           , 15  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD3_LEN                       , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD4                           , 20  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD4_LEN                       , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD5                           , 25  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD5_LEN                       , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD6                           , 30  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD6_LEN                       , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD7                           , 35  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD7_LEN                       , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD8                           , 40  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD8_LEN                       , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD9                           , 45  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD9_LEN                       , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD10                          , 50  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD10_LEN                      , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_RESERVED1                      , 55  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_RESERVED1_LEN                  , 8   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_ACT                            , 63  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD0                          , 0   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD0       );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD0_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD1                          , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD1       );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD1_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD2                          , 10  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD2       );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD2_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD3                          , 15  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD3       );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD3_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD4                          , 20  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD4       );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD4_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD5                          , 25  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD5       );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD5_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD6                          , 30  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD6       );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD6_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD7                          , 35  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD7       );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD7_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD8                          , 40  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD8       );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD8_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD9                          , 45  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD9       );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD9_LEN                      , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD10                         , 50  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD10      );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD10_LEN                     , 5   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_RESERVED1                     , 55  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_ACT                           , 63  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC                            , 0   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_MISC       );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_LEN                        , 64  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_MISC_LEN   );
+
+REG64_FLD( PU_DISABLE_FORCE_PFET_OFF_REG                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REG        );
+REG64_FLD( PU_DISABLE_FORCE_PFET_OFF_REG_LEN                       , 30  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REG_LEN    );
+REG64_FLD( PU_DISABLE_FORCE_PFET_OFF_RESERVED                      , 30  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_DISABLE_FORCE_PFET_OFF_RESERVED_LEN                  , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU0_DISPALT_CTRL_ENABLE                             , 54  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU0_DISPALT_CTRL_WRITE                              , 55  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_WRITE      );
+REG64_FLD( PU_NPU0_DISPALT_CTRL_SLICE                              , 56  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_SLICE      );
+REG64_FLD( PU_NPU0_DISPALT_CTRL_SLICE_LEN                          , 2   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_SLICE_LEN  );
+REG64_FLD( PU_NPU0_DISPALT_CTRL_ENTRY                              , 58  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_ENTRY      );
+REG64_FLD( PU_NPU0_DISPALT_CTRL_ENTRY_LEN                          , 6   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_ENTRY_LEN  );
+
+REG64_FLD( PU_NPU1_DISPALT_CTRL_ENABLE                             , 54  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU1_DISPALT_CTRL_WRITE                              , 55  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_WRITE      );
+REG64_FLD( PU_NPU1_DISPALT_CTRL_SLICE                              , 56  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_SLICE      );
+REG64_FLD( PU_NPU1_DISPALT_CTRL_SLICE_LEN                          , 2   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_SLICE_LEN  );
+REG64_FLD( PU_NPU1_DISPALT_CTRL_ENTRY                              , 58  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_ENTRY      );
+REG64_FLD( PU_NPU1_DISPALT_CTRL_ENTRY_LEN                          , 6   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_ENTRY_LEN  );
+
+REG64_FLD( PU_NPU2_DISPALT_CTRL_ENABLE                             , 54  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU2_DISPALT_CTRL_WRITE                              , 55  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_WRITE      );
+REG64_FLD( PU_NPU2_DISPALT_CTRL_SLICE                              , 56  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_SLICE      );
+REG64_FLD( PU_NPU2_DISPALT_CTRL_SLICE_LEN                          , 2   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_SLICE_LEN  );
+REG64_FLD( PU_NPU2_DISPALT_CTRL_ENTRY                              , 58  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_ENTRY      );
+REG64_FLD( PU_NPU2_DISPALT_CTRL_ENTRY_LEN                          , 6   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_ENTRY_LEN  );
+
+REG64_FLD( PU_NPU0_DISPALT_DAT0_WORD                               , 0   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_WORD       );
+REG64_FLD( PU_NPU0_DISPALT_DAT0_WORD_LEN                           , 64  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_WORD_LEN   );
+
+REG64_FLD( PU_NPU1_DISPALT_DAT0_WORD                               , 0   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_WORD       );
+REG64_FLD( PU_NPU1_DISPALT_DAT0_WORD_LEN                           , 64  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_WORD_LEN   );
+
+REG64_FLD( PU_NPU2_DISPALT_DAT0_WORD                               , 0   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_WORD       );
+REG64_FLD( PU_NPU2_DISPALT_DAT0_WORD_LEN                           , 64  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_WORD_LEN   );
+
+REG64_FLD( PU_NPU0_DISPALT_DAT1_WORD                               , 0   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_WORD       );
+REG64_FLD( PU_NPU0_DISPALT_DAT1_WORD_LEN                           , 64  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_WORD_LEN   );
+
+REG64_FLD( PU_NPU1_DISPALT_DAT1_WORD                               , 0   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_WORD       );
+REG64_FLD( PU_NPU1_DISPALT_DAT1_WORD_LEN                           , 64  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_WORD_LEN   );
+
+REG64_FLD( PU_NPU2_DISPALT_DAT1_WORD                               , 0   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_WORD       );
+REG64_FLD( PU_NPU2_DISPALT_DAT1_WORD_LEN                           , 64  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_WORD_LEN   );
+
+REG64_FLD( PU_NPU0_DISPALT_STAT_ECC_BUSY                           , 47  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_BUSY       );
+REG64_FLD( PU_NPU0_DISPALT_STAT_ECC_ECC                            , 48  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_ECC        );
+REG64_FLD( PU_NPU0_DISPALT_STAT_ECC_ECC_LEN                        , 16  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_ECC_LEN    );
+
+REG64_FLD( PU_NPU1_DISPALT_STAT_ECC_BUSY                           , 47  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_BUSY       );
+REG64_FLD( PU_NPU1_DISPALT_STAT_ECC_ECC                            , 48  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_ECC        );
+REG64_FLD( PU_NPU1_DISPALT_STAT_ECC_ECC_LEN                        , 16  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_ECC_LEN    );
+
+REG64_FLD( PU_NPU2_DISPALT_STAT_ECC_BUSY                           , 47  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_BUSY       );
+REG64_FLD( PU_NPU2_DISPALT_STAT_ECC_ECC                            , 48  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_ECC        );
+REG64_FLD( PU_NPU2_DISPALT_STAT_ECC_ECC_LEN                        , 16  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_ECC_LEN    );
+
+REG64_FLD( PU_DMA_UP_ADDR_BASE_UPPER_BITS                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BASE_UPPER_BITS );
+REG64_FLD( PU_DMA_UP_ADDR_BASE_UPPER_BITS_LEN                      , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BASE_UPPER_BITS_LEN );
+REG64_FLD( PU_DMA_UP_ADDR_ESCAPE_ADDRESS                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ESCAPE_ADDRESS );
+REG64_FLD( PU_DMA_UP_ADDR_ESCAPE_ADDRESS_LEN                       , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ESCAPE_ADDRESS_LEN );
+
+REG64_FLD( PU_DMA_VAS_MMIO_BAR_BAR                                 , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BAR        );
+REG64_FLD( PU_DMA_VAS_MMIO_BAR_BAR_LEN                             , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BAR_LEN    );
+
+REG64_FLD( PEC_DRPPRICTL_REG_PE_DROPPRIORITYMASK                   , 0   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DROPPRIORITYMASK );
+REG64_FLD( PEC_DRPPRICTL_REG_PE_DROPPRIORITYMASK_LEN               , 6   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DROPPRIORITYMASK_LEN );
+REG64_FLD( PEC_DRPPRICTL_REG_PE_ENABLE_CTAG_DROP_PRIORITY          , 6   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_ENABLE_CTAG_DROP_PRIORITY );
+REG64_FLD( PEC_DRPPRICTL_REG_PE_ENABLE_IO_CMD_PACING               , 7   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_ENABLE_IO_CMD_PACING );
+REG64_FLD( PEC_DRPPRICTL_REG_PE_DROPPACECOUNT                      , 8   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DROPPACECOUNT );
+REG64_FLD( PEC_DRPPRICTL_REG_PE_DROPPACECOUNT_LEN                  , 9   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DROPPACECOUNT_LEN );
+REG64_FLD( PEC_DRPPRICTL_REG_PE_DROPPACEINC                        , 17  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DROPPACEINC );
+REG64_FLD( PEC_DRPPRICTL_REG_PE_DROPPACEINC_LEN                    , 6   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DROPPACEINC_LEN );
+REG64_FLD( PEC_DRPPRICTL_REG_PE_RTYDROPDIVIDER                     , 23  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_RTYDROPDIVIDER );
+REG64_FLD( PEC_DRPPRICTL_REG_PE_RTYDROPDIVIDER_LEN                 , 3   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_RTYDROPDIVIDER_LEN );
+
+REG64_FLD( PU_NPU0_ECC_CONFIG_RESERVED1                            , 0   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_ECC_CONFIG_RESERVED1_LEN                        , 29  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_ECC_CONFIG_PBTX_AMO_IGNORE_XUE                  , 29  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_PBTX_AMO_IGNORE_XUE );
+REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_BR_PERR                      , 30  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_BR_PERR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_IR_PERR                      , 31  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_IR_PERR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_OR_PERR                      , 32  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_OR_PERR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_PT                          , 33  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_CORR_DIS_PT );
+REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_PR                          , 34  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_CORR_DIS_PR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_BR                          , 35  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_CORR_DIS_BR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_IR                          , 36  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_CORR_DIS_IR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_OR                          , 37  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_CORR_DIS_OR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_COUNT_DIS_PT                         , 38  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_COUNT_DIS_PT );
+REG64_FLD( PU_NPU0_ECC_CONFIG_COUNT_DIS_PR                         , 39  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_COUNT_DIS_PR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_COUNT_DIS_BR                         , 40  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_COUNT_DIS_BR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_COUNT_DIS_IR                         , 41  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_COUNT_DIS_IR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_COUNT_DIS_OR                         , 42  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_COUNT_DIS_OR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_PT                           , 43  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_PT );
+REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_PR                           , 44  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_PR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_BR                           , 45  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_BR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_IR                           , 46  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_IR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_OR                           , 47  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_OR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_CE_THRESH                            , 48  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_CE_THRESH  );
+REG64_FLD( PU_NPU0_ECC_CONFIG_CE_THRESH_LEN                        , 16  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_CE_THRESH_LEN );
+
+REG64_FLD( PU_NPU1_ECC_CONFIG_RESERVED1                            , 0   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_ECC_CONFIG_RESERVED1_LEN                        , 29  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_ECC_CONFIG_PBTX_AMO_IGNORE_XUE                  , 29  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_PBTX_AMO_IGNORE_XUE );
+REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_BR_PERR                      , 30  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_BR_PERR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_IR_PERR                      , 31  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_IR_PERR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_OR_PERR                      , 32  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_OR_PERR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_PT                          , 33  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_CORR_DIS_PT );
+REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_PR                          , 34  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_CORR_DIS_PR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_BR                          , 35  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_CORR_DIS_BR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_IR                          , 36  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_CORR_DIS_IR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_OR                          , 37  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_CORR_DIS_OR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_COUNT_DIS_PT                         , 38  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_COUNT_DIS_PT );
+REG64_FLD( PU_NPU1_ECC_CONFIG_COUNT_DIS_PR                         , 39  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_COUNT_DIS_PR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_COUNT_DIS_BR                         , 40  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_COUNT_DIS_BR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_COUNT_DIS_IR                         , 41  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_COUNT_DIS_IR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_COUNT_DIS_OR                         , 42  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_COUNT_DIS_OR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_PT                           , 43  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_PT );
+REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_PR                           , 44  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_PR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_BR                           , 45  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_BR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_IR                           , 46  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_IR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_OR                           , 47  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_OR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_CE_THRESH                            , 48  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_CE_THRESH  );
+REG64_FLD( PU_NPU1_ECC_CONFIG_CE_THRESH_LEN                        , 16  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_CE_THRESH_LEN );
+
+REG64_FLD( PU_NPU2_ECC_CONFIG_RESERVED1                            , 0   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_ECC_CONFIG_RESERVED1_LEN                        , 29  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_ECC_CONFIG_PBTX_AMO_IGNORE_XUE                  , 29  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_PBTX_AMO_IGNORE_XUE );
+REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_BR_PERR                      , 30  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_BR_PERR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_IR_PERR                      , 31  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_IR_PERR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_OR_PERR                      , 32  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_OR_PERR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_PT                          , 33  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_CORR_DIS_PT );
+REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_PR                          , 34  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_CORR_DIS_PR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_BR                          , 35  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_CORR_DIS_BR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_IR                          , 36  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_CORR_DIS_IR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_OR                          , 37  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_CORR_DIS_OR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_COUNT_DIS_PT                         , 38  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_COUNT_DIS_PT );
+REG64_FLD( PU_NPU2_ECC_CONFIG_COUNT_DIS_PR                         , 39  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_COUNT_DIS_PR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_COUNT_DIS_BR                         , 40  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_COUNT_DIS_BR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_COUNT_DIS_IR                         , 41  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_COUNT_DIS_IR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_COUNT_DIS_OR                         , 42  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_COUNT_DIS_OR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_PT                           , 43  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_PT );
+REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_PR                           , 44  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_PR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_BR                           , 45  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_BR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_IR                           , 46  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_IR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_OR                           , 47  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_SUE_DIS_OR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_CE_THRESH                            , 48  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_CE_THRESH  );
+REG64_FLD( PU_NPU2_ECC_CONFIG_CE_THRESH_LEN                        , 16  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_CE_THRESH_LEN );
+
+REG64_FLD( PU_NPU0_ECC_COUNT_CE_CMD                                , 30  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_CE_CMD     );
+REG64_FLD( PU_NPU0_ECC_COUNT_CE_CMD_LEN                            , 2   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_CE_CMD_LEN );
+REG64_FLD( PU_NPU0_ECC_COUNT_CE_WVAL                               , 32  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_CE_WVAL    );
+REG64_FLD( PU_NPU0_ECC_COUNT_CE_WVAL_LEN                           , 16  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_CE_WVAL_LEN );
+REG64_FLD( PU_NPU0_ECC_COUNT_CE                                    , 48  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_CE         );
+REG64_FLD( PU_NPU0_ECC_COUNT_CE_LEN                                , 16  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_CE_LEN     );
+
+REG64_FLD( PU_NPU1_ECC_COUNT_CE_CMD                                , 30  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_CE_CMD     );
+REG64_FLD( PU_NPU1_ECC_COUNT_CE_CMD_LEN                            , 2   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_CE_CMD_LEN );
+REG64_FLD( PU_NPU1_ECC_COUNT_CE_WVAL                               , 32  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_CE_WVAL    );
+REG64_FLD( PU_NPU1_ECC_COUNT_CE_WVAL_LEN                           , 16  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_CE_WVAL_LEN );
+REG64_FLD( PU_NPU1_ECC_COUNT_CE                                    , 48  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_CE         );
+REG64_FLD( PU_NPU1_ECC_COUNT_CE_LEN                                , 16  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_CE_LEN     );
+
+REG64_FLD( PU_NPU2_ECC_COUNT_CE_CMD                                , 30  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_CE_CMD     );
+REG64_FLD( PU_NPU2_ECC_COUNT_CE_CMD_LEN                            , 2   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_CE_CMD_LEN );
+REG64_FLD( PU_NPU2_ECC_COUNT_CE_WVAL                               , 32  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_CE_WVAL    );
+REG64_FLD( PU_NPU2_ECC_COUNT_CE_WVAL_LEN                           , 16  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_CE_WVAL_LEN );
+REG64_FLD( PU_NPU2_ECC_COUNT_CE                                    , 48  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_CE         );
+REG64_FLD( PU_NPU2_ECC_COUNT_CE_LEN                                , 16  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_CE_LEN     );
+
+REG64_FLD( PU_NPU0_ECC_ERRINJ_ENABLE                               , 0   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU0_ECC_ERRINJ_PBRX_MASK                            , 1   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_PBRX_MASK  );
+REG64_FLD( PU_NPU0_ECC_ERRINJ_PBRX_MASK_LEN                        , 8   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_PBRX_MASK_LEN );
+REG64_FLD( PU_NPU0_ECC_ERRINJ_BBWR_MASK                            , 9   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_BBWR_MASK  );
+REG64_FLD( PU_NPU0_ECC_ERRINJ_BBWR_MASK_LEN                        , 4   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_BBWR_MASK_LEN );
+REG64_FLD( PU_NPU0_ECC_ERRINJ_IBWR_MASK                            , 13  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IBWR_MASK  );
+REG64_FLD( PU_NPU0_ECC_ERRINJ_IBWR_MASK_LEN                        , 16  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IBWR_MASK_LEN );
+REG64_FLD( PU_NPU0_ECC_ERRINJ_OBWR_MASK                            , 29  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_OBWR_MASK  );
+REG64_FLD( PU_NPU0_ECC_ERRINJ_OBWR_MASK_LEN                        , 16  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_OBWR_MASK_LEN );
+REG64_FLD( PU_NPU0_ECC_ERRINJ_RESERVED                             , 45  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU0_ECC_ERRINJ_RESERVED_LEN                         , 3   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU1_ECC_ERRINJ_ENABLE                               , 0   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU1_ECC_ERRINJ_PBRX_MASK                            , 1   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_PBRX_MASK  );
+REG64_FLD( PU_NPU1_ECC_ERRINJ_PBRX_MASK_LEN                        , 8   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_PBRX_MASK_LEN );
+REG64_FLD( PU_NPU1_ECC_ERRINJ_BBWR_MASK                            , 9   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_BBWR_MASK  );
+REG64_FLD( PU_NPU1_ECC_ERRINJ_BBWR_MASK_LEN                        , 4   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_BBWR_MASK_LEN );
+REG64_FLD( PU_NPU1_ECC_ERRINJ_IBWR_MASK                            , 13  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IBWR_MASK  );
+REG64_FLD( PU_NPU1_ECC_ERRINJ_IBWR_MASK_LEN                        , 16  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IBWR_MASK_LEN );
+REG64_FLD( PU_NPU1_ECC_ERRINJ_OBWR_MASK                            , 29  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_OBWR_MASK  );
+REG64_FLD( PU_NPU1_ECC_ERRINJ_OBWR_MASK_LEN                        , 16  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_OBWR_MASK_LEN );
+REG64_FLD( PU_NPU1_ECC_ERRINJ_RESERVED                             , 45  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU1_ECC_ERRINJ_RESERVED_LEN                         , 3   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU2_ECC_ERRINJ_ENABLE                               , 0   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU2_ECC_ERRINJ_PBRX_MASK                            , 1   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_PBRX_MASK  );
+REG64_FLD( PU_NPU2_ECC_ERRINJ_PBRX_MASK_LEN                        , 8   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_PBRX_MASK_LEN );
+REG64_FLD( PU_NPU2_ECC_ERRINJ_BBWR_MASK                            , 9   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_BBWR_MASK  );
+REG64_FLD( PU_NPU2_ECC_ERRINJ_BBWR_MASK_LEN                        , 4   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_BBWR_MASK_LEN );
+REG64_FLD( PU_NPU2_ECC_ERRINJ_IBWR_MASK                            , 13  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IBWR_MASK  );
+REG64_FLD( PU_NPU2_ECC_ERRINJ_IBWR_MASK_LEN                        , 16  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IBWR_MASK_LEN );
+REG64_FLD( PU_NPU2_ECC_ERRINJ_OBWR_MASK                            , 29  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_OBWR_MASK  );
+REG64_FLD( PU_NPU2_ECC_ERRINJ_OBWR_MASK_LEN                        , 16  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_OBWR_MASK_LEN );
+REG64_FLD( PU_NPU2_ECC_ERRINJ_RESERVED                             , 45  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_ECC_ERRINJ_RESERVED_LEN                         , 3   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART0_REGISTER_PART_0                   , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_0     );
+REG64_FLD( PU_OTPROM0_ECID_PART0_REGISTER_PART_0_LEN               , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_0_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART0_REGISTER_PART_0                   , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_0     );
+REG64_FLD( PU_OTPROM1_ECID_PART0_REGISTER_PART_0_LEN               , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_0_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART10_REGISTER_PART_10                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_10    );
+REG64_FLD( PU_OTPROM0_ECID_PART10_REGISTER_PART_10_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_10_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART10_REGISTER_PART_10                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_10    );
+REG64_FLD( PU_OTPROM1_ECID_PART10_REGISTER_PART_10_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_10_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART11_REGISTER_PART_11                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_11    );
+REG64_FLD( PU_OTPROM0_ECID_PART11_REGISTER_PART_11_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_11_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART11_REGISTER_PART_11                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_11    );
+REG64_FLD( PU_OTPROM1_ECID_PART11_REGISTER_PART_11_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_11_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART12_REGISTER_PART_12                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_12    );
+REG64_FLD( PU_OTPROM0_ECID_PART12_REGISTER_PART_12_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_12_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART12_REGISTER_PART_12                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_12    );
+REG64_FLD( PU_OTPROM1_ECID_PART12_REGISTER_PART_12_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_12_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART13_REGISTER_PART_13                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_13    );
+REG64_FLD( PU_OTPROM0_ECID_PART13_REGISTER_PART_13_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_13_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART13_REGISTER_PART_13                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_13    );
+REG64_FLD( PU_OTPROM1_ECID_PART13_REGISTER_PART_13_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_13_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART14_REGISTER_PART_14                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_14    );
+REG64_FLD( PU_OTPROM0_ECID_PART14_REGISTER_PART_14_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_14_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART14_REGISTER_PART_14                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_14    );
+REG64_FLD( PU_OTPROM1_ECID_PART14_REGISTER_PART_14_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_14_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART15_REGISTER_PART_15                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_15    );
+REG64_FLD( PU_OTPROM0_ECID_PART15_REGISTER_PART_15_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_15_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART15_REGISTER_PART_15                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_15    );
+REG64_FLD( PU_OTPROM1_ECID_PART15_REGISTER_PART_15_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_15_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART16_REGISTER_PART_16                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_16    );
+REG64_FLD( PU_OTPROM0_ECID_PART16_REGISTER_PART_16_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_16_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART16_REGISTER_PART_16                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_16    );
+REG64_FLD( PU_OTPROM1_ECID_PART16_REGISTER_PART_16_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_16_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART17_REGISTER_PART_17                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_17    );
+REG64_FLD( PU_OTPROM0_ECID_PART17_REGISTER_PART_17_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_17_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART17_REGISTER_PART_17                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_17    );
+REG64_FLD( PU_OTPROM1_ECID_PART17_REGISTER_PART_17_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_17_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART18_REGISTER_PART_18                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_18    );
+REG64_FLD( PU_OTPROM0_ECID_PART18_REGISTER_PART_18_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_18_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART18_REGISTER_PART_18                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_18    );
+REG64_FLD( PU_OTPROM1_ECID_PART18_REGISTER_PART_18_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_18_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART19_REGISTER_PART_19                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_19    );
+REG64_FLD( PU_OTPROM0_ECID_PART19_REGISTER_PART_19_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_19_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART19_REGISTER_PART_19                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_19    );
+REG64_FLD( PU_OTPROM1_ECID_PART19_REGISTER_PART_19_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_19_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART1_REGISTER_PART_1                   , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_1     );
+REG64_FLD( PU_OTPROM0_ECID_PART1_REGISTER_PART_1_LEN               , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_1_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART1_REGISTER_PART_1                   , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_1     );
+REG64_FLD( PU_OTPROM1_ECID_PART1_REGISTER_PART_1_LEN               , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_1_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART20_REGISTER_PART_20                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_20    );
+REG64_FLD( PU_OTPROM0_ECID_PART20_REGISTER_PART_20_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_20_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART20_REGISTER_PART_20                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_20    );
+REG64_FLD( PU_OTPROM1_ECID_PART20_REGISTER_PART_20_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_20_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART21_REGISTER_PART_21                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_21    );
+REG64_FLD( PU_OTPROM0_ECID_PART21_REGISTER_PART_21_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_21_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART21_REGISTER_PART_21                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_21    );
+REG64_FLD( PU_OTPROM1_ECID_PART21_REGISTER_PART_21_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_21_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART22_REGISTER_PART_22                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_22    );
+REG64_FLD( PU_OTPROM0_ECID_PART22_REGISTER_PART_22_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_22_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART22_REGISTER_PART_22                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_22    );
+REG64_FLD( PU_OTPROM1_ECID_PART22_REGISTER_PART_22_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_22_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART23_REGISTER_PART_23                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_23    );
+REG64_FLD( PU_OTPROM0_ECID_PART23_REGISTER_PART_23_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_23_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART23_REGISTER_PART_23                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_23    );
+REG64_FLD( PU_OTPROM1_ECID_PART23_REGISTER_PART_23_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_23_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART24_REGISTER_PART_24                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_24    );
+REG64_FLD( PU_OTPROM0_ECID_PART24_REGISTER_PART_24_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_24_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART24_REGISTER_PART_24                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_24    );
+REG64_FLD( PU_OTPROM1_ECID_PART24_REGISTER_PART_24_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_24_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART25_REGISTER_PART_25                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_25    );
+REG64_FLD( PU_OTPROM0_ECID_PART25_REGISTER_PART_25_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_25_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART25_REGISTER_PART_25                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_25    );
+REG64_FLD( PU_OTPROM1_ECID_PART25_REGISTER_PART_25_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_25_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART26_REGISTER_PART_26                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_26    );
+REG64_FLD( PU_OTPROM0_ECID_PART26_REGISTER_PART_26_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_26_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART26_REGISTER_PART_26                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_26    );
+REG64_FLD( PU_OTPROM1_ECID_PART26_REGISTER_PART_26_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_26_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART27_REGISTER_PART_27                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_27    );
+REG64_FLD( PU_OTPROM0_ECID_PART27_REGISTER_PART_27_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_27_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART27_REGISTER_PART_27                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_27    );
+REG64_FLD( PU_OTPROM1_ECID_PART27_REGISTER_PART_27_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_27_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART28_REGISTER_PART_28                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_28    );
+REG64_FLD( PU_OTPROM0_ECID_PART28_REGISTER_PART_28_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_28_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART28_REGISTER_PART_28                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_28    );
+REG64_FLD( PU_OTPROM1_ECID_PART28_REGISTER_PART_28_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_28_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART29_REGISTER_PART_29                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_29    );
+REG64_FLD( PU_OTPROM0_ECID_PART29_REGISTER_PART_29_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_29_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART29_REGISTER_PART_29                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_29    );
+REG64_FLD( PU_OTPROM1_ECID_PART29_REGISTER_PART_29_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_29_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART2_REGISTER_PART_2                   , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_2     );
+REG64_FLD( PU_OTPROM0_ECID_PART2_REGISTER_PART_2_LEN               , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_2_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART2_REGISTER_PART_2                   , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_2     );
+REG64_FLD( PU_OTPROM1_ECID_PART2_REGISTER_PART_2_LEN               , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_2_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART30_REGISTER_PART_30                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_30    );
+REG64_FLD( PU_OTPROM0_ECID_PART30_REGISTER_PART_30_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_30_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART30_REGISTER_PART_30                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_30    );
+REG64_FLD( PU_OTPROM1_ECID_PART30_REGISTER_PART_30_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_30_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART31_REGISTER_PART_31                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_31    );
+REG64_FLD( PU_OTPROM0_ECID_PART31_REGISTER_PART_31_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_31_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART31_REGISTER_PART_31                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_31    );
+REG64_FLD( PU_OTPROM1_ECID_PART31_REGISTER_PART_31_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_31_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART32_REGISTER_PART_32                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_32    );
+REG64_FLD( PU_OTPROM0_ECID_PART32_REGISTER_PART_32_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_32_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART32_REGISTER_PART_32                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_32    );
+REG64_FLD( PU_OTPROM1_ECID_PART32_REGISTER_PART_32_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_32_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART33_REGISTER_PART_33                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_33    );
+REG64_FLD( PU_OTPROM0_ECID_PART33_REGISTER_PART_33_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_33_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART33_REGISTER_PART_33                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_33    );
+REG64_FLD( PU_OTPROM1_ECID_PART33_REGISTER_PART_33_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_33_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART34_REGISTER_PART_34                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_34    );
+REG64_FLD( PU_OTPROM0_ECID_PART34_REGISTER_PART_34_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_34_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART34_REGISTER_PART_34                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_34    );
+REG64_FLD( PU_OTPROM1_ECID_PART34_REGISTER_PART_34_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_34_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART35_REGISTER_PART_35                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_35    );
+REG64_FLD( PU_OTPROM0_ECID_PART35_REGISTER_PART_35_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_35_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART35_REGISTER_PART_35                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_35    );
+REG64_FLD( PU_OTPROM1_ECID_PART35_REGISTER_PART_35_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_35_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART36_REGISTER_PART_36                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_36    );
+REG64_FLD( PU_OTPROM0_ECID_PART36_REGISTER_PART_36_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_36_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART36_REGISTER_PART_36                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_36    );
+REG64_FLD( PU_OTPROM1_ECID_PART36_REGISTER_PART_36_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_36_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART37_REGISTER_PART_37                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_37    );
+REG64_FLD( PU_OTPROM0_ECID_PART37_REGISTER_PART_37_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_37_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART37_REGISTER_PART_37                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_37    );
+REG64_FLD( PU_OTPROM1_ECID_PART37_REGISTER_PART_37_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_37_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART38_REGISTER_PART_38                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_38    );
+REG64_FLD( PU_OTPROM0_ECID_PART38_REGISTER_PART_38_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_38_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART38_REGISTER_PART_38                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_38    );
+REG64_FLD( PU_OTPROM1_ECID_PART38_REGISTER_PART_38_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_38_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART39_REGISTER_PART_39                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_39    );
+REG64_FLD( PU_OTPROM0_ECID_PART39_REGISTER_PART_39_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_39_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART39_REGISTER_PART_39                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_39    );
+REG64_FLD( PU_OTPROM1_ECID_PART39_REGISTER_PART_39_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_39_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART3_REGISTER_PART_3                   , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_3     );
+REG64_FLD( PU_OTPROM0_ECID_PART3_REGISTER_PART_3_LEN               , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_3_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART3_REGISTER_PART_3                   , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_3     );
+REG64_FLD( PU_OTPROM1_ECID_PART3_REGISTER_PART_3_LEN               , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_3_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART40_REGISTER_PART_40                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_40    );
+REG64_FLD( PU_OTPROM0_ECID_PART40_REGISTER_PART_40_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_40_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART40_REGISTER_PART_40                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_40    );
+REG64_FLD( PU_OTPROM1_ECID_PART40_REGISTER_PART_40_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_40_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART41_REGISTER_PART_41                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_41    );
+REG64_FLD( PU_OTPROM0_ECID_PART41_REGISTER_PART_41_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_41_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART41_REGISTER_PART_41                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_41    );
+REG64_FLD( PU_OTPROM1_ECID_PART41_REGISTER_PART_41_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_41_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART42_REGISTER_PART_42                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_42    );
+REG64_FLD( PU_OTPROM0_ECID_PART42_REGISTER_PART_42_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_42_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART42_REGISTER_PART_42                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_42    );
+REG64_FLD( PU_OTPROM1_ECID_PART42_REGISTER_PART_42_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_42_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART43_REGISTER_PART_43                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_43    );
+REG64_FLD( PU_OTPROM0_ECID_PART43_REGISTER_PART_43_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_43_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART43_REGISTER_PART_43                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_43    );
+REG64_FLD( PU_OTPROM1_ECID_PART43_REGISTER_PART_43_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_43_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART44_REGISTER_PART_44                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_44    );
+REG64_FLD( PU_OTPROM0_ECID_PART44_REGISTER_PART_44_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_44_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART44_REGISTER_PART_44                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_44    );
+REG64_FLD( PU_OTPROM1_ECID_PART44_REGISTER_PART_44_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_44_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART45_REGISTER_PART_45                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_45    );
+REG64_FLD( PU_OTPROM0_ECID_PART45_REGISTER_PART_45_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_45_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART45_REGISTER_PART_45                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_45    );
+REG64_FLD( PU_OTPROM1_ECID_PART45_REGISTER_PART_45_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_45_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART46_REGISTER_PART_46                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_46    );
+REG64_FLD( PU_OTPROM0_ECID_PART46_REGISTER_PART_46_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_46_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART46_REGISTER_PART_46                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_46    );
+REG64_FLD( PU_OTPROM1_ECID_PART46_REGISTER_PART_46_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_46_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART47_REGISTER_PART_47                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_47    );
+REG64_FLD( PU_OTPROM0_ECID_PART47_REGISTER_PART_47_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_47_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART47_REGISTER_PART_47                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_47    );
+REG64_FLD( PU_OTPROM1_ECID_PART47_REGISTER_PART_47_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_47_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART48_REGISTER_PART_48                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_48    );
+REG64_FLD( PU_OTPROM0_ECID_PART48_REGISTER_PART_48_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_48_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART48_REGISTER_PART_48                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_48    );
+REG64_FLD( PU_OTPROM1_ECID_PART48_REGISTER_PART_48_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_48_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART49_REGISTER_PART_49                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_49    );
+REG64_FLD( PU_OTPROM0_ECID_PART49_REGISTER_PART_49_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_49_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART49_REGISTER_PART_49                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_49    );
+REG64_FLD( PU_OTPROM1_ECID_PART49_REGISTER_PART_49_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_49_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART4_REGISTER_PART_4                   , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_4     );
+REG64_FLD( PU_OTPROM0_ECID_PART4_REGISTER_PART_4_LEN               , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_4_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART4_REGISTER_PART_4                   , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_4     );
+REG64_FLD( PU_OTPROM1_ECID_PART4_REGISTER_PART_4_LEN               , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_4_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART50_REGISTER_PART_50                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_50    );
+REG64_FLD( PU_OTPROM0_ECID_PART50_REGISTER_PART_50_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_50_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART50_REGISTER_PART_50                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_50    );
+REG64_FLD( PU_OTPROM1_ECID_PART50_REGISTER_PART_50_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_50_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART51_REGISTER_PART_51                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_51    );
+REG64_FLD( PU_OTPROM0_ECID_PART51_REGISTER_PART_51_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_51_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART51_REGISTER_PART_51                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_51    );
+REG64_FLD( PU_OTPROM1_ECID_PART51_REGISTER_PART_51_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_51_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART52_REGISTER_PART_52                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_52    );
+REG64_FLD( PU_OTPROM0_ECID_PART52_REGISTER_PART_52_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_52_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART52_REGISTER_PART_52                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_52    );
+REG64_FLD( PU_OTPROM1_ECID_PART52_REGISTER_PART_52_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_52_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART53_REGISTER_PART_53                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_53    );
+REG64_FLD( PU_OTPROM0_ECID_PART53_REGISTER_PART_53_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_53_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART53_REGISTER_PART_53                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_53    );
+REG64_FLD( PU_OTPROM1_ECID_PART53_REGISTER_PART_53_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_53_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART54_REGISTER_PART_54                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_54    );
+REG64_FLD( PU_OTPROM0_ECID_PART54_REGISTER_PART_54_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_54_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART54_REGISTER_PART_54                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_54    );
+REG64_FLD( PU_OTPROM1_ECID_PART54_REGISTER_PART_54_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_54_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART55_REGISTER_PART_55                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_55    );
+REG64_FLD( PU_OTPROM0_ECID_PART55_REGISTER_PART_55_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_55_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART55_REGISTER_PART_55                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_55    );
+REG64_FLD( PU_OTPROM1_ECID_PART55_REGISTER_PART_55_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_55_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART56_REGISTER_PART_56                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_56    );
+REG64_FLD( PU_OTPROM0_ECID_PART56_REGISTER_PART_56_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_56_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART56_REGISTER_PART_56                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_56    );
+REG64_FLD( PU_OTPROM1_ECID_PART56_REGISTER_PART_56_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_56_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART57_REGISTER_PART_57                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_57    );
+REG64_FLD( PU_OTPROM0_ECID_PART57_REGISTER_PART_57_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_57_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART57_REGISTER_PART_57                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_57    );
+REG64_FLD( PU_OTPROM1_ECID_PART57_REGISTER_PART_57_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_57_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART58_REGISTER_PART_58                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_58    );
+REG64_FLD( PU_OTPROM0_ECID_PART58_REGISTER_PART_58_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_58_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART58_REGISTER_PART_58                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_58    );
+REG64_FLD( PU_OTPROM1_ECID_PART58_REGISTER_PART_58_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_58_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART59_REGISTER_PART_59                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_59    );
+REG64_FLD( PU_OTPROM0_ECID_PART59_REGISTER_PART_59_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_59_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART59_REGISTER_PART_59                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_59    );
+REG64_FLD( PU_OTPROM1_ECID_PART59_REGISTER_PART_59_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_59_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART5_REGISTER_PART_5                   , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_5     );
+REG64_FLD( PU_OTPROM0_ECID_PART5_REGISTER_PART_5_LEN               , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_5_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART5_REGISTER_PART_5                   , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_5     );
+REG64_FLD( PU_OTPROM1_ECID_PART5_REGISTER_PART_5_LEN               , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_5_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART60_REGISTER_PART_60                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_60    );
+REG64_FLD( PU_OTPROM0_ECID_PART60_REGISTER_PART_60_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_60_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART60_REGISTER_PART_60                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_60    );
+REG64_FLD( PU_OTPROM1_ECID_PART60_REGISTER_PART_60_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_60_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART61_REGISTER_PART_61                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_61    );
+REG64_FLD( PU_OTPROM0_ECID_PART61_REGISTER_PART_61_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_61_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART61_REGISTER_PART_61                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_61    );
+REG64_FLD( PU_OTPROM1_ECID_PART61_REGISTER_PART_61_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_61_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART62_REGISTER_PART_62                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_62    );
+REG64_FLD( PU_OTPROM0_ECID_PART62_REGISTER_PART_62_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_62_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART62_REGISTER_PART_62                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_62    );
+REG64_FLD( PU_OTPROM1_ECID_PART62_REGISTER_PART_62_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_62_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART63_REGISTER_PART_63                 , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_63    );
+REG64_FLD( PU_OTPROM0_ECID_PART63_REGISTER_PART_63_LEN             , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_63_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART63_REGISTER_PART_63                 , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_63    );
+REG64_FLD( PU_OTPROM1_ECID_PART63_REGISTER_PART_63_LEN             , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_63_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART6_REGISTER_PART_6                   , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_6     );
+REG64_FLD( PU_OTPROM0_ECID_PART6_REGISTER_PART_6_LEN               , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_6_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART6_REGISTER_PART_6                   , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_6     );
+REG64_FLD( PU_OTPROM1_ECID_PART6_REGISTER_PART_6_LEN               , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_6_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART7_REGISTER_PART_7                   , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_7     );
+REG64_FLD( PU_OTPROM0_ECID_PART7_REGISTER_PART_7_LEN               , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_7_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART7_REGISTER_PART_7                   , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_7     );
+REG64_FLD( PU_OTPROM1_ECID_PART7_REGISTER_PART_7_LEN               , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_7_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART8_REGISTER_PART_8                   , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_8     );
+REG64_FLD( PU_OTPROM0_ECID_PART8_REGISTER_PART_8_LEN               , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_8_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART8_REGISTER_PART_8                   , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_8     );
+REG64_FLD( PU_OTPROM1_ECID_PART8_REGISTER_PART_8_LEN               , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_8_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART9_REGISTER_PART_9                   , 0   ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_9     );
+REG64_FLD( PU_OTPROM0_ECID_PART9_REGISTER_PART_9_LEN               , 64  ,
+           SH_UNT_PU_OTPROM0, SH_ACS_SCOM     , SH_FLD_PART_9_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART9_REGISTER_PART_9                   , 0   ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_9     );
+REG64_FLD( PU_OTPROM1_ECID_PART9_REGISTER_PART_9_LEN               , 64  ,
+           SH_UNT_PU_OTPROM1, SH_ACS_SCOM     , SH_FLD_PART_9_LEN );
+
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID              , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_LPID );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN          , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_LPID_LEN );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID               , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_PID );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN           , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_PID_LEN );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID               , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_TID );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN           , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_TID_LEN );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE            , 63  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_ENABLE );
+
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_BAR_PRIORITY                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY   );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN               , 46  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_LEN );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE              , 54  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_SIZE );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN          , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_SIZE_LEN );
+
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET      , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_READ_OFFSET );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_READ_OFFSET_LEN );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED           , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_QUEUED );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN       , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_QUEUED_LEN );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX           , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_PRIMAX );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX_LEN       , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_PRIMAX_LEN );
+
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID              , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_LPID );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN          , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_LPID_LEN );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID               , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_PID );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN           , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_PID_LEN );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID               , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_TID );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN           , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_TID_LEN );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE            , 63  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_ENABLE );
+
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_BAR_PRIORITY                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY   );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN               , 46  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_LEN );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE              , 54  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_SIZE );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN          , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_SIZE_LEN );
+
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET      , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_READ_OFFSET );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_READ_OFFSET_LEN );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED           , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_QUEUED );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN       , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_QUEUED_LEN );
+
+REG64_FLD( PU_EFT_MAX_BYTE_CNT_LIMIT                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LIMIT      );
+REG64_FLD( PU_EFT_MAX_BYTE_CNT_LIMIT_LEN                           , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LIMIT_LEN  );
+REG64_FLD( PU_EFT_MAX_BYTE_CNT_SRC_DDE                             , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SRC_DDE    );
+REG64_FLD( PU_EFT_MAX_BYTE_CNT_SRC_DDE_LEN                         , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SRC_DDE_LEN );
+REG64_FLD( PU_EFT_MAX_BYTE_CNT_TARGET_DDE                          , 13  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_TARGET_DDE );
+REG64_FLD( PU_EFT_MAX_BYTE_CNT_TARGET_DDE_LEN                      , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_TARGET_DDE_LEN );
+
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_0_OUT                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE1_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_0_OUT                      , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE2_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_0_OUT                      , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE1_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_0_OUT                      , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE2_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_1_OUT                      , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE1_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_1_OUT                      , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE2_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_1_OUT                      , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE1_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_1_OUT                      , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE2_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_2_OUT                      , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE1_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_2_OUT                      , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE2_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_2_OUT                      , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE1_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_2_OUT                      , 11  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE2_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_3_OUT                      , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE1_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_3_OUT                      , 13  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE2_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_3_OUT                      , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE1_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_3_OUT                      , 15  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE2_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_4_OUT                      , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE1_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_4_OUT                      , 17  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE2_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_4_OUT                      , 18  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE1_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_4_OUT                      , 19  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE2_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_5_OUT                      , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE1_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_5_OUT                      , 21  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE2_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_5_OUT                      , 22  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE1_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_5_OUT                      , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE2_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_6_OUT                      , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE1_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_6_OUT                      , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE2_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_6_OUT                      , 26  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE1_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_6_OUT                      , 27  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE2_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_7_OUT                      , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE1_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_7_OUT                      , 29  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE2_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_7_OUT                      , 30  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE1_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_7_OUT                      , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE2_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_DROP_COUNTER_FULL              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DROP_COUNTER_FULL );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_INTERNAL_ERROR                 , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INTERNAL_ERROR );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_SCOM_ERROR                     , 34  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SCOM_ERROR );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_PARITY_ERROR                   , 35  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PARITY_ERROR );
+
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_0_OUT                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE1_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_0_OUT                      , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE2_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_0_OUT                      , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE1_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_0_OUT                      , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE2_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_1_OUT                      , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE1_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_1_OUT                      , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE2_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_1_OUT                      , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE1_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_1_OUT                      , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE2_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_2_OUT                      , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE1_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_2_OUT                      , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE2_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_2_OUT                      , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE1_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_2_OUT                      , 11  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE2_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_3_OUT                      , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE1_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_3_OUT                      , 13  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE2_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_3_OUT                      , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE1_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_3_OUT                      , 15  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE2_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_4_OUT                      , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE1_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_4_OUT                      , 17  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE2_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_4_OUT                      , 18  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE1_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_4_OUT                      , 19  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE2_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_5_OUT                      , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE1_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_5_OUT                      , 21  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE2_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_5_OUT                      , 22  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE1_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_5_OUT                      , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE2_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_6_OUT                      , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE1_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_6_OUT                      , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE2_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_6_OUT                      , 26  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE1_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_6_OUT                      , 27  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE2_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_7_OUT                      , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE1_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_7_OUT                      , 29  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CE2_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_7_OUT                      , 30  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE1_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_7_OUT                      , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UE2_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_DROP_COUNTER_FULL              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DROP_COUNTER_FULL );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_INTERNAL_ERROR                 , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INTERNAL_ERROR );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_SCOM_ERROR                     , 34  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SCOM_ERROR );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_PARITY_ERROR                   , 35  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PARITY_ERROR );
+
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_0_OUT                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE1_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_0_OUT                         , 1   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE2_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_0_OUT                         , 2   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE1_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_0_OUT                         , 3   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE2_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_1_OUT                         , 4   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE1_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_1_OUT                         , 5   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE2_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_1_OUT                         , 6   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE1_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_1_OUT                         , 7   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE2_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_2_OUT                         , 8   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE1_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_2_OUT                         , 9   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE2_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_2_OUT                         , 10  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE1_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_2_OUT                         , 11  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE2_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_3_OUT                         , 12  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE1_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_3_OUT                         , 13  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE2_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_3_OUT                         , 14  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE1_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_3_OUT                         , 15  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE2_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_4_OUT                         , 16  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE1_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_4_OUT                         , 17  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE2_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_4_OUT                         , 18  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE1_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_4_OUT                         , 19  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE2_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_5_OUT                         , 20  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE1_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_5_OUT                         , 21  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE2_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_5_OUT                         , 22  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE1_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_5_OUT                         , 23  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE2_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_6_OUT                         , 24  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE1_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_6_OUT                         , 25  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE2_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_6_OUT                         , 26  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE1_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_6_OUT                         , 27  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE2_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_7_OUT                         , 28  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE1_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_7_OUT                         , 29  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE2_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_7_OUT                         , 30  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE1_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_7_OUT                         , 31  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE2_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_DROP_COUNTER_FULL                 , 32  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DROP_COUNTER_FULL );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_INTERNAL_ERROR                    , 33  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_ERROR );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_SCOM_ERROR                        , 34  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERROR );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_PARITY_ERROR                      , 35  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERROR );
+
+REG64_FLD( PU_EHHCA_FIR_REG_CE1_0_OUT                              , 0   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE1_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE2_0_OUT                              , 1   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE2_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE1_0_OUT                              , 2   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE1_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE2_0_OUT                              , 3   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE2_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE1_1_OUT                              , 4   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE1_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE2_1_OUT                              , 5   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE2_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE1_1_OUT                              , 6   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE1_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE2_1_OUT                              , 7   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE2_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE1_2_OUT                              , 8   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE1_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE2_2_OUT                              , 9   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE2_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE1_2_OUT                              , 10  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE1_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE2_2_OUT                              , 11  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE2_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE1_3_OUT                              , 12  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE1_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE2_3_OUT                              , 13  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE2_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE1_3_OUT                              , 14  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE1_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE2_3_OUT                              , 15  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE2_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE1_4_OUT                              , 16  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE1_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE2_4_OUT                              , 17  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE2_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE1_4_OUT                              , 18  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE1_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE2_4_OUT                              , 19  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE2_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE1_5_OUT                              , 20  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE1_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE2_5_OUT                              , 21  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE2_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE1_5_OUT                              , 22  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE1_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE2_5_OUT                              , 23  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE2_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE1_6_OUT                              , 24  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE1_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE2_6_OUT                              , 25  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE2_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE1_6_OUT                              , 26  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE1_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE2_6_OUT                              , 27  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE2_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE1_7_OUT                              , 28  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE1_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE2_7_OUT                              , 29  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CE2_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE1_7_OUT                              , 30  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE1_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE2_7_OUT                              , 31  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UE2_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_DROP_COUNTER_FULL                      , 32  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DROP_COUNTER_FULL );
+REG64_FLD( PU_EHHCA_FIR_REG_INTERNAL_ERROR                         , 33  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_ERROR );
+REG64_FLD( PU_EHHCA_FIR_REG_SCOM_ERROR                             , 34  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERROR );
+REG64_FLD( PU_EHHCA_FIR_REG_PARITY_ERROR                           , 35  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERROR );
+
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_RATE                         , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RATE       );
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_RATE_LEN                     , 4   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_W0_COUNT                     , 4   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_W1_COUNT                     , 16  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_R0_COUNT                     , 28  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_R1_COUNT                     , 40  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_R2_COUNT                     , 52  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_RATE                         , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RATE       );
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_RATE_LEN                     , 4   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_W0_COUNT                     , 4   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_W1_COUNT                     , 16  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_R0_COUNT                     , 28  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_R1_COUNT                     , 40  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_R2_COUNT                     , 52  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_RATE                         , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RATE       );
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_RATE_LEN                     , 4   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_W0_COUNT                     , 4   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_W1_COUNT                     , 16  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_R0_COUNT                     , 28  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_R1_COUNT                     , 40  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_R2_COUNT                     , 52  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_RATE                         , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RATE       );
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_RATE_LEN                     , 4   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_W0_COUNT                     , 4   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_W1_COUNT                     , 16  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_R0_COUNT                     , 28  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_R1_COUNT                     , 40  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_R2_COUNT                     , 52  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_RATE                         , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RATE       );
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_RATE_LEN                     , 4   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_W0_COUNT                     , 4   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_W1_COUNT                     , 16  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_R0_COUNT                     , 28  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_R1_COUNT                     , 40  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_R2_COUNT                     , 52  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_RATE                         , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RATE       );
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_RATE_LEN                     , 4   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_W0_COUNT                     , 4   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_W1_COUNT                     , 16  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_R0_COUNT                     , 28  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_R1_COUNT                     , 40  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_R2_COUNT                     , 52  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_RATE                         , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RATE       );
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_RATE_LEN                     , 4   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_W0_COUNT                     , 4   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_W1_COUNT                     , 16  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_R0_COUNT                     , 28  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_R1_COUNT                     , 40  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_R2_COUNT                     , 52  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_RATE                         , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RATE       );
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_RATE_LEN                     , 4   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_W0_COUNT                     , 4   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_W1_COUNT                     , 16  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_R0_COUNT                     , 28  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_R1_COUNT                     , 40  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_R2_COUNT                     , 52  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_RATE                         , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RATE       );
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_RATE_LEN                     , 4   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_W0_COUNT                     , 4   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_W1_COUNT                     , 16  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_R0_COUNT                     , 28  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_R1_COUNT                     , 40  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_R2_COUNT                     , 52  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_RATE                         , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RATE       );
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_RATE_LEN                     , 4   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_W0_COUNT                     , 4   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_W1_COUNT                     , 16  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_R0_COUNT                     , 28  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_R1_COUNT                     , 40  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_R2_COUNT                     , 52  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_RATE                         , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RATE       );
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_RATE_LEN                     , 4   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_W0_COUNT                     , 4   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_W1_COUNT                     , 16  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_R0_COUNT                     , 28  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_R1_COUNT                     , 40  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_R2_COUNT                     , 52  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_RATE                         , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RATE       );
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_RATE_LEN                     , 4   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_W0_COUNT                     , 4   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_W1_COUNT                     , 16  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_R0_COUNT                     , 28  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_R1_COUNT                     , 40  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_R2_COUNT                     , 52  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_ERAT_STATUS_CONTROL_FORCE_BYPASS                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FORCE_BYPASS );
+REG64_FLD( PU_ERAT_STATUS_CONTROL_IDLE                             , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IDLE       );
+REG64_FLD( PU_ERAT_STATUS_CONTROL_VALID_ENTRY                      , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_VALID_ENTRY );
+REG64_FLD( PU_ERAT_STATUS_CONTROL_DISABLE_HIT_UNDER_BARRIER        , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_HIT_UNDER_BARRIER );
+REG64_FLD( PU_ERAT_STATUS_CONTROL_SPECULATIVE_CHECKIN_COUNT        , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SPECULATIVE_CHECKIN_COUNT );
+REG64_FLD( PU_ERAT_STATUS_CONTROL_SPECULATIVE_CHECKIN_COUNT_LEN    , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SPECULATIVE_CHECKIN_COUNT_LEN );
+
+REG64_FLD( PU_NPU1_SM2_ERROR1_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM2_ERROR1_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_NTL0_ERROR1_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_NTL0_ERROR1_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM3_ERROR1_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM3_ERROR1_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_NTL1_ERROR1_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_NTL1_ERROR1_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_NTL1_ERROR1_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_NTL1_ERROR1_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM1_ERROR1_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM1_ERROR1_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_NTL1_ERROR1_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_NTL1_ERROR1_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM2_ERROR1_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM2_ERROR1_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM1_ERROR1_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM1_ERROR1_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_NTL0_ERROR1_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_NTL0_ERROR1_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM0_ERROR1_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM0_ERROR1_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_NTL0_ERROR1_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_NTL0_ERROR1_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM3_ERROR1_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM3_ERROR1_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM3_ERROR1_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM3_ERROR1_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM2_ERROR1_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM2_ERROR1_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM1_ERROR1_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM1_ERROR1_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM0_ERROR1_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM0_ERROR1_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM0_ERROR1_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM0_ERROR1_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM2_ERROR2_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM2_ERROR2_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_NTL0_ERROR2_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_NTL0_ERROR2_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM3_ERROR2_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM3_ERROR2_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_NTL1_ERROR2_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_NTL1_ERROR2_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_NTL1_ERROR2_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_NTL1_ERROR2_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM1_ERROR2_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM1_ERROR2_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_NTL1_ERROR2_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_NTL1_ERROR2_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM2_ERROR2_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM2_ERROR2_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_CTL_ERROR2_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_CTL_ERROR2_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM1_ERROR2_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM1_ERROR2_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_NTL0_ERROR2_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_NTL0_ERROR2_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM0_ERROR2_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM0_ERROR2_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_NTL0_ERROR2_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_NTL0_ERROR2_IDIAL_LEN                           , 64  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM3_ERROR2_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM3_ERROR2_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM3_ERROR2_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM3_ERROR2_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM2_ERROR2_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM2_ERROR2_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_CTL_ERROR2_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_CTL_ERROR2_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM1_ERROR2_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM1_ERROR2_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM0_ERROR2_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM0_ERROR2_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_CTL_ERROR2_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_CTL_ERROR2_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM0_ERROR2_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM0_ERROR2_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_ESB_CI_BASE_BASE                                     , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BASE       );
+REG64_FLD( PU_ESB_CI_BASE_BASE_LEN                                 , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BASE_LEN   );
+REG64_FLD( PU_ESB_CI_BASE_VALID                                    , 63  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_VALID      );
+
+REG64_FLD( PU_ESB_NOTIFY_ADDR                                      , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADDR       );
+REG64_FLD( PU_ESB_NOTIFY_ADDR_LEN                                  , 53  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_ESB_NOTIFY_VALID                                     , 63  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_VALID      );
+
+REG64_FLD( PU_EXPORT_REGL_CTRL_TP_NX_ALLOW_CRYPTO_DC               , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TP_NX_ALLOW_CRYPTO_DC );
+REG64_FLD( PU_EXPORT_REGL_CTRL_TP_EXSD_FULLSPEED_DC                , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TP_EXSD_FULLSPEED_DC );
+REG64_FLD( PU_EXPORT_REGL_CTRL_TP_EX_FUSE_VMX_CRYPTO_DIS_DC        , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TP_EX_FUSE_VMX_CRYPTO_DIS_DC );
+REG64_FLD( PU_EXPORT_REGL_CTRL_TP_EX_FUSE_FP_THROTTLE_EN_DC        , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TP_EX_FUSE_FP_THROTTLE_EN_DC );
+
+REG64_FLD( PU_EXTENDED_STATUS_B_MSM_CURR_STATE_0                   , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MSM_CURR_STATE_0 );
+REG64_FLD( PU_EXTENDED_STATUS_B_MSM_CURR_STATE_0_LEN               , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MSM_CURR_STATE_0_LEN );
+REG64_FLD( PU_EXTENDED_STATUS_B_SELF_BUSY_0                        , 25  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SELF_BUSY_0 );
+REG64_FLD( PU_EXTENDED_STATUS_B_PEEK_DATA1_0                       , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_EXTENDED_STATUS_B_PEEK_DATA1_0_LEN                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_EXTENDED_STATUS_B_LBUS_PARITY_ERR1_0                 , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_EXTENDED_STATUS_C_MSM_CURR_STATE_1                   , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MSM_CURR_STATE_1 );
+REG64_FLD( PU_EXTENDED_STATUS_C_MSM_CURR_STATE_1_LEN               , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MSM_CURR_STATE_1_LEN );
+REG64_FLD( PU_EXTENDED_STATUS_C_SELF_BUSY_1                        , 25  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SELF_BUSY_1 );
+REG64_FLD( PU_EXTENDED_STATUS_C_PEEK_DATA1_1                       , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_EXTENDED_STATUS_C_PEEK_DATA1_1_LEN                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_EXTENDED_STATUS_C_LBUS_PARITY_ERR1_1                 , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_EXTENDED_STATUS_D_MSM_CURR_STATE_2                   , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MSM_CURR_STATE_2 );
+REG64_FLD( PU_EXTENDED_STATUS_D_MSM_CURR_STATE_2_LEN               , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MSM_CURR_STATE_2_LEN );
+REG64_FLD( PU_EXTENDED_STATUS_D_SELF_BUSY_2                        , 25  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SELF_BUSY_2 );
+REG64_FLD( PU_EXTENDED_STATUS_D_PEEK_DATA1_2                       , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_EXTENDED_STATUS_D_PEEK_DATA1_2_LEN                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_EXTENDED_STATUS_D_LBUS_PARITY_ERR1_2                 , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_EXTENDED_STATUS_E_MSM_CURR_STATE_3                   , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MSM_CURR_STATE_3 );
+REG64_FLD( PU_EXTENDED_STATUS_E_MSM_CURR_STATE_3_LEN               , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MSM_CURR_STATE_3_LEN );
+REG64_FLD( PU_EXTENDED_STATUS_E_SELF_BUSY_3                        , 25  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SELF_BUSY_3 );
+REG64_FLD( PU_EXTENDED_STATUS_E_PEEK_DATA1_3                       , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_EXTENDED_STATUS_E_PEEK_DATA1_3_LEN                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_EXTENDED_STATUS_E_LBUS_PARITY_ERR1_3                 , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( PU_FIFO1_REGISTER_READ_B_FIFO_BITS_READ0_0              , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_BITS_READ0_0 );
+REG64_FLD( PU_FIFO1_REGISTER_READ_B_FIFO_BITS_READ0_0_LEN          , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_BITS_READ0_0_LEN );
+REG64_FLD( PU_FIFO1_REGISTER_READ_B_PEEK_DATA1_0                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_FIFO1_REGISTER_READ_B_PEEK_DATA1_0_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_FIFO1_REGISTER_READ_B_LBUS_PARITY_ERR1_0             , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_FIFO1_REGISTER_READ_C_FIFO_BITS_READ0_1              , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_BITS_READ0_1 );
+REG64_FLD( PU_FIFO1_REGISTER_READ_C_FIFO_BITS_READ0_1_LEN          , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_BITS_READ0_1_LEN );
+REG64_FLD( PU_FIFO1_REGISTER_READ_C_PEEK_DATA1_1                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_FIFO1_REGISTER_READ_C_PEEK_DATA1_1_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_FIFO1_REGISTER_READ_C_LBUS_PARITY_ERR1_1             , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_FIFO1_REGISTER_READ_D_FIFO_BITS_READ0_2              , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_BITS_READ0_2 );
+REG64_FLD( PU_FIFO1_REGISTER_READ_D_FIFO_BITS_READ0_2_LEN          , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_BITS_READ0_2_LEN );
+REG64_FLD( PU_FIFO1_REGISTER_READ_D_PEEK_DATA1_2                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_FIFO1_REGISTER_READ_D_PEEK_DATA1_2_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_FIFO1_REGISTER_READ_D_LBUS_PARITY_ERR1_2             , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_FIFO1_REGISTER_READ_E_FIFO_BITS_READ0_3              , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_BITS_READ0_3 );
+REG64_FLD( PU_FIFO1_REGISTER_READ_E_FIFO_BITS_READ0_3_LEN          , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_BITS_READ0_3_LEN );
+REG64_FLD( PU_FIFO1_REGISTER_READ_E_PEEK_DATA1_3                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_FIFO1_REGISTER_READ_E_PEEK_DATA1_3_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_FIFO1_REGISTER_READ_E_LBUS_PARITY_ERR1_3             , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ0_0              , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_BITS_READ0_0 );
+REG64_FLD( PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ0_0_LEN          , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_BITS_READ0_0_LEN );
+REG64_FLD( PU_FIFO4_REGISTER_READ_B_PEEK_DATA1_0                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_FIFO4_REGISTER_READ_B_PEEK_DATA1_0_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_FIFO4_REGISTER_READ_B_LBUS_PARITY_ERR1_0             , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ0_1              , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_BITS_READ0_1 );
+REG64_FLD( PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ0_1_LEN          , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_BITS_READ0_1_LEN );
+REG64_FLD( PU_FIFO4_REGISTER_READ_C_PEEK_DATA1_1                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_FIFO4_REGISTER_READ_C_PEEK_DATA1_1_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_FIFO4_REGISTER_READ_C_LBUS_PARITY_ERR1_1             , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ0_2              , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_BITS_READ0_2 );
+REG64_FLD( PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ0_2_LEN          , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_BITS_READ0_2_LEN );
+REG64_FLD( PU_FIFO4_REGISTER_READ_D_PEEK_DATA1_2                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_FIFO4_REGISTER_READ_D_PEEK_DATA1_2_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_FIFO4_REGISTER_READ_D_LBUS_PARITY_ERR1_2             , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ0_3              , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_BITS_READ0_3 );
+REG64_FLD( PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ0_3_LEN          , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_BITS_READ0_3_LEN );
+REG64_FLD( PU_FIFO4_REGISTER_READ_E_PEEK_DATA1_3                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_FIFO4_REGISTER_READ_E_PEEK_DATA1_3_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_FIFO4_REGISTER_READ_E_LBUS_PARITY_ERR1_3             , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( PU_NPU_CTL_FIR_ACTION0_REG_ACTION0                      , 0   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM_RW  , SH_FLD_ACTION0    );
+REG64_FLD( PU_NPU_CTL_FIR_ACTION0_REG_ACTION0_LEN                  , 64  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM_RW  , SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_IOP1_FIR_ACTION0_REG_ACTION0                         , 0   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM_RO  , SH_FLD_ACTION0    );
+REG64_FLD( PU_IOP1_FIR_ACTION0_REG_ACTION0_LEN                     , 37  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM_RO  , SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_FIR_ACTION0_REG_ACTION0                              , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACTION0    );
+REG64_FLD( PU_FIR_ACTION0_REG_ACTION0_LEN                          , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_IOP0_FIR_ACTION0_REG_ACTION0                         , 0   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM_RO  , SH_FLD_ACTION0    );
+REG64_FLD( PU_IOP0_FIR_ACTION0_REG_ACTION0_LEN                     , 37  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM_RO  , SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_IOP2_FIR_ACTION0_REG_ACTION0                         , 0   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM_RO  , SH_FLD_ACTION0    );
+REG64_FLD( PU_IOP2_FIR_ACTION0_REG_ACTION0_LEN                     , 37  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM_RO  , SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_NPU_CTL_FIR_ACTION1_REG_ACTION1                      , 0   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM_RW  , SH_FLD_ACTION1    );
+REG64_FLD( PU_NPU_CTL_FIR_ACTION1_REG_ACTION1_LEN                  , 64  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM_RW  , SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_IOP1_FIR_ACTION1_REG_ACTION1                         , 0   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM_RO  , SH_FLD_ACTION1    );
+REG64_FLD( PU_IOP1_FIR_ACTION1_REG_ACTION1_LEN                     , 37  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM_RO  , SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_FIR_ACTION1_REG_ACTION1                              , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACTION1    );
+REG64_FLD( PU_FIR_ACTION1_REG_ACTION1_LEN                          , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_IOP0_FIR_ACTION1_REG_ACTION1                         , 0   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM_RO  , SH_FLD_ACTION1    );
+REG64_FLD( PU_IOP0_FIR_ACTION1_REG_ACTION1_LEN                     , 37  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM_RO  , SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_IOP2_FIR_ACTION1_REG_ACTION1                         , 0   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM_RO  , SH_FLD_ACTION1    );
+REG64_FLD( PU_IOP2_FIR_ACTION1_REG_ACTION1_LEN                     , 37  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM_RO  , SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_0_ERR                     , 0   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_0_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_1_ERR                     , 1   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_1_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_2_ERR                     , 2   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_2_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_3_ERR                     , 3   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_3_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_4_ERR                     , 4   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_4_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_5_ERR                     , 5   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_5_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_6_ERR                     , 6   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_6_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_7_ERR                     , 7   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_7_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_8_ERR                     , 8   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_8_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_9_ERR                     , 9   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_9_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_10_ERR                    , 10  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_10_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_11_ERR                    , 11  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_11_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_12_ERR                    , 12  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_12_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_13_ERR                    , 13  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_13_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_14_ERR                    , 14  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_14_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_15_ERR                    , 15  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_15_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_16_ERR                    , 16  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_16_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_17_ERR                    , 17  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_17_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_18_ERR                    , 18  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_18_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_19_ERR                    , 19  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_19_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_20_ERR                    , 20  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_20_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_21_ERR                    , 21  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_21_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_22_ERR                    , 22  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_22_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_23_ERR                    , 23  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_23_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_24_ERR                    , 24  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_24_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_25_ERR                    , 25  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_25_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_26_ERR                    , 26  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_26_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_27_ERR                    , 27  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_27_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_28_ERR                    , 28  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_28_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_29_ERR                    , 29  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_29_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_30_ERR                    , 30  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_30_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_31_ERR                    , 31  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_31_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_32_ERR                    , 32  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_32_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_33_ERR                    , 33  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_33_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_34_ERR                    , 34  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_34_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_35_ERR                    , 35  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_35_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_36_ERR                    , 36  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_36_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_37_ERR                    , 37  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_37_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_38_ERR                    , 38  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_38_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_39_ERR                    , 39  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_39_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_40_ERR                    , 40  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_40_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_41_ERR                    , 41  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_41_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_42_ERR                    , 42  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_42_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_43_ERR                    , 43  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_43_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_44_ERR                    , 44  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_44_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_45_ERR                    , 45  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_45_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_46_ERR                    , 46  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_46_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_47_ERR                    , 47  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_47_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_48_ERR                    , 48  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_48_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_49_ERR                    , 49  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_49_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_50_ERR                    , 50  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_50_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_51_ERR                    , 51  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_51_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_52_ERR                    , 52  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_52_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_53_ERR                    , 53  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_53_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_54_ERR                    , 54  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_54_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_55_ERR                    , 55  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_55_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_56_ERR                    , 56  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_56_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_57_ERR                    , 57  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_57_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_58_ERR                    , 58  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_58_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_59_ERR                    , 59  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_59_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_60_ERR                    , 60  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_60_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_DUMMY_61_ERR                    , 61  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_61_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_PARITY_ERR_MASK2                , 62  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERR_MASK2 );
+REG64_FLD( PU_NPU_CTL_FIR_MASK_REG_SCOMFIR_ERR_DUP                 , 63  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_SCOMFIR_ERR_DUP );
+
+REG64_FLD( PU_IOP1_FIR_MASK_REG_HSSCALERR                          , 0   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_HSSCALERR  );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_HSSPLLAERR                         , 1   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_HSSPLLAERR );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_HSSPLLBERR                         , 2   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_HSSPLLBERR );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_TXAERR                             , 3   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXAERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_TXBERR                             , 4   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXBERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_TXCERR                             , 5   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXCERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_TXDERR                             , 6   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXDERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_TXEERR                             , 7   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXEERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_TXFERR                             , 8   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXFERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_TXGERR                             , 9   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXGERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_TXHERR                             , 10  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXHERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_TXIERR                             , 11  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXIERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_TXJERR                             , 12  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXJERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_TXKERR                             , 13  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXKERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_TXLERR                             , 14  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXLERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_TXMERR                             , 15  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXMERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_TXNERR                             , 16  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXNERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_TXOERR                             , 17  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXOERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_TXPERR                             , 18  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXPERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_RXAERR                             , 19  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXAERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_RXBERR                             , 20  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXBERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_RXCERR                             , 21  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXCERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_RXDERR                             , 22  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXDERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_RXEERR                             , 23  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXEERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_RXFERR                             , 24  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXFERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_RXGERR                             , 25  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXGERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_RXHERR                             , 26  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXHERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_RXIERR                             , 27  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXIERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_RXJERR                             , 28  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXJERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_RXKERR                             , 29  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXKERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_RXLERR                             , 30  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXLERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_RXMERR                             , 31  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXMERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_RXNERR                             , 32  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXNERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_RXOERR                             , 33  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXOERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_RXPERR                             , 34  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXPERR     );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_SCOM_PERR0                         , 35  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PERR0 );
+REG64_FLD( PU_IOP1_FIR_MASK_REG_SCOM_PERR1                         , 36  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PERR1 );
+
+REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED0                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PSI_RESERVED0 );
+REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED1                           , 1   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PSI_RESERVED1 );
+REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED2                           , 2   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PSI_RESERVED2 );
+REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED3                           , 3   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PSI_RESERVED3 );
+REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED4                           , 4   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PSI_RESERVED4 );
+REG64_FLD( PU_FIR_MASK_REG_INTERNAL_SCOM_ERROR                     , 5   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_SCOM_ERROR );
+REG64_FLD( PU_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE               , 6   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_SCOM_ERROR_CLONE );
+
+REG64_FLD( PU_IOP0_FIR_MASK_REG_HSSCALERR                          , 0   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_HSSCALERR  );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_HSSPLLAERR                         , 1   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_HSSPLLAERR );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_HSSPLLBERR                         , 2   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_HSSPLLBERR );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_TXAERR                             , 3   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXAERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_TXBERR                             , 4   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXBERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_TXCERR                             , 5   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXCERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_TXDERR                             , 6   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXDERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_TXEERR                             , 7   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXEERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_TXFERR                             , 8   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXFERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_TXGERR                             , 9   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXGERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_TXHERR                             , 10  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXHERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_TXIERR                             , 11  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXIERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_TXJERR                             , 12  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXJERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_TXKERR                             , 13  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXKERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_TXLERR                             , 14  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXLERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_TXMERR                             , 15  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXMERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_TXNERR                             , 16  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXNERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_TXOERR                             , 17  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXOERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_TXPERR                             , 18  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXPERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_RXAERR                             , 19  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXAERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_RXBERR                             , 20  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXBERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_RXCERR                             , 21  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXCERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_RXDERR                             , 22  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXDERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_RXEERR                             , 23  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXEERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_RXFERR                             , 24  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXFERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_RXGERR                             , 25  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXGERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_RXHERR                             , 26  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXHERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_RXIERR                             , 27  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXIERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_RXJERR                             , 28  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXJERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_RXKERR                             , 29  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXKERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_RXLERR                             , 30  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXLERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_RXMERR                             , 31  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXMERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_RXNERR                             , 32  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXNERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_RXOERR                             , 33  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXOERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_RXPERR                             , 34  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXPERR     );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_SCOM_PERR0                         , 35  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PERR0 );
+REG64_FLD( PU_IOP0_FIR_MASK_REG_SCOM_PERR1                         , 36  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PERR1 );
+
+REG64_FLD( PU_IOP2_FIR_MASK_REG_HSSCALERR                          , 0   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_HSSCALERR  );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_HSSPLLAERR                         , 1   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_HSSPLLAERR );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_HSSPLLBERR                         , 2   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_HSSPLLBERR );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_TXAERR                             , 3   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXAERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_TXBERR                             , 4   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXBERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_TXCERR                             , 5   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXCERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_TXDERR                             , 6   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXDERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_TXEERR                             , 7   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXEERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_TXFERR                             , 8   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXFERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_TXGERR                             , 9   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXGERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_TXHERR                             , 10  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXHERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_TXIERR                             , 11  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXIERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_TXJERR                             , 12  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXJERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_TXKERR                             , 13  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXKERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_TXLERR                             , 14  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXLERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_TXMERR                             , 15  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXMERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_TXNERR                             , 16  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXNERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_TXOERR                             , 17  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXOERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_TXPERR                             , 18  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXPERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_RXAERR                             , 19  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXAERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_RXBERR                             , 20  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXBERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_RXCERR                             , 21  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXCERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_RXDERR                             , 22  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXDERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_RXEERR                             , 23  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXEERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_RXFERR                             , 24  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXFERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_RXGERR                             , 25  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXGERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_RXHERR                             , 26  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXHERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_RXIERR                             , 27  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXIERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_RXJERR                             , 28  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXJERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_RXKERR                             , 29  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXKERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_RXLERR                             , 30  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXLERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_RXMERR                             , 31  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXMERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_RXNERR                             , 32  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXNERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_RXOERR                             , 33  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXOERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_RXPERR                             , 34  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXPERR     );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_SCOM_PERR0                         , 35  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PERR0 );
+REG64_FLD( PU_IOP2_FIR_MASK_REG_SCOM_PERR1                         , 36  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PERR1 );
+
+REG64_FLD( PU_FIR_MASK_REGISTER_ECC_UNCORRECTED_ERR_PIB            , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_UNCORRECTED_ERR_PIB );
+REG64_FLD( PU_FIR_MASK_REGISTER_BAD_ARRAY_ADDR_PIB                 , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BAD_ARRAY_ADDR_PIB );
+REG64_FLD( PU_FIR_MASK_REGISTER_WRT_RST_INTRPT_PIB                 , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WRT_RST_INTRPT_PIB );
+REG64_FLD( PU_FIR_MASK_REGISTER_RD_RST_INTRPT_PIB                  , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RD_RST_INTRPT_PIB );
+REG64_FLD( PU_FIR_MASK_REGISTER_ECC_UNCORRECTED_ERR_FACES          , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_UNCORRECTED_ERR_FACES );
+REG64_FLD( PU_FIR_MASK_REGISTER_BAD_ARRAY_ADDR_FACES               , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BAD_ARRAY_ADDR_FACES );
+REG64_FLD( PU_FIR_MASK_REGISTER_WRT_RST_INTRPT_FACES               , 25  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WRT_RST_INTRPT_FACES );
+REG64_FLD( PU_FIR_MASK_REGISTER_RD_RST_INTRPT_FACES                , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RD_RST_INTRPT_FACES );
+
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_0_ERR                          , 0   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_0_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_1_ERR                          , 1   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_1_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_2_ERR                          , 2   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_2_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_3_ERR                          , 3   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_3_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_4_ERR                          , 4   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_4_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_5_ERR                          , 5   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_5_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_6_ERR                          , 6   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_6_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_7_ERR                          , 7   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_7_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_8_ERR                          , 8   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_8_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_9_ERR                          , 9   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_9_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_10_ERR                         , 10  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_10_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_11_ERR                         , 11  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_11_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_12_ERR                         , 12  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_12_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_13_ERR                         , 13  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_13_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_14_ERR                         , 14  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_14_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_15_ERR                         , 15  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_15_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_16_ERR                         , 16  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_16_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_17_ERR                         , 17  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_17_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_18_ERR                         , 18  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_18_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_19_ERR                         , 19  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_19_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_20_ERR                         , 20  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_20_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_21_ERR                         , 21  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_21_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_22_ERR                         , 22  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_22_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_23_ERR                         , 23  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_23_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_24_ERR                         , 24  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_24_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_25_ERR                         , 25  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_25_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_26_ERR                         , 26  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_26_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_27_ERR                         , 27  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_27_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_28_ERR                         , 28  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_28_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_29_ERR                         , 29  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_29_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_30_ERR                         , 30  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_30_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_31_ERR                         , 31  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_31_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_32_ERR                         , 32  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_32_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_33_ERR                         , 33  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_33_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_34_ERR                         , 34  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_34_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_35_ERR                         , 35  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_35_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_36_ERR                         , 36  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_36_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_37_ERR                         , 37  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_37_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_38_ERR                         , 38  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_38_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_39_ERR                         , 39  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_39_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_40_ERR                         , 40  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_40_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_41_ERR                         , 41  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_41_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_42_ERR                         , 42  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_42_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_43_ERR                         , 43  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_43_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_44_ERR                         , 44  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_44_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_45_ERR                         , 45  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_45_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_46_ERR                         , 46  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_46_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_47_ERR                         , 47  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_47_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_48_ERR                         , 48  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_48_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_49_ERR                         , 49  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_49_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_50_ERR                         , 50  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_50_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_51_ERR                         , 51  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_51_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_52_ERR                         , 52  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_52_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_53_ERR                         , 53  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_53_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_54_ERR                         , 54  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_54_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_55_ERR                         , 55  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_55_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_56_ERR                         , 56  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_56_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_57_ERR                         , 57  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_57_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_58_ERR                         , 58  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_58_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_59_ERR                         , 59  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_59_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_60_ERR                         , 60  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_60_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_DUMMY_61_ERR                         , 61  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_DUMMY_61_ERR );
+REG64_FLD( PU_NPU_CTL_FIR_REG_PARITY_ERR2                          , 62  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERR2 );
+REG64_FLD( PU_NPU_CTL_FIR_REG_PARITY_ERR                           , 63  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERR );
+
+REG64_FLD( PU_FIR_REG_PSI_RESERVED0                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PSI_RESERVED0 );
+REG64_FLD( PU_FIR_REG_PSI_RESERVED1                                , 1   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PSI_RESERVED1 );
+REG64_FLD( PU_FIR_REG_PSI_RESERVED2                                , 2   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PSI_RESERVED2 );
+REG64_FLD( PU_FIR_REG_PSI_RESERVED3                                , 3   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PSI_RESERVED3 );
+REG64_FLD( PU_FIR_REG_PSI_RESERVED4                                , 4   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PSI_RESERVED4 );
+REG64_FLD( PU_FIR_REG_INTERNAL_SCOM_ERROR                          , 5   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_SCOM_ERROR );
+REG64_FLD( PU_FIR_REG_INTERNAL_SCOM_ERROR_CLONE                    , 6   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_SCOM_ERROR_CLONE );
+
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_HSSCALERR                        , 0   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_HSSCALERR  );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_HSSPLLAERR                       , 1   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_HSSPLLAERR );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_HSSPLLBERR                       , 2   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_HSSPLLBERR );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_TXAERR                           , 3   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXAERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_TXBERR                           , 4   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXBERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_TXCERR                           , 5   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXCERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_TXDERR                           , 6   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXDERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_TXEERR                           , 7   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXEERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_TXFERR                           , 8   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXFERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_TXGERR                           , 9   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXGERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_TXHERR                           , 10  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXHERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_TXIERR                           , 11  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXIERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_TXJERR                           , 12  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXJERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_TXKERR                           , 13  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXKERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_TXLERR                           , 14  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXLERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_TXMERR                           , 15  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXMERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_TXNERR                           , 16  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXNERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_TXOERR                           , 17  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXOERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_TXPERR                           , 18  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_TXPERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_RXAERR                           , 19  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXAERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_RXBERR                           , 20  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXBERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_RXCERR                           , 21  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXCERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_RXDERR                           , 22  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXDERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_RXEERR                           , 23  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXEERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_RXFERR                           , 24  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXFERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_RXGERR                           , 25  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXGERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_RXHERR                           , 26  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXHERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_RXIERR                           , 27  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXIERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_RXJERR                           , 28  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXJERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_RXKERR                           , 29  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXKERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_RXLERR                           , 30  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXLERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_RXMERR                           , 31  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXMERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_RXNERR                           , 32  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXNERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_RXOERR                           , 33  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXOERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_RXPERR                           , 34  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_RXPERR     );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_SCOM_PERR0                       , 35  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PERR0 );
+REG64_FLD( PU_IOP1_FIR_STATUS_REG_SCOM_PERR1                       , 36  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PERR1 );
+
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_HSSCALERR                        , 0   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_HSSCALERR  );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_HSSPLLAERR                       , 1   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_HSSPLLAERR );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_HSSPLLBERR                       , 2   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_HSSPLLBERR );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_TXAERR                           , 3   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXAERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_TXBERR                           , 4   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXBERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_TXCERR                           , 5   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXCERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_TXDERR                           , 6   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXDERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_TXEERR                           , 7   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXEERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_TXFERR                           , 8   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXFERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_TXGERR                           , 9   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXGERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_TXHERR                           , 10  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXHERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_TXIERR                           , 11  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXIERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_TXJERR                           , 12  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXJERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_TXKERR                           , 13  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXKERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_TXLERR                           , 14  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXLERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_TXMERR                           , 15  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXMERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_TXNERR                           , 16  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXNERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_TXOERR                           , 17  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXOERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_TXPERR                           , 18  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_TXPERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_RXAERR                           , 19  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXAERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_RXBERR                           , 20  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXBERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_RXCERR                           , 21  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXCERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_RXDERR                           , 22  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXDERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_RXEERR                           , 23  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXEERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_RXFERR                           , 24  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXFERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_RXGERR                           , 25  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXGERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_RXHERR                           , 26  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXHERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_RXIERR                           , 27  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXIERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_RXJERR                           , 28  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXJERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_RXKERR                           , 29  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXKERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_RXLERR                           , 30  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXLERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_RXMERR                           , 31  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXMERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_RXNERR                           , 32  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXNERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_RXOERR                           , 33  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXOERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_RXPERR                           , 34  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_RXPERR     );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_SCOM_PERR0                       , 35  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PERR0 );
+REG64_FLD( PU_IOP0_FIR_STATUS_REG_SCOM_PERR1                       , 36  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PERR1 );
+
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_HSSCALERR                        , 0   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_HSSCALERR  );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_HSSPLLAERR                       , 1   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_HSSPLLAERR );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_HSSPLLBERR                       , 2   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_HSSPLLBERR );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_TXAERR                           , 3   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXAERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_TXBERR                           , 4   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXBERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_TXCERR                           , 5   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXCERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_TXDERR                           , 6   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXDERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_TXEERR                           , 7   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXEERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_TXFERR                           , 8   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXFERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_TXGERR                           , 9   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXGERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_TXHERR                           , 10  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXHERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_TXIERR                           , 11  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXIERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_TXJERR                           , 12  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXJERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_TXKERR                           , 13  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXKERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_TXLERR                           , 14  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXLERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_TXMERR                           , 15  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXMERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_TXNERR                           , 16  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXNERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_TXOERR                           , 17  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXOERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_TXPERR                           , 18  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_TXPERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_RXAERR                           , 19  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXAERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_RXBERR                           , 20  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXBERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_RXCERR                           , 21  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXCERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_RXDERR                           , 22  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXDERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_RXEERR                           , 23  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXEERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_RXFERR                           , 24  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXFERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_RXGERR                           , 25  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXGERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_RXHERR                           , 26  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXHERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_RXIERR                           , 27  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXIERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_RXJERR                           , 28  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXJERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_RXKERR                           , 29  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXKERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_RXLERR                           , 30  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXLERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_RXMERR                           , 31  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXMERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_RXNERR                           , 32  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXNERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_RXOERR                           , 33  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXOERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_RXPERR                           , 34  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_RXPERR     );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_SCOM_PERR0                       , 35  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PERR0 );
+REG64_FLD( PU_IOP2_FIR_STATUS_REG_SCOM_PERR1                       , 36  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PERR1 );
+
+REG64_FLD( PU_NPU_CTL_FIR_WOF_REG_WOF                              , 0   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM_WCLRREG, SH_FLD_WOF        );
+REG64_FLD( PU_NPU_CTL_FIR_WOF_REG_WOF_LEN                          , 64  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LEN    );
+
+REG64_FLD( PU_IOP1_FIR_WOF_REG_WOF                                 , 0   ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF        );
+REG64_FLD( PU_IOP1_FIR_WOF_REG_WOF_LEN                             , 37  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LEN    );
+
+REG64_FLD( PU_IOP0_FIR_WOF_REG_WOF                                 , 0   ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF        );
+REG64_FLD( PU_IOP0_FIR_WOF_REG_WOF_LEN                             , 37  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LEN    );
+
+REG64_FLD( PU_IOP2_FIR_WOF_REG_WOF                                 , 0   ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF        );
+REG64_FLD( PU_IOP2_FIR_WOF_REG_WOF_LEN                             , 37  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LEN    );
+
+REG64_FLD( PU_FMU_MODE_REG_TOD_CNTR_REF                            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TOD_CNTR_REF );
+REG64_FLD( PU_FMU_MODE_REG_TOD_CNTR_REF_LEN                        , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TOD_CNTR_REF_LEN );
+REG64_FLD( PU_FMU_MODE_REG_POWER_UP_CNTR_REF                       , 17  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_POWER_UP_CNTR_REF );
+REG64_FLD( PU_FMU_MODE_REG_POWER_UP_CNTR_REF_LEN                   , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_POWER_UP_CNTR_REF_LEN );
+
+REG64_FLD( PU_FMU_OSC_CNTR1_REG_RESULT_AVAILABLE                   , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESULT_AVAILABLE );
+REG64_FLD( PU_FMU_OSC_CNTR1_REG_PULSE1_CNTR                        , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PULSE1_CNTR );
+REG64_FLD( PU_FMU_OSC_CNTR1_REG_PULSE1_CNTR_LEN                    , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PULSE1_CNTR_LEN );
+
+REG64_FLD( PU_FMU_OSC_CNTR2_REG_RESULT_AVAILABLE                   , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESULT_AVAILABLE );
+REG64_FLD( PU_FMU_OSC_CNTR2_REG_PULSE2_CNTR                        , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PULSE2_CNTR );
+REG64_FLD( PU_FMU_OSC_CNTR2_REG_PULSE2_CNTR_LEN                    , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PULSE2_CNTR_LEN );
+
+REG64_FLD( PU_FMU_PULSE_GEN_REG_INT_ENA                            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INT_ENA    );
+REG64_FLD( PU_FMU_PULSE_GEN_REG_INT_CNTR_REF                       , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INT_CNTR_REF );
+REG64_FLD( PU_FMU_PULSE_GEN_REG_INT_CNTR_REF_LEN                   , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INT_CNTR_REF_LEN );
+
+REG64_FLD( PU_FORCE_ECC_REG_ALTD_DATA_ITAG                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ALTD_DATA_ITAG );
+REG64_FLD( PU_FORCE_ECC_REG_ALTD_DATA_TX                           , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ALTD_DATA_TX );
+REG64_FLD( PU_FORCE_ECC_REG_ALTD_DATA_TX_LEN                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ALTD_DATA_TX_LEN );
+REG64_FLD( PU_FORCE_ECC_REG_ALTD_DATA_TX_OVERWRITE                 , 17  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ALTD_DATA_TX_OVERWRITE );
+
+REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SBE          , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DNFIFO_REQ_RESET_FR_SBE );
+REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SP           , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DNFIFO_REQ_RESET_FR_SP );
+REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_DEQUEUED_EOT_FLAG         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DNFIFO_DEQUEUED_EOT_FLAG );
+REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_FULL                 , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DNFIFO_FIFO_FULL );
+REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EMPTY                , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DNFIFO_FIFO_EMPTY );
+REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT          , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DNFIFO_FIFO_ENTRY_COUNT );
+REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT_LEN      , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DNFIFO_FIFO_ENTRY_COUNT_LEN );
+REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS          , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DNFIFO_FIFO_VALID_FLAGS );
+REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS_LEN      , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DNFIFO_FIFO_VALID_FLAGS_LEN );
+REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DNFIFO_FIFO_EOT_FLAGS );
+REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS_LEN        , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DNFIFO_FIFO_EOT_FLAGS_LEN );
+
+REG64_FLD( PU_FSB_UPFIFO_STATUS_REQ_RESET_FR_SP                    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REQ_RESET_FR_SP );
+REG64_FLD( PU_FSB_UPFIFO_STATUS_REQ_RESET_FR_SBE                   , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REQ_RESET_FR_SBE );
+REG64_FLD( PU_FSB_UPFIFO_STATUS_DEQUEUED_EOT_FLAG                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DEQUEUED_EOT_FLAG );
+REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_FULL                          , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_FULL  );
+REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_EMPTY                         , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_EMPTY );
+REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT                   , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_ENTRY_COUNT );
+REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_ENTRY_COUNT_LEN );
+REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS                   , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_VALID_FLAGS );
+REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_VALID_FLAGS_LEN );
+REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS                     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_EOT_FLAGS );
+REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS_LEN                 , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_EOT_FLAGS_LEN );
+
+REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM0_GENID_BAR_RESERVED1                         , 1   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_ADDR                       , 2   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_ADDR_LEN                   , 25  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM0_GENID_BAR_RESERVED2                         , 27  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM2_GENID_BAR_RESERVED1                         , 1   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_ADDR                       , 2   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_ADDR_LEN                   , 25  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM2_GENID_BAR_RESERVED2                         , 27  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM3_GENID_BAR_RESERVED1                         , 1   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_ADDR                       , 2   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_ADDR_LEN                   , 25  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM3_GENID_BAR_RESERVED2                         , 27  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM3_GENID_BAR_RESERVED1                         , 1   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_ADDR                       , 2   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_ADDR_LEN                   , 25  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM3_GENID_BAR_RESERVED2                         , 27  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM3_GENID_BAR_RESERVED1                         , 1   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_ADDR                       , 2   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_ADDR_LEN                   , 25  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM3_GENID_BAR_RESERVED2                         , 27  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM1_GENID_BAR_RESERVED1                         , 1   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_ADDR                       , 2   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_ADDR_LEN                   , 25  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM1_GENID_BAR_RESERVED2                         , 27  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM2_GENID_BAR_RESERVED1                         , 1   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_ADDR                       , 2   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_ADDR_LEN                   , 25  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM2_GENID_BAR_RESERVED2                         , 27  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM1_GENID_BAR_RESERVED1                         , 1   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_ADDR                       , 2   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_ADDR_LEN                   , 25  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM1_GENID_BAR_RESERVED2                         , 27  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM2_GENID_BAR_RESERVED1                         , 1   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_ADDR                       , 2   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_ADDR_LEN                   , 25  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM2_GENID_BAR_RESERVED2                         , 27  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM0_GENID_BAR_RESERVED1                         , 1   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_ADDR                       , 2   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_ADDR_LEN                   , 25  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM0_GENID_BAR_RESERVED2                         , 27  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM1_GENID_BAR_RESERVED1                         , 1   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_ADDR                       , 2   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_ADDR_LEN                   , 25  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM1_GENID_BAR_RESERVED2                         , 27  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM0_GENID_BAR_RESERVED1                         , 1   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_ADDR                       , 2   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_ADDR_LEN                   , 25  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM0_GENID_BAR_RESERVED2                         , 27  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_GPE2_GPEDBG_EN_DBG                                   , 0   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_EN_DBG     );
+REG64_FLD( PU_GPE2_GPEDBG_HALT_ON_XSTOP                            , 1   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_GPE2_GPEDBG_HALT_ON_TRIG                             , 2   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_GPE2_GPEDBG_EN_RISCTRACE                             , 3   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_EN_RISCTRACE );
+REG64_FLD( PU_GPE2_GPEDBG_EN_TRACE_FULL_IVA                        , 4   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_EN_TRACE_FULL_IVA );
+REG64_FLD( PU_GPE2_GPEDBG_DIS_TRACE_EXTRA                          , 5   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_DIS_TRACE_EXTRA );
+REG64_FLD( PU_GPE2_GPEDBG_DIS_TRACE_STALL                          , 6   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_DIS_TRACE_STALL );
+REG64_FLD( PU_GPE2_GPEDBG_EN_WIDE_TRACE                            , 7   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_EN_WIDE_TRACE );
+REG64_FLD( PU_GPE2_GPEDBG_SYNC_TIMER_SEL                           , 8   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_SYNC_TIMER_SEL );
+REG64_FLD( PU_GPE2_GPEDBG_SYNC_TIMER_SEL_LEN                       , 4   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_SYNC_TIMER_SEL_LEN );
+REG64_FLD( PU_GPE2_GPEDBG_FIR_TRIGGER                              , 12  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_GPE2_GPEDBG_SPARE                                    , 13  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE2_GPEDBG_SPARE_LEN                                , 3   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_GPE1_GPEDBG_EN_DBG                                   , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_EN_DBG     );
+REG64_FLD( PU_GPE1_GPEDBG_HALT_ON_XSTOP                            , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_GPE1_GPEDBG_HALT_ON_TRIG                             , 2   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_GPE1_GPEDBG_EN_RISCTRACE                             , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_EN_RISCTRACE );
+REG64_FLD( PU_GPE1_GPEDBG_EN_TRACE_FULL_IVA                        , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_EN_TRACE_FULL_IVA );
+REG64_FLD( PU_GPE1_GPEDBG_DIS_TRACE_EXTRA                          , 5   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_DIS_TRACE_EXTRA );
+REG64_FLD( PU_GPE1_GPEDBG_DIS_TRACE_STALL                          , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_DIS_TRACE_STALL );
+REG64_FLD( PU_GPE1_GPEDBG_EN_WIDE_TRACE                            , 7   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_EN_WIDE_TRACE );
+REG64_FLD( PU_GPE1_GPEDBG_SYNC_TIMER_SEL                           , 8   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_SYNC_TIMER_SEL );
+REG64_FLD( PU_GPE1_GPEDBG_SYNC_TIMER_SEL_LEN                       , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_SYNC_TIMER_SEL_LEN );
+REG64_FLD( PU_GPE1_GPEDBG_FIR_TRIGGER                              , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_GPE1_GPEDBG_SPARE                                    , 13  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE1_GPEDBG_SPARE_LEN                                , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_GPE3_GPEDBG_EN_DBG                                   , 0   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_EN_DBG     );
+REG64_FLD( PU_GPE3_GPEDBG_HALT_ON_XSTOP                            , 1   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_GPE3_GPEDBG_HALT_ON_TRIG                             , 2   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_GPE3_GPEDBG_EN_RISCTRACE                             , 3   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_EN_RISCTRACE );
+REG64_FLD( PU_GPE3_GPEDBG_EN_TRACE_FULL_IVA                        , 4   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_EN_TRACE_FULL_IVA );
+REG64_FLD( PU_GPE3_GPEDBG_DIS_TRACE_EXTRA                          , 5   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_DIS_TRACE_EXTRA );
+REG64_FLD( PU_GPE3_GPEDBG_DIS_TRACE_STALL                          , 6   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_DIS_TRACE_STALL );
+REG64_FLD( PU_GPE3_GPEDBG_EN_WIDE_TRACE                            , 7   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_EN_WIDE_TRACE );
+REG64_FLD( PU_GPE3_GPEDBG_SYNC_TIMER_SEL                           , 8   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_SYNC_TIMER_SEL );
+REG64_FLD( PU_GPE3_GPEDBG_SYNC_TIMER_SEL_LEN                       , 4   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_SYNC_TIMER_SEL_LEN );
+REG64_FLD( PU_GPE3_GPEDBG_FIR_TRIGGER                              , 12  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_GPE3_GPEDBG_SPARE                                    , 13  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE3_GPEDBG_SPARE_LEN                                , 3   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_GPE0_GPEDBG_EN_DBG                                   , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_EN_DBG     );
+REG64_FLD( PU_GPE0_GPEDBG_HALT_ON_XSTOP                            , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_GPE0_GPEDBG_HALT_ON_TRIG                             , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_GPE0_GPEDBG_EN_RISCTRACE                             , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_EN_RISCTRACE );
+REG64_FLD( PU_GPE0_GPEDBG_EN_TRACE_FULL_IVA                        , 4   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_EN_TRACE_FULL_IVA );
+REG64_FLD( PU_GPE0_GPEDBG_DIS_TRACE_EXTRA                          , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_DIS_TRACE_EXTRA );
+REG64_FLD( PU_GPE0_GPEDBG_DIS_TRACE_STALL                          , 6   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_DIS_TRACE_STALL );
+REG64_FLD( PU_GPE0_GPEDBG_EN_WIDE_TRACE                            , 7   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_EN_WIDE_TRACE );
+REG64_FLD( PU_GPE0_GPEDBG_SYNC_TIMER_SEL                           , 8   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_SYNC_TIMER_SEL );
+REG64_FLD( PU_GPE0_GPEDBG_SYNC_TIMER_SEL_LEN                       , 4   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_SYNC_TIMER_SEL_LEN );
+REG64_FLD( PU_GPE0_GPEDBG_FIR_TRIGGER                              , 12  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_GPE0_GPEDBG_SPARE                                    , 13  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE0_GPEDBG_SPARE_LEN                                , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_GPE2_GPEIVPR_IVPR                                    , 0   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_IVPR       );
+REG64_FLD( PU_GPE2_GPEIVPR_IVPR_LEN                                , 23  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_IVPR_LEN   );
+
+REG64_FLD( PU_GPE1_GPEIVPR_IVPR                                    , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_IVPR       );
+REG64_FLD( PU_GPE1_GPEIVPR_IVPR_LEN                                , 23  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_IVPR_LEN   );
+
+REG64_FLD( PU_GPE3_GPEIVPR_IVPR                                    , 0   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_IVPR       );
+REG64_FLD( PU_GPE3_GPEIVPR_IVPR_LEN                                , 23  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_IVPR_LEN   );
+
+REG64_FLD( PU_GPE0_GPEIVPR_IVPR                                    , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_IVPR       );
+REG64_FLD( PU_GPE0_GPEIVPR_IVPR_LEN                                , 23  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_IVPR_LEN   );
+
+REG64_FLD( PU_GPE2_GPEMACR_MEM_LOW_PRIORITY                        , 0   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_MEM_LOW_PRIORITY );
+REG64_FLD( PU_GPE2_GPEMACR_MEM_LOW_PRIORITY_LEN                    , 2   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_MEM_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE2_GPEMACR_MEM_HIGH_PRIORITY                       , 2   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_MEM_HIGH_PRIORITY );
+REG64_FLD( PU_GPE2_GPEMACR_MEM_HIGH_PRIORITY_LEN                   , 2   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_MEM_HIGH_PRIORITY_LEN );
+REG64_FLD( PU_GPE2_GPEMACR_LOCAL_LOW_PRIORITY                      , 4   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_LOCAL_LOW_PRIORITY );
+REG64_FLD( PU_GPE2_GPEMACR_LOCAL_LOW_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_LOCAL_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE2_GPEMACR_LOCAL_HIGH_PRIORITY                     , 6   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_LOCAL_HIGH_PRIORITY );
+REG64_FLD( PU_GPE2_GPEMACR_LOCAL_HIGH_PRIORITY_LEN                 , 2   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_LOCAL_HIGH_PRIORITY_LEN );
+REG64_FLD( PU_GPE2_GPEMACR_SRAM_LOW_PRIORITY                       , 8   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_SRAM_LOW_PRIORITY );
+REG64_FLD( PU_GPE2_GPEMACR_SRAM_LOW_PRIORITY_LEN                   , 2   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_SRAM_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE2_GPEMACR_SRAM_HIGH_PRIORITY                      , 10  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_SRAM_HIGH_PRIORITY );
+REG64_FLD( PU_GPE2_GPEMACR_SRAM_HIGH_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_SRAM_HIGH_PRIORITY_LEN );
+
+REG64_FLD( PU_GPE1_GPEMACR_MEM_LOW_PRIORITY                        , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_MEM_LOW_PRIORITY );
+REG64_FLD( PU_GPE1_GPEMACR_MEM_LOW_PRIORITY_LEN                    , 2   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_MEM_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE1_GPEMACR_MEM_HIGH_PRIORITY                       , 2   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_MEM_HIGH_PRIORITY );
+REG64_FLD( PU_GPE1_GPEMACR_MEM_HIGH_PRIORITY_LEN                   , 2   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_MEM_HIGH_PRIORITY_LEN );
+REG64_FLD( PU_GPE1_GPEMACR_LOCAL_LOW_PRIORITY                      , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_LOCAL_LOW_PRIORITY );
+REG64_FLD( PU_GPE1_GPEMACR_LOCAL_LOW_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_LOCAL_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE1_GPEMACR_LOCAL_HIGH_PRIORITY                     , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_LOCAL_HIGH_PRIORITY );
+REG64_FLD( PU_GPE1_GPEMACR_LOCAL_HIGH_PRIORITY_LEN                 , 2   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_LOCAL_HIGH_PRIORITY_LEN );
+REG64_FLD( PU_GPE1_GPEMACR_SRAM_LOW_PRIORITY                       , 8   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_SRAM_LOW_PRIORITY );
+REG64_FLD( PU_GPE1_GPEMACR_SRAM_LOW_PRIORITY_LEN                   , 2   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_SRAM_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE1_GPEMACR_SRAM_HIGH_PRIORITY                      , 10  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_SRAM_HIGH_PRIORITY );
+REG64_FLD( PU_GPE1_GPEMACR_SRAM_HIGH_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_SRAM_HIGH_PRIORITY_LEN );
+
+REG64_FLD( PU_GPE3_GPEMACR_MEM_LOW_PRIORITY                        , 0   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_MEM_LOW_PRIORITY );
+REG64_FLD( PU_GPE3_GPEMACR_MEM_LOW_PRIORITY_LEN                    , 2   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_MEM_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE3_GPEMACR_MEM_HIGH_PRIORITY                       , 2   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_MEM_HIGH_PRIORITY );
+REG64_FLD( PU_GPE3_GPEMACR_MEM_HIGH_PRIORITY_LEN                   , 2   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_MEM_HIGH_PRIORITY_LEN );
+REG64_FLD( PU_GPE3_GPEMACR_LOCAL_LOW_PRIORITY                      , 4   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_LOCAL_LOW_PRIORITY );
+REG64_FLD( PU_GPE3_GPEMACR_LOCAL_LOW_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_LOCAL_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE3_GPEMACR_LOCAL_HIGH_PRIORITY                     , 6   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_LOCAL_HIGH_PRIORITY );
+REG64_FLD( PU_GPE3_GPEMACR_LOCAL_HIGH_PRIORITY_LEN                 , 2   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_LOCAL_HIGH_PRIORITY_LEN );
+REG64_FLD( PU_GPE3_GPEMACR_SRAM_LOW_PRIORITY                       , 8   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_SRAM_LOW_PRIORITY );
+REG64_FLD( PU_GPE3_GPEMACR_SRAM_LOW_PRIORITY_LEN                   , 2   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_SRAM_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE3_GPEMACR_SRAM_HIGH_PRIORITY                      , 10  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_SRAM_HIGH_PRIORITY );
+REG64_FLD( PU_GPE3_GPEMACR_SRAM_HIGH_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_SRAM_HIGH_PRIORITY_LEN );
+
+REG64_FLD( PU_GPE0_GPEMACR_MEM_LOW_PRIORITY                        , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_MEM_LOW_PRIORITY );
+REG64_FLD( PU_GPE0_GPEMACR_MEM_LOW_PRIORITY_LEN                    , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_MEM_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE0_GPEMACR_MEM_HIGH_PRIORITY                       , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_MEM_HIGH_PRIORITY );
+REG64_FLD( PU_GPE0_GPEMACR_MEM_HIGH_PRIORITY_LEN                   , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_MEM_HIGH_PRIORITY_LEN );
+REG64_FLD( PU_GPE0_GPEMACR_LOCAL_LOW_PRIORITY                      , 4   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_LOCAL_LOW_PRIORITY );
+REG64_FLD( PU_GPE0_GPEMACR_LOCAL_LOW_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_LOCAL_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE0_GPEMACR_LOCAL_HIGH_PRIORITY                     , 6   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_LOCAL_HIGH_PRIORITY );
+REG64_FLD( PU_GPE0_GPEMACR_LOCAL_HIGH_PRIORITY_LEN                 , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_LOCAL_HIGH_PRIORITY_LEN );
+REG64_FLD( PU_GPE0_GPEMACR_SRAM_LOW_PRIORITY                       , 8   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_SRAM_LOW_PRIORITY );
+REG64_FLD( PU_GPE0_GPEMACR_SRAM_LOW_PRIORITY_LEN                   , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_SRAM_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE0_GPEMACR_SRAM_HIGH_PRIORITY                      , 10  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_SRAM_HIGH_PRIORITY );
+REG64_FLD( PU_GPE0_GPEMACR_SRAM_HIGH_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_SRAM_HIGH_PRIORITY_LEN );
+
+REG64_FLD( PU_GPE2_GPESTR_PBASE                                    , 12  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_PBASE      );
+REG64_FLD( PU_GPE2_GPESTR_PBASE_LEN                                , 10  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_PBASE_LEN  );
+REG64_FLD( PU_GPE2_GPESTR_SIZE                                     , 29  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_SIZE       );
+REG64_FLD( PU_GPE2_GPESTR_SIZE_LEN                                 , 3   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_SIZE_LEN   );
+
+REG64_FLD( PU_GPE1_GPESTR_PBASE                                    , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_PBASE      );
+REG64_FLD( PU_GPE1_GPESTR_PBASE_LEN                                , 10  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_PBASE_LEN  );
+REG64_FLD( PU_GPE1_GPESTR_SIZE                                     , 29  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_SIZE       );
+REG64_FLD( PU_GPE1_GPESTR_SIZE_LEN                                 , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_SIZE_LEN   );
+
+REG64_FLD( PU_GPE3_GPESTR_PBASE                                    , 12  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_PBASE      );
+REG64_FLD( PU_GPE3_GPESTR_PBASE_LEN                                , 10  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_PBASE_LEN  );
+REG64_FLD( PU_GPE3_GPESTR_SIZE                                     , 29  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_SIZE       );
+REG64_FLD( PU_GPE3_GPESTR_SIZE_LEN                                 , 3   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_SIZE_LEN   );
+
+REG64_FLD( PU_GPE0_GPESTR_PBASE                                    , 12  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_PBASE      );
+REG64_FLD( PU_GPE0_GPESTR_PBASE_LEN                                , 10  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_PBASE_LEN  );
+REG64_FLD( PU_GPE0_GPESTR_SIZE                                     , 29  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_SIZE       );
+REG64_FLD( PU_GPE0_GPESTR_SIZE_LEN                                 , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_SIZE_LEN   );
+
+REG64_FLD( PU_GPE2_GPETSEL_FIT_SEL                                 , 0   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_FIT_SEL    );
+REG64_FLD( PU_GPE2_GPETSEL_FIT_SEL_LEN                             , 4   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_GPE2_GPETSEL_WATCHDOG_SEL                            , 4   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_GPE2_GPETSEL_WATCHDOG_SEL_LEN                        , 4   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_GPE1_GPETSEL_FIT_SEL                                 , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_FIT_SEL    );
+REG64_FLD( PU_GPE1_GPETSEL_FIT_SEL_LEN                             , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_GPE1_GPETSEL_WATCHDOG_SEL                            , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_GPE1_GPETSEL_WATCHDOG_SEL_LEN                        , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_GPE3_GPETSEL_FIT_SEL                                 , 0   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_FIT_SEL    );
+REG64_FLD( PU_GPE3_GPETSEL_FIT_SEL_LEN                             , 4   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_GPE3_GPETSEL_WATCHDOG_SEL                            , 4   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_GPE3_GPETSEL_WATCHDOG_SEL_LEN                        , 4   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_GPE0_GPETSEL_FIT_SEL                                 , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_FIT_SEL    );
+REG64_FLD( PU_GPE0_GPETSEL_FIT_SEL_LEN                             , 4   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_GPE0_GPETSEL_WATCHDOG_SEL                            , 4   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_GPE0_GPETSEL_WATCHDOG_SEL_LEN                        , 4   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_GPE2_GPEXIEDR_PPE_XIRAMEDR_EDR                       , 0   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_PPE_XIRAMEDR_EDR );
+REG64_FLD( PU_GPE2_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN                   , 32  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_PPE_XIRAMEDR_EDR_LEN );
+
+REG64_FLD( PU_GPE1_GPEXIEDR_PPE_XIRAMEDR_EDR                       , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_PPE_XIRAMEDR_EDR );
+REG64_FLD( PU_GPE1_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN                   , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_PPE_XIRAMEDR_EDR_LEN );
+
+REG64_FLD( PU_GPE3_GPEXIEDR_PPE_XIRAMEDR_EDR                       , 0   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_PPE_XIRAMEDR_EDR );
+REG64_FLD( PU_GPE3_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN                   , 32  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_PPE_XIRAMEDR_EDR_LEN );
+
+REG64_FLD( PU_GPE0_GPEXIEDR_PPE_XIRAMEDR_EDR                       , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_PPE_XIRAMEDR_EDR );
+REG64_FLD( PU_GPE0_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN                   , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_PPE_XIRAMEDR_EDR_LEN );
+
+REG64_FLD( PU_GPE2_GPEXIIR_PPE_XIRAMGA_IR                          , 0   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_PPE_XIRAMGA_IR );
+REG64_FLD( PU_GPE2_GPEXIIR_PPE_XIRAMGA_IR_LEN                      , 32  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_PPE_XIRAMGA_IR_LEN );
+
+REG64_FLD( PU_GPE1_GPEXIIR_PPE_XIRAMGA_IR                          , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_PPE_XIRAMGA_IR );
+REG64_FLD( PU_GPE1_GPEXIIR_PPE_XIRAMGA_IR_LEN                      , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_PPE_XIRAMGA_IR_LEN );
+
+REG64_FLD( PU_GPE3_GPEXIIR_PPE_XIRAMGA_IR                          , 0   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_PPE_XIRAMGA_IR );
+REG64_FLD( PU_GPE3_GPEXIIR_PPE_XIRAMGA_IR_LEN                      , 32  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_PPE_XIRAMGA_IR_LEN );
+
+REG64_FLD( PU_GPE0_GPEXIIR_PPE_XIRAMGA_IR                          , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_PPE_XIRAMGA_IR );
+REG64_FLD( PU_GPE0_GPEXIIR_PPE_XIRAMGA_IR_LEN                      , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_PPE_XIRAMGA_IR_LEN );
+
+REG64_FLD( PU_GPE2_GPEXISPRG0_PPE_XIRAMRA_SPRG0                    , 0   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_PPE_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE2_GPEXISPRG0_PPE_XIRAMRA_SPRG0_LEN                , 32  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RW  , SH_FLD_PPE_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE1_GPEXISPRG0_PPE_XIRAMRA_SPRG0                    , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_PPE_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE1_GPEXISPRG0_PPE_XIRAMRA_SPRG0_LEN                , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RW  , SH_FLD_PPE_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE3_GPEXISPRG0_PPE_XIRAMRA_SPRG0                    , 0   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_PPE_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE3_GPEXISPRG0_PPE_XIRAMRA_SPRG0_LEN                , 32  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RW  , SH_FLD_PPE_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE0_GPEXISPRG0_PPE_XIRAMRA_SPRG0                    , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_PPE_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE0_GPEXISPRG0_PPE_XIRAMRA_SPRG0_LEN                , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RW  , SH_FLD_PPE_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE2_GPEXIXCR_PPE_XIXCR_XCR                          , 1   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_WO  , SH_FLD_PPE_XIXCR_XCR );
+REG64_FLD( PU_GPE2_GPEXIXCR_PPE_XIXCR_XCR_LEN                      , 3   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_WO  , SH_FLD_PPE_XIXCR_XCR_LEN );
+
+REG64_FLD( PU_GPE1_GPEXIXCR_PPE_XIXCR_XCR                          , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_WO  , SH_FLD_PPE_XIXCR_XCR );
+REG64_FLD( PU_GPE1_GPEXIXCR_PPE_XIXCR_XCR_LEN                      , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_WO  , SH_FLD_PPE_XIXCR_XCR_LEN );
+
+REG64_FLD( PU_GPE3_GPEXIXCR_PPE_XIXCR_XCR                          , 1   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_WO  , SH_FLD_PPE_XIXCR_XCR );
+REG64_FLD( PU_GPE3_GPEXIXCR_PPE_XIXCR_XCR_LEN                      , 3   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_WO  , SH_FLD_PPE_XIXCR_XCR_LEN );
+
+REG64_FLD( PU_GPE0_GPEXIXCR_PPE_XIXCR_XCR                          , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_WO  , SH_FLD_PPE_XIXCR_XCR );
+REG64_FLD( PU_GPE0_GPEXIXCR_PPE_XIXCR_XCR_LEN                      , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_WO  , SH_FLD_PPE_XIXCR_XCR_LEN );
+
+REG64_FLD( PU_GPE2_GPEXIXSR_NULL_MSR_SIBRC                         , 9   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE2_GPEXIXSR_NULL_MSR_SIBRC_LEN                     , 3   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE2_GPEXIXSR_NULL_MSR_WE                            , 14  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE2_GPEXIXSR_NULL_MSR_LP                            , 20  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_NULL_MSR_LP );
+
+REG64_FLD( PU_GPE1_GPEXIXSR_NULL_MSR_SIBRC                         , 9   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE1_GPEXIXSR_NULL_MSR_SIBRC_LEN                     , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE1_GPEXIXSR_NULL_MSR_WE                            , 14  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE1_GPEXIXSR_NULL_MSR_LP                            , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_NULL_MSR_LP );
+
+REG64_FLD( PU_GPE3_GPEXIXSR_NULL_MSR_SIBRC                         , 9   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE3_GPEXIXSR_NULL_MSR_SIBRC_LEN                     , 3   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE3_GPEXIXSR_NULL_MSR_WE                            , 14  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE3_GPEXIXSR_NULL_MSR_LP                            , 20  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_NULL_MSR_LP );
+
+REG64_FLD( PU_GPE0_GPEXIXSR_NULL_MSR_SIBRC                         , 9   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE0_GPEXIXSR_NULL_MSR_SIBRC_LEN                     , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE0_GPEXIXSR_NULL_MSR_WE                            , 14  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE0_GPEXIXSR_NULL_MSR_LP                            , 20  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_NULL_MSR_LP );
+
+REG64_FLD( PU_NPU0_SM0_GPU0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM0_GPU0_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU0_SM0_GPU0_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU0_SM0_GPU0_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU0_SM0_GPU0_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM0_GPU0_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM0_GPU0_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU0_SM0_GPU0_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU0_SM0_GPU0_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU0_SM0_GPU0_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU1_SM2_GPU0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM2_GPU0_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU1_SM2_GPU0_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU1_SM2_GPU0_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU1_SM2_GPU0_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM2_GPU0_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM2_GPU0_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU1_SM2_GPU0_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU1_SM2_GPU0_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU1_SM2_GPU0_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU2_SM3_GPU0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM3_GPU0_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU2_SM3_GPU0_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU2_SM3_GPU0_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU2_SM3_GPU0_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM3_GPU0_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM3_GPU0_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU2_SM3_GPU0_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU2_SM3_GPU0_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU2_SM3_GPU0_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU1_SM3_GPU0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM3_GPU0_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU1_SM3_GPU0_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU1_SM3_GPU0_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU1_SM3_GPU0_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM3_GPU0_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM3_GPU0_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU1_SM3_GPU0_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU1_SM3_GPU0_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU1_SM3_GPU0_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU0_SM3_GPU0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM3_GPU0_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU0_SM3_GPU0_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU0_SM3_GPU0_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU0_SM3_GPU0_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM3_GPU0_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM3_GPU0_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU0_SM3_GPU0_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU0_SM3_GPU0_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU0_SM3_GPU0_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU1_SM1_GPU0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM1_GPU0_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU1_SM1_GPU0_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU1_SM1_GPU0_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU1_SM1_GPU0_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM1_GPU0_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM1_GPU0_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU1_SM1_GPU0_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU1_SM1_GPU0_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU1_SM1_GPU0_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU2_SM2_GPU0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM2_GPU0_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU2_SM2_GPU0_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU2_SM2_GPU0_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU2_SM2_GPU0_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM2_GPU0_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM2_GPU0_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU2_SM2_GPU0_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU2_SM2_GPU0_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU2_SM2_GPU0_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU2_SM1_GPU0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM1_GPU0_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU2_SM1_GPU0_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU2_SM1_GPU0_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU2_SM1_GPU0_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM1_GPU0_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM1_GPU0_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU2_SM1_GPU0_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU2_SM1_GPU0_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU2_SM1_GPU0_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU0_SM2_GPU0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM2_GPU0_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU0_SM2_GPU0_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU0_SM2_GPU0_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU0_SM2_GPU0_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM2_GPU0_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM2_GPU0_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU0_SM2_GPU0_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU0_SM2_GPU0_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU0_SM2_GPU0_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU2_SM0_GPU0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM0_GPU0_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU2_SM0_GPU0_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU2_SM0_GPU0_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU2_SM0_GPU0_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM0_GPU0_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM0_GPU0_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU2_SM0_GPU0_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU2_SM0_GPU0_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU2_SM0_GPU0_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU0_SM1_GPU0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM1_GPU0_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU0_SM1_GPU0_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU0_SM1_GPU0_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU0_SM1_GPU0_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM1_GPU0_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM1_GPU0_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU0_SM1_GPU0_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU0_SM1_GPU0_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU0_SM1_GPU0_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU1_SM0_GPU0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM0_GPU0_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU1_SM0_GPU0_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU1_SM0_GPU0_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU1_SM0_GPU0_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM0_GPU0_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM0_GPU0_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU1_SM0_GPU0_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU1_SM0_GPU0_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU1_SM0_GPU0_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU0_SM0_GPU1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM0_GPU1_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU0_SM0_GPU1_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU0_SM0_GPU1_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU0_SM0_GPU1_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM0_GPU1_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM0_GPU1_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU0_SM0_GPU1_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU0_SM0_GPU1_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU0_SM0_GPU1_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU1_SM2_GPU1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM2_GPU1_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU1_SM2_GPU1_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU1_SM2_GPU1_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU1_SM2_GPU1_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM2_GPU1_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM2_GPU1_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU1_SM2_GPU1_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU1_SM2_GPU1_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU1_SM2_GPU1_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU2_SM3_GPU1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM3_GPU1_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU2_SM3_GPU1_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU2_SM3_GPU1_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU2_SM3_GPU1_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM3_GPU1_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM3_GPU1_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU2_SM3_GPU1_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU2_SM3_GPU1_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU2_SM3_GPU1_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU1_SM3_GPU1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM3_GPU1_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU1_SM3_GPU1_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU1_SM3_GPU1_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU1_SM3_GPU1_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM3_GPU1_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM3_GPU1_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU1_SM3_GPU1_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU1_SM3_GPU1_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU1_SM3_GPU1_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU0_SM3_GPU1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM3_GPU1_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU0_SM3_GPU1_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU0_SM3_GPU1_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU0_SM3_GPU1_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM3_GPU1_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM3_GPU1_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU0_SM3_GPU1_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU0_SM3_GPU1_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU0_SM3_GPU1_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU1_SM1_GPU1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM1_GPU1_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU1_SM1_GPU1_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU1_SM1_GPU1_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU1_SM1_GPU1_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM1_GPU1_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM1_GPU1_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU1_SM1_GPU1_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU1_SM1_GPU1_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU1_SM1_GPU1_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU2_SM2_GPU1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM2_GPU1_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU2_SM2_GPU1_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU2_SM2_GPU1_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU2_SM2_GPU1_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM2_GPU1_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM2_GPU1_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU2_SM2_GPU1_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU2_SM2_GPU1_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU2_SM2_GPU1_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU2_SM1_GPU1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM1_GPU1_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU2_SM1_GPU1_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU2_SM1_GPU1_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU2_SM1_GPU1_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM1_GPU1_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM1_GPU1_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU2_SM1_GPU1_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU2_SM1_GPU1_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU2_SM1_GPU1_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU0_SM2_GPU1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM2_GPU1_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU0_SM2_GPU1_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU0_SM2_GPU1_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU0_SM2_GPU1_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM2_GPU1_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM2_GPU1_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU0_SM2_GPU1_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU0_SM2_GPU1_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU0_SM2_GPU1_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU2_SM0_GPU1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM0_GPU1_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU2_SM0_GPU1_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU2_SM0_GPU1_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU2_SM0_GPU1_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM0_GPU1_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM0_GPU1_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU2_SM0_GPU1_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU2_SM0_GPU1_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU2_SM0_GPU1_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU0_SM1_GPU1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM1_GPU1_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU0_SM1_GPU1_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU0_SM1_GPU1_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU0_SM1_GPU1_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM1_GPU1_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM1_GPU1_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU0_SM1_GPU1_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU0_SM1_GPU1_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU0_SM1_GPU1_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_NPU1_SM0_GPU1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM0_GPU1_BAR_CONFIG_GRANULE                     , 1   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_GRANULE );
+REG64_FLD( PU_NPU1_SM0_GPU1_BAR_CONFIG_MEMTYPE                     , 2   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE );
+REG64_FLD( PU_NPU1_SM0_GPU1_BAR_CONFIG_MEMTYPE_LEN                 , 2   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MEMTYPE_LEN );
+REG64_FLD( PU_NPU1_SM0_GPU1_BAR_CONFIG_ADDR                        , 4   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM0_GPU1_BAR_CONFIG_ADDR_LEN                    , 12  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM0_GPU1_BAR_CONFIG_SIZE                        , 16  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE );
+REG64_FLD( PU_NPU1_SM0_GPU1_BAR_CONFIG_SIZE_LEN                    , 4   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_SIZE_LEN );
+REG64_FLD( PU_NPU1_SM0_GPU1_BAR_CONFIG_MODE                        , 20  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE );
+REG64_FLD( PU_NPU1_SM0_GPU1_BAR_CONFIG_MODE_LEN                    , 4   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_MODE_LEN );
+
+REG64_FLD( PU_GZIP_CONTROL_REG_DISABLE_NEAR_HISTORY                , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_NEAR_HISTORY );
+REG64_FLD( PU_GZIP_CONTROL_REG_DISABLE_FAR_HISTORY                 , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_FAR_HISTORY );
+REG64_FLD( PU_GZIP_CONTROL_REG_DISABLE_EXTRA_HASH_ACCESSES         , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_EXTRA_HASH_ACCESSES );
+REG64_FLD( PU_GZIP_CONTROL_REG_DISABLE_EXTRA_FIFO_ACCESSES         , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_EXTRA_FIFO_ACCESSES );
+REG64_FLD( PU_GZIP_CONTROL_REG_HASH_SIZE_MASK                      , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HASH_SIZE_MASK );
+REG64_FLD( PU_GZIP_CONTROL_REG_HASH_SIZE_MASK_LEN                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HASH_SIZE_MASK_LEN );
+
+REG64_FLD( PU_GZIP_ERRRPT_HOLD_REG_HOLD                            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HOLD       );
+REG64_FLD( PU_GZIP_ERRRPT_HOLD_REG_HOLD_LEN                        , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HOLD_LEN   );
+
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID             , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_LPID );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN         , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_LPID_LEN );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID              , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_PID );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN          , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_PID_LEN );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID              , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_TID );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN          , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_TID_LEN );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE           , 63  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_ENABLE );
+
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_BAR_PRIORITY                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY   );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN              , 46  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_LEN );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE             , 54  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_SIZE );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN         , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_SIZE_LEN );
+
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET     , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_READ_OFFSET );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_READ_OFFSET_LEN );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED          , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_QUEUED );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN      , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_QUEUED_LEN );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX          , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_PRIMAX );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX_LEN      , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_PRIMAX_LEN );
+
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID             , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_LPID );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN         , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_LPID_LEN );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID              , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_PID );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN          , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_PID_LEN );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID              , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_TID );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN          , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_TID_LEN );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE           , 63  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_ENABLE );
+
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_BAR_PRIORITY                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY   );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN              , 46  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_LEN );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE             , 54  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_SIZE );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN         , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_SIZE_LEN );
+
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET     , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_READ_OFFSET );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_READ_OFFSET_LEN );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED          , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_QUEUED );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN      , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_QUEUED_LEN );
+
+REG64_FLD( PU_GZIP_MAX_BYTE_CNT_LOW                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LOW        );
+REG64_FLD( PU_GZIP_MAX_BYTE_CNT_LOW_LEN                            , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LOW_LEN    );
+REG64_FLD( PU_GZIP_MAX_BYTE_CNT_HIGH                               , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HIGH       );
+REG64_FLD( PU_GZIP_MAX_BYTE_CNT_HIGH_LEN                           , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HIGH_LEN   );
+REG64_FLD( PU_GZIP_MAX_BYTE_CNT_THRESHOLD                          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_THRESHOLD  );
+REG64_FLD( PU_GZIP_MAX_BYTE_CNT_SRC_DDE                            , 11  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SRC_DDE    );
+REG64_FLD( PU_GZIP_MAX_BYTE_CNT_SRC_DDE_LEN                        , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SRC_DDE_LEN );
+REG64_FLD( PU_GZIP_MAX_BYTE_CNT_TARGET_DDE                         , 19  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_TARGET_DDE );
+REG64_FLD( PU_GZIP_MAX_BYTE_CNT_TARGET_DDE_LEN                     , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_TARGET_DDE_LEN );
+
+REG64_FLD( PU_HCA_BAR_ADDR                                         , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDR       );
+REG64_FLD( PU_HCA_BAR_ADDR_LEN                                     , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_HCA_BAR_RANGE                                        , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RANGE      );
+REG64_FLD( PU_HCA_BAR_RANGE_LEN                                    , 11  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RANGE_LEN  );
+REG64_FLD( PU_HCA_BAR_PAGE_SIZE_64K                                , 62  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PAGE_SIZE_64K );
+REG64_FLD( PU_HCA_BAR_VALID                                        , 63  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VALID      );
+
+REG64_FLD( PU_HCA_COUNT_BAR_ADDR                                   , 21  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDR       );
+REG64_FLD( PU_HCA_COUNT_BAR_ADDR_LEN                               , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_HCA_COUNT_BAR_VALID                                  , 63  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VALID      );
+
+REG64_FLD( PU_HCA_DROP_PIPE_COUNTER                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PIPE_COUNTER );
+REG64_FLD( PU_HCA_DROP_PIPE_COUNTER_LEN                            , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PIPE_COUNTER_LEN );
+REG64_FLD( PU_HCA_DROP_WRITE_COUNTER                               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_COUNTER );
+REG64_FLD( PU_HCA_DROP_WRITE_COUNTER_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_COUNTER_LEN );
+
+REG64_FLD( PU_HCA_FLUSH_INDEX                                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_INDEX      );
+REG64_FLD( PU_HCA_FLUSH_INDEX_LEN                                  , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_INDEX_LEN  );
+REG64_FLD( PU_HCA_FLUSH_CONG                                       , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CONG       );
+REG64_FLD( PU_HCA_FLUSH_CONG_LEN                                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CONG_LEN   );
+REG64_FLD( PU_HCA_FLUSH_COUNT                                      , 17  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNT      );
+REG64_FLD( PU_HCA_FLUSH_COUNT_LEN                                  , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNT_LEN  );
+
+REG64_FLD( PU_HCA_MIRROR_BAR_ADDR                                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDR       );
+REG64_FLD( PU_HCA_MIRROR_BAR_ADDR_LEN                              , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_HCA_MIRROR_BAR_VALID                                 , 63  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VALID      );
+
+REG64_FLD( PU_HCA_MODES_FULLMASK                                   , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FULLMASK   );
+REG64_FLD( PU_HCA_MODES_FULLMASK_LEN                               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FULLMASK_LEN );
+REG64_FLD( PU_HCA_MODES_ERROR_INJECT                               , 13  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ERROR_INJECT );
+REG64_FLD( PU_HCA_MODES_ERROR_INJECT_LEN                           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ERROR_INJECT_LEN );
+
+REG64_FLD( PU_HCA_REF_BAR_ADDR                                     , 21  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDR       );
+REG64_FLD( PU_HCA_REF_BAR_ADDR_LEN                                 , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_HCA_REF_BAR_VALID                                    , 63  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VALID      );
+
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_XATS                      , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_XATS_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PWR0                      , 6   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PWR1                      , 12  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_REQ0                      , 18  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PRB0                      , 24  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_REQ1                      , 30  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PRB1                      , 36  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_RESERVED1                        , 42  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_RESERVED1_LEN                    , 2   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_XATS                      , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_XATS_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PWR0                      , 6   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PWR1                      , 12  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_REQ0                      , 18  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PRB0                      , 24  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_REQ1                      , 30  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PRB1                      , 36  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_RESERVED1                        , 42  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_RESERVED1_LEN                    , 2   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_XATS                      , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_XATS_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PWR0                      , 6   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PWR1                      , 12  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_REQ0                      , 18  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PRB0                      , 24  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_REQ1                      , 30  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PRB1                      , 36  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_RESERVED1                        , 42  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_RESERVED1_LEN                    , 2   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_XATS                      , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_XATS_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PWR0                      , 6   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PWR1                      , 12  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_REQ0                      , 18  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PRB0                      , 24  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_REQ1                      , 30  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PRB1                      , 36  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_RESERVED1                        , 42  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_RESERVED1_LEN                    , 2   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_XATS                      , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_XATS_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PWR0                      , 6   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PWR1                      , 12  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_REQ0                      , 18  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PRB0                      , 24  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_REQ1                      , 30  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PRB1                      , 36  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_RESERVED1                        , 42  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_RESERVED1_LEN                    , 2   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_XATS                      , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_XATS_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PWR0                      , 6   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PWR1                      , 12  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_REQ0                      , 18  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PRB0                      , 24  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_REQ1                      , 30  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PRB1                      , 36  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_RESERVED1                        , 42  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_RESERVED1_LEN                    , 2   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_XATS                      , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_XATS_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PWR0                      , 6   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PWR1                      , 12  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_REQ0                      , 18  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PRB0                      , 24  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_REQ1                      , 30  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PRB1                      , 36  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_RESERVED1                        , 42  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_RESERVED1_LEN                    , 2   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_XATS                      , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_XATS_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PWR0                      , 6   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PWR1                      , 12  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_REQ0                      , 18  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PRB0                      , 24  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_REQ1                      , 30  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PRB1                      , 36  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_RESERVED1                        , 42  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_RESERVED1_LEN                    , 2   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_XATS                      , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_XATS_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PWR0                      , 6   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PWR1                      , 12  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_REQ0                      , 18  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PRB0                      , 24  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_REQ1                      , 30  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PRB1                      , 36  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_RESERVED1                        , 42  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_RESERVED1_LEN                    , 2   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_XATS                      , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_XATS_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PWR0                      , 6   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PWR1                      , 12  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_REQ0                      , 18  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PRB0                      , 24  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_REQ1                      , 30  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PRB1                      , 36  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_RESERVED1                        , 42  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_RESERVED1_LEN                    , 2   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_XATS                      , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_XATS_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PWR0                      , 6   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PWR1                      , 12  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_REQ0                      , 18  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PRB0                      , 24  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_REQ1                      , 30  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PRB1                      , 36  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_RESERVED1                        , 42  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_RESERVED1_LEN                    , 2   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_XATS                      , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_XATS_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PWR0                      , 6   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PWR1                      , 12  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_REQ0                      , 18  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PRB0                      , 24  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_REQ1                      , 30  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PRB1                      , 36  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_RESERVED1                        , 42  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_RESERVED1_LEN                    , 2   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_OPER_HANG_DIV_RATIO               , 0   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_OPER_HANG_DIV_RATIO );
+REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_OPER_HANG_DIV_RATIO_LEN           , 5   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_OPER_HANG_DIV_RATIO_LEN );
+REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_RTY_DRP_COUNT                     , 5   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_RTY_DRP_COUNT );
+REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_RTY_DRP_COUNT_LEN                 , 4   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_RTY_DRP_COUNT_LEN );
+REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_DIS_DRP_PRIORITY_INCR             , 9   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_DIS_DRP_PRIORITY_INCR );
+REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_DIS_RETRY_BACKOFF                 , 10  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_DIS_RETRY_BACKOFF );
+REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_DIS_OPER_HANG                     , 11  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_DIS_OPER_HANG );
+
+REG64_FLD( PU_HTM1_HTM_CFG_HTMSC_OPER_HANG_DIV_RATIO               , 0   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_OPER_HANG_DIV_RATIO );
+REG64_FLD( PU_HTM1_HTM_CFG_HTMSC_OPER_HANG_DIV_RATIO_LEN           , 5   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_OPER_HANG_DIV_RATIO_LEN );
+REG64_FLD( PU_HTM1_HTM_CFG_HTMSC_RTY_DRP_COUNT                     , 5   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_RTY_DRP_COUNT );
+REG64_FLD( PU_HTM1_HTM_CFG_HTMSC_RTY_DRP_COUNT_LEN                 , 4   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_RTY_DRP_COUNT_LEN );
+REG64_FLD( PU_HTM1_HTM_CFG_HTMSC_DIS_DRP_PRIORITY_INCR             , 9   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_DIS_DRP_PRIORITY_INCR );
+REG64_FLD( PU_HTM1_HTM_CFG_HTMSC_DIS_RETRY_BACKOFF                 , 10  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_DIS_RETRY_BACKOFF );
+REG64_FLD( PU_HTM1_HTM_CFG_HTMSC_DIS_OPER_HANG                     , 11  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_DIS_OPER_HANG );
+
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_TRIG                             , 0   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_TRIG );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_TRIG_LEN                         , 2   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_TRIG_LEN );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_MARK                             , 4   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_MARK );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_MARK_LEN                         , 2   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_MARK_LEN );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_DBG0_STOP                        , 6   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_DBG0_STOP );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_DBG1_STOP                        , 7   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_DBG1_STOP );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_RUN_STOP                         , 8   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_RUN_STOP );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_OTHER_DBG0_STOP                  , 9   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_OTHER_DBG0_STOP );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_SPARE1012                        , 10  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SPARE1012 );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_SPARE1012_LEN                    , 3   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SPARE1012_LEN );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_XSTOP_STOP                       , 13  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_XSTOP_STOP );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_SPARE1415                        , 14  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SPARE1415 );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_SPARE1415_LEN                    , 2   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SPARE1415_LEN );
+
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_TRIG                             , 0   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_TRIG );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_TRIG_LEN                         , 2   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_TRIG_LEN );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_MARK                             , 4   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_MARK );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_MARK_LEN                         , 2   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_MARK_LEN );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_DBG0_STOP                        , 6   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_DBG0_STOP );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_DBG1_STOP                        , 7   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_DBG1_STOP );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_RUN_STOP                         , 8   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_RUN_STOP );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_OTHER_DBG0_STOP                  , 9   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_OTHER_DBG0_STOP );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_SPARE1012                        , 10  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SPARE1012 );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_SPARE1012_LEN                    , 3   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SPARE1012_LEN );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_XSTOP_STOP                       , 13  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_XSTOP_STOP );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_SPARE1415                        , 14  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SPARE1415 );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_SPARE1415_LEN                    , 2   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SPARE1415_LEN );
+
+REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_PAT                              , 0   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_PAT  );
+REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_PAT_LEN                          , 23  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_PAT_LEN );
+REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_CRESP_PAT                        , 27  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_CRESP_PAT );
+REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_CRESP_PAT_LEN                    , 5   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_CRESP_PAT_LEN );
+REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_MASK                             , 32  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_MASK );
+REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_MASK_LEN                         , 23  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_MASK_LEN );
+REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_CRESP_MASK                       , 59  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_CRESP_MASK );
+REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_CRESP_MASK_LEN                   , 5   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_CRESP_MASK_LEN );
+
+REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_PAT                              , 0   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_PAT  );
+REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_PAT_LEN                          , 23  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_PAT_LEN );
+REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_CRESP_PAT                        , 27  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_CRESP_PAT );
+REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_CRESP_PAT_LEN                    , 5   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_CRESP_PAT_LEN );
+REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_MASK                             , 32  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_MASK );
+REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_MASK_LEN                         , 23  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_MASK_LEN );
+REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_CRESP_MASK                       , 59  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_CRESP_MASK );
+REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_CRESP_MASK_LEN                   , 5   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_CRESP_MASK_LEN );
+
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL0                    , 0   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL0 );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL0_LEN                , 4   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL0_LEN );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL1                    , 4   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL1 );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL1_LEN                , 4   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL1_LEN );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL2                    , 8   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL2 );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL2_LEN                , 4   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL2_LEN );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL3                    , 12  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL3 );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL3_LEN                , 4   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL3_LEN );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL4                    , 16  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL4 );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL4_LEN                , 4   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL4_LEN );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL5                    , 20  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL5 );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL5_LEN                , 4   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL5_LEN );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL0                    , 24  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_CGRPSEL0 );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL0_LEN                , 4   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_CGRPSEL0_LEN );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL1                    , 28  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_CGRPSEL1 );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL1_LEN                , 4   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_CGRPSEL1_LEN );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL2                    , 32  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_CGRPSEL2 );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL2_LEN                , 4   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_CGRPSEL2_LEN );
+
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL0                    , 0   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL0 );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL0_LEN                , 4   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL0_LEN );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL1                    , 4   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL1 );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL1_LEN                , 4   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL1_LEN );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL2                    , 8   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL2 );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL2_LEN                , 4   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL2_LEN );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL3                    , 12  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL3 );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL3_LEN                , 4   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL3_LEN );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL4                    , 16  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL4 );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL4_LEN                , 4   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL4_LEN );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL5                    , 20  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL5 );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL5_LEN                , 4   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_RGRPSEL5_LEN );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL0                    , 24  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_CGRPSEL0 );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL0_LEN                , 4   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_CGRPSEL0_LEN );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL1                    , 28  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_CGRPSEL1 );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL1_LEN                , 4   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_CGRPSEL1_LEN );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL2                    , 32  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_CGRPSEL2 );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL2_LEN                , 4   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_FMUX_CGRPSEL2_LEN );
+
+REG64_FLD( PU_HTM0_HTM_LAST_ADDRESS                                , 8   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_HTM0_HTM_LAST_ADDRESS_LEN                            , 49  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_HTM1_HTM_LAST_ADDRESS                                , 8   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_HTM1_HTM_LAST_ADDRESS_LEN                            , 49  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_ALLOC                             , 0   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_ALLOC );
+REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_SCOPE                             , 1   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SCOPE );
+REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_SCOPE_LEN                         , 3   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SCOPE_LEN );
+REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_PRIORITY                          , 4   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_PRIORITY );
+REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_SIZE_SMALL                        , 5   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SIZE_SMALL );
+REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_SPARE67                           , 6   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SPARE67 );
+REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_SPARE67_LEN                       , 2   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SPARE67_LEN );
+REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_BASE                              , 8   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_BASE );
+REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_BASE_LEN                          , 32  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_BASE_LEN );
+REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_SIZE                              , 40  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SIZE );
+REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_SIZE_LEN                          , 9   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SIZE_LEN );
+
+REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_ALLOC                             , 0   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_ALLOC );
+REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_SCOPE                             , 1   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SCOPE );
+REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_SCOPE_LEN                         , 3   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SCOPE_LEN );
+REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_PRIORITY                          , 4   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_PRIORITY );
+REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_SIZE_SMALL                        , 5   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SIZE_SMALL );
+REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_SPARE67                           , 6   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SPARE67 );
+REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_SPARE67_LEN                       , 2   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SPARE67_LEN );
+REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_BASE                              , 8   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_BASE );
+REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_BASE_LEN                          , 32  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_BASE_LEN );
+REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_SIZE                              , 40  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SIZE );
+REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_SIZE_LEN                          , 9   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SIZE_LEN );
+
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_ENABLE                           , 0   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_ENABLE );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_CONTENT_SEL                      , 1   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_CONTENT_SEL );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_CONTENT_SEL_LEN                  , 2   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_CONTENT_SEL_LEN );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SPARE3                           , 3   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SPARE3 );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_CAPTURE                          , 4   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_CAPTURE );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_CAPTURE_LEN                      , 9   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_CAPTURE_LEN );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_WRAP                             , 13  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_WRAP );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_DIS_TSTAMP                       , 14  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_DIS_TSTAMP );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SINGLE_TSTAMP                    , 15  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SINGLE_TSTAMP );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SPARE16                          , 16  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SPARE16 );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_MARKERS_ONLY                     , 17  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_MARKERS_ONLY );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_DIS_FORCE_GROUP_SCOPE            , 18  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_DIS_FORCE_GROUP_SCOPE );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SYNC_STAMP_FORCE                 , 19  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SYNC_STAMP_FORCE );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SYNC_STAMP_FORCE_LEN             , 3   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SYNC_STAMP_FORCE_LEN );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_WRITETOIO                        , 22  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_WRITETOIO );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SPARE23                          , 23  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SPARE23 );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_VGTARGET                         , 24  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_VGTARGET );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_VGTARGET_LEN                     , 16  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_VGTARGET_LEN );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SPARE4043                        , 40  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SPARE4043 );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SPARE4043_LEN                    , 4   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SPARE4043_LEN );
+
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_ENABLE                           , 0   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_ENABLE );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_CONTENT_SEL                      , 1   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_CONTENT_SEL );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_CONTENT_SEL_LEN                  , 2   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_CONTENT_SEL_LEN );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SPARE3                           , 3   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SPARE3 );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_CAPTURE                          , 4   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_CAPTURE );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_CAPTURE_LEN                      , 9   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_CAPTURE_LEN );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_WRAP                             , 13  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_WRAP );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_DIS_TSTAMP                       , 14  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_DIS_TSTAMP );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SINGLE_TSTAMP                    , 15  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SINGLE_TSTAMP );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SPARE16                          , 16  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SPARE16 );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_MARKERS_ONLY                     , 17  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_MARKERS_ONLY );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_DIS_FORCE_GROUP_SCOPE            , 18  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_DIS_FORCE_GROUP_SCOPE );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SYNC_STAMP_FORCE                 , 19  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SYNC_STAMP_FORCE );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SYNC_STAMP_FORCE_LEN             , 3   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SYNC_STAMP_FORCE_LEN );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_WRITETOIO                        , 22  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_WRITETOIO );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SPARE23                          , 23  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SPARE23 );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_VGTARGET                         , 24  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_VGTARGET );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_VGTARGET_LEN                     , 16  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_VGTARGET_LEN );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SPARE4043                        , 40  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SPARE4043 );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SPARE4043_LEN                    , 4   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_SPARE4043_LEN );
+
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_SPARE                     , 0   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_SPARE );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_SPARE_LEN                 , 2   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_SPARE_LEN );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_CRESP_OV                  , 2   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_CRESP_OV );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_REPAIR                    , 3   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_REPAIR );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_BUF_WAIT                  , 4   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_BUF_WAIT );
+REG64_FLD( PU_HTM0_HTM_STAT_STATUS_TRIG_DROPPED_Q                  , 5   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  , SH_FLD_STATUS_TRIG_DROPPED_Q );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_ADDR_ERROR                , 6   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_ADDR_ERROR );
+REG64_FLD( PU_HTM0_HTM_STAT_STATUS_REC_DROPPED_Q                   , 7   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  , SH_FLD_STATUS_REC_DROPPED_Q );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_INIT                      , 8   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_INIT );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_PREREQ                    , 9   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_PREREQ );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_READY                     , 10  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_READY );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_TRACING                   , 11  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_TRACING );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_PAUSED                    , 12  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_PAUSED );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_FLUSH                     , 13  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_FLUSH );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_COMPLETE                  , 14  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_COMPLETE );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_ENABLE                    , 15  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_ENABLE );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_STAMP                     , 16  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_STAMP );
+REG64_FLD( PU_HTM0_HTM_STAT_STATUS_SCOM_ERROR                      , 17  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  , SH_FLD_STATUS_SCOM_ERROR );
+REG64_FLD( PU_HTM0_HTM_STAT_STATUS_PARITY_ERROR                    , 18  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  , SH_FLD_STATUS_PARITY_ERROR );
+REG64_FLD( PU_HTM0_HTM_STAT_STATUS_INVALID_CRESP                   , 19  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  , SH_FLD_STATUS_INVALID_CRESP );
+
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_SPARE                     , 0   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_SPARE );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_SPARE_LEN                 , 2   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_SPARE_LEN );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_CRESP_OV                  , 2   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_CRESP_OV );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_REPAIR                    , 3   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_REPAIR );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_BUF_WAIT                  , 4   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_BUF_WAIT );
+REG64_FLD( PU_HTM1_HTM_STAT_STATUS_TRIG_DROPPED_Q                  , 5   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  , SH_FLD_STATUS_TRIG_DROPPED_Q );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_ADDR_ERROR                , 6   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_ADDR_ERROR );
+REG64_FLD( PU_HTM1_HTM_STAT_STATUS_REC_DROPPED_Q                   , 7   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  , SH_FLD_STATUS_REC_DROPPED_Q );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_INIT                      , 8   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_INIT );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_PREREQ                    , 9   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_PREREQ );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_READY                     , 10  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_READY );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_TRACING                   , 11  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_TRACING );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_PAUSED                    , 12  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_PAUSED );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_FLUSH                     , 13  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_FLUSH );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_COMPLETE                  , 14  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_COMPLETE );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_ENABLE                    , 15  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_ENABLE );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_STAMP                     , 16  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  , SH_FLD_HTMCO_STATUS_STAMP );
+REG64_FLD( PU_HTM1_HTM_STAT_STATUS_SCOM_ERROR                      , 17  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  , SH_FLD_STATUS_SCOM_ERROR );
+REG64_FLD( PU_HTM1_HTM_STAT_STATUS_PARITY_ERROR                    , 18  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  , SH_FLD_STATUS_PARITY_ERROR );
+REG64_FLD( PU_HTM1_HTM_STAT_STATUS_INVALID_CRESP                   , 19  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  , SH_FLD_STATUS_INVALID_CRESP );
+
+REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_START                            , 0   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_START );
+REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_STOP                             , 1   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_STOP );
+REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_PAUSE                            , 2   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_PAUSE );
+REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_STOP_ALT                         , 3   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_STOP_ALT );
+REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_RESET                            , 4   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_RESET );
+REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_MARK_VALID                       , 5   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_MARK_VALID );
+REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_MARK_TYPE                        , 6   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_MARK_TYPE );
+REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_MARK_TYPE_LEN                    , 10  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_MARK_TYPE_LEN );
+
+REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_START                            , 0   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_START );
+REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_STOP                             , 1   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_STOP );
+REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_PAUSE                            , 2   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_PAUSE );
+REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_STOP_ALT                         , 3   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_STOP_ALT );
+REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_RESET                            , 4   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_RESET );
+REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_MARK_VALID                       , 5   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_MARK_VALID );
+REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_MARK_TYPE                        , 6   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_MARK_TYPE );
+REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_MARK_TYPE_LEN                    , 10  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_MARK_TYPE_LEN );
+
+REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_PAT                         , 1   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_PAT  );
+REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_PAT_LEN                     , 7   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_PAT_LEN );
+REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_PAT               , 8   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_TSIZEFILT_PAT );
+REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_PAT_LEN           , 8   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_TSIZEFILT_PAT_LEN );
+REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_MASK                        , 17  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_MASK );
+REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_MASK_LEN                    , 7   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_MASK_LEN );
+REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_MASK              , 24  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_TSIZEFILT_MASK );
+REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_MASK_LEN          , 8   ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_TSIZEFILT_MASK_LEN );
+REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_INVERT                      , 32  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_INVERT );
+REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_CRESPFILT_INVERT            , 33  ,
+           SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_CRESPFILT_INVERT );
+
+REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_PAT                         , 1   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_PAT  );
+REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_PAT_LEN                     , 7   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_PAT_LEN );
+REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_TSIZEFILT_PAT               , 8   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_TSIZEFILT_PAT );
+REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_TSIZEFILT_PAT_LEN           , 8   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_TSIZEFILT_PAT_LEN );
+REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_MASK                        , 17  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_MASK );
+REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_MASK_LEN                    , 7   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_MASK_LEN );
+REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_TSIZEFILT_MASK              , 24  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_TSIZEFILT_MASK );
+REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_TSIZEFILT_MASK_LEN          , 8   ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_TSIZEFILT_MASK_LEN );
+REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_INVERT                      , 32  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_INVERT );
+REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_CRESPFILT_INVERT            , 33  ,
+           SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  , SH_FLD_HTMSC_CRESPFILT_INVERT );
+
+REG64_FLD( PU_I2C_BUSY_REGISTER_B_PEEK_DATA1_0                     , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_I2C_BUSY_REGISTER_B_PEEK_DATA1_0_LEN                 , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_I2C_BUSY_REGISTER_B_LBUS_PARITY_ERR1_0               , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_I2C_BUSY_REGISTER_C_PEEK_DATA1_1                     , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_I2C_BUSY_REGISTER_C_PEEK_DATA1_1_LEN                 , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_I2C_BUSY_REGISTER_C_LBUS_PARITY_ERR1_1               , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_I2C_BUSY_REGISTER_D_PEEK_DATA1_2                     , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_I2C_BUSY_REGISTER_D_PEEK_DATA1_2_LEN                 , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_I2C_BUSY_REGISTER_D_LBUS_PARITY_ERR1_2               , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_I2C_BUSY_REGISTER_E_PEEK_DATA1_3                     , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_I2C_BUSY_REGISTER_E_PEEK_DATA1_3_LEN                 , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_I2C_BUSY_REGISTER_E_LBUS_PARITY_ERR1_3               , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( PU_INTERRUPTS_B_PEEK_DATA1_0                            , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_INTERRUPTS_B_PEEK_DATA1_0_LEN                        , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_INTERRUPTS_B_LBUS_PARITY_ERR1_0                      , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_INTERRUPTS_C_PEEK_DATA1_1                            , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_INTERRUPTS_C_PEEK_DATA1_1_LEN                        , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_INTERRUPTS_C_LBUS_PARITY_ERR1_1                      , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_INTERRUPTS_D_PEEK_DATA1_2                            , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_INTERRUPTS_D_PEEK_DATA1_2_LEN                        , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_INTERRUPTS_D_LBUS_PARITY_ERR1_2                      , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_INTERRUPTS_E_PEEK_DATA1_3                            , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_INTERRUPTS_E_PEEK_DATA1_3_LEN                        , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_INTERRUPTS_E_LBUS_PARITY_ERR1_3                      , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( PU_INTERRUPT_COND_B_INVALID_CMD_0                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INVALID_CMD_0 );
+REG64_FLD( PU_INTERRUPT_COND_B_LBUS_PARITY_ERROR_0                 , 17  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERROR_0 );
+REG64_FLD( PU_INTERRUPT_COND_B_BE_OV_ERROR_0                       , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BE_OV_ERROR_0 );
+REG64_FLD( PU_INTERRUPT_COND_B_BE_ACC_ERROR_0                      , 19  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BE_ACC_ERROR_0 );
+REG64_FLD( PU_INTERRUPT_COND_B_ARBITRATION_LOST_ERROR_0            , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ARBITRATION_LOST_ERROR_0 );
+REG64_FLD( PU_INTERRUPT_COND_B_NACK_RECEIVED_ERROR_0               , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NACK_RECEIVED_ERROR_0 );
+REG64_FLD( PU_INTERRUPT_COND_B_DATA_REQUEST_0                      , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DATA_REQUEST_0 );
+REG64_FLD( PU_INTERRUPT_COND_B_STOP_ERROR_0                        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STOP_ERROR_0 );
+REG64_FLD( PU_INTERRUPT_COND_B_PEEK_DATA1_0                        , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_INTERRUPT_COND_B_PEEK_DATA1_0_LEN                    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_INTERRUPT_COND_B_LBUS_PARITY_ERR1_0                  , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_INTERRUPT_COND_C_INVALID_CMD_1                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INVALID_CMD_1 );
+REG64_FLD( PU_INTERRUPT_COND_C_LBUS_PARITY_ERROR_1                 , 17  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERROR_1 );
+REG64_FLD( PU_INTERRUPT_COND_C_BE_OV_ERROR_1                       , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BE_OV_ERROR_1 );
+REG64_FLD( PU_INTERRUPT_COND_C_BE_ACC_ERROR_1                      , 19  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BE_ACC_ERROR_1 );
+REG64_FLD( PU_INTERRUPT_COND_C_ARBITRATION_LOST_ERROR_1            , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ARBITRATION_LOST_ERROR_1 );
+REG64_FLD( PU_INTERRUPT_COND_C_NACK_RECEIVED_ERROR_1               , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NACK_RECEIVED_ERROR_1 );
+REG64_FLD( PU_INTERRUPT_COND_C_DATA_REQUEST_1                      , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DATA_REQUEST_1 );
+REG64_FLD( PU_INTERRUPT_COND_C_STOP_ERROR_1                        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STOP_ERROR_1 );
+REG64_FLD( PU_INTERRUPT_COND_C_PEEK_DATA1_1                        , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_INTERRUPT_COND_C_PEEK_DATA1_1_LEN                    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_INTERRUPT_COND_C_LBUS_PARITY_ERR1_1                  , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_INTERRUPT_COND_D_INVALID_CMD_2                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INVALID_CMD_2 );
+REG64_FLD( PU_INTERRUPT_COND_D_LBUS_PARITY_ERROR_2                 , 17  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERROR_2 );
+REG64_FLD( PU_INTERRUPT_COND_D_BE_OV_ERROR_2                       , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BE_OV_ERROR_2 );
+REG64_FLD( PU_INTERRUPT_COND_D_BE_ACC_ERROR_2                      , 19  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BE_ACC_ERROR_2 );
+REG64_FLD( PU_INTERRUPT_COND_D_ARBITRATION_LOST_ERROR_2            , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ARBITRATION_LOST_ERROR_2 );
+REG64_FLD( PU_INTERRUPT_COND_D_NACK_RECEIVED_ERROR_2               , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NACK_RECEIVED_ERROR_2 );
+REG64_FLD( PU_INTERRUPT_COND_D_DATA_REQUEST_2                      , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DATA_REQUEST_2 );
+REG64_FLD( PU_INTERRUPT_COND_D_STOP_ERROR_2                        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STOP_ERROR_2 );
+REG64_FLD( PU_INTERRUPT_COND_D_PEEK_DATA1_2                        , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_INTERRUPT_COND_D_PEEK_DATA1_2_LEN                    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_INTERRUPT_COND_D_LBUS_PARITY_ERR1_2                  , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_INTERRUPT_COND_E_INVALID_CMD_3                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INVALID_CMD_3 );
+REG64_FLD( PU_INTERRUPT_COND_E_LBUS_PARITY_ERROR_3                 , 17  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERROR_3 );
+REG64_FLD( PU_INTERRUPT_COND_E_BE_OV_ERROR_3                       , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BE_OV_ERROR_3 );
+REG64_FLD( PU_INTERRUPT_COND_E_BE_ACC_ERROR_3                      , 19  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BE_ACC_ERROR_3 );
+REG64_FLD( PU_INTERRUPT_COND_E_ARBITRATION_LOST_ERROR_3            , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ARBITRATION_LOST_ERROR_3 );
+REG64_FLD( PU_INTERRUPT_COND_E_NACK_RECEIVED_ERROR_3               , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NACK_RECEIVED_ERROR_3 );
+REG64_FLD( PU_INTERRUPT_COND_E_DATA_REQUEST_3                      , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DATA_REQUEST_3 );
+REG64_FLD( PU_INTERRUPT_COND_E_STOP_ERROR_3                        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STOP_ERROR_3 );
+REG64_FLD( PU_INTERRUPT_COND_E_PEEK_DATA1_3                        , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_INTERRUPT_COND_E_PEEK_DATA1_3_LEN                    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_INTERRUPT_COND_E_LBUS_PARITY_ERR1_3                  , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_B_INT_0                      , 16  ,
+           SH_UNT          , SH_ACS_SCOM2_AND, SH_FLD_INT_0      );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_B_INT_0_LEN                  , 16  ,
+           SH_UNT          , SH_ACS_SCOM2_AND, SH_FLD_INT_0_LEN  );
+
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_C_INT_1                      , 16  ,
+           SH_UNT          , SH_ACS_SCOM2_AND, SH_FLD_INT_1      );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_C_INT_1_LEN                  , 16  ,
+           SH_UNT          , SH_ACS_SCOM2_AND, SH_FLD_INT_1_LEN  );
+
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_D_INT_2                      , 16  ,
+           SH_UNT          , SH_ACS_SCOM2_AND, SH_FLD_INT_2      );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_D_INT_2_LEN                  , 16  ,
+           SH_UNT          , SH_ACS_SCOM2_AND, SH_FLD_INT_2_LEN  );
+
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_E_INT_3                      , 16  ,
+           SH_UNT          , SH_ACS_SCOM2_AND, SH_FLD_INT_3      );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_E_INT_3_LEN                  , 16  ,
+           SH_UNT          , SH_ACS_SCOM2_AND, SH_FLD_INT_3_LEN  );
+
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_B_INT_0                 , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INT_0      );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_B_INT_0_LEN             , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INT_0_LEN  );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_B_PEEK_DATA1_0          , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_B_PEEK_DATA1_0_LEN      , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_B_LBUS_PARITY_ERR1_0    , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_C_INT_1                 , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INT_1      );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_C_INT_1_LEN             , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INT_1_LEN  );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_C_PEEK_DATA1_1          , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_C_PEEK_DATA1_1_LEN      , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_C_LBUS_PARITY_ERR1_1    , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_D_INT_2                 , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INT_2      );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_D_INT_2_LEN             , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INT_2_LEN  );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_D_PEEK_DATA1_2          , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_D_PEEK_DATA1_2_LEN      , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_D_LBUS_PARITY_ERR1_2    , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_E_INT_3                 , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INT_3      );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_E_INT_3_LEN             , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INT_3_LEN  );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_E_PEEK_DATA1_3          , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_E_PEEK_DATA1_3_LEN      , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_E_LBUS_PARITY_ERR1_3    , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_DIS_ECCCHK_IN                    , 0   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_DIS_ECCCHK_IN );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_EXTRA_CMD_SPACING_0_2            , 1   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_EXTRA_CMD_SPACING_0_2 );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_EXTRA_CMD_SPACING_0_2_LEN        , 3   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_EXTRA_CMD_SPACING_0_2_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_EXTRA_DAT_SPACING_0_3            , 4   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_EXTRA_DAT_SPACING_0_3 );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_EXTRA_DAT_SPACING_0_3_LEN        , 4   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_EXTRA_DAT_SPACING_0_3_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_PC_PRIORITY_LIMIT_0_3            , 8   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_PC_PRIORITY_LIMIT_0_3 );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_PC_PRIORITY_LIMIT_0_3_LEN        , 4   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_PC_PRIORITY_LIMIT_0_3_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_VC_PRIORITY_LIMIT_0_3            , 12  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_VC_PRIORITY_LIMIT_0_3 );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_VC_PRIORITY_LIMIT_0_3_LEN        , 4   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_VC_PRIORITY_LIMIT_0_3_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_PRIORITY_LIMIT_0_3               , 16  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_PRIORITY_LIMIT_0_3 );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_PRIORITY_LIMIT_0_3_LEN           , 4   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_PRIORITY_LIMIT_0_3_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_RESERVED_20_31                   , 20  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_RESERVED_20_31 );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_RESERVED_20_31_LEN               , 12  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_RESERVED_20_31_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_CH0_CMD_CREDITS_0_5              , 32  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_CH0_CMD_CREDITS_0_5 );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_CH0_CMD_CREDITS_0_5_LEN          , 6   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_CH0_CMD_CREDITS_0_5_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_CH1_CMD_CREDITS_0_5              , 38  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_CH1_CMD_CREDITS_0_5 );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_CH1_CMD_CREDITS_0_5_LEN          , 6   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_CH1_CMD_CREDITS_0_5_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_CH1_DAT_CREDITS_0_5              , 44  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_CH1_DAT_CREDITS_0_5 );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_CH1_DAT_CREDITS_0_5_LEN          , 6   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_CH1_DAT_CREDITS_0_5_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_CH2_CMD_CREDITS_PC_0_5           , 50  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_CH2_CMD_CREDITS_PC_0_5 );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_CH2_CMD_CREDITS_PC_0_5_LEN       , 6   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_CH2_CMD_CREDITS_PC_0_5_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_CH2_CMD_CREDITS_VC_0_5           , 56  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_CH2_CMD_CREDITS_VC_0_5 );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_CH2_CMD_CREDITS_VC_0_5_LEN       , 6   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_CH2_CMD_CREDITS_VC_0_5_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_RESERVED_62                      , 62  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_RESERVED_62 );
+REG64_FLD( PU_NMMU_INT_CQ_AIB_CTL_REINIT_CREDITS                   , 63  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_REINIT_CREDITS );
+
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_LDQ_IVE_MIN_0_4                  , 0   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_LDQ_IVE_MIN_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_LDQ_IVE_MIN_0_4_LEN              , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_LDQ_IVE_MIN_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_LDQ_IVE_MAX_0_4                  , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_LDQ_IVE_MAX_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_LDQ_IVE_MAX_0_4_LEN              , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_LDQ_IVE_MAX_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_LDQ_EQD_MIN_0_4                  , 10  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_LDQ_EQD_MIN_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_LDQ_EQD_MIN_0_4_LEN              , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_LDQ_EQD_MIN_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_LDQ_EQD_MAX_0_4                  , 15  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_LDQ_EQD_MAX_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_LDQ_EQD_MAX_0_4_LEN              , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_LDQ_EQD_MAX_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_LDQ_THR_MIN_0_4                  , 20  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_LDQ_THR_MIN_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_LDQ_THR_MIN_0_4_LEN              , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_LDQ_THR_MIN_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_LDQ_THR_MAX_0_4                  , 25  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_LDQ_THR_MAX_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_LDQ_THR_MAX_0_4_LEN              , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_LDQ_THR_MAX_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_LDQ_VPC_MIN_0_4                  , 30  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_LDQ_VPC_MIN_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_LDQ_VPC_MIN_0_4_LEN              , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_LDQ_VPC_MIN_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_LDQ_VPC_MAX_0_4                  , 35  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_LDQ_VPC_MAX_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_LDQ_VPC_MAX_0_4_LEN              , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_LDQ_VPC_MAX_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_LDQ_REG_MIN_0_4                  , 40  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_LDQ_REG_MIN_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_LDQ_REG_MIN_0_4_LEN              , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_LDQ_REG_MIN_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_LDQ_REG_MAX_0_4                  , 45  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_LDQ_REG_MAX_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_LDQ_REG_MAX_0_4_LEN              , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_LDQ_REG_MAX_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_LDQ_REG_ORDER_ALL                , 50  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_LDQ_REG_ORDER_ALL );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_RESERVED_51_63                   , 51  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_51_63 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_LDQ_RESERVED_51_63_LEN               , 13  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_51_63_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_CFG_PB_GEN_ADDR_BAR_MODE                 , 0   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_ADDR_BAR_MODE );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_PB_GEN_PUMP_MODE                     , 1   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_PUMP_MODE  );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_PB_GEN_PHYP_SCOPE                    , 2   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_PHYP_SCOPE );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_PB_GEN_INIT                          , 3   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_INIT       );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_PB_GEN_MODE_128K_VP                  , 4   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_MODE_128K_VP );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_PB_GEN_RESERVED_5_15                 , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_RESERVED_5_15 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_PB_GEN_RESERVED_5_15_LEN             , 11  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_RESERVED_5_15_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_IPI_MIN_0_4                 , 0   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_IPI_MIN_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_IPI_MIN_0_4_LEN             , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_IPI_MIN_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_IPI_MAX_0_4                 , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_IPI_MAX_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_IPI_MAX_0_4_LEN             , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_IPI_MAX_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_HW_MIN_0_4                  , 10  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_HW_MIN_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_HW_MIN_0_4_LEN              , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_HW_MIN_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_HW_MAX_0_4                  , 15  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_HW_MAX_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_HW_MAX_0_4_LEN              , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_HW_MAX_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_OS_MIN_0_4                  , 20  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_OS_MIN_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_OS_MIN_0_4_LEN              , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_OS_MIN_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_OS_MAX_0_4                  , 25  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_OS_MAX_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_OS_MAX_0_4_LEN              , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_OS_MAX_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_HYP_MIN_0_4                 , 30  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_HYP_MIN_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_HYP_MIN_0_4_LEN             , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_HYP_MIN_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_HYP_MAX_0_4                 , 35  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_HYP_MAX_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_HYP_MAX_0_4_LEN             , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_HYP_MAX_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_RDI_MIN_0_4                 , 40  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_RDI_MIN_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_RDI_MIN_0_4_LEN             , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_RDI_MIN_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_RDI_MAX_0_4                 , 45  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_RDI_MAX_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_RDI_MAX_0_4_LEN             , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_RDI_MAX_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_THR_MIN_0_4                 , 50  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_THR_MIN_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_THR_MIN_0_4_LEN             , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_THR_MIN_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_THR_MAX_0_4                 , 55  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_THR_MAX_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_STQ_THR_MAX_0_4_LEN             , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_THR_MAX_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_RESERVED_60_63                  , 60  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_60_63 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ1_RESERVED_60_63_LEN              , 4   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_60_63_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ2_STQ_VPC_MIN_0_4                 , 0   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_VPC_MIN_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ2_STQ_VPC_MIN_0_4_LEN             , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_VPC_MIN_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ2_STQ_VPC_MAX_0_4                 , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_VPC_MAX_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ2_STQ_VPC_MAX_0_4_LEN             , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_VPC_MAX_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ2_STQ_REG_MIN_0_4                 , 10  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_REG_MIN_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ2_STQ_REG_MIN_0_4_LEN             , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_REG_MIN_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ2_STQ_REG_MAX_0_4                 , 15  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_REG_MAX_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ2_STQ_REG_MAX_0_4_LEN             , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_STQ_REG_MAX_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ2_RESERVED_20_31                  , 20  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_20_31 );
+REG64_FLD( PU_NMMU_INT_CQ_CFG_STQ2_RESERVED_20_31_LEN              , 12  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_20_31_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE0                  , 0   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_PMON_MUX_BYTE0 );
+REG64_FLD( PU_NMMU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE0_LEN              , 3   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_PMON_MUX_BYTE0_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE1                  , 3   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_PMON_MUX_BYTE1 );
+REG64_FLD( PU_NMMU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE1_LEN              , 3   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_PMON_MUX_BYTE1_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE2                  , 6   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_PMON_MUX_BYTE2 );
+REG64_FLD( PU_NMMU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE2_LEN              , 3   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_PMON_MUX_BYTE2_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE3                  , 9   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_PMON_MUX_BYTE3 );
+REG64_FLD( PU_NMMU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE3_LEN              , 3   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_PMON_MUX_BYTE3_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CNPM_SEL_RESERVED_12_23                  , 12  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_12_23 );
+REG64_FLD( PU_NMMU_INT_CQ_CNPM_SEL_RESERVED_12_23_LEN              , 12  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_12_23_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_CNPM_SEL_EBUS_ENABLE                     , 24  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_EBUS_ENABLE );
+REG64_FLD( PU_NMMU_INT_CQ_CNPM_SEL_EBUS_ENABLE_LEN                 , 16  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_EBUS_ENABLE_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO0_INFO_CAPTURED                  , 0   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_INFO_CAPTURED );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO0_RCMD0_ADDR_PERR                , 1   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_RCMD0_ADDR_PERR );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO0_RCMD1_ADDR_PERR                , 2   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_RCMD1_ADDR_PERR );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO0_RCMD2_ADDR_PERR                , 3   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_RCMD2_ADDR_PERR );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO0_RCMD3_ADDR_PERR                , 4   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_RCMD3_ADDR_PERR );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO0_RCMD0_TTAG_PERR                , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_RCMD0_TTAG_PERR );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO0_RCMD1_TTAG_PERR                , 6   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_RCMD1_TTAG_PERR );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO0_RCMD2_TTAG_PERR                , 7   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_RCMD2_TTAG_PERR );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO0_RCMD3_TTAG_PERR                , 8   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_RCMD3_TTAG_PERR );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO0_CR0_TTAG_PERR                  , 9   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_CR0_TTAG_PERR );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO0_CR1_TTAG_PERR                  , 10  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_CR1_TTAG_PERR );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO0_CR2_TTAG_PERR                  , 11  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_CR2_TTAG_PERR );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO0_CR3_TTAG_PERR                  , 12  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_CR3_TTAG_PERR );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO0_CR0_ATAG_PERR                  , 13  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_CR0_ATAG_PERR );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO0_CR1_ATAG_PERR                  , 14  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_CR1_ATAG_PERR );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO0_CR2_ATAG_PERR                  , 15  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_CR2_ATAG_PERR );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO0_CR3_ATAG_PERR                  , 16  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_CR3_ATAG_PERR );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO0_RTAG_PERR                      , 17  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_RTAG_PERR  );
+
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO1_INFO_CAPTURED                  , 0   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_INFO_CAPTURED );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO1_CI_WRITE                       , 1   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_CI_WRITE   );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO1_CI_READ                        , 2   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_CI_READ    );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO1_DMA_WRITE                      , 3   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_DMA_WRITE  );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO1_TSIZE_4_6                      , 4   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_TSIZE_4_6  );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO1_TSIZE_4_6_LEN                  , 3   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_TSIZE_4_6_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO1_RESERVED_7                     , 7   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_RESERVED_7 );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO1_ADDRESS_8_63                   , 8   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_ADDRESS_8_63 );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO1_ADDRESS_8_63_LEN               , 56  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_ADDRESS_8_63_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO2_INFO_CAPTURED                  , 0   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_INFO_CAPTURED );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO2_RESERVED_1_5                   , 1   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_RESERVED_1_5 );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO2_RESERVED_1_5_LEN               , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_RESERVED_1_5_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO2_HI                             , 6   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_HI         );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO2_LO                             , 7   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_LO         );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO2_RD_ADDR_0_7                    , 8   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_RD_ADDR_0_7 );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO2_RD_ADDR_0_7_LEN                , 8   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_RD_ADDR_0_7_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO2_SYN_HI_0_7                     , 16  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_SYN_HI_0_7 );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO2_SYN_HI_0_7_LEN                 , 8   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_SYN_HI_0_7_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO2_SYN_LO_0_7                     , 24  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_SYN_LO_0_7 );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO2_SYN_LO_0_7_LEN                 , 8   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_SYN_LO_0_7_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO3_INFO_CAPTURED                  , 0   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_INFO_CAPTURED );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO3_STQ_INVALID_ST                 , 1   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_STQ_INVALID_ST );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO3_LDQ_FSM_PERR                   , 2   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_LDQ_FSM_PERR );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO3_WRQ_FSM_PERR                   , 3   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_WRQ_FSM_PERR );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO3_RDQ_FSM_PERR                   , 4   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_RDQ_FSM_PERR );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO3_INTQ_FSM_PERR                  , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_INTQ_FSM_PERR );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO3_WRQ_OVERFLOW                   , 6   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_WRQ_OVERFLOW );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO3_RDQ_OVERFLOW                   , 7   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_RDQ_OVERFLOW );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_INFO3_INTQ_OVERFLOW                  , 8   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_WCLRPART, SH_FLD_INTQ_OVERFLOW );
+
+REG64_FLD( PU_NMMU_INT_CQ_ERR_RPT_HOLD_HOLD_0_51                   , 0   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_HOLD_0_51  );
+REG64_FLD( PU_NMMU_INT_CQ_ERR_RPT_HOLD_HOLD_0_51_LEN               , 52  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_HOLD_0_51_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_IC_BAR_ADDR_8_48                         , 8   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_ADDR_8_48  );
+REG64_FLD( PU_NMMU_INT_CQ_IC_BAR_ADDR_8_48_LEN                     , 41  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_ADDR_8_48_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_MSGSND_CORES_ENABLED                     , 0   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_CORES_ENABLED );
+REG64_FLD( PU_NMMU_INT_CQ_MSGSND_CORES_ENABLED_LEN                 , 24  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_CORES_ENABLED_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_PBI_CTL_DIS_ECCCHK                       , 0   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_DIS_ECCCHK );
+REG64_FLD( PU_NMMU_INT_CQ_PBI_CTL_DIS_ECCCHK_STO                   , 1   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_DIS_ECCCHK_STO );
+REG64_FLD( PU_NMMU_INT_CQ_PBI_CTL_EN_SPEC_CILD                     , 2   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_EN_SPEC_CILD );
+REG64_FLD( PU_NMMU_INT_CQ_PBI_CTL_PAGE_SIZE_64K_IC                 , 3   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_PAGE_SIZE_64K_IC );
+REG64_FLD( PU_NMMU_INT_CQ_PBI_CTL_PAGE_SIZE_64K_TM                 , 4   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_PAGE_SIZE_64K_TM );
+REG64_FLD( PU_NMMU_INT_CQ_PBI_CTL_PAGE_SIZE_64K_PC                 , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_PAGE_SIZE_64K_PC );
+REG64_FLD( PU_NMMU_INT_CQ_PBI_CTL_PAGE_SIZE_64K_VC                 , 6   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_PAGE_SIZE_64K_VC );
+REG64_FLD( PU_NMMU_INT_CQ_PBI_CTL_LINUX_TRIG_MODE                  , 7   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_LINUX_TRIG_MODE );
+REG64_FLD( PU_NMMU_INT_CQ_PBI_CTL_TRACE_BUS_SEL_0_1                , 8   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_TRACE_BUS_SEL_0_1 );
+REG64_FLD( PU_NMMU_INT_CQ_PBI_CTL_TRACE_BUS_SEL_0_1_LEN            , 2   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_TRACE_BUS_SEL_0_1_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_PBI_CTL_TRACE_SEL_0_1                    , 10  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_TRACE_SEL_0_1 );
+REG64_FLD( PU_NMMU_INT_CQ_PBI_CTL_TRACE_SEL_0_1_LEN                , 2   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_TRACE_SEL_0_1_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_PBI_CTL_DIS_DMA_W                        , 12  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_DIS_DMA_W  );
+REG64_FLD( PU_NMMU_INT_CQ_PBI_CTL_STRICT_IPI_RULES                 , 13  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_STRICT_IPI_RULES );
+REG64_FLD( PU_NMMU_INT_CQ_PBI_CTL_FORCE_ECC_CE                     , 14  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_FORCE_ECC_CE );
+REG64_FLD( PU_NMMU_INT_CQ_PBI_CTL_FORCE_ECC_UE                     , 15  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_FORCE_ECC_UE );
+REG64_FLD( PU_NMMU_INT_CQ_PBI_CTL_FORCE_ECC_SEL                    , 16  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_FORCE_ECC_SEL );
+REG64_FLD( PU_NMMU_INT_CQ_PBI_CTL_SPEC_CILD_G                      , 17  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_SPEC_CILD_G );
+REG64_FLD( PU_NMMU_INT_CQ_PBI_CTL_RESERVED_18_31                   , 18  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_RESERVED_18_31 );
+REG64_FLD( PU_NMMU_INT_CQ_PBI_CTL_RESERVED_18_31_LEN               , 14  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_RESERVED_18_31_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_DIS_ECCCHK_LDO                   , 0   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_DIS_ECCCHK_LDO );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_DIS_ECCCHK_WRO                   , 1   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_DIS_ECCCHK_WRO );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_DIS_ECCCHK_CLO                   , 2   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_DIS_ECCCHK_CLO );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_RESERVED_3                       , 3   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_RESERVED_3 );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_STRICT_ORDER                     , 4   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_STRICT_ORDER );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_FORCE_MAX_SCOPE_INTRP            , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_FORCE_MAX_SCOPE_INTRP );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_FORCE_VG_SYS_INTRP               , 6   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_FORCE_VG_SYS_INTRP );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_DROP_PRI_INTRP                   , 7   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_DROP_PRI_INTRP );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_DROP_PRI_HPC_READ                , 8   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_DROP_PRI_HPC_READ );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_DROP_PRI_DMA                     , 9   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_DROP_PRI_DMA );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_DROP_MASK_0_5                    , 10  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_DROP_MASK_0_5 );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_DROP_MASK_0_5_LEN                , 6   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_DROP_MASK_0_5_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_SLOW_CMD_RATE                    , 16  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_SLOW_CMD_RATE );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_EN_RANDOM_BACKOFF                , 17  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_EN_RANDOM_BACKOFF );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_EN_POLL_BACKOFF                  , 18  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_EN_POLL_BACKOFF );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_RESERVED_19                      , 19  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_RESERVED_19 );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_FORCE_ECC_CE                     , 20  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_FORCE_ECC_CE );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_FORCE_ECC_UE                     , 21  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_FORCE_ECC_UE );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_FORCE_ECC_SEL_0_1                , 22  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_FORCE_ECC_SEL_0_1 );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_FORCE_ECC_SEL_0_1_LEN            , 2   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_FORCE_ECC_SEL_0_1_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_DISABLE_INJECT                   , 24  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_DISABLE_INJECT );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_FORCE_CL_INJECT                  , 25  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_FORCE_CL_INJECT );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_FORCE_PR_INJECT                  , 26  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_FORCE_PR_INJECT );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_HANG_ON_ADDR_ERROR               , 27  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_HANG_ON_ADDR_ERROR );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_HANG_ON_ACK_DEAD                 , 28  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_HANG_ON_ACK_DEAD );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_POLL_BCST_RTY_MON                , 29  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_POLL_BCST_RTY_MON );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_MAX_GRP_POLL_BCST_0_4            , 30  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_MAX_GRP_POLL_BCST_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_MAX_GRP_POLL_BCST_0_4_LEN        , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_MAX_GRP_POLL_BCST_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_MAX_ALL_POLL_BCST_0_4            , 35  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_MAX_ALL_POLL_BCST_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_MAX_ALL_POLL_BCST_0_4_LEN        , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_MAX_ALL_POLL_BCST_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_DISABLE_NN_RN                    , 40  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_DISABLE_NN_RN );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_DISABLE_VG_NOT_SYS               , 41  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_DISABLE_G                        , 42  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_DISABLE_G  );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_DISABLE_LN                       , 43  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_DISABLE_LN );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_SKIP_G                           , 44  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_SKIP_G     );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_RESERVED_45_63                   , 45  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_RESERVED_45_63 );
+REG64_FLD( PU_NMMU_INT_CQ_PBO_CTL_RESERVED_45_63_LEN               , 19  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_RESERVED_45_63_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_PC_BAR_ADDR_8_38                         , 8   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_ADDR_8_38  );
+REG64_FLD( PU_NMMU_INT_CQ_PC_BAR_ADDR_8_38_LEN                     , 31  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_ADDR_8_38_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_PC_BARM_ADDR_26_38                       , 26  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_ADDR_26_38 );
+REG64_FLD( PU_NMMU_INT_CQ_PC_BARM_ADDR_26_38_LEN                   , 13  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_ADDR_26_38_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_PMC_0_COUNT_47                           , 16  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_COUNT_47   );
+REG64_FLD( PU_NMMU_INT_CQ_PMC_0_COUNT_47_LEN                       , 48  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_COUNT_47_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_PMC_1_COUNT_0_47                         , 16  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_COUNT_0_47 );
+REG64_FLD( PU_NMMU_INT_CQ_PMC_1_COUNT_0_47_LEN                     , 48  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_COUNT_0_47_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_PMC_2_COUNT_0_47                         , 16  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_COUNT_0_47 );
+REG64_FLD( PU_NMMU_INT_CQ_PMC_2_COUNT_0_47_LEN                     , 48  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_COUNT_0_47_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_PMC_3_COUNT_0_47                         , 16  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_COUNT_0_47 );
+REG64_FLD( PU_NMMU_INT_CQ_PMC_3_COUNT_0_47_LEN                     , 48  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_COUNT_0_47_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_PMC_4_COUNT_0_47                         , 16  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_COUNT_0_47 );
+REG64_FLD( PU_NMMU_INT_CQ_PMC_4_COUNT_0_47_LEN                     , 48  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_COUNT_0_47_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_PMC_5_COUNT_0_47                         , 16  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_COUNT_0_47 );
+REG64_FLD( PU_NMMU_INT_CQ_PMC_5_COUNT_0_47_LEN                     , 48  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_COUNT_0_47_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_PMC_6_COUNT_0_47                         , 16  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_COUNT_0_47 );
+REG64_FLD( PU_NMMU_INT_CQ_PMC_6_COUNT_0_47_LEN                     , 48  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_COUNT_0_47_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_PMC_7_COUNT_0_47                         , 16  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_COUNT_0_47 );
+REG64_FLD( PU_NMMU_INT_CQ_PMC_7_COUNT_0_47_LEN                     , 48  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_COUNT_0_47_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_PM_CTL_ENABLE_0_7                        , 0   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_ENABLE_0_7 );
+REG64_FLD( PU_NMMU_INT_CQ_PM_CTL_ENABLE_0_7_LEN                    , 8   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_ENABLE_0_7_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_PM_CTL_RESET_0_7                         , 8   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_RESET_0_7  );
+REG64_FLD( PU_NMMU_INT_CQ_PM_CTL_RESET_0_7_LEN                     , 8   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_RESET_0_7_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_PM_CTL_SOURCE_SUBUNIT_0_1                , 16  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_SOURCE_SUBUNIT_0_1 );
+REG64_FLD( PU_NMMU_INT_CQ_PM_CTL_SOURCE_SUBUNIT_0_1_LEN            , 2   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_SOURCE_SUBUNIT_0_1_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_PM_CTL_GROUP_SEL_0_4                     , 18  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_GROUP_SEL_0_4 );
+REG64_FLD( PU_NMMU_INT_CQ_PM_CTL_GROUP_SEL_0_4_LEN                 , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_GROUP_SEL_0_4_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_RST_CTL_SYNC_RESET                       , 0   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_SYNC_RESET );
+REG64_FLD( PU_NMMU_INT_CQ_RST_CTL_QUIESCE_PB                       , 1   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_QUIESCE_PB );
+REG64_FLD( PU_NMMU_INT_CQ_RST_CTL_MASTER_IDLE                      , 2   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_MASTER_IDLE );
+REG64_FLD( PU_NMMU_INT_CQ_RST_CTL_SLAVE_IDLE                       , 3   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_SLAVE_IDLE );
+REG64_FLD( PU_NMMU_INT_CQ_RST_CTL_RESERVED_4_7                     , 4   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_RESERVED_4_7 );
+REG64_FLD( PU_NMMU_INT_CQ_RST_CTL_RESERVED_4_7_LEN                 , 4   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM     , SH_FLD_RESERVED_4_7_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_SWI_RSP_HIST_DONE                        , 0   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_HIST_DONE  );
+REG64_FLD( PU_NMMU_INT_CQ_SWI_RSP_POLL_DONE                        , 1   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_POLL_DONE  );
+REG64_FLD( PU_NMMU_INT_CQ_SWI_RSP_BCAST_DONE                       , 2   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_BCAST_DONE );
+REG64_FLD( PU_NMMU_INT_CQ_SWI_RSP_ASSN_DONE                        , 3   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_ASSN_DONE  );
+REG64_FLD( PU_NMMU_INT_CQ_SWI_RSP_BLKU_DONE                        , 4   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_BLKU_DONE  );
+REG64_FLD( PU_NMMU_INT_CQ_SWI_RSP_Z                                , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_Z          );
+REG64_FLD( PU_NMMU_INT_CQ_SWI_RSP_O                                , 6   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_O          );
+REG64_FLD( PU_NMMU_INT_CQ_SWI_RSP_M                                , 7   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_M          );
+REG64_FLD( PU_NMMU_INT_CQ_SWI_RSP_CRESP_0_4                        , 8   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_CRESP_0_4  );
+REG64_FLD( PU_NMMU_INT_CQ_SWI_RSP_CRESP_0_4_LEN                    , 5   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_CRESP_0_4_LEN );
+REG64_FLD( PU_NMMU_INT_CQ_SWI_RSP_RSVD0                            , 13  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_RSVD0      );
+REG64_FLD( PU_NMMU_INT_CQ_SWI_RSP_COLLISON                         , 14  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_COLLISON   );
+REG64_FLD( PU_NMMU_INT_CQ_SWI_RSP_PRECLUDE                         , 15  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_PRECLUDE   );
+REG64_FLD( PU_NMMU_INT_CQ_SWI_RSP_ATAG_0_15                        , 16  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_ATAG_0_15  );
+REG64_FLD( PU_NMMU_INT_CQ_SWI_RSP_ATAG_0_15_LEN                    , 16  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RO  , SH_FLD_ATAG_0_15_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_TM1_BAR_ADDR_8_49                        , 8   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_ADDR_8_49  );
+REG64_FLD( PU_NMMU_INT_CQ_TM1_BAR_ADDR_8_49_LEN                    , 42  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_ADDR_8_49_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_TM2_BAR_ADDR_8_49                        , 8   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_ADDR_8_49  );
+REG64_FLD( PU_NMMU_INT_CQ_TM2_BAR_ADDR_8_49_LEN                    , 42  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_ADDR_8_49_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_VC_BAR_ADDR_8_37                         , 8   ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_ADDR_8_37  );
+REG64_FLD( PU_NMMU_INT_CQ_VC_BAR_ADDR_8_37_LEN                     , 30  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_ADDR_8_37_LEN );
+
+REG64_FLD( PU_NMMU_INT_CQ_VC_BARM_ADDR_21_37                       , 21  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_ADDR_21_37 );
+REG64_FLD( PU_NMMU_INT_CQ_VC_BARM_ADDR_21_37_LEN                   , 17  ,
+           SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  , SH_FLD_ADDR_21_37_LEN );
+
+REG64_FLD( PU_INT_PC_AIB_MAX_CMD_CRD_REG_CH0                       , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH0        );
+REG64_FLD( PU_INT_PC_AIB_MAX_CMD_CRD_REG_CH0_LEN                   , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH0_LEN    );
+REG64_FLD( PU_INT_PC_AIB_MAX_CMD_CRD_REG_CH1                       , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH1        );
+REG64_FLD( PU_INT_PC_AIB_MAX_CMD_CRD_REG_CH1_LEN                   , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH1_LEN    );
+REG64_FLD( PU_INT_PC_AIB_MAX_CMD_CRD_REG_CH2                       , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH2        );
+REG64_FLD( PU_INT_PC_AIB_MAX_CMD_CRD_REG_CH2_LEN                   , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH2_LEN    );
+REG64_FLD( PU_INT_PC_AIB_MAX_CMD_CRD_REG_CH3                       , 18  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH3        );
+REG64_FLD( PU_INT_PC_AIB_MAX_CMD_CRD_REG_CH3_LEN                   , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH3_LEN    );
+
+REG64_FLD( PU_INT_PC_AIB_MAX_DAT_CRD_REG_CH0                       , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH0        );
+REG64_FLD( PU_INT_PC_AIB_MAX_DAT_CRD_REG_CH0_LEN                   , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH0_LEN    );
+REG64_FLD( PU_INT_PC_AIB_MAX_DAT_CRD_REG_CH1                       , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH1        );
+REG64_FLD( PU_INT_PC_AIB_MAX_DAT_CRD_REG_CH1_LEN                   , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH1_LEN    );
+REG64_FLD( PU_INT_PC_AIB_MAX_DAT_CRD_REG_CH2                       , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH2        );
+REG64_FLD( PU_INT_PC_AIB_MAX_DAT_CRD_REG_CH2_LEN                   , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH2_LEN    );
+REG64_FLD( PU_INT_PC_AIB_MAX_DAT_CRD_REG_CH3                       , 18  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH3        );
+REG64_FLD( PU_INT_PC_AIB_MAX_DAT_CRD_REG_CH3_LEN                   , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH3_LEN    );
+
+REG64_FLD( PU_INT_PC_CRD_INIT_TIMER_TIMER                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_TIMER      );
+REG64_FLD( PU_INT_PC_CRD_INIT_TIMER_TIMER_LEN                      , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_TIMER_LEN  );
+
+REG64_FLD( PU_INT_PC_GEN_CFG_INDIRECT_MODE                         , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_INDIRECT_MODE );
+REG64_FLD( PU_INT_PC_GEN_CFG_RESERVED_33_63                        , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_33_63 );
+REG64_FLD( PU_INT_PC_GEN_CFG_RESERVED_33_63_LEN                    , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_33_63_LEN );
+
+REG64_FLD( PU_INT_PC_INDIR0_REG_VLD                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VLD        );
+REG64_FLD( PU_INT_PC_INDIR0_REG_THRDID                             , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_THRDID     );
+REG64_FLD( PU_INT_PC_INDIR0_REG_THRDID_LEN                         , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_THRDID_LEN );
+
+REG64_FLD( PU_INT_PC_INDIR1_REG_VLD                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VLD        );
+REG64_FLD( PU_INT_PC_INDIR1_REG_THRDID                             , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_THRDID     );
+REG64_FLD( PU_INT_PC_INDIR1_REG_THRDID_LEN                         , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_THRDID_LEN );
+
+REG64_FLD( PU_INT_PC_INDIR2_REG_VLD                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VLD        );
+REG64_FLD( PU_INT_PC_INDIR2_REG_THRDID                             , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_THRDID     );
+REG64_FLD( PU_INT_PC_INDIR2_REG_THRDID_LEN                         , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_THRDID_LEN );
+
+REG64_FLD( PU_INT_PC_INDIR3_REG_VLD                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VLD        );
+REG64_FLD( PU_INT_PC_INDIR3_REG_THRDID                             , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_THRDID     );
+REG64_FLD( PU_INT_PC_INDIR3_REG_THRDID_LEN                         , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_THRDID_LEN );
+
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_DONE_PARSE_PULL_RR_SEL       , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_DONE_PARSE_PULL_RR_SEL );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_DONE_PARSE_PULL_RR_SEL_LEN   , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_DONE_PARSE_PULL_RR_SEL_LEN );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_DONE_PARSE_IACK_RR_SEL       , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_DONE_PARSE_IACK_RR_SEL );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_DONE_PARSE_IACK_RR_SEL_LEN   , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_DONE_PARSE_IACK_RR_SEL_LEN );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_DONE_PULL_PRIO_HYP           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_DONE_PULL_PRIO_HYP );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_DONE_PULL_PRIO_HYP_LEN       , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_DONE_PULL_PRIO_HYP_LEN );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_DONE_IACK_PRIO_HYP           , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_DONE_IACK_PRIO_HYP );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_DONE_IACK_PRIO_HYP_LEN       , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_DONE_IACK_PRIO_HYP_LEN );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_DONE_PRIO_IACK               , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_DONE_PRIO_IACK );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_DONE_PRIO_IACK_LEN           , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_DONE_PRIO_IACK_LEN );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_PCMD_PRIO_LDST_SET           , 13  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PCMD_PRIO_LDST_SET );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_PCMD_PRIO_LDST_SET_LEN       , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PCMD_PRIO_LDST_SET_LEN );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_PCMD_PRIO_LDST_RSP           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PCMD_PRIO_LDST_RSP );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_PCMD_PRIO_LDST_RSP_LEN       , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PCMD_PRIO_LDST_RSP_LEN );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_PCMD_PRIO_DONE               , 19  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PCMD_PRIO_DONE );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_PCMD_PRIO_DONE_LEN           , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PCMD_PRIO_DONE_LEN );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_PCMD_PRIO_RR                 , 22  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PCMD_PRIO_RR );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_PCMD_PRIO_RR_LEN             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PCMD_PRIO_RR_LEN );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_LDST_PRIO_SET_LD             , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_LDST_PRIO_SET_LD );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_LDST_PRIO_SET_LD_LEN         , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_LDST_PRIO_SET_LD_LEN );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_LDST_PRIO_RSP_LD             , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_LDST_PRIO_RSP_LD );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_LDST_PRIO_RSP_LD_LEN         , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_LDST_PRIO_RSP_LD_LEN );
+
+REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_CFG_PRIO_LSI                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PRIO_LSI );
+REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_CFG_PRIO_LSI_LEN                 , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PRIO_LSI_LEN );
+REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_CFG_PRIO_MMIO                    , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PRIO_MMIO );
+REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_CFG_PRIO_MMIO_LEN                , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PRIO_MMIO_LEN );
+REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_CFG_PRIO_VRQ_REQ                 , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PRIO_VRQ_REQ );
+REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_CFG_PRIO_VRQ_REQ_LEN             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PRIO_VRQ_REQ_LEN );
+REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_CFG_PRIO_VRQ_RSP                 , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PRIO_VRQ_RSP );
+REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_CFG_PRIO_VRQ_RSP_LEN             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PRIO_VRQ_RSP_LEN );
+REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_CFG_PRIO_RR                      , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PRIO_RR );
+REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_CFG_PRIO_RR_LEN                  , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PRIO_RR_LEN );
+
+REG64_FLD( PU_INT_PC_REGS_ERR_CFG_REG0_ERROR_CONFIG                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ERROR_CONFIG );
+REG64_FLD( PU_INT_PC_REGS_ERR_CFG_REG0_ERROR_CONFIG_LEN            , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ERROR_CONFIG_LEN );
+
+REG64_FLD( PU_INT_PC_REGS_ERR_CFG_REG1_ERROR_CONFIG                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ERROR_CONFIG );
+REG64_FLD( PU_INT_PC_REGS_ERR_CFG_REG1_ERROR_CONFIG_LEN            , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ERROR_CONFIG_LEN );
+
+REG64_FLD( PU_INT_PC_REGS_FATAL_ERR_ERROR                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR      );
+REG64_FLD( PU_INT_PC_REGS_FATAL_ERR_ERROR_LEN                      , 64  ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_PC_REGS_INFO_ERR_ERROR                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR      );
+REG64_FLD( PU_INT_PC_REGS_INFO_ERR_ERROR_LEN                       , 64  ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_PC_REGS_RECOV_ERR_ERROR                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR      );
+REG64_FLD( PU_INT_PC_REGS_RECOV_ERR_ERROR_LEN                      , 64  ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_PC_REGS_WOF_ERR_ERROR                            , 0   ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR      );
+REG64_FLD( PU_INT_PC_REGS_WOF_ERR_ERROR_LEN                        , 64  ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_PC_REGS_WOF_ERR_DETAIL_ERROR                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ERROR      );
+REG64_FLD( PU_INT_PC_REGS_WOF_ERR_DETAIL_ERROR_LEN                 , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_CHIPID                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHIPID     );
+REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_CHIPID_LEN                      , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHIPID_LEN );
+REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_CHIPID_OVERRIDE                 , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHIPID_OVERRIDE );
+REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_HARD_CHIPID_IN_BLOCK_EN         , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HARD_CHIPID_IN_BLOCK_EN );
+REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_24CORE_EN                       , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_24CORE_EN  );
+REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_ACM_EN                          , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACM_EN     );
+REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_BLOCK_TRACK_EN                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BLOCK_TRACK_EN );
+REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_LBS_IDX0_SEL                    , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LBS_IDX0_SEL );
+REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_WAKEUP_PULSE                    , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WAKEUP_PULSE );
+REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_WAKEUP_PULSE_LEN                , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WAKEUP_PULSE_LEN );
+REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_BLOCK_GROUP_EN                  , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BLOCK_GROUP_EN );
+REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_BLOCK_TRACK_RESET_DELAY         , 15  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BLOCK_TRACK_RESET_DELAY );
+REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_BLOCK_TRACK_RESET_DELAY_LEN     , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BLOCK_TRACK_RESET_DELAY_LEN );
+
+REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C0                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C0     );
+REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C0_LEN                       , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C0_LEN );
+REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C1                           , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C1     );
+REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C1_LEN                       , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C1_LEN );
+REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C2                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C2     );
+REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C2_LEN                       , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C2_LEN );
+REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C3                           , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C3     );
+REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C3_LEN                       , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C3_LEN );
+REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C4                           , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C4     );
+REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C4_LEN                       , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C4_LEN );
+REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C5                           , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C5     );
+REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C5_LEN                       , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C5_LEN );
+REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C6                           , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C6     );
+REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C6_LEN                       , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C6_LEN );
+REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C7                           , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C7     );
+REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C7_LEN                       , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C7_LEN );
+
+REG64_FLD( PU_INT_PC_THRD_EN_REG1_CFG_C8                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C8     );
+REG64_FLD( PU_INT_PC_THRD_EN_REG1_CFG_C8_LEN                       , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C8_LEN );
+REG64_FLD( PU_INT_PC_THRD_EN_REG1_CFG_C9                           , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C9     );
+REG64_FLD( PU_INT_PC_THRD_EN_REG1_CFG_C9_LEN                       , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C9_LEN );
+REG64_FLD( PU_INT_PC_THRD_EN_REG1_CFG_C10                          , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C10    );
+REG64_FLD( PU_INT_PC_THRD_EN_REG1_CFG_C10_LEN                      , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C10_LEN );
+REG64_FLD( PU_INT_PC_THRD_EN_REG1_CFG_C11                          , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C11    );
+REG64_FLD( PU_INT_PC_THRD_EN_REG1_CFG_C11_LEN                      , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_C11_LEN );
+
+REG64_FLD( PU_INT_PC_VRQ_ARB_CFG_CFG_PRIO_RSVD                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PRIO_RSVD );
+REG64_FLD( PU_INT_PC_VRQ_ARB_CFG_CFG_PRIO_RSVD_LEN                 , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PRIO_RSVD_LEN );
+REG64_FLD( PU_INT_PC_VRQ_ARB_CFG_CFG_PRIO_PULL                     , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PRIO_PULL );
+REG64_FLD( PU_INT_PC_VRQ_ARB_CFG_CFG_PRIO_PULL_LEN                 , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PRIO_PULL_LEN );
+REG64_FLD( PU_INT_PC_VRQ_ARB_CFG_CFG_PRIO_PUSH_LCL                 , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PRIO_PUSH_LCL );
+REG64_FLD( PU_INT_PC_VRQ_ARB_CFG_CFG_PRIO_PUSH_LCL_LEN             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PRIO_PUSH_LCL_LEN );
+REG64_FLD( PU_INT_PC_VRQ_ARB_CFG_CFG_PRIO_PUSH_ARX                 , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PRIO_PUSH_ARX );
+REG64_FLD( PU_INT_PC_VRQ_ARB_CFG_CFG_PRIO_PUSH_ARX_LEN             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PRIO_PUSH_ARX_LEN );
+REG64_FLD( PU_INT_PC_VRQ_ARB_CFG_CFG_PRIO_RR                       , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PRIO_RR );
+REG64_FLD( PU_INT_PC_VRQ_ARB_CFG_CFG_PRIO_RR_LEN                   , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PRIO_RR_LEN );
+REG64_FLD( PU_INT_PC_VRQ_ARB_CFG_CFG_STALL                         , 15  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_STALL  );
+
+REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_PULL_RSVD                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PULL_RSVD );
+REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_PULL_RSVD_LEN                 , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PULL_RSVD_LEN );
+REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_VPC_PULL_LMIT                 , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_VPC_PULL_LMIT );
+REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_VPC_PULL_LMIT_LEN             , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_VPC_PULL_LMIT_LEN );
+REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_VPC_PUSH_LCL_RSVD             , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_VPC_PUSH_LCL_RSVD );
+REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_VPC_PUSH_LCL_RSVD_LEN         , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_VPC_PUSH_LCL_RSVD_LEN );
+REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_VPC_PUSH_LCL_LMIT             , 18  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_VPC_PUSH_LCL_LMIT );
+REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_VPC_PUSH_LCL_LMIT_LEN         , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_VPC_PUSH_LCL_LMIT_LEN );
+REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_PUSH_ARX_RSVD                 , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PUSH_ARX_RSVD );
+REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_PUSH_ARX_RSVD_LEN             , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PUSH_ARX_RSVD_LEN );
+REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_VPC_PUSH_ARX_LMIT             , 30  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_VPC_PUSH_ARX_LMIT );
+REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_VPC_PUSH_ARX_LMIT_LEN         , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_VPC_PUSH_ARX_LMIT_LEN );
+REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_MAX                           , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_MAX    );
+REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_MAX_LEN                       , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_MAX_LEN );
+
+REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_PARSE_QUERY_RR_SEL           , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PARSE_QUERY_RR_SEL );
+REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_PARSE_QUERY_RR_SEL_LEN       , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PARSE_QUERY_RR_SEL_LEN );
+REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_PARSE_PULL_RR_SEL            , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PARSE_PULL_RR_SEL );
+REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_PARSE_PULL_RR_SEL_LEN        , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PARSE_PULL_RR_SEL_LEN );
+REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_PARSE_PUSH_RR_SEL            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PARSE_PUSH_RR_SEL );
+REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_PARSE_PUSH_RR_SEL_LEN        , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PARSE_PUSH_RR_SEL_LEN );
+REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PULL_PRIO_HYP            , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_ARB_PULL_PRIO_HYP );
+REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PULL_PRIO_HYP_LEN        , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_ARB_PULL_PRIO_HYP_LEN );
+REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PUSH_PRIO_HYP            , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_ARB_PUSH_PRIO_HYP );
+REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PUSH_PRIO_HYP_LEN        , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_ARB_PUSH_PRIO_HYP_LEN );
+REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PRIO_QUERY               , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_ARB_PRIO_QUERY );
+REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PRIO_QUERY_LEN           , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_ARB_PRIO_QUERY_LEN );
+REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PRIO_PUSH                , 15  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_ARB_PRIO_PUSH );
+REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PRIO_PUSH_LEN            , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_ARB_PRIO_PUSH_LEN );
+REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PRIO_PULL                , 18  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_ARB_PRIO_PULL );
+REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PRIO_PULL_LEN            , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_ARB_PRIO_PULL_LEN );
+REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PRIO_RR                  , 21  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_ARB_PRIO_RR );
+REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PRIO_RR_LEN              , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_ARB_PRIO_RR_LEN );
+
+REG64_FLD( PU_INT_PC_VRQ_QUE_CFG_CFG_QUEUE_ECC_CORR_EN             , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_QUEUE_ECC_CORR_EN );
+REG64_FLD( PU_INT_PC_VRQ_QUE_CFG_CFG_QUEUE_SIZE_PULL               , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_QUEUE_SIZE_PULL );
+REG64_FLD( PU_INT_PC_VRQ_QUE_CFG_CFG_QUEUE_SIZE_PULL_LEN           , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_QUEUE_SIZE_PULL_LEN );
+REG64_FLD( PU_INT_PC_VRQ_QUE_CFG_CFG_QUEUE_SIZE_PUSH_LCL           , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_QUEUE_SIZE_PUSH_LCL );
+REG64_FLD( PU_INT_PC_VRQ_QUE_CFG_CFG_QUEUE_SIZE_PUSH_LCL_LEN       , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_QUEUE_SIZE_PUSH_LCL_LEN );
+
+REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_AUTO_INCREMENT                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_AUTO_INCREMENT );
+REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_SELECT                         , 13  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SELECT     );
+REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_SELECT_LEN                     , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SELECT_LEN );
+REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_RESERVED_16_26                 , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_16_26 );
+REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_RESERVED_16_26_LEN             , 11  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_16_26_LEN );
+REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_ADDRESS                        , 27  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_ADDRESS_LEN                    , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_INT_VC_AIB_TIMEOUT_DELAY                             , 58  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DELAY      );
+REG64_FLD( PU_INT_VC_AIB_TIMEOUT_DELAY_LEN                         , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DELAY_LEN  );
+
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_32_43            , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32_43 );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_32_43_LEN        , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32_43_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_REGS         , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ATX_PRIO_FOR_REGS );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_REGS_LEN     , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ATX_PRIO_FOR_REGS_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_IRQ          , 46  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ATX_PRIO_FOR_IRQ );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_IRQ_LEN      , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ATX_PRIO_FOR_IRQ_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_IVC          , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ATX_PRIO_FOR_IVC );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_IVC_LEN      , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ATX_PRIO_FOR_IVC_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_50_51            , 50  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_50_51 );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_50_51_LEN        , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_50_51_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_SBC_EOI_RESP , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ATX_PRIO_FOR_SBC_EOI_RESP );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_SBC_EOI_RESP_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ATX_PRIO_FOR_SBC_EOI_RESP_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_SBC_DMA      , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ATX_PRIO_FOR_SBC_DMA );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_SBC_DMA_LEN  , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ATX_PRIO_FOR_SBC_DMA_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_TRIG_FWD     , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ATX_PRIO_FOR_TRIG_FWD );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_TRIG_FWD_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ATX_PRIO_FOR_TRIG_FWD_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_EQC_EOI_EQP  , 58  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ATX_PRIO_FOR_EQC_EOI_EQP );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_EQC_EOI_EQP_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ATX_PRIO_FOR_EQC_EOI_EQP_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_LSS_CI_LOAD  , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ATX_PRIO_FOR_LSS_CI_LOAD );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_LSS_CI_LOAD_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ATX_PRIO_FOR_LSS_CI_LOAD_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_EQD_DMA      , 62  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ATX_PRIO_FOR_EQD_DMA );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_EQD_DMA_LEN  , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ATX_PRIO_FOR_EQD_DMA_LEN );
+
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_REGS                    , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_REGS       );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_REGS_LEN                , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_REGS_LEN   );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_IRQ                     , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_IRQ        );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_IRQ_LEN                 , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_IRQ_LEN    );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_IVC                     , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_IVC        );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_IVC_LEN                 , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_IVC_LEN    );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_RESERVED_48_55          , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_48_55 );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_RESERVED_48_55_LEN      , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_48_55_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_EOI                 , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SBC_EOI    );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_EOI_LEN             , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SBC_EOI_LEN );
+
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RESERVED_20_22          , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_20_22 );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RESERVED_20_22_LEN      , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_20_22_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_DISABLE_PTAG_IN_AIBTAG  , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DISABLE_PTAG_IN_AIBTAG );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_SBC_DMA                 , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SBC_DMA    );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_SBC_DMA_LEN             , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SBC_DMA_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_CISTORE             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EQC_CISTORE );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_CISTORE_LEN         , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EQC_CISTORE_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_EQP             , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EQC_EOI_EQP );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_EQP_LEN         , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EQC_EOI_EQP_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_CILOAD              , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EQC_CILOAD );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_CILOAD_LEN          , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EQC_CILOAD_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_DMA                 , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EQC_DMA    );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_DMA_LEN             , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EQC_DMA_LEN );
+
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_CRD_REQUEST             , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CRD_REQUEST );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_25             , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_25 );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_DMA_READ        , 26  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RSD_CRD_DMA_READ );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_DMA_READ_LEN    , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RSD_CRD_DMA_READ_LEN );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_AT_MACRO        , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RSD_CRD_AT_MACRO );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_AT_MACRO_LEN    , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RSD_CRD_AT_MACRO_LEN );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_EQC_DOING_CI_LOAD , 30  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RSD_CRD_EQC_DOING_CI_LOAD );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_EQC_DOING_CI_LOAD_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RSD_CRD_EQC_DOING_CI_LOAD_LEN );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_32_33          , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32_33 );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_32_33_LEN      , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32_33_LEN );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_READ_CRD_POOL           , 34  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_READ_CRD_POOL );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_READ_CRD_POOL_LEN       , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_READ_CRD_POOL_LEN );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_40_47          , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_40_47 );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_40_47_LEN      , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_40_47_LEN );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_DMA_WRITE       , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RSD_CRD_DMA_WRITE );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_DMA_WRITE_LEN   , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RSD_CRD_DMA_WRITE_LEN );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_EQ_POST         , 50  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RSD_CRD_EQ_POST );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_EQ_POST_LEN     , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RSD_CRD_EQ_POST_LEN );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_TRIG_FWD_1      , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RSD_CRD_TRIG_FWD_1 );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_TRIG_FWD_1_LEN  , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RSD_CRD_TRIG_FWD_1_LEN );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_TRIG_FWD_2      , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RSD_CRD_TRIG_FWD_2 );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_TRIG_FWD_2_LEN  , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RSD_CRD_TRIG_FWD_2_LEN );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_56_58          , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_56_58 );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_56_58_LEN      , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_56_58_LEN );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_WRITE_CRD_POOL          , 59  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRITE_CRD_POOL );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_WRITE_CRD_POOL_LEN      , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRITE_CRD_POOL_LEN );
+
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R0                   , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R0     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R0_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R0_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R1R                  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R1R    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R1R_LEN              , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R1R_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R1W                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R1W    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R1W_LEN              , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R1W_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R2                   , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R2     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R2_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R2_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R3                   , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R3     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R3_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R3_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R4                   , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R4     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R4_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R4_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R5R                  , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R5R    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R5R_LEN              , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R5R_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R5W                  , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R5W    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R5W_LEN              , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R5W_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R6                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R6     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R6_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R6_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7RSP                , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R7RSP  );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7RSP_LEN            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R7RSP_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7INT                , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R7INT  );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7INT_LEN            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R7INT_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7EQP                , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R7EQP  );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7EQP_LEN            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R7EQP_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R8                   , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R8     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R8_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R8_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R9                   , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R9     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R9_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R9_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R10R                 , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R10R   );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R10R_LEN             , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R10R_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R10W                 , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R10W   );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R10W_LEN             , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R10W_LEN );
+
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R0                   , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R0     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R0_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R0_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R1R                  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R1R    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R1R_LEN              , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R1R_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R1W                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R1W    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R1W_LEN              , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R1W_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R2                   , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R2     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R2_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R2_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R3                   , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R3     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R3_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R3_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R4                   , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R4     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R4_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R4_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R5R                  , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R5R    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R5R_LEN              , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R5R_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R5W                  , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R5W    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R5W_LEN              , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R5W_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R6                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R6     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R6_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R6_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7RSP                , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R7RSP  );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7RSP_LEN            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R7RSP_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7INT                , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R7INT  );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7INT_LEN            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R7INT_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7EQP                , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R7EQP  );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7EQP_LEN            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R7EQP_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R8                   , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R8     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R8_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R8_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R9                   , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R9     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R9_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R9_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R10R                 , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R10R   );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R10R_LEN             , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R10R_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R10W                 , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R10W   );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R10W_LEN             , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R10W_LEN );
+
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R0                   , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R0     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R0_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R0_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R1R                  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R1R    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R1R_LEN              , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R1R_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R1W                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R1W    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R1W_LEN              , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R1W_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R2                   , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R2     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R2_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R2_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R3                   , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R3     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R3_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R3_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R4                   , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R4     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R4_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R4_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R5R                  , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R5R    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R5R_LEN              , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R5R_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R5W                  , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R5W    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R5W_LEN              , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R5W_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R6                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R6     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R6_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R6_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7RSP                , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R7RSP  );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7RSP_LEN            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R7RSP_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7INT                , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R7INT  );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7INT_LEN            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R7INT_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7EQP                , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R7EQP  );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7EQP_LEN            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R7EQP_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R8                   , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R8     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R8_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R8_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R9                   , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R9     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R9_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R9_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R10R                 , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R10R   );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R10R_LEN             , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R10R_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R10W                 , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R10W   );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R10W_LEN             , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_R10W_LEN );
+
+REG64_FLD( PU_INT_VC_AT_MACRO_KILL_VALID                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VALID      );
+REG64_FLD( PU_INT_VC_AT_MACRO_KILL_VST_TYPE                        , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VST_TYPE   );
+REG64_FLD( PU_INT_VC_AT_MACRO_KILL_VST_TYPE_LEN                    , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VST_TYPE_LEN );
+REG64_FLD( PU_INT_VC_AT_MACRO_KILL_BLOCKID                         , 27  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_VC_AT_MACRO_KILL_BLOCKID_LEN                     , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_VC_AT_MACRO_KILL_OFFSET                          , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_VC_AT_MACRO_KILL_OFFSET_LEN                      , 13  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_OFFSET_LEN );
+
+REG64_FLD( PU_INT_VC_AT_MACRO_KILL_MASK_BLOCKID                    , 27  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_VC_AT_MACRO_KILL_MASK_BLOCKID_LEN                , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_VC_AT_MACRO_KILL_MASK_OFFSET                     , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_VC_AT_MACRO_KILL_MASK_OFFSET_LEN                 , 13  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_OFFSET_LEN );
+
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_P0_IS_IDLE              , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_P0_IS_IDLE );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_P1_IS_IDLE              , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_P1_IS_IDLE );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_PTAG_IN_USE         , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_PTAG_IN_USE );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_PTAG_IN_USE_LEN     , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_PTAG_IN_USE_LEN );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_OUTSTANDING_EOI     , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_EOI );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_OUTSTANDING_EOI_LEN , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_EOI_LEN );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_UNLOCK_IN_FIFO      , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_UNLOCK_IN_FIFO );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_UNLOCK_IN_FIFO_LEN  , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_UNLOCK_IN_FIFO_LEN );
+
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQD_FETCH , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_EQD_FETCH );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQD_FETCH_LEN , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_EQD_FETCH_LEN );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQP     , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_EQP );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQP_LEN , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_EQP_LEN );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING         , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_LEN     , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_LEN );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_LOAD , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_CI_LOAD );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_LOAD_LEN , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_CI_LOAD_LEN );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_STORE , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_CI_STORE );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_STORE_LEN , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_CI_STORE_LEN );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQD_WRITE , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_EQD_WRITE );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQD_WRITE_LEN , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_EQD_WRITE_LEN );
+
+REG64_FLD( PU_INT_VC_EQC_CACHE_EN_ENABLE                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE     );
+REG64_FLD( PU_INT_VC_EQC_CACHE_EN_ENABLE_LEN                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE_LEN );
+
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA0_DATA                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DATA       );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA0_DATA_LEN                , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA1_DATA                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DATA       );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA1_DATA_LEN                , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA2_DATA                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DATA       );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA2_DATA_LEN                , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA3_DATA                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DATA       );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA3_DATA_LEN                , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_CONFLICT                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CONFLICT   );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_1_7             , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_1_7 );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_1_7_LEN         , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_1_7_LEN );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_FULL                     , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FULL       );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_9_27            , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_9_27 );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_9_27_LEN        , 19  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_9_27_LEN );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_BLOCKID                  , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_BLOCKID_LEN              , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_32_39           , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_32_39 );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_32_39_LEN       , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_32_39_LEN );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_OFFSET                   , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_OFFSET_LEN               , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OFFSET_LEN );
+
+REG64_FLD( PU_INT_VC_EQC_CONFIG_PAGE_OFFSET_CFG                    , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PAGE_OFFSET_CFG );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_PAGE_OFFSET_CFG_LEN                , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PAGE_OFFSET_CFG_LEN );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_SYNC_DONE                          , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SYNC_DONE  );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_SYNC_DONE_LEN                      , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SYNC_DONE_LEN );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_RESERVED_37_51                     , 37  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_37_51 );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_RESERVED_37_51_LEN                 , 15  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_37_51_LEN );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_BG_SCAN_RATE                       , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BG_SCAN_RATE );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_BG_SCAN_RATE_LEN                   , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BG_SCAN_RATE_LEN );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_RESERVED_56_58                     , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_56_58 );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_RESERVED_56_58_LEN                 , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_56_58_LEN );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_MAX_ENTRIES_IN_MODIFIED            , 59  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MAX_ENTRIES_IN_MODIFIED );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_MAX_ENTRIES_IN_MODIFIED_LEN        , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MAX_ENTRIES_IN_MODIFIED_LEN );
+
+REG64_FLD( PU_INT_VC_EQC_DEBUG_RESERVED_0_32                       , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_0_32 );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_RESERVED_0_32_LEN                   , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_0_32_LEN );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_ARX_ECC_CORRECTION              , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_ARX_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_TAG_ECC_CORRECTION              , 34  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_TAG_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_TAG_ECC_CORRECTION_LEN          , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_TAG_ECC_CORRECTION_LEN );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_STATE_ECC_CORRECTION            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_STATE_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_STATE_ECC_CORRECTION_LEN        , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_STATE_ECC_CORRECTION_LEN );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_CTRLBUF_ECC_CORRECTION          , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_CTRLBUF_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_DATA_ECC_CORRECTION             , 45  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_DATA_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_DATA_ECC_CORRECTION_LEN         , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_DATA_ECC_CORRECTION_LEN );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_FORCE_SINGLE_BIT_ECC_ERR            , 49  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FORCE_SINGLE_BIT_ECC_ERR );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR            , 50  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FORCE_DOUBLE_BIT_ECC_ERR );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_ECC_ERR_INJ_ARRAY_SEL               , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ECC_ERR_INJ_ARRAY_SEL );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_ECC_ERR_INJ_ARRAY_SEL_LEN           , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ECC_ERR_INJ_ARRAY_SEL_LEN );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_TRACE_ENABLE                        , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_TRACE_ENABLE );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_RESERVED_57_58                      , 57  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_57_58 );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_RESERVED_57_58_LEN                  , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_57_58_LEN );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_RESERVED_59                         , 59  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_59 );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_USE_WATCH_TO_READ_CTRL_ARY          , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_USE_WATCH_TO_READ_CTRL_ARY );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_CACHE_CTRL_ARY_SELECT               , 61  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CACHE_CTRL_ARY_SELECT );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_CACHE_CTRL_ARY_SELECT_LEN           , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CACHE_CTRL_ARY_SELECT_LEN );
+
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_IPI  , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQ_TRIGGER_FROM_IPI );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_IPI_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQ_TRIGGER_FROM_IPI_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_HWD  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQ_TRIGGER_FROM_HWD );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_HWD_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQ_TRIGGER_FROM_HWD_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_1ESC , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQ_TRIGGER_FROM_1ESC );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_1ESC_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQ_TRIGGER_FROM_1ESC_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_2ESC , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQ_TRIGGER_FROM_2ESC );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_2ESC_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQ_TRIGGER_FROM_2ESC_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_REDIS , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQ_TRIGGER_FROM_REDIS );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_REDIS_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQ_TRIGGER_FROM_REDIS_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI         , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_NON_SPEC_EOI );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_LEN     , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_NON_SPEC_EOI_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_LOCAL_ESCALATE       , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_LOCAL_ESCALATE );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_LOCAL_ESCALATE_LEN   , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_LOCAL_ESCALATE_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIG_CACHE_HIT    , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQ_TRIG_CACHE_HIT );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIG_CACHE_HIT_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQ_TRIG_CACHE_HIT_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EOI_CACHE_HIT        , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EOI_CACHE_HIT );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EOI_CACHE_HIT_LEN    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EOI_CACHE_HIT_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_LOCAL_ESC_CACHE_HIT  , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_LOCAL_ESC_CACHE_HIT );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_LOCAL_ESC_CACHE_HIT_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_LOCAL_ESC_CACHE_HIT_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU        , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_VICTIM_IS_LRU );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU_LEN    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_VICTIM_IS_LRU_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_FIRST_USABLE , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_VICTIM_IS_FIRST_USABLE );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_FIRST_USABLE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_VICTIM_IS_FIRST_USABLE_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_RETRY                , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_RETRY  );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_RETRY_LEN            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_RETRY_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES     , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TOO_MANY_ENTRIES );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TOO_MANY_ENTRIES_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_RESERVED_56_63           , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_56_63 );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_RESERVED_56_63_LEN       , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_56_63_LEN );
+
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQD_FETCH            , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQD_FETCH );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQD_FETCH_LEN        , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQD_FETCH_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQP                  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQP    );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQP_LEN              , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQP_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_WAKEUP               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_WAKEUP );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_WAKEUP_LEN           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_WAKEUP_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LS                   , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_LS     );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LS_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_LS_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_VP                   , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_VP     );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_VP_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_VP_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_GROUP                , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_GROUP  );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_GROUP_LEN            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_GROUP_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_BROADCAST            , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_BROADCAST );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_BROADCAST_LEN        , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_BROADCAST_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQ_FWD               , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQ_FWD );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQ_FWD_LEN           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQ_FWD_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_ESCALATE             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_ESCALATE );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_ESCALATE_LEN         , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_ESCALATE_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LOCAL_VPC_UPD        , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_LOCAL_VPC_UPD );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LOCAL_VPC_UPD_LEN    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_LOCAL_VPC_UPD_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_REMOTE_VPC_UPD       , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_REMOTE_VPC_UPD );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_REMOTE_VPC_UPD_LEN   , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_REMOTE_VPC_UPD_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LOCAL_SBC_UPD        , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_LOCAL_SBC_UPD );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LOCAL_SBC_UPD_LEN    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_LOCAL_SBC_UPD_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_REMOTE_SBC_UPD       , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_REMOTE_SBC_UPD );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_REMOTE_SBC_UPD_LEN   , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_REMOTE_SBC_UPD_LEN );
+
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EQD_FETCH_REPLAY     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQD_FETCH_REPLAY );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EQD_FETCH_REPLAY_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQD_FETCH_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EQP_REPLAY           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQP_REPLAY );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EQP_REPLAY_LEN       , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQP_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_REPLAY               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_REPLAY );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_REPLAY_LEN           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_CI_STORE_REPLAY      , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_CI_STORE_REPLAY );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_CI_STORE_REPLAY_LEN  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_CI_STORE_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_ESC_REPLAY     , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_LOCAL_ESC_REPLAY );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_ESC_REPLAY_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_LOCAL_ESC_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_REMOTE_CI_LOAD_REPLAY , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_REMOTE_CI_LOAD_REPLAY );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_REMOTE_CI_LOAD_REPLAY_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_REMOTE_CI_LOAD_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_VPC_REPLAY     , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_LOCAL_VPC_REPLAY );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_VPC_REPLAY_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_LOCAL_VPC_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_SBC_REPLAY     , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_LOCAL_SBC_REPLAY );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_SBC_REPLAY_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_LOCAL_SBC_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EOI_RESP_REPLAY      , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EOI_RESP_REPLAY );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EOI_RESP_REPLAY_LEN  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EOI_RESP_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_NEW_CMD_STALLED      , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_NEW_CMD_STALLED );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_NEW_CMD_STALLED_LEN  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_NEW_CMD_STALLED_LEN );
+
+REG64_FLD( PU_INT_VC_EQC_SCRUB_MASK_BLOCKID                        , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_MASK_BLOCKID_LEN                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_MASK_RESERVED_32_39                 , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32_39 );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_MASK_RESERVED_32_39_LEN             , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32_39_LEN );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_MASK_OFFSET                         , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_MASK_OFFSET_LEN                     , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_OFFSET_LEN );
+
+REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_VALID                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VALID      );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_WANT_CACHE_DISABLE             , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WANT_CACHE_DISABLE );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_WANT_INVALIDATE                , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WANT_INVALIDATE );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_BLOCKID                        , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_BLOCKID_LEN                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_RESERVED_32_39                 , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32_39 );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_RESERVED_32_39_LEN             , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32_39_LEN );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_OFFSET                         , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_OFFSET_LEN                     , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_OFFSET_LEN );
+
+REG64_FLD( PU_INT_VC_EQD_BLOCK_MODE_MODE                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MODE       );
+REG64_FLD( PU_INT_VC_EQD_BLOCK_MODE_MODE_LEN                       , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MODE_LEN   );
+
+REG64_FLD( PU_INT_VC_ERR_CFG_G0R0_ERROR_CONFIG                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ERROR_CONFIG );
+REG64_FLD( PU_INT_VC_ERR_CFG_G0R0_ERROR_CONFIG_LEN                 , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ERROR_CONFIG_LEN );
+
+REG64_FLD( PU_INT_VC_ERR_CFG_G0R1_ERROR_CONFIG                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ERROR_CONFIG );
+REG64_FLD( PU_INT_VC_ERR_CFG_G0R1_ERROR_CONFIG_LEN                 , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ERROR_CONFIG_LEN );
+
+REG64_FLD( PU_INT_VC_ERR_CFG_G1R0_ERROR_CONFIG                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ERROR_CONFIG );
+REG64_FLD( PU_INT_VC_ERR_CFG_G1R0_ERROR_CONFIG_LEN                 , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ERROR_CONFIG_LEN );
+
+REG64_FLD( PU_INT_VC_ERR_CFG_G1R1_ERROR_CONFIG                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ERROR_CONFIG );
+REG64_FLD( PU_INT_VC_ERR_CFG_G1R1_ERROR_CONFIG_LEN                 , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ERROR_CONFIG_LEN );
+
+REG64_FLD( PU_INT_VC_FATAL_ERR_G0_ERROR                            , 0   ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR      );
+REG64_FLD( PU_INT_VC_FATAL_ERR_G0_ERROR_LEN                        , 55  ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_VC_FATAL_ERR_G1_ERROR                            , 0   ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR      );
+REG64_FLD( PU_INT_VC_FATAL_ERR_G1_ERROR_LEN                        , 43  ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_VC_GLOBAL_CONFIG_INDIRECT_MODE                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_INDIRECT_MODE );
+REG64_FLD( PU_INT_VC_GLOBAL_CONFIG_RESERVED_33_63                  , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_33_63 );
+REG64_FLD( PU_INT_VC_GLOBAL_CONFIG_RESERVED_33_63_LEN              , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_33_63_LEN );
+
+REG64_FLD( PU_INT_VC_INFO_ERR_G0_ERROR                             , 0   ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR      );
+REG64_FLD( PU_INT_VC_INFO_ERR_G0_ERROR_LEN                         , 55  ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_VC_INFO_ERR_G1_ERROR                             , 0   ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR      );
+REG64_FLD( PU_INT_VC_INFO_ERR_G1_ERROR_LEN                         , 43  ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_20                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_20 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_20_LEN                  , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_20_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_PREFETCH_DISTANCE                , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PREFETCH_DISTANCE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_PREFETCH_DISTANCE_LEN            , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PREFETCH_DISTANCE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_MAX_CRD_TO_CQ                    , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_CQ );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_MAX_CRD_TO_CQ_LEN                , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_CQ_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_32_34                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_32_34 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_32_34_LEN               , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_32_34_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_MAX_CRD_TO_PC                    , 35  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_PC );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_MAX_CRD_TO_PC_LEN                , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_PC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_40_41                   , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_40_41 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_40_41_LEN               , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_40_41_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_PREFETCH_DISABLE                 , 42  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PREFETCH_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_QUEUE_DISABLE                    , 43  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_QUEUE_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_IVC_INTF_DISABLE                 , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IVC_INTF_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_ENABLE_MEMORY_BACKING            , 45  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE_MEMORY_BACKING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_MEM_SIZE                         , 46  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MEM_SIZE   );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_MEM_SIZE_LEN                     , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MEM_SIZE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_52                      , 52  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_52 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_NB_WRITE_SLOT                    , 53  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_WRITE_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_NB_WRITE_SLOT_LEN                , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_WRITE_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_56                      , 56  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_56 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_NB_CLEAN_SLOT                    , 57  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_CLEAN_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_NB_CLEAN_SLOT_LEN                , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_CLEAN_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_FULL_WRITEBACK_ENABLE            , 60  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FULL_WRITEBACK_ENABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_QUEUE_NOT_EMPTY                  , 61  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_QUEUE_NOT_EMPTY );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_CREDIT_UPDATE_PENDING            , 62  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CREDIT_UPDATE_PENDING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_FIFO_FULL                        , 63  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_FULL  );
+
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_0_20                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_0_20 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_0_20_LEN                , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_0_20_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_PREFETCH_DISTANCE                , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PREFETCH_DISTANCE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_PREFETCH_DISTANCE_LEN            , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PREFETCH_DISTANCE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_MAX_CRD_TO_CQ                    , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_CQ );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_MAX_CRD_TO_CQ_LEN                , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_CQ_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_32_34                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_32_34 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_32_34_LEN               , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_32_34_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_MAX_CRD_TO_PC                    , 35  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_PC );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_MAX_CRD_TO_PC_LEN                , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_PC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_40_41                   , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_40_41 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_40_41_LEN               , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_40_41_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_PREFETCH_DISABLE                 , 42  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PREFETCH_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_QUEUE_DISABLE                    , 43  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_QUEUE_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_IVC_INTF_DISABLE                 , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IVC_INTF_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_ENABLE_MEMORY_BACKING            , 45  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE_MEMORY_BACKING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_MEM_SIZE                         , 46  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MEM_SIZE   );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_MEM_SIZE_LEN                     , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MEM_SIZE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_52                      , 52  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_52 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_NB_WRITE_SLOT                    , 53  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_WRITE_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_NB_WRITE_SLOT_LEN                , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_WRITE_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_56                      , 56  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_56 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_NB_CLEAN_SLOT                    , 57  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_CLEAN_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_NB_CLEAN_SLOT_LEN                , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_CLEAN_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_FULL_WRITEBACK_ENABLE            , 60  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FULL_WRITEBACK_ENABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_QUEUE_NOT_EMPTY                  , 61  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_QUEUE_NOT_EMPTY );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_CREDIT_UPDATE_PENDING            , 62  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CREDIT_UPDATE_PENDING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_FIFO_FULL                        , 63  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_FULL  );
+
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_0_20                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_0_20 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_0_20_LEN                , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_0_20_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_PREFETCH_DISTANCE                , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PREFETCH_DISTANCE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_PREFETCH_DISTANCE_LEN            , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PREFETCH_DISTANCE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_MAX_CRD_TO_CQ                    , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_CQ );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_MAX_CRD_TO_CQ_LEN                , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_CQ_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_32_34                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_32_34 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_32_34_LEN               , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_32_34_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_MAX_CRD_TO_PC                    , 35  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_PC );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_MAX_CRD_TO_PC_LEN                , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_PC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_40_41                   , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_40_41 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_40_41_LEN               , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_40_41_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_PREFETCH_DISABLE                 , 42  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PREFETCH_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_QUEUE_DISABLE                    , 43  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_QUEUE_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_IVC_INTF_DISABLE                 , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IVC_INTF_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_ENABLE_MEMORY_BACKING            , 45  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE_MEMORY_BACKING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_MEM_SIZE                         , 46  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MEM_SIZE   );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_MEM_SIZE_LEN                     , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MEM_SIZE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_52                      , 52  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_52 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_NB_WRITE_SLOT                    , 53  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_WRITE_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_NB_WRITE_SLOT_LEN                , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_WRITE_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_56                      , 56  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_56 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_NB_CLEAN_SLOT                    , 57  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_CLEAN_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_NB_CLEAN_SLOT_LEN                , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_CLEAN_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_FULL_WRITEBACK_ENABLE            , 60  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FULL_WRITEBACK_ENABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_QUEUE_NOT_EMPTY                  , 61  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_QUEUE_NOT_EMPTY );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_CREDIT_UPDATE_PENDING            , 62  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CREDIT_UPDATE_PENDING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_FIFO_FULL                        , 63  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_FULL  );
+
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_0_20                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_0_20 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_0_20_LEN                , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_0_20_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_PREFETCH_DISTANCE                , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PREFETCH_DISTANCE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_PREFETCH_DISTANCE_LEN            , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PREFETCH_DISTANCE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_MAX_CRD_TO_CQ                    , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_CQ );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_MAX_CRD_TO_CQ_LEN                , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_CQ_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_32_34                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_32_34 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_32_34_LEN               , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_32_34_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_MAX_CRD_TO_PC                    , 35  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_PC );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_MAX_CRD_TO_PC_LEN                , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_PC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_40_41                   , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_40_41 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_40_41_LEN               , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_40_41_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_PREFETCH_DISABLE                 , 42  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PREFETCH_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_QUEUE_DISABLE                    , 43  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_QUEUE_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_IVC_INTF_DISABLE                 , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IVC_INTF_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_ENABLE_MEMORY_BACKING            , 45  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE_MEMORY_BACKING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_MEM_SIZE                         , 46  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MEM_SIZE   );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_MEM_SIZE_LEN                     , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MEM_SIZE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_52                      , 52  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_52 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_NB_WRITE_SLOT                    , 53  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_WRITE_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_NB_WRITE_SLOT_LEN                , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_WRITE_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_56                      , 56  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_56 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_NB_CLEAN_SLOT                    , 57  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_CLEAN_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_NB_CLEAN_SLOT_LEN                , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_CLEAN_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_FULL_WRITEBACK_ENABLE            , 60  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FULL_WRITEBACK_ENABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_QUEUE_NOT_EMPTY                  , 61  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_QUEUE_NOT_EMPTY );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_CREDIT_UPDATE_PENDING            , 62  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CREDIT_UPDATE_PENDING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_FIFO_FULL                        , 63  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_FULL  );
+
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_0_20                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_0_20 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_0_20_LEN                , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_0_20_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_PREFETCH_DISTANCE                , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PREFETCH_DISTANCE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_PREFETCH_DISTANCE_LEN            , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PREFETCH_DISTANCE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_MAX_CRD_TO_CQ                    , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_CQ );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_MAX_CRD_TO_CQ_LEN                , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_CQ_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_32_34                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_32_34 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_32_34_LEN               , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_32_34_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_MAX_CRD_TO_PC                    , 35  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_PC );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_MAX_CRD_TO_PC_LEN                , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_PC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_40_41                   , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_40_41 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_40_41_LEN               , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_40_41_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_PREFETCH_DISABLE                 , 42  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PREFETCH_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_QUEUE_DISABLE                    , 43  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_QUEUE_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_IVC_INTF_DISABLE                 , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IVC_INTF_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_ENABLE_MEMORY_BACKING            , 45  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE_MEMORY_BACKING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_MEM_SIZE                         , 46  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MEM_SIZE   );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_MEM_SIZE_LEN                     , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MEM_SIZE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_52                      , 52  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_52 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_NB_WRITE_SLOT                    , 53  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_WRITE_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_NB_WRITE_SLOT_LEN                , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_WRITE_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_56                      , 56  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_56 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_NB_CLEAN_SLOT                    , 57  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_CLEAN_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_NB_CLEAN_SLOT_LEN                , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_CLEAN_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_FULL_WRITEBACK_ENABLE            , 60  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FULL_WRITEBACK_ENABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_QUEUE_NOT_EMPTY                  , 61  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_QUEUE_NOT_EMPTY );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_CREDIT_UPDATE_PENDING            , 62  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CREDIT_UPDATE_PENDING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_FIFO_FULL                        , 63  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_FULL  );
+
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_0_20                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_0_20 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_0_20_LEN                , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_0_20_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_PREFETCH_DISTANCE                , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PREFETCH_DISTANCE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_PREFETCH_DISTANCE_LEN            , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PREFETCH_DISTANCE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_MAX_CRD_TO_CQ                    , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_CQ );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_MAX_CRD_TO_CQ_LEN                , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_CQ_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_32_34                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_32_34 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_32_34_LEN               , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_32_34_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_MAX_CRD_TO_PC                    , 35  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_PC );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_MAX_CRD_TO_PC_LEN                , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAX_CRD_TO_PC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_40_41                   , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_40_41 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_40_41_LEN               , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_40_41_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_PREFETCH_DISABLE                 , 42  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PREFETCH_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_QUEUE_DISABLE                    , 43  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_QUEUE_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_IVC_INTF_DISABLE                 , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IVC_INTF_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_ENABLE_MEMORY_BACKING            , 45  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE_MEMORY_BACKING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_MEM_SIZE                         , 46  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MEM_SIZE   );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_MEM_SIZE_LEN                     , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MEM_SIZE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_52                      , 52  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_52 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_NB_WRITE_SLOT                    , 53  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_WRITE_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_NB_WRITE_SLOT_LEN                , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_WRITE_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_56                      , 56  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_56 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_NB_CLEAN_SLOT                    , 57  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_CLEAN_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_NB_CLEAN_SLOT_LEN                , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NB_CLEAN_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_FULL_WRITEBACK_ENABLE            , 60  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FULL_WRITEBACK_ENABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_QUEUE_NOT_EMPTY                  , 61  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_QUEUE_NOT_EMPTY );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_CREDIT_UPDATE_PENDING            , 62  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CREDIT_UPDATE_PENDING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_FIFO_FULL                        , 63  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_FULL  );
+
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_FROM_AIB        , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FROM_AIB );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_FROM_AIB_LEN    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FROM_AIB_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_DROPPED         , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_DROPPED );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_DROPPED_LEN     , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_DROPPED_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_FWD_TO_EQC      , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FWD_TO_EQC );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_FWD_TO_EQC_LEN  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_DMA_WR               , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_WR );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_DMA_WR_LEN           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_WR_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_DMA_RD               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_RD );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_DMA_RD_LEN           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_RD_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_FIFO_FULL            , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_FIFO_FULL );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_FIFO_FULL_LEN        , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_FIFO_FULL_LEN );
+
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_FROM_AIB        , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FROM_AIB );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_FROM_AIB_LEN    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FROM_AIB_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_DROPPED         , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_DROPPED );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_DROPPED_LEN     , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_DROPPED_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_FWD_TO_EQC      , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FWD_TO_EQC );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_FWD_TO_EQC_LEN  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_DMA_WR               , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_WR );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_DMA_WR_LEN           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_WR_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_DMA_RD               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_RD );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_DMA_RD_LEN           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_RD_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_FIFO_FULL            , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_FIFO_FULL );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_FIFO_FULL_LEN        , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_FIFO_FULL_LEN );
+
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_FROM_AIB        , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FROM_AIB );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_FROM_AIB_LEN    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FROM_AIB_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_DROPPED         , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_DROPPED );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_DROPPED_LEN     , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_DROPPED_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_FWD_TO_EQC      , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FWD_TO_EQC );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_FWD_TO_EQC_LEN  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_DMA_WR               , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_WR );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_DMA_WR_LEN           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_WR_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_DMA_RD               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_RD );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_DMA_RD_LEN           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_RD_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_FIFO_FULL            , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_FIFO_FULL );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_FIFO_FULL_LEN        , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_FIFO_FULL_LEN );
+
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_FROM_AIB        , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FROM_AIB );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_FROM_AIB_LEN    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FROM_AIB_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_DROPPED         , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_DROPPED );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_DROPPED_LEN     , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_DROPPED_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_FWD_TO_EQC      , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FWD_TO_EQC );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_FWD_TO_EQC_LEN  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_DMA_WR               , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_WR );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_DMA_WR_LEN           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_WR_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_DMA_RD               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_RD );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_DMA_RD_LEN           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_RD_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_FIFO_FULL            , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_FIFO_FULL );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_FIFO_FULL_LEN        , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_FIFO_FULL_LEN );
+
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_FROM_AIB        , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FROM_AIB );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_FROM_AIB_LEN    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FROM_AIB_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_DROPPED         , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_DROPPED );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_DROPPED_LEN     , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_DROPPED_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_FWD_TO_EQC      , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FWD_TO_EQC );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_FWD_TO_EQC_LEN  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_DMA_WR               , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_WR );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_DMA_WR_LEN           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_WR_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_DMA_RD               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_RD );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_DMA_RD_LEN           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_RD_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_FIFO_FULL            , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_FIFO_FULL );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_FIFO_FULL_LEN        , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_FIFO_FULL_LEN );
+
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_FROM_AIB        , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FROM_AIB );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_FROM_AIB_LEN    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FROM_AIB_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_DROPPED         , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_DROPPED );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_DROPPED_LEN     , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_DROPPED_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_FWD_TO_EQC      , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FWD_TO_EQC );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_FWD_TO_EQC_LEN  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_DMA_WR               , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_WR );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_DMA_WR_LEN           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_WR_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_DMA_RD               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_RD );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_DMA_RD_LEN           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DMA_RD_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_FIFO_FULL            , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_FIFO_FULL );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_FIFO_FULL_LEN        , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_FIFO_FULL_LEN );
+
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_IPI_PRIORITY               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_IPI_PRIORITY );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_IPI_PRIORITY_LEN           , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_IPI_PRIORITY_LEN );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_IPI_RSD                    , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_IPI_RSD    );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_IPI_RSD_LEN                , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_IPI_RSD_LEN );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_HWD_PRIORITY               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_PRIORITY );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_HWD_PRIORITY_LEN           , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_PRIORITY_LEN );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_HWD_RSD                    , 11  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_RSD    );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_HWD_RSD_LEN                , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_RSD_LEN );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC1_PRIORITY              , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ESC1_PRIORITY );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC1_PRIORITY_LEN          , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ESC1_PRIORITY_LEN );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC1_RSD                   , 19  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ESC1_RSD   );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC1_RSD_LEN               , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ESC1_RSD_LEN );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC2_PRIORITY              , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ESC2_PRIORITY );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC2_PRIORITY_LEN          , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ESC2_PRIORITY_LEN );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC2_RSD                   , 27  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ESC2_RSD   );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC2_RSD_LEN               , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ESC2_RSD_LEN );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_REDIS_PRIORITY             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_REDIS_PRIORITY );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_REDIS_PRIORITY_LEN         , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_REDIS_PRIORITY_LEN );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_REDIS_RSD                  , 35  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_REDIS_RSD  );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_REDIS_RSD_LEN              , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_REDIS_RSD_LEN );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_RESERVED_40_42             , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_40_42 );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_RESERVED_40_42_LEN         , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_40_42_LEN );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_POOL                       , 43  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_POOL       );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_POOL_LEN                   , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_POOL_LEN   );
+
+REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_P0_IS_IDLE                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_P0_IS_IDLE );
+REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_P1_IS_IDLE                , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_P1_IS_IDLE );
+REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_PTAG_IN_USE           , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_PTAG_IN_USE );
+REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_PTAG_IN_USE_LEN       , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_PTAG_IN_USE_LEN );
+REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_UNLOCK_IN_FIFO        , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_UNLOCK_IN_FIFO );
+REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_UNLOCK_IN_FIFO_LEN    , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_UNLOCK_IN_FIFO_LEN );
+REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_OUTSTANDING_IVE_FETCH , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_IVE_FETCH );
+REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_OUTSTANDING_IVE_FETCH_LEN , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_IVE_FETCH_LEN );
+REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_OUTSTANDING_SBC_LOOKUP , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_SBC_LOOKUP );
+REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_OUTSTANDING_SBC_LOOKUP_LEN , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_SBC_LOOKUP_LEN );
+
+REG64_FLD( PU_INT_VC_IVC_CACHE_EN_ENABLE                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE     );
+REG64_FLD( PU_INT_VC_IVC_CACHE_EN_ENABLE_LEN                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE_LEN );
+
+REG64_FLD( PU_INT_VC_IVC_CACHE_WATCH_ADDR_SET_INDEX                , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SET_INDEX  );
+REG64_FLD( PU_INT_VC_IVC_CACHE_WATCH_ADDR_SET_INDEX_LEN            , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SET_INDEX_LEN );
+
+REG64_FLD( PU_INT_VC_IVC_CACHE_WATCH_DATA_DATA                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_INT_VC_IVC_CACHE_WATCH_DATA_DATA_LEN                 , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_32_33                      , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32_33 );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_32_33_LEN                  , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32_33_LEN );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_DIS_TAG_ECC_CORRECTION              , 34  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_TAG_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_DIS_TAG_ECC_CORRECTION_LEN          , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_TAG_ECC_CORRECTION_LEN );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_38_41                      , 38  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_38_41 );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_38_41_LEN                  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_38_41_LEN );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_DIS_STATE_ECC_CORRECTION            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_STATE_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_43_44                      , 43  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_43_44 );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_43_44_LEN                  , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_43_44_LEN );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_DIS_DATA_ECC_CORRECTION             , 45  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_DATA_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_DIS_DATA_ECC_CORRECTION_LEN         , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_DATA_ECC_CORRECTION_LEN );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_47_48                      , 47  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_47_48 );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_47_48_LEN                  , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_47_48_LEN );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_FORCE_SINGLE_BIT_ECC_ERR            , 49  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FORCE_SINGLE_BIT_ECC_ERR );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR            , 50  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FORCE_DOUBLE_BIT_ECC_ERR );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_ECC_ERR_INJ_ARRAY_SEL               , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ECC_ERR_INJ_ARRAY_SEL );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_ECC_ERR_INJ_ARRAY_SEL_LEN           , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ECC_ERR_INJ_ARRAY_SEL_LEN );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_TRACE_ENABLE                        , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_TRACE_ENABLE );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_57_59                      , 57  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_57_59 );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_57_59_LEN                  , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_57_59_LEN );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_CACHE_CTRL_ARY_SELECT               , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CACHE_CTRL_ARY_SELECT );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_CACHE_CTRL_ARY_SELECT_LEN           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CACHE_CTRL_ARY_SELECT_LEN );
+
+REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_0                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_0 );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_0                              , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_0      );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_0_LEN                          , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_0_LEN  );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_8                         , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_8 );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD                                , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD        );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_LEN                            , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_LEN    );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_16                        , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_16 );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_2                              , 17  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_2      );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_2_LEN                          , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_2_LEN  );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_24                        , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_24 );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_3                              , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_3      );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_3_LEN                          , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_3_LEN  );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_32                        , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32 );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_4                              , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_4      );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_4_LEN                          , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_4_LEN  );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_40                        , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_40 );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_5                              , 41  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_5      );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_5_LEN                          , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_5_LEN  );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_48                        , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_48 );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_6                              , 49  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_6      );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_6_LEN                          , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_6_LEN  );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_56                        , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_56 );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_7                              , 57  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_7      );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_7_LEN                          , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_7_LEN  );
+
+REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_0                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_0 );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_8                              , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_8      );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_8_LEN                          , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_8_LEN  );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_8                         , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_8 );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_9                              , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_9      );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_9_LEN                          , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_9_LEN  );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_16                        , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_16 );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_10                             , 17  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_10     );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_10_LEN                         , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_10_LEN );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_24                        , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_24 );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_11                             , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_11     );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_11_LEN                         , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_11_LEN );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_32                        , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32 );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_12                             , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_12     );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_12_LEN                         , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_12_LEN );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_40                        , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_40 );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_13                             , 41  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_13     );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_13_LEN                         , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_13_LEN );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_48                        , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_48 );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_14                             , 49  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_14     );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_14_LEN                         , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_14_LEN );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_56                        , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_56 );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_15                             , 57  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_15     );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_15_LEN                         , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HWD_15_LEN );
+
+REG64_FLD( PU_INT_VC_IVC_HASH_3_RESERVED_0                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_0 );
+REG64_FLD( PU_INT_VC_IVC_HASH_3_IPI                                , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_IPI        );
+REG64_FLD( PU_INT_VC_IVC_HASH_3_IPI_LEN                            , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_IPI_LEN    );
+
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_PRF_IVE     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_IPI_DOES_PRF_IVE );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_PRF_IVE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_IPI_DOES_PRF_IVE_LEN );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_PRF_IVE_SBC , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_IPI_DOES_PRF_IVE_SBC );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_PRF_IVE_SBC_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_IPI_DOES_PRF_IVE_SBC_LEN );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_HWD_DOES_PRF_IVE     , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_HWD_DOES_PRF_IVE );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_HWD_DOES_PRF_IVE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_HWD_DOES_PRF_IVE_LEN );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_DEM_IVE     , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_IPI_DOES_DEM_IVE );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_DEM_IVE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_IPI_DOES_DEM_IVE_LEN );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_DEM_IVE_SBC , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_IPI_DOES_DEM_IVE_SBC );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_DEM_IVE_SBC_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_IPI_DOES_DEM_IVE_SBC_LEN );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CND_HWD_DOES_DEM_IVE     , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CND_HWD_DOES_DEM_IVE );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CND_HWD_DOES_DEM_IVE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CND_HWD_DOES_DEM_IVE_LEN );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_PRF_CACHE_HIT        , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_PRF_CACHE_HIT );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_PRF_CACHE_HIT_LEN    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_PRF_CACHE_HIT_LEN );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_DEM_CACHE_HIT        , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DEM_CACHE_HIT );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_DEM_CACHE_HIT_LEN    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_DEM_CACHE_HIT_LEN );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU        , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_VICTIM_IS_LRU );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU_LEN    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_VICTIM_IS_LRU_LEN );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_1ST_USABLE , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_VICTIM_IS_1ST_USABLE );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_1ST_USABLE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_VICTIM_IS_1ST_USABLE_LEN );
+
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_2_CNT_IVE_FETCH            , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_IVE_FETCH );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_2_CNT_IVE_FETCH_LEN        , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_IVE_FETCH_LEN );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_2_CNT_SBC_LOOKUP           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_SBC_LOOKUP );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_2_CNT_SBC_LOOKUP_LEN       , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_SBC_LOOKUP_LEN );
+
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_3_CNT_IVE_FETCH_REPLAY     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_IVE_FETCH_REPLAY );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_3_CNT_IVE_FETCH_REPLAY_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_IVE_FETCH_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_3_CNT_SBC_LOOKUP_REPLAY    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_SBC_LOOKUP_REPLAY );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_3_CNT_SBC_LOOKUP_REPLAY_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_SBC_LOOKUP_REPLAY_LEN );
+
+REG64_FLD( PU_INT_VC_IVC_SCRUB_MASK_BLOCKID                        , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_MASK_BLOCKID_LEN                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_MASK_RESERVED_32_35                 , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32_35 );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_MASK_RESERVED_32_35_LEN             , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32_35_LEN );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_MASK_OFFSET                         , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_MASK_OFFSET_LEN                     , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_OFFSET_LEN );
+
+REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_VALID                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VALID      );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_WANT_CACHE_DISABLE             , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WANT_CACHE_DISABLE );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_BLOCKID                        , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_BLOCKID_LEN                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_RESERVED_32_35                 , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32_35 );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_RESERVED_32_35_LEN             , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32_35_LEN );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_OFFSET                         , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_OFFSET_LEN                     , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_OFFSET_LEN );
+
+REG64_FLD( PU_INT_VC_IVE_ISB_BLOCK_MODE_MODE                       , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MODE       );
+REG64_FLD( PU_INT_VC_IVE_ISB_BLOCK_MODE_MODE_LEN                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MODE_LEN   );
+
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_DIS_AIB_IN_ECC_CORRECTION          , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_AIB_IN_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_DIS_IRQ_ECC_CORRECTION             , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_IRQ_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_DIS_AT_SRAM_ECC_CORRECTION         , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_AT_SRAM_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_DIS_BAR_SRAM_ECC_CORRECTION        , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_BAR_SRAM_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_DIS_TAG_SRAM_ECC_CORRECTION        , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_TAG_SRAM_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_IRQ_TRACE_ENABLE                   , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_IRQ_TRACE_ENABLE );
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_FORCE_SINGLE_BIT_ECC_ERR           , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FORCE_SINGLE_BIT_ECC_ERR );
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR           , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FORCE_DOUBLE_BIT_ECC_ERR );
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_RESERVED_8_9                       , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_8_9 );
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_RESERVED_8_9_LEN                   , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_8_9_LEN );
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_ECC_ERR_INJ_SELECTION              , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ECC_ERR_INJ_SELECTION );
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_ECC_ERR_INJ_SELECTION_LEN          , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ECC_ERR_INJ_SELECTION_LEN );
+
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_0_17    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_0_17 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_0_17_LEN , 18  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_0_17_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_CI_STORE         , 18  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CI_STORE   );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_CI_STORE_LEN     , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CI_STORE_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_24_25   , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_24_25 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_24_25_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_24_25_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_REQUEST          , 26  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_REQUEST    );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_REQUEST_LEN      , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_REQUEST_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_32_33   , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32_33 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_32_33_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32_33_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQ_POST          , 34  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EQ_POST    );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQ_POST_LEN      , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EQ_POST_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_40_41   , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_40_41 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_40_41_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_40_41_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_CI_LOAD          , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CI_LOAD    );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_CI_LOAD_LEN      , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CI_LOAD_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_48_49   , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_48_49 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_48_49_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_48_49_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQD_DMA_READ     , 50  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EQD_DMA_READ );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQD_DMA_READ_LEN , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EQD_DMA_READ_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_56_57   , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_56_57 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_56_57_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_56_57_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQD_DMA_WRITE    , 58  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EQD_DMA_WRITE );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQD_DMA_WRITE_LEN , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EQD_DMA_WRITE_LEN );
+
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_RESERVED_0_17         , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_0_17 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_RESERVED_0_17_LEN     , 18  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_0_17_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_DMA_READ              , 18  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_READ   );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_DMA_READ_LEN          , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_READ_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_RESERVED_24_25        , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_24_25 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_RESERVED_24_25_LEN    , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_24_25_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_DMA_WRITE             , 26  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_WRITE  );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_DMA_WRITE_LEN         , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_WRITE_LEN );
+
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_RESERVED_48_50        , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_48_50 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_RESERVED_48_50_LEN    , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_48_50_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_SBC_LOOKUP            , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SBC_LOOKUP );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_SBC_LOOKUP_LEN        , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SBC_LOOKUP_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_RESERVED_56_58        , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_56_58 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_RESERVED_56_58_LEN    , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_56_58_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_DMA_READ              , 59  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_READ   );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_DMA_READ_LEN          , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_READ_LEN );
+
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_RESERVED_48_50        , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_48_50 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_RESERVED_48_50_LEN    , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_48_50_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_DMA_READ              , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_READ   );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_DMA_READ_LEN          , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_READ_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_RESERVED_56_58        , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_56_58 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_RESERVED_56_58_LEN    , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_56_58_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_DMA_WRITE             , 59  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_WRITE  );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_DMA_WRITE_LEN         , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_WRITE_LEN );
+
+REG64_FLD( PU_INT_VC_RECOV_ERR_G0_ERROR                            , 0   ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR      );
+REG64_FLD( PU_INT_VC_RECOV_ERR_G0_ERROR_LEN                        , 55  ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_VC_RECOV_ERR_G1_ERROR                            , 0   ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR      );
+REG64_FLD( PU_INT_VC_RECOV_ERR_G1_ERROR_LEN                        , 43  ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_P0_IS_IDLE                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_P0_IS_IDLE );
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_P1_IS_IDLE                , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_P1_IS_IDLE );
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_PTAG_IN_USE           , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_PTAG_IN_USE );
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_PTAG_IN_USE_LEN       , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_PTAG_IN_USE_LEN );
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_SOFT_EOI  , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_SOFT_EOI );
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_SOFT_EOI_LEN , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_SOFT_EOI_LEN );
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_UNLOCK_IN_FIFO        , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_UNLOCK_IN_FIFO );
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_UNLOCK_IN_FIFO_LEN    , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_UNLOCK_IN_FIFO_LEN );
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_ISB_FETCH , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_ISB_FETCH );
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_ISB_FETCH_LEN , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_ISB_FETCH_LEN );
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_ISB_WRITE , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_ISB_WRITE );
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_ISB_WRITE_LEN , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MAX_OUTSTANDING_ISB_WRITE_LEN );
+
+REG64_FLD( PU_INT_VC_SBC_CACHE_EN_ENABLE                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE     );
+REG64_FLD( PU_INT_VC_SBC_CACHE_EN_ENABLE_LEN                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE_LEN );
+
+REG64_FLD( PU_INT_VC_SBC_CACHE_WATCH_ADDR_SET_INDEX                , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SET_INDEX  );
+REG64_FLD( PU_INT_VC_SBC_CACHE_WATCH_ADDR_SET_INDEX_LEN            , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SET_INDEX_LEN );
+
+REG64_FLD( PU_INT_VC_SBC_CACHE_WATCH_DATA_DATA                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_INT_VC_SBC_CACHE_WATCH_DATA_DATA_LEN                 , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_INT_VC_SBC_CONFIG_BG_SCAN_RATE                       , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BG_SCAN_RATE );
+REG64_FLD( PU_INT_VC_SBC_CONFIG_BG_SCAN_RATE_LEN                   , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BG_SCAN_RATE_LEN );
+REG64_FLD( PU_INT_VC_SBC_CONFIG_RESERVED_56_59                     , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_56_59 );
+REG64_FLD( PU_INT_VC_SBC_CONFIG_RESERVED_56_59_LEN                 , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_56_59_LEN );
+REG64_FLD( PU_INT_VC_SBC_CONFIG_MAX_ENTRIES_IN_MODIFIED            , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MAX_ENTRIES_IN_MODIFIED );
+REG64_FLD( PU_INT_VC_SBC_CONFIG_MAX_ENTRIES_IN_MODIFIED_LEN        , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MAX_ENTRIES_IN_MODIFIED_LEN );
+
+REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_32_33                      , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32_33 );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_32_33_LEN                  , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32_33_LEN );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_DIS_TAG_ECC_CORRECTION              , 34  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_TAG_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_DIS_TAG_ECC_CORRECTION_LEN          , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_TAG_ECC_CORRECTION_LEN );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_38_41                      , 38  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_38_41 );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_38_41_LEN                  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_38_41_LEN );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_DIS_STATE_ECC_CORRECTION            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_STATE_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_43_44                      , 43  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_43_44 );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_43_44_LEN                  , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_43_44_LEN );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_DIS_DATA_ECC_CORRECTION             , 45  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_DATA_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_DIS_DATA_ECC_CORRECTION_LEN         , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_DATA_ECC_CORRECTION_LEN );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_47_48                      , 47  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_47_48 );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_47_48_LEN                  , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_47_48_LEN );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_FORCE_SINGLE_BIT_ECC_ERR            , 49  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FORCE_SINGLE_BIT_ECC_ERR );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR            , 50  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FORCE_DOUBLE_BIT_ECC_ERR );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_ECC_ERR_INJ_ARRAY_SEL               , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ECC_ERR_INJ_ARRAY_SEL );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_ECC_ERR_INJ_ARRAY_SEL_LEN           , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ECC_ERR_INJ_ARRAY_SEL_LEN );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_TRACE_ENABLE                        , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_TRACE_ENABLE );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_57_59                      , 57  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_57_59 );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_57_59_LEN                  , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_57_59_LEN );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_CACHE_CTRL_ARY_SELECT               , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CACHE_CTRL_ARY_SELECT );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_CACHE_CTRL_ARY_SELECT_LEN           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CACHE_CTRL_ARY_SELECT_LEN );
+
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_IVC_PRF              , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_IVC_PRF );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_IVC_PRF_LEN          , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_IVC_PRF_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_IVC_DEMAND           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_IVC_DEMAND );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_IVC_DEMAND_LEN       , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_IVC_DEMAND_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_EQC_COMMAND          , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQC_COMMAND );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_EQC_COMMAND_LEN      , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EQC_COMMAND_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_OWNED   , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_NON_SPEC_EOI_OWNED );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_OWNED_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_NON_SPEC_EOI_OWNED_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_NOTOWNED , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_NON_SPEC_EOI_NOTOWNED );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_NOTOWNED_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_NON_SPEC_EOI_NOTOWNED_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_SPEC_EOI             , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_SPEC_EOI );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_SPEC_EOI_LEN         , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_SPEC_EOI_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_SPEC_EOI_CACHE_HIT   , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_SPEC_EOI_CACHE_HIT );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_SPEC_EOI_CACHE_HIT_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_SPEC_EOI_CACHE_HIT_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_PRF_CACHE_HIT        , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_PRF_CACHE_HIT );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_PRF_CACHE_HIT_LEN    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_PRF_CACHE_HIT_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_OTHER_CACHE_HIT      , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_OTHER_CACHE_HIT );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_OTHER_CACHE_HIT_LEN  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_OTHER_CACHE_HIT_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU        , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_VICTIM_IS_LRU );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU_LEN    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_VICTIM_IS_LRU_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_1ST_USABLE , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_VICTIM_IS_1ST_USABLE );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_1ST_USABLE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_VICTIM_IS_1ST_USABLE_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_RETRY                , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_RETRY  );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_RETRY_LEN            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_RETRY_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES     , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TOO_MANY_ENTRIES );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_TOO_MANY_ENTRIES_LEN );
+
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_FETCH            , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_ISB_FETCH );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_FETCH_LEN        , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_ISB_FETCH_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_IVVC_RESP            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_IVVC_RESP );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_IVVC_RESP_LEN        , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_IVVC_RESP_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_WRITE            , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_ISB_WRITE );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_WRITE_LEN        , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_ISB_WRITE_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_RESERVED_12_15           , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_RESERVED_12_15_LEN       , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_12_15_LEN );
+
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_ISB_FETCH_REPLAY     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_ISB_FETCH_REPLAY );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_ISB_FETCH_REPLAY_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_ISB_FETCH_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_IVC_RESP_REPLAY      , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_IVC_RESP_REPLAY );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_IVC_RESP_REPLAY_LEN  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_IVC_RESP_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_EOI_RESP_REPLAY      , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EOI_RESP_REPLAY );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_EOI_RESP_REPLAY_LEN  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CNT_EOI_RESP_REPLAY_LEN );
+
+REG64_FLD( PU_INT_VC_SBC_SCRUB_MASK_BLOCKID                        , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_MASK_BLOCKID_LEN                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_MASK_RESERVED_32_40                 , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32_40 );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_MASK_RESERVED_32_40_LEN             , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32_40_LEN );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_MASK_OFFSET                         , 41  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_MASK_OFFSET_LEN                     , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_OFFSET_LEN );
+
+REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_VALID                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VALID      );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_WANT_CACHE_DISABLE             , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WANT_CACHE_DISABLE );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_WANT_INVALIDATE                , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WANT_INVALIDATE );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_BLOCKID                        , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_BLOCKID_LEN                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_RESERVED_32_40                 , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32_40 );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_RESERVED_32_40_LEN             , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_32_40_LEN );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_OFFSET                         , 41  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_OFFSET_LEN                     , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_OFFSET_LEN );
+
+REG64_FLD( PU_INT_VC_VPS_BLOCK_MODE_MODE                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MODE       );
+REG64_FLD( PU_INT_VC_VPS_BLOCK_MODE_MODE_LEN                       , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MODE_LEN   );
+
+REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_AUTO_INCREMENT                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_AUTO_INCREMENT );
+REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_SELECT                         , 13  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SELECT     );
+REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_SELECT_LEN                     , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SELECT_LEN );
+REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_RESERVED_16_26                 , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_16_26 );
+REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_RESERVED_16_26_LEN             , 11  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_16_26_LEN );
+REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_ADDRESS                        , 27  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_ADDRESS_LEN                    , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_INT_VC_WOF_ERR_G0_ERROR                              , 0   ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR      );
+REG64_FLD( PU_INT_VC_WOF_ERR_G0_ERROR_LEN                          , 55  ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_VC_WOF_ERR_G0_DETAIL_ERROR                       , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ERROR      );
+REG64_FLD( PU_INT_VC_WOF_ERR_G0_DETAIL_ERROR_LEN                   , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_VC_WOF_ERR_G1_ERROR                              , 0   ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR      );
+REG64_FLD( PU_INT_VC_WOF_ERR_G1_ERROR_LEN                          , 43  ,
+           SH_UNT          , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_VC_WOF_ERR_G1_DETAIL_ERROR                       , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ERROR      );
+REG64_FLD( PU_INT_VC_WOF_ERR_G1_DETAIL_ERROR_LEN                   , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_NPU_SM1_IODA_ADDR_AUTO_INCREMENT                     , 0   ,
+           SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     , SH_FLD_AUTO_INCREMENT );
+REG64_FLD( PU_NPU_SM1_IODA_ADDR_TABLE_SELECT                       , 11  ,
+           SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     , SH_FLD_TABLE_SELECT );
+REG64_FLD( PU_NPU_SM1_IODA_ADDR_TABLE_SELECT_LEN                   , 5   ,
+           SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     , SH_FLD_TABLE_SELECT_LEN );
+REG64_FLD( PU_NPU_SM1_IODA_ADDR_TABLE_ADDRESS                      , 54  ,
+           SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     , SH_FLD_TABLE_ADDRESS );
+REG64_FLD( PU_NPU_SM1_IODA_ADDR_TABLE_ADDRESS_LEN                  , 10  ,
+           SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     , SH_FLD_TABLE_ADDRESS_LEN );
+
+REG64_FLD( PU_NPU_SM1_IODA_DAT0_TABLE_DATA                         , 0   ,
+           SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     , SH_FLD_TABLE_DATA );
+REG64_FLD( PU_NPU_SM1_IODA_DAT0_TABLE_DATA_LEN                     , 64  ,
+           SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     , SH_FLD_TABLE_DATA_LEN );
+
+REG64_FLD( PU_IO_DATA_REG_PCB_TMP                                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PCB_TMP    );
+REG64_FLD( PU_IO_DATA_REG_PCB_TMP_LEN                              , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PCB_TMP_LEN );
+
+REG64_FLD( PU_IVT_OFFSET_PAYLOAD                                   , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PAYLOAD    );
+REG64_FLD( PU_IVT_OFFSET_PAYLOAD_LEN                               , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PAYLOAD_LEN );
+
+REG64_FLD( PU_GPE6_JTG_PIB_OJCFG_JTAG_SRC_SEL                      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_JTAG_SRC_SEL );
+REG64_FLD( PU_GPE6_JTG_PIB_OJCFG_RUN_TCK                           , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_RUN_TCK    );
+REG64_FLD( PU_GPE6_JTG_PIB_OJCFG_TCK_WIDTH                         , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_TCK_WIDTH  );
+REG64_FLD( PU_GPE6_JTG_PIB_OJCFG_TCK_WIDTH_LEN                     , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_TCK_WIDTH_LEN );
+REG64_FLD( PU_GPE6_JTG_PIB_OJCFG_JTAG_TRST_B                       , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_JTAG_TRST_B );
+REG64_FLD( PU_GPE6_JTG_PIB_OJCFG_DBG_HALT                          , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_DBG_HALT   );
+
+REG64_FLD( PU_GPE6_JTG_PIB_OJIC_START_JTAG_CMD                     , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_START_JTAG_CMD );
+REG64_FLD( PU_GPE6_JTG_PIB_OJIC_DO_IR                              , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_DO_IR      );
+REG64_FLD( PU_GPE6_JTG_PIB_OJIC_DO_DR                              , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_DO_DR      );
+REG64_FLD( PU_GPE6_JTG_PIB_OJIC_DO_TAP_RESET                       , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_DO_TAP_RESET );
+REG64_FLD( PU_GPE6_JTG_PIB_OJIC_WR_VALID                           , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_WR_VALID   );
+REG64_FLD( PU_GPE6_JTG_PIB_OJIC_JTAG_INSTR                         , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_JTAG_INSTR );
+REG64_FLD( PU_GPE6_JTG_PIB_OJIC_JTAG_INSTR_LEN                     , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_JTAG_INSTR_LEN );
+
+REG64_FLD( PU_GPE6_JTG_PIB_OJSTAT_JTAG_INPROG                      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_JTAG_INPROG );
+REG64_FLD( PU_GPE6_JTG_PIB_OJSTAT_SRC_SEL_EQ1_ERR                  , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_SRC_SEL_EQ1_ERR );
+REG64_FLD( PU_GPE6_JTG_PIB_OJSTAT_RUN_TCK_EQ0_ERR                  , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_RUN_TCK_EQ0_ERR );
+REG64_FLD( PU_GPE6_JTG_PIB_OJSTAT_TRST_B_EQ0_ERR                   , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_TRST_B_EQ0_ERR );
+REG64_FLD( PU_GPE6_JTG_PIB_OJSTAT_IR_DR_EQ0_ERR                    , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_IR_DR_EQ0_ERR );
+REG64_FLD( PU_GPE6_JTG_PIB_OJSTAT_INPROG_WR_ERR                    , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_INPROG_WR_ERR );
+REG64_FLD( PU_GPE6_JTG_PIB_OJSTAT_FSM_ERROR                        , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_FSM_ERROR  );
+
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDI_JTAG_TDI                          , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_JTAG_TDI   );
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDI_JTAG_TDI_LEN                      , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_JTAG_TDI_LEN );
+
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDO_JTAG_TDO                          , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_JTAG_TDO   );
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDO_JTAG_TDO_LEN                      , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_JTAG_TDO_LEN );
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDO_OJCFG_JTAG_SRC_SEL                , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OJCFG_JTAG_SRC_SEL );
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDO_OJCFG_RUN_TCK                     , 33  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OJCFG_RUN_TCK );
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDO_OJCFG_TCK_WIDTH                   , 34  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OJCFG_TCK_WIDTH );
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDO_OJCFG_TCK_WIDTH_LEN               , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OJCFG_TCK_WIDTH_LEN );
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDO_OJCFG_JTAG_TRST_B                 , 37  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OJCFG_JTAG_TRST_B );
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDO_OJCFG_DBG_HALT                    , 38  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OJCFG_DBG_HALT );
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDO_OJSTAT_JTAG_INPROG                , 40  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OJSTAT_JTAG_INPROG );
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDO_OJSTAT_SRC_SEL_EQ1_ERR            , 41  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OJSTAT_SRC_SEL_EQ1_ERR );
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDO_OJSTAT_RUN_TCK_EQ0_ERR            , 42  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OJSTAT_RUN_TCK_EQ0_ERR );
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDO_OJSTAT_TRST_B_EQ0_ERR             , 43  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OJSTAT_TRST_B_EQ0_ERR );
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDO_OJSTAT_IR_DR_EQ0_ERR              , 44  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OJSTAT_IR_DR_EQ0_ERR );
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDO_OJSTAT_INPROG_WR_ERR              , 45  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OJSTAT_INPROG_WR_ERR );
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDO_OJSTAT_FSM_ERROR                  , 46  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OJSTAT_FSM_ERROR );
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDO_OJIC_DO_IR                        , 49  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OJIC_DO_IR );
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDO_OJIC_DO_DR                        , 50  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OJIC_DO_DR );
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDO_OJIC_DO_TAP_RESET                 , 51  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OJIC_DO_TAP_RESET );
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDO_OJIC_WR_VALID                     , 52  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OJIC_WR_VALID );
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDO_OJIC_JTAG_INSTR                   , 60  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OJIC_JTAG_INSTR );
+REG64_FLD( PU_GPE6_JTG_PIB_OJTDO_OJIC_JTAG_INSTR_LEN               , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OJIC_JTAG_INSTR_LEN );
+
+REG64_FLD( PU_NPU_CTL_LCO_CONFIG_V_TARG                            , 0   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_V_TARG     );
+REG64_FLD( PU_NPU_CTL_LCO_CONFIG_V_TARG_LEN                        , 12  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_V_TARG_LEN );
+REG64_FLD( PU_NPU_CTL_LCO_CONFIG_E_TARG_MIN                        , 12  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_E_TARG_MIN );
+REG64_FLD( PU_NPU_CTL_LCO_CONFIG_E_TARG_MIN_LEN                    , 4   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_E_TARG_MIN_LEN );
+REG64_FLD( PU_NPU_CTL_LCO_CONFIG_RAND_EVENT                        , 16  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_RAND_EVENT );
+REG64_FLD( PU_NPU_CTL_LCO_CONFIG_RAND_EVENT_LEN                    , 4   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_RAND_EVENT_LEN );
+
+REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_MODE_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_LP_MODE_ENABLE );
+REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_ONLY_MODE                       , 1   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_LP_ONLY_MODE );
+REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_TIMER_TICK_CONFIG               , 2   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_LP_TIMER_TICK_CONFIG );
+REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN           , 6   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_LP_TIMER_TICK_CONFIG_LEN );
+REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_MIN_CRED_THRESH                 , 8   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_LP_MIN_CRED_THRESH );
+REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_MIN_CRED_THRESH_LEN             , 12  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_LP_MIN_CRED_THRESH_LEN );
+REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_MAX_CRED_THRESH                 , 20  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_LP_MAX_CRED_THRESH );
+REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_MAX_CRED_THRESH_LEN             , 12  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_LP_MAX_CRED_THRESH_LEN );
+REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_CNT_THRESH                      , 32  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_LP_CNT_THRESH );
+REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_CNT_THRESH_LEN                  , 12  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_LP_CNT_THRESH_LEN );
+
+REG64_FLD( PU_NPU0_NTL1_LOW_PWR_LP_MODE_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_LP_MODE_ENABLE );
+REG64_FLD( PU_NPU0_NTL1_LOW_PWR_LP_ONLY_MODE                       , 1   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_LP_ONLY_MODE );
+REG64_FLD( PU_NPU0_NTL1_LOW_PWR_LP_TIMER_TICK_CONFIG               , 2   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_LP_TIMER_TICK_CONFIG );
+REG64_FLD( PU_NPU0_NTL1_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN           , 6   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_LP_TIMER_TICK_CONFIG_LEN );
+REG64_FLD( PU_NPU0_NTL1_LOW_PWR_LP_MIN_CRED_THRESH                 , 8   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_LP_MIN_CRED_THRESH );
+REG64_FLD( PU_NPU0_NTL1_LOW_PWR_LP_MIN_CRED_THRESH_LEN             , 12  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_LP_MIN_CRED_THRESH_LEN );
+REG64_FLD( PU_NPU0_NTL1_LOW_PWR_LP_MAX_CRED_THRESH                 , 20  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_LP_MAX_CRED_THRESH );
+REG64_FLD( PU_NPU0_NTL1_LOW_PWR_LP_MAX_CRED_THRESH_LEN             , 12  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_LP_MAX_CRED_THRESH_LEN );
+REG64_FLD( PU_NPU0_NTL1_LOW_PWR_LP_CNT_THRESH                      , 32  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_LP_CNT_THRESH );
+REG64_FLD( PU_NPU0_NTL1_LOW_PWR_LP_CNT_THRESH_LEN                  , 12  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_LP_CNT_THRESH_LEN );
+
+REG64_FLD( PU_NPU1_NTL0_LOW_PWR_LP_MODE_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_LP_MODE_ENABLE );
+REG64_FLD( PU_NPU1_NTL0_LOW_PWR_LP_ONLY_MODE                       , 1   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_LP_ONLY_MODE );
+REG64_FLD( PU_NPU1_NTL0_LOW_PWR_LP_TIMER_TICK_CONFIG               , 2   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_LP_TIMER_TICK_CONFIG );
+REG64_FLD( PU_NPU1_NTL0_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN           , 6   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_LP_TIMER_TICK_CONFIG_LEN );
+REG64_FLD( PU_NPU1_NTL0_LOW_PWR_LP_MIN_CRED_THRESH                 , 8   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_LP_MIN_CRED_THRESH );
+REG64_FLD( PU_NPU1_NTL0_LOW_PWR_LP_MIN_CRED_THRESH_LEN             , 12  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_LP_MIN_CRED_THRESH_LEN );
+REG64_FLD( PU_NPU1_NTL0_LOW_PWR_LP_MAX_CRED_THRESH                 , 20  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_LP_MAX_CRED_THRESH );
+REG64_FLD( PU_NPU1_NTL0_LOW_PWR_LP_MAX_CRED_THRESH_LEN             , 12  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_LP_MAX_CRED_THRESH_LEN );
+REG64_FLD( PU_NPU1_NTL0_LOW_PWR_LP_CNT_THRESH                      , 32  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_LP_CNT_THRESH );
+REG64_FLD( PU_NPU1_NTL0_LOW_PWR_LP_CNT_THRESH_LEN                  , 12  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_LP_CNT_THRESH_LEN );
+
+REG64_FLD( PU_NPU1_NTL1_LOW_PWR_LP_MODE_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_LP_MODE_ENABLE );
+REG64_FLD( PU_NPU1_NTL1_LOW_PWR_LP_ONLY_MODE                       , 1   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_LP_ONLY_MODE );
+REG64_FLD( PU_NPU1_NTL1_LOW_PWR_LP_TIMER_TICK_CONFIG               , 2   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_LP_TIMER_TICK_CONFIG );
+REG64_FLD( PU_NPU1_NTL1_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN           , 6   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_LP_TIMER_TICK_CONFIG_LEN );
+REG64_FLD( PU_NPU1_NTL1_LOW_PWR_LP_MIN_CRED_THRESH                 , 8   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_LP_MIN_CRED_THRESH );
+REG64_FLD( PU_NPU1_NTL1_LOW_PWR_LP_MIN_CRED_THRESH_LEN             , 12  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_LP_MIN_CRED_THRESH_LEN );
+REG64_FLD( PU_NPU1_NTL1_LOW_PWR_LP_MAX_CRED_THRESH                 , 20  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_LP_MAX_CRED_THRESH );
+REG64_FLD( PU_NPU1_NTL1_LOW_PWR_LP_MAX_CRED_THRESH_LEN             , 12  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_LP_MAX_CRED_THRESH_LEN );
+REG64_FLD( PU_NPU1_NTL1_LOW_PWR_LP_CNT_THRESH                      , 32  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_LP_CNT_THRESH );
+REG64_FLD( PU_NPU1_NTL1_LOW_PWR_LP_CNT_THRESH_LEN                  , 12  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_LP_CNT_THRESH_LEN );
+
+REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_MODE_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_LP_MODE_ENABLE );
+REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_ONLY_MODE                       , 1   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_LP_ONLY_MODE );
+REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_TIMER_TICK_CONFIG               , 2   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_LP_TIMER_TICK_CONFIG );
+REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN           , 6   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_LP_TIMER_TICK_CONFIG_LEN );
+REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_MIN_CRED_THRESH                 , 8   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_LP_MIN_CRED_THRESH );
+REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_MIN_CRED_THRESH_LEN             , 12  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_LP_MIN_CRED_THRESH_LEN );
+REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_MAX_CRED_THRESH                 , 20  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_LP_MAX_CRED_THRESH );
+REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_MAX_CRED_THRESH_LEN             , 12  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_LP_MAX_CRED_THRESH_LEN );
+REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_CNT_THRESH                      , 32  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_LP_CNT_THRESH );
+REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_CNT_THRESH_LEN                  , 12  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_LP_CNT_THRESH_LEN );
+
+REG64_FLD( PU_NPU0_NTL0_LOW_PWR_LP_MODE_ENABLE                     , 0   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_LP_MODE_ENABLE );
+REG64_FLD( PU_NPU0_NTL0_LOW_PWR_LP_ONLY_MODE                       , 1   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_LP_ONLY_MODE );
+REG64_FLD( PU_NPU0_NTL0_LOW_PWR_LP_TIMER_TICK_CONFIG               , 2   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_LP_TIMER_TICK_CONFIG );
+REG64_FLD( PU_NPU0_NTL0_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN           , 6   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_LP_TIMER_TICK_CONFIG_LEN );
+REG64_FLD( PU_NPU0_NTL0_LOW_PWR_LP_MIN_CRED_THRESH                 , 8   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_LP_MIN_CRED_THRESH );
+REG64_FLD( PU_NPU0_NTL0_LOW_PWR_LP_MIN_CRED_THRESH_LEN             , 12  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_LP_MIN_CRED_THRESH_LEN );
+REG64_FLD( PU_NPU0_NTL0_LOW_PWR_LP_MAX_CRED_THRESH                 , 20  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_LP_MAX_CRED_THRESH );
+REG64_FLD( PU_NPU0_NTL0_LOW_PWR_LP_MAX_CRED_THRESH_LEN             , 12  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_LP_MAX_CRED_THRESH_LEN );
+REG64_FLD( PU_NPU0_NTL0_LOW_PWR_LP_CNT_THRESH                      , 32  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_LP_CNT_THRESH );
+REG64_FLD( PU_NPU0_NTL0_LOW_PWR_LP_CNT_THRESH_LEN                  , 12  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_LP_CNT_THRESH_LEN );
+
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_XATS                       , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_XATS_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PWR0                       , 6   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PWR0_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PWR1                       , 12  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PWR1_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_REQ0                       , 18  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_REQ0_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PRB0                       , 24  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PRB0_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_REQ1                       , 30  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_REQ1_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PRB1                       , 36  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PRB1_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_RESERVED1                         , 42  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 43  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_XATS                       , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_XATS_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PWR0                       , 6   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PWR0_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PWR1                       , 12  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PWR1_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_REQ0                       , 18  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_REQ0_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PRB0                       , 24  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PRB0_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_REQ1                       , 30  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_REQ1_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PRB1                       , 36  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PRB1_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_RESERVED1                         , 42  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 43  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_XATS                       , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_XATS_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PWR0                       , 6   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PWR0_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PWR1                       , 12  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PWR1_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_REQ0                       , 18  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_REQ0_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PRB0                       , 24  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PRB0_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_REQ1                       , 30  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_REQ1_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PRB1                       , 36  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PRB1_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_RESERVED1                         , 42  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 43  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_XATS                       , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_XATS_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PWR0                       , 6   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PWR0_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PWR1                       , 12  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PWR1_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_REQ0                       , 18  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_REQ0_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PRB0                       , 24  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PRB0_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_REQ1                       , 30  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_REQ1_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PRB1                       , 36  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PRB1_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_RESERVED1                         , 42  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 43  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_XATS                       , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_XATS_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PWR0                       , 6   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PWR0_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PWR1                       , 12  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PWR1_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_REQ0                       , 18  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_REQ0_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PRB0                       , 24  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PRB0_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_REQ1                       , 30  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_REQ1_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PRB1                       , 36  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PRB1_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_RESERVED1                         , 42  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 43  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_XATS                       , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_XATS_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PWR0                       , 6   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PWR0_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PWR1                       , 12  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PWR1_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_REQ0                       , 18  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_REQ0_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PRB0                       , 24  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PRB0_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_REQ1                       , 30  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_REQ1_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PRB1                       , 36  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PRB1_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_RESERVED1                         , 42  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 43  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_XATS                       , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_XATS_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PWR0                       , 6   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PWR0_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PWR1                       , 12  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PWR1_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_REQ0                       , 18  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_REQ0_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PRB0                       , 24  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PRB0_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_REQ1                       , 30  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_REQ1_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PRB1                       , 36  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PRB1_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_RESERVED1                         , 42  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 43  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_XATS                       , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_XATS_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PWR0                       , 6   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PWR0_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PWR1                       , 12  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PWR1_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_REQ0                       , 18  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_REQ0_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PRB0                       , 24  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PRB0_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_REQ1                       , 30  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_REQ1_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PRB1                       , 36  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PRB1_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_RESERVED1                         , 42  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 43  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_XATS                       , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_XATS_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PWR0                       , 6   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PWR0_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PWR1                       , 12  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PWR1_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_REQ0                       , 18  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_REQ0_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PRB0                       , 24  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PRB0_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_REQ1                       , 30  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_REQ1_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PRB1                       , 36  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PRB1_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_RESERVED1                         , 42  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 43  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_XATS                       , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_XATS_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PWR0                       , 6   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PWR0_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PWR1                       , 12  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PWR1_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_REQ0                       , 18  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_REQ0_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PRB0                       , 24  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PRB0_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_REQ1                       , 30  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_REQ1_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PRB1                       , 36  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PRB1_LEN                   , 6   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_RESERVED1                         , 42  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 43  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_XATS                       , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_XATS_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PWR0                       , 6   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PWR0_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PWR1                       , 12  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PWR1_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_REQ0                       , 18  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_REQ0_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PRB0                       , 24  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PRB0_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_REQ1                       , 30  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_REQ1_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PRB1                       , 36  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PRB1_LEN                   , 6   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_RESERVED1                         , 42  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 43  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_XATS                       , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_XATS_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PWR0                       , 6   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PWR0_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PWR1                       , 12  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PWR1_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_REQ0                       , 18  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_REQ0_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PRB0                       , 24  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PRB0_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_REQ1                       , 30  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_REQ1_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PRB1                       , 36  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PRB1_LEN                   , 6   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_RESERVED1                         , 42  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 43  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_LPC_BASE_REG_BASE                                    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BASE       );
+REG64_FLD( PU_LPC_BASE_REG_BASE_LEN                                , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BASE_LEN   );
+REG64_FLD( PU_LPC_BASE_REG_DISABLE                                 , 63  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE    );
+
+REG64_FLD( PU_LPC_CMD_REG_RNW                                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RNW        );
+REG64_FLD( PU_LPC_CMD_REG_SIZE                                     , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SIZE       );
+REG64_FLD( PU_LPC_CMD_REG_SIZE_LEN                                 , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SIZE_LEN   );
+REG64_FLD( PU_LPC_CMD_REG_ADR                                      , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADR        );
+REG64_FLD( PU_LPC_CMD_REG_ADR_LEN                                  , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADR_LEN    );
+
+REG64_FLD( PU_LPC_DATA_REG_DATA                                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_LPC_DATA_REG_DATA_LEN                                , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PEC_STACK2_LSIBAR_REG_PE_LSI_BAR                        , 0   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM     , SH_FLD_PE_LSI_BAR );
+REG64_FLD( PEC_STACK2_LSIBAR_REG_PE_LSI_BAR_LEN                    , 40  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM     , SH_FLD_PE_LSI_BAR_LEN );
+
+REG64_FLD( PEC_STACK1_LSIBAR_REG_PE_LSI_BAR                        , 0   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM     , SH_FLD_PE_LSI_BAR );
+REG64_FLD( PEC_STACK1_LSIBAR_REG_PE_LSI_BAR_LEN                    , 40  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM     , SH_FLD_PE_LSI_BAR_LEN );
+
+REG64_FLD( PEC_STACK0_LSIBAR_REG_PE_LSI_BAR                        , 0   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM     , SH_FLD_PE_LSI_BAR );
+REG64_FLD( PEC_STACK0_LSIBAR_REG_PE_LSI_BAR_LEN                    , 40  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM     , SH_FLD_PE_LSI_BAR_LEN );
+
+REG64_FLD( PU_NPU1_SM2_MASK1_MISC_MACH_ERROR_MASK                  , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK );
+REG64_FLD( PU_NPU1_SM2_MASK1_MISC_MACH_ERROR_MASK_LEN              , 64  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK_LEN );
+
+REG64_FLD( PU_NPU1_NTL0_MASK1_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_NTL0_MASK1_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM3_MASK1_MISC_MACH_ERROR_MASK                  , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK );
+REG64_FLD( PU_NPU1_SM3_MASK1_MISC_MACH_ERROR_MASK_LEN              , 64  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK_LEN );
+
+REG64_FLD( PU_NPU1_NTL1_MASK1_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_NTL1_MASK1_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_NTL1_MASK1_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_NTL1_MASK1_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM1_MASK1_MISC_MACH_ERROR_MASK                  , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK );
+REG64_FLD( PU_NPU1_SM1_MASK1_MISC_MACH_ERROR_MASK_LEN              , 64  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK_LEN );
+
+REG64_FLD( PU_NPU0_NTL1_MASK1_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_NTL1_MASK1_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM2_MASK1_MISC_MACH_ERROR_MASK                  , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK );
+REG64_FLD( PU_NPU0_SM2_MASK1_MISC_MACH_ERROR_MASK_LEN              , 64  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK_LEN );
+
+REG64_FLD( PU_NPU0_SM1_MASK1_MISC_MACH_ERROR_MASK                  , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK );
+REG64_FLD( PU_NPU0_SM1_MASK1_MISC_MACH_ERROR_MASK_LEN              , 64  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK_LEN );
+
+REG64_FLD( PU_NPU0_NTL0_MASK1_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_NTL0_MASK1_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM0_MASK1_MISC_MACH_ERROR_MASK                  , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK );
+REG64_FLD( PU_NPU0_SM0_MASK1_MISC_MACH_ERROR_MASK_LEN              , 64  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK_LEN );
+
+REG64_FLD( PU_NPU2_NTL0_MASK1_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_NTL0_MASK1_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM3_MASK1_MISC_MACH_ERROR_MASK                  , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK );
+REG64_FLD( PU_NPU2_SM3_MASK1_MISC_MACH_ERROR_MASK_LEN              , 64  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK_LEN );
+
+REG64_FLD( PU_NPU0_SM3_MASK1_MISC_MACH_ERROR_MASK                  , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK );
+REG64_FLD( PU_NPU0_SM3_MASK1_MISC_MACH_ERROR_MASK_LEN              , 64  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK_LEN );
+
+REG64_FLD( PU_NPU2_SM2_MASK1_MISC_MACH_ERROR_MASK                  , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK );
+REG64_FLD( PU_NPU2_SM2_MASK1_MISC_MACH_ERROR_MASK_LEN              , 64  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK_LEN );
+
+REG64_FLD( PU_NPU2_SM1_MASK1_MISC_MACH_ERROR_MASK                  , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK );
+REG64_FLD( PU_NPU2_SM1_MASK1_MISC_MACH_ERROR_MASK_LEN              , 64  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK_LEN );
+
+REG64_FLD( PU_NPU2_SM0_MASK1_MISC_MACH_ERROR_MASK                  , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK );
+REG64_FLD( PU_NPU2_SM0_MASK1_MISC_MACH_ERROR_MASK_LEN              , 64  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK_LEN );
+
+REG64_FLD( PU_NPU1_SM0_MASK1_MISC_MACH_ERROR_MASK                  , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK );
+REG64_FLD( PU_NPU1_SM0_MASK1_MISC_MACH_ERROR_MASK_LEN              , 64  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_MISC_MACH_ERROR_MASK_LEN );
+
+REG64_FLD( PU_NPU1_SM2_MASK2_IDIAL                                 , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM2_MASK2_IDIAL_LEN                             , 64  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_NTL0_MASK2_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_NTL0_MASK2_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM3_MASK2_IDIAL                                 , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM3_MASK2_IDIAL_LEN                             , 64  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_NTL1_MASK2_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_NTL1_MASK2_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_NTL1_MASK2_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_NTL1_MASK2_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM1_MASK2_IDIAL                                 , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM1_MASK2_IDIAL_LEN                             , 64  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_NTL1_MASK2_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_NTL1_MASK2_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM2_MASK2_IDIAL                                 , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM2_MASK2_IDIAL_LEN                             , 64  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_CTL_MASK2_IDIAL                                 , 0   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_CTL_MASK2_IDIAL_LEN                             , 64  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM1_MASK2_IDIAL                                 , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM1_MASK2_IDIAL_LEN                             , 64  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_NTL0_MASK2_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_NTL0_MASK2_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM0_MASK2_IDIAL                                 , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM0_MASK2_IDIAL_LEN                             , 64  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_NTL0_MASK2_IDIAL                                , 0   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_NTL0_MASK2_IDIAL_LEN                            , 64  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM3_MASK2_IDIAL                                 , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM3_MASK2_IDIAL_LEN                             , 64  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM3_MASK2_IDIAL                                 , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM3_MASK2_IDIAL_LEN                             , 64  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM2_MASK2_IDIAL                                 , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM2_MASK2_IDIAL_LEN                             , 64  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_CTL_MASK2_IDIAL                                 , 0   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_CTL_MASK2_IDIAL_LEN                             , 64  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM1_MASK2_IDIAL                                 , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM1_MASK2_IDIAL_LEN                             , 64  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM0_MASK2_IDIAL                                 , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM0_MASK2_IDIAL_LEN                             , 64  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_CTL_MASK2_IDIAL                                 , 0   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_CTL_MASK2_IDIAL_LEN                             , 64  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM0_MASK2_IDIAL                                 , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM0_MASK2_IDIAL_LEN                             , 64  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM0_MAX_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM0_MAX_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM0_MAX_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM0_MAX_BAR_CONFIG_ADDR_LEN                     , 26  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+
+REG64_FLD( PU_NPU1_SM2_MAX_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM2_MAX_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM2_MAX_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM2_MAX_BAR_CONFIG_ADDR_LEN                     , 26  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+
+REG64_FLD( PU_NPU2_SM3_MAX_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM3_MAX_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM3_MAX_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM3_MAX_BAR_CONFIG_ADDR_LEN                     , 26  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+
+REG64_FLD( PU_NPU1_SM3_MAX_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM3_MAX_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM3_MAX_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM3_MAX_BAR_CONFIG_ADDR_LEN                     , 26  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+
+REG64_FLD( PU_NPU0_SM3_MAX_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM3_MAX_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM3_MAX_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM3_MAX_BAR_CONFIG_ADDR_LEN                     , 26  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+
+REG64_FLD( PU_NPU1_SM1_MAX_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM1_MAX_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM1_MAX_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM1_MAX_BAR_CONFIG_ADDR_LEN                     , 26  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+
+REG64_FLD( PU_NPU2_SM2_MAX_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM2_MAX_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM2_MAX_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM2_MAX_BAR_CONFIG_ADDR_LEN                     , 26  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+
+REG64_FLD( PU_NPU2_SM1_MAX_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM1_MAX_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM1_MAX_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM1_MAX_BAR_CONFIG_ADDR_LEN                     , 26  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+
+REG64_FLD( PU_NPU0_SM2_MAX_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM2_MAX_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM2_MAX_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM2_MAX_BAR_CONFIG_ADDR_LEN                     , 26  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+
+REG64_FLD( PU_NPU2_SM0_MAX_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM0_MAX_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM0_MAX_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM0_MAX_BAR_CONFIG_ADDR_LEN                     , 26  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+
+REG64_FLD( PU_NPU0_SM1_MAX_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM1_MAX_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM1_MAX_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM1_MAX_BAR_CONFIG_ADDR_LEN                     , 26  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+
+REG64_FLD( PU_NPU1_SM0_MAX_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM0_MAX_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM0_MAX_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM0_MAX_BAR_CONFIG_ADDR_LEN                     , 26  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+
+REG64_FLD( PU_MCD_DBG_TRACE_ENABLE                                 , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRACE_ENABLE );
+REG64_FLD( PU_MCD_DBG_TRACE_SELECT                                 , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRACE_SELECT );
+REG64_FLD( PU_MCD_DBG_TRACE_SELECT_LEN                             , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRACE_SELECT_LEN );
+REG64_FLD( PU_MCD_DBG_ERR_INJ_ENABLE                               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERR_INJ_ENABLE );
+REG64_FLD( PU_MCD_DBG_ERR_INJ_TYPE                                 , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERR_INJ_TYPE );
+REG64_FLD( PU_MCD_DBG_ERR_INJ_ACTION                               , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERR_INJ_ACTION );
+REG64_FLD( PU_MCD_DBG_ERR_INJ_ARRAY_SEL                            , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERR_INJ_ARRAY_SEL );
+REG64_FLD( PU_MCD_DBG_ERR_INJ_ARRAY_SEL_LEN                        , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERR_INJ_ARRAY_SEL_LEN );
+REG64_FLD( PU_MCD_DBG_ERR_INJ_STATUS                               , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERR_INJ_STATUS );
+REG64_FLD( PU_MCD_DBG_PMU_ENABLE                                   , 19  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PMU_ENABLE );
+REG64_FLD( PU_MCD_DBG_PMU_SELECT_LOW                               , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PMU_SELECT_LOW );
+REG64_FLD( PU_MCD_DBG_PMU_SELECT_LOW_LEN                           , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PMU_SELECT_LOW_LEN );
+REG64_FLD( PU_MCD_DBG_PMU_SELECT_HIGH                              , 23  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PMU_SELECT_HIGH );
+REG64_FLD( PU_MCD_DBG_PMU_SELECT_HIGH_LEN                          , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PMU_SELECT_HIGH_LEN );
+REG64_FLD( PU_MCD_DBG_PMU_BUS_ENABLE                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PMU_BUS_ENABLE );
+REG64_FLD( PU_MCD_DBG_PMU_BUS_ENABLE_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PMU_BUS_ENABLE_LEN );
+
+REG64_FLD( PU_MCD1_MCD_DBG_TRACE_ENABLE                            , 3   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_TRACE_ENABLE );
+REG64_FLD( PU_MCD1_MCD_DBG_TRACE_SELECT                            , 4   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_TRACE_SELECT );
+REG64_FLD( PU_MCD1_MCD_DBG_TRACE_SELECT_LEN                        , 4   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_TRACE_SELECT_LEN );
+REG64_FLD( PU_MCD1_MCD_DBG_ERR_INJ_ENABLE                          , 8   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_ERR_INJ_ENABLE );
+REG64_FLD( PU_MCD1_MCD_DBG_ERR_INJ_TYPE                            , 9   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_ERR_INJ_TYPE );
+REG64_FLD( PU_MCD1_MCD_DBG_ERR_INJ_ACTION                          , 10  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_ERR_INJ_ACTION );
+REG64_FLD( PU_MCD1_MCD_DBG_ERR_INJ_ARRAY_SEL                       , 11  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_ERR_INJ_ARRAY_SEL );
+REG64_FLD( PU_MCD1_MCD_DBG_ERR_INJ_ARRAY_SEL_LEN                   , 4   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_ERR_INJ_ARRAY_SEL_LEN );
+REG64_FLD( PU_MCD1_MCD_DBG_ERR_INJ_STATUS                          , 15  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_ERR_INJ_STATUS );
+REG64_FLD( PU_MCD1_MCD_DBG_PMU_ENABLE                              , 19  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_PMU_ENABLE );
+REG64_FLD( PU_MCD1_MCD_DBG_PMU_SELECT_LOW                          , 20  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_PMU_SELECT_LOW );
+REG64_FLD( PU_MCD1_MCD_DBG_PMU_SELECT_LOW_LEN                      , 3   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_PMU_SELECT_LOW_LEN );
+REG64_FLD( PU_MCD1_MCD_DBG_PMU_SELECT_HIGH                         , 23  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_PMU_SELECT_HIGH );
+REG64_FLD( PU_MCD1_MCD_DBG_PMU_SELECT_HIGH_LEN                     , 3   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_PMU_SELECT_HIGH_LEN );
+REG64_FLD( PU_MCD1_MCD_DBG_PMU_BUS_ENABLE                          , 32  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_PMU_BUS_ENABLE );
+REG64_FLD( PU_MCD1_MCD_DBG_PMU_BUS_ENABLE_LEN                      , 16  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_PMU_BUS_ENABLE_LEN );
+
+REG64_FLD( PU_MCD_ECAP_ECC_CLEAR                                   , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_CLEAR  );
+REG64_FLD( PU_MCD_ECAP_ECC_UE                                      , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_UE     );
+REG64_FLD( PU_MCD_ECAP_ECC_CE                                      , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_CE     );
+REG64_FLD( PU_MCD_ECAP_ECC_ERROR_COUNT                             , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_ERROR_COUNT );
+REG64_FLD( PU_MCD_ECAP_ECC_ERROR_COUNT_LEN                         , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_ERROR_COUNT_LEN );
+REG64_FLD( PU_MCD_ECAP_ECC_ERROR_ADDR                              , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_ERROR_ADDR );
+REG64_FLD( PU_MCD_ECAP_ECC_ERROR_ADDR_LEN                          , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_ERROR_ADDR_LEN );
+REG64_FLD( PU_MCD_ECAP_ECC_SYNDROME                                , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_SYNDROME );
+REG64_FLD( PU_MCD_ECAP_ECC_SYNDROME_LEN                            , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_SYNDROME_LEN );
+REG64_FLD( PU_MCD_ECAP_SLICE0_CFG_ECC_UE_ERR                       , 33  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SLICE0_CFG_ECC_UE_ERR );
+REG64_FLD( PU_MCD_ECAP_SLICE0_CFG_ECC_CE_ERR                       , 34  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SLICE0_CFG_ECC_CE_ERR );
+REG64_FLD( PU_MCD_ECAP_SLICE1_CFG_ECC_UE_ERR                       , 35  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SLICE1_CFG_ECC_UE_ERR );
+REG64_FLD( PU_MCD_ECAP_SLICE1_CFG_ECC_CE_ERR                       , 36  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SLICE1_CFG_ECC_CE_ERR );
+REG64_FLD( PU_MCD_ECAP_SLICE2_CFG_ECC_UE_ERR                       , 37  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SLICE2_CFG_ECC_UE_ERR );
+REG64_FLD( PU_MCD_ECAP_SLICE2_CFG_ECC_CE_ERR                       , 38  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SLICE2_CFG_ECC_CE_ERR );
+REG64_FLD( PU_MCD_ECAP_SLICE3_CFG_ECC_UE_ERR                       , 39  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SLICE3_CFG_ECC_UE_ERR );
+REG64_FLD( PU_MCD_ECAP_SLICE3_CFG_ECC_CE_ERR                       , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SLICE3_CFG_ECC_CE_ERR );
+REG64_FLD( PU_MCD_ECAP_PRESP_RTY_OTHER                             , 41  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRESP_RTY_OTHER );
+REG64_FLD( PU_MCD_ECAP_REC_SM_ERROR_ERR                            , 42  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REC_SM_ERROR_ERR );
+REG64_FLD( PU_MCD_ECAP_REC_PB_SM_ERROR_ERR                         , 43  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REC_PB_SM_ERROR_ERR );
+REG64_FLD( PU_MCD_ECAP_ADDR_ERROR_PULSE                            , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADDR_ERROR_PULSE );
+REG64_FLD( PU_MCD_ECAP_RCMD0_ADDR_PARITY_ERROR                     , 45  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RCMD0_ADDR_PARITY_ERROR );
+REG64_FLD( PU_MCD_ECAP_RCMD1_ADDR_PARITY_ERROR                     , 46  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RCMD1_ADDR_PARITY_ERROR );
+REG64_FLD( PU_MCD_ECAP_RCMD2_ADDR_PARITY_ERROR                     , 47  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RCMD2_ADDR_PARITY_ERROR );
+REG64_FLD( PU_MCD_ECAP_RCMD3_ADDR_PARITY_ERROR                     , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RCMD3_ADDR_PARITY_ERROR );
+REG64_FLD( PU_MCD_ECAP_WARB_INVALID_CASE_ERROR                     , 49  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WARB_INVALID_CASE_ERROR );
+REG64_FLD( PU_MCD_ECAP_INVALID_CRESP_ERROR                         , 50  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INVALID_CRESP_ERROR );
+REG64_FLD( PU_MCD_ECAP_TTAG_PARITY_ERROR                           , 51  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TTAG_PARITY_ERROR );
+REG64_FLD( PU_MCD_ECAP_RDADDR_ARB_BAD_HAND                         , 52  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RDADDR_ARB_BAD_HAND );
+REG64_FLD( PU_MCD_ECAP_RDWR_UPDATE_ERROR                           , 53  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RDWR_UPDATE_ERROR );
+REG64_FLD( PU_MCD_ECAP_REC_UPDATE_ERROR                            , 54  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REC_UPDATE_ERROR );
+
+REG64_FLD( PU_MCD1_MCD_ECAP_ECC_CLEAR                              , 0   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_ECC_CLEAR  );
+REG64_FLD( PU_MCD1_MCD_ECAP_ECC_UE                                 , 2   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_ECC_UE     );
+REG64_FLD( PU_MCD1_MCD_ECAP_ECC_CE                                 , 3   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_ECC_CE     );
+REG64_FLD( PU_MCD1_MCD_ECAP_ECC_ERROR_COUNT                        , 4   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_ECC_ERROR_COUNT );
+REG64_FLD( PU_MCD1_MCD_ECAP_ECC_ERROR_COUNT_LEN                    , 4   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_ECC_ERROR_COUNT_LEN );
+REG64_FLD( PU_MCD1_MCD_ECAP_ECC_ERROR_ADDR                         , 10  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_ECC_ERROR_ADDR );
+REG64_FLD( PU_MCD1_MCD_ECAP_ECC_ERROR_ADDR_LEN                     , 14  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_ECC_ERROR_ADDR_LEN );
+REG64_FLD( PU_MCD1_MCD_ECAP_ECC_SYNDROME                           , 24  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_ECC_SYNDROME );
+REG64_FLD( PU_MCD1_MCD_ECAP_ECC_SYNDROME_LEN                       , 8   ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_ECC_SYNDROME_LEN );
+REG64_FLD( PU_MCD1_MCD_ECAP_SLICE0_CFG_ECC_UE_ERR                  , 33  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_SLICE0_CFG_ECC_UE_ERR );
+REG64_FLD( PU_MCD1_MCD_ECAP_SLICE0_CFG_ECC_CE_ERR                  , 34  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_SLICE0_CFG_ECC_CE_ERR );
+REG64_FLD( PU_MCD1_MCD_ECAP_SLICE1_CFG_ECC_UE_ERR                  , 35  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_SLICE1_CFG_ECC_UE_ERR );
+REG64_FLD( PU_MCD1_MCD_ECAP_SLICE1_CFG_ECC_CE_ERR                  , 36  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_SLICE1_CFG_ECC_CE_ERR );
+REG64_FLD( PU_MCD1_MCD_ECAP_SLICE2_CFG_ECC_UE_ERR                  , 37  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_SLICE2_CFG_ECC_UE_ERR );
+REG64_FLD( PU_MCD1_MCD_ECAP_SLICE2_CFG_ECC_CE_ERR                  , 38  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_SLICE2_CFG_ECC_CE_ERR );
+REG64_FLD( PU_MCD1_MCD_ECAP_SLICE3_CFG_ECC_UE_ERR                  , 39  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_SLICE3_CFG_ECC_UE_ERR );
+REG64_FLD( PU_MCD1_MCD_ECAP_SLICE3_CFG_ECC_CE_ERR                  , 40  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_SLICE3_CFG_ECC_CE_ERR );
+REG64_FLD( PU_MCD1_MCD_ECAP_PRESP_RTY_OTHER                        , 41  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_PRESP_RTY_OTHER );
+REG64_FLD( PU_MCD1_MCD_ECAP_REC_SM_ERROR_ERR                       , 42  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_REC_SM_ERROR_ERR );
+REG64_FLD( PU_MCD1_MCD_ECAP_REC_PB_SM_ERROR_ERR                    , 43  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_REC_PB_SM_ERROR_ERR );
+REG64_FLD( PU_MCD1_MCD_ECAP_ADDR_ERROR_PULSE                       , 44  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_ADDR_ERROR_PULSE );
+REG64_FLD( PU_MCD1_MCD_ECAP_RCMD0_ADDR_PARITY_ERROR                , 45  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_RCMD0_ADDR_PARITY_ERROR );
+REG64_FLD( PU_MCD1_MCD_ECAP_RCMD1_ADDR_PARITY_ERROR                , 46  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_RCMD1_ADDR_PARITY_ERROR );
+REG64_FLD( PU_MCD1_MCD_ECAP_RCMD2_ADDR_PARITY_ERROR                , 47  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_RCMD2_ADDR_PARITY_ERROR );
+REG64_FLD( PU_MCD1_MCD_ECAP_RCMD3_ADDR_PARITY_ERROR                , 48  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_RCMD3_ADDR_PARITY_ERROR );
+REG64_FLD( PU_MCD1_MCD_ECAP_WARB_INVALID_CASE_ERROR                , 49  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_WARB_INVALID_CASE_ERROR );
+REG64_FLD( PU_MCD1_MCD_ECAP_INVALID_CRESP_ERROR                    , 50  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_INVALID_CRESP_ERROR );
+REG64_FLD( PU_MCD1_MCD_ECAP_TTAG_PARITY_ERROR                      , 51  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_TTAG_PARITY_ERROR );
+REG64_FLD( PU_MCD1_MCD_ECAP_RDADDR_ARB_BAD_HAND                    , 52  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_RDADDR_ARB_BAD_HAND );
+REG64_FLD( PU_MCD1_MCD_ECAP_RDWR_UPDATE_ERROR                      , 53  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_RDWR_UPDATE_ERROR );
+REG64_FLD( PU_MCD1_MCD_ECAP_REC_UPDATE_ERROR                       , 54  ,
+           SH_UNT_PU_MCD1  , SH_ACS_SCOM     , SH_FLD_REC_UPDATE_ERROR );
+
+REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_TAG_ADDR                      , 0   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_DCACHE_TAG_ADDR );
+REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN                  , 27  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_DCACHE_TAG_ADDR_LEN );
+REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_ERR                           , 32  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_DCACHE_ERR );
+
+REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_TAG_ADDR                      , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_DCACHE_TAG_ADDR );
+REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN                  , 27  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_DCACHE_TAG_ADDR_LEN );
+REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_ERR                           , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_DCACHE_ERR );
+
+REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_TAG_ADDR                      , 0   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_DCACHE_TAG_ADDR );
+REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN                  , 27  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_DCACHE_TAG_ADDR_LEN );
+REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_ERR                           , 32  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_DCACHE_ERR );
+
+REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_TAG_ADDR                      , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_DCACHE_TAG_ADDR );
+REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN                  , 27  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_DCACHE_TAG_ADDR_LEN );
+REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_ERR                           , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_DCACHE_ERR );
+
+REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_TAG_ADDR                      , 0   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_TAG_ADDR );
+REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_TAG_ADDR_LEN                  , 27  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_TAG_ADDR_LEN );
+REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_ERR                           , 32  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_ERR );
+REG64_FLD( PU_GPE2_MIB_XIICAC_XISIB_PIB_IFETCH_PENDING             , 34  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_XISIB_PIB_IFETCH_PENDING );
+REG64_FLD( PU_GPE2_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING             , 35  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_XIMEM_MEM_IFETCH_PENDING );
+REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_VALID                         , 36  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_VALID );
+REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_VALID_LEN                     , 4   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_VALID_LEN );
+
+REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_TAG_ADDR                      , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_TAG_ADDR );
+REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_TAG_ADDR_LEN                  , 27  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_TAG_ADDR_LEN );
+REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_ERR                           , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_ERR );
+REG64_FLD( PU_GPE1_MIB_XIICAC_XISIB_PIB_IFETCH_PENDING             , 34  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_XISIB_PIB_IFETCH_PENDING );
+REG64_FLD( PU_GPE1_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING             , 35  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_XIMEM_MEM_IFETCH_PENDING );
+REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_VALID                         , 36  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_VALID );
+REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_VALID_LEN                     , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_VALID_LEN );
+
+REG64_FLD( PU_MIB_XIICAC_ICACHE_TAG_ADDR                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_TAG_ADDR );
+REG64_FLD( PU_MIB_XIICAC_ICACHE_TAG_ADDR_LEN                       , 27  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_TAG_ADDR_LEN );
+REG64_FLD( PU_MIB_XIICAC_ICACHE_ERR                                , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_ERR );
+REG64_FLD( PU_MIB_XIICAC_XISIB_PIB_IFETCH_PENDING                  , 34  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_XISIB_PIB_IFETCH_PENDING );
+REG64_FLD( PU_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING                  , 35  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_XIMEM_MEM_IFETCH_PENDING );
+REG64_FLD( PU_MIB_XIICAC_ICACHE_VALID                              , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_VALID );
+REG64_FLD( PU_MIB_XIICAC_ICACHE_VALID_LEN                          , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_VALID_LEN );
+
+REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_TAG_ADDR                      , 0   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_TAG_ADDR );
+REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_TAG_ADDR_LEN                  , 27  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_TAG_ADDR_LEN );
+REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_ERR                           , 32  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_ERR );
+REG64_FLD( PU_GPE3_MIB_XIICAC_XISIB_PIB_IFETCH_PENDING             , 34  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_XISIB_PIB_IFETCH_PENDING );
+REG64_FLD( PU_GPE3_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING             , 35  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_XIMEM_MEM_IFETCH_PENDING );
+REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_VALID                         , 36  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_VALID );
+REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_VALID_LEN                     , 4   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_VALID_LEN );
+
+REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_TAG_ADDR                      , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_TAG_ADDR );
+REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_TAG_ADDR_LEN                  , 27  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_TAG_ADDR_LEN );
+REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_ERR                           , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_ERR );
+REG64_FLD( PU_GPE0_MIB_XIICAC_XISIB_PIB_IFETCH_PENDING             , 34  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_XISIB_PIB_IFETCH_PENDING );
+REG64_FLD( PU_GPE0_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING             , 35  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_XIMEM_MEM_IFETCH_PENDING );
+REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_VALID                         , 36  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_VALID );
+REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_VALID_LEN                     , 4   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_VALID_LEN );
+
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_ADDR                              , 0   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_MEM_ADDR   );
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_ADDR_LEN                          , 32  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_MEM_ADDR_LEN );
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_R_NW                              , 32  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_MEM_R_NW   );
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_BUSY                              , 33  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_MEM_BUSY   );
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING           , 34  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_BYTE_ENABLE                       , 35  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_MEM_BYTE_ENABLE );
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_BYTE_ENABLE_LEN                   , 8   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_MEM_BYTE_ENABLE_LEN );
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_LINE_MODE                         , 43  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_MEM_LINE_MODE );
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_ERROR                             , 49  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_MEM_ERROR  );
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_ERROR_LEN                         , 3   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_MEM_ERROR_LEN );
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_IFETCH_PENDING                    , 62  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_MEM_IFETCH_PENDING );
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_DATAOP_PENDING                    , 63  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_MEM_DATAOP_PENDING );
+
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_ADDR                              , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_MEM_ADDR   );
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_ADDR_LEN                          , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_MEM_ADDR_LEN );
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_R_NW                              , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_MEM_R_NW   );
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_BUSY                              , 33  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_MEM_BUSY   );
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING           , 34  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_BYTE_ENABLE                       , 35  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_MEM_BYTE_ENABLE );
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_BYTE_ENABLE_LEN                   , 8   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_MEM_BYTE_ENABLE_LEN );
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_LINE_MODE                         , 43  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_MEM_LINE_MODE );
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_ERROR                             , 49  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_MEM_ERROR  );
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_ERROR_LEN                         , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_MEM_ERROR_LEN );
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_IFETCH_PENDING                    , 62  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_MEM_IFETCH_PENDING );
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_DATAOP_PENDING                    , 63  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_MEM_DATAOP_PENDING );
+
+REG64_FLD( PU_MIB_XIMEM_MEM_ADDR                                   , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MEM_ADDR   );
+REG64_FLD( PU_MIB_XIMEM_MEM_ADDR_LEN                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MEM_ADDR_LEN );
+REG64_FLD( PU_MIB_XIMEM_MEM_R_NW                                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MEM_R_NW   );
+REG64_FLD( PU_MIB_XIMEM_MEM_BUSY                                   , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MEM_BUSY   );
+REG64_FLD( PU_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING                , 34  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_MIB_XIMEM_MEM_BYTE_ENABLE                            , 35  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MEM_BYTE_ENABLE );
+REG64_FLD( PU_MIB_XIMEM_MEM_BYTE_ENABLE_LEN                        , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MEM_BYTE_ENABLE_LEN );
+REG64_FLD( PU_MIB_XIMEM_MEM_LINE_MODE                              , 43  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MEM_LINE_MODE );
+REG64_FLD( PU_MIB_XIMEM_MEM_ERROR                                  , 49  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MEM_ERROR  );
+REG64_FLD( PU_MIB_XIMEM_MEM_ERROR_LEN                              , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MEM_ERROR_LEN );
+REG64_FLD( PU_MIB_XIMEM_MEM_IFETCH_PENDING                         , 62  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MEM_IFETCH_PENDING );
+REG64_FLD( PU_MIB_XIMEM_MEM_DATAOP_PENDING                         , 63  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MEM_DATAOP_PENDING );
+
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_ADDR                              , 0   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_MEM_ADDR   );
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_ADDR_LEN                          , 32  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_MEM_ADDR_LEN );
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_R_NW                              , 32  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_MEM_R_NW   );
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_BUSY                              , 33  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_MEM_BUSY   );
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING           , 34  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_BYTE_ENABLE                       , 35  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_MEM_BYTE_ENABLE );
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_BYTE_ENABLE_LEN                   , 8   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_MEM_BYTE_ENABLE_LEN );
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_LINE_MODE                         , 43  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_MEM_LINE_MODE );
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_ERROR                             , 49  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_MEM_ERROR  );
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_ERROR_LEN                         , 3   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_MEM_ERROR_LEN );
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_IFETCH_PENDING                    , 62  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_MEM_IFETCH_PENDING );
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_DATAOP_PENDING                    , 63  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_MEM_DATAOP_PENDING );
+
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_ADDR                              , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_MEM_ADDR   );
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_ADDR_LEN                          , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_MEM_ADDR_LEN );
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_R_NW                              , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_MEM_R_NW   );
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_BUSY                              , 33  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_MEM_BUSY   );
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING           , 34  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_BYTE_ENABLE                       , 35  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_MEM_BYTE_ENABLE );
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_BYTE_ENABLE_LEN                   , 8   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_MEM_BYTE_ENABLE_LEN );
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_LINE_MODE                         , 43  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_MEM_LINE_MODE );
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_ERROR                             , 49  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_MEM_ERROR  );
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_ERROR_LEN                         , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_MEM_ERROR_LEN );
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_IFETCH_PENDING                    , 62  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_MEM_IFETCH_PENDING );
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_DATAOP_PENDING                    , 63  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_MEM_DATAOP_PENDING );
+
+REG64_FLD( PU_GPE2_MIB_XISGB_STORE_ADDRESS                         , 0   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_STORE_ADDRESS );
+REG64_FLD( PU_GPE2_MIB_XISGB_STORE_ADDRESS_LEN                     , 32  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_STORE_ADDRESS_LEN );
+REG64_FLD( PU_GPE2_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING     , 35  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_GPE2_MIB_XISGB_SGB_BYTE_VALID                        , 36  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_SGB_BYTE_VALID );
+REG64_FLD( PU_GPE2_MIB_XISGB_SGB_BYTE_VALID_LEN                    , 4   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_SGB_BYTE_VALID_LEN );
+REG64_FLD( PU_GPE2_MIB_XISGB_SGB_FLUSH_PENDING                     , 63  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_SGB_FLUSH_PENDING );
+
+REG64_FLD( PU_GPE1_MIB_XISGB_STORE_ADDRESS                         , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_STORE_ADDRESS );
+REG64_FLD( PU_GPE1_MIB_XISGB_STORE_ADDRESS_LEN                     , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_STORE_ADDRESS_LEN );
+REG64_FLD( PU_GPE1_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING     , 35  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_GPE1_MIB_XISGB_SGB_BYTE_VALID                        , 36  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_SGB_BYTE_VALID );
+REG64_FLD( PU_GPE1_MIB_XISGB_SGB_BYTE_VALID_LEN                    , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_SGB_BYTE_VALID_LEN );
+REG64_FLD( PU_GPE1_MIB_XISGB_SGB_FLUSH_PENDING                     , 63  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_SGB_FLUSH_PENDING );
+
+REG64_FLD( PU_MIB_XISGB_STORE_ADDRESS                              , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_STORE_ADDRESS );
+REG64_FLD( PU_MIB_XISGB_STORE_ADDRESS_LEN                          , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_STORE_ADDRESS_LEN );
+REG64_FLD( PU_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING          , 35  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_MIB_XISGB_SGB_BYTE_VALID                             , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SGB_BYTE_VALID );
+REG64_FLD( PU_MIB_XISGB_SGB_BYTE_VALID_LEN                         , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SGB_BYTE_VALID_LEN );
+REG64_FLD( PU_MIB_XISGB_SGB_FLUSH_PENDING                          , 63  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SGB_FLUSH_PENDING );
+
+REG64_FLD( PU_GPE3_MIB_XISGB_STORE_ADDRESS                         , 0   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_STORE_ADDRESS );
+REG64_FLD( PU_GPE3_MIB_XISGB_STORE_ADDRESS_LEN                     , 32  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_STORE_ADDRESS_LEN );
+REG64_FLD( PU_GPE3_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING     , 35  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_GPE3_MIB_XISGB_SGB_BYTE_VALID                        , 36  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_SGB_BYTE_VALID );
+REG64_FLD( PU_GPE3_MIB_XISGB_SGB_BYTE_VALID_LEN                    , 4   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_SGB_BYTE_VALID_LEN );
+REG64_FLD( PU_GPE3_MIB_XISGB_SGB_FLUSH_PENDING                     , 63  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_SGB_FLUSH_PENDING );
+
+REG64_FLD( PU_GPE0_MIB_XISGB_STORE_ADDRESS                         , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_STORE_ADDRESS );
+REG64_FLD( PU_GPE0_MIB_XISGB_STORE_ADDRESS_LEN                     , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_STORE_ADDRESS_LEN );
+REG64_FLD( PU_GPE0_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING     , 35  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_GPE0_MIB_XISGB_SGB_BYTE_VALID                        , 36  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_SGB_BYTE_VALID );
+REG64_FLD( PU_GPE0_MIB_XISGB_SGB_BYTE_VALID_LEN                    , 4   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_SGB_BYTE_VALID_LEN );
+REG64_FLD( PU_GPE0_MIB_XISGB_SGB_FLUSH_PENDING                     , 63  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_SGB_FLUSH_PENDING );
+
+REG64_FLD( PU_GPE2_MIB_XISIB_PIB_ADDR                              , 0   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_PIB_ADDR   );
+REG64_FLD( PU_GPE2_MIB_XISIB_PIB_ADDR_LEN                          , 32  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_PIB_ADDR_LEN );
+REG64_FLD( PU_GPE2_MIB_XISIB_PIB_R_NW                              , 32  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_PIB_R_NW   );
+REG64_FLD( PU_GPE2_MIB_XISIB_PIB_BUSY                              , 33  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_PIB_BUSY   );
+REG64_FLD( PU_GPE2_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING           , 34  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_PIB_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_GPE2_MIB_XISIB_PIB_RSP_INFO                          , 49  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_PIB_RSP_INFO );
+REG64_FLD( PU_GPE2_MIB_XISIB_PIB_RSP_INFO_LEN                      , 3   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_PIB_RSP_INFO_LEN );
+REG64_FLD( PU_GPE2_MIB_XISIB_PIB_IFETCH_PENDING                    , 62  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_PIB_IFETCH_PENDING );
+REG64_FLD( PU_GPE2_MIB_XISIB_PIB_DATAOP_PENDING                    , 63  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_RO  , SH_FLD_PIB_DATAOP_PENDING );
+
+REG64_FLD( PU_GPE1_MIB_XISIB_PIB_ADDR                              , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_PIB_ADDR   );
+REG64_FLD( PU_GPE1_MIB_XISIB_PIB_ADDR_LEN                          , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_PIB_ADDR_LEN );
+REG64_FLD( PU_GPE1_MIB_XISIB_PIB_R_NW                              , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_PIB_R_NW   );
+REG64_FLD( PU_GPE1_MIB_XISIB_PIB_BUSY                              , 33  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_PIB_BUSY   );
+REG64_FLD( PU_GPE1_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING           , 34  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_PIB_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_GPE1_MIB_XISIB_PIB_RSP_INFO                          , 49  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_PIB_RSP_INFO );
+REG64_FLD( PU_GPE1_MIB_XISIB_PIB_RSP_INFO_LEN                      , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_PIB_RSP_INFO_LEN );
+REG64_FLD( PU_GPE1_MIB_XISIB_PIB_IFETCH_PENDING                    , 62  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_PIB_IFETCH_PENDING );
+REG64_FLD( PU_GPE1_MIB_XISIB_PIB_DATAOP_PENDING                    , 63  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_RO  , SH_FLD_PIB_DATAOP_PENDING );
+
+REG64_FLD( PU_MIB_XISIB_PIB_ADDR                                   , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PIB_ADDR   );
+REG64_FLD( PU_MIB_XISIB_PIB_ADDR_LEN                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PIB_ADDR_LEN );
+REG64_FLD( PU_MIB_XISIB_PIB_R_NW                                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PIB_R_NW   );
+REG64_FLD( PU_MIB_XISIB_PIB_BUSY                                   , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PIB_BUSY   );
+REG64_FLD( PU_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING                , 34  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PIB_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_MIB_XISIB_PIB_RSP_INFO                               , 49  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PIB_RSP_INFO );
+REG64_FLD( PU_MIB_XISIB_PIB_RSP_INFO_LEN                           , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PIB_RSP_INFO_LEN );
+REG64_FLD( PU_MIB_XISIB_PIB_IFETCH_PENDING                         , 62  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PIB_IFETCH_PENDING );
+REG64_FLD( PU_MIB_XISIB_PIB_DATAOP_PENDING                         , 63  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PIB_DATAOP_PENDING );
+
+REG64_FLD( PU_GPE3_MIB_XISIB_PIB_ADDR                              , 0   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_PIB_ADDR   );
+REG64_FLD( PU_GPE3_MIB_XISIB_PIB_ADDR_LEN                          , 32  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_PIB_ADDR_LEN );
+REG64_FLD( PU_GPE3_MIB_XISIB_PIB_R_NW                              , 32  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_PIB_R_NW   );
+REG64_FLD( PU_GPE3_MIB_XISIB_PIB_BUSY                              , 33  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_PIB_BUSY   );
+REG64_FLD( PU_GPE3_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING           , 34  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_PIB_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_GPE3_MIB_XISIB_PIB_RSP_INFO                          , 49  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_PIB_RSP_INFO );
+REG64_FLD( PU_GPE3_MIB_XISIB_PIB_RSP_INFO_LEN                      , 3   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_PIB_RSP_INFO_LEN );
+REG64_FLD( PU_GPE3_MIB_XISIB_PIB_IFETCH_PENDING                    , 62  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_PIB_IFETCH_PENDING );
+REG64_FLD( PU_GPE3_MIB_XISIB_PIB_DATAOP_PENDING                    , 63  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_RO  , SH_FLD_PIB_DATAOP_PENDING );
+
+REG64_FLD( PU_GPE0_MIB_XISIB_PIB_ADDR                              , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_PIB_ADDR   );
+REG64_FLD( PU_GPE0_MIB_XISIB_PIB_ADDR_LEN                          , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_PIB_ADDR_LEN );
+REG64_FLD( PU_GPE0_MIB_XISIB_PIB_R_NW                              , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_PIB_R_NW   );
+REG64_FLD( PU_GPE0_MIB_XISIB_PIB_BUSY                              , 33  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_PIB_BUSY   );
+REG64_FLD( PU_GPE0_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING           , 34  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_PIB_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_GPE0_MIB_XISIB_PIB_RSP_INFO                          , 49  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_PIB_RSP_INFO );
+REG64_FLD( PU_GPE0_MIB_XISIB_PIB_RSP_INFO_LEN                      , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_PIB_RSP_INFO_LEN );
+REG64_FLD( PU_GPE0_MIB_XISIB_PIB_IFETCH_PENDING                    , 62  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_PIB_IFETCH_PENDING );
+REG64_FLD( PU_GPE0_MIB_XISIB_PIB_DATAOP_PENDING                    , 63  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_RO  , SH_FLD_PIB_DATAOP_PENDING );
+
+REG64_FLD( PEC_STACK2_MMIOBAR0_MASK_REG_PE_MMIO_MASK0              , 0   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM     , SH_FLD_PE_MMIO_MASK0 );
+REG64_FLD( PEC_STACK2_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN          , 40  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM     , SH_FLD_PE_MMIO_MASK0_LEN );
+
+REG64_FLD( PEC_STACK1_MMIOBAR0_MASK_REG_PE_MMIO_MASK0              , 0   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM     , SH_FLD_PE_MMIO_MASK0 );
+REG64_FLD( PEC_STACK1_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN          , 40  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM     , SH_FLD_PE_MMIO_MASK0_LEN );
+
+REG64_FLD( PEC_STACK0_MMIOBAR0_MASK_REG_PE_MMIO_MASK0              , 0   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM     , SH_FLD_PE_MMIO_MASK0 );
+REG64_FLD( PEC_STACK0_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN          , 40  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM     , SH_FLD_PE_MMIO_MASK0_LEN );
+
+REG64_FLD( PEC_STACK2_MMIOBAR0_REG_PE_MMIO_BAR0                    , 0   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM     , SH_FLD_PE_MMIO_BAR0 );
+REG64_FLD( PEC_STACK2_MMIOBAR0_REG_PE_MMIO_BAR0_LEN                , 40  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM     , SH_FLD_PE_MMIO_BAR0_LEN );
+
+REG64_FLD( PEC_STACK1_MMIOBAR0_REG_PE_MMIO_BAR0                    , 0   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM     , SH_FLD_PE_MMIO_BAR0 );
+REG64_FLD( PEC_STACK1_MMIOBAR0_REG_PE_MMIO_BAR0_LEN                , 40  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM     , SH_FLD_PE_MMIO_BAR0_LEN );
+
+REG64_FLD( PEC_STACK0_MMIOBAR0_REG_PE_MMIO_BAR0                    , 0   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM     , SH_FLD_PE_MMIO_BAR0 );
+REG64_FLD( PEC_STACK0_MMIOBAR0_REG_PE_MMIO_BAR0_LEN                , 40  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM     , SH_FLD_PE_MMIO_BAR0_LEN );
+
+REG64_FLD( PEC_STACK2_MMIOBAR1_MASK_REG_PE_MMIO_MASK1              , 0   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM     , SH_FLD_PE_MMIO_MASK1 );
+REG64_FLD( PEC_STACK2_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN          , 40  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM     , SH_FLD_PE_MMIO_MASK1_LEN );
+
+REG64_FLD( PEC_STACK1_MMIOBAR1_MASK_REG_PE_MMIO_MASK1              , 0   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM     , SH_FLD_PE_MMIO_MASK1 );
+REG64_FLD( PEC_STACK1_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN          , 40  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM     , SH_FLD_PE_MMIO_MASK1_LEN );
+
+REG64_FLD( PEC_STACK0_MMIOBAR1_MASK_REG_PE_MMIO_MASK1              , 0   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM     , SH_FLD_PE_MMIO_MASK1 );
+REG64_FLD( PEC_STACK0_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN          , 40  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM     , SH_FLD_PE_MMIO_MASK1_LEN );
+
+REG64_FLD( PEC_STACK2_MMIOBAR1_REG_PE_MMIO_BAR1                    , 0   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM     , SH_FLD_PE_MMIO_BAR1 );
+REG64_FLD( PEC_STACK2_MMIOBAR1_REG_PE_MMIO_BAR1_LEN                , 40  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM     , SH_FLD_PE_MMIO_BAR1_LEN );
+
+REG64_FLD( PEC_STACK1_MMIOBAR1_REG_PE_MMIO_BAR1                    , 0   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM     , SH_FLD_PE_MMIO_BAR1 );
+REG64_FLD( PEC_STACK1_MMIOBAR1_REG_PE_MMIO_BAR1_LEN                , 40  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM     , SH_FLD_PE_MMIO_BAR1_LEN );
+
+REG64_FLD( PEC_STACK0_MMIOBAR1_REG_PE_MMIO_BAR1                    , 0   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM     , SH_FLD_PE_MMIO_BAR1 );
+REG64_FLD( PEC_STACK0_MMIOBAR1_REG_PE_MMIO_BAR1_LEN                , 40  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM     , SH_FLD_PE_MMIO_BAR1_LEN );
+
+REG64_FLD( PU_MM_CFG_NMMU_CTL_MISC_BKINV_INTERLOCK_DIS             , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BKINV_INTERLOCK_DIS );
+REG64_FLD( PU_MM_CFG_NMMU_CTL_MISC_LFSR_DIS                        , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LFSR_DIS   );
+REG64_FLD( PU_MM_CFG_NMMU_CTL_MISC_FBC_LFSR_DIS                    , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_LFSR_DIS );
+
+REG64_FLD( PU_MM_CFG_NMMU_CTL_SLB_MBR_DIS                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MBR_DIS    );
+REG64_FLD( PU_MM_CFG_NMMU_CTL_SLB_MBR_DIS_LEN                      , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MBR_DIS_LEN );
+REG64_FLD( PU_MM_CFG_NMMU_CTL_SLB_SNGL_THD_EN                      , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SNGL_THD_EN );
+REG64_FLD( PU_MM_CFG_NMMU_CTL_SLB_CAC_ALLOC_DIS                    , 17  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CAC_ALLOC_DIS );
+REG64_FLD( PU_MM_CFG_NMMU_CTL_SLB_DMAP_MODE_EN                     , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DMAP_MODE_EN );
+REG64_FLD( PU_MM_CFG_NMMU_CTL_SLB_ALT_SEGSZ_DIS                    , 19  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ALT_SEGSZ_DIS );
+
+REG64_FLD( PU_MM_CFG_NMMU_CTL_SM_TWSM_DIS                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TWSM_DIS   );
+REG64_FLD( PU_MM_CFG_NMMU_CTL_SM_TWSM_DIS_LEN                      , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TWSM_DIS_LEN );
+REG64_FLD( PU_MM_CFG_NMMU_CTL_SM_CKINSM_DIS                        , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CKINSM_DIS );
+REG64_FLD( PU_MM_CFG_NMMU_CTL_SM_CKINSM_DIS_LEN                    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CKINSM_DIS_LEN );
+REG64_FLD( PU_MM_CFG_NMMU_CTL_SM_INV_SINGLE_THREAD_EN              , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INV_SINGLE_THREAD_EN );
+
+REG64_FLD( PU_MM_CFG_NMMU_CTL_TLB_MBR_DIS                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MBR_DIS    );
+REG64_FLD( PU_MM_CFG_NMMU_CTL_TLB_MBR_DIS_LEN                      , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MBR_DIS_LEN );
+REG64_FLD( PU_MM_CFG_NMMU_CTL_TLB_SNGL_THD_EN                      , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SNGL_THD_EN );
+REG64_FLD( PU_MM_CFG_NMMU_CTL_TLB_CAC_ALLOC_DIS                    , 17  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CAC_ALLOC_DIS );
+REG64_FLD( PU_MM_CFG_NMMU_CTL_TLB_DMAP_MODE_EN                     , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DMAP_MODE_EN );
+REG64_FLD( PU_MM_CFG_NMMU_CTL_TLB_MPSS_DIS                         , 19  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MPSS_DIS   );
+REG64_FLD( PU_MM_CFG_NMMU_CTL_TLB_HASH_LPID_DIS                    , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HASH_LPID_DIS );
+REG64_FLD( PU_MM_CFG_NMMU_CTL_TLB_HASH_PID_DIS                     , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HASH_PID_DIS );
+
+REG64_FLD( PU_MM_CFG_NMMU_XLAT_CTL_REG0_HRMOR                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HRMOR      );
+REG64_FLD( PU_MM_CFG_NMMU_XLAT_CTL_REG0_HRMOR_LEN                  , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HRMOR_LEN  );
+
+REG64_FLD( PU_MM_CFG_NMMU_XLAT_CTL_REG1_PTCR                       , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PTCR       );
+REG64_FLD( PU_MM_CFG_NMMU_XLAT_CTL_REG1_PTCR_LEN                   , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PTCR_LEN   );
+
+REG64_FLD( PU_MM_CFG_NMMU_XLAT_CTL_REG2_SEIDBAR                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SEIDBAR    );
+REG64_FLD( PU_MM_CFG_NMMU_XLAT_CTL_REG2_SEIDBAR_LEN                , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SEIDBAR_LEN );
+
+REG64_FLD( PU_MM_NMMU_DBG_MODE_MODE                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MODE       );
+REG64_FLD( PU_MM_NMMU_DBG_MODE_MODE_LEN                            , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MODE_LEN   );
+
+REG64_FLD( PU_MM_NMMU_ERR_INJ_INJ                                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INJ        );
+REG64_FLD( PU_MM_NMMU_ERR_INJ_INJ_LEN                              , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INJ_LEN    );
+
+REG64_FLD( PU_MM_NMMU_ERR_LOG_LOG                                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LOG        );
+REG64_FLD( PU_MM_NMMU_ERR_LOG_LOG_LEN                              , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LOG_LEN    );
+
+REG64_FLD( PU_MM_NMMU_FIR_FIR                                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIR        );
+REG64_FLD( PU_MM_NMMU_FIR_FIR_LEN                                  , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIR_LEN    );
+
+REG32_FLD( PU_MODE_REGISTER_DCOMP_ENABLE                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DCOMP_ENABLE );
+REG32_FLD( PU_MODE_REGISTER_ECC_ENABLE                             , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_ENABLE );
+REG32_FLD( PU_MODE_REGISTER_PROGRAM_ENABLE                         , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PROGRAM_ENABLE );
+REG32_FLD( PU_MODE_REGISTER_ECC_CHK_DISABLE                        , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_CHK_DISABLE );
+REG32_FLD( PU_MODE_REGISTER_UNUSED_4_15                            , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED_4_15 );
+REG32_FLD( PU_MODE_REGISTER_UNUSED_4_15_LEN                        , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED_4_15_LEN );
+REG32_FLD( PU_MODE_REGISTER_CLK_RATE_SEL                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CLK_RATE_SEL );
+REG32_FLD( PU_MODE_REGISTER_CLK_RATE_SEL_LEN                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CLK_RATE_SEL_LEN );
+
+REG64_FLD( PU_MODE_REGISTER_B_BIT_RATE_DIVISOR_0                   , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BIT_RATE_DIVISOR_0 );
+REG64_FLD( PU_MODE_REGISTER_B_BIT_RATE_DIVISOR_0_LEN               , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BIT_RATE_DIVISOR_0_LEN );
+REG64_FLD( PU_MODE_REGISTER_B_PORT_NUMBER_0                        , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PORT_NUMBER_0 );
+REG64_FLD( PU_MODE_REGISTER_B_PORT_NUMBER_0_LEN                    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PORT_NUMBER_0_LEN );
+REG64_FLD( PU_MODE_REGISTER_B_CHKSW_I2C_BUSY_0                     , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CHKSW_I2C_BUSY_0 );
+REG64_FLD( PU_MODE_REGISTER_B_FGAT_0                               , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FGAT_0     );
+REG64_FLD( PU_MODE_REGISTER_B_DIAG_0                               , 29  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DIAG_0     );
+REG64_FLD( PU_MODE_REGISTER_B_PACING_ALLOW_0                       , 30  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PACING_ALLOW_0 );
+REG64_FLD( PU_MODE_REGISTER_B_WRAP_0                               , 31  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WRAP_0     );
+REG64_FLD( PU_MODE_REGISTER_B_PEEK_DATA1_0                         , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_MODE_REGISTER_B_PEEK_DATA1_0_LEN                     , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_MODE_REGISTER_B_LBUS_PARITY_ERR1_0                   , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_MODE_REGISTER_C_BIT_RATE_DIVISOR_1                   , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BIT_RATE_DIVISOR_1 );
+REG64_FLD( PU_MODE_REGISTER_C_BIT_RATE_DIVISOR_1_LEN               , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BIT_RATE_DIVISOR_1_LEN );
+REG64_FLD( PU_MODE_REGISTER_C_PORT_NUMBER_1                        , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PORT_NUMBER_1 );
+REG64_FLD( PU_MODE_REGISTER_C_PORT_NUMBER_1_LEN                    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PORT_NUMBER_1_LEN );
+REG64_FLD( PU_MODE_REGISTER_C_CHKSW_I2C_BUSY_1                     , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CHKSW_I2C_BUSY_1 );
+REG64_FLD( PU_MODE_REGISTER_C_FGAT_1                               , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FGAT_1     );
+REG64_FLD( PU_MODE_REGISTER_C_DIAG_1                               , 29  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DIAG_1     );
+REG64_FLD( PU_MODE_REGISTER_C_PACING_ALLOW_1                       , 30  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PACING_ALLOW_1 );
+REG64_FLD( PU_MODE_REGISTER_C_WRAP_1                               , 31  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WRAP_1     );
+REG64_FLD( PU_MODE_REGISTER_C_PEEK_DATA1_1                         , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_MODE_REGISTER_C_PEEK_DATA1_1_LEN                     , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_MODE_REGISTER_C_LBUS_PARITY_ERR1_1                   , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_MODE_REGISTER_D_BIT_RATE_DIVISOR_2                   , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BIT_RATE_DIVISOR_2 );
+REG64_FLD( PU_MODE_REGISTER_D_BIT_RATE_DIVISOR_2_LEN               , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BIT_RATE_DIVISOR_2_LEN );
+REG64_FLD( PU_MODE_REGISTER_D_PORT_NUMBER_2                        , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PORT_NUMBER_2 );
+REG64_FLD( PU_MODE_REGISTER_D_PORT_NUMBER_2_LEN                    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PORT_NUMBER_2_LEN );
+REG64_FLD( PU_MODE_REGISTER_D_CHKSW_I2C_BUSY_2                     , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CHKSW_I2C_BUSY_2 );
+REG64_FLD( PU_MODE_REGISTER_D_FGAT_2                               , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FGAT_2     );
+REG64_FLD( PU_MODE_REGISTER_D_DIAG_2                               , 29  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DIAG_2     );
+REG64_FLD( PU_MODE_REGISTER_D_PACING_ALLOW_2                       , 30  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PACING_ALLOW_2 );
+REG64_FLD( PU_MODE_REGISTER_D_WRAP_2                               , 31  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WRAP_2     );
+REG64_FLD( PU_MODE_REGISTER_D_PEEK_DATA1_2                         , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_MODE_REGISTER_D_PEEK_DATA1_2_LEN                     , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_MODE_REGISTER_D_LBUS_PARITY_ERR1_2                   , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_MODE_REGISTER_E_BIT_RATE_DIVISOR_3                   , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BIT_RATE_DIVISOR_3 );
+REG64_FLD( PU_MODE_REGISTER_E_BIT_RATE_DIVISOR_3_LEN               , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BIT_RATE_DIVISOR_3_LEN );
+REG64_FLD( PU_MODE_REGISTER_E_PORT_NUMBER_3                        , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PORT_NUMBER_3 );
+REG64_FLD( PU_MODE_REGISTER_E_PORT_NUMBER_3_LEN                    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PORT_NUMBER_3_LEN );
+REG64_FLD( PU_MODE_REGISTER_E_CHKSW_I2C_BUSY_3                     , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CHKSW_I2C_BUSY_3 );
+REG64_FLD( PU_MODE_REGISTER_E_FGAT_3                               , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FGAT_3     );
+REG64_FLD( PU_MODE_REGISTER_E_DIAG_3                               , 29  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DIAG_3     );
+REG64_FLD( PU_MODE_REGISTER_E_PACING_ALLOW_3                       , 30  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PACING_ALLOW_3 );
+REG64_FLD( PU_MODE_REGISTER_E_WRAP_3                               , 31  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WRAP_3     );
+REG64_FLD( PU_MODE_REGISTER_E_PEEK_DATA1_3                         , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_MODE_REGISTER_E_PEEK_DATA1_3_LEN                     , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_MODE_REGISTER_E_LBUS_PARITY_ERR1_3                   , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( PEC_STACK2_MSIBAR_REG_PE_MSI_BAR                        , 0   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM     , SH_FLD_PE_MSI_BAR );
+REG64_FLD( PEC_STACK2_MSIBAR_REG_PE_MSI_BAR_LEN                    , 32  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM     , SH_FLD_PE_MSI_BAR_LEN );
+
+REG64_FLD( PEC_STACK1_MSIBAR_REG_PE_MSI_BAR                        , 0   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM     , SH_FLD_PE_MSI_BAR );
+REG64_FLD( PEC_STACK1_MSIBAR_REG_PE_MSI_BAR_LEN                    , 32  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM     , SH_FLD_PE_MSI_BAR_LEN );
+
+REG64_FLD( PEC_STACK0_MSIBAR_REG_PE_MSI_BAR                        , 0   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM     , SH_FLD_PE_MSI_BAR );
+REG64_FLD( PEC_STACK0_MSIBAR_REG_PE_MSI_BAR_LEN                    , 32  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM     , SH_FLD_PE_MSI_BAR_LEN );
+
+REG64_FLD( PU_NPU_CTL_NDLMUX_CONFIG_BRK0TO2                        , 0   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_BRK0TO2    );
+REG64_FLD( PU_NPU_CTL_NDLMUX_CONFIG_BRK0TO2_LEN                    , 3   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_BRK0TO2_LEN );
+
+REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM0_NDT0_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM0_NDT0_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM2_NDT0_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM2_NDT0_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM3_NDT0_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM3_NDT0_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM3_NDT0_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM3_NDT0_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM3_NDT0_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM3_NDT0_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM1_NDT0_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM1_NDT0_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM2_NDT0_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM2_NDT0_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM1_NDT0_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM1_NDT0_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM2_NDT0_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM2_NDT0_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM0_NDT0_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM0_NDT0_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM1_NDT0_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM1_NDT0_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM0_NDT0_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM0_NDT0_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM0_NDT1_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM0_NDT1_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM2_NDT1_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM2_NDT1_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM3_NDT1_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM3_NDT1_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM3_NDT1_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM3_NDT1_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM3_NDT1_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM3_NDT1_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM1_NDT1_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM1_NDT1_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM2_NDT1_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM2_NDT1_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM1_NDT1_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM1_NDT1_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM2_NDT1_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM2_NDT1_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM0_NDT1_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM0_NDT1_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM1_NDT1_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM1_NDT1_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_ENABLE                      , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM0_NDT1_BAR_RESERVED1                          , 1   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_ADDR                        , 2   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM0_NDT1_BAR_RESERVED2                          , 27  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PEC_NESTTRC_REG_PE_ENABLENESTTRACE                      , 0   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_ENABLENESTTRACE );
+REG64_FLD( PEC_NESTTRC_REG_PE_NESTTRACESEL                         , 1   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_NESTTRACESEL );
+REG64_FLD( PEC_NESTTRC_REG_PE_NESTTRACESEL_LEN                     , 3   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_NESTTRACESEL_LEN );
+
+REG64_FLD( PEC_STACK2_NFIRACTION0_REG_NFIRACTION0                  , 0   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  , SH_FLD_NFIRACTION0 );
+REG64_FLD( PEC_STACK2_NFIRACTION0_REG_NFIRACTION0_LEN              , 30  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  , SH_FLD_NFIRACTION0_LEN );
+
+REG64_FLD( PEC_STACK1_NFIRACTION0_REG_NFIRACTION0                  , 0   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  , SH_FLD_NFIRACTION0 );
+REG64_FLD( PEC_STACK1_NFIRACTION0_REG_NFIRACTION0_LEN              , 30  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  , SH_FLD_NFIRACTION0_LEN );
+
+REG64_FLD( PEC_STACK0_NFIRACTION0_REG_NFIRACTION0                  , 0   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  , SH_FLD_NFIRACTION0 );
+REG64_FLD( PEC_STACK0_NFIRACTION0_REG_NFIRACTION0_LEN              , 30  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  , SH_FLD_NFIRACTION0_LEN );
+
+REG64_FLD( PEC_STACK2_NFIRACTION1_REG_NFIRACTION1                  , 0   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  , SH_FLD_NFIRACTION1 );
+REG64_FLD( PEC_STACK2_NFIRACTION1_REG_NFIRACTION1_LEN              , 30  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  , SH_FLD_NFIRACTION1_LEN );
+
+REG64_FLD( PEC_STACK1_NFIRACTION1_REG_NFIRACTION1                  , 0   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  , SH_FLD_NFIRACTION1 );
+REG64_FLD( PEC_STACK1_NFIRACTION1_REG_NFIRACTION1_LEN              , 30  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  , SH_FLD_NFIRACTION1_LEN );
+
+REG64_FLD( PEC_STACK0_NFIRACTION1_REG_NFIRACTION1                  , 0   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  , SH_FLD_NFIRACTION1 );
+REG64_FLD( PEC_STACK0_NFIRACTION1_REG_NFIRACTION1_LEN              , 30  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  , SH_FLD_NFIRACTION1_LEN );
+
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_BAR_PE_MASK                     , 0   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_BAR_PE_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_NONBAR_PE_MASK                  , 1   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_NONBAR_PE_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_TO_PEC_CE_MASK               , 2   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PB_TO_PEC_CE_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_TO_PEC_UE_MASK               , 3   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PB_TO_PEC_UE_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_TO_PEC_SUE_MASK              , 4   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PB_TO_PEC_SUE_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_ARY_ECC_CE_MASK                 , 5   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_ARY_ECC_CE_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_ARY_ECC_UE_MASK                 , 6   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_ARY_ECC_UE_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_ARY_ECC_SUE_MASK                , 7   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_ARY_ECC_SUE_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_REGISTER_ARRAY_PE_MASK          , 8   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_REGISTER_ARRAY_PE_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_INTERFACE_PE_MASK            , 9   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PB_INTERFACE_PE_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_DATA_HANG_ERRORS_MASK        , 10  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PB_DATA_HANG_ERRORS_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_HANG_ERRORS_MASK             , 11  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PB_HANG_ERRORS_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_RD_ARE_ERRORS_MASK              , 12  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_RD_ARE_ERRORS_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_NONRD_ARE_ERRORS_MASK           , 13  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_NONRD_ARE_ERRORS_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_PCI_HANG_ERROR_MASK             , 14  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PCI_HANG_ERROR_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_PCI_CLOCK_ERROR_MASK            , 15  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PCI_CLOCK_ERROR_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_AIB_FENCE_MASK                  , 16  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_AIB_FENCE_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_HW_ERRORS_MASK                  , 17  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_HW_ERRORS_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_UNSOLICITIEDPBDATA_MASK         , 18  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_UNSOLICITIEDPBDATA_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_UNEXPECTEDCRESP_MASK            , 19  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_UNEXPECTEDCRESP_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_INVALIDCRESP_MASK               , 20  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_INVALIDCRESP_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_PBUNSUPPORTEDSIZE_MASK          , 21  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PBUNSUPPORTEDSIZE_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_PBUNSUPPORTEDCMD_MASK           , 22  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PBUNSUPPORTEDCMD_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_AIB_PE_MASK                     , 23  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_AIB_PE_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_CAPP_ERROR_MASK                 , 24  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_CAPP_ERROR_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_PEC_SCOM_ERR_MASK               , 27  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PEC_SCOM_ERR_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_STACK_SCOM_ERR0_MASK            , 28  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_STACK_SCOM_ERR0_MASK );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_STACK_SCOM_ERR1_MASK            , 29  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_STACK_SCOM_ERR1_MASK );
+
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_BAR_PE_MASK                     , 0   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_BAR_PE_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_NONBAR_PE_MASK                  , 1   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_NONBAR_PE_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_TO_PEC_CE_MASK               , 2   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PB_TO_PEC_CE_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_TO_PEC_UE_MASK               , 3   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PB_TO_PEC_UE_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_TO_PEC_SUE_MASK              , 4   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PB_TO_PEC_SUE_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_ARY_ECC_CE_MASK                 , 5   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_ARY_ECC_CE_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_ARY_ECC_UE_MASK                 , 6   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_ARY_ECC_UE_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_ARY_ECC_SUE_MASK                , 7   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_ARY_ECC_SUE_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_REGISTER_ARRAY_PE_MASK          , 8   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_REGISTER_ARRAY_PE_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_INTERFACE_PE_MASK            , 9   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PB_INTERFACE_PE_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_DATA_HANG_ERRORS_MASK        , 10  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PB_DATA_HANG_ERRORS_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_HANG_ERRORS_MASK             , 11  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PB_HANG_ERRORS_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_RD_ARE_ERRORS_MASK              , 12  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_RD_ARE_ERRORS_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_NONRD_ARE_ERRORS_MASK           , 13  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_NONRD_ARE_ERRORS_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_PCI_HANG_ERROR_MASK             , 14  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PCI_HANG_ERROR_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_PCI_CLOCK_ERROR_MASK            , 15  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PCI_CLOCK_ERROR_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_AIB_FENCE_MASK                  , 16  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_AIB_FENCE_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_HW_ERRORS_MASK                  , 17  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_HW_ERRORS_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_UNSOLICITIEDPBDATA_MASK         , 18  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_UNSOLICITIEDPBDATA_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_UNEXPECTEDCRESP_MASK            , 19  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_UNEXPECTEDCRESP_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_INVALIDCRESP_MASK               , 20  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_INVALIDCRESP_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_PBUNSUPPORTEDSIZE_MASK          , 21  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PBUNSUPPORTEDSIZE_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_PBUNSUPPORTEDCMD_MASK           , 22  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PBUNSUPPORTEDCMD_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_AIB_PE_MASK                     , 23  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_AIB_PE_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_CAPP_ERROR_MASK                 , 24  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_CAPP_ERROR_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_PEC_SCOM_ERR_MASK               , 27  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PEC_SCOM_ERR_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_STACK_SCOM_ERR0_MASK            , 28  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_STACK_SCOM_ERR0_MASK );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_STACK_SCOM_ERR1_MASK            , 29  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_STACK_SCOM_ERR1_MASK );
+
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_BAR_PE_MASK                     , 0   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_BAR_PE_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_NONBAR_PE_MASK                  , 1   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_NONBAR_PE_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_TO_PEC_CE_MASK               , 2   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_PB_TO_PEC_CE_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_TO_PEC_UE_MASK               , 3   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_PB_TO_PEC_UE_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_TO_PEC_SUE_MASK              , 4   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_PB_TO_PEC_SUE_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_ARY_ECC_CE_MASK                 , 5   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_ARY_ECC_CE_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_ARY_ECC_UE_MASK                 , 6   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_ARY_ECC_UE_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_ARY_ECC_SUE_MASK                , 7   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_ARY_ECC_SUE_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_REGISTER_ARRAY_PE_MASK          , 8   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_REGISTER_ARRAY_PE_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_INTERFACE_PE_MASK            , 9   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_PB_INTERFACE_PE_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_DATA_HANG_ERRORS_MASK        , 10  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_PB_DATA_HANG_ERRORS_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_HANG_ERRORS_MASK             , 11  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_PB_HANG_ERRORS_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_RD_ARE_ERRORS_MASK              , 12  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_RD_ARE_ERRORS_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_NONRD_ARE_ERRORS_MASK           , 13  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_NONRD_ARE_ERRORS_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_PCI_HANG_ERROR_MASK             , 14  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_PCI_HANG_ERROR_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_PCI_CLOCK_ERROR_MASK            , 15  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_PCI_CLOCK_ERROR_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_AIB_FENCE_MASK                  , 16  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_AIB_FENCE_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_HW_ERRORS_MASK                  , 17  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_HW_ERRORS_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_UNSOLICITIEDPBDATA_MASK         , 18  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_UNSOLICITIEDPBDATA_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_UNEXPECTEDCRESP_MASK            , 19  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_UNEXPECTEDCRESP_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_INVALIDCRESP_MASK               , 20  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_INVALIDCRESP_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_PBUNSUPPORTEDSIZE_MASK          , 21  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_PBUNSUPPORTEDSIZE_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_PBUNSUPPORTEDCMD_MASK           , 22  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_PBUNSUPPORTEDCMD_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_AIB_PE_MASK                     , 23  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_AIB_PE_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_CAPP_ERROR_MASK                 , 24  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_CAPP_ERROR_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_PEC_SCOM_ERR_MASK               , 27  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_PEC_SCOM_ERR_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_STACK_SCOM_ERR0_MASK            , 28  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_STACK_SCOM_ERR0_MASK );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_STACK_SCOM_ERR1_MASK            , 29  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_STACK_SCOM_ERR1_MASK );
+
+REG64_FLD( PEC_STACK2_NFIR_REG_BAR_PE                              , 0   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_BAR_PE     );
+REG64_FLD( PEC_STACK2_NFIR_REG_NONBAR_PE                           , 1   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_NONBAR_PE  );
+REG64_FLD( PEC_STACK2_NFIR_REG_PB_TO_PEC_CE                        , 2   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PB_TO_PEC_CE );
+REG64_FLD( PEC_STACK2_NFIR_REG_PB_TO_PEC_UE                        , 3   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PB_TO_PEC_UE );
+REG64_FLD( PEC_STACK2_NFIR_REG_PB_TO_PEC_SUE                       , 4   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PB_TO_PEC_SUE );
+REG64_FLD( PEC_STACK2_NFIR_REG_ARY_ECC_CE                          , 5   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_ARY_ECC_CE );
+REG64_FLD( PEC_STACK2_NFIR_REG_ARY_ECC_UE                          , 6   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_ARY_ECC_UE );
+REG64_FLD( PEC_STACK2_NFIR_REG_ARY_ECC_SUE                         , 7   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_ARY_ECC_SUE );
+REG64_FLD( PEC_STACK2_NFIR_REG_REGISTER_ARRAY_PE                   , 8   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_REGISTER_ARRAY_PE );
+REG64_FLD( PEC_STACK2_NFIR_REG_PB_INTERFACE_PE                     , 9   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PB_INTERFACE_PE );
+REG64_FLD( PEC_STACK2_NFIR_REG_PB_DATA_HANG_ERRORS                 , 10  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PB_DATA_HANG_ERRORS );
+REG64_FLD( PEC_STACK2_NFIR_REG_PB_HANG_ERRORS                      , 11  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PB_HANG_ERRORS );
+REG64_FLD( PEC_STACK2_NFIR_REG_RD_ARE_ERRORS                       , 12  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_RD_ARE_ERRORS );
+REG64_FLD( PEC_STACK2_NFIR_REG_NONRD_ARE_ERRORS                    , 13  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_NONRD_ARE_ERRORS );
+REG64_FLD( PEC_STACK2_NFIR_REG_PCI_HANG_ERROR                      , 14  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PCI_HANG_ERROR );
+REG64_FLD( PEC_STACK2_NFIR_REG_PCI_CLOCK_ERROR                     , 15  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PCI_CLOCK_ERROR );
+REG64_FLD( PEC_STACK2_NFIR_REG_AIB_FENCE                           , 16  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_AIB_FENCE  );
+REG64_FLD( PEC_STACK2_NFIR_REG_HW_ERRORS                           , 17  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_HW_ERRORS  );
+REG64_FLD( PEC_STACK2_NFIR_REG_UNSOLICITIEDPBDATA                  , 18  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_UNSOLICITIEDPBDATA );
+REG64_FLD( PEC_STACK2_NFIR_REG_UNEXPECTEDCRESP                     , 19  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_UNEXPECTEDCRESP );
+REG64_FLD( PEC_STACK2_NFIR_REG_INVALIDCRESP                        , 20  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_INVALIDCRESP );
+REG64_FLD( PEC_STACK2_NFIR_REG_PBUNSUPPORTEDSIZE                   , 21  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PBUNSUPPORTEDSIZE );
+REG64_FLD( PEC_STACK2_NFIR_REG_PBUNSUPPORTEDCMD                    , 22  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PBUNSUPPORTEDCMD );
+REG64_FLD( PEC_STACK2_NFIR_REG_AIB_PE                              , 23  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_AIB_PE     );
+REG64_FLD( PEC_STACK2_NFIR_REG_CAPP_ERROR                          , 24  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_CAPP_ERROR );
+REG64_FLD( PEC_STACK2_NFIR_REG_PEC_SCOM_ERR                        , 27  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PEC_SCOM_ERR );
+REG64_FLD( PEC_STACK2_NFIR_REG_STACK_SCOM_ERR0                     , 28  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_STACK_SCOM_ERR0 );
+REG64_FLD( PEC_STACK2_NFIR_REG_STACK_SCOM_ERR1                     , 29  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_STACK_SCOM_ERR1 );
+
+REG64_FLD( PEC_STACK1_NFIR_REG_BAR_PE                              , 0   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_BAR_PE     );
+REG64_FLD( PEC_STACK1_NFIR_REG_NONBAR_PE                           , 1   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_NONBAR_PE  );
+REG64_FLD( PEC_STACK1_NFIR_REG_PB_TO_PEC_CE                        , 2   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PB_TO_PEC_CE );
+REG64_FLD( PEC_STACK1_NFIR_REG_PB_TO_PEC_UE                        , 3   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PB_TO_PEC_UE );
+REG64_FLD( PEC_STACK1_NFIR_REG_PB_TO_PEC_SUE                       , 4   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PB_TO_PEC_SUE );
+REG64_FLD( PEC_STACK1_NFIR_REG_ARY_ECC_CE                          , 5   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_ARY_ECC_CE );
+REG64_FLD( PEC_STACK1_NFIR_REG_ARY_ECC_UE                          , 6   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_ARY_ECC_UE );
+REG64_FLD( PEC_STACK1_NFIR_REG_ARY_ECC_SUE                         , 7   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_ARY_ECC_SUE );
+REG64_FLD( PEC_STACK1_NFIR_REG_REGISTER_ARRAY_PE                   , 8   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_REGISTER_ARRAY_PE );
+REG64_FLD( PEC_STACK1_NFIR_REG_PB_INTERFACE_PE                     , 9   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PB_INTERFACE_PE );
+REG64_FLD( PEC_STACK1_NFIR_REG_PB_DATA_HANG_ERRORS                 , 10  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PB_DATA_HANG_ERRORS );
+REG64_FLD( PEC_STACK1_NFIR_REG_PB_HANG_ERRORS                      , 11  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PB_HANG_ERRORS );
+REG64_FLD( PEC_STACK1_NFIR_REG_RD_ARE_ERRORS                       , 12  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_RD_ARE_ERRORS );
+REG64_FLD( PEC_STACK1_NFIR_REG_NONRD_ARE_ERRORS                    , 13  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_NONRD_ARE_ERRORS );
+REG64_FLD( PEC_STACK1_NFIR_REG_PCI_HANG_ERROR                      , 14  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PCI_HANG_ERROR );
+REG64_FLD( PEC_STACK1_NFIR_REG_PCI_CLOCK_ERROR                     , 15  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PCI_CLOCK_ERROR );
+REG64_FLD( PEC_STACK1_NFIR_REG_AIB_FENCE                           , 16  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_AIB_FENCE  );
+REG64_FLD( PEC_STACK1_NFIR_REG_HW_ERRORS                           , 17  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_HW_ERRORS  );
+REG64_FLD( PEC_STACK1_NFIR_REG_UNSOLICITIEDPBDATA                  , 18  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_UNSOLICITIEDPBDATA );
+REG64_FLD( PEC_STACK1_NFIR_REG_UNEXPECTEDCRESP                     , 19  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_UNEXPECTEDCRESP );
+REG64_FLD( PEC_STACK1_NFIR_REG_INVALIDCRESP                        , 20  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_INVALIDCRESP );
+REG64_FLD( PEC_STACK1_NFIR_REG_PBUNSUPPORTEDSIZE                   , 21  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PBUNSUPPORTEDSIZE );
+REG64_FLD( PEC_STACK1_NFIR_REG_PBUNSUPPORTEDCMD                    , 22  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PBUNSUPPORTEDCMD );
+REG64_FLD( PEC_STACK1_NFIR_REG_AIB_PE                              , 23  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_AIB_PE     );
+REG64_FLD( PEC_STACK1_NFIR_REG_CAPP_ERROR                          , 24  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_CAPP_ERROR );
+REG64_FLD( PEC_STACK1_NFIR_REG_PEC_SCOM_ERR                        , 27  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PEC_SCOM_ERR );
+REG64_FLD( PEC_STACK1_NFIR_REG_STACK_SCOM_ERR0                     , 28  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_STACK_SCOM_ERR0 );
+REG64_FLD( PEC_STACK1_NFIR_REG_STACK_SCOM_ERR1                     , 29  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_STACK_SCOM_ERR1 );
+
+REG64_FLD( PEC_STACK0_NFIR_REG_BAR_PE                              , 0   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_BAR_PE     );
+REG64_FLD( PEC_STACK0_NFIR_REG_NONBAR_PE                           , 1   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_NONBAR_PE  );
+REG64_FLD( PEC_STACK0_NFIR_REG_PB_TO_PEC_CE                        , 2   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_PB_TO_PEC_CE );
+REG64_FLD( PEC_STACK0_NFIR_REG_PB_TO_PEC_UE                        , 3   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_PB_TO_PEC_UE );
+REG64_FLD( PEC_STACK0_NFIR_REG_PB_TO_PEC_SUE                       , 4   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_PB_TO_PEC_SUE );
+REG64_FLD( PEC_STACK0_NFIR_REG_ARY_ECC_CE                          , 5   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_ARY_ECC_CE );
+REG64_FLD( PEC_STACK0_NFIR_REG_ARY_ECC_UE                          , 6   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_ARY_ECC_UE );
+REG64_FLD( PEC_STACK0_NFIR_REG_ARY_ECC_SUE                         , 7   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_ARY_ECC_SUE );
+REG64_FLD( PEC_STACK0_NFIR_REG_REGISTER_ARRAY_PE                   , 8   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_REGISTER_ARRAY_PE );
+REG64_FLD( PEC_STACK0_NFIR_REG_PB_INTERFACE_PE                     , 9   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_PB_INTERFACE_PE );
+REG64_FLD( PEC_STACK0_NFIR_REG_PB_DATA_HANG_ERRORS                 , 10  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_PB_DATA_HANG_ERRORS );
+REG64_FLD( PEC_STACK0_NFIR_REG_PB_HANG_ERRORS                      , 11  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_PB_HANG_ERRORS );
+REG64_FLD( PEC_STACK0_NFIR_REG_RD_ARE_ERRORS                       , 12  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_RD_ARE_ERRORS );
+REG64_FLD( PEC_STACK0_NFIR_REG_NONRD_ARE_ERRORS                    , 13  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_NONRD_ARE_ERRORS );
+REG64_FLD( PEC_STACK0_NFIR_REG_PCI_HANG_ERROR                      , 14  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_PCI_HANG_ERROR );
+REG64_FLD( PEC_STACK0_NFIR_REG_PCI_CLOCK_ERROR                     , 15  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_PCI_CLOCK_ERROR );
+REG64_FLD( PEC_STACK0_NFIR_REG_AIB_FENCE                           , 16  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_AIB_FENCE  );
+REG64_FLD( PEC_STACK0_NFIR_REG_HW_ERRORS                           , 17  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_HW_ERRORS  );
+REG64_FLD( PEC_STACK0_NFIR_REG_UNSOLICITIEDPBDATA                  , 18  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_UNSOLICITIEDPBDATA );
+REG64_FLD( PEC_STACK0_NFIR_REG_UNEXPECTEDCRESP                     , 19  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_UNEXPECTEDCRESP );
+REG64_FLD( PEC_STACK0_NFIR_REG_INVALIDCRESP                        , 20  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_INVALIDCRESP );
+REG64_FLD( PEC_STACK0_NFIR_REG_PBUNSUPPORTEDSIZE                   , 21  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_PBUNSUPPORTEDSIZE );
+REG64_FLD( PEC_STACK0_NFIR_REG_PBUNSUPPORTEDCMD                    , 22  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_PBUNSUPPORTEDCMD );
+REG64_FLD( PEC_STACK0_NFIR_REG_AIB_PE                              , 23  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_AIB_PE     );
+REG64_FLD( PEC_STACK0_NFIR_REG_CAPP_ERROR                          , 24  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_CAPP_ERROR );
+REG64_FLD( PEC_STACK0_NFIR_REG_PEC_SCOM_ERR                        , 27  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_PEC_SCOM_ERR );
+REG64_FLD( PEC_STACK0_NFIR_REG_STACK_SCOM_ERR0                     , 28  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_STACK_SCOM_ERR0 );
+REG64_FLD( PEC_STACK0_NFIR_REG_STACK_SCOM_ERR1                     , 29  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_STACK_SCOM_ERR1 );
+
+REG64_FLD( PU_NOTRUST_BAR0_UNTRUSTED                               , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNTRUSTED  );
+REG64_FLD( PU_NOTRUST_BAR0_UNTRUSTED_LEN                           , 30  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNTRUSTED_LEN );
+
+REG64_FLD( PU_NOTRUST_BAR0MASK_UNTRUSTED                           , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNTRUSTED  );
+REG64_FLD( PU_NOTRUST_BAR0MASK_UNTRUSTED_LEN                       , 30  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNTRUSTED_LEN );
+
+REG64_FLD( PU_NOTRUST_BAR1_UNTRUSTED                               , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNTRUSTED  );
+REG64_FLD( PU_NOTRUST_BAR1_UNTRUSTED_LEN                           , 30  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNTRUSTED_LEN );
+
+REG64_FLD( PU_NOTRUST_BAR1MASK_UNTRUSTED                           , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNTRUSTED  );
+REG64_FLD( PU_NOTRUST_BAR1MASK_UNTRUSTED_LEN                       , 30  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNTRUSTED_LEN );
+
+REG64_FLD( PU_NPU_SM0_NPU_AT_ECC_INJECT_MODE                       , 0   ,
+           SH_UNT_PU_NPU_SM0, SH_ACS_SCOM     , SH_FLD_INJECT_MODE );
+REG64_FLD( PU_NPU_SM0_NPU_AT_ECC_INJECT_MODE_LEN                   , 2   ,
+           SH_UNT_PU_NPU_SM0, SH_ACS_SCOM     , SH_FLD_INJECT_MODE_LEN );
+REG64_FLD( PU_NPU_SM0_NPU_AT_ECC_INJECT_TYPE                       , 2   ,
+           SH_UNT_PU_NPU_SM0, SH_ACS_SCOM     , SH_FLD_INJECT_TYPE );
+REG64_FLD( PU_NPU_SM0_NPU_AT_ECC_INJECT_TYPE_LEN                   , 2   ,
+           SH_UNT_PU_NPU_SM0, SH_ACS_SCOM     , SH_FLD_INJECT_TYPE_LEN );
+REG64_FLD( PU_NPU_SM0_NPU_AT_ECC_INJECT_ENABLE                     , 4   ,
+           SH_UNT_PU_NPU_SM0, SH_ACS_SCOM     , SH_FLD_INJECT_ENABLE );
+REG64_FLD( PU_NPU_SM0_NPU_AT_ECC_ARRAY_SELECT                      , 5   ,
+           SH_UNT_PU_NPU_SM0, SH_ACS_SCOM     , SH_FLD_ARRAY_SELECT );
+REG64_FLD( PU_NPU_SM0_NPU_AT_ECC_ARRAY_SELECT_LEN                  , 4   ,
+           SH_UNT_PU_NPU_SM0, SH_ACS_SCOM     , SH_FLD_ARRAY_SELECT_LEN );
+
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_LN                   , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DMA_WR_DISABLE_LN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_GROUP                , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DMA_WR_DISABLE_GROUP );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_VG_NOT_SYS           , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DMA_WR_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_NN_RN                , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DMA_WR_DISABLE_NN_RN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_RD_DISABLE_LN                   , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DMA_RD_DISABLE_LN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_RD_DISABLE_GROUP                , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DMA_RD_DISABLE_GROUP );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_RD_DISABLE_VG_NOT_SYS           , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DMA_RD_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_RD_DISABLE_NN_RN                , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DMA_RD_DISABLE_NN_RN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_WR_DISABLE_LN                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UMAC_WR_DISABLE_LN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_WR_DISABLE_GROUP               , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UMAC_WR_DISABLE_GROUP );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_WR_DISABLE_VG_NOT_SYS          , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UMAC_WR_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_WR_DISABLE_NN_RN               , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UMAC_WR_DISABLE_NN_RN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_RD_DISABLE_LN                  , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UMAC_RD_DISABLE_LN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_RD_DISABLE_GROUP               , 13  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UMAC_RD_DISABLE_GROUP );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_RD_DISABLE_VG_NOT_SYS          , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UMAC_RD_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_RD_DISABLE_NN_RN               , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UMAC_RD_DISABLE_NN_RN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_NX_FREEZE_MODES                     , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NX_FREEZE_MODES );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_NX_FREEZE_MODES_LEN                 , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NX_FREEZE_MODES_LEN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_RESERVED                            , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_RESERVED_LEN                        , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_NOT_INJECT                   , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DMA_WR_NOT_INJECT );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_PARTIAL_WRT_NOT_INJECT          , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DMA_PARTIAL_WRT_NOT_INJECT );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_RD_GO_M_QOS                         , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RD_GO_M_QOS );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_ADDR_BAR                            , 23  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADDR_BAR   );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_SKIP_G                              , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SKIP_G     );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DATA_ARB_LFSR_CONFIG                , 25  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DATA_ARB_LFSR_CONFIG );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DATA_ARB_LFSR_CONFIG_LEN            , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DATA_ARB_LFSR_CONFIG_LEN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_HANG_SM_ON_ARE                      , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HANG_SM_ON_ARE );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_HANG_SM_ON_LINK_FAIL                , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HANG_SM_ON_LINK_FAIL );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_CFG_PUMP                            , 29  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CFG_PUMP   );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DISABLE_FLOW_SCOPE                  , 30  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_FLOW_SCOPE );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DISABLE_PMU_SNOOPING                , 31  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_PMU_SNOOPING );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_ENDABLE_PMU_CNT_RESET               , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENDABLE_PMU_CNT_RESET );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DISABLE_WRP                         , 33  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_WRP );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_UNUSED                              , 34  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED     );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_UNUSED_LEN                          , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED_LEN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_RD_VG_RESET_TIMER_MASK          , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DMA_RD_VG_RESET_TIMER_MASK );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_RD_VG_RESET_TIMER_MASK_LEN      , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DMA_RD_VG_RESET_TIMER_MASK_LEN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_VG_RESET_TIMER_MASK          , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DMA_WR_VG_RESET_TIMER_MASK );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_VG_RESET_TIMER_MASK_LEN      , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DMA_WR_VG_RESET_TIMER_MASK_LEN );
+
+REG64_FLD( PU_NX_AS_CMD_CFG_STC_MAX_Q_DEPTH                        , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STC_MAX_Q_DEPTH );
+REG64_FLD( PU_NX_AS_CMD_CFG_STC_MAX_Q_DEPTH_LEN                    , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STC_MAX_Q_DEPTH_LEN );
+REG64_FLD( PU_NX_AS_CMD_CFG_ST_MAX_Q_DEPTH                         , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ST_MAX_Q_DEPTH );
+REG64_FLD( PU_NX_AS_CMD_CFG_ST_MAX_Q_DEPTH_LEN                     , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ST_MAX_Q_DEPTH_LEN );
+REG64_FLD( PU_NX_AS_CMD_CFG_INT_MAX_Q_DEPTH                        , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INT_MAX_Q_DEPTH );
+REG64_FLD( PU_NX_AS_CMD_CFG_INT_MAX_Q_DEPTH_LEN                    , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INT_MAX_Q_DEPTH_LEN );
+
+REG64_FLD( PU_NX_COP_CFG_SYM_MAX_Q_DEPTH                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SYM_MAX_Q_DEPTH );
+REG64_FLD( PU_NX_COP_CFG_SYM_MAX_Q_DEPTH_LEN                       , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SYM_MAX_Q_DEPTH_LEN );
+REG64_FLD( PU_NX_COP_CFG_AMF_MAX_Q_DEPTH                           , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_AMF_MAX_Q_DEPTH );
+REG64_FLD( PU_NX_COP_CFG_AMF_MAX_Q_DEPTH_LEN                       , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_AMF_MAX_Q_DEPTH_LEN );
+
+REG64_FLD( PU_NX_CQ_FIR_ACTION0_REG_ACTION0                        , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACTION0    );
+REG64_FLD( PU_NX_CQ_FIR_ACTION0_REG_ACTION0_LEN                    , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_NX_CQ_FIR_ACTION1_REG_ACTION1                        , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACTION1    );
+REG64_FLD( PU_NX_CQ_FIR_ACTION1_REG_ACTION1_LEN                    , 19  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_NX_CQ_FIR_MASK_REG_MASK                              , 0   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MASK       );
+REG64_FLD( PU_NX_CQ_FIR_MASK_REG_MASK_LEN                          , 20  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MASK_LEN   );
+
+REG64_FLD( PU_NX_CQ_FIR_REG_PBI_PE                                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PBI_PE     );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_ECC_CE                            , 1   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PBUS_ECC_CE );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_ECC_UE                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PBUS_ECC_UE );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_ECC_SUE                           , 3   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PBUS_ECC_SUE );
+REG64_FLD( PU_NX_CQ_FIR_REG_INBD_ARRAY_ECC_CE                      , 4   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INBD_ARRAY_ECC_CE );
+REG64_FLD( PU_NX_CQ_FIR_REG_INBD_ARRAY_ECC_UE                      , 5   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INBD_ARRAY_ECC_UE );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_DATA_HANG                         , 6   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PBUS_DATA_HANG );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_CMD_HANG                          , 7   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PBUS_CMD_HANG );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_READ_ARE                          , 8   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PBUS_READ_ARE );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_WRITE_ARE                         , 9   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PBUS_WRITE_ARE );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_MISC_HW                           , 10  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PBUS_MISC_HW );
+REG64_FLD( PU_NX_CQ_FIR_REG_MMIO_BAR_PE                            , 11  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MMIO_BAR_PE );
+REG64_FLD( PU_NX_CQ_FIR_REG_CRBKILL_WITH_ISN_UE                    , 12  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CRBKILL_WITH_ISN_UE );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_LOAD_LINK_ERR                     , 13  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PBUS_LOAD_LINK_ERR );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_STORE_LINK_ERR                    , 14  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PBUS_STORE_LINK_ERR );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_LINK_ABORT                        , 15  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PBUS_LINK_ABORT );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBI_INTERNAL_HANG                      , 16  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PBI_INTERNAL_HANG );
+REG64_FLD( PU_NX_CQ_FIR_REG_SECURE_ACCESS_VIOLATION                , 17  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_SECURE_ACCESS_VIOLATION );
+REG64_FLD( PU_NX_CQ_FIR_REG_SCOM_PE                                , 18  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PE    );
+REG64_FLD( PU_NX_CQ_FIR_REG_SCOM_PE_DUP                            , 19  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PE_DUP );
+
+REG64_FLD( PU_NX_DEBUGMUX_CTRL_BITS                                , 47  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BITS       );
+REG64_FLD( PU_NX_DEBUGMUX_CTRL_BITS_LEN                            , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NX_DEBUG_SNAPSHOT_0_B0_63                            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_B0_63      );
+REG64_FLD( PU_NX_DEBUG_SNAPSHOT_0_B0_63_LEN                        , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_B0_63_LEN  );
+
+REG64_FLD( PU_NX_DEBUG_SNAPSHOT_1_B64_87                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_B64_87     );
+REG64_FLD( PU_NX_DEBUG_SNAPSHOT_1_B64_87_LEN                       , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_B64_87_LEN );
+
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_00                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_00 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_ICS_INVALID_STATE                     , 1   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_ICS_INVALID_STATE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_02                           , 2   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_02 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_03                           , 3   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_03 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH0_842_ECC_CE                        , 4   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CH0_842_ECC_CE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH0_842_ECC_UE                        , 5   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CH0_842_ECC_UE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH1_842_ECC_CE                        , 6   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CH1_842_ECC_CE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH1_842_ECC_UE                        , 7   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CH1_842_ECC_UE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_NONZERO_CSB_CC                        , 8   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_NONZERO_CSB_CC );
+REG64_FLD( PU_NX_DMA_ENG_FIR_ECC_CE                                , 9   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_ECC_CE     );
+REG64_FLD( PU_NX_DMA_ENG_FIR_OUTWR_INRD_ECC_CE                     , 10  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_OUTWR_INRD_ECC_CE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH5_AMF_ECC_CE                        , 11  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CH5_AMF_ECC_CE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH6_AMF_ECC_CE                        , 12  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CH6_AMF_ECC_CE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH7_AMF_ECC_CE                        , 13  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CH7_AMF_ECC_CE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_OTHER_SCOM_SAT                        , 14  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_OTHER_SCOM_SAT );
+REG64_FLD( PU_NX_DMA_ENG_FIR_INVALID_STATE_RECOV                   , 15  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INVALID_STATE_RECOV );
+REG64_FLD( PU_NX_DMA_ENG_FIR_INVALID_STATE_UNRECOV                 , 16  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INVALID_STATE_UNRECOV );
+REG64_FLD( PU_NX_DMA_ENG_FIR_ECC_UE                                , 17  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_ECC_UE     );
+REG64_FLD( PU_NX_DMA_ENG_FIR_OUTWR_INRD_ECC_UE                     , 18  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_OUTWR_INRD_ECC_UE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_INRD_DONE_ERR                         , 19  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INRD_DONE_ERR );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH0_INVALID_STATE                     , 20  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CH0_INVALID_STATE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH1_INVALID_STATE                     , 21  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CH1_INVALID_STATE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH2_INVALID_STATE                     , 22  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CH2_INVALID_STATE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH3_INVALID_STATE                     , 23  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CH3_INVALID_STATE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH4_INVALID_STATE                     , 24  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CH4_INVALID_STATE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH5_INVALID_STATE                     , 25  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CH5_INVALID_STATE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH6_INVALID_STATE                     , 26  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CH6_INVALID_STATE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH7_INVALID_STATE                     , 27  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CH7_INVALID_STATE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH5_AMF_ECC_UE                        , 28  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CH5_AMF_ECC_UE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH6_AMF_ECC_UE                        , 29  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CH6_AMF_ECC_UE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH7_AMF_ECC_UE                        , 30  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CH7_AMF_ECC_UE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CRB_ECC_UE                            , 31  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CRB_ECC_UE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CRB_ECC_SUE                           , 32  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CRB_ECC_SUE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_OUTWR_INRD_ECC_SUE                    , 33  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_OUTWR_INRD_ECC_SUE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_34                           , 34  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_34 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_35                           , 35  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_35 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH4_AMF_ECC_CE                        , 36  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CH4_AMF_ECC_CE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH4_AMF_ECC_UE                        , 37  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CH4_AMF_ECC_UE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_38                           , 38  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_38 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_39                           , 39  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_39 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_40                           , 40  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_40 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_41                           , 41  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_41 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_42                           , 42  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_42 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_43                           , 43  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_43 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_44                           , 44  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_44 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_45                           , 45  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_45 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_46                           , 46  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_46 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_47                           , 47  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_47 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_SCOM_PE                               , 48  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PE    );
+REG64_FLD( PU_NX_DMA_ENG_FIR_SCOM_PE_DUP                           , 49  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PE_DUP );
+
+REG64_FLD( PU_NX_DMA_ENG_FIR_ACTION0_BITS                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BITS       );
+REG64_FLD( PU_NX_DMA_ENG_FIR_ACTION0_BITS_LEN                      , 50  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NX_DMA_ENG_FIR_ACTION1_BITS                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BITS       );
+REG64_FLD( PU_NX_DMA_ENG_FIR_ACTION1_BITS_LEN                      , 50  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NX_DMA_ENG_FIR_MASK_BITS                             , 0   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BITS       );
+REG64_FLD( PU_NX_DMA_ENG_FIR_MASK_BITS_LEN                         , 50  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NX_DMA_ENG_FIR_WOF_BITS                              , 0   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_BITS       );
+REG64_FLD( PU_NX_DMA_ENG_FIR_WOF_BITS_LEN                          , 50  ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NX_EPSILON_COUNTER_VALUE_NXWR_CFG                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NXWR_CFG   );
+REG64_FLD( PU_NX_EPSILON_COUNTER_VALUE_NXWR_CFG_LEN                , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NXWR_CFG_LEN );
+REG64_FLD( PU_NX_EPSILON_COUNTER_VALUE_NXWR_DISABLE_CP             , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NXWR_DISABLE_CP );
+
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH0EFT_ENA                          , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH0EFT_ENA );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH0EFT_TYPE                         , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH0EFT_TYPE );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH0EFT_ACTION                       , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH0EFT_ACTION );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH0EFT_SELECT                       , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH0EFT_SELECT );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH0EFT_SELECT_LEN                   , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH0EFT_SELECT_LEN );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH1EFT_ENA                          , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH1EFT_ENA );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH1EFT_TYPE                         , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH1EFT_TYPE );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH1EFT_ACTION                       , 11  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH1EFT_ACTION );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH1EFT_SELECT                       , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH1EFT_SELECT );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH1EFT_SELECT_LEN                   , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH1EFT_SELECT_LEN );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INWR_ENA                        , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_INWR_ENA );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INWR_TYPE                       , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_INWR_TYPE );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INWR_ACTION                     , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_INWR_ACTION );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_OUTWR_ENA                       , 26  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_OUTWR_ENA );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_OUTWR_TYPE                      , 27  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_OUTWR_TYPE );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_OUTWR_ACTION                    , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_OUTWR_ACTION );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_ENA                    , 29  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_INGARRAY_ENA );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_TYPE                   , 30  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_INGARRAY_TYPE );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_ACTION                 , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_INGARRAY_ACTION );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_SELECT                 , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_INGARRAY_SELECT );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_SELECT_LEN             , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_INGARRAY_SELECT_LEN );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_ENA                    , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_EGRARRAY_ENA );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_TYPE                   , 37  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_EGRARRAY_TYPE );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_ACTION                 , 38  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_EGRARRAY_ACTION );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_SELECT                 , 39  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_EGRARRAY_SELECT );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_SELECT_LEN             , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_EGRARRAY_SELECT_LEN );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_CRBARRAY_ENA                    , 43  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_CRBARRAY_ENA );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_CRBARRAY_TYPE                   , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_CRBARRAY_TYPE );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_CRBARRAY_ACTION                 , 45  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_CRBARRAY_ACTION );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_CRBARRAY_SELECT                 , 46  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_CRBARRAY_SELECT );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH4GZIP_ENA                         , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH4GZIP_ENA );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH4GZIP_TYPE                        , 49  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH4GZIP_TYPE );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH4GZIP_ACTION                      , 50  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH4GZIP_ACTION );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH4GZIP_SELECT                      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH4GZIP_SELECT );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH4GZIP_SELECT_LEN                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH4GZIP_SELECT_LEN );
+
+REG64_FLD( PU_NX_FOREIGN_F_BAR0_PB_FORF0_BAR_EN                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_FORF0_BAR_EN );
+REG64_FLD( PU_NX_FOREIGN_F_BAR0_PB_FORF0_MASK                      , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_FORF0_MASK );
+REG64_FLD( PU_NX_FOREIGN_F_BAR0_PB_FORF0_MASK_LEN                  , 19  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_FORF0_MASK_LEN );
+REG64_FLD( PU_NX_FOREIGN_F_BAR0_PB_FORF0_BAR                       , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_FORF0_BAR );
+REG64_FLD( PU_NX_FOREIGN_F_BAR0_PB_FORF0_BAR_LEN                   , 26  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_FORF0_BAR_LEN );
+
+REG64_FLD( PU_NX_FOREIGN_F_BAR1_PB_FORF1_BAR_EN                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_FORF1_BAR_EN );
+REG64_FLD( PU_NX_FOREIGN_F_BAR1_PB_FORF1_MASK                      , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_FORF1_MASK );
+REG64_FLD( PU_NX_FOREIGN_F_BAR1_PB_FORF1_MASK_LEN                  , 19  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_FORF1_MASK_LEN );
+REG64_FLD( PU_NX_FOREIGN_F_BAR1_PB_FORF1_BAR                       , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_FORF1_BAR );
+REG64_FLD( PU_NX_FOREIGN_F_BAR1_PB_FORF1_BAR_LEN                   , 26  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_FORF1_BAR_LEN );
+
+REG64_FLD( PU_NX_FOREIGN_L_BAR0_PB_FORL0_BAR_EN                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_FORL0_BAR_EN );
+REG64_FLD( PU_NX_FOREIGN_L_BAR0_PB_FORL0_MASK                      , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_FORL0_MASK );
+REG64_FLD( PU_NX_FOREIGN_L_BAR0_PB_FORL0_MASK_LEN                  , 19  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_FORL0_MASK_LEN );
+REG64_FLD( PU_NX_FOREIGN_L_BAR0_PB_FORL0_BAR                       , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_FORL0_BAR );
+REG64_FLD( PU_NX_FOREIGN_L_BAR0_PB_FORL0_BAR_LEN                   , 26  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_FORL0_BAR_LEN );
+
+REG64_FLD( PU_NX_FOREIGN_L_BAR1_PB_FORL1_BAR_EN                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_FORL1_BAR_EN );
+REG64_FLD( PU_NX_FOREIGN_L_BAR1_PB_FORL1_MASK                      , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_FORL1_MASK );
+REG64_FLD( PU_NX_FOREIGN_L_BAR1_PB_FORL1_MASK_LEN                  , 19  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_FORL1_MASK_LEN );
+REG64_FLD( PU_NX_FOREIGN_L_BAR1_PB_FORL1_BAR                       , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_FORL1_BAR );
+REG64_FLD( PU_NX_FOREIGN_L_BAR1_PB_FORL1_BAR_LEN                   , 26  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_FORL1_BAR_LEN );
+
+REG64_FLD( PU_NX_GROUP_BAR0_PB_EN                                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_EN      );
+REG64_FLD( PU_NX_GROUP_BAR0_PB_MASK0                               , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_MASK0   );
+REG64_FLD( PU_NX_GROUP_BAR0_PB_MASK0_LEN                           , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_MASK0_LEN );
+REG64_FLD( PU_NX_GROUP_BAR0_PB                                     , 15  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB         );
+REG64_FLD( PU_NX_GROUP_BAR0_PB_LEN                                 , 18  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_LEN     );
+
+REG64_FLD( PU_NX_GROUP_BAR1_PB_EN                                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_EN      );
+REG64_FLD( PU_NX_GROUP_BAR1_PB_MASK1                               , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_MASK1   );
+REG64_FLD( PU_NX_GROUP_BAR1_PB_MASK1_LEN                           , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_MASK1_LEN );
+REG64_FLD( PU_NX_GROUP_BAR1_PB                                     , 15  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB         );
+REG64_FLD( PU_NX_GROUP_BAR1_PB_LEN                                 , 18  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_LEN     );
+
+REG64_FLD( PU_NX_ICS_CFG_REG_TRUSTED_PRIORITY                      , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRUSTED_PRIORITY );
+REG64_FLD( PU_NX_ICS_CFG_REG_TRUSTED_PRIORITY_LEN                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRUSTED_PRIORITY_LEN );
+REG64_FLD( PU_NX_ICS_CFG_REG_TRUSTED_SERVER_NUMBER                 , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRUSTED_SERVER_NUMBER );
+REG64_FLD( PU_NX_ICS_CFG_REG_TRUSTED_SERVER_NUMBER_LEN             , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRUSTED_SERVER_NUMBER_LEN );
+REG64_FLD( PU_NX_ICS_CFG_REG_RESEND_COUNTER                        , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESEND_COUNTER );
+REG64_FLD( PU_NX_ICS_CFG_REG_RESEND_COUNTER_LEN                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESEND_COUNTER_LEN );
+REG64_FLD( PU_NX_ICS_CFG_REG_SWITCHOVER_STATUS                     , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SWITCHOVER_STATUS );
+REG64_FLD( PU_NX_ICS_CFG_REG_RETRY_COUNTER                         , 54  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RETRY_COUNTER );
+REG64_FLD( PU_NX_ICS_CFG_REG_RETRY_COUNTER_LEN                     , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RETRY_COUNTER_LEN );
+
+REG64_FLD( PU_NX_ICS_CFG_REG2_FSP_OCC_BUID                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FSP_OCC_BUID );
+REG64_FLD( PU_NX_ICS_CFG_REG2_FSP_OCC_BUID_LEN                     , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FSP_OCC_BUID_LEN );
+REG64_FLD( PU_NX_ICS_CFG_REG2_FSP_INTERRUPT_VALUE                  , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FSP_INTERRUPT_VALUE );
+REG64_FLD( PU_NX_ICS_CFG_REG2_FSP_INTERRUPT_VALUE_LEN              , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FSP_INTERRUPT_VALUE_LEN );
+REG64_FLD( PU_NX_ICS_CFG_REG2_FSP_PRIORITY                         , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FSP_PRIORITY );
+REG64_FLD( PU_NX_ICS_CFG_REG2_FSP_PRIORITY_LEN                     , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FSP_PRIORITY_LEN );
+REG64_FLD( PU_NX_ICS_CFG_REG2_FSP_SERVER_NUMBER                    , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FSP_SERVER_NUMBER );
+REG64_FLD( PU_NX_ICS_CFG_REG2_FSP_SERVER_NUMBER_LEN                , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FSP_SERVER_NUMBER_LEN );
+REG64_FLD( PU_NX_ICS_CFG_REG2_OCC_INTERRUPT_VALUE                  , 37  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OCC_INTERRUPT_VALUE );
+REG64_FLD( PU_NX_ICS_CFG_REG2_OCC_INTERRUPT_VALUE_LEN              , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OCC_INTERRUPT_VALUE_LEN );
+REG64_FLD( PU_NX_ICS_CFG_REG2_OCC_PRIORITY                         , 42  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OCC_PRIORITY );
+REG64_FLD( PU_NX_ICS_CFG_REG2_OCC_PRIORITY_LEN                     , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OCC_PRIORITY_LEN );
+REG64_FLD( PU_NX_ICS_CFG_REG2_OCC_SERVER_NUMBER                    , 50  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OCC_SERVER_NUMBER );
+REG64_FLD( PU_NX_ICS_CFG_REG2_OCC_SERVER_NUMBER_LEN                , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OCC_SERVER_NUMBER_LEN );
+
+REG64_FLD( PU_NX_MISC_CONTROL_REG_INTERRUPT_ENABLE                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INTERRUPT_ENABLE );
+REG64_FLD( PU_NX_MISC_CONTROL_REG_AS_INTERRUPT_ENABLE              , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_AS_INTERRUPT_ENABLE );
+REG64_FLD( PU_NX_MISC_CONTROL_REG_HANG_POLL_SCALE                  , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HANG_POLL_SCALE );
+REG64_FLD( PU_NX_MISC_CONTROL_REG_HANG_POLL_SCALE_LEN              , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HANG_POLL_SCALE_LEN );
+REG64_FLD( PU_NX_MISC_CONTROL_REG_HANG_DATA_SCALE                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HANG_DATA_SCALE );
+REG64_FLD( PU_NX_MISC_CONTROL_REG_HANG_DATA_SCALE_LEN              , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HANG_DATA_SCALE_LEN );
+REG64_FLD( PU_NX_MISC_CONTROL_REG_HANG_SHM_SCALE                   , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HANG_SHM_SCALE );
+REG64_FLD( PU_NX_MISC_CONTROL_REG_HANG_SHM_SCALE_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HANG_SHM_SCALE_LEN );
+
+REG64_FLD( PU_NX_MMIO_BAR_BAR                                      , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BAR        );
+REG64_FLD( PU_NX_MMIO_BAR_BAR_LEN                                  , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BAR_LEN    );
+REG64_FLD( PU_NX_MMIO_BAR_ENABLE                                   , 52  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE     );
+
+REG64_FLD( PU_NX_NODAL_BAR0_PB_EN                                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_EN      );
+REG64_FLD( PU_NX_NODAL_BAR0_PB_MASK0                               , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_MASK0   );
+REG64_FLD( PU_NX_NODAL_BAR0_PB_MASK0_LEN                           , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_MASK0_LEN );
+REG64_FLD( PU_NX_NODAL_BAR0_PB                                     , 15  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB         );
+REG64_FLD( PU_NX_NODAL_BAR0_PB_LEN                                 , 18  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_LEN     );
+
+REG64_FLD( PU_NX_NODAL_BAR1_PB_EN                                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_EN      );
+REG64_FLD( PU_NX_NODAL_BAR1_PB_MASK1                               , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_MASK1   );
+REG64_FLD( PU_NX_NODAL_BAR1_PB_MASK1_LEN                           , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_MASK1_LEN );
+REG64_FLD( PU_NX_NODAL_BAR1_PB                                     , 15  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB         );
+REG64_FLD( PU_NX_NODAL_BAR1_PB_LEN                                 , 18  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PB_LEN     );
+
+REG64_FLD( PU_NX_PB_DEBUG_REG_NXCQ_TRACE_CNTL                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NXCQ_TRACE_CNTL );
+REG64_FLD( PU_NX_PB_DEBUG_REG_NXCQ_TRACE_CNTL_LEN                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NXCQ_TRACE_CNTL_LEN );
+
+REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_INJECT_MODE                       , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NXCQ_INJECT_MODE );
+REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_INJECT_MODE_LEN                   , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NXCQ_INJECT_MODE_LEN );
+REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_INJECT_TYPE                       , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NXCQ_INJECT_TYPE );
+REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_INJECT_TYPE_LEN                   , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NXCQ_INJECT_TYPE_LEN );
+REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_PBCQ_INJECT_ENABLE                , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NXCQ_PBCQ_INJECT_ENABLE );
+REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_PBCQ_ARRAY                        , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NXCQ_PBCQ_ARRAY );
+REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_PBCQ_ARRAY_LEN                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NXCQ_PBCQ_ARRAY_LEN );
+
+REG64_FLD( PU_NX_PB_ERR_RPT_0_PBI_WRITE_IDLE                       , 63  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PBI_WRITE_IDLE );
+
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_ENABLE                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_FREEZE                           , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FREEZE     );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_RESET                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESET      );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_DIS_GLOB_SCOM                    , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DIS_GLOB_SCOM );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL0                   , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRESCALAR_SEL0 );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL0_LEN               , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRESCALAR_SEL0_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL1                   , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRESCALAR_SEL1 );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL1_LEN               , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRESCALAR_SEL1_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL2                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRESCALAR_SEL2 );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL2_LEN               , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRESCALAR_SEL2_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL3                   , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRESCALAR_SEL3 );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL3_LEN               , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRESCALAR_SEL3_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT0_PAIR_OP                     , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT0_PAIR_OP );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT0_PAIR_OP_LEN                 , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT0_PAIR_OP_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT1_PAIR_OP                     , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT1_PAIR_OP );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT1_PAIR_OP_LEN                 , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT1_PAIR_OP_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT2_PAIR_OP                     , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT2_PAIR_OP );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT2_PAIR_OP_LEN                 , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT2_PAIR_OP_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT3_PAIR_OP                     , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT3_PAIR_OP );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT3_PAIR_OP_LEN                 , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT3_PAIR_OP_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT0_MUX_SEL                     , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT0_MUX_SEL );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT0_MUX_SEL_LEN                 , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT0_MUX_SEL_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT1_MUX_SEL                     , 23  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT1_MUX_SEL );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT1_MUX_SEL_LEN                 , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT1_MUX_SEL_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT2_MUX_SEL                     , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT2_MUX_SEL );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT2_MUX_SEL_LEN                 , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT2_MUX_SEL_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT3_MUX_SEL                     , 29  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT3_MUX_SEL );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT3_MUX_SEL_LEN                 , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT3_MUX_SEL_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_FREEZE_ON_OVERFLOW               , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FREEZE_ON_OVERFLOW );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CASCADE                          , 33  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CASCADE    );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CASCADE_LEN                      , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CASCADE_LEN );
+
+REG64_FLD( PU_NX_PMU0_COUNTER_REG_0                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_0          );
+REG64_FLD( PU_NX_PMU0_COUNTER_REG_0_LEN                            , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_0_LEN      );
+REG64_FLD( PU_NX_PMU0_COUNTER_REG_1                                , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_1          );
+REG64_FLD( PU_NX_PMU0_COUNTER_REG_1_LEN                            , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_1_LEN      );
+REG64_FLD( PU_NX_PMU0_COUNTER_REG_2                                , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_2          );
+REG64_FLD( PU_NX_PMU0_COUNTER_REG_2_LEN                            , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_2_LEN      );
+REG64_FLD( PU_NX_PMU0_COUNTER_REG_3                                , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_3          );
+REG64_FLD( PU_NX_PMU0_COUNTER_REG_3_LEN                            , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_3_LEN      );
+
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_ENABLE                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_FREEZE                           , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FREEZE     );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_RESET                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESET      );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_DIS_GLOB_SCOM                    , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DIS_GLOB_SCOM );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL0                   , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRESCALAR_SEL0 );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL0_LEN               , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRESCALAR_SEL0_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL1                   , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRESCALAR_SEL1 );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL1_LEN               , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRESCALAR_SEL1_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL2                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRESCALAR_SEL2 );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL2_LEN               , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRESCALAR_SEL2_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL3                   , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRESCALAR_SEL3 );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL3_LEN               , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRESCALAR_SEL3_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT0_PAIR_OP                     , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT0_PAIR_OP );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT0_PAIR_OP_LEN                 , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT0_PAIR_OP_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT1_PAIR_OP                     , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT1_PAIR_OP );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT1_PAIR_OP_LEN                 , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT1_PAIR_OP_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT2_PAIR_OP                     , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT2_PAIR_OP );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT2_PAIR_OP_LEN                 , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT2_PAIR_OP_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT3_PAIR_OP                     , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT3_PAIR_OP );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT3_PAIR_OP_LEN                 , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT3_PAIR_OP_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT0_MUX_SEL                     , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT0_MUX_SEL );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT0_MUX_SEL_LEN                 , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT0_MUX_SEL_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT1_MUX_SEL                     , 23  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT1_MUX_SEL );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT1_MUX_SEL_LEN                 , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT1_MUX_SEL_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT2_MUX_SEL                     , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT2_MUX_SEL );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT2_MUX_SEL_LEN                 , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT2_MUX_SEL_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT3_MUX_SEL                     , 29  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT3_MUX_SEL );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT3_MUX_SEL_LEN                 , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT3_MUX_SEL_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_FREEZE_ON_OVERFLOW               , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FREEZE_ON_OVERFLOW );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CASCADE                          , 33  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CASCADE    );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CASCADE_LEN                      , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CASCADE_LEN );
+
+REG64_FLD( PU_NX_PMU1_COUNTER_REG_0                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_0          );
+REG64_FLD( PU_NX_PMU1_COUNTER_REG_0_LEN                            , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_0_LEN      );
+REG64_FLD( PU_NX_PMU1_COUNTER_REG_1                                , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_1          );
+REG64_FLD( PU_NX_PMU1_COUNTER_REG_1_LEN                            , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_1_LEN      );
+REG64_FLD( PU_NX_PMU1_COUNTER_REG_2                                , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_2          );
+REG64_FLD( PU_NX_PMU1_COUNTER_REG_2_LEN                            , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_2_LEN      );
+REG64_FLD( PU_NX_PMU1_COUNTER_REG_3                                , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_3          );
+REG64_FLD( PU_NX_PMU1_COUNTER_REG_3_LEN                            , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_3_LEN      );
+
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT0_ENABLE                       , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT0_ENABLE );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT1_ENABLE                       , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT1_ENABLE );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT2_ENABLE                       , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT2_ENABLE );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT3_ENABLE                       , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT3_ENABLE );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_PRESCALER_SEL                     , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRESCALER_SEL );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_PRESCALER_SEL_LEN                 , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRESCALER_SEL_LEN );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT0_POSEDGE_SEL                  , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT0_POSEDGE_SEL );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT1_POSEDGE_SEL                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT1_POSEDGE_SEL );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT2_POSEDGE_SEL                  , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT2_POSEDGE_SEL );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT3_POSEDGE_SEL                  , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT3_POSEDGE_SEL );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_RESET                             , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESET      );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT0_EVENT_SEL                    , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT0_EVENT_SEL );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT0_EVENT_SEL_LEN                , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT0_EVENT_SEL_LEN );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT0_BIT_PAIR_SEL                 , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT0_BIT_PAIR_SEL );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT0_BIT_PAIR_SEL_LEN             , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT0_BIT_PAIR_SEL_LEN );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT1_EVENT_SEL                    , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT1_EVENT_SEL );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT1_EVENT_SEL_LEN                , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT1_EVENT_SEL_LEN );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT1_BIT_PAIR_SEL                 , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT1_BIT_PAIR_SEL );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT1_BIT_PAIR_SEL_LEN             , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT1_BIT_PAIR_SEL_LEN );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT2_EVENT_SEL                    , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT2_EVENT_SEL );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT2_EVENT_SEL_LEN                , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT2_EVENT_SEL_LEN );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT2_BIT_PAIR_SEL                 , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT2_BIT_PAIR_SEL );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT2_BIT_PAIR_SEL_LEN             , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT2_BIT_PAIR_SEL_LEN );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT3_EVENT_SEL                    , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT3_EVENT_SEL );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT3_EVENT_SEL_LEN                , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT3_EVENT_SEL_LEN );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT3_BIT_PAIR_SEL                 , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT3_BIT_PAIR_SEL );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_CNT3_BIT_PAIR_SEL_LEN             , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CNT3_BIT_PAIR_SEL_LEN );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_PORT_SEL                          , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PORT_SEL   );
+REG64_FLD( PU_NX_PMU_CONTROL_REG_PORT_SEL_LEN                      , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PORT_SEL_LEN );
+
+REG64_FLD( PU_NX_PMU_COUNTER_REG_0                                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_0          );
+REG64_FLD( PU_NX_PMU_COUNTER_REG_0_LEN                             , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_0_LEN      );
+REG64_FLD( PU_NX_PMU_COUNTER_REG_1                                 , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_1          );
+REG64_FLD( PU_NX_PMU_COUNTER_REG_1_LEN                             , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_1_LEN      );
+REG64_FLD( PU_NX_PMU_COUNTER_REG_2                                 , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_2          );
+REG64_FLD( PU_NX_PMU_COUNTER_REG_2_LEN                             , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_2_LEN      );
+REG64_FLD( PU_NX_PMU_COUNTER_REG_3                                 , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_3          );
+REG64_FLD( PU_NX_PMU_COUNTER_REG_3_LEN                             , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_3_LEN      );
+
+REG64_FLD( PU_NX_RNG_BYPASS_RRN_DATA                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RRN_DATA   );
+REG64_FLD( PU_NX_RNG_BYPASS_RRN_DATA_LEN                           , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RRN_DATA_LEN );
+
+REG64_FLD( PU_NX_RNG_CFG_FAIL_REG                                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FAIL_REG   );
+REG64_FLD( PU_NX_RNG_CFG_FAIL_REG_LEN                              , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FAIL_REG_LEN );
+REG64_FLD( PU_NX_RNG_CFG_RNG0_FAIL                                 , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RNG0_FAIL  );
+REG64_FLD( PU_NX_RNG_CFG_RNG1_FAIL                                 , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RNG1_FAIL  );
+REG64_FLD( PU_NX_RNG_CFG_INTERRUPT_SENT                            , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INTERRUPT_SENT );
+REG64_FLD( PU_NX_RNG_CFG_BIST_ENABLE                               , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BIST_ENABLE );
+REG64_FLD( PU_NX_RNG_CFG_BIST_COMPLETE                             , 17  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BIST_COMPLETE );
+REG64_FLD( PU_NX_RNG_CFG_RNG0_BIST_FAIL                            , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RNG0_BIST_FAIL );
+REG64_FLD( PU_NX_RNG_CFG_RNG1_BIST_FAIL                            , 19  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RNG1_BIST_FAIL );
+REG64_FLD( PU_NX_RNG_CFG_BIST_BIT_FAIL_TH                          , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BIST_BIT_FAIL_TH );
+REG64_FLD( PU_NX_RNG_CFG_BIST_BIT_FAIL_TH_LEN                      , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BIST_BIT_FAIL_TH_LEN );
+REG64_FLD( PU_NX_RNG_CFG_RNG0_INJ_CONTINOUS_ERROR                  , 23  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RNG0_INJ_CONTINOUS_ERROR );
+REG64_FLD( PU_NX_RNG_CFG_RNG1_INJ_CONTINOUS_ERROR                  , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RNG1_INJ_CONTINOUS_ERROR );
+REG64_FLD( PU_NX_RNG_CFG_ST2_RESET_PERIOD                          , 30  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ST2_RESET_PERIOD );
+REG64_FLD( PU_NX_RNG_CFG_ST2_RESET_PERIOD_LEN                      , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ST2_RESET_PERIOD_LEN );
+REG64_FLD( PU_NX_RNG_CFG_RRN_BYPASS_ENABLE                         , 38  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RRN_BYPASS_ENABLE );
+REG64_FLD( PU_NX_RNG_CFG_MASK_TOGGLE_ENABLE                        , 39  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASK_TOGGLE_ENABLE );
+REG64_FLD( PU_NX_RNG_CFG_SAMPTEST_ENABLE                           , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SAMPTEST_ENABLE );
+REG64_FLD( PU_NX_RNG_CFG_REPTEST_ENABLE                            , 41  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REPTEST_ENABLE );
+REG64_FLD( PU_NX_RNG_CFG_ADAPTEST_1BIT_ENABLE                      , 42  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_1BIT_ENABLE );
+REG64_FLD( PU_NX_RNG_CFG_ADAPTEST_ENABLE                           , 43  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_ENABLE );
+REG64_FLD( PU_NX_RNG_CFG_COND_STARTUP_TEST_FAIL                    , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_COND_STARTUP_TEST_FAIL );
+REG64_FLD( PU_NX_RNG_CFG_PACE_RATE                                 , 46  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PACE_RATE  );
+REG64_FLD( PU_NX_RNG_CFG_PACE_RATE_LEN                             , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PACE_RATE_LEN );
+REG64_FLD( PU_NX_RNG_CFG_ENABLE                                    , 63  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE     );
+
+REG64_FLD( PU_NX_RNG_RDELAY_CQ_FILL_THRESHOLD                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CQ_FILL_THRESHOLD );
+REG64_FLD( PU_NX_RNG_RDELAY_CQ_FILL_THRESHOLD_LEN                  , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CQ_FILL_THRESHOLD_LEN );
+REG64_FLD( PU_NX_RNG_RDELAY_CQ_DRAIN_THRESHOLD                     , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CQ_DRAIN_THRESHOLD );
+REG64_FLD( PU_NX_RNG_RDELAY_CQ_DRAIN_THRESHOLD_LEN                 , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CQ_DRAIN_THRESHOLD_LEN );
+REG64_FLD( PU_NX_RNG_RDELAY_CQ_LFSR_RESEED_EN                      , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CQ_LFSR_RESEED_EN );
+REG64_FLD( PU_NX_RNG_RDELAY_CQ_READ_RTY_RATIO                      , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CQ_READ_RTY_RATIO );
+REG64_FLD( PU_NX_RNG_RDELAY_CQ_READ_RTY_RATIO_LEN                  , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CQ_READ_RTY_RATIO_LEN );
+
+REG64_FLD( PU_NX_RNG_RESET_RESET                                   , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESET      );
+
+REG64_FLD( PU_NX_RNG_ST0_REPTEST_MATCH_TH                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REPTEST_MATCH_TH );
+REG64_FLD( PU_NX_RNG_ST0_REPTEST_MATCH_TH_LEN                      , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REPTEST_MATCH_TH_LEN );
+REG64_FLD( PU_NX_RNG_ST0_REPTEST_SOFT_FAIL_TH                      , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REPTEST_SOFT_FAIL_TH );
+REG64_FLD( PU_NX_RNG_ST0_REPTEST_SOFT_FAIL_TH_LEN                  , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REPTEST_SOFT_FAIL_TH_LEN );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE                      , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_SAMPLE_SIZE );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE_LEN                  , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_SAMPLE_SIZE_LEN );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_WINDOW_SIZE                      , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_WINDOW_SIZE );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_WINDOW_SIZE_LEN                  , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_WINDOW_SIZE_LEN );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH                , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_RRN_RNG0_MATCH_TH );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH_LEN            , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_RRN_RNG0_MATCH_TH_LEN );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH                , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_RRN_RNG1_MATCH_TH );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH_LEN            , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_RRN_RNG1_MATCH_TH_LEN );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH                , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_CRN_RNG0_MATCH_TH );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH_LEN            , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_CRN_RNG0_MATCH_TH_LEN );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH                , 36  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_CRN_RNG1_MATCH_TH );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH_LEN            , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_CRN_RNG1_MATCH_TH_LEN );
+
+REG64_FLD( PU_NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_SOFT_FAIL_TH );
+REG64_FLD( PU_NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH_LEN                 , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_SOFT_FAIL_TH_LEN );
+REG64_FLD( PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN                , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_1BIT_MATCH_TH_MIN );
+REG64_FLD( PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN_LEN            , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_1BIT_MATCH_TH_MIN_LEN );
+REG64_FLD( PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX                , 23  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_1BIT_MATCH_TH_MAX );
+REG64_FLD( PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX_LEN            , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_1BIT_MATCH_TH_MAX_LEN );
+REG64_FLD( PU_NX_RNG_ST1_SAMPTEST_RRN_ENABLE                       , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SAMPTEST_RRN_ENABLE );
+REG64_FLD( PU_NX_RNG_ST1_SAMPTEST_WINDOW_SIZE                      , 45  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SAMPTEST_WINDOW_SIZE );
+REG64_FLD( PU_NX_RNG_ST1_SAMPTEST_WINDOW_SIZE_LEN                  , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SAMPTEST_WINDOW_SIZE_LEN );
+REG64_FLD( PU_NX_RNG_ST1_SAMPTEST_MATCH_TH_MIN                     , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SAMPTEST_MATCH_TH_MIN );
+REG64_FLD( PU_NX_RNG_ST1_SAMPTEST_MATCH_TH_MIN_LEN                 , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SAMPTEST_MATCH_TH_MIN_LEN );
+REG64_FLD( PU_NX_RNG_ST1_SAMPTEST_MATCH_TH_MAX                     , 56  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SAMPTEST_MATCH_TH_MAX );
+REG64_FLD( PU_NX_RNG_ST1_SAMPTEST_MATCH_TH_MAX_LEN                 , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SAMPTEST_MATCH_TH_MAX_LEN );
+
+REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0 );
+REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0_LEN     , 8   ,
+           SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0_LEN );
+REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1 );
+REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1_LEN     , 8   ,
+           SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1_LEN );
+REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0         , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0 );
+REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0_LEN     , 8   ,
+           SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0_LEN );
+REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1 );
+REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1_LEN     , 8   ,
+           SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1_LEN );
+REG64_FLD( PU_NX_RNG_ST2_REPTEST_SOFT_FAIL_COUNT_RNG0              , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG0 );
+REG64_FLD( PU_NX_RNG_ST2_REPTEST_SOFT_FAIL_COUNT_RNG0_LEN          , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG0_LEN );
+REG64_FLD( PU_NX_RNG_ST2_REPTEST_SOFT_FAIL_COUNT_RNG1              , 38  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG1 );
+REG64_FLD( PU_NX_RNG_ST2_REPTEST_SOFT_FAIL_COUNT_RNG1_LEN          , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG1_LEN );
+
+REG64_FLD( PU_NX_TRIGGER_CTRL_BITS                                 , 50  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BITS       );
+REG64_FLD( PU_NX_TRIGGER_CTRL_BITS_LEN                             , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_GPE6_OCB_OCI_CCSR_CORE_CONFIG                        , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_CORE_CONFIG );
+REG64_FLD( PU_GPE6_OCB_OCI_CCSR_CORE_CONFIG_LEN                    , 24  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_CORE_CONFIG_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_CCSR_RESERVED_24                        , 24  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_24 );
+REG64_FLD( PU_GPE6_OCB_OCI_CCSR_RESERVED_24_LEN                    , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_24_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_CCSR_CHANGE_IN_PROGRESS                 , 31  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_CHANGE_IN_PROGRESS );
+
+REG64_FLD( PU_GPE0_OCB_OCI_CCSR_CORE_CONFIG                        , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_CORE_CONFIG );
+REG64_FLD( PU_GPE0_OCB_OCI_CCSR_CORE_CONFIG_LEN                    , 24  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_CORE_CONFIG_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_CCSR_RESERVED_24                        , 24  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_RESERVED_24 );
+REG64_FLD( PU_GPE0_OCB_OCI_CCSR_RESERVED_24_LEN                    , 7   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_RESERVED_24_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_CCSR_CHANGE_IN_PROGRESS                 , 31  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_CHANGE_IN_PROGRESS );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCMD0A_O2SCMD_A_N_RESERVED_0          , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SCMD_A_N_RESERVED_0 );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCMD0A_O2S_CLEAR_STICKY_BITS_A_N      , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_CLEAR_STICKY_BITS_A_N );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCMD0A_O2SCMD_A_N_RESERVED_0          , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2SCMD_A_N_RESERVED_0 );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCMD0A_O2S_CLEAR_STICKY_BITS_A_N      , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_CLEAR_STICKY_BITS_A_N );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCMD0B_O2SCMD_A_N_RESERVED_0          , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SCMD_A_N_RESERVED_0 );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCMD0B_O2S_CLEAR_STICKY_BITS_A_N      , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_CLEAR_STICKY_BITS_A_N );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCMD0B_O2SCMD_A_N_RESERVED_0          , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2SCMD_A_N_RESERVED_0 );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCMD0B_O2S_CLEAR_STICKY_BITS_A_N      , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_CLEAR_STICKY_BITS_A_N );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCMD1A_O2SCMD_A_N_RESERVED_0          , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SCMD_A_N_RESERVED_0 );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCMD1A_O2S_CLEAR_STICKY_BITS_A_N      , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_CLEAR_STICKY_BITS_A_N );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCMD1A_O2SCMD_A_N_RESERVED_0          , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2SCMD_A_N_RESERVED_0 );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCMD1A_O2S_CLEAR_STICKY_BITS_A_N      , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_CLEAR_STICKY_BITS_A_N );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCMD1B_O2SCMD_A_N_RESERVED_0          , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SCMD_A_N_RESERVED_0 );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCMD1B_O2S_CLEAR_STICKY_BITS_A_N      , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_CLEAR_STICKY_BITS_A_N );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCMD1B_O2SCMD_A_N_RESERVED_0          , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2SCMD_A_N_RESERVED_0 );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCMD1B_O2S_CLEAR_STICKY_BITS_A_N      , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_CLEAR_STICKY_BITS_A_N );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL10A_O2S_BRIDGE_ENABLE_A_N        , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_BRIDGE_ENABLE_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL10A_O2SCTRL1_A_N_RESERVED_1      , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SCTRL1_A_N_RESERVED_1 );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL10A_O2S_CPOL_A_N                 , 2   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_CPOL_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL10A_O2S_CPHA_A_N                 , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_CPHA_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL10A_O2S_CLOCK_DIVIDER_A_N        , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_CLOCK_DIVIDER_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL10A_O2S_CLOCK_DIVIDER_A_N_LEN    , 10  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_CLOCK_DIVIDER_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL10A_O2SCTRL1_A_N_RESERVED_14_16  , 14  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16 );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL10A_O2SCTRL1_A_N_RESERVED_14_16_LEN , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL10A_O2S_NR_OF_FRAMES_A_N         , 17  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_NR_OF_FRAMES_A_N );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL10A_O2S_BRIDGE_ENABLE_A_N        , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_BRIDGE_ENABLE_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL10A_O2SCTRL1_A_N_RESERVED_1      , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2SCTRL1_A_N_RESERVED_1 );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL10A_O2S_CPOL_A_N                 , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_CPOL_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL10A_O2S_CPHA_A_N                 , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_CPHA_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL10A_O2S_CLOCK_DIVIDER_A_N        , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_CLOCK_DIVIDER_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL10A_O2S_CLOCK_DIVIDER_A_N_LEN    , 10  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_CLOCK_DIVIDER_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL10A_O2SCTRL1_A_N_RESERVED_14_16  , 14  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16 );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL10A_O2SCTRL1_A_N_RESERVED_14_16_LEN , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL10A_O2S_NR_OF_FRAMES_A_N         , 17  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_NR_OF_FRAMES_A_N );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL10B_O2S_BRIDGE_ENABLE_A_N        , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_BRIDGE_ENABLE_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL10B_O2SCTRL1_A_N_RESERVED_1      , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SCTRL1_A_N_RESERVED_1 );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL10B_O2S_CPOL_A_N                 , 2   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_CPOL_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL10B_O2S_CPHA_A_N                 , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_CPHA_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL10B_O2S_CLOCK_DIVIDER_A_N        , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_CLOCK_DIVIDER_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL10B_O2S_CLOCK_DIVIDER_A_N_LEN    , 10  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_CLOCK_DIVIDER_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL10B_O2SCTRL1_A_N_RESERVED_14_16  , 14  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16 );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL10B_O2SCTRL1_A_N_RESERVED_14_16_LEN , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL10B_O2S_NR_OF_FRAMES_A_N         , 17  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_NR_OF_FRAMES_A_N );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL10B_O2S_BRIDGE_ENABLE_A_N        , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_BRIDGE_ENABLE_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL10B_O2SCTRL1_A_N_RESERVED_1      , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2SCTRL1_A_N_RESERVED_1 );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL10B_O2S_CPOL_A_N                 , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_CPOL_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL10B_O2S_CPHA_A_N                 , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_CPHA_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL10B_O2S_CLOCK_DIVIDER_A_N        , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_CLOCK_DIVIDER_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL10B_O2S_CLOCK_DIVIDER_A_N_LEN    , 10  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_CLOCK_DIVIDER_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL10B_O2SCTRL1_A_N_RESERVED_14_16  , 14  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16 );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL10B_O2SCTRL1_A_N_RESERVED_14_16_LEN , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL10B_O2S_NR_OF_FRAMES_A_N         , 17  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_NR_OF_FRAMES_A_N );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL11A_O2S_BRIDGE_ENABLE_A_N        , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_BRIDGE_ENABLE_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL11A_O2SCTRL1_A_N_RESERVED_1      , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SCTRL1_A_N_RESERVED_1 );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL11A_O2S_CPOL_A_N                 , 2   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_CPOL_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL11A_O2S_CPHA_A_N                 , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_CPHA_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL11A_O2S_CLOCK_DIVIDER_A_N        , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_CLOCK_DIVIDER_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL11A_O2S_CLOCK_DIVIDER_A_N_LEN    , 10  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_CLOCK_DIVIDER_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL11A_O2SCTRL1_A_N_RESERVED_14_16  , 14  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16 );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL11A_O2SCTRL1_A_N_RESERVED_14_16_LEN , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL11A_O2S_NR_OF_FRAMES_A_N         , 17  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_NR_OF_FRAMES_A_N );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL11A_O2S_BRIDGE_ENABLE_A_N        , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_BRIDGE_ENABLE_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL11A_O2SCTRL1_A_N_RESERVED_1      , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2SCTRL1_A_N_RESERVED_1 );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL11A_O2S_CPOL_A_N                 , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_CPOL_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL11A_O2S_CPHA_A_N                 , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_CPHA_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL11A_O2S_CLOCK_DIVIDER_A_N        , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_CLOCK_DIVIDER_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL11A_O2S_CLOCK_DIVIDER_A_N_LEN    , 10  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_CLOCK_DIVIDER_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL11A_O2SCTRL1_A_N_RESERVED_14_16  , 14  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16 );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL11A_O2SCTRL1_A_N_RESERVED_14_16_LEN , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL11A_O2S_NR_OF_FRAMES_A_N         , 17  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_NR_OF_FRAMES_A_N );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL11B_O2S_BRIDGE_ENABLE_A_N        , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_BRIDGE_ENABLE_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL11B_O2SCTRL1_A_N_RESERVED_1      , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SCTRL1_A_N_RESERVED_1 );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL11B_O2S_CPOL_A_N                 , 2   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_CPOL_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL11B_O2S_CPHA_A_N                 , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_CPHA_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL11B_O2S_CLOCK_DIVIDER_A_N        , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_CLOCK_DIVIDER_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL11B_O2S_CLOCK_DIVIDER_A_N_LEN    , 10  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_CLOCK_DIVIDER_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL11B_O2SCTRL1_A_N_RESERVED_14_16  , 14  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16 );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL11B_O2SCTRL1_A_N_RESERVED_14_16_LEN , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL11B_O2S_NR_OF_FRAMES_A_N         , 17  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_NR_OF_FRAMES_A_N );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL11B_O2S_BRIDGE_ENABLE_A_N        , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_BRIDGE_ENABLE_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL11B_O2SCTRL1_A_N_RESERVED_1      , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2SCTRL1_A_N_RESERVED_1 );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL11B_O2S_CPOL_A_N                 , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_CPOL_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL11B_O2S_CPHA_A_N                 , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_CPHA_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL11B_O2S_CLOCK_DIVIDER_A_N        , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_CLOCK_DIVIDER_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL11B_O2S_CLOCK_DIVIDER_A_N_LEN    , 10  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_CLOCK_DIVIDER_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL11B_O2SCTRL1_A_N_RESERVED_14_16  , 14  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16 );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL11B_O2SCTRL1_A_N_RESERVED_14_16_LEN , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL11B_O2S_NR_OF_FRAMES_A_N         , 17  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_NR_OF_FRAMES_A_N );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL20A_O2S_INTER_FRAME_DELAY_A_N    , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_INTER_FRAME_DELAY_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL20A_O2S_INTER_FRAME_DELAY_A_N_LEN , 17  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_INTER_FRAME_DELAY_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL20A_O2S_INTER_FRAME_DELAY_A_N    , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_INTER_FRAME_DELAY_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL20A_O2S_INTER_FRAME_DELAY_A_N_LEN , 17  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_INTER_FRAME_DELAY_A_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL20B_O2S_INTER_FRAME_DELAY_A_N    , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_INTER_FRAME_DELAY_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL20B_O2S_INTER_FRAME_DELAY_A_N_LEN , 17  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_INTER_FRAME_DELAY_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL20B_O2S_INTER_FRAME_DELAY_A_N    , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_INTER_FRAME_DELAY_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL20B_O2S_INTER_FRAME_DELAY_A_N_LEN , 17  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_INTER_FRAME_DELAY_A_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL21A_O2S_INTER_FRAME_DELAY_A_N    , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_INTER_FRAME_DELAY_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL21A_O2S_INTER_FRAME_DELAY_A_N_LEN , 17  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_INTER_FRAME_DELAY_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL21A_O2S_INTER_FRAME_DELAY_A_N    , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_INTER_FRAME_DELAY_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL21A_O2S_INTER_FRAME_DELAY_A_N_LEN , 17  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_INTER_FRAME_DELAY_A_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL21B_O2S_INTER_FRAME_DELAY_A_N    , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_INTER_FRAME_DELAY_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRL21B_O2S_INTER_FRAME_DELAY_A_N_LEN , 17  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_INTER_FRAME_DELAY_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL21B_O2S_INTER_FRAME_DELAY_A_N    , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_INTER_FRAME_DELAY_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRL21B_O2S_INTER_FRAME_DELAY_A_N_LEN , 17  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_INTER_FRAME_DELAY_A_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF0A_O2S_FRAME_SIZE_A_N           , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_FRAME_SIZE_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF0A_O2S_FRAME_SIZE_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_FRAME_SIZE_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF0A_O2S_OUT_COUNT1_A_N           , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_OUT_COUNT1_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF0A_O2S_OUT_COUNT1_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_OUT_COUNT1_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF0A_O2S_IN_DELAY1_A_N            , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_DELAY1_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF0A_O2S_IN_DELAY1_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_DELAY1_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF0A_O2S_IN_COUNT1_A_N            , 18  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_COUNT1_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF0A_O2S_IN_COUNT1_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_COUNT1_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF0A_O2S_FRAME_SIZE_A_N           , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_FRAME_SIZE_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF0A_O2S_FRAME_SIZE_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_FRAME_SIZE_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF0A_O2S_OUT_COUNT1_A_N           , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_OUT_COUNT1_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF0A_O2S_OUT_COUNT1_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_OUT_COUNT1_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF0A_O2S_IN_DELAY1_A_N            , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_DELAY1_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF0A_O2S_IN_DELAY1_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_DELAY1_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF0A_O2S_IN_COUNT1_A_N            , 18  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_COUNT1_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF0A_O2S_IN_COUNT1_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_COUNT1_A_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF0B_O2S_FRAME_SIZE_A_N           , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_FRAME_SIZE_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF0B_O2S_FRAME_SIZE_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_FRAME_SIZE_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF0B_O2S_OUT_COUNT1_A_N           , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_OUT_COUNT1_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF0B_O2S_OUT_COUNT1_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_OUT_COUNT1_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF0B_O2S_IN_DELAY1_A_N            , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_DELAY1_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF0B_O2S_IN_DELAY1_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_DELAY1_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF0B_O2S_IN_COUNT1_A_N            , 18  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_COUNT1_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF0B_O2S_IN_COUNT1_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_COUNT1_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF0B_O2S_FRAME_SIZE_A_N           , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_FRAME_SIZE_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF0B_O2S_FRAME_SIZE_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_FRAME_SIZE_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF0B_O2S_OUT_COUNT1_A_N           , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_OUT_COUNT1_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF0B_O2S_OUT_COUNT1_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_OUT_COUNT1_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF0B_O2S_IN_DELAY1_A_N            , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_DELAY1_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF0B_O2S_IN_DELAY1_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_DELAY1_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF0B_O2S_IN_COUNT1_A_N            , 18  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_COUNT1_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF0B_O2S_IN_COUNT1_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_COUNT1_A_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF1A_O2S_FRAME_SIZE_A_N           , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_FRAME_SIZE_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF1A_O2S_FRAME_SIZE_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_FRAME_SIZE_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF1A_O2S_OUT_COUNT1_A_N           , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_OUT_COUNT1_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF1A_O2S_OUT_COUNT1_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_OUT_COUNT1_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF1A_O2S_IN_DELAY1_A_N            , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_DELAY1_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF1A_O2S_IN_DELAY1_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_DELAY1_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF1A_O2S_IN_COUNT1_A_N            , 18  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_COUNT1_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF1A_O2S_IN_COUNT1_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_COUNT1_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF1A_O2S_FRAME_SIZE_A_N           , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_FRAME_SIZE_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF1A_O2S_FRAME_SIZE_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_FRAME_SIZE_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF1A_O2S_OUT_COUNT1_A_N           , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_OUT_COUNT1_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF1A_O2S_OUT_COUNT1_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_OUT_COUNT1_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF1A_O2S_IN_DELAY1_A_N            , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_DELAY1_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF1A_O2S_IN_DELAY1_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_DELAY1_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF1A_O2S_IN_COUNT1_A_N            , 18  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_COUNT1_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF1A_O2S_IN_COUNT1_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_COUNT1_A_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF1B_O2S_FRAME_SIZE_A_N           , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_FRAME_SIZE_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF1B_O2S_FRAME_SIZE_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_FRAME_SIZE_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF1B_O2S_OUT_COUNT1_A_N           , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_OUT_COUNT1_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF1B_O2S_OUT_COUNT1_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_OUT_COUNT1_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF1B_O2S_IN_DELAY1_A_N            , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_DELAY1_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF1B_O2S_IN_DELAY1_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_DELAY1_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF1B_O2S_IN_COUNT1_A_N            , 18  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_COUNT1_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLF1B_O2S_IN_COUNT1_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_COUNT1_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF1B_O2S_FRAME_SIZE_A_N           , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_FRAME_SIZE_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF1B_O2S_FRAME_SIZE_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_FRAME_SIZE_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF1B_O2S_OUT_COUNT1_A_N           , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_OUT_COUNT1_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF1B_O2S_OUT_COUNT1_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_OUT_COUNT1_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF1B_O2S_IN_DELAY1_A_N            , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_DELAY1_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF1B_O2S_IN_DELAY1_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_DELAY1_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF1B_O2S_IN_COUNT1_A_N            , 18  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_COUNT1_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLF1B_O2S_IN_COUNT1_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_COUNT1_A_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS0A_O2S_OUT_COUNT2_A_N           , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_OUT_COUNT2_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS0A_O2S_OUT_COUNT2_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_OUT_COUNT2_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS0A_O2S_IN_DELAY2_A_N            , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_DELAY2_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS0A_O2S_IN_DELAY2_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_DELAY2_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS0A_O2S_IN_COUNT2_A_N            , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_COUNT2_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS0A_O2S_IN_COUNT2_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_COUNT2_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS0A_O2S_OUT_COUNT2_A_N           , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_OUT_COUNT2_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS0A_O2S_OUT_COUNT2_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_OUT_COUNT2_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS0A_O2S_IN_DELAY2_A_N            , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_DELAY2_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS0A_O2S_IN_DELAY2_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_DELAY2_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS0A_O2S_IN_COUNT2_A_N            , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_COUNT2_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS0A_O2S_IN_COUNT2_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_COUNT2_A_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS0B_O2S_OUT_COUNT2_A_N           , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_OUT_COUNT2_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS0B_O2S_OUT_COUNT2_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_OUT_COUNT2_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS0B_O2S_IN_DELAY2_A_N            , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_DELAY2_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS0B_O2S_IN_DELAY2_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_DELAY2_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS0B_O2S_IN_COUNT2_A_N            , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_COUNT2_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS0B_O2S_IN_COUNT2_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_COUNT2_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS0B_O2S_OUT_COUNT2_A_N           , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_OUT_COUNT2_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS0B_O2S_OUT_COUNT2_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_OUT_COUNT2_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS0B_O2S_IN_DELAY2_A_N            , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_DELAY2_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS0B_O2S_IN_DELAY2_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_DELAY2_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS0B_O2S_IN_COUNT2_A_N            , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_COUNT2_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS0B_O2S_IN_COUNT2_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_COUNT2_A_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS1A_O2S_OUT_COUNT2_A_N           , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_OUT_COUNT2_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS1A_O2S_OUT_COUNT2_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_OUT_COUNT2_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS1A_O2S_IN_DELAY2_A_N            , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_DELAY2_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS1A_O2S_IN_DELAY2_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_DELAY2_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS1A_O2S_IN_COUNT2_A_N            , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_COUNT2_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS1A_O2S_IN_COUNT2_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_COUNT2_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS1A_O2S_OUT_COUNT2_A_N           , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_OUT_COUNT2_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS1A_O2S_OUT_COUNT2_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_OUT_COUNT2_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS1A_O2S_IN_DELAY2_A_N            , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_DELAY2_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS1A_O2S_IN_DELAY2_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_DELAY2_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS1A_O2S_IN_COUNT2_A_N            , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_COUNT2_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS1A_O2S_IN_COUNT2_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_COUNT2_A_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS1B_O2S_OUT_COUNT2_A_N           , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_OUT_COUNT2_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS1B_O2S_OUT_COUNT2_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_OUT_COUNT2_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS1B_O2S_IN_DELAY2_A_N            , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_DELAY2_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS1B_O2S_IN_DELAY2_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_DELAY2_A_N_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS1B_O2S_IN_COUNT2_A_N            , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_COUNT2_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SCTRLS1B_O2S_IN_COUNT2_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_IN_COUNT2_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS1B_O2S_OUT_COUNT2_A_N           , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_OUT_COUNT2_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS1B_O2S_OUT_COUNT2_A_N_LEN       , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_OUT_COUNT2_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS1B_O2S_IN_DELAY2_A_N            , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_DELAY2_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS1B_O2S_IN_DELAY2_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_DELAY2_A_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS1B_O2S_IN_COUNT2_A_N            , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_COUNT2_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SCTRLS1B_O2S_IN_COUNT2_A_N_LEN        , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_IN_COUNT2_A_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SRD0A_O2S_RDATA_A_N                   , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_RDATA_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SRD0A_O2S_RDATA_A_N_LEN               , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_RDATA_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SRD0A_O2S_RDATA_A_N                   , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2S_RDATA_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SRD0A_O2S_RDATA_A_N_LEN               , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2S_RDATA_A_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SRD0B_O2S_RDATA_A_N                   , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_RDATA_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SRD0B_O2S_RDATA_A_N_LEN               , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_RDATA_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SRD0B_O2S_RDATA_A_N                   , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2S_RDATA_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SRD0B_O2S_RDATA_A_N_LEN               , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2S_RDATA_A_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SRD1A_O2S_RDATA_A_N                   , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_RDATA_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SRD1A_O2S_RDATA_A_N_LEN               , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_RDATA_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SRD1A_O2S_RDATA_A_N                   , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2S_RDATA_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SRD1A_O2S_RDATA_A_N_LEN               , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2S_RDATA_A_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SRD1B_O2S_RDATA_A_N                   , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_RDATA_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SRD1B_O2S_RDATA_A_N_LEN               , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_RDATA_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SRD1B_O2S_RDATA_A_N                   , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2S_RDATA_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SRD1B_O2S_RDATA_A_N_LEN               , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2S_RDATA_A_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST0A_O2S_ONGOING_A_N                 , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_ONGOING_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST0A_O2SST_A_N_RESERVED_1_4          , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SST_A_N_RESERVED_1_4 );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST0A_O2SST_A_N_RESERVED_1_4_LEN      , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SST_A_N_RESERVED_1_4_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST0A_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N , 5   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      ,
+           SH_FLD_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST0A_O2SST_A_N_RESERVED_6            , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SST_A_N_RESERVED_6 );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST0A_O2S_FSM_ERR_A_N                 , 7   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_FSM_ERR_A_N );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST0A_O2S_ONGOING_A_N                 , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2S_ONGOING_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST0A_O2SST_A_N_RESERVED_1_4          , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2SST_A_N_RESERVED_1_4 );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST0A_O2SST_A_N_RESERVED_1_4_LEN      , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2SST_A_N_RESERVED_1_4_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST0A_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST0A_O2SST_A_N_RESERVED_6            , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2SST_A_N_RESERVED_6 );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST0A_O2S_FSM_ERR_A_N                 , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2S_FSM_ERR_A_N );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST0B_O2S_ONGOING_A_N                 , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_ONGOING_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST0B_O2SST_A_N_RESERVED_1_4          , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SST_A_N_RESERVED_1_4 );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST0B_O2SST_A_N_RESERVED_1_4_LEN      , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SST_A_N_RESERVED_1_4_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST0B_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N , 5   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      ,
+           SH_FLD_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST0B_O2SST_A_N_RESERVED_6            , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SST_A_N_RESERVED_6 );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST0B_O2S_FSM_ERR_A_N                 , 7   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_FSM_ERR_A_N );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST0B_O2S_ONGOING_A_N                 , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2S_ONGOING_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST0B_O2SST_A_N_RESERVED_1_4          , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2SST_A_N_RESERVED_1_4 );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST0B_O2SST_A_N_RESERVED_1_4_LEN      , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2SST_A_N_RESERVED_1_4_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST0B_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST0B_O2SST_A_N_RESERVED_6            , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2SST_A_N_RESERVED_6 );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST0B_O2S_FSM_ERR_A_N                 , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2S_FSM_ERR_A_N );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST1A_O2S_ONGOING_A_N                 , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_ONGOING_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST1A_O2SST_A_N_RESERVED_1_4          , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SST_A_N_RESERVED_1_4 );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST1A_O2SST_A_N_RESERVED_1_4_LEN      , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SST_A_N_RESERVED_1_4_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST1A_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N , 5   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      ,
+           SH_FLD_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST1A_O2SST_A_N_RESERVED_6            , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SST_A_N_RESERVED_6 );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST1A_O2S_FSM_ERR_A_N                 , 7   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_FSM_ERR_A_N );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST1A_O2S_ONGOING_A_N                 , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2S_ONGOING_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST1A_O2SST_A_N_RESERVED_1_4          , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2SST_A_N_RESERVED_1_4 );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST1A_O2SST_A_N_RESERVED_1_4_LEN      , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2SST_A_N_RESERVED_1_4_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST1A_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST1A_O2SST_A_N_RESERVED_6            , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2SST_A_N_RESERVED_6 );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST1A_O2S_FSM_ERR_A_N                 , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2S_FSM_ERR_A_N );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST1B_O2S_ONGOING_A_N                 , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_ONGOING_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST1B_O2SST_A_N_RESERVED_1_4          , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SST_A_N_RESERVED_1_4 );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST1B_O2SST_A_N_RESERVED_1_4_LEN      , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SST_A_N_RESERVED_1_4_LEN );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST1B_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N , 5   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      ,
+           SH_FLD_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST1B_O2SST_A_N_RESERVED_6            , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2SST_A_N_RESERVED_6 );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SST1B_O2S_FSM_ERR_A_N                 , 7   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_FSM_ERR_A_N );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST1B_O2S_ONGOING_A_N                 , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2S_ONGOING_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST1B_O2SST_A_N_RESERVED_1_4          , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2SST_A_N_RESERVED_1_4 );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST1B_O2SST_A_N_RESERVED_1_4_LEN      , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2SST_A_N_RESERVED_1_4_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST1B_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST1B_O2SST_A_N_RESERVED_6            , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2SST_A_N_RESERVED_6 );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SST1B_O2S_FSM_ERR_A_N                 , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_O2S_FSM_ERR_A_N );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SWD0A_O2S_WDATA_A_N                   , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_WDATA_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SWD0A_O2S_WDATA_A_N_LEN               , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_WDATA_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SWD0A_O2S_WDATA_A_N                   , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_WDATA_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SWD0A_O2S_WDATA_A_N_LEN               , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_WDATA_A_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SWD0B_O2S_WDATA_A_N                   , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_WDATA_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SWD0B_O2S_WDATA_A_N_LEN               , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_WDATA_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SWD0B_O2S_WDATA_A_N                   , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_WDATA_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SWD0B_O2S_WDATA_A_N_LEN               , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_WDATA_A_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SWD1A_O2S_WDATA_A_N                   , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_WDATA_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SWD1A_O2S_WDATA_A_N_LEN               , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_WDATA_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SWD1A_O2S_WDATA_A_N                   , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_WDATA_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SWD1A_O2S_WDATA_A_N_LEN               , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_WDATA_A_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_O2SWD1B_O2S_WDATA_A_N                   , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_WDATA_A_N );
+REG64_FLD( PU_GPE1_OCB_OCI_O2SWD1B_O2S_WDATA_A_N_LEN               , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI      , SH_FLD_O2S_WDATA_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_O2SWD1B_O2S_WDATA_A_N                   , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_WDATA_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_O2SWD1B_O2S_WDATA_A_N_LEN               , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_O2S_WDATA_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_ENABLE           , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_ENABLE );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR0_SPARE_0                        , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_SPARE_0    );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR0_SPARE_0_LEN                    , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_SPARE_0_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_BAR              , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_BAR );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_BAR_LEN          , 17  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_BAR_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_MASK             , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_MASK );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_MASK_LEN         , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_MASK_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_ENABLE           , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_ENABLE );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR0_SPARE_0                        , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE_0    );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR0_SPARE_0_LEN                    , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE_0_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_BAR              , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_BAR );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_BAR_LEN          , 17  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_BAR_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_MASK             , 20  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_MASK );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_MASK_LEN         , 12  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_MASK_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_ENABLE           , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_ENABLE );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR1_SPARE_0                        , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_SPARE_0    );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR1_SPARE_0_LEN                    , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_SPARE_0_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_BAR              , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_BAR );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_BAR_LEN          , 17  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_BAR_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_MASK             , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_MASK );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_MASK_LEN         , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_MASK_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_ENABLE           , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_ENABLE );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR1_SPARE_0                        , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE_0    );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR1_SPARE_0_LEN                    , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE_0_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_BAR              , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_BAR );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_BAR_LEN          , 17  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_BAR_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_MASK             , 20  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_MASK );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_MASK_LEN         , 12  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_MASK_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_ENABLE           , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_ENABLE );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR2_SPARE_0                        , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_SPARE_0    );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR2_SPARE_0_LEN                    , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_SPARE_0_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_BAR              , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_BAR );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_BAR_LEN          , 17  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_BAR_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_MASK             , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_MASK );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_MASK_LEN         , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_MASK_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_ENABLE           , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_ENABLE );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR2_SPARE_0                        , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE_0    );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR2_SPARE_0_LEN                    , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE_0_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_BAR              , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_BAR );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_BAR_LEN          , 17  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_BAR_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_MASK             , 20  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_MASK );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_MASK_LEN         , 12  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_MASK_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_ENABLE           , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_ENABLE );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR3_SPARE_0                        , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_SPARE_0    );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR3_SPARE_0_LEN                    , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_SPARE_0_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_BAR              , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_BAR );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_BAR_LEN          , 17  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_BAR_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_MASK             , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_MASK );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_MASK_LEN         , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_MASK_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_ENABLE           , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_ENABLE );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR3_SPARE_0                        , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE_0    );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR3_SPARE_0_LEN                    , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE_0_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_BAR              , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_BAR );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_BAR_LEN          , 17  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_BAR_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_MASK             , 20  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_MASK );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_MASK_LEN         , 12  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_MASK_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_REGION          , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_REGION );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_REGION_LEN      , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_REGION_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_BASE            , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_BASE );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_BASE_LEN        , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_BASE_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_REGION          , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_REGION );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_REGION_LEN      , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_REGION_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_BASE            , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_BASE );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_BASE_LEN        , 7   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_BASE_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_REGION          , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_REGION );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_REGION_LEN      , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_REGION_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_BASE            , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_BASE );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_BASE_LEN        , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_BASE_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_REGION          , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_REGION );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_REGION_LEN      , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_REGION_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_BASE            , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_BASE );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_BASE_LEN        , 7   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_BASE_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_REGION          , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_REGION );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_REGION_LEN      , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_REGION_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_BASE            , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_BASE );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_BASE_LEN        , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_BASE_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_REGION          , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_REGION );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_REGION_LEN      , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_REGION_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_BASE            , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_BASE );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_BASE_LEN        , 7   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_BASE_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_REGION          , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_REGION );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_REGION_LEN      , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_REGION_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_BASE            , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_BASE );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_BASE_LEN        , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_LINEAR_WINDOW_BASE_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_REGION          , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_REGION );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_REGION_LEN      , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_REGION_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_BASE            , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_BASE );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_BASE_LEN        , 7   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_BASE_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSR0_LINEAR_WINDOW_SCRESP           , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_LINEAR_WINDOW_SCRESP );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSR0_LINEAR_WINDOW_SCRESP_LEN       , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_LINEAR_WINDOW_SCRESP_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSR0_SPARE0                         , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_SPARE0     );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSR0_SPARE0_LEN                     , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_SPARE0_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSR0_LINEAR_WINDOW_SCRESP           , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_SCRESP );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSR0_LINEAR_WINDOW_SCRESP_LEN       , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_SCRESP_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSR0_SPARE0                         , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE0     );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSR0_SPARE0_LEN                     , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE0_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSR1_LINEAR_WINDOW_SCRESP           , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_LINEAR_WINDOW_SCRESP );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSR1_LINEAR_WINDOW_SCRESP_LEN       , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_LINEAR_WINDOW_SCRESP_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSR1_SPARE0                         , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_SPARE0     );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSR1_SPARE0_LEN                     , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_SPARE0_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSR1_LINEAR_WINDOW_SCRESP           , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_SCRESP );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSR1_LINEAR_WINDOW_SCRESP_LEN       , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_SCRESP_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSR1_SPARE0                         , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE0     );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSR1_SPARE0_LEN                     , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE0_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSR2_LINEAR_WINDOW_SCRESP           , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_LINEAR_WINDOW_SCRESP );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSR2_LINEAR_WINDOW_SCRESP_LEN       , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_LINEAR_WINDOW_SCRESP_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSR2_SPARE0                         , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_SPARE0     );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSR2_SPARE0_LEN                     , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_SPARE0_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSR2_LINEAR_WINDOW_SCRESP           , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_SCRESP );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSR2_LINEAR_WINDOW_SCRESP_LEN       , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_SCRESP_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSR2_SPARE0                         , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE0     );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSR2_SPARE0_LEN                     , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE0_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSR3_LINEAR_WINDOW_SCRESP           , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_LINEAR_WINDOW_SCRESP );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSR3_LINEAR_WINDOW_SCRESP_LEN       , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_LINEAR_WINDOW_SCRESP_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSR3_SPARE0                         , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_SPARE0     );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBLWSR3_SPARE0_LEN                     , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_SPARE0_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSR3_LINEAR_WINDOW_SCRESP           , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_SCRESP );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSR3_LINEAR_WINDOW_SCRESP_LEN       , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_LINEAR_WINDOW_SCRESP_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSR3_SPARE0                         , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE0     );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBLWSR3_SPARE0_LEN                     , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE0_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSES0_PUSH_READ_UNDERFLOW             , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PUSH_READ_UNDERFLOW );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSES0_PULL_WRITE_OVERFLOW             , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PULL_WRITE_OVERFLOW );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSES0_PUSH_READ_UNDERFLOW             , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_READ_UNDERFLOW );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSES0_PULL_WRITE_OVERFLOW             , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_WRITE_OVERFLOW );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSES1_PUSH_READ_UNDERFLOW             , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PUSH_READ_UNDERFLOW );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSES1_PULL_WRITE_OVERFLOW             , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PULL_WRITE_OVERFLOW );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSES1_PUSH_READ_UNDERFLOW             , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_READ_UNDERFLOW );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSES1_PULL_WRITE_OVERFLOW             , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_WRITE_OVERFLOW );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSES2_PUSH_READ_UNDERFLOW             , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PUSH_READ_UNDERFLOW );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSES2_PULL_WRITE_OVERFLOW             , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PULL_WRITE_OVERFLOW );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSES2_PUSH_READ_UNDERFLOW             , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_READ_UNDERFLOW );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSES2_PULL_WRITE_OVERFLOW             , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_WRITE_OVERFLOW );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSES3_PUSH_READ_UNDERFLOW             , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PUSH_READ_UNDERFLOW );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSES3_PULL_WRITE_OVERFLOW             , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PULL_WRITE_OVERFLOW );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSES3_PUSH_READ_UNDERFLOW             , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_READ_UNDERFLOW );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSES3_PULL_WRITE_OVERFLOW             , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_WRITE_OVERFLOW );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHBR0_PUSH_REGION                    , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PUSH_REGION );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHBR0_PUSH_REGION_LEN                , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PUSH_REGION_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHBR0_PUSH_START                     , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PUSH_START );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHBR0_PUSH_START_LEN                 , 26  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PUSH_START_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHBR0_PUSH_REGION                    , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_REGION );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHBR0_PUSH_REGION_LEN                , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_REGION_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHBR0_PUSH_START                     , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_START );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHBR0_PUSH_START_LEN                 , 26  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_START_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHBR1_PUSH_REGION                    , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PUSH_REGION );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHBR1_PUSH_REGION_LEN                , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PUSH_REGION_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHBR1_PUSH_START                     , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PUSH_START );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHBR1_PUSH_START_LEN                 , 26  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PUSH_START_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHBR1_PUSH_REGION                    , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_REGION );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHBR1_PUSH_REGION_LEN                , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_REGION_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHBR1_PUSH_START                     , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_START );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHBR1_PUSH_START_LEN                 , 26  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_START_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHBR2_PUSH_REGION                    , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PUSH_REGION );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHBR2_PUSH_REGION_LEN                , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PUSH_REGION_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHBR2_PUSH_START                     , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PUSH_START );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHBR2_PUSH_START_LEN                 , 26  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PUSH_START_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHBR2_PUSH_REGION                    , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_REGION );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHBR2_PUSH_REGION_LEN                , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_REGION_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHBR2_PUSH_START                     , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_START );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHBR2_PUSH_START_LEN                 , 26  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_START_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHBR3_PUSH_REGION                    , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PUSH_REGION );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHBR3_PUSH_REGION_LEN                , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PUSH_REGION_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHBR3_PUSH_START                     , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PUSH_START );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHBR3_PUSH_START_LEN                 , 26  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PUSH_START_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHBR3_PUSH_REGION                    , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_REGION );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHBR3_PUSH_REGION_LEN                , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_REGION_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHBR3_PUSH_START                     , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_START );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHBR3_PUSH_START_LEN                 , 26  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_START_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS0_PUSH_FULL                      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_FULL  );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS0_PUSH_EMPTY                     , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_EMPTY );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS0_SPARE                          , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS0_SPARE_LEN                      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS0_PUSH_INTR_ACTION_0_1           , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_INTR_ACTION_0_1 );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS0_PUSH_INTR_ACTION_0_1_LEN       , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS0_PUSH_LENGTH                    , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_LENGTH );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS0_PUSH_LENGTH_LEN                , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_LENGTH_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS0_PUSH_WRITE_PTR                 , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_WRITE_PTR );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS0_PUSH_WRITE_PTR_LEN             , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_WRITE_PTR_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS0_PUSH_READ_PTR                  , 21  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_READ_PTR );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS0_PUSH_READ_PTR_LEN              , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_READ_PTR_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS0_PUSH_ENABLE                    , 31  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_ENABLE );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS0_PUSH_FULL                      , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_FULL  );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS0_PUSH_EMPTY                     , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_EMPTY );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS0_SPARE                          , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS0_SPARE_LEN                      , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS0_PUSH_INTR_ACTION_0_1           , 4   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_INTR_ACTION_0_1 );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS0_PUSH_INTR_ACTION_0_1_LEN       , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS0_PUSH_LENGTH                    , 6   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_LENGTH );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS0_PUSH_LENGTH_LEN                , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_LENGTH_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS0_PUSH_WRITE_PTR                 , 13  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_WRITE_PTR );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS0_PUSH_WRITE_PTR_LEN             , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_WRITE_PTR_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS0_PUSH_READ_PTR                  , 21  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_READ_PTR );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS0_PUSH_READ_PTR_LEN              , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_READ_PTR_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS0_PUSH_ENABLE                    , 31  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_ENABLE );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS1_PUSH_FULL                      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_FULL  );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS1_PUSH_EMPTY                     , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_EMPTY );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS1_SPARE                          , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS1_SPARE_LEN                      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS1_PUSH_INTR_ACTION_0_1           , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_INTR_ACTION_0_1 );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS1_PUSH_INTR_ACTION_0_1_LEN       , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS1_PUSH_LENGTH                    , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_LENGTH );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS1_PUSH_LENGTH_LEN                , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_LENGTH_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS1_PUSH_WRITE_PTR                 , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_WRITE_PTR );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS1_PUSH_WRITE_PTR_LEN             , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_WRITE_PTR_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS1_PUSH_READ_PTR                  , 21  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_READ_PTR );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS1_PUSH_READ_PTR_LEN              , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_READ_PTR_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS1_PUSH_ENABLE                    , 31  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_ENABLE );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS1_PUSH_FULL                      , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_FULL  );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS1_PUSH_EMPTY                     , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_EMPTY );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS1_SPARE                          , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS1_SPARE_LEN                      , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS1_PUSH_INTR_ACTION_0_1           , 4   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_INTR_ACTION_0_1 );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS1_PUSH_INTR_ACTION_0_1_LEN       , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS1_PUSH_LENGTH                    , 6   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_LENGTH );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS1_PUSH_LENGTH_LEN                , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_LENGTH_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS1_PUSH_WRITE_PTR                 , 13  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_WRITE_PTR );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS1_PUSH_WRITE_PTR_LEN             , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_WRITE_PTR_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS1_PUSH_READ_PTR                  , 21  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_READ_PTR );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS1_PUSH_READ_PTR_LEN              , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_READ_PTR_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS1_PUSH_ENABLE                    , 31  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_ENABLE );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS2_PUSH_FULL                      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_FULL  );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS2_PUSH_EMPTY                     , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_EMPTY );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS2_SPARE                          , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS2_SPARE_LEN                      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS2_PUSH_INTR_ACTION_0_1           , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_INTR_ACTION_0_1 );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS2_PUSH_INTR_ACTION_0_1_LEN       , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS2_PUSH_LENGTH                    , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_LENGTH );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS2_PUSH_LENGTH_LEN                , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_LENGTH_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS2_PUSH_WRITE_PTR                 , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_WRITE_PTR );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS2_PUSH_WRITE_PTR_LEN             , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_WRITE_PTR_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS2_PUSH_READ_PTR                  , 21  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_READ_PTR );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS2_PUSH_READ_PTR_LEN              , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_READ_PTR_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS2_PUSH_ENABLE                    , 31  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_ENABLE );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS2_PUSH_FULL                      , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_FULL  );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS2_PUSH_EMPTY                     , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_EMPTY );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS2_SPARE                          , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS2_SPARE_LEN                      , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS2_PUSH_INTR_ACTION_0_1           , 4   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_INTR_ACTION_0_1 );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS2_PUSH_INTR_ACTION_0_1_LEN       , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS2_PUSH_LENGTH                    , 6   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_LENGTH );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS2_PUSH_LENGTH_LEN                , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_LENGTH_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS2_PUSH_WRITE_PTR                 , 13  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_WRITE_PTR );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS2_PUSH_WRITE_PTR_LEN             , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_WRITE_PTR_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS2_PUSH_READ_PTR                  , 21  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_READ_PTR );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS2_PUSH_READ_PTR_LEN              , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_READ_PTR_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS2_PUSH_ENABLE                    , 31  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_ENABLE );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS3_PUSH_FULL                      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_FULL  );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS3_PUSH_EMPTY                     , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_EMPTY );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS3_SPARE                          , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS3_SPARE_LEN                      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS3_PUSH_INTR_ACTION_0_1           , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_INTR_ACTION_0_1 );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS3_PUSH_INTR_ACTION_0_1_LEN       , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS3_PUSH_LENGTH                    , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_LENGTH );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS3_PUSH_LENGTH_LEN                , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_LENGTH_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS3_PUSH_WRITE_PTR                 , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_WRITE_PTR );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS3_PUSH_WRITE_PTR_LEN             , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_WRITE_PTR_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS3_PUSH_READ_PTR                  , 21  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_READ_PTR );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS3_PUSH_READ_PTR_LEN              , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_READ_PTR_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSHCS3_PUSH_ENABLE                    , 31  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PUSH_ENABLE );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS3_PUSH_FULL                      , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_FULL  );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS3_PUSH_EMPTY                     , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_EMPTY );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS3_SPARE                          , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS3_SPARE_LEN                      , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS3_PUSH_INTR_ACTION_0_1           , 4   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_INTR_ACTION_0_1 );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS3_PUSH_INTR_ACTION_0_1_LEN       , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS3_PUSH_LENGTH                    , 6   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_LENGTH );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS3_PUSH_LENGTH_LEN                , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_LENGTH_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS3_PUSH_WRITE_PTR                 , 13  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_WRITE_PTR );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS3_PUSH_WRITE_PTR_LEN             , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_WRITE_PTR_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS3_PUSH_READ_PTR                  , 21  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_READ_PTR );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS3_PUSH_READ_PTR_LEN              , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_READ_PTR_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSHCS3_PUSH_ENABLE                    , 31  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PUSH_ENABLE );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLBR0_PULL_REGION                    , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PULL_REGION );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLBR0_PULL_REGION_LEN                , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PULL_REGION_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLBR0_PULL_START                     , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PULL_START );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLBR0_PULL_START_LEN                 , 26  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PULL_START_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLBR0_PULL_REGION                    , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_REGION );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLBR0_PULL_REGION_LEN                , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_REGION_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLBR0_PULL_START                     , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_START );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLBR0_PULL_START_LEN                 , 26  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_START_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLBR1_PULL_REGION                    , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PULL_REGION );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLBR1_PULL_REGION_LEN                , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PULL_REGION_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLBR1_PULL_START                     , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PULL_START );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLBR1_PULL_START_LEN                 , 26  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PULL_START_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLBR1_PULL_REGION                    , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_REGION );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLBR1_PULL_REGION_LEN                , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_REGION_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLBR1_PULL_START                     , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_START );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLBR1_PULL_START_LEN                 , 26  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_START_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLBR2_PULL_REGION                    , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PULL_REGION );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLBR2_PULL_REGION_LEN                , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PULL_REGION_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLBR2_PULL_START                     , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PULL_START );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLBR2_PULL_START_LEN                 , 26  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PULL_START_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLBR2_PULL_REGION                    , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_REGION );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLBR2_PULL_REGION_LEN                , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_REGION_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLBR2_PULL_START                     , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_START );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLBR2_PULL_START_LEN                 , 26  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_START_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLBR3_PULL_REGION                    , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PULL_REGION );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLBR3_PULL_REGION_LEN                , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PULL_REGION_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLBR3_PULL_START                     , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PULL_START );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLBR3_PULL_START_LEN                 , 26  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PULL_START_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLBR3_PULL_REGION                    , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_REGION );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLBR3_PULL_REGION_LEN                , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_REGION_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLBR3_PULL_START                     , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_START );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLBR3_PULL_START_LEN                 , 26  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_START_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS0_PULL_FULL                      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_FULL  );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS0_PULL_EMPTY                     , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_EMPTY );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS0_SPARE                          , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS0_SPARE_LEN                      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS0_PULL_INTR_ACTION_0_1           , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_INTR_ACTION_0_1 );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS0_PULL_INTR_ACTION_0_1_LEN       , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS0_PULL_LENGTH                    , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_LENGTH );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS0_PULL_LENGTH_LEN                , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_LENGTH_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS0_PULL_WRITE_PTR                 , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_WRITE_PTR );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS0_PULL_WRITE_PTR_LEN             , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_WRITE_PTR_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS0_PULL_READ_PTR                  , 21  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_READ_PTR );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS0_PULL_READ_PTR_LEN              , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_READ_PTR_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS0_PULL_ENABLE                    , 31  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_ENABLE );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS0_PULL_FULL                      , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_FULL  );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS0_PULL_EMPTY                     , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_EMPTY );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS0_SPARE                          , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS0_SPARE_LEN                      , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS0_PULL_INTR_ACTION_0_1           , 4   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_INTR_ACTION_0_1 );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS0_PULL_INTR_ACTION_0_1_LEN       , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS0_PULL_LENGTH                    , 6   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_LENGTH );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS0_PULL_LENGTH_LEN                , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_LENGTH_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS0_PULL_WRITE_PTR                 , 13  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_WRITE_PTR );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS0_PULL_WRITE_PTR_LEN             , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_WRITE_PTR_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS0_PULL_READ_PTR                  , 21  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_READ_PTR );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS0_PULL_READ_PTR_LEN              , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_READ_PTR_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS0_PULL_ENABLE                    , 31  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_ENABLE );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS1_PULL_FULL                      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_FULL  );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS1_PULL_EMPTY                     , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_EMPTY );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS1_SPARE                          , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS1_SPARE_LEN                      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS1_PULL_INTR_ACTION_0_1           , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_INTR_ACTION_0_1 );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS1_PULL_INTR_ACTION_0_1_LEN       , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS1_PULL_LENGTH                    , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_LENGTH );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS1_PULL_LENGTH_LEN                , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_LENGTH_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS1_PULL_WRITE_PTR                 , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_WRITE_PTR );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS1_PULL_WRITE_PTR_LEN             , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_WRITE_PTR_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS1_PULL_READ_PTR                  , 21  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_READ_PTR );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS1_PULL_READ_PTR_LEN              , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_READ_PTR_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS1_PULL_ENABLE                    , 31  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_ENABLE );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS1_PULL_FULL                      , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_FULL  );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS1_PULL_EMPTY                     , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_EMPTY );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS1_SPARE                          , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS1_SPARE_LEN                      , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS1_PULL_INTR_ACTION_0_1           , 4   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_INTR_ACTION_0_1 );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS1_PULL_INTR_ACTION_0_1_LEN       , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS1_PULL_LENGTH                    , 6   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_LENGTH );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS1_PULL_LENGTH_LEN                , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_LENGTH_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS1_PULL_WRITE_PTR                 , 13  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_WRITE_PTR );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS1_PULL_WRITE_PTR_LEN             , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_WRITE_PTR_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS1_PULL_READ_PTR                  , 21  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_READ_PTR );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS1_PULL_READ_PTR_LEN              , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_READ_PTR_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS1_PULL_ENABLE                    , 31  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_ENABLE );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS2_PULL_FULL                      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_FULL  );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS2_PULL_EMPTY                     , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_EMPTY );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS2_SPARE                          , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS2_SPARE_LEN                      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS2_PULL_INTR_ACTION_0_1           , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_INTR_ACTION_0_1 );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS2_PULL_INTR_ACTION_0_1_LEN       , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS2_PULL_LENGTH                    , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_LENGTH );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS2_PULL_LENGTH_LEN                , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_LENGTH_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS2_PULL_WRITE_PTR                 , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_WRITE_PTR );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS2_PULL_WRITE_PTR_LEN             , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_WRITE_PTR_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS2_PULL_READ_PTR                  , 21  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_READ_PTR );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS2_PULL_READ_PTR_LEN              , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_READ_PTR_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS2_PULL_ENABLE                    , 31  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_ENABLE );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS2_PULL_FULL                      , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_FULL  );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS2_PULL_EMPTY                     , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_EMPTY );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS2_SPARE                          , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS2_SPARE_LEN                      , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS2_PULL_INTR_ACTION_0_1           , 4   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_INTR_ACTION_0_1 );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS2_PULL_INTR_ACTION_0_1_LEN       , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS2_PULL_LENGTH                    , 6   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_LENGTH );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS2_PULL_LENGTH_LEN                , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_LENGTH_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS2_PULL_WRITE_PTR                 , 13  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_WRITE_PTR );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS2_PULL_WRITE_PTR_LEN             , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_WRITE_PTR_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS2_PULL_READ_PTR                  , 21  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_READ_PTR );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS2_PULL_READ_PTR_LEN              , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_READ_PTR_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS2_PULL_ENABLE                    , 31  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_ENABLE );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS3_PULL_FULL                      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_FULL  );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS3_PULL_EMPTY                     , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_EMPTY );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS3_SPARE                          , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS3_SPARE_LEN                      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS3_PULL_INTR_ACTION_0_1           , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_INTR_ACTION_0_1 );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS3_PULL_INTR_ACTION_0_1_LEN       , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS3_PULL_LENGTH                    , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_LENGTH );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS3_PULL_LENGTH_LEN                , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_LENGTH_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS3_PULL_WRITE_PTR                 , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_WRITE_PTR );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS3_PULL_WRITE_PTR_LEN             , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_WRITE_PTR_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS3_PULL_READ_PTR                  , 21  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_READ_PTR );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS3_PULL_READ_PTR_LEN              , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_READ_PTR_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCBSLCS3_PULL_ENABLE                    , 31  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_PULL_ENABLE );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS3_PULL_FULL                      , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_FULL  );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS3_PULL_EMPTY                     , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_EMPTY );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS3_SPARE                          , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS3_SPARE_LEN                      , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS3_PULL_INTR_ACTION_0_1           , 4   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_INTR_ACTION_0_1 );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS3_PULL_INTR_ACTION_0_1_LEN       , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS3_PULL_LENGTH                    , 6   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_LENGTH );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS3_PULL_LENGTH_LEN                , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_LENGTH_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS3_PULL_WRITE_PTR                 , 13  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_WRITE_PTR );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS3_PULL_WRITE_PTR_LEN             , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_WRITE_PTR_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS3_PULL_READ_PTR                  , 21  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_READ_PTR );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS3_PULL_READ_PTR_LEN              , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_READ_PTR_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCBSLCS3_PULL_ENABLE                    , 31  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PULL_ENABLE );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCCFLG_OCC_FLAGS                        , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCC_FLAGS  );
+REG64_FLD( PU_GPE6_OCB_OCI_OCCFLG_OCC_FLAGS_LEN                    , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCC_FLAGS_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCCFLG_OCC_FLAGS                        , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_OCC_FLAGS  );
+REG64_FLD( PU_GPE0_OCB_OCI_OCCFLG_OCC_FLAGS_LEN                    , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_OCC_FLAGS_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCCHBR_OCC_HEARTBEAT_COUNT              , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCC_HEARTBEAT_COUNT );
+REG64_FLD( PU_GPE6_OCB_OCI_OCCHBR_OCC_HEARTBEAT_COUNT_LEN          , 16  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCC_HEARTBEAT_COUNT_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCCHBR_OCC_HEARTBEAT_EN                 , 16  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCC_HEARTBEAT_EN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCCHBR_OCC_HEARTBEAT_COUNT              , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_OCC_HEARTBEAT_COUNT );
+REG64_FLD( PU_GPE0_OCB_OCI_OCCHBR_OCC_HEARTBEAT_COUNT_LEN          , 16  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_OCC_HEARTBEAT_COUNT_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCCHBR_OCC_HEARTBEAT_EN                 , 16  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_OCC_HEARTBEAT_EN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCCMISC_CORE_EXT_INTR                   , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2    , SH_FLD_CORE_EXT_INTR );
+REG64_FLD( PU_GPE6_OCB_OCI_OCCMISC_SPARE_1_3                       , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2    , SH_FLD_SPARE_1_3  );
+REG64_FLD( PU_GPE6_OCB_OCI_OCCMISC_SPARE_1_3_LEN                   , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2    , SH_FLD_SPARE_1_3_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCCMISC_PVREF_ERROR_EN                  , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2    , SH_FLD_PVREF_ERROR_EN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCCMISC_PVREF_ERROR_EN_LEN              , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2    , SH_FLD_PVREF_ERROR_EN_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCCMISC_PVREF_ERROR_GROSS               , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2    , SH_FLD_PVREF_ERROR_GROSS );
+REG64_FLD( PU_GPE6_OCB_OCI_OCCMISC_PVREF_ERROR_FINE                , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2    , SH_FLD_PVREF_ERROR_FINE );
+REG64_FLD( PU_GPE6_OCB_OCI_OCCMISC_SPARE                           , 8   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2    , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE6_OCB_OCI_OCCMISC_SPARE_LEN                       , 8   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2    , SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCCMISC_CORE_EXT_INTR                   , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_CORE_EXT_INTR );
+REG64_FLD( PU_GPE0_OCB_OCI_OCCMISC_SPARE_1_3                       , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_SPARE_1_3  );
+REG64_FLD( PU_GPE0_OCB_OCI_OCCMISC_SPARE_1_3_LEN                   , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_SPARE_1_3_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCCMISC_PVREF_ERROR_EN                  , 4   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PVREF_ERROR_EN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCCMISC_PVREF_ERROR_EN_LEN              , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PVREF_ERROR_EN_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCCMISC_PVREF_ERROR_GROSS               , 6   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PVREF_ERROR_GROSS );
+REG64_FLD( PU_GPE0_OCB_OCI_OCCMISC_PVREF_ERROR_FINE                , 7   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PVREF_ERROR_FINE );
+REG64_FLD( PU_GPE0_OCB_OCI_OCCMISC_SPARE                           , 8   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE0_OCB_OCI_OCCMISC_SPARE_LEN                       , 8   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCCS0_OCC_SCRATCH_N                     , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCC_SCRATCH_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OCCS0_OCC_SCRATCH_N_LEN                 , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCC_SCRATCH_N_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCCS0_OCC_SCRATCH_N                     , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_OCC_SCRATCH_N );
+REG64_FLD( PU_GPE0_OCB_OCI_OCCS0_OCC_SCRATCH_N_LEN                 , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_OCC_SCRATCH_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCCS1_OCC_SCRATCH_N                     , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCC_SCRATCH_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OCCS1_OCC_SCRATCH_N_LEN                 , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCC_SCRATCH_N_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCCS1_OCC_SCRATCH_N                     , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_OCC_SCRATCH_N );
+REG64_FLD( PU_GPE0_OCB_OCI_OCCS1_OCC_SCRATCH_N_LEN                 , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_OCC_SCRATCH_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCCS2_OCC_SCRATCH_N                     , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCC_SCRATCH_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OCCS2_OCC_SCRATCH_N_LEN                 , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCC_SCRATCH_N_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCCS2_OCC_SCRATCH_N                     , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_OCC_SCRATCH_N );
+REG64_FLD( PU_GPE0_OCB_OCI_OCCS2_OCC_SCRATCH_N_LEN                 , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_OCC_SCRATCH_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_M0_PRIORITY                      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_M0_PRIORITY );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_M0_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_M0_PRIORITY_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_M1_PRIORITY                      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_M1_PRIORITY );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_M1_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_M1_PRIORITY_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_M2_PRIORITY                      , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_M2_PRIORITY );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_M2_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_M2_PRIORITY_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_M3_PRIORITY                      , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_M3_PRIORITY );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_M3_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_M3_PRIORITY_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_M4_PRIORITY                      , 8   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_M4_PRIORITY );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_M4_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_M4_PRIORITY_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_M5_PRIORITY                      , 10  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_M5_PRIORITY );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_M5_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_M5_PRIORITY_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_M6_PRIORITY                      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_M6_PRIORITY );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_M6_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_M6_PRIORITY_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_M7_PRIORITY                      , 14  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_M7_PRIORITY );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_M7_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_M7_PRIORITY_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_M0_PRIORITY_SEL                  , 16  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_M0_PRIORITY_SEL );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_M1_PRIORITY_SEL                  , 17  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_M1_PRIORITY_SEL );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_M2_PRIORITY_SEL                  , 18  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_M2_PRIORITY_SEL );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_M3_PRIORITY_SEL                  , 19  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_M3_PRIORITY_SEL );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_OCICFG_RESERVED_20               , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCICFG_RESERVED_20 );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_M5_PRIORITY_SEL                  , 21  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_M5_PRIORITY_SEL );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_OCICFG_RESERVED_23               , 22  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCICFG_RESERVED_23 );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_M7_PRIORITY_SEL                  , 23  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_M7_PRIORITY_SEL );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_PLBARB_LOCKERR                   , 24  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_PLBARB_LOCKERR );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_SPARE_24_31                      , 25  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_SPARE_24_31 );
+REG64_FLD( PU_GPE6_OCB_OCI_OCICFG_SPARE_24_31_LEN                  , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_SPARE_24_31_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_M0_PRIORITY                      , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_M0_PRIORITY );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_M0_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_M0_PRIORITY_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_M1_PRIORITY                      , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_M1_PRIORITY );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_M1_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_M1_PRIORITY_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_M2_PRIORITY                      , 4   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_M2_PRIORITY );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_M2_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_M2_PRIORITY_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_M3_PRIORITY                      , 6   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_M3_PRIORITY );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_M3_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_M3_PRIORITY_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_M4_PRIORITY                      , 8   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_M4_PRIORITY );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_M4_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_M4_PRIORITY_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_M5_PRIORITY                      , 10  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_M5_PRIORITY );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_M5_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_M5_PRIORITY_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_M6_PRIORITY                      , 12  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_M6_PRIORITY );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_M6_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_M6_PRIORITY_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_M7_PRIORITY                      , 14  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_M7_PRIORITY );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_M7_PRIORITY_LEN                  , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_M7_PRIORITY_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_M0_PRIORITY_SEL                  , 16  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_M0_PRIORITY_SEL );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_M1_PRIORITY_SEL                  , 17  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_M1_PRIORITY_SEL );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_M2_PRIORITY_SEL                  , 18  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_M2_PRIORITY_SEL );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_M3_PRIORITY_SEL                  , 19  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_M3_PRIORITY_SEL );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_OCICFG_RESERVED_20               , 20  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_OCICFG_RESERVED_20 );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_M5_PRIORITY_SEL                  , 21  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_M5_PRIORITY_SEL );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_OCICFG_RESERVED_23               , 22  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_OCICFG_RESERVED_23 );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_M7_PRIORITY_SEL                  , 23  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_M7_PRIORITY_SEL );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_PLBARB_LOCKERR                   , 24  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_PLBARB_LOCKERR );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_SPARE_24_31                      , 25  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE_24_31 );
+REG64_FLD( PU_GPE0_OCB_OCI_OCICFG_SPARE_24_31_LEN                  , 7   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE_24_31_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OEHDR_EVENT2HALT_DELAY                  , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_EVENT2HALT_DELAY );
+REG64_FLD( PU_GPE6_OCB_OCI_OEHDR_EVENT2HALT_DELAY_LEN              , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_EVENT2HALT_DELAY_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OEHDR_EVENT2HALT_DELAY                  , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_EVENT2HALT_DELAY );
+REG64_FLD( PU_GPE0_OCB_OCI_OEHDR_EVENT2HALT_DELAY_LEN              , 20  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_EVENT2HALT_DELAY_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OHTMCR_HTM_SRC_SEL                      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_HTM_SRC_SEL );
+REG64_FLD( PU_GPE6_OCB_OCI_OHTMCR_HTM_SRC_SEL_LEN                  , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_HTM_SRC_SEL_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OHTMCR_HTM_STOP                         , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_HTM_STOP   );
+REG64_FLD( PU_GPE6_OCB_OCI_OHTMCR_HTM_MARKER_SLAVE_ADRS            , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_HTM_MARKER_SLAVE_ADRS );
+REG64_FLD( PU_GPE6_OCB_OCI_OHTMCR_HTM_MARKER_SLAVE_ADRS_LEN        , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_HTM_MARKER_SLAVE_ADRS_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OHTMCR_EVENT2HALT_MODE                  , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_EVENT2HALT_MODE );
+REG64_FLD( PU_GPE6_OCB_OCI_OHTMCR_EVENT2HALT_MODE_LEN              , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_EVENT2HALT_MODE_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OHTMCR_EVENT2HALT_EN                    , 8   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_EVENT2HALT_EN );
+REG64_FLD( PU_GPE6_OCB_OCI_OHTMCR_EVENT2HALT_EN_LEN                , 11  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_EVENT2HALT_EN_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OHTMCR_EVENT2HALT_OCC                   , 23  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_EVENT2HALT_OCC );
+REG64_FLD( PU_GPE6_OCB_OCI_OHTMCR_EVENT2HALT_GPE0                  , 24  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_EVENT2HALT_GPE0 );
+REG64_FLD( PU_GPE6_OCB_OCI_OHTMCR_EVENT2HALT_GPE1                  , 25  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_EVENT2HALT_GPE1 );
+REG64_FLD( PU_GPE6_OCB_OCI_OHTMCR_EVENT2HALT_GPE2                  , 26  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_EVENT2HALT_GPE2 );
+REG64_FLD( PU_GPE6_OCB_OCI_OHTMCR_EVENT2HALT_GPE3                  , 27  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_EVENT2HALT_GPE3 );
+REG64_FLD( PU_GPE6_OCB_OCI_OHTMCR_EVENT2HALT_HALT_STATE            , 31  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_EVENT2HALT_HALT_STATE );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OHTMCR_HTM_SRC_SEL                      , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_HTM_SRC_SEL );
+REG64_FLD( PU_GPE0_OCB_OCI_OHTMCR_HTM_SRC_SEL_LEN                  , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_HTM_SRC_SEL_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OHTMCR_HTM_STOP                         , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_HTM_STOP   );
+REG64_FLD( PU_GPE0_OCB_OCI_OHTMCR_HTM_MARKER_SLAVE_ADRS            , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_HTM_MARKER_SLAVE_ADRS );
+REG64_FLD( PU_GPE0_OCB_OCI_OHTMCR_HTM_MARKER_SLAVE_ADRS_LEN        , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_HTM_MARKER_SLAVE_ADRS_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OHTMCR_EVENT2HALT_MODE                  , 6   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_EVENT2HALT_MODE );
+REG64_FLD( PU_GPE0_OCB_OCI_OHTMCR_EVENT2HALT_MODE_LEN              , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_EVENT2HALT_MODE_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OHTMCR_EVENT2HALT_EN                    , 8   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_EVENT2HALT_EN );
+REG64_FLD( PU_GPE0_OCB_OCI_OHTMCR_EVENT2HALT_EN_LEN                , 11  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_EVENT2HALT_EN_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OHTMCR_EVENT2HALT_OCC                   , 23  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_EVENT2HALT_OCC );
+REG64_FLD( PU_GPE0_OCB_OCI_OHTMCR_EVENT2HALT_GPE0                  , 24  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_EVENT2HALT_GPE0 );
+REG64_FLD( PU_GPE0_OCB_OCI_OHTMCR_EVENT2HALT_GPE1                  , 25  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_EVENT2HALT_GPE1 );
+REG64_FLD( PU_GPE0_OCB_OCI_OHTMCR_EVENT2HALT_GPE2                  , 26  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_EVENT2HALT_GPE2 );
+REG64_FLD( PU_GPE0_OCB_OCI_OHTMCR_EVENT2HALT_GPE3                  , 27  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_EVENT2HALT_GPE3 );
+REG64_FLD( PU_GPE0_OCB_OCI_OHTMCR_EVENT2HALT_HALT_STATE            , 31  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_EVENT2HALT_HALT_STATE );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OIEPR0_INTERRUPT_EDGE_POL_N             , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_EDGE_POL_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OIEPR0_INTERRUPT_EDGE_POL_N_LEN         , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_EDGE_POL_N_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OIEPR0_INTERRUPT_EDGE_POL_N             , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_EDGE_POL_N );
+REG64_FLD( PU_GPE0_OCB_OCI_OIEPR0_INTERRUPT_EDGE_POL_N_LEN         , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_EDGE_POL_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OIEPR1_INTERRUPT_EDGE_POL_N             , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_EDGE_POL_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OIEPR1_INTERRUPT_EDGE_POL_N_LEN         , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_EDGE_POL_N_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OIEPR1_INTERRUPT_EDGE_POL_N             , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_EDGE_POL_N );
+REG64_FLD( PU_GPE0_OCB_OCI_OIEPR1_INTERRUPT_EDGE_POL_N_LEN         , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_EDGE_POL_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OIMR0_INTERRUPT_MASK_N                  , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_MASK_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OIMR0_INTERRUPT_MASK_N_LEN              , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_MASK_N_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OIMR0_INTERRUPT_MASK_N                  , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_MASK_N );
+REG64_FLD( PU_GPE0_OCB_OCI_OIMR0_INTERRUPT_MASK_N_LEN              , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_MASK_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OIMR1_INTERRUPT_MASK_N                  , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_MASK_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OIMR1_INTERRUPT_MASK_N_LEN              , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_MASK_N_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OIMR1_INTERRUPT_MASK_N                  , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_MASK_N );
+REG64_FLD( PU_GPE0_OCB_OCI_OIMR1_INTERRUPT_MASK_N_LEN              , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_MASK_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OIRR0A_INTERRUPT_ROUTE_A_N              , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OIRR0A_INTERRUPT_ROUTE_A_N_LEN          , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OIRR0A_INTERRUPT_ROUTE_A_N              , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_ROUTE_A_N );
+REG64_FLD( PU_GPE0_OCB_OCI_OIRR0A_INTERRUPT_ROUTE_A_N_LEN          , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_ROUTE_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OIRR0B_INTERRUPT_ROUTE_A_N              , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OIRR0B_INTERRUPT_ROUTE_A_N_LEN          , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OIRR0B_INTERRUPT_ROUTE_A_N              , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_ROUTE_A_N );
+REG64_FLD( PU_GPE0_OCB_OCI_OIRR0B_INTERRUPT_ROUTE_A_N_LEN          , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_ROUTE_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OIRR0C_INTERRUPT_ROUTE_A_N              , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OIRR0C_INTERRUPT_ROUTE_A_N_LEN          , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OIRR0C_INTERRUPT_ROUTE_A_N              , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_ROUTE_A_N );
+REG64_FLD( PU_GPE0_OCB_OCI_OIRR0C_INTERRUPT_ROUTE_A_N_LEN          , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_ROUTE_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OIRR1A_INTERRUPT_ROUTE_A_N              , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OIRR1A_INTERRUPT_ROUTE_A_N_LEN          , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OIRR1A_INTERRUPT_ROUTE_A_N              , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_ROUTE_A_N );
+REG64_FLD( PU_GPE0_OCB_OCI_OIRR1A_INTERRUPT_ROUTE_A_N_LEN          , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_ROUTE_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OIRR1B_INTERRUPT_ROUTE_A_N              , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OIRR1B_INTERRUPT_ROUTE_A_N_LEN          , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OIRR1B_INTERRUPT_ROUTE_A_N              , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_ROUTE_A_N );
+REG64_FLD( PU_GPE0_OCB_OCI_OIRR1B_INTERRUPT_ROUTE_A_N_LEN          , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_ROUTE_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OIRR1C_INTERRUPT_ROUTE_A_N              , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OIRR1C_INTERRUPT_ROUTE_A_N_LEN          , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OIRR1C_INTERRUPT_ROUTE_A_N              , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_ROUTE_A_N );
+REG64_FLD( PU_GPE0_OCB_OCI_OIRR1C_INTERRUPT_ROUTE_A_N_LEN          , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_ROUTE_A_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_DEBUGGER                          , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_DEBUGGER   );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_TRACE_TRIGGER                     , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_TRACE_TRIGGER );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_OCC_ERROR                         , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCC_ERROR  );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_PBA_ERROR                         , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PBA_ERROR  );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_SRT_ERROR                         , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SRT_ERROR  );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_GPE0_ERROR                        , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_GPE0_ERROR );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_GPE1_ERROR                        , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_GPE1_ERROR );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_GPE2_ERROR                        , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_GPE2_ERROR );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_GPE3_ERROR                        , 8   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_GPE3_ERROR );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_PPC405_HALT                       , 9   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PPC405_HALT );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_ERROR                             , 10  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_ERROR      );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_SPIPSS_ERROR                      , 11  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SPIPSS_ERROR );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_CHECK_STOP_PPC405                 , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_CHECK_STOP_PPC405 );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_CHECK_STOP_GPE0                   , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_CHECK_STOP_GPE0 );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_CHECK_STOP_GPE1                   , 14  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_CHECK_STOP_GPE1 );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_CHECK_STOP_GPE2                   , 15  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_CHECK_STOP_GPE2 );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_CHECK_STOP_GPE3                   , 16  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_CHECK_STOP_GPE3 );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_OCC_MALF_ALERT                    , 17  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCC_MALF_ALERT );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_ADU_MALF_ALERT                    , 18  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_ADU_MALF_ALERT );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_EXTERNAL_TRAP                     , 19  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_EXTERNAL_TRAP );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_IVRM_PVREF_ERROR                  , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_IVRM_PVREF_ERROR );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_OCC_TIMER0                        , 21  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCC_TIMER0 );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_OCC_TIMER1                        , 22  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCC_TIMER1 );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_AVS_SLAVE0                        , 23  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_AVS_SLAVE0 );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_AVS_SLAVE1                        , 24  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_AVS_SLAVE1 );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_IPI0_HI_PRIORITY                  , 25  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_IPI0_HI_PRIORITY );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_IPI1_HI_PRIORITY                  , 26  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_IPI1_HI_PRIORITY );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_IPI2_HI_PRIORITY                  , 27  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_IPI2_HI_PRIORITY );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_IPI3_HI_PRIORITY                  , 28  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_IPI3_HI_PRIORITY );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_IPI4_HI_PRIORITY                  , 29  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_IPI4_HI_PRIORITY );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_ADCFSM_ONGOING                    , 30  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_ADCFSM_ONGOING );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR0_SPARE_31                          , 31  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SPARE_31   );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_DEBUGGER                          , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_DEBUGGER   );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_TRACE_TRIGGER                     , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_TRACE_TRIGGER );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_OCC_ERROR                         , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_OCC_ERROR  );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_PBA_ERROR                         , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PBA_ERROR  );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_SRT_ERROR                         , 4   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_SRT_ERROR  );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_GPE0_ERROR                        , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_GPE0_ERROR );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_GPE1_ERROR                        , 6   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_GPE1_ERROR );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_GPE2_ERROR                        , 7   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_GPE2_ERROR );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_GPE3_ERROR                        , 8   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_GPE3_ERROR );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_PPC405_HALT                       , 9   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PPC405_HALT );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_ERROR                             , 10  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_ERROR      );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_SPIPSS_ERROR                      , 11  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_SPIPSS_ERROR );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_CHECK_STOP_PPC405                 , 12  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_CHECK_STOP_PPC405 );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_CHECK_STOP_GPE0                   , 13  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_CHECK_STOP_GPE0 );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_CHECK_STOP_GPE1                   , 14  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_CHECK_STOP_GPE1 );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_CHECK_STOP_GPE2                   , 15  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_CHECK_STOP_GPE2 );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_CHECK_STOP_GPE3                   , 16  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_CHECK_STOP_GPE3 );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_OCC_MALF_ALERT                    , 17  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_OCC_MALF_ALERT );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_ADU_MALF_ALERT                    , 18  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_ADU_MALF_ALERT );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_EXTERNAL_TRAP                     , 19  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_EXTERNAL_TRAP );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_IVRM_PVREF_ERROR                  , 20  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_IVRM_PVREF_ERROR );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_OCC_TIMER0                        , 21  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_OCC_TIMER0 );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_OCC_TIMER1                        , 22  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_OCC_TIMER1 );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_AVS_SLAVE0                        , 23  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_AVS_SLAVE0 );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_AVS_SLAVE1                        , 24  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_AVS_SLAVE1 );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_IPI0_HI_PRIORITY                  , 25  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_IPI0_HI_PRIORITY );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_IPI1_HI_PRIORITY                  , 26  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_IPI1_HI_PRIORITY );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_IPI2_HI_PRIORITY                  , 27  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_IPI2_HI_PRIORITY );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_IPI3_HI_PRIORITY                  , 28  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_IPI3_HI_PRIORITY );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_IPI4_HI_PRIORITY                  , 29  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_IPI4_HI_PRIORITY );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_ADCFSM_ONGOING                    , 30  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_ADCFSM_ONGOING );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR0_SPARE_31                          , 31  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_SPARE_31   );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_PBAX_OCC_SEND_ATTN                , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PBAX_OCC_SEND_ATTN );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_PBAX_OCC_PUSH0                    , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PBAX_OCC_PUSH0 );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_PBAX_OCC_PUSH1                    , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PBAX_OCC_PUSH1 );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_PBA_BCDE_ATTN                     , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PBA_BCDE_ATTN );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_PBA_BCUE_ATTN                     , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PBA_BCUE_ATTN );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_OCC_STRM0_PULL                    , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCC_STRM0_PULL );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_OCC_STRM0_PUSH                    , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCC_STRM0_PUSH );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_OCC_STRM1_PULL                    , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCC_STRM1_PULL );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_OCC_STRM1_PUSH                    , 8   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCC_STRM1_PUSH );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_OCC_STRM2_PULL                    , 9   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCC_STRM2_PULL );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_OCC_STRM2_PUSH                    , 10  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCC_STRM2_PUSH );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_OCC_STRM3_PULL                    , 11  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCC_STRM3_PULL );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_OCC_STRM3_PUSH                    , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCC_STRM3_PUSH );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE0_PENDING        , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PMC_PCB_INTR_TYPE0_PENDING );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE1_PENDING        , 14  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PMC_PCB_INTR_TYPE1_PENDING );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE2_PENDING        , 15  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PMC_PCB_INTR_TYPE2_PENDING );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE3_PENDING        , 16  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PMC_PCB_INTR_TYPE3_PENDING );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE4_PENDING        , 17  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PMC_PCB_INTR_TYPE4_PENDING );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE5_PENDING        , 18  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PMC_PCB_INTR_TYPE5_PENDING );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE6_PENDING        , 19  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PMC_PCB_INTR_TYPE6_PENDING );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE7_PENDING        , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PMC_PCB_INTR_TYPE7_PENDING );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_PMC_O2S_0A_ONGOING                , 21  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PMC_O2S_0A_ONGOING );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_PMC_O2S_0B_ONGOING                , 22  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PMC_O2S_0B_ONGOING );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_PMC_O2S_1A_ONGOING                , 23  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PMC_O2S_1A_ONGOING );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_PMC_O2S_1B_ONGOING                , 24  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PMC_O2S_1B_ONGOING );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_PSSBRIDGE_ONGOING                 , 25  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PSSBRIDGE_ONGOING );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_IPI0_LO_PRIORITY                  , 26  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_IPI0_LO_PRIORITY );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_IPI1_LO_PRIORITY                  , 27  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_IPI1_LO_PRIORITY );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_IPI2_LO_PRIORITY                  , 28  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_IPI2_LO_PRIORITY );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_IPI3_LO_PRIORITY                  , 29  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_IPI3_LO_PRIORITY );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_IPI4_LO_PRIORITY                  , 30  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_IPI4_LO_PRIORITY );
+REG64_FLD( PU_GPE6_OCB_OCI_OISR1_SPARE_31                          , 31  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SPARE_31   );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_PBAX_OCC_SEND_ATTN                , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PBAX_OCC_SEND_ATTN );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_PBAX_OCC_PUSH0                    , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PBAX_OCC_PUSH0 );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_PBAX_OCC_PUSH1                    , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PBAX_OCC_PUSH1 );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_PBA_BCDE_ATTN                     , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PBA_BCDE_ATTN );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_PBA_BCUE_ATTN                     , 4   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PBA_BCUE_ATTN );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_OCC_STRM0_PULL                    , 5   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_OCC_STRM0_PULL );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_OCC_STRM0_PUSH                    , 6   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_OCC_STRM0_PUSH );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_OCC_STRM1_PULL                    , 7   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_OCC_STRM1_PULL );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_OCC_STRM1_PUSH                    , 8   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_OCC_STRM1_PUSH );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_OCC_STRM2_PULL                    , 9   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_OCC_STRM2_PULL );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_OCC_STRM2_PUSH                    , 10  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_OCC_STRM2_PUSH );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_OCC_STRM3_PULL                    , 11  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_OCC_STRM3_PULL );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_OCC_STRM3_PUSH                    , 12  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_OCC_STRM3_PUSH );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE0_PENDING        , 13  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PMC_PCB_INTR_TYPE0_PENDING );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE1_PENDING        , 14  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PMC_PCB_INTR_TYPE1_PENDING );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE2_PENDING        , 15  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PMC_PCB_INTR_TYPE2_PENDING );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE3_PENDING        , 16  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PMC_PCB_INTR_TYPE3_PENDING );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE4_PENDING        , 17  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PMC_PCB_INTR_TYPE4_PENDING );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE5_PENDING        , 18  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PMC_PCB_INTR_TYPE5_PENDING );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE6_PENDING        , 19  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PMC_PCB_INTR_TYPE6_PENDING );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE7_PENDING        , 20  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PMC_PCB_INTR_TYPE7_PENDING );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_PMC_O2S_0A_ONGOING                , 21  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PMC_O2S_0A_ONGOING );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_PMC_O2S_0B_ONGOING                , 22  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PMC_O2S_0B_ONGOING );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_PMC_O2S_1A_ONGOING                , 23  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PMC_O2S_1A_ONGOING );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_PMC_O2S_1B_ONGOING                , 24  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PMC_O2S_1B_ONGOING );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_PSSBRIDGE_ONGOING                 , 25  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_PSSBRIDGE_ONGOING );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_IPI0_LO_PRIORITY                  , 26  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_IPI0_LO_PRIORITY );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_IPI1_LO_PRIORITY                  , 27  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_IPI1_LO_PRIORITY );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_IPI2_LO_PRIORITY                  , 28  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_IPI2_LO_PRIORITY );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_IPI3_LO_PRIORITY                  , 29  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_IPI3_LO_PRIORITY );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_IPI4_LO_PRIORITY                  , 30  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_IPI4_LO_PRIORITY );
+REG64_FLD( PU_GPE0_OCB_OCI_OISR1_SPARE_31                          , 31  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_SPARE_31   );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OITR0_INTERRUPT_TYPE_N                  , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_TYPE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OITR0_INTERRUPT_TYPE_N_LEN              , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_TYPE_N_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OITR0_INTERRUPT_TYPE_N                  , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_TYPE_N );
+REG64_FLD( PU_GPE0_OCB_OCI_OITR0_INTERRUPT_TYPE_N_LEN              , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_TYPE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OITR1_INTERRUPT_TYPE_N                  , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_TYPE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OITR1_INTERRUPT_TYPE_N_LEN              , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_TYPE_N_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OITR1_INTERRUPT_TYPE_N                  , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_TYPE_N );
+REG64_FLD( PU_GPE0_OCB_OCI_OITR1_INTERRUPT_TYPE_N_LEN              , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_INTERRUPT_TYPE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C0_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C0_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C0_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C0_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C1_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C1_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C1_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C1_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C10_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C10_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C10_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C10_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C11_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C11_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C11_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C11_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C12_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C12_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C12_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C12_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C13_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C13_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C13_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C13_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C14_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C14_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C14_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C14_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C15_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C15_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C15_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C15_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C16_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C16_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C16_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C16_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C17_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C17_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C17_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C17_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C18_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C18_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C18_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C18_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C19_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C19_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C19_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C19_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C2_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C2_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C2_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C2_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C20_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C20_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C20_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C20_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C21_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C21_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C21_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C21_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C22_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C22_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C22_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C22_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C23_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C23_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C23_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C23_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C3_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C3_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C3_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C3_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C4_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C4_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C4_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C4_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C5_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C5_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C5_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C5_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C6_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C6_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C6_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C6_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C7_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C7_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C7_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C7_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C8_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C8_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C8_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C8_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C9_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0C9_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C9_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0C9_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_0      , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_1      , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_2      , 2   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_3      , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_4      , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_5      , 5   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_6      , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_6 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_7      , 7   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_7 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_8      , 8   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_8 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_9      , 9   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_9 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_10     , 10  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_10 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_11     , 11  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_11 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_12     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_12 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_13     , 13  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_13 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_14     , 14  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_14 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_15     , 15  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_15 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_16     , 16  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_16 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_17     , 17  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_17 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_18     , 18  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_18 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_19     , 19  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_19 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_20     , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_20 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_21     , 21  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_21 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_22     , 22  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_22 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_23     , 23  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_23 );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_0      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_1      , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_2      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_3      , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_4      , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_5      , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_6      , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_6 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_7      , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_7 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_8      , 8   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_8 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_9      , 9   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_9 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_10     , 10  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_10 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_11     , 11  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_11 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_12     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_12 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_13     , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_13 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_14     , 14  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_14 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_15     , 15  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_15 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_16     , 16  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_16 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_17     , 17  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_17 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_18     , 18  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_18 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_19     , 19  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_19 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_20     , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_20 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_21     , 21  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_21 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_22     , 22  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_22 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_23     , 23  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_23 );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C0_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C0_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C0_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C0_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C1_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C1_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C1_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C1_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C10_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C10_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C10_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C10_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C11_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C11_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C11_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C11_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C12_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C12_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C12_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C12_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C13_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C13_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C13_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C13_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C14_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C14_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C14_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C14_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C15_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C15_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C15_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C15_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C16_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C16_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C16_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C16_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C17_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C17_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C17_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C17_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C18_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C18_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C18_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C18_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C19_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C19_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C19_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C19_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C2_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C2_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C2_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C2_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C20_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C20_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C20_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C20_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C21_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C21_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C21_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C21_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C22_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C22_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C22_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C22_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C23_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C23_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C23_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C23_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C3_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C3_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C3_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C3_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C4_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C4_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C4_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C4_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C5_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C5_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C5_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C5_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C6_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C6_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C6_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C6_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C7_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C7_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C7_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C7_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C8_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C8_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C8_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C8_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C9_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1C9_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C9_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1C9_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_0      , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_1      , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_2      , 2   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_3      , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_4      , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_5      , 5   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_6      , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_6 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_7      , 7   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_7 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_8      , 8   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_8 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_9      , 9   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_9 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_10     , 10  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_10 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_11     , 11  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_11 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_12     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_12 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_13     , 13  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_13 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_14     , 14  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_14 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_15     , 15  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_15 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_16     , 16  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_16 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_17     , 17  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_17 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_18     , 18  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_18 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_19     , 19  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_19 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_20     , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_20 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_21     , 21  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_21 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_22     , 22  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_22 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_23     , 23  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_23 );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_0      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_1      , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_2      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_3      , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_4      , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_5      , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_6      , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_6 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_7      , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_7 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_8      , 8   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_8 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_9      , 9   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_9 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_10     , 10  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_10 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_11     , 11  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_11 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_12     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_12 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_13     , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_13 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_14     , 14  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_14 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_15     , 15  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_15 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_16     , 16  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_16 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_17     , 17  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_17 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_18     , 18  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_18 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_19     , 19  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_19 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_20     , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_20 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_21     , 21  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_21 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_22     , 22  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_22 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_23     , 23  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_23 );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C0_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C0_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C0_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C0_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C1_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C1_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C1_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C1_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C10_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C10_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C10_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C10_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C11_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C11_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C11_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C11_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C12_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C12_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C12_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C12_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C13_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C13_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C13_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C13_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C14_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C14_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C14_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C14_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C15_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C15_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C15_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C15_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C16_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C16_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C16_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C16_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C17_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C17_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C17_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C17_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C18_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C18_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C18_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C18_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C19_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C19_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C19_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C19_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C2_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C2_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C2_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C2_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C20_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C20_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C20_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C20_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C21_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C21_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C21_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C21_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C22_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C22_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C22_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C22_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C23_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C23_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C23_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C23_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C3_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C3_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C3_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C3_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C4_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C4_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C4_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C4_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C5_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C5_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C5_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C5_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C6_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C6_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C6_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C6_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C7_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C7_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C7_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C7_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C8_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C8_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C8_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C8_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C9_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2C9_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C9_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2C9_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_0      , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_1      , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_2      , 2   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_3      , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_4      , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_5      , 5   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_6      , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_6 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_7      , 7   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_7 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_8      , 8   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_8 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_9      , 9   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_9 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_10     , 10  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_10 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_11     , 11  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_11 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_12     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_12 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_13     , 13  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_13 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_14     , 14  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_14 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_15     , 15  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_15 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_16     , 16  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_16 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_17     , 17  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_17 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_18     , 18  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_18 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_19     , 19  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_19 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_20     , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_20 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_21     , 21  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_21 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_22     , 22  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_22 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_23     , 23  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_23 );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_0      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_1      , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_2      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_3      , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_4      , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_5      , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_6      , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_6 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_7      , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_7 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_8      , 8   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_8 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_9      , 9   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_9 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_10     , 10  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_10 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_11     , 11  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_11 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_12     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_12 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_13     , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_13 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_14     , 14  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_14 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_15     , 15  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_15 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_16     , 16  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_16 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_17     , 17  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_17 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_18     , 18  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_18 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_19     , 19  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_19 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_20     , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_20 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_21     , 21  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_21 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_22     , 22  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_22 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_23     , 23  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_23 );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C0_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C0_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C0_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C0_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C1_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C1_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C1_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C1_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C10_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C10_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C10_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C10_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C11_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C11_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C11_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C11_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C12_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C12_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C12_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C12_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C13_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C13_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C13_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C13_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C14_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C14_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C14_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C14_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C15_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C15_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C15_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C15_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C16_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C16_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C16_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C16_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C17_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C17_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C17_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C17_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C18_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C18_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C18_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C18_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C19_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C19_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C19_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C19_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C2_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C2_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C2_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C2_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C20_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C20_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C20_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C20_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C21_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C21_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C21_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C21_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C22_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C22_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C22_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C22_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C23_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C23_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C23_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C23_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C3_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C3_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C3_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C3_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C4_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C4_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C4_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C4_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C5_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C5_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C5_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C5_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C6_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C6_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C6_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C6_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C7_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C7_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C7_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C7_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C8_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C8_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C8_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C8_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C9_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3C9_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C9_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3C9_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_0      , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_1      , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_2      , 2   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_3      , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_4      , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_5      , 5   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_6      , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_6 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_7      , 7   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_7 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_8      , 8   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_8 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_9      , 9   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_9 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_10     , 10  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_10 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_11     , 11  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_11 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_12     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_12 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_13     , 13  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_13 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_14     , 14  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_14 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_15     , 15  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_15 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_16     , 16  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_16 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_17     , 17  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_17 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_18     , 18  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_18 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_19     , 19  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_19 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_20     , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_20 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_21     , 21  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_21 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_22     , 22  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_22 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_23     , 23  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_23 );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_0      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_1      , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_2      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_3      , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_4      , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_5      , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_6      , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_6 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_7      , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_7 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_8      , 8   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_8 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_9      , 9   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_9 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_10     , 10  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_10 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_11     , 11  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_11 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_12     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_12 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_13     , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_13 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_14     , 14  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_14 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_15     , 15  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_15 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_16     , 16  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_16 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_17     , 17  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_17 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_18     , 18  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_18 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_19     , 19  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_19 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_20     , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_20 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_21     , 21  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_21 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_22     , 22  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_22 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_23     , 23  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_23 );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C0_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C0_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C0_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C0_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C1_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C1_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C1_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C1_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C10_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C10_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C10_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C10_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C11_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C11_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C11_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C11_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C12_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C12_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C12_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C12_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C13_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C13_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C13_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C13_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C14_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C14_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C14_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C14_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C15_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C15_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C15_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C15_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C16_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C16_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C16_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C16_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C17_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C17_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C17_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C17_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C18_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C18_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C18_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C18_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C19_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C19_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C19_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C19_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C2_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C2_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C2_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C2_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C20_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C20_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C20_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C20_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C21_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C21_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C21_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C21_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C22_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C22_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C22_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C22_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C23_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C23_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C23_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C23_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C3_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C3_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C3_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C3_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C4_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C4_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C4_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C4_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C5_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C5_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C5_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C5_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C6_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C6_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C6_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C6_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C7_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C7_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C7_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C7_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C8_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C8_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C8_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C8_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C9_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4C9_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C9_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4C9_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_0      , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_1      , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_2      , 2   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_3      , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_4      , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_5      , 5   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_6      , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_6 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_7      , 7   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_7 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_8      , 8   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_8 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_9      , 9   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_9 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_10     , 10  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_10 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_11     , 11  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_11 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_12     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_12 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_13     , 13  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_13 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_14     , 14  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_14 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_15     , 15  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_15 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_16     , 16  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_16 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_17     , 17  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_17 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_18     , 18  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_18 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_19     , 19  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_19 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_20     , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_20 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_21     , 21  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_21 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_22     , 22  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_22 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_23     , 23  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_23 );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_0      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_1      , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_2      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_3      , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_4      , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_5      , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_6      , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_6 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_7      , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_7 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_8      , 8   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_8 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_9      , 9   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_9 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_10     , 10  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_10 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_11     , 11  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_11 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_12     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_12 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_13     , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_13 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_14     , 14  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_14 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_15     , 15  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_15 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_16     , 16  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_16 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_17     , 17  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_17 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_18     , 18  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_18 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_19     , 19  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_19 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_20     , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_20 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_21     , 21  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_21 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_22     , 22  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_22 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_23     , 23  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_23 );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C0_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C0_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C0_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C0_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C1_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C1_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C1_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C1_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C10_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C10_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C10_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C10_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C11_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C11_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C11_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C11_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C12_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C12_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C12_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C12_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C13_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C13_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C13_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C13_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C14_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C14_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C14_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C14_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C15_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C15_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C15_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C15_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C16_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C16_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C16_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C16_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C17_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C17_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C17_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C17_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C18_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C18_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C18_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C18_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C19_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C19_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C19_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C19_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C2_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C2_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C2_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C2_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C20_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C20_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C20_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C20_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C21_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C21_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C21_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C21_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C22_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C22_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C22_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C22_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C23_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C23_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C23_PCB_INTR_TYPE_A_CORE_N         , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C23_PCB_INTR_TYPE_A_CORE_N_LEN     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C3_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C3_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C3_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C3_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C4_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C4_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C4_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C4_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C5_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C5_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C5_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C5_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C6_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C6_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C6_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C6_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C7_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C7_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C7_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C7_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C8_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C8_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C8_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C8_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C9_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5C9_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C9_PCB_INTR_TYPE_A_CORE_N          , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5C9_PCB_INTR_TYPE_A_CORE_N_LEN      , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_0      , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_1      , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_2      , 2   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_3      , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_4      , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_5      , 5   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_6      , 6   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_6 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_7      , 7   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_7 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_8      , 8   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_8 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_9      , 9   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_9 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_10     , 10  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_10 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_11     , 11  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_11 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_12     , 12  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_12 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_13     , 13  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_13 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_14     , 14  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_14 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_15     , 15  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_15 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_16     , 16  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_16 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_17     , 17  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_17 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_18     , 18  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_18 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_19     , 19  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_19 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_20     , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_20 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_21     , 21  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_21 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_22     , 22  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_22 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_23     , 23  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_23 );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_0      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_1      , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_2      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_3      , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_4      , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_5      , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_6      , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_6 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_7      , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_7 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_8      , 8   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_8 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_9      , 9   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_9 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_10     , 10  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_10 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_11     , 11  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_11 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_12     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_12 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_13     , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_13 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_14     , 14  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_14 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_15     , 15  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_15 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_16     , 16  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_16 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_17     , 17  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_17 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_18     , 18  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_18 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_19     , 19  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_19 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_20     , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_20 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_21     , 21  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_21 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_22     , 22  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_22 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_23     , 23  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_23 );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_0      , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_1      , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_2      , 2   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_3      , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_4      , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_5      , 5   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_0      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_1      , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_2      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_3      , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_4      , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_5      , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT6Q0_PCB_INTR_TYPE_A_QUAD_N          , 28  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT6Q0_PCB_INTR_TYPE_A_QUAD_N_LEN      , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT6Q0_PCB_INTR_TYPE_A_QUAD_N          , 28  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT6Q0_PCB_INTR_TYPE_A_QUAD_N_LEN      , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT6Q1_PCB_INTR_TYPE_A_QUAD_N          , 28  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT6Q1_PCB_INTR_TYPE_A_QUAD_N_LEN      , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT6Q1_PCB_INTR_TYPE_A_QUAD_N          , 28  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT6Q1_PCB_INTR_TYPE_A_QUAD_N_LEN      , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT6Q2_PCB_INTR_TYPE_A_QUAD_N          , 28  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT6Q2_PCB_INTR_TYPE_A_QUAD_N_LEN      , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT6Q2_PCB_INTR_TYPE_A_QUAD_N          , 28  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT6Q2_PCB_INTR_TYPE_A_QUAD_N_LEN      , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT6Q3_PCB_INTR_TYPE_A_QUAD_N          , 28  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT6Q3_PCB_INTR_TYPE_A_QUAD_N_LEN      , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT6Q3_PCB_INTR_TYPE_A_QUAD_N          , 28  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT6Q3_PCB_INTR_TYPE_A_QUAD_N_LEN      , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT6Q4_PCB_INTR_TYPE_A_QUAD_N          , 28  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT6Q4_PCB_INTR_TYPE_A_QUAD_N_LEN      , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT6Q4_PCB_INTR_TYPE_A_QUAD_N          , 28  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT6Q4_PCB_INTR_TYPE_A_QUAD_N_LEN      , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT6Q5_PCB_INTR_TYPE_A_QUAD_N          , 28  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT6Q5_PCB_INTR_TYPE_A_QUAD_N_LEN      , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT6Q5_PCB_INTR_TYPE_A_QUAD_N          , 28  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT6Q5_PCB_INTR_TYPE_A_QUAD_N_LEN      , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_0      , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_1      , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_2      , 2   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_3      , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_4      , 4   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_5      , 5   ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_0      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_1      , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_2      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_3      , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_4      , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_5      , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT7Q0_PCB_INTR_TYPE_A_QUAD_N          , 31  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT7Q0_PCB_INTR_TYPE_A_QUAD_N          , 31  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT7Q1_PCB_INTR_TYPE_A_QUAD_N          , 31  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT7Q1_PCB_INTR_TYPE_A_QUAD_N          , 31  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT7Q2_PCB_INTR_TYPE_A_QUAD_N          , 31  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT7Q2_PCB_INTR_TYPE_A_QUAD_N          , 31  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT7Q3_PCB_INTR_TYPE_A_QUAD_N          , 31  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT7Q3_PCB_INTR_TYPE_A_QUAD_N          , 31  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT7Q4_PCB_INTR_TYPE_A_QUAD_N          , 31  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT7Q4_PCB_INTR_TYPE_A_QUAD_N          , 31  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+
+REG64_FLD( PU_GPE1_OCB_OCI_OPIT7Q5_PCB_INTR_TYPE_A_QUAD_N          , 31  ,
+           SH_UNT_PU_GPE1  , SH_ACS_OCI1     , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OPIT7Q5_PCB_INTR_TYPE_A_QUAD_N          , 31  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OTBR_TIMEBASE                           , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_TIMEBASE   );
+REG64_FLD( PU_GPE6_OCB_OCI_OTBR_TIMEBASE_LEN                       , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_TIMEBASE_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OTBR_TIMEBASE                           , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_TIMEBASE   );
+REG64_FLD( PU_GPE0_OCB_OCI_OTBR_TIMEBASE_LEN                       , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_TIMEBASE_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OTR0_TIMEOUT_N                          , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_TIMEOUT_N  );
+REG64_FLD( PU_GPE6_OCB_OCI_OTR0_CONTROL_N                          , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_CONTROL_N  );
+REG64_FLD( PU_GPE6_OCB_OCI_OTR0_AUTO_RELOAD_N                      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_AUTO_RELOAD_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OTR0_SPARE_N                            , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_SPARE_N    );
+REG64_FLD( PU_GPE6_OCB_OCI_OTR0_SPARE_N_LEN                        , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_SPARE_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OTR0_TIMER_N                            , 16  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_TIMER_N    );
+REG64_FLD( PU_GPE6_OCB_OCI_OTR0_TIMER_N_LEN                        , 16  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_TIMER_N_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OTR0_TIMEOUT_N                          , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_TIMEOUT_N  );
+REG64_FLD( PU_GPE0_OCB_OCI_OTR0_CONTROL_N                          , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_CONTROL_N  );
+REG64_FLD( PU_GPE0_OCB_OCI_OTR0_AUTO_RELOAD_N                      , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_AUTO_RELOAD_N );
+REG64_FLD( PU_GPE0_OCB_OCI_OTR0_SPARE_N                            , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE_N    );
+REG64_FLD( PU_GPE0_OCB_OCI_OTR0_SPARE_N_LEN                        , 13  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE_N_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OTR0_TIMER_N                            , 16  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_TIMER_N    );
+REG64_FLD( PU_GPE0_OCB_OCI_OTR0_TIMER_N_LEN                        , 16  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_TIMER_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_OTR1_TIMEOUT_N                          , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_TIMEOUT_N  );
+REG64_FLD( PU_GPE6_OCB_OCI_OTR1_CONTROL_N                          , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_CONTROL_N  );
+REG64_FLD( PU_GPE6_OCB_OCI_OTR1_AUTO_RELOAD_N                      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_AUTO_RELOAD_N );
+REG64_FLD( PU_GPE6_OCB_OCI_OTR1_SPARE_N                            , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_SPARE_N    );
+REG64_FLD( PU_GPE6_OCB_OCI_OTR1_SPARE_N_LEN                        , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_SPARE_N_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_OTR1_TIMER_N                            , 16  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_TIMER_N    );
+REG64_FLD( PU_GPE6_OCB_OCI_OTR1_TIMER_N_LEN                        , 16  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM     , SH_FLD_TIMER_N_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_OTR1_TIMEOUT_N                          , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_TIMEOUT_N  );
+REG64_FLD( PU_GPE0_OCB_OCI_OTR1_CONTROL_N                          , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_CONTROL_N  );
+REG64_FLD( PU_GPE0_OCB_OCI_OTR1_AUTO_RELOAD_N                      , 2   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_AUTO_RELOAD_N );
+REG64_FLD( PU_GPE0_OCB_OCI_OTR1_SPARE_N                            , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE_N    );
+REG64_FLD( PU_GPE0_OCB_OCI_OTR1_SPARE_N_LEN                        , 13  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_SPARE_N_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_OTR1_TIMER_N                            , 16  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_TIMER_N    );
+REG64_FLD( PU_GPE0_OCB_OCI_OTR1_TIMER_N_LEN                        , 16  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI      , SH_FLD_TIMER_N_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_QCSR_CORE_CONFIG                        , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_CORE_CONFIG );
+REG64_FLD( PU_GPE6_OCB_OCI_QCSR_CORE_CONFIG_LEN                    , 24  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_CORE_CONFIG_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_QCSR_RESERVED_24_31                     , 24  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_24_31 );
+REG64_FLD( PU_GPE6_OCB_OCI_QCSR_RESERVED_24_31_LEN                 , 8   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_24_31_LEN );
+
+REG64_FLD( PU_GPE0_OCB_OCI_QCSR_CORE_CONFIG                        , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_CORE_CONFIG );
+REG64_FLD( PU_GPE0_OCB_OCI_QCSR_CORE_CONFIG_LEN                    , 24  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_CORE_CONFIG_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_QCSR_RESERVED_24_31                     , 24  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_RESERVED_24_31 );
+REG64_FLD( PU_GPE0_OCB_OCI_QCSR_RESERVED_24_31_LEN                 , 8   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_RESERVED_24_31_LEN );
+
+REG64_FLD( PU_GPE6_OCB_OCI_QSSR_L2_STOPPED                         , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_L2_STOPPED );
+REG64_FLD( PU_GPE6_OCB_OCI_QSSR_L2_STOPPED_LEN                     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_L2_STOPPED_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_QSSR_L3_STOPPED                         , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_L3_STOPPED );
+REG64_FLD( PU_GPE6_OCB_OCI_QSSR_L3_STOPPED_LEN                     , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_L3_STOPPED_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_QSSR_QUAD_STOPPED                       , 24  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_QUAD_STOPPED );
+REG64_FLD( PU_GPE6_OCB_OCI_QSSR_QUAD_STOPPED_LEN                   , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_QUAD_STOPPED_LEN );
+REG64_FLD( PU_GPE6_OCB_OCI_QSSR_RESERVED_30                        , 30  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_30 );
+REG64_FLD( PU_GPE6_OCB_OCI_QSSR_CHANGE_IN_PROGRESS                 , 31  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_CHANGE_IN_PROGRESS );
+
+REG64_FLD( PU_GPE0_OCB_OCI_QSSR_L2_STOPPED                         , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_L2_STOPPED );
+REG64_FLD( PU_GPE0_OCB_OCI_QSSR_L2_STOPPED_LEN                     , 12  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_L2_STOPPED_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_QSSR_L3_STOPPED                         , 12  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_L3_STOPPED );
+REG64_FLD( PU_GPE0_OCB_OCI_QSSR_L3_STOPPED_LEN                     , 12  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_L3_STOPPED_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_QSSR_QUAD_STOPPED                       , 24  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_QUAD_STOPPED );
+REG64_FLD( PU_GPE0_OCB_OCI_QSSR_QUAD_STOPPED_LEN                   , 6   ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_QUAD_STOPPED_LEN );
+REG64_FLD( PU_GPE0_OCB_OCI_QSSR_RESERVED_30                        , 30  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_RESERVED_30 );
+REG64_FLD( PU_GPE0_OCB_OCI_QSSR_CHANGE_IN_PROGRESS                 , 31  ,
+           SH_UNT_PU_GPE0  , SH_ACS_OCI2     , SH_FLD_CHANGE_IN_PROGRESS );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OACR_OCI_PRIORITY_MODE                  , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCI_PRIORITY_MODE );
+REG64_FLD( PU_GPE6_OCB_PIB_OACR_OCI_PRIORITY_ORDER                 , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCI_PRIORITY_ORDER );
+REG64_FLD( PU_GPE6_OCB_PIB_OACR_OCI_PRIORITY_ORDER_LEN             , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCI_PRIORITY_ORDER_LEN );
+REG64_FLD( PU_GPE6_OCB_PIB_OACR_OCI_HI_BUS_MODE                    , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCI_HI_BUS_MODE );
+REG64_FLD( PU_GPE6_OCB_PIB_OACR_OCI_READ_PIPELINE_CONTROL          , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCI_READ_PIPELINE_CONTROL );
+REG64_FLD( PU_GPE6_OCB_PIB_OACR_OCI_READ_PIPELINE_CONTROL_LEN      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCI_READ_PIPELINE_CONTROL_LEN );
+REG64_FLD( PU_GPE6_OCB_PIB_OACR_OCI_WRITE_PIPELINE_CONTROL         , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCI_WRITE_PIPELINE_CONTROL );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OCBAR0_OCI_REGION                       , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCI_REGION );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBAR0_OCI_REGION_LEN                   , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCI_REGION_LEN );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBAR0_ADDRESS                          , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBAR0_ADDRESS_LEN                      , 26  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OCBAR1_OCI_REGION                       , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCI_REGION );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBAR1_OCI_REGION_LEN                   , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCI_REGION_LEN );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBAR1_ADDRESS                          , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBAR1_ADDRESS_LEN                      , 26  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OCBAR2_OCI_REGION                       , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCI_REGION );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBAR2_OCI_REGION_LEN                   , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCI_REGION_LEN );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBAR2_ADDRESS                          , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBAR2_ADDRESS_LEN                      , 26  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OCBAR3_OCI_REGION                       , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCI_REGION );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBAR3_OCI_REGION_LEN                   , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCI_REGION_LEN );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBAR3_ADDRESS                          , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBAR3_ADDRESS_LEN                      , 26  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR0_PULL_READ_UNDERFLOW             , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PULL_READ_UNDERFLOW );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR0_PUSH_WRITE_OVERFLOW             , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PUSH_WRITE_OVERFLOW );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR0_PULL_READ_UNDERFLOW_EN          , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PULL_READ_UNDERFLOW_EN );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR0_PUSH_WRITE_OVERFLOW_EN          , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PUSH_WRITE_OVERFLOW_EN );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR0_STREAM_MODE                     , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_STREAM_MODE );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR0_STREAM_TYPE                     , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_STREAM_TYPE );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR0_SPARE0                          , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SPARE0     );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR0_SPARE0_LEN                      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SPARE0_LEN );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR0_OCI_TIMEOUT                     , 8   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCI_TIMEOUT );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR0_OCI_READ_DATA_PARITY            , 9   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCI_READ_DATA_PARITY );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR0_OCI_SLAVE_ERROR                 , 10  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCI_SLAVE_ERROR );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR0_ADDR_PARITY_ERR                 , 11  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_ADDR_PARITY_ERR );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR0_DATA_PARITY_ERR                 , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_DATA_PARITY_ERR );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR0_SPARE1                          , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SPARE1     );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR0_FSM_ERR                         , 14  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_FSM_ERR    );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR0_SPARE2                          , 15  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SPARE2     );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR1_PULL_READ_UNDERFLOW             , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PULL_READ_UNDERFLOW );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR1_PUSH_WRITE_OVERFLOW             , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PUSH_WRITE_OVERFLOW );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR1_PULL_READ_UNDERFLOW_EN          , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PULL_READ_UNDERFLOW_EN );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR1_PUSH_WRITE_OVERFLOW_EN          , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PUSH_WRITE_OVERFLOW_EN );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR1_STREAM_MODE                     , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_STREAM_MODE );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR1_STREAM_TYPE                     , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_STREAM_TYPE );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR1_SPARE0                          , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SPARE0     );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR1_SPARE0_LEN                      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SPARE0_LEN );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR1_OCI_TIMEOUT                     , 8   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCI_TIMEOUT );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR1_OCI_READ_DATA_PARITY            , 9   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCI_READ_DATA_PARITY );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR1_OCI_SLAVE_ERROR                 , 10  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCI_SLAVE_ERROR );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR1_ADDR_PARITY_ERR                 , 11  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_ADDR_PARITY_ERR );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR1_DATA_PARITY_ERR                 , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_DATA_PARITY_ERR );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR1_SPARE1                          , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SPARE1     );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR1_FSM_ERR                         , 14  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_FSM_ERR    );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR1_SPARE2                          , 15  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SPARE2     );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR2_PULL_READ_UNDERFLOW             , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PULL_READ_UNDERFLOW );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR2_PUSH_WRITE_OVERFLOW             , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PUSH_WRITE_OVERFLOW );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR2_PULL_READ_UNDERFLOW_EN          , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PULL_READ_UNDERFLOW_EN );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR2_PUSH_WRITE_OVERFLOW_EN          , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PUSH_WRITE_OVERFLOW_EN );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR2_STREAM_MODE                     , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_STREAM_MODE );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR2_STREAM_TYPE                     , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_STREAM_TYPE );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR2_SPARE0                          , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SPARE0     );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR2_SPARE0_LEN                      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SPARE0_LEN );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR2_OCI_TIMEOUT                     , 8   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCI_TIMEOUT );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR2_OCI_READ_DATA_PARITY            , 9   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCI_READ_DATA_PARITY );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR2_OCI_SLAVE_ERROR                 , 10  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCI_SLAVE_ERROR );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR2_ADDR_PARITY_ERR                 , 11  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_ADDR_PARITY_ERR );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR2_DATA_PARITY_ERR                 , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_DATA_PARITY_ERR );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR2_SPARE1                          , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SPARE1     );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR2_FSM_ERR                         , 14  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_FSM_ERR    );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR2_SPARE2                          , 15  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SPARE2     );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR3_PULL_READ_UNDERFLOW             , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PULL_READ_UNDERFLOW );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR3_PUSH_WRITE_OVERFLOW             , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PUSH_WRITE_OVERFLOW );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR3_PULL_READ_UNDERFLOW_EN          , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PULL_READ_UNDERFLOW_EN );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR3_PUSH_WRITE_OVERFLOW_EN          , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_PUSH_WRITE_OVERFLOW_EN );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR3_STREAM_MODE                     , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_STREAM_MODE );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR3_STREAM_TYPE                     , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_STREAM_TYPE );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR3_SPARE0                          , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SPARE0     );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR3_SPARE0_LEN                      , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SPARE0_LEN );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR3_OCI_TIMEOUT                     , 8   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCI_TIMEOUT );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR3_OCI_READ_DATA_PARITY            , 9   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCI_READ_DATA_PARITY );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR3_OCI_SLAVE_ERROR                 , 10  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCI_SLAVE_ERROR );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR3_ADDR_PARITY_ERR                 , 11  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_ADDR_PARITY_ERR );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR3_DATA_PARITY_ERR                 , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_DATA_PARITY_ERR );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR3_SPARE1                          , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SPARE1     );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR3_FSM_ERR                         , 14  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_FSM_ERR    );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBCSR3_SPARE2                          , 15  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SPARE2     );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OCBDR0_DATA                             , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WO  , SH_FLD_DATA       );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBDR0_DATA_LEN                         , 64  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OCBDR1_DATA                             , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WO  , SH_FLD_DATA       );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBDR1_DATA_LEN                         , 64  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OCBDR2_DATA                             , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WO  , SH_FLD_DATA       );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBDR2_DATA_LEN                         , 64  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OCBDR3_DATA                             , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WO  , SH_FLD_DATA       );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBDR3_DATA_LEN                         , 64  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OCBEAR_ERROR_ADDRESS                    , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLRPART, SH_FLD_ERROR_ADDRESS );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBEAR_ERROR_ADDRESS_LEN                , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLRPART, SH_FLD_ERROR_ADDRESS_LEN );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBEAR_RESERVED_32_34                   , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLRPART, SH_FLD_RESERVED_32_34 );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBEAR_RESERVED_32_34_LEN               , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLRPART, SH_FLD_RESERVED_32_34_LEN );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBEAR_DIRECT_BRIDGE_SOURCE             , 35  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLRPART, SH_FLD_DIRECT_BRIDGE_SOURCE );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBEAR_INDIRECT_BRIDGE_0_SOURCE         , 36  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLRPART, SH_FLD_INDIRECT_BRIDGE_0_SOURCE );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBEAR_INDIRECT_BRIDGE_1_SOURCE         , 37  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLRPART, SH_FLD_INDIRECT_BRIDGE_1_SOURCE );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBEAR_INDIRECT_BRIDGE_2_SOURCE         , 38  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLRPART, SH_FLD_INDIRECT_BRIDGE_2_SOURCE );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBEAR_INDIRECT_BRIDGE_3_SOURCE         , 39  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLRPART, SH_FLD_INDIRECT_BRIDGE_3_SOURCE );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OCBESR0_ERROR_ADDR                      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLRREG, SH_FLD_ERROR_ADDR );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBESR0_ERROR_ADDR_LEN                  , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLRREG, SH_FLD_ERROR_ADDR_LEN );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OCBESR1_ERROR_ADDR                      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLRREG, SH_FLD_ERROR_ADDR );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBESR1_ERROR_ADDR_LEN                  , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLRREG, SH_FLD_ERROR_ADDR_LEN );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OCBESR2_ERROR_ADDR                      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLRREG, SH_FLD_ERROR_ADDR );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBESR2_ERROR_ADDR_LEN                  , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLRREG, SH_FLD_ERROR_ADDR_LEN );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OCBESR3_ERROR_ADDR                      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLRREG, SH_FLD_ERROR_ADDR );
+REG64_FLD( PU_GPE6_OCB_PIB_OCBESR3_ERROR_ADDR_LEN                  , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLRREG, SH_FLD_ERROR_ADDR_LEN );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OCDBG_MST_DIS_ABUSPAREN                 , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_MST_DIS_ABUSPAREN );
+REG64_FLD( PU_GPE6_OCB_PIB_OCDBG_MST_DIS_BEPAREN                   , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_MST_DIS_BEPAREN );
+REG64_FLD( PU_GPE6_OCB_PIB_OCDBG_MST_DIS_WRDBUSPAREN               , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_MST_DIS_WRDBUSPAREN );
+REG64_FLD( PU_GPE6_OCB_PIB_OCDBG_MST_DIS_RDDBUSPAR                 , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_MST_DIS_RDDBUSPAR );
+REG64_FLD( PU_GPE6_OCB_PIB_OCDBG_MST_SPARE                         , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_MST_SPARE  );
+REG64_FLD( PU_GPE6_OCB_PIB_OCDBG_SLV_DIS_SACK                      , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_SLV_DIS_SACK );
+REG64_FLD( PU_GPE6_OCB_PIB_OCDBG_SLV_DIS_ABUSPAR                   , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_SLV_DIS_ABUSPAR );
+REG64_FLD( PU_GPE6_OCB_PIB_OCDBG_SLV_DIS_BEPAR                     , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_SLV_DIS_BEPAR );
+REG64_FLD( PU_GPE6_OCB_PIB_OCDBG_SLV_DIS_BE                        , 8   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_SLV_DIS_BE );
+REG64_FLD( PU_GPE6_OCB_PIB_OCDBG_SLV_DIS_WRDBUSPAR                 , 9   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_SLV_DIS_WRDBUSPAR );
+REG64_FLD( PU_GPE6_OCB_PIB_OCDBG_SLV_DIS_RDDBUSPAREN               , 10  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_SLV_DIS_RDDBUSPAREN );
+REG64_FLD( PU_GPE6_OCB_PIB_OCDBG_SLV_SPARE                         , 11  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_SLV_SPARE  );
+REG64_FLD( PU_GPE6_OCB_PIB_OCDBG_SPARE                             , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE6_OCB_PIB_OCDBG_SPARE_LEN                         , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OCR_CORE_RESET                          , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_CORE_RESET );
+REG64_FLD( PU_GPE6_OCB_PIB_OCR_CHIP_RESET                          , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_CHIP_RESET );
+REG64_FLD( PU_GPE6_OCB_PIB_OCR_SYSTEM_RESET                        , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SYSTEM_RESET );
+REG64_FLD( PU_GPE6_OCB_PIB_OCR_OCI_ARB_RESET                       , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCI_ARB_RESET );
+REG64_FLD( PU_GPE6_OCB_PIB_OCR_TRACE_DISABLE                       , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_TRACE_DISABLE );
+REG64_FLD( PU_GPE6_OCB_PIB_OCR_TRACE_EVENT                         , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_TRACE_EVENT );
+REG64_FLD( PU_GPE6_OCB_PIB_OCR_DBG_UNCONDITIONAL_EVENT             , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_DBG_UNCONDITIONAL_EVENT );
+REG64_FLD( PU_GPE6_OCB_PIB_OCR_EXT_INTERRUPT                       , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_EXT_INTERRUPT );
+REG64_FLD( PU_GPE6_OCB_PIB_OCR_CRITICAL_INTERRUPT                  , 8   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_CRITICAL_INTERRUPT );
+REG64_FLD( PU_GPE6_OCB_PIB_OCR_SLAVE_RESET_TO_405_ENABLE           , 9   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SLAVE_RESET_TO_405_ENABLE );
+REG64_FLD( PU_GPE6_OCB_PIB_OCR_OCR_DBG_HALT                        , 10  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_OCR_DBG_HALT );
+REG64_FLD( PU_GPE6_OCB_PIB_OCR_SPARE                               , 11  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE6_OCB_PIB_OCR_SPARE_LEN                           , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM2_OR , SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OEAR_OCI_TIMEOUT_ADDR                   , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OCI_TIMEOUT_ADDR );
+REG64_FLD( PU_GPE6_OCB_PIB_OEAR_OCI_TIMEOUT_ADDR_LEN               , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OCI_TIMEOUT_ADDR_LEN );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M0_TIMEOUT_ERROR               , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M0_TIMEOUT_ERROR );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M0_RW_STATUS                   , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M0_RW_STATUS );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M0_FLCK                        , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M0_FLCK );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M0_OEAR_LOCK                   , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M0_OEAR_LOCK );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M1_TIMEOUT_ERROR               , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M1_TIMEOUT_ERROR );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M1_RW_STATUS                   , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M1_RW_STATUS );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M1_FLCK                        , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M1_FLCK );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M1_OEAR_LOCK                   , 7   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M1_OEAR_LOCK );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M2_TIMEOUT_ERROR               , 8   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M2_TIMEOUT_ERROR );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M2_RW_STATUS                   , 9   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M2_RW_STATUS );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M2_FLCK                        , 10  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M2_FLCK );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M2_OEAR_LOCK                   , 11  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M2_OEAR_LOCK );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M3_TIMEOUT_ERROR               , 12  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M3_TIMEOUT_ERROR );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M3_RW_STATUS                   , 13  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M3_RW_STATUS );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M3_FLCK                        , 14  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M3_FLCK );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M3_OEAR_LOCK                   , 15  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M3_OEAR_LOCK );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M4_TIMEOUT_ERROR               , 16  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M4_TIMEOUT_ERROR );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M4_RW_STATUS                   , 17  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M4_RW_STATUS );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M4_FLCK                        , 18  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M4_FLCK );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M4_OEAR_LOCK                   , 19  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M4_OEAR_LOCK );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M5_TIMEOUT_ERROR               , 20  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M5_TIMEOUT_ERROR );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M5_RW_STATUS                   , 21  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M5_RW_STATUS );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M5_FLCK                        , 22  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M5_FLCK );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M5_OEAR_LOCK                   , 23  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M5_OEAR_LOCK );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M6_TIMEOUT_ERROR               , 24  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M6_TIMEOUT_ERROR );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M6_RW_STATUS                   , 25  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M6_RW_STATUS );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M6_FLCK                        , 26  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M6_FLCK );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M6_OEAR_LOCK                   , 27  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M6_OEAR_LOCK );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M7_TIMEOUT_ERROR               , 28  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M7_TIMEOUT_ERROR );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M7_RW_STATUS                   , 29  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M7_RW_STATUS );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M7_FLCK                        , 30  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M7_FLCK );
+REG64_FLD( PU_GPE6_OCB_PIB_OESR_OCI_M7_OEAR_LOCK                   , 31  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M7_OEAR_LOCK );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OPPCINJ_OCI_ERR_INJ_DCU                 , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCI_ERR_INJ_DCU );
+REG64_FLD( PU_GPE6_OCB_PIB_OPPCINJ_OCI_ERR_INJ_ICU                 , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCI_ERR_INJ_ICU );
+REG64_FLD( PU_GPE6_OCB_PIB_OPPCINJ_OCI_ERR_INJ_CE_UE               , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCI_ERR_INJ_CE_UE );
+REG64_FLD( PU_GPE6_OCB_PIB_OPPCINJ_OCI_ERR_INJ_SINGL_CONT          , 3   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCI_ERR_INJ_SINGL_CONT );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OSTOEAR_OCC_SPCL_TIMEOUT_ADDR           , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OCC_SPCL_TIMEOUT_ADDR );
+REG64_FLD( PU_GPE6_OCB_PIB_OSTOEAR_OCC_SPCL_TIMEOUT_ADDR_LEN       , 32  ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RO  , SH_FLD_OCC_SPCL_TIMEOUT_ADDR_LEN );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OSTOESR_ICU_TIMEOUT_ERROR               , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_ICU_TIMEOUT_ERROR );
+REG64_FLD( PU_GPE6_OCB_PIB_OSTOESR_ICU_RNW                         , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_ICU_RNW    );
+REG64_FLD( PU_GPE6_OCB_PIB_OSTOESR_RESERVED_2_3                    , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_RESERVED_2_3 );
+REG64_FLD( PU_GPE6_OCB_PIB_OSTOESR_RESERVED_2_3_LEN                , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_RESERVED_2_3_LEN );
+REG64_FLD( PU_GPE6_OCB_PIB_OSTOESR_DCU_TIMEOUT_ERROR               , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_DCU_TIMEOUT_ERROR );
+REG64_FLD( PU_GPE6_OCB_PIB_OSTOESR_DCU_RNW                         , 5   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_DCU_RNW    );
+REG64_FLD( PU_GPE6_OCB_PIB_OSTOESR_RESERVED_6_7                    , 6   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_RESERVED_6_7 );
+REG64_FLD( PU_GPE6_OCB_PIB_OSTOESR_RESERVED_6_7_LEN                , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_WCLEAR, SH_FLD_RESERVED_6_7_LEN );
+
+REG64_FLD( PU_GPE6_OCB_PIB_OTDCR_TRACE_BUS_EN                      , 0   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_TRACE_BUS_EN );
+REG64_FLD( PU_GPE6_OCB_PIB_OTDCR_TRACE_MUX_SEL                     , 1   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_TRACE_MUX_SEL );
+REG64_FLD( PU_GPE6_OCB_PIB_OTDCR_OCC_TRACE_MUX_SEL                 , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCC_TRACE_MUX_SEL );
+REG64_FLD( PU_GPE6_OCB_PIB_OTDCR_OCC_TRACE_MUX_SEL_LEN             , 2   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCC_TRACE_MUX_SEL_LEN );
+REG64_FLD( PU_GPE6_OCB_PIB_OTDCR_OCI_TRACE_MUX_SEL                 , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCI_TRACE_MUX_SEL );
+REG64_FLD( PU_GPE6_OCB_PIB_OTDCR_OCI_TRACE_MUX_SEL_LEN             , 4   ,
+           SH_UNT_PU_GPE6  , SH_ACS_SCOM_RW  , SH_FLD_OCI_TRACE_MUX_SEL_LEN );
+
+REG64_FLD( PU_OSCERR_HOLD_CP                                       , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CP         );
+REG64_FLD( PU_OSCERR_HOLD_CP_LEN                                   , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CP_LEN     );
+REG64_FLD( PU_OSCERR_HOLD_MEM                                      , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MEM        );
+REG64_FLD( PU_OSCERR_HOLD_MEM_LEN                                  , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MEM_LEN    );
+REG64_FLD( PU_OSCERR_HOLD_GX                                       , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_GX         );
+REG64_FLD( PU_OSCERR_HOLD_GX_LEN                                   , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_GX_LEN     );
+REG64_FLD( PU_OSCERR_HOLD_CPLITE                                   , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CPLITE     );
+REG64_FLD( PU_OSCERR_HOLD_CPLITE_LEN                               , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CPLITE_LEN );
+
+REG64_FLD( PU_OSCERR_MASK_CP                                       , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CP         );
+REG64_FLD( PU_OSCERR_MASK_CP_LEN                                   , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CP_LEN     );
+REG64_FLD( PU_OSCERR_MASK_MEM                                      , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MEM        );
+REG64_FLD( PU_OSCERR_MASK_MEM_LEN                                  , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MEM_LEN    );
+REG64_FLD( PU_OSCERR_MASK_GX                                       , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_GX         );
+REG64_FLD( PU_OSCERR_MASK_GX_LEN                                   , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_GX_LEN     );
+REG64_FLD( PU_OSCERR_MASK_CPLITE                                   , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CPLITE     );
+REG64_FLD( PU_OSCERR_MASK_CPLITE_LEN                               , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CPLITE_LEN );
+
+REG64_FLD( PU_OSCERR_MCODE_IN                                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IN         );
+REG64_FLD( PU_OSCERR_MCODE_IN_LEN                                  , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IN_LEN     );
+
+REG64_FLD( PU_PBABAR0_CMD_SCOPE                                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CMD_SCOPE  );
+REG64_FLD( PU_PBABAR0_CMD_SCOPE_LEN                                , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CMD_SCOPE_LEN );
+REG64_FLD( PU_PBABAR0_RESERVED_3                                   , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_3 );
+REG64_FLD( PU_PBABAR0_ADDR                                         , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDR       );
+REG64_FLD( PU_PBABAR0_ADDR_LEN                                     , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_PBABAR0_VTARGET                                      , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VTARGET    );
+REG64_FLD( PU_PBABAR0_VTARGET_LEN                                  , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VTARGET_LEN );
+
+REG64_FLD( PU_PBABAR1_CMD_SCOPE                                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CMD_SCOPE  );
+REG64_FLD( PU_PBABAR1_CMD_SCOPE_LEN                                , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CMD_SCOPE_LEN );
+REG64_FLD( PU_PBABAR1_RESERVED_3                                   , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_3 );
+REG64_FLD( PU_PBABAR1_ADDR                                         , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDR       );
+REG64_FLD( PU_PBABAR1_ADDR_LEN                                     , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_PBABAR1_VTARGET                                      , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VTARGET    );
+REG64_FLD( PU_PBABAR1_VTARGET_LEN                                  , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VTARGET_LEN );
+
+REG64_FLD( PU_PBABAR2_CMD_SCOPE                                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CMD_SCOPE  );
+REG64_FLD( PU_PBABAR2_CMD_SCOPE_LEN                                , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CMD_SCOPE_LEN );
+REG64_FLD( PU_PBABAR2_RESERVED_3                                   , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_3 );
+REG64_FLD( PU_PBABAR2_ADDR                                         , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDR       );
+REG64_FLD( PU_PBABAR2_ADDR_LEN                                     , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_PBABAR2_VTARGET                                      , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VTARGET    );
+REG64_FLD( PU_PBABAR2_VTARGET_LEN                                  , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VTARGET_LEN );
+
+REG64_FLD( PU_PBABAR3_CMD_SCOPE                                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CMD_SCOPE  );
+REG64_FLD( PU_PBABAR3_CMD_SCOPE_LEN                                , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CMD_SCOPE_LEN );
+REG64_FLD( PU_PBABAR3_RESERVED_3                                   , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_3 );
+REG64_FLD( PU_PBABAR3_ADDR                                         , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDR       );
+REG64_FLD( PU_PBABAR3_ADDR_LEN                                     , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_PBABAR3_VTARGET                                      , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VTARGET    );
+REG64_FLD( PU_PBABAR3_VTARGET_LEN                                  , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VTARGET_LEN );
+
+REG64_FLD( PU_PBABARMSK0_MSK                                       , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MSK        );
+REG64_FLD( PU_PBABARMSK0_MSK_LEN                                   , 21  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MSK_LEN    );
+
+REG64_FLD( PU_PBABARMSK1_MSK                                       , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MSK        );
+REG64_FLD( PU_PBABARMSK1_MSK_LEN                                   , 21  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MSK_LEN    );
+
+REG64_FLD( PU_PBABARMSK2_MSK                                       , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MSK        );
+REG64_FLD( PU_PBABARMSK2_MSK_LEN                                   , 21  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MSK_LEN    );
+
+REG64_FLD( PU_PBABARMSK3_MSK                                       , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MSK        );
+REG64_FLD( PU_PBABARMSK3_MSK_LEN                                   , 21  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MSK_LEN    );
+
+REG64_FLD( PU_PBACFG_PBREQ_SLVFW_MAX_PRIORITY                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBREQ_SLVFW_MAX_PRIORITY );
+REG64_FLD( PU_PBACFG_PBREQ_EXIT_ON_HANG                            , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBREQ_EXIT_ON_HANG );
+REG64_FLD( PU_PBACFG_PBREQ_BCE_MAX_PRIORITY                        , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBREQ_BCE_MAX_PRIORITY );
+REG64_FLD( PU_PBACFG_PBREQ_EXIT_ON_HANG_PBAX                       , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBREQ_EXIT_ON_HANG_PBAX );
+REG64_FLD( PU_PBACFG_PBREQ_DATA_HANG_DIV                           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBREQ_DATA_HANG_DIV );
+REG64_FLD( PU_PBACFG_PBREQ_DATA_HANG_DIV_LEN                       , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBREQ_DATA_HANG_DIV_LEN );
+REG64_FLD( PU_PBACFG_PBREQ_OPER_HANG_DIV                           , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBREQ_OPER_HANG_DIV );
+REG64_FLD( PU_PBACFG_PBREQ_OPER_HANG_DIV_LEN                       , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBREQ_OPER_HANG_DIV_LEN );
+REG64_FLD( PU_PBACFG_PBREQ_DROP_PRIORITY_MASK                      , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBREQ_DROP_PRIORITY_MASK );
+REG64_FLD( PU_PBACFG_PBREQ_DROP_PRIORITY_MASK_LEN                  , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBREQ_DROP_PRIORITY_MASK_LEN );
+REG64_FLD( PU_PBACFG_PBREQ_EXIT_HANG_DIV                           , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBREQ_EXIT_HANG_DIV );
+REG64_FLD( PU_PBACFG_PBREQ_EXIT_HANG_DIV_LEN                       , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBREQ_EXIT_HANG_DIV_LEN );
+REG64_FLD( PU_PBACFG_CHSW_HANG_ON_ADRERROR                         , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHSW_HANG_ON_ADRERROR );
+REG64_FLD( PU_PBACFG_CHSW_DIS_OCIABUSPAR_CHECK                     , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHSW_DIS_OCIABUSPAR_CHECK );
+REG64_FLD( PU_PBACFG_CHSW_DIS_OCIBEPAR_CHECK                       , 26  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHSW_DIS_OCIBEPAR_CHECK );
+REG64_FLD( PU_PBACFG_CHSW_HANG_ON_DERROR                           , 27  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHSW_HANG_ON_DERROR );
+REG64_FLD( PU_PBACFG_RESERVED_28                                   , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_28 );
+REG64_FLD( PU_PBACFG_CHSW_DIS_WRITE_MATCH_REARB                    , 29  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHSW_DIS_WRITE_MATCH_REARB );
+REG64_FLD( PU_PBACFG_CHSW_DIS_OCIDATAPAR_GEN                       , 30  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHSW_DIS_OCIDATAPAR_GEN );
+REG64_FLD( PU_PBACFG_CHSW_DIS_OCIDATAPAR_CHECK                     , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHSW_DIS_OCIDATAPAR_CHECK );
+REG64_FLD( PU_PBACFG_CHSW_DIS_OPER_HANG                            , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHSW_DIS_OPER_HANG );
+REG64_FLD( PU_PBACFG_CHSW_DIS_DATA_HANG                            , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHSW_DIS_DATA_HANG );
+REG64_FLD( PU_PBACFG_CHSW_DIS_ECC_CHECK                            , 34  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHSW_DIS_ECC_CHECK );
+REG64_FLD( PU_PBACFG_CHSW_DIS_RETRY_BACKOFF                        , 35  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHSW_DIS_RETRY_BACKOFF );
+REG64_FLD( PU_PBACFG_CHSW_EXIT_ON_INVALID_CRESP                    , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHSW_EXIT_ON_INVALID_CRESP );
+REG64_FLD( PU_PBACFG_RESERVED_37                                   , 37  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_37 );
+REG64_FLD( PU_PBACFG_CHSW_DIS_GROUP_SCOPE                          , 38  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHSW_DIS_GROUP_SCOPE );
+REG64_FLD( PU_PBACFG_CHSW_DIS_RTAG_PARITY_CHK                      , 39  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHSW_DIS_RTAG_PARITY_CHK );
+REG64_FLD( PU_PBACFG_CHSW_DIS_PB_PARITY_CHK                        , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHSW_DIS_PB_PARITY_CHK );
+REG64_FLD( PU_PBACFG_CHSW_SKIP_GROUP_SCOPE                         , 41  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHSW_SKIP_GROUP_SCOPE );
+REG64_FLD( PU_PBACFG_CHSW_USE_PR_DMA_INJ                           , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHSW_USE_PR_DMA_INJ );
+REG64_FLD( PU_PBACFG_CHSW_USE_CL_DMA_INJ                           , 43  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CHSW_USE_CL_DMA_INJ );
+REG64_FLD( PU_PBACFG_RESERVED_44_47                                , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_44_47 );
+REG64_FLD( PU_PBACFG_RESERVED_44_47_LEN                            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_44_47_LEN );
+
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_RDDATATO_FW                       , 0   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_RDDATATO_FW );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_RDDATATO_FW_LEN                   , 6   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_RDDATATO_FW_LEN );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_RDADRERR_FW                       , 6   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_RDADRERR_FW );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_RDADRERR_FW_LEN                   , 6   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_RDADRERR_FW_LEN );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_WRADRERR_FW                       , 12  ,
+           SH_UNT          , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_WRADRERR_FW );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_WRADRERR_FW_LEN                   , 4   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_WRADRERR_FW_LEN );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_ACKDEAD_FW_RD                     , 16  ,
+           SH_UNT          , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_ACKDEAD_FW_RD );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_ACKDEAD_FW_RD_LEN                 , 6   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_ACKDEAD_FW_RD_LEN );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_ACKDEAD_FW_WR                     , 22  ,
+           SH_UNT          , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_ACKDEAD_FW_WR );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_ACKDEAD_FW_WR_LEN                 , 2   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_ACKDEAD_FW_WR_LEN );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_UNEXPCRESP                        , 24  ,
+           SH_UNT          , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_UNEXPCRESP );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_UNEXPCRESP_LEN                    , 11  ,
+           SH_UNT          , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_UNEXPCRESP_LEN );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_UNEXPDATA                         , 35  ,
+           SH_UNT          , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_UNEXPDATA );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_UNEXPDATA_LEN                     , 6   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_UNEXPDATA_LEN );
+
+REG64_FLD( PU_PBAERRRPT1_CERR_PB_BADCRESP                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_PB_BADCRESP );
+REG64_FLD( PU_PBAERRRPT1_CERR_PB_BADCRESP_LEN                      , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_PB_BADCRESP_LEN );
+REG64_FLD( PU_PBAERRRPT1_CERR_PB_OPERTO                            , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_PB_OPERTO );
+REG64_FLD( PU_PBAERRRPT1_CERR_PB_OPERTO_LEN                        , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_PB_OPERTO_LEN );
+REG64_FLD( PU_PBAERRRPT1_RESERVED_24_29                            , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RESERVED_24_29 );
+REG64_FLD( PU_PBAERRRPT1_RESERVED_24_29_LEN                        , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RESERVED_24_29_LEN );
+REG64_FLD( PU_PBAERRRPT1_CERR_BCDE_SETUP_ERR                       , 30  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_BCDE_SETUP_ERR );
+REG64_FLD( PU_PBAERRRPT1_CERR_BCDE_SETUP_ERR_LEN                   , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_BCDE_SETUP_ERR_LEN );
+REG64_FLD( PU_PBAERRRPT1_CERR_BCUE_SETUP_ERR                       , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_BCUE_SETUP_ERR );
+REG64_FLD( PU_PBAERRRPT1_CERR_BCUE_SETUP_ERR_LEN                   , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_BCUE_SETUP_ERR_LEN );
+REG64_FLD( PU_PBAERRRPT1_CERR_BCUE_OCI_DATAERR                     , 34  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_BCUE_OCI_DATAERR );
+REG64_FLD( PU_PBAERRRPT1_CERR_BCUE_OCI_DATAERR_LEN                 , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_BCUE_OCI_DATAERR_LEN );
+
+REG64_FLD( PU_PBAERRRPT2_CERR_SLV_INTERNAL_ERR                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_SLV_INTERNAL_ERR );
+REG64_FLD( PU_PBAERRRPT2_CERR_SLV_INTERNAL_ERR_LEN                 , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_SLV_INTERNAL_ERR_LEN );
+REG64_FLD( PU_PBAERRRPT2_CERR_BCDE_INTERNAL_ERR                    , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_BCDE_INTERNAL_ERR );
+REG64_FLD( PU_PBAERRRPT2_CERR_BCDE_INTERNAL_ERR_LEN                , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_BCDE_INTERNAL_ERR_LEN );
+REG64_FLD( PU_PBAERRRPT2_CERR_BCUE_INTERNAL_ERR                    , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_BCUE_INTERNAL_ERR );
+REG64_FLD( PU_PBAERRRPT2_CERR_BCUE_INTERNAL_ERR_LEN                , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_BCUE_INTERNAL_ERR_LEN );
+REG64_FLD( PU_PBAERRRPT2_CERR_BAR_PARITY_ERR                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_BAR_PARITY_ERR );
+REG64_FLD( PU_PBAERRRPT2_CERR_SCOMTB_ERR                           , 17  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_SCOMTB_ERR );
+REG64_FLD( PU_PBAERRRPT2_CERR_SPARE                                , 18  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_SPARE );
+REG64_FLD( PU_PBAERRRPT2_CERR_SPARE_LEN                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_SPARE_LEN );
+REG64_FLD( PU_PBAERRRPT2_CERR_PBDOUT_PARITY_ERR                    , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_PBDOUT_PARITY_ERR );
+REG64_FLD( PU_PBAERRRPT2_CERR_PB_PARITY_ERR                        , 21  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_PB_PARITY_ERR );
+REG64_FLD( PU_PBAERRRPT2_CERR_PB_PARITY_ERR_LEN                    , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_PB_PARITY_ERR_LEN );
+REG64_FLD( PU_PBAERRRPT2_CERR_AXFLOW_ERR                           , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_AXFLOW_ERR );
+REG64_FLD( PU_PBAERRRPT2_CERR_AXFLOW_ERR_LEN                       , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_AXFLOW_ERR_LEN );
+REG64_FLD( PU_PBAERRRPT2_CERR_AXPUSH_WRERR                         , 29  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_AXPUSH_WRERR );
+REG64_FLD( PU_PBAERRRPT2_CERR_AXPUSH_WRERR_LEN                     , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CERR_AXPUSH_WRERR_LEN );
+
+REG64_FLD( PU_PBAFIR_OCI_APAR_ERR                                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_OCI_APAR_ERR );
+REG64_FLD( PU_PBAFIR_PB_RDADRERR_FW                                , 1   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_RDADRERR_FW );
+REG64_FLD( PU_PBAFIR_PB_RDDATATO_FW                                , 2   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_RDDATATO_FW );
+REG64_FLD( PU_PBAFIR_PB_SUE_FW                                     , 3   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_SUE_FW  );
+REG64_FLD( PU_PBAFIR_PB_UE_FW                                      , 4   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_UE_FW   );
+REG64_FLD( PU_PBAFIR_PB_CE_FW                                      , 5   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_CE_FW   );
+REG64_FLD( PU_PBAFIR_OCI_SLAVE_INIT                                , 6   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_OCI_SLAVE_INIT );
+REG64_FLD( PU_PBAFIR_OCI_WRPAR_ERR                                 , 7   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_OCI_WRPAR_ERR );
+REG64_FLD( PU_PBAFIR_RESERVED_8                                    , 8   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_8 );
+REG64_FLD( PU_PBAFIR_PB_UNEXPCRESP                                 , 9   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_UNEXPCRESP );
+REG64_FLD( PU_PBAFIR_PB_UNEXPDATA                                  , 10  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_UNEXPDATA );
+REG64_FLD( PU_PBAFIR_PB_PARITY_ERR                                 , 11  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_PARITY_ERR );
+REG64_FLD( PU_PBAFIR_PB_WRADRERR_FW                                , 12  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_WRADRERR_FW );
+REG64_FLD( PU_PBAFIR_PB_BADCRESP                                   , 13  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_BADCRESP );
+REG64_FLD( PU_PBAFIR_PB_ACKDEAD_FW_RD                              , 14  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_ACKDEAD_FW_RD );
+REG64_FLD( PU_PBAFIR_PB_OPERTO                                     , 15  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_OPERTO  );
+REG64_FLD( PU_PBAFIR_BCUE_SETUP_ERR                                , 16  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCUE_SETUP_ERR );
+REG64_FLD( PU_PBAFIR_BCUE_PB_ACK_DEAD                              , 17  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCUE_PB_ACK_DEAD );
+REG64_FLD( PU_PBAFIR_BCUE_PB_ADRERR                                , 18  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCUE_PB_ADRERR );
+REG64_FLD( PU_PBAFIR_BCUE_OCI_DATERR                               , 19  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCUE_OCI_DATERR );
+REG64_FLD( PU_PBAFIR_BCDE_SETUP_ERR                                , 20  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCDE_SETUP_ERR );
+REG64_FLD( PU_PBAFIR_BCDE_PB_ACK_DEAD                              , 21  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCDE_PB_ACK_DEAD );
+REG64_FLD( PU_PBAFIR_BCDE_PB_ADRERR                                , 22  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCDE_PB_ADRERR );
+REG64_FLD( PU_PBAFIR_BCDE_RDDATATO_ERR                             , 23  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCDE_RDDATATO_ERR );
+REG64_FLD( PU_PBAFIR_BCDE_SUE_ERR                                  , 24  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCDE_SUE_ERR );
+REG64_FLD( PU_PBAFIR_BCDE_UE_ERR                                   , 25  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCDE_UE_ERR );
+REG64_FLD( PU_PBAFIR_BCDE_CE                                       , 26  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCDE_CE    );
+REG64_FLD( PU_PBAFIR_BCDE_OCI_DATERR                               , 27  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCDE_OCI_DATERR );
+REG64_FLD( PU_PBAFIR_INTERNAL_ERR                                  , 28  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_ERR );
+REG64_FLD( PU_PBAFIR_ILLEGAL_CACHE_OP                              , 29  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_ILLEGAL_CACHE_OP );
+REG64_FLD( PU_PBAFIR_OCI_BAD_REG_ADDR                              , 30  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_OCI_BAD_REG_ADDR );
+REG64_FLD( PU_PBAFIR_AXPUSH_WRERR                                  , 31  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_AXPUSH_WRERR );
+REG64_FLD( PU_PBAFIR_AXRCV_DLO_ERR                                 , 32  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_AXRCV_DLO_ERR );
+REG64_FLD( PU_PBAFIR_AXRCV_DLO_TO                                  , 33  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_AXRCV_DLO_TO );
+REG64_FLD( PU_PBAFIR_AXRCV_RSVDATA_TO                              , 34  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_AXRCV_RSVDATA_TO );
+REG64_FLD( PU_PBAFIR_AXFLOW_ERR                                    , 35  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_AXFLOW_ERR );
+REG64_FLD( PU_PBAFIR_AXSND_DHI_RTYTO                               , 36  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_AXSND_DHI_RTYTO );
+REG64_FLD( PU_PBAFIR_AXSND_DLO_RTYTO                               , 37  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_AXSND_DLO_RTYTO );
+REG64_FLD( PU_PBAFIR_AXSND_RSVTO                                   , 38  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_AXSND_RSVTO );
+REG64_FLD( PU_PBAFIR_AXSND_RSVERR                                  , 39  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_AXSND_RSVERR );
+REG64_FLD( PU_PBAFIR_PB_ACKDEAD_FW_WR                              , 40  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_ACKDEAD_FW_WR );
+REG64_FLD( PU_PBAFIR_RESERVED_41                                   , 41  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_41 );
+REG64_FLD( PU_PBAFIR_RESERVED_42                                   , 42  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_42 );
+REG64_FLD( PU_PBAFIR_RESERVED_43                                   , 43  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_43 );
+REG64_FLD( PU_PBAFIR_FIR_PARITY_ERR2                               , 44  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FIR_PARITY_ERR2 );
+REG64_FLD( PU_PBAFIR_FIR_PARITY_ERR                                , 45  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FIR_PARITY_ERR );
+
+REG64_FLD( PU_PBAFIRACT0_FIR_ACTION0                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FIR_ACTION0 );
+REG64_FLD( PU_PBAFIRACT0_FIR_ACTION0_LEN                           , 46  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FIR_ACTION0_LEN );
+
+REG64_FLD( PU_PBAFIRACT1_FIR_ACTION1                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FIR_ACTION1 );
+REG64_FLD( PU_PBAFIRACT1_FIR_ACTION1_LEN                           , 46  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FIR_ACTION1_LEN );
+
+REG64_FLD( PU_PBAFIRMASK_OCI_APAR_ERR_MASK                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_OCI_APAR_ERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_RDADRERR_FW_MASK                       , 1   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_RDADRERR_FW_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_RDDATATO_FW_MASK                       , 2   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_RDDATATO_FW_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_SUE_FW_MASK                            , 3   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_SUE_FW_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_UE_FW_MASK                             , 4   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_UE_FW_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_CE_FW_MASK                             , 5   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_CE_FW_MASK );
+REG64_FLD( PU_PBAFIRMASK_OCI_SLAVE_INIT_MASK                       , 6   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_OCI_SLAVE_INIT_MASK );
+REG64_FLD( PU_PBAFIRMASK_OCI_WRPAR_ERR_MASK                        , 7   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_OCI_WRPAR_ERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_RESERVED_8                                , 8   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_8 );
+REG64_FLD( PU_PBAFIRMASK_PB_UNEXPCRESP_MASK                        , 9   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_UNEXPCRESP_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_UNEXPDATA_MASK                         , 10  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_UNEXPDATA_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_PARITY_ERR_MASK                        , 11  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_PARITY_ERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_WRADRERR_FW_MASK                       , 12  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_WRADRERR_FW_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_BADCRESP_MASK                          , 13  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_BADCRESP_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_ACKDEAD_FW_RD_MASK                     , 14  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_ACKDEAD_FW_RD_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_OPERTO_MASK                            , 15  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_OPERTO_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCUE_SETUP_ERR_MASK                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCUE_SETUP_ERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCUE_PB_ACK_DEAD_MASK                     , 17  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCUE_PB_ACK_DEAD_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCUE_PB_ADRERR_MASK                       , 18  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCUE_PB_ADRERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCUE_OCI_DATERR_MASK                      , 19  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCUE_OCI_DATERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCDE_SETUP_ERR_MASK                       , 20  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCDE_SETUP_ERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCDE_PB_ACK_DEAD_MASK                     , 21  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCDE_PB_ACK_DEAD_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCDE_PB_ADRERR_MASK                       , 22  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCDE_PB_ADRERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCDE_RDDATATO_ERR_MASK                    , 23  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCDE_RDDATATO_ERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCDE_SUE_ERR_MASK                         , 24  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCDE_SUE_ERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCDE_UE_ERR_MASK                          , 25  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCDE_UE_ERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCDE_CE_MASK                              , 26  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCDE_CE_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCDE_OCI_DATERR_MASK                      , 27  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_BCDE_OCI_DATERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_INTERNAL_ERR_MASK                         , 28  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_ERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_ILLEGAL_CACHE_OP_MASK                     , 29  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_ILLEGAL_CACHE_OP_MASK );
+REG64_FLD( PU_PBAFIRMASK_OCI_BAD_REG_ADDR_MASK                     , 30  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_OCI_BAD_REG_ADDR_MASK );
+REG64_FLD( PU_PBAFIRMASK_AXPUSH_WRERR_MASK                         , 31  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_AXPUSH_WRERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_AXRCV_DLO_ERR_MASK                        , 32  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_AXRCV_DLO_ERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_AXRCV_DLO_TO_MASK                         , 33  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_AXRCV_DLO_TO_MASK );
+REG64_FLD( PU_PBAFIRMASK_AXRCV_RSVDATA_TO_MASK                     , 34  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_AXRCV_RSVDATA_TO_MASK );
+REG64_FLD( PU_PBAFIRMASK_AXFLOW_ERR_MASK                           , 35  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_AXFLOW_ERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_AXSND_DHI_RTYTO_MASK                      , 36  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_AXSND_DHI_RTYTO_MASK );
+REG64_FLD( PU_PBAFIRMASK_AXSND_DLO_RTYTO_MASK                      , 37  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_AXSND_DLO_RTYTO_MASK );
+REG64_FLD( PU_PBAFIRMASK_AXSND_RSVTO_MASK                          , 38  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_AXSND_RSVTO_MASK );
+REG64_FLD( PU_PBAFIRMASK_AXSND_RSVERR_MASK                         , 39  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_AXSND_RSVERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_ACKDEAD_FW_WR_MASK                     , 40  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_ACKDEAD_FW_WR_MASK );
+REG64_FLD( PU_PBAFIRMASK_RESERVED_41_43                            , 41  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_41_43 );
+REG64_FLD( PU_PBAFIRMASK_RESERVED_41_43_LEN                        , 3   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_41_43_LEN );
+REG64_FLD( PU_PBAFIRMASK_FIR_PARITY_ERR2_MASK                      , 44  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FIR_PARITY_ERR2_MASK );
+REG64_FLD( PU_PBAFIRMASK_FIR_PARITY_ERR_MASK                       , 45  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FIR_PARITY_ERR_MASK );
+
+REG64_FLD( PU_PBAIB1_PBAIBHWCFG_REG_PE_OSMB_DATASTART_MODE         , 16  ,
+           SH_UNT_PU_PBAIB1, SH_ACS_SCOM_RW  , SH_FLD_PE_OSMB_DATASTART_MODE );
+REG64_FLD( PU_PBAIB1_PBAIBHWCFG_REG_PE_OSMB_DATASTART_MODE_LEN     , 3   ,
+           SH_UNT_PU_PBAIB1, SH_ACS_SCOM_RW  , SH_FLD_PE_OSMB_DATASTART_MODE_LEN );
+REG64_FLD( PU_PBAIB1_PBAIBHWCFG_REG_PE_TX_RESP_HWM                 , 20  ,
+           SH_UNT_PU_PBAIB1, SH_ACS_SCOM_RW  , SH_FLD_PE_TX_RESP_HWM );
+REG64_FLD( PU_PBAIB1_PBAIBHWCFG_REG_PE_TX_RESP_HWM_LEN             , 4   ,
+           SH_UNT_PU_PBAIB1, SH_ACS_SCOM_RW  , SH_FLD_PE_TX_RESP_HWM_LEN );
+REG64_FLD( PU_PBAIB1_PBAIBHWCFG_REG_PE_TX_RESP_LWM                 , 24  ,
+           SH_UNT_PU_PBAIB1, SH_ACS_SCOM_RW  , SH_FLD_PE_TX_RESP_LWM );
+REG64_FLD( PU_PBAIB1_PBAIBHWCFG_REG_PE_TX_RESP_LWM_LEN             , 4   ,
+           SH_UNT_PU_PBAIB1, SH_ACS_SCOM_RW  , SH_FLD_PE_TX_RESP_LWM_LEN );
+REG64_FLD( PU_PBAIB1_PBAIBHWCFG_REG_PE_OSMB_EARLYEMPTY_MODE        , 28  ,
+           SH_UNT_PU_PBAIB1, SH_ACS_SCOM_RW  , SH_FLD_PE_OSMB_EARLYEMPTY_MODE );
+REG64_FLD( PU_PBAIB1_PBAIBHWCFG_REG_PE_OSMB_EARLYEMPTY_MODE_LEN    , 2   ,
+           SH_UNT_PU_PBAIB1, SH_ACS_SCOM_RW  , SH_FLD_PE_OSMB_EARLYEMPTY_MODE_LEN );
+REG64_FLD( PU_PBAIB1_PBAIBHWCFG_REG_PE_PCIE_CLK_TRACE_EN           , 30  ,
+           SH_UNT_PU_PBAIB1, SH_ACS_SCOM_RW  , SH_FLD_PE_PCIE_CLK_TRACE_EN );
+REG64_FLD( PU_PBAIB1_PBAIBHWCFG_REG_PE_SELECT_ETU_TRACE            , 31  ,
+           SH_UNT_PU_PBAIB1, SH_ACS_SCOM_RW  , SH_FLD_PE_SELECT_ETU_TRACE );
+REG64_FLD( PU_PBAIB1_PBAIBHWCFG_REG_PE_PCI_CLK_TRACE_SEL           , 32  ,
+           SH_UNT_PU_PBAIB1, SH_ACS_SCOM_RW  , SH_FLD_PE_PCI_CLK_TRACE_SEL );
+REG64_FLD( PU_PBAIB1_PBAIBHWCFG_REG_PE_PCI_CLK_TRACE_SEL_LEN       , 4   ,
+           SH_UNT_PU_PBAIB1, SH_ACS_SCOM_RW  , SH_FLD_PE_PCI_CLK_TRACE_SEL_LEN );
+REG64_FLD( PU_PBAIB1_PBAIBHWCFG_REG_PE_ISMB_ERROR_INJECT           , 36  ,
+           SH_UNT_PU_PBAIB1, SH_ACS_SCOM_RW  , SH_FLD_PE_ISMB_ERROR_INJECT );
+REG64_FLD( PU_PBAIB1_PBAIBHWCFG_REG_PE_ISMB_ERROR_INJECT_LEN       , 3   ,
+           SH_UNT_PU_PBAIB1, SH_ACS_SCOM_RW  , SH_FLD_PE_ISMB_ERROR_INJECT_LEN );
+REG64_FLD( PU_PBAIB1_PBAIBHWCFG_REG_PE_OSMB_HOL_BLK_CNT            , 40  ,
+           SH_UNT_PU_PBAIB1, SH_ACS_SCOM_RW  , SH_FLD_PE_OSMB_HOL_BLK_CNT );
+REG64_FLD( PU_PBAIB1_PBAIBHWCFG_REG_PE_OSMB_HOL_BLK_CNT_LEN        , 3   ,
+           SH_UNT_PU_PBAIB1, SH_ACS_SCOM_RW  , SH_FLD_PE_OSMB_HOL_BLK_CNT_LEN );
+
+REG64_FLD( PU_PBAIB2_PBAIBHWCFG_REG_PE_OSMB_DATASTART_MODE         , 16  ,
+           SH_UNT_PU_PBAIB2, SH_ACS_SCOM_RW  , SH_FLD_PE_OSMB_DATASTART_MODE );
+REG64_FLD( PU_PBAIB2_PBAIBHWCFG_REG_PE_OSMB_DATASTART_MODE_LEN     , 3   ,
+           SH_UNT_PU_PBAIB2, SH_ACS_SCOM_RW  , SH_FLD_PE_OSMB_DATASTART_MODE_LEN );
+REG64_FLD( PU_PBAIB2_PBAIBHWCFG_REG_PE_TX_RESP_HWM                 , 20  ,
+           SH_UNT_PU_PBAIB2, SH_ACS_SCOM_RW  , SH_FLD_PE_TX_RESP_HWM );
+REG64_FLD( PU_PBAIB2_PBAIBHWCFG_REG_PE_TX_RESP_HWM_LEN             , 4   ,
+           SH_UNT_PU_PBAIB2, SH_ACS_SCOM_RW  , SH_FLD_PE_TX_RESP_HWM_LEN );
+REG64_FLD( PU_PBAIB2_PBAIBHWCFG_REG_PE_TX_RESP_LWM                 , 24  ,
+           SH_UNT_PU_PBAIB2, SH_ACS_SCOM_RW  , SH_FLD_PE_TX_RESP_LWM );
+REG64_FLD( PU_PBAIB2_PBAIBHWCFG_REG_PE_TX_RESP_LWM_LEN             , 4   ,
+           SH_UNT_PU_PBAIB2, SH_ACS_SCOM_RW  , SH_FLD_PE_TX_RESP_LWM_LEN );
+REG64_FLD( PU_PBAIB2_PBAIBHWCFG_REG_PE_OSMB_EARLYEMPTY_MODE        , 28  ,
+           SH_UNT_PU_PBAIB2, SH_ACS_SCOM_RW  , SH_FLD_PE_OSMB_EARLYEMPTY_MODE );
+REG64_FLD( PU_PBAIB2_PBAIBHWCFG_REG_PE_OSMB_EARLYEMPTY_MODE_LEN    , 2   ,
+           SH_UNT_PU_PBAIB2, SH_ACS_SCOM_RW  , SH_FLD_PE_OSMB_EARLYEMPTY_MODE_LEN );
+REG64_FLD( PU_PBAIB2_PBAIBHWCFG_REG_PE_PCIE_CLK_TRACE_EN           , 30  ,
+           SH_UNT_PU_PBAIB2, SH_ACS_SCOM_RW  , SH_FLD_PE_PCIE_CLK_TRACE_EN );
+REG64_FLD( PU_PBAIB2_PBAIBHWCFG_REG_PE_SELECT_ETU_TRACE            , 31  ,
+           SH_UNT_PU_PBAIB2, SH_ACS_SCOM_RW  , SH_FLD_PE_SELECT_ETU_TRACE );
+REG64_FLD( PU_PBAIB2_PBAIBHWCFG_REG_PE_PCI_CLK_TRACE_SEL           , 32  ,
+           SH_UNT_PU_PBAIB2, SH_ACS_SCOM_RW  , SH_FLD_PE_PCI_CLK_TRACE_SEL );
+REG64_FLD( PU_PBAIB2_PBAIBHWCFG_REG_PE_PCI_CLK_TRACE_SEL_LEN       , 4   ,
+           SH_UNT_PU_PBAIB2, SH_ACS_SCOM_RW  , SH_FLD_PE_PCI_CLK_TRACE_SEL_LEN );
+REG64_FLD( PU_PBAIB2_PBAIBHWCFG_REG_PE_ISMB_ERROR_INJECT           , 36  ,
+           SH_UNT_PU_PBAIB2, SH_ACS_SCOM_RW  , SH_FLD_PE_ISMB_ERROR_INJECT );
+REG64_FLD( PU_PBAIB2_PBAIBHWCFG_REG_PE_ISMB_ERROR_INJECT_LEN       , 3   ,
+           SH_UNT_PU_PBAIB2, SH_ACS_SCOM_RW  , SH_FLD_PE_ISMB_ERROR_INJECT_LEN );
+REG64_FLD( PU_PBAIB2_PBAIBHWCFG_REG_PE_OSMB_HOL_BLK_CNT            , 40  ,
+           SH_UNT_PU_PBAIB2, SH_ACS_SCOM_RW  , SH_FLD_PE_OSMB_HOL_BLK_CNT );
+REG64_FLD( PU_PBAIB2_PBAIBHWCFG_REG_PE_OSMB_HOL_BLK_CNT_LEN        , 3   ,
+           SH_UNT_PU_PBAIB2, SH_ACS_SCOM_RW  , SH_FLD_PE_OSMB_HOL_BLK_CNT_LEN );
+
+REG64_FLD( PU_PBAIB0_PBAIBHWCFG_REG_PE_OSMB_DATASTART_MODE         , 16  ,
+           SH_UNT_PU_PBAIB0, SH_ACS_SCOM_RW  , SH_FLD_PE_OSMB_DATASTART_MODE );
+REG64_FLD( PU_PBAIB0_PBAIBHWCFG_REG_PE_OSMB_DATASTART_MODE_LEN     , 3   ,
+           SH_UNT_PU_PBAIB0, SH_ACS_SCOM_RW  , SH_FLD_PE_OSMB_DATASTART_MODE_LEN );
+REG64_FLD( PU_PBAIB0_PBAIBHWCFG_REG_PE_TX_RESP_HWM                 , 20  ,
+           SH_UNT_PU_PBAIB0, SH_ACS_SCOM_RW  , SH_FLD_PE_TX_RESP_HWM );
+REG64_FLD( PU_PBAIB0_PBAIBHWCFG_REG_PE_TX_RESP_HWM_LEN             , 4   ,
+           SH_UNT_PU_PBAIB0, SH_ACS_SCOM_RW  , SH_FLD_PE_TX_RESP_HWM_LEN );
+REG64_FLD( PU_PBAIB0_PBAIBHWCFG_REG_PE_TX_RESP_LWM                 , 24  ,
+           SH_UNT_PU_PBAIB0, SH_ACS_SCOM_RW  , SH_FLD_PE_TX_RESP_LWM );
+REG64_FLD( PU_PBAIB0_PBAIBHWCFG_REG_PE_TX_RESP_LWM_LEN             , 4   ,
+           SH_UNT_PU_PBAIB0, SH_ACS_SCOM_RW  , SH_FLD_PE_TX_RESP_LWM_LEN );
+REG64_FLD( PU_PBAIB0_PBAIBHWCFG_REG_PE_OSMB_EARLYEMPTY_MODE        , 28  ,
+           SH_UNT_PU_PBAIB0, SH_ACS_SCOM_RW  , SH_FLD_PE_OSMB_EARLYEMPTY_MODE );
+REG64_FLD( PU_PBAIB0_PBAIBHWCFG_REG_PE_OSMB_EARLYEMPTY_MODE_LEN    , 2   ,
+           SH_UNT_PU_PBAIB0, SH_ACS_SCOM_RW  , SH_FLD_PE_OSMB_EARLYEMPTY_MODE_LEN );
+REG64_FLD( PU_PBAIB0_PBAIBHWCFG_REG_PE_PCIE_CLK_TRACE_EN           , 30  ,
+           SH_UNT_PU_PBAIB0, SH_ACS_SCOM_RW  , SH_FLD_PE_PCIE_CLK_TRACE_EN );
+REG64_FLD( PU_PBAIB0_PBAIBHWCFG_REG_PE_SELECT_ETU_TRACE            , 31  ,
+           SH_UNT_PU_PBAIB0, SH_ACS_SCOM_RW  , SH_FLD_PE_SELECT_ETU_TRACE );
+REG64_FLD( PU_PBAIB0_PBAIBHWCFG_REG_PE_PCI_CLK_TRACE_SEL           , 32  ,
+           SH_UNT_PU_PBAIB0, SH_ACS_SCOM_RW  , SH_FLD_PE_PCI_CLK_TRACE_SEL );
+REG64_FLD( PU_PBAIB0_PBAIBHWCFG_REG_PE_PCI_CLK_TRACE_SEL_LEN       , 4   ,
+           SH_UNT_PU_PBAIB0, SH_ACS_SCOM_RW  , SH_FLD_PE_PCI_CLK_TRACE_SEL_LEN );
+REG64_FLD( PU_PBAIB0_PBAIBHWCFG_REG_PE_ISMB_ERROR_INJECT           , 36  ,
+           SH_UNT_PU_PBAIB0, SH_ACS_SCOM_RW  , SH_FLD_PE_ISMB_ERROR_INJECT );
+REG64_FLD( PU_PBAIB0_PBAIBHWCFG_REG_PE_ISMB_ERROR_INJECT_LEN       , 3   ,
+           SH_UNT_PU_PBAIB0, SH_ACS_SCOM_RW  , SH_FLD_PE_ISMB_ERROR_INJECT_LEN );
+REG64_FLD( PU_PBAIB0_PBAIBHWCFG_REG_PE_OSMB_HOL_BLK_CNT            , 40  ,
+           SH_UNT_PU_PBAIB0, SH_ACS_SCOM_RW  , SH_FLD_PE_OSMB_HOL_BLK_CNT );
+REG64_FLD( PU_PBAIB0_PBAIBHWCFG_REG_PE_OSMB_HOL_BLK_CNT_LEN        , 3   ,
+           SH_UNT_PU_PBAIB0, SH_ACS_SCOM_RW  , SH_FLD_PE_OSMB_HOL_BLK_CNT_LEN );
+
+REG64_FLD( PU_PBAMODE_RESERVED_0_3                                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_0_3 );
+REG64_FLD( PU_PBAMODE_RESERVED_0_3_LEN                             , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_0_3_LEN );
+REG64_FLD( PU_PBAMODE_DIS_REARB                                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DIS_REARB  );
+REG64_FLD( PU_PBAMODE_DIS_MSTID_MATCH_PREF_INV                     , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DIS_MSTID_MATCH_PREF_INV );
+REG64_FLD( PU_PBAMODE_DIS_SLAVE_RDPIPE                             , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DIS_SLAVE_RDPIPE );
+REG64_FLD( PU_PBAMODE_DIS_SLAVE_WRPIPE                             , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DIS_SLAVE_WRPIPE );
+REG64_FLD( PU_PBAMODE_EN_MARKER_ACK                                , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_EN_MARKER_ACK );
+REG64_FLD( PU_PBAMODE_RESERVED_9                                   , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_9 );
+REG64_FLD( PU_PBAMODE_EN_SECOND_WRBUF                              , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_EN_SECOND_WRBUF );
+REG64_FLD( PU_PBAMODE_DIS_REREQUEST_TO                             , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DIS_REREQUEST_TO );
+REG64_FLD( PU_PBAMODE_INJECT_TYPE                                  , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INJECT_TYPE );
+REG64_FLD( PU_PBAMODE_INJECT_TYPE_LEN                              , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INJECT_TYPE_LEN );
+REG64_FLD( PU_PBAMODE_INJECT_MODE                                  , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INJECT_MODE );
+REG64_FLD( PU_PBAMODE_INJECT_MODE_LEN                              , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INJECT_MODE_LEN );
+REG64_FLD( PU_PBAMODE_PBA_REGION                                   , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PBA_REGION );
+REG64_FLD( PU_PBAMODE_PBA_REGION_LEN                               , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PBA_REGION_LEN );
+REG64_FLD( PU_PBAMODE_OCI_MARKER_SPACE                             , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OCI_MARKER_SPACE );
+REG64_FLD( PU_PBAMODE_OCI_MARKER_SPACE_LEN                         , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OCI_MARKER_SPACE_LEN );
+REG64_FLD( PU_PBAMODE_BCDE_OCITRANS                                , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BCDE_OCITRANS );
+REG64_FLD( PU_PBAMODE_BCDE_OCITRANS_LEN                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BCDE_OCITRANS_LEN );
+REG64_FLD( PU_PBAMODE_BCUE_OCITRANS                                , 23  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BCUE_OCITRANS );
+REG64_FLD( PU_PBAMODE_BCUE_OCITRANS_LEN                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BCUE_OCITRANS_LEN );
+REG64_FLD( PU_PBAMODE_DIS_MASTER_RD_PIPE                           , 25  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DIS_MASTER_RD_PIPE );
+REG64_FLD( PU_PBAMODE_DIS_MASTER_WR_PIPE                           , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DIS_MASTER_WR_PIPE );
+REG64_FLD( PU_PBAMODE_EN_SLV_FAIRNESS                              , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_EN_SLV_FAIRNESS );
+REG64_FLD( PU_PBAMODE_EN_EVENT_COUNT                               , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_EN_EVENT_COUNT );
+REG64_FLD( PU_PBAMODE_PB_NOCI_EVENT_SEL                            , 29  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PB_NOCI_EVENT_SEL );
+REG64_FLD( PU_PBAMODE_SLV_EVENT_MUX                                , 30  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SLV_EVENT_MUX );
+REG64_FLD( PU_PBAMODE_SLV_EVENT_MUX_LEN                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SLV_EVENT_MUX_LEN );
+REG64_FLD( PU_PBAMODE_ENABLE_DEBUG_BUS                             , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE_DEBUG_BUS );
+REG64_FLD( PU_PBAMODE_DEBUG_PB_NOT_OCI                             , 33  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DEBUG_PB_NOT_OCI );
+REG64_FLD( PU_PBAMODE_DEBUG_OCI_MODE                               , 34  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DEBUG_OCI_MODE );
+REG64_FLD( PU_PBAMODE_DEBUG_OCI_MODE_LEN                           , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DEBUG_OCI_MODE_LEN );
+REG64_FLD( PU_PBAMODE_RESERVED_39                                  , 39  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_39 );
+REG64_FLD( PU_PBAMODE_OCISLV_FAIRNESS_MASK                         , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OCISLV_FAIRNESS_MASK );
+REG64_FLD( PU_PBAMODE_OCISLV_FAIRNESS_MASK_LEN                     , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OCISLV_FAIRNESS_MASK_LEN );
+REG64_FLD( PU_PBAMODE_OCISLV_REREQ_HANG_DIV                        , 45  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OCISLV_REREQ_HANG_DIV );
+REG64_FLD( PU_PBAMODE_OCISLV_REREQ_HANG_DIV_LEN                    , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OCISLV_REREQ_HANG_DIV_LEN );
+REG64_FLD( PU_PBAMODE_DIS_CHGRATE_COUNT                            , 50  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DIS_CHGRATE_COUNT );
+REG64_FLD( PU_PBAMODE_PBREQ_EVENT_MUX                              , 51  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PBREQ_EVENT_MUX );
+REG64_FLD( PU_PBAMODE_PBREQ_EVENT_MUX_LEN                          , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PBREQ_EVENT_MUX_LEN );
+REG64_FLD( PU_PBAMODE_RESERVED_53_63                               , 53  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_53_63 );
+REG64_FLD( PU_PBAMODE_RESERVED_53_63_LEN                           , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_53_63_LEN );
+
+REG64_FLD( PU_PBAOCCACT_OCC_ACTION_SET                             , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_OCC_ACTION_SET );
+REG64_FLD( PU_PBAOCCACT_OCC_ACTION_SET_LEN                         , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_OCC_ACTION_SET_LEN );
+
+REG64_FLD( PU_PBAPBOCR0_EVENT                                      , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_EVENT      );
+REG64_FLD( PU_PBAPBOCR0_EVENT_LEN                                  , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_EVENT_LEN  );
+REG64_FLD( PU_PBAPBOCR0_ACCUM                                      , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ACCUM      );
+REG64_FLD( PU_PBAPBOCR0_ACCUM_LEN                                  , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ACCUM_LEN  );
+
+REG64_FLD( PU_PBAPBOCR1_EVENT                                      , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_EVENT      );
+REG64_FLD( PU_PBAPBOCR1_EVENT_LEN                                  , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_EVENT_LEN  );
+REG64_FLD( PU_PBAPBOCR1_ACCUM                                      , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ACCUM      );
+REG64_FLD( PU_PBAPBOCR1_ACCUM_LEN                                  , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ACCUM_LEN  );
+
+REG64_FLD( PU_PBAPBOCR2_EVENT                                      , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_EVENT      );
+REG64_FLD( PU_PBAPBOCR2_EVENT_LEN                                  , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_EVENT_LEN  );
+REG64_FLD( PU_PBAPBOCR2_ACCUM                                      , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ACCUM      );
+REG64_FLD( PU_PBAPBOCR2_ACCUM_LEN                                  , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ACCUM_LEN  );
+
+REG64_FLD( PU_PBAPBOCR3_EVENT                                      , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_EVENT      );
+REG64_FLD( PU_PBAPBOCR3_EVENT_LEN                                  , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_EVENT_LEN  );
+REG64_FLD( PU_PBAPBOCR3_ACCUM                                      , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ACCUM      );
+REG64_FLD( PU_PBAPBOCR3_ACCUM_LEN                                  , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ACCUM_LEN  );
+
+REG64_FLD( PU_PBAPBOCR4_EVENT                                      , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_EVENT      );
+REG64_FLD( PU_PBAPBOCR4_EVENT_LEN                                  , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_EVENT_LEN  );
+REG64_FLD( PU_PBAPBOCR4_ACCUM                                      , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ACCUM      );
+REG64_FLD( PU_PBAPBOCR4_ACCUM_LEN                                  , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ACCUM_LEN  );
+
+REG64_FLD( PU_PBAPBOCR5_EVENT                                      , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_EVENT      );
+REG64_FLD( PU_PBAPBOCR5_EVENT_LEN                                  , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_EVENT_LEN  );
+REG64_FLD( PU_PBAPBOCR5_ACCUM                                      , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ACCUM      );
+REG64_FLD( PU_PBAPBOCR5_ACCUM_LEN                                  , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ACCUM_LEN  );
+
+REG64_FLD( PU_PBARBUFVAL0_RD_SLVNUM                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RD_SLVNUM  );
+REG64_FLD( PU_PBARBUFVAL0_RD_SLVNUM_LEN                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RD_SLVNUM_LEN );
+REG64_FLD( PU_PBARBUFVAL0_CUR_RD_ADDR                              , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CUR_RD_ADDR );
+REG64_FLD( PU_PBARBUFVAL0_CUR_RD_ADDR_LEN                          , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CUR_RD_ADDR_LEN );
+REG64_FLD( PU_PBARBUFVAL0_PREFETCH                                 , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PREFETCH   );
+REG64_FLD( PU_PBARBUFVAL0_ABORT                                    , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ABORT      );
+REG64_FLD( PU_PBARBUFVAL0_BUFFER_STATUS                            , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_BUFFER_STATUS );
+REG64_FLD( PU_PBARBUFVAL0_BUFFER_STATUS_LEN                        , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_BUFFER_STATUS_LEN );
+REG64_FLD( PU_PBARBUFVAL0_MASTERID                                 , 41  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MASTERID   );
+REG64_FLD( PU_PBARBUFVAL0_MASTERID_LEN                             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MASTERID_LEN );
+
+REG64_FLD( PU_PBARBUFVAL1_RD_SLVNUM                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RD_SLVNUM  );
+REG64_FLD( PU_PBARBUFVAL1_RD_SLVNUM_LEN                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RD_SLVNUM_LEN );
+REG64_FLD( PU_PBARBUFVAL1_CUR_RD_ADDR                              , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CUR_RD_ADDR );
+REG64_FLD( PU_PBARBUFVAL1_CUR_RD_ADDR_LEN                          , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CUR_RD_ADDR_LEN );
+REG64_FLD( PU_PBARBUFVAL1_PREFETCH                                 , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PREFETCH   );
+REG64_FLD( PU_PBARBUFVAL1_ABORT                                    , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ABORT      );
+REG64_FLD( PU_PBARBUFVAL1_BUFFER_STATUS                            , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_BUFFER_STATUS );
+REG64_FLD( PU_PBARBUFVAL1_BUFFER_STATUS_LEN                        , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_BUFFER_STATUS_LEN );
+REG64_FLD( PU_PBARBUFVAL1_MASTERID                                 , 41  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MASTERID   );
+REG64_FLD( PU_PBARBUFVAL1_MASTERID_LEN                             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MASTERID_LEN );
+
+REG64_FLD( PU_PBARBUFVAL2_RD_SLVNUM                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RD_SLVNUM  );
+REG64_FLD( PU_PBARBUFVAL2_RD_SLVNUM_LEN                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RD_SLVNUM_LEN );
+REG64_FLD( PU_PBARBUFVAL2_CUR_RD_ADDR                              , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CUR_RD_ADDR );
+REG64_FLD( PU_PBARBUFVAL2_CUR_RD_ADDR_LEN                          , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CUR_RD_ADDR_LEN );
+REG64_FLD( PU_PBARBUFVAL2_PREFETCH                                 , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PREFETCH   );
+REG64_FLD( PU_PBARBUFVAL2_ABORT                                    , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ABORT      );
+REG64_FLD( PU_PBARBUFVAL2_BUFFER_STATUS                            , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_BUFFER_STATUS );
+REG64_FLD( PU_PBARBUFVAL2_BUFFER_STATUS_LEN                        , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_BUFFER_STATUS_LEN );
+REG64_FLD( PU_PBARBUFVAL2_MASTERID                                 , 41  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MASTERID   );
+REG64_FLD( PU_PBARBUFVAL2_MASTERID_LEN                             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MASTERID_LEN );
+
+REG64_FLD( PU_PBARBUFVAL3_RD_SLVNUM                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RD_SLVNUM  );
+REG64_FLD( PU_PBARBUFVAL3_RD_SLVNUM_LEN                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RD_SLVNUM_LEN );
+REG64_FLD( PU_PBARBUFVAL3_CUR_RD_ADDR                              , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CUR_RD_ADDR );
+REG64_FLD( PU_PBARBUFVAL3_CUR_RD_ADDR_LEN                          , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CUR_RD_ADDR_LEN );
+REG64_FLD( PU_PBARBUFVAL3_PREFETCH                                 , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PREFETCH   );
+REG64_FLD( PU_PBARBUFVAL3_ABORT                                    , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ABORT      );
+REG64_FLD( PU_PBARBUFVAL3_BUFFER_STATUS                            , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_BUFFER_STATUS );
+REG64_FLD( PU_PBARBUFVAL3_BUFFER_STATUS_LEN                        , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_BUFFER_STATUS_LEN );
+REG64_FLD( PU_PBARBUFVAL3_MASTERID                                 , 41  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MASTERID   );
+REG64_FLD( PU_PBARBUFVAL3_MASTERID_LEN                             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MASTERID_LEN );
+
+REG64_FLD( PU_PBARBUFVAL4_RD_SLVNUM                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RD_SLVNUM  );
+REG64_FLD( PU_PBARBUFVAL4_RD_SLVNUM_LEN                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RD_SLVNUM_LEN );
+REG64_FLD( PU_PBARBUFVAL4_CUR_RD_ADDR                              , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CUR_RD_ADDR );
+REG64_FLD( PU_PBARBUFVAL4_CUR_RD_ADDR_LEN                          , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CUR_RD_ADDR_LEN );
+REG64_FLD( PU_PBARBUFVAL4_PREFETCH                                 , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PREFETCH   );
+REG64_FLD( PU_PBARBUFVAL4_ABORT                                    , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ABORT      );
+REG64_FLD( PU_PBARBUFVAL4_BUFFER_STATUS                            , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_BUFFER_STATUS );
+REG64_FLD( PU_PBARBUFVAL4_BUFFER_STATUS_LEN                        , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_BUFFER_STATUS_LEN );
+REG64_FLD( PU_PBARBUFVAL4_MASTERID                                 , 41  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MASTERID   );
+REG64_FLD( PU_PBARBUFVAL4_MASTERID_LEN                             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MASTERID_LEN );
+
+REG64_FLD( PU_PBARBUFVAL5_RD_SLVNUM                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RD_SLVNUM  );
+REG64_FLD( PU_PBARBUFVAL5_RD_SLVNUM_LEN                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RD_SLVNUM_LEN );
+REG64_FLD( PU_PBARBUFVAL5_CUR_RD_ADDR                              , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CUR_RD_ADDR );
+REG64_FLD( PU_PBARBUFVAL5_CUR_RD_ADDR_LEN                          , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CUR_RD_ADDR_LEN );
+REG64_FLD( PU_PBARBUFVAL5_PREFETCH                                 , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PREFETCH   );
+REG64_FLD( PU_PBARBUFVAL5_ABORT                                    , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ABORT      );
+REG64_FLD( PU_PBARBUFVAL5_BUFFER_STATUS                            , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_BUFFER_STATUS );
+REG64_FLD( PU_PBARBUFVAL5_BUFFER_STATUS_LEN                        , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_BUFFER_STATUS_LEN );
+REG64_FLD( PU_PBARBUFVAL5_MASTERID                                 , 41  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MASTERID   );
+REG64_FLD( PU_PBARBUFVAL5_MASTERID_LEN                             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_MASTERID_LEN );
+
+REG64_FLD( PU_PBASLVCTL0_ENABLE                                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE     );
+REG64_FLD( PU_PBASLVCTL0_MID_MATCH_VALUE                           , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MID_MATCH_VALUE );
+REG64_FLD( PU_PBASLVCTL0_MID_MATCH_VALUE_LEN                       , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MID_MATCH_VALUE_LEN );
+REG64_FLD( PU_PBASLVCTL0_RESERVED_4                                , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_4 );
+REG64_FLD( PU_PBASLVCTL0_MID_CARE_MASK                             , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MID_CARE_MASK );
+REG64_FLD( PU_PBASLVCTL0_MID_CARE_MASK_LEN                         , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MID_CARE_MASK_LEN );
+REG64_FLD( PU_PBASLVCTL0_WRITE_TTYPE                               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRITE_TTYPE );
+REG64_FLD( PU_PBASLVCTL0_WRITE_TTYPE_LEN                           , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRITE_TTYPE_LEN );
+REG64_FLD( PU_PBASLVCTL0_RESERVED_11_14                            , 11  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_11_14 );
+REG64_FLD( PU_PBASLVCTL0_RESERVED_11_14_LEN                        , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_11_14_LEN );
+REG64_FLD( PU_PBASLVCTL0_READ_TTYPE                                , 15  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_READ_TTYPE );
+REG64_FLD( PU_PBASLVCTL0_READ_PREFETCH_CTL                         , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_READ_PREFETCH_CTL );
+REG64_FLD( PU_PBASLVCTL0_READ_PREFETCH_CTL_LEN                     , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_READ_PREFETCH_CTL_LEN );
+REG64_FLD( PU_PBASLVCTL0_BUF_INVALIDATE_CTL                        , 18  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BUF_INVALIDATE_CTL );
+REG64_FLD( PU_PBASLVCTL0_BUF_ALLOC_W                               , 19  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BUF_ALLOC_W );
+REG64_FLD( PU_PBASLVCTL0_BUF_ALLOC_A                               , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BUF_ALLOC_A );
+REG64_FLD( PU_PBASLVCTL0_BUF_ALLOC_B                               , 21  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BUF_ALLOC_B );
+REG64_FLD( PU_PBASLVCTL0_BUF_ALLOC_C                               , 22  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BUF_ALLOC_C );
+REG64_FLD( PU_PBASLVCTL0_RESERVED_23                               , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_23 );
+REG64_FLD( PU_PBASLVCTL0_DIS_WRITE_GATHER                          , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_WRITE_GATHER );
+REG64_FLD( PU_PBASLVCTL0_WR_GATHER_TIMEOUT                         , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WR_GATHER_TIMEOUT );
+REG64_FLD( PU_PBASLVCTL0_WR_GATHER_TIMEOUT_LEN                     , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WR_GATHER_TIMEOUT_LEN );
+REG64_FLD( PU_PBASLVCTL0_WRITE_TSIZE                               , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRITE_TSIZE );
+REG64_FLD( PU_PBASLVCTL0_WRITE_TSIZE_LEN                           , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRITE_TSIZE_LEN );
+REG64_FLD( PU_PBASLVCTL0_EXTADDR                                   , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EXTADDR    );
+REG64_FLD( PU_PBASLVCTL0_EXTADDR_LEN                               , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EXTADDR_LEN );
+REG64_FLD( PU_PBASLVCTL0_RESERVED_50                               , 50  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_50 );
+
+REG64_FLD( PU_PBASLVCTL1_ENABLE                                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE     );
+REG64_FLD( PU_PBASLVCTL1_MID_MATCH_VALUE                           , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MID_MATCH_VALUE );
+REG64_FLD( PU_PBASLVCTL1_MID_MATCH_VALUE_LEN                       , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MID_MATCH_VALUE_LEN );
+REG64_FLD( PU_PBASLVCTL1_RESERVED_4                                , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_4 );
+REG64_FLD( PU_PBASLVCTL1_MID_CARE_MASK                             , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MID_CARE_MASK );
+REG64_FLD( PU_PBASLVCTL1_MID_CARE_MASK_LEN                         , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MID_CARE_MASK_LEN );
+REG64_FLD( PU_PBASLVCTL1_WRITE_TTYPE                               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRITE_TTYPE );
+REG64_FLD( PU_PBASLVCTL1_WRITE_TTYPE_LEN                           , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRITE_TTYPE_LEN );
+REG64_FLD( PU_PBASLVCTL1_RESERVED_11_14                            , 11  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_11_14 );
+REG64_FLD( PU_PBASLVCTL1_RESERVED_11_14_LEN                        , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_11_14_LEN );
+REG64_FLD( PU_PBASLVCTL1_READ_TTYPE                                , 15  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_READ_TTYPE );
+REG64_FLD( PU_PBASLVCTL1_READ_PREFETCH_CTL                         , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_READ_PREFETCH_CTL );
+REG64_FLD( PU_PBASLVCTL1_READ_PREFETCH_CTL_LEN                     , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_READ_PREFETCH_CTL_LEN );
+REG64_FLD( PU_PBASLVCTL1_BUF_INVALIDATE_CTL                        , 18  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BUF_INVALIDATE_CTL );
+REG64_FLD( PU_PBASLVCTL1_BUF_ALLOC_W                               , 19  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BUF_ALLOC_W );
+REG64_FLD( PU_PBASLVCTL1_BUF_ALLOC_A                               , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BUF_ALLOC_A );
+REG64_FLD( PU_PBASLVCTL1_BUF_ALLOC_B                               , 21  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BUF_ALLOC_B );
+REG64_FLD( PU_PBASLVCTL1_BUF_ALLOC_C                               , 22  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BUF_ALLOC_C );
+REG64_FLD( PU_PBASLVCTL1_RESERVED_23                               , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_23 );
+REG64_FLD( PU_PBASLVCTL1_DIS_WRITE_GATHER                          , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_WRITE_GATHER );
+REG64_FLD( PU_PBASLVCTL1_WR_GATHER_TIMEOUT                         , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WR_GATHER_TIMEOUT );
+REG64_FLD( PU_PBASLVCTL1_WR_GATHER_TIMEOUT_LEN                     , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WR_GATHER_TIMEOUT_LEN );
+REG64_FLD( PU_PBASLVCTL1_WRITE_TSIZE                               , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRITE_TSIZE );
+REG64_FLD( PU_PBASLVCTL1_WRITE_TSIZE_LEN                           , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRITE_TSIZE_LEN );
+REG64_FLD( PU_PBASLVCTL1_EXTADDR                                   , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EXTADDR    );
+REG64_FLD( PU_PBASLVCTL1_EXTADDR_LEN                               , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EXTADDR_LEN );
+REG64_FLD( PU_PBASLVCTL1_RESERVED_50                               , 50  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_50 );
+
+REG64_FLD( PU_PBASLVCTL2_ENABLE                                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE     );
+REG64_FLD( PU_PBASLVCTL2_MID_MATCH_VALUE                           , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MID_MATCH_VALUE );
+REG64_FLD( PU_PBASLVCTL2_MID_MATCH_VALUE_LEN                       , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MID_MATCH_VALUE_LEN );
+REG64_FLD( PU_PBASLVCTL2_RESERVED_4                                , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_4 );
+REG64_FLD( PU_PBASLVCTL2_MID_CARE_MASK                             , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MID_CARE_MASK );
+REG64_FLD( PU_PBASLVCTL2_MID_CARE_MASK_LEN                         , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MID_CARE_MASK_LEN );
+REG64_FLD( PU_PBASLVCTL2_WRITE_TTYPE                               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRITE_TTYPE );
+REG64_FLD( PU_PBASLVCTL2_WRITE_TTYPE_LEN                           , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRITE_TTYPE_LEN );
+REG64_FLD( PU_PBASLVCTL2_RESERVED_11_14                            , 11  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_11_14 );
+REG64_FLD( PU_PBASLVCTL2_RESERVED_11_14_LEN                        , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_11_14_LEN );
+REG64_FLD( PU_PBASLVCTL2_READ_TTYPE                                , 15  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_READ_TTYPE );
+REG64_FLD( PU_PBASLVCTL2_READ_PREFETCH_CTL                         , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_READ_PREFETCH_CTL );
+REG64_FLD( PU_PBASLVCTL2_READ_PREFETCH_CTL_LEN                     , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_READ_PREFETCH_CTL_LEN );
+REG64_FLD( PU_PBASLVCTL2_BUF_INVALIDATE_CTL                        , 18  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BUF_INVALIDATE_CTL );
+REG64_FLD( PU_PBASLVCTL2_BUF_ALLOC_W                               , 19  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BUF_ALLOC_W );
+REG64_FLD( PU_PBASLVCTL2_BUF_ALLOC_A                               , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BUF_ALLOC_A );
+REG64_FLD( PU_PBASLVCTL2_BUF_ALLOC_B                               , 21  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BUF_ALLOC_B );
+REG64_FLD( PU_PBASLVCTL2_BUF_ALLOC_C                               , 22  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BUF_ALLOC_C );
+REG64_FLD( PU_PBASLVCTL2_RESERVED_23                               , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_23 );
+REG64_FLD( PU_PBASLVCTL2_DIS_WRITE_GATHER                          , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_WRITE_GATHER );
+REG64_FLD( PU_PBASLVCTL2_WR_GATHER_TIMEOUT                         , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WR_GATHER_TIMEOUT );
+REG64_FLD( PU_PBASLVCTL2_WR_GATHER_TIMEOUT_LEN                     , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WR_GATHER_TIMEOUT_LEN );
+REG64_FLD( PU_PBASLVCTL2_WRITE_TSIZE                               , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRITE_TSIZE );
+REG64_FLD( PU_PBASLVCTL2_WRITE_TSIZE_LEN                           , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRITE_TSIZE_LEN );
+REG64_FLD( PU_PBASLVCTL2_EXTADDR                                   , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EXTADDR    );
+REG64_FLD( PU_PBASLVCTL2_EXTADDR_LEN                               , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EXTADDR_LEN );
+REG64_FLD( PU_PBASLVCTL2_RESERVED_50                               , 50  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_50 );
+
+REG64_FLD( PU_PBASLVCTL3_ENABLE                                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE     );
+REG64_FLD( PU_PBASLVCTL3_MID_MATCH_VALUE                           , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MID_MATCH_VALUE );
+REG64_FLD( PU_PBASLVCTL3_MID_MATCH_VALUE_LEN                       , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MID_MATCH_VALUE_LEN );
+REG64_FLD( PU_PBASLVCTL3_RESERVED_4                                , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_4 );
+REG64_FLD( PU_PBASLVCTL3_MID_CARE_MASK                             , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MID_CARE_MASK );
+REG64_FLD( PU_PBASLVCTL3_MID_CARE_MASK_LEN                         , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MID_CARE_MASK_LEN );
+REG64_FLD( PU_PBASLVCTL3_WRITE_TTYPE                               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRITE_TTYPE );
+REG64_FLD( PU_PBASLVCTL3_WRITE_TTYPE_LEN                           , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRITE_TTYPE_LEN );
+REG64_FLD( PU_PBASLVCTL3_RESERVED_11_14                            , 11  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_11_14 );
+REG64_FLD( PU_PBASLVCTL3_RESERVED_11_14_LEN                        , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_11_14_LEN );
+REG64_FLD( PU_PBASLVCTL3_READ_TTYPE                                , 15  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_READ_TTYPE );
+REG64_FLD( PU_PBASLVCTL3_READ_PREFETCH_CTL                         , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_READ_PREFETCH_CTL );
+REG64_FLD( PU_PBASLVCTL3_READ_PREFETCH_CTL_LEN                     , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_READ_PREFETCH_CTL_LEN );
+REG64_FLD( PU_PBASLVCTL3_BUF_INVALIDATE_CTL                        , 18  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BUF_INVALIDATE_CTL );
+REG64_FLD( PU_PBASLVCTL3_BUF_ALLOC_W                               , 19  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BUF_ALLOC_W );
+REG64_FLD( PU_PBASLVCTL3_BUF_ALLOC_A                               , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BUF_ALLOC_A );
+REG64_FLD( PU_PBASLVCTL3_BUF_ALLOC_B                               , 21  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BUF_ALLOC_B );
+REG64_FLD( PU_PBASLVCTL3_BUF_ALLOC_C                               , 22  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BUF_ALLOC_C );
+REG64_FLD( PU_PBASLVCTL3_RESERVED_23                               , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_23 );
+REG64_FLD( PU_PBASLVCTL3_DIS_WRITE_GATHER                          , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIS_WRITE_GATHER );
+REG64_FLD( PU_PBASLVCTL3_WR_GATHER_TIMEOUT                         , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WR_GATHER_TIMEOUT );
+REG64_FLD( PU_PBASLVCTL3_WR_GATHER_TIMEOUT_LEN                     , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WR_GATHER_TIMEOUT_LEN );
+REG64_FLD( PU_PBASLVCTL3_WRITE_TSIZE                               , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRITE_TSIZE );
+REG64_FLD( PU_PBASLVCTL3_WRITE_TSIZE_LEN                           , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRITE_TSIZE_LEN );
+REG64_FLD( PU_PBASLVCTL3_EXTADDR                                   , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EXTADDR    );
+REG64_FLD( PU_PBASLVCTL3_EXTADDR_LEN                               , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EXTADDR_LEN );
+REG64_FLD( PU_PBASLVCTL3_RESERVED_50                               , 50  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_50 );
+
+REG64_FLD( PU_PBASLVRST_SET                                        , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SET        );
+REG64_FLD( PU_PBASLVRST_SET_LEN                                    , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SET_LEN    );
+REG64_FLD( PU_PBASLVRST_IN_PROG                                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IN_PROG    );
+REG64_FLD( PU_PBASLVRST_IN_PROG_LEN                                , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IN_PROG_LEN );
+REG64_FLD( PU_PBASLVRST_BUSY_STATUS                                , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUSY_STATUS );
+REG64_FLD( PU_PBASLVRST_BUSY_STATUS_LEN                            , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUSY_STATUS_LEN );
+REG64_FLD( PU_PBASLVRST_SCOPE_ATTN_BAR                             , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SCOPE_ATTN_BAR );
+REG64_FLD( PU_PBASLVRST_SCOPE_ATTN_BAR_LEN                         , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SCOPE_ATTN_BAR_LEN );
+
+REG64_FLD( PU_PBAWBUFVAL0_WR_SLVNUM                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WR_SLVNUM  );
+REG64_FLD( PU_PBAWBUFVAL0_WR_SLVNUM_LEN                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WR_SLVNUM_LEN );
+REG64_FLD( PU_PBAWBUFVAL0_START_WR_ADDR                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_START_WR_ADDR );
+REG64_FLD( PU_PBAWBUFVAL0_START_WR_ADDR_LEN                        , 30  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_START_WR_ADDR_LEN );
+REG64_FLD( PU_PBAWBUFVAL0_WR_BUFFER_STATUS                         , 35  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WR_BUFFER_STATUS );
+REG64_FLD( PU_PBAWBUFVAL0_WR_BUFFER_STATUS_LEN                     , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WR_BUFFER_STATUS_LEN );
+REG64_FLD( PU_PBAWBUFVAL0_WR_BYTE_COUNT                            , 41  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WR_BYTE_COUNT );
+REG64_FLD( PU_PBAWBUFVAL0_WR_BYTE_COUNT_LEN                        , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WR_BYTE_COUNT_LEN );
+
+REG64_FLD( PU_PBAWBUFVAL1_WR_SLVNUM                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WR_SLVNUM  );
+REG64_FLD( PU_PBAWBUFVAL1_WR_SLVNUM_LEN                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WR_SLVNUM_LEN );
+REG64_FLD( PU_PBAWBUFVAL1_START_WR_ADDR                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_START_WR_ADDR );
+REG64_FLD( PU_PBAWBUFVAL1_START_WR_ADDR_LEN                        , 30  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_START_WR_ADDR_LEN );
+REG64_FLD( PU_PBAWBUFVAL1_WR_BUFFER_STATUS                         , 35  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WR_BUFFER_STATUS );
+REG64_FLD( PU_PBAWBUFVAL1_WR_BUFFER_STATUS_LEN                     , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WR_BUFFER_STATUS_LEN );
+REG64_FLD( PU_PBAWBUFVAL1_WR_BYTE_COUNT                            , 41  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WR_BYTE_COUNT );
+REG64_FLD( PU_PBAWBUFVAL1_WR_BYTE_COUNT_LEN                        , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WR_BYTE_COUNT_LEN );
+
+REG64_FLD( PU_PBAXCFG_PBAX_EN                                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PBAX_EN    );
+REG64_FLD( PU_PBAXCFG_RESERVATION_EN                               , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVATION_EN );
+REG64_FLD( PU_PBAXCFG_SND_RESET                                    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SND_RESET  );
+REG64_FLD( PU_PBAXCFG_RCV_RESET                                    , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RCV_RESET  );
+REG64_FLD( PU_PBAXCFG_RCV_GROUPID                                  , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RCV_GROUPID );
+REG64_FLD( PU_PBAXCFG_RCV_GROUPID_LEN                              , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RCV_GROUPID_LEN );
+REG64_FLD( PU_PBAXCFG_RCV_CHIPID                                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RCV_CHIPID );
+REG64_FLD( PU_PBAXCFG_RCV_CHIPID_LEN                               , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RCV_CHIPID_LEN );
+REG64_FLD( PU_PBAXCFG_RESERVED_11                                  , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_11 );
+REG64_FLD( PU_PBAXCFG_RCV_BRDCST_GROUP                             , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RCV_BRDCST_GROUP );
+REG64_FLD( PU_PBAXCFG_RCV_BRDCST_GROUP_LEN                         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RCV_BRDCST_GROUP_LEN );
+REG64_FLD( PU_PBAXCFG_RCV_DATATO_DIV                               , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RCV_DATATO_DIV );
+REG64_FLD( PU_PBAXCFG_RCV_DATATO_DIV_LEN                           , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RCV_DATATO_DIV_LEN );
+REG64_FLD( PU_PBAXCFG_RESERVED_25_26                               , 25  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_25_26 );
+REG64_FLD( PU_PBAXCFG_RESERVED_25_26_LEN                           , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_25_26_LEN );
+REG64_FLD( PU_PBAXCFG_SND_RETRY_COUNT_OVERCOM                      , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SND_RETRY_COUNT_OVERCOM );
+REG64_FLD( PU_PBAXCFG_SND_RETRY_THRESH                             , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SND_RETRY_THRESH );
+REG64_FLD( PU_PBAXCFG_SND_RETRY_THRESH_LEN                         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SND_RETRY_THRESH_LEN );
+REG64_FLD( PU_PBAXCFG_SND_RSVTO_DIV                                , 36  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SND_RSVTO_DIV );
+REG64_FLD( PU_PBAXCFG_SND_RSVTO_DIV_LEN                            , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SND_RSVTO_DIV_LEN );
+
+REG64_FLD( PU_PBAXRCVSTAT_RCV_IN_PROGRESS                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RCV_IN_PROGRESS );
+REG64_FLD( PU_PBAXRCVSTAT_RCV_ERROR                                , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RCV_ERROR  );
+REG64_FLD( PU_PBAXRCVSTAT_RCV_WRITE_IN_PROGRESS                    , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RCV_WRITE_IN_PROGRESS );
+REG64_FLD( PU_PBAXRCVSTAT_RCV_RESERVATION_SET                      , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RCV_RESERVATION_SET );
+REG64_FLD( PU_PBAXRCVSTAT_RCV_CAPTURE                              , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RCV_CAPTURE );
+REG64_FLD( PU_PBAXRCVSTAT_RCV_CAPTURE_LEN                          , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RCV_CAPTURE_LEN );
+
+REG64_FLD( PU_PBAXSHBR0_PUSH_START                                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PUSH_START );
+REG64_FLD( PU_PBAXSHBR0_PUSH_START_LEN                             , 29  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PUSH_START_LEN );
+
+REG64_FLD( PU_PBAXSHBR1_PUSH_START                                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PUSH_START );
+REG64_FLD( PU_PBAXSHBR1_PUSH_START_LEN                             , 29  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PUSH_START_LEN );
+
+REG64_FLD( PU_PBAXSHCS0_PUSH_FULL                                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PUSH_FULL  );
+REG64_FLD( PU_PBAXSHCS0_PUSH_EMPTY                                 , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PUSH_EMPTY );
+REG64_FLD( PU_PBAXSHCS0_RESERVED_2_3                               , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_2_3 );
+REG64_FLD( PU_PBAXSHCS0_RESERVED_2_3_LEN                           , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_2_3_LEN );
+REG64_FLD( PU_PBAXSHCS0_PUSH_INTR_ACTION_0_1                       , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PUSH_INTR_ACTION_0_1 );
+REG64_FLD( PU_PBAXSHCS0_PUSH_INTR_ACTION_0_1_LEN                   , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PUSH_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_PBAXSHCS0_PUSH_LENGTH                                , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PUSH_LENGTH );
+REG64_FLD( PU_PBAXSHCS0_PUSH_LENGTH_LEN                            , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PUSH_LENGTH_LEN );
+REG64_FLD( PU_PBAXSHCS0_PUSH_WRITE_PTR                             , 13  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PUSH_WRITE_PTR );
+REG64_FLD( PU_PBAXSHCS0_PUSH_WRITE_PTR_LEN                         , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PUSH_WRITE_PTR_LEN );
+REG64_FLD( PU_PBAXSHCS0_PUSH_READ_PTR                              , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PUSH_READ_PTR );
+REG64_FLD( PU_PBAXSHCS0_PUSH_READ_PTR_LEN                          , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PUSH_READ_PTR_LEN );
+REG64_FLD( PU_PBAXSHCS0_PUSH_ENABLE                                , 31  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PUSH_ENABLE );
+
+REG64_FLD( PU_PBAXSHCS1_PUSH_FULL                                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PUSH_FULL  );
+REG64_FLD( PU_PBAXSHCS1_PUSH_EMPTY                                 , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PUSH_EMPTY );
+REG64_FLD( PU_PBAXSHCS1_RESERVED_2_3                               , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_2_3 );
+REG64_FLD( PU_PBAXSHCS1_RESERVED_2_3_LEN                           , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_2_3_LEN );
+REG64_FLD( PU_PBAXSHCS1_PUSH_INTR_ACTION_0_1                       , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PUSH_INTR_ACTION_0_1 );
+REG64_FLD( PU_PBAXSHCS1_PUSH_INTR_ACTION_0_1_LEN                   , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PUSH_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_PBAXSHCS1_PUSH_LENGTH                                , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PUSH_LENGTH );
+REG64_FLD( PU_PBAXSHCS1_PUSH_LENGTH_LEN                            , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PUSH_LENGTH_LEN );
+REG64_FLD( PU_PBAXSHCS1_PUSH_WRITE_PTR                             , 13  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PUSH_WRITE_PTR );
+REG64_FLD( PU_PBAXSHCS1_PUSH_WRITE_PTR_LEN                         , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PUSH_WRITE_PTR_LEN );
+REG64_FLD( PU_PBAXSHCS1_PUSH_READ_PTR                              , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PUSH_READ_PTR );
+REG64_FLD( PU_PBAXSHCS1_PUSH_READ_PTR_LEN                          , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PUSH_READ_PTR_LEN );
+REG64_FLD( PU_PBAXSHCS1_PUSH_ENABLE                                , 31  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PUSH_ENABLE );
+
+REG64_FLD( PU_PBAXSNDSTAT_SND_IN_PROGRESS                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SND_IN_PROGRESS );
+REG64_FLD( PU_PBAXSNDSTAT_SND_ERROR                                , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SND_ERROR  );
+REG64_FLD( PU_PBAXSNDSTAT_SND_PHASE_STATUS                         , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SND_PHASE_STATUS );
+REG64_FLD( PU_PBAXSNDSTAT_SND_PHASE_STATUS_LEN                     , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SND_PHASE_STATUS_LEN );
+REG64_FLD( PU_PBAXSNDSTAT_SND_CNT_STATUS                           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SND_CNT_STATUS );
+REG64_FLD( PU_PBAXSNDSTAT_SND_CNT_STATUS_LEN                       , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SND_CNT_STATUS_LEN );
+REG64_FLD( PU_PBAXSNDSTAT_SND_RETRY_COUNT                          , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SND_RETRY_COUNT );
+REG64_FLD( PU_PBAXSNDSTAT_SND_RETRY_COUNT_LEN                      , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SND_RETRY_COUNT_LEN );
+
+REG64_FLD( PU_PBAXSNDTX_SND_SCOPE                                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SND_SCOPE  );
+REG64_FLD( PU_PBAXSNDTX_SND_SCOPE_LEN                              , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SND_SCOPE_LEN );
+REG64_FLD( PU_PBAXSNDTX_SND_QID                                    , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SND_QID    );
+REG64_FLD( PU_PBAXSNDTX_SND_TYPE                                   , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SND_TYPE   );
+REG64_FLD( PU_PBAXSNDTX_SND_RESERVATION                            , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SND_RESERVATION );
+REG64_FLD( PU_PBAXSNDTX_RESERVED_6_7                               , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_6_7 );
+REG64_FLD( PU_PBAXSNDTX_RESERVED_6_7_LEN                           , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_6_7_LEN );
+REG64_FLD( PU_PBAXSNDTX_SND_GROUPID                                , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SND_GROUPID );
+REG64_FLD( PU_PBAXSNDTX_SND_GROUPID_LEN                            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SND_GROUPID_LEN );
+REG64_FLD( PU_PBAXSNDTX_SND_CHIPID                                 , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SND_CHIPID );
+REG64_FLD( PU_PBAXSNDTX_SND_CHIPID_LEN                             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SND_CHIPID_LEN );
+REG64_FLD( PU_PBAXSNDTX_RESERVED_15                                , 15  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RESERVED_15 );
+REG64_FLD( PU_PBAXSNDTX_VG_TARGE                                   , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VG_TARGE   );
+REG64_FLD( PU_PBAXSNDTX_VG_TARGE_LEN                               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_VG_TARGE_LEN );
+REG64_FLD( PU_PBAXSNDTX_SND_STOP                                   , 59  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SND_STOP   );
+REG64_FLD( PU_PBAXSNDTX_SND_CNT                                    , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SND_CNT    );
+REG64_FLD( PU_PBAXSNDTX_SND_CNT_LEN                                , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SND_CNT_LEN );
+
+REG64_FLD( PEC_PBCQEINJ_REG_PE_ECC_INJECT_TYPE                     , 0   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_ECC_INJECT_TYPE );
+REG64_FLD( PEC_PBCQEINJ_REG_PE_ECC_INJECT_TYPE_LEN                 , 2   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_ECC_INJECT_TYPE_LEN );
+REG64_FLD( PEC_PBCQEINJ_REG_PE_CQ_ECC_INJECT_ENABLE                , 2   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_CQ_ECC_INJECT_ENABLE );
+REG64_FLD( PEC_PBCQEINJ_REG_PE_CQ_SRAM_ARRAY                       , 3   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_CQ_SRAM_ARRAY );
+REG64_FLD( PEC_PBCQEINJ_REG_PE_CQ_SRAM_ARRAY_LEN                   , 4   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_CQ_SRAM_ARRAY_LEN );
+REG64_FLD( PEC_PBCQEINJ_REG_PE_CQ_PAR_INJECT_ENABLE                , 7   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_CQ_PAR_INJECT_ENABLE );
+REG64_FLD( PEC_PBCQEINJ_REG_PE_CQ_REGISTER_ARRAY                   , 8   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_CQ_REGISTER_ARRAY );
+REG64_FLD( PEC_PBCQEINJ_REG_PE_CQ_REGISTER_ARRAY_LEN               , 3   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_CQ_REGISTER_ARRAY_LEN );
+REG64_FLD( PEC_PBCQEINJ_REG_PE_EINJ_STACK                          , 11  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_EINJ_STACK );
+REG64_FLD( PEC_PBCQEINJ_REG_PE_EINJ_STACK_LEN                      , 2   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_EINJ_STACK_LEN );
+
+REG64_FLD( PEC_PBCQHWCFG_REG_HANG_POLL_SCALE                       , 0   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_HANG_POLL_SCALE );
+REG64_FLD( PEC_PBCQHWCFG_REG_HANG_POLL_SCALE_LEN                   , 4   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_HANG_POLL_SCALE_LEN );
+REG64_FLD( PEC_PBCQHWCFG_REG_HANG_DATA_SCALE                       , 4   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_HANG_DATA_SCALE );
+REG64_FLD( PEC_PBCQHWCFG_REG_HANG_DATA_SCALE_LEN                   , 4   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_HANG_DATA_SCALE_LEN );
+REG64_FLD( PEC_PBCQHWCFG_REG_HANG_PE_SCALE                         , 8   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_HANG_PE_SCALE );
+REG64_FLD( PEC_PBCQHWCFG_REG_HANG_PE_SCALE_LEN                     , 4   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_HANG_PE_SCALE_LEN );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_BLOCK_CQPB_PB_INIT                 , 12  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_BLOCK_CQPB_PB_INIT );
+REG64_FLD( PEC_PBCQHWCFG_REG_DISABLE_RCMD_CLKGATE                  , 13  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_DISABLE_RCMD_CLKGATE );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_HANG_SM_ON_ARE                     , 14  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_HANG_SM_ON_ARE );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_PCI_CLK_CHECK              , 15  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DISABLE_PCI_CLK_CHECK );
+REG64_FLD( PEC_PBCQHWCFG_REG_LFSR_ARB_MODE                         , 16  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_LFSR_ARB_MODE );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_ENABLE_DMAR_IOPACING               , 17  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_ENABLE_DMAR_IOPACING );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_ENABLE_DMAW_IOPACING               , 18  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_ENABLE_DMAW_IOPACING );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_ADR_BAR_MODE                       , 19  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_ADR_BAR_MODE );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_STQ_ALLOCATION                     , 20  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_STQ_ALLOCATION );
+REG64_FLD( PEC_PBCQHWCFG_REG_DISABLE_LPC_CMDS                      , 21  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_DISABLE_LPC_CMDS );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_OOO_MODE                   , 22  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DISABLE_OOO_MODE );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_OSMB_EARLY_START                   , 23  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_OSMB_EARLY_START );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_OSMB_EARLY_START_LEN               , 4   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_OSMB_EARLY_START_LEN );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_QFIFO_HOLD_MODE                    , 27  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_QFIFO_HOLD_MODE );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_QFIFO_HOLD_MODE_LEN                , 2   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_QFIFO_HOLD_MODE_LEN );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_WR_STRICT_ORDER_MODE               , 32  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_WR_STRICT_ORDER_MODE );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_CHANNEL_STREAMING_EN               , 33  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_CHANNEL_STREAMING_EN );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_WR_CACHE_INJECT_MODE               , 34  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_WR_CACHE_INJECT_MODE );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_WR_CACHE_INJECT_MODE_LEN           , 2   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_WR_CACHE_INJECT_MODE_LEN );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_ENABLE_NEW_FLOW_CACHE_INJECT       , 36  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_ENABLE_NEW_FLOW_CACHE_INJECT );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_INJ_ON_RESEND              , 37  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DISABLE_INJ_ON_RESEND );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_FORCE_DISABLED_CTAG_TO_FOLLOW_FLOW , 38  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_FORCE_DISABLED_CTAG_TO_FOLLOW_FLOW );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_ENABLE_ENH_FLOW                    , 39  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_ENABLE_ENH_FLOW );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_WR_VG                      , 41  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DISABLE_WR_VG );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_WR_SCOPE_GROUP             , 42  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DISABLE_WR_SCOPE_GROUP );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_INTWR_VG                   , 43  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DISABLE_INTWR_VG );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_INTWR_SCOPE_GROUP          , 44  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DISABLE_INTWR_SCOPE_GROUP );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_INTWR_SCOPE_NODE           , 45  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DISABLE_INTWR_SCOPE_NODE );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_RD_WRITE_ORDERING                  , 48  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_RD_WRITE_ORDERING );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_RD_WRITE_ORDERING_LEN              , 2   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_RD_WRITE_ORDERING_LEN );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_RD_SCOPE_NODAL             , 50  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DISABLE_RD_SCOPE_NODAL );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_RD_SCOPE_GROUP             , 51  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DISABLE_RD_SCOPE_GROUP );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_RD_SCOPE_RNNN              , 52  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DISABLE_RD_SCOPE_RNNN );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_ENABLE_RD_SKIP_GROUP               , 53  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_ENABLE_RD_SKIP_GROUP );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_RD_VG                      , 54  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DISABLE_RD_VG );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_SCOPE_NODAL            , 55  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DISABLE_TCE_SCOPE_NODAL );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_SCOPE_GROUP            , 56  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DISABLE_TCE_SCOPE_GROUP );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_SCOPE_RNNN             , 57  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DISABLE_TCE_SCOPE_RNNN );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_ENABLE_TCE_SKIP_GROUP              , 58  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_ENABLE_TCE_SKIP_GROUP );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_VG                     , 59  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DISABLE_TCE_VG );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_ARBITRATION            , 60  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DISABLE_TCE_ARBITRATION );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_CQ_TCE_ARBITRATION         , 61  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DISABLE_CQ_TCE_ARBITRATION );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_MC_PREFETCH                , 62  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_DISABLE_MC_PREFETCH );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_IGNORE_SFSTAT                      , 63  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_IGNORE_SFSTAT );
+
+REG64_FLD( PEC_STACK2_PBCQMODE_REG_PE_PEER2PEER_MODDE              , 0   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  , SH_FLD_PE_PEER2PEER_MODDE );
+REG64_FLD( PEC_STACK2_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE     , 1   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  , SH_FLD_PE_ENHANCED_PEER2PEER_MODDE );
+
+REG64_FLD( PEC_STACK1_PBCQMODE_REG_PE_PEER2PEER_MODDE              , 0   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  , SH_FLD_PE_PEER2PEER_MODDE );
+REG64_FLD( PEC_STACK1_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE     , 1   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  , SH_FLD_PE_ENHANCED_PEER2PEER_MODDE );
+
+REG64_FLD( PEC_STACK0_PBCQMODE_REG_PE_PEER2PEER_MODDE              , 0   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  , SH_FLD_PE_PEER2PEER_MODDE );
+REG64_FLD( PEC_STACK0_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE     , 1   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  , SH_FLD_PE_ENHANCED_PEER2PEER_MODDE );
+
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_VALID                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_VALID   );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_WR_NOT_RD                     , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_WR_NOT_RD );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_BAD_ADDR                      , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_BAD_ADDR );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_LINK_DOWN                     , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_LINK_DOWN );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_CORRUPT                       , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_CORRUPT );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_SENT                          , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_SENT    );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_BAD_WRITE                     , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_BAD_WRITE );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_RESET                         , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_RESET   );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_ID                               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ID         );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_LINK_ID                       , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_LINK_ID );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_LINK_ID_LEN                   , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_LINK_ID_LEN );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_SPARE                         , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_SPARE   );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_SPARE_LEN                     , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_SPARE_LEN );
+
+REG64_FLD( PU_PBO_MAILBOX_CTL_REG_MB_VALID                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_VALID   );
+REG64_FLD( PU_PBO_MAILBOX_CTL_REG_MB_WR_NOT_RD                     , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_WR_NOT_RD );
+REG64_FLD( PU_PBO_MAILBOX_CTL_REG_MB_BAD_ADDR                      , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_BAD_ADDR );
+REG64_FLD( PU_PBO_MAILBOX_CTL_REG_MB_LINK_DOWN                     , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_LINK_DOWN );
+REG64_FLD( PU_PBO_MAILBOX_CTL_REG_MB_CORRUPT                       , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_CORRUPT );
+REG64_FLD( PU_PBO_MAILBOX_CTL_REG_MB_SENT                          , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_SENT    );
+REG64_FLD( PU_PBO_MAILBOX_CTL_REG_MB_BAD_WRITE                     , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_BAD_WRITE );
+REG64_FLD( PU_PBO_MAILBOX_CTL_REG_MB_RESET                         , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_RESET   );
+REG64_FLD( PU_PBO_MAILBOX_CTL_REG_ID                               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ID         );
+REG64_FLD( PU_PBO_MAILBOX_CTL_REG_MB_LINK_ID                       , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_LINK_ID );
+REG64_FLD( PU_PBO_MAILBOX_CTL_REG_MB_LINK_ID_LEN                   , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_LINK_ID_LEN );
+REG64_FLD( PU_PBO_MAILBOX_CTL_REG_MB_SPARE                         , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_SPARE   );
+REG64_FLD( PU_PBO_MAILBOX_CTL_REG_MB_SPARE_LEN                     , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MB_SPARE_LEN );
+
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_LIMIT             , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK0_DOB_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_LIMIT_LEN         , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK0_DOB_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_VC0_LIMIT         , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK0_DOB_VC0_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_VC0_LIMIT_LEN     , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK0_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_VC1_LIMIT         , 17  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK0_DOB_VC1_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_VC1_LIMIT_LEN     , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK0_DOB_VC1_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK01_DIB_VC_LIMIT         , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK01_DIB_VC_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK01_DIB_VC_LIMIT_LEN     , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK01_DIB_VC_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_LIMIT             , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK1_DOB_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_LIMIT_LEN         , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK1_DOB_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_VC0_LIMIT         , 41  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK1_DOB_VC0_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_VC0_LIMIT_LEN     , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK1_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_VC1_LIMIT         , 49  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK1_DOB_VC1_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_VC1_LIMIT_LEN     , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK1_DOB_VC1_LIMIT_LEN );
+
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_LIMIT             , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK2_DOB_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_LIMIT_LEN         , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK2_DOB_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_VC0_LIMIT         , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK2_DOB_VC0_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_VC0_LIMIT_LEN     , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK2_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_VC1_LIMIT         , 17  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK2_DOB_VC1_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_VC1_LIMIT_LEN     , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK2_DOB_VC1_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK23_DIB_VC_LIMIT         , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK23_DIB_VC_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK23_DIB_VC_LIMIT_LEN     , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK23_DIB_VC_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_LIMIT             , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK3_DOB_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_LIMIT_LEN         , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK3_DOB_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_VC0_LIMIT         , 41  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK3_DOB_VC0_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_VC0_LIMIT_LEN     , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK3_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_VC1_LIMIT         , 49  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK3_DOB_VC1_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_VC1_LIMIT_LEN     , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK3_DOB_VC1_LIMIT_LEN );
+
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_LIMIT             , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK4_DOB_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_LIMIT_LEN         , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK4_DOB_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_VC0_LIMIT         , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK4_DOB_VC0_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_VC0_LIMIT_LEN     , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK4_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_VC1_LIMIT         , 17  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK4_DOB_VC1_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_VC1_LIMIT_LEN     , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK4_DOB_VC1_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK45_DIB_VC_LIMIT         , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK45_DIB_VC_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK45_DIB_VC_LIMIT_LEN     , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK45_DIB_VC_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_LIMIT             , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK5_DOB_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_LIMIT_LEN         , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK5_DOB_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC0_LIMIT         , 41  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK5_DOB_VC0_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC0_LIMIT_LEN     , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK5_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT         , 49  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK5_DOB_VC1_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT_LEN     , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK5_DOB_VC1_LIMIT_LEN );
+
+REG64_FLD( PU_PB_ELINK_PMU0_COUNTER0                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_ELINK_PMU0_COUNTER0_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_ELINK_PMU0_COUNTER1                               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_ELINK_PMU0_COUNTER1_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_ELINK_PMU0_COUNTER2                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_ELINK_PMU0_COUNTER2_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_ELINK_PMU0_COUNTER3                               , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_ELINK_PMU0_COUNTER3_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_ELINK_PMU1_COUNTER0                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_ELINK_PMU1_COUNTER0_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_ELINK_PMU1_COUNTER1                               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_ELINK_PMU1_COUNTER1_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_ELINK_PMU1_COUNTER2                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_ELINK_PMU1_COUNTER2_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_ELINK_PMU1_COUNTER3                               , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_ELINK_PMU1_COUNTER3_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_ELINK_PMU2_COUNTER0                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_ELINK_PMU2_COUNTER0_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_ELINK_PMU2_COUNTER1                               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_ELINK_PMU2_COUNTER1_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_ELINK_PMU2_COUNTER2                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_ELINK_PMU2_COUNTER2_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_ELINK_PMU2_COUNTER3                               , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_ELINK_PMU2_COUNTER3_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_ELINK_PMU3_COUNTER0                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_ELINK_PMU3_COUNTER0_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_ELINK_PMU3_COUNTER1                               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_ELINK_PMU3_COUNTER1_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_ELINK_PMU3_COUNTER2                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_ELINK_PMU3_COUNTER2_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_ELINK_PMU3_COUNTER3                               , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_ELINK_PMU3_COUNTER3_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_ELINK_PMU4_COUNTER0                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_ELINK_PMU4_COUNTER0_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_ELINK_PMU4_COUNTER1                               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_ELINK_PMU4_COUNTER1_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_ELINK_PMU4_COUNTER2                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_ELINK_PMU4_COUNTER2_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_ELINK_PMU4_COUNTER3                               , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_ELINK_PMU4_COUNTER3_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_ELINK_PMU5_COUNTER0                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_ELINK_PMU5_COUNTER0_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_ELINK_PMU5_COUNTER1                               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_ELINK_PMU5_COUNTER1_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_ELINK_PMU5_COUNTER2                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_ELINK_PMU5_COUNTER2_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_ELINK_PMU5_COUNTER3                               , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_ELINK_PMU5_COUNTER3_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_ELINK_PMU6_COUNTER0                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_ELINK_PMU6_COUNTER0_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_ELINK_PMU6_COUNTER1                               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_ELINK_PMU6_COUNTER1_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_ELINK_PMU6_COUNTER2                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_ELINK_PMU6_COUNTER2_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_ELINK_PMU6_COUNTER3                               , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_ELINK_PMU6_COUNTER3_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_ELINK_PMU7_COUNTER0                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_ELINK_PMU7_COUNTER0_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_ELINK_PMU7_COUNTER1                               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_ELINK_PMU7_COUNTER1_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_ELINK_PMU7_COUNTER2                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_ELINK_PMU7_COUNTER2_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_ELINK_PMU7_COUNTER3                               , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_ELINK_PMU7_COUNTER3_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0_ENABLE                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU0_ENABLE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU1_ENABLE                     , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU1_ENABLE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2_ENABLE                     , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU2_ENABLE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU3_ENABLE                     , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU3_ENABLE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU4_ENABLE                     , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU4_ENABLE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU5_ENABLE                     , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU5_ENABLE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU6_ENABLE                     , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU6_ENABLE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU7_ENABLE                     , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU7_ENABLE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMULET_FREEZE_MODE              , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMULET_FREEZE_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_COMMON_FREEZE_MODE              , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COMMON_FREEZE_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMULET_RESET_MODE               , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMULET_RESET_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_EVENT0_SEL                      , 11  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EVENT0_SEL );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_EVENT1_SEL                      , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EVENT1_SEL );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_EVENT1_SEL_LEN                  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EVENT1_SEL_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_EVENT2_SEL                      , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EVENT2_SEL );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_EVENT2_SEL_LEN                  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EVENT2_SEL_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_EVENT3_SEL                      , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EVENT3_SEL );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_EVENT3_SEL_LEN                  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EVENT3_SEL_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0_SIZE                       , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU0_SIZE  );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0_SIZE_LEN                   , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU0_SIZE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU1_SIZE                       , 26  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU1_SIZE  );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU1_SIZE_LEN                   , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU1_SIZE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2_SIZE                       , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU2_SIZE  );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2_SIZE_LEN                   , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU2_SIZE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU3_SIZE                       , 30  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU3_SIZE  );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU3_SIZE_LEN                   , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU3_SIZE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU01_LINK_SELECT               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU01_LINK_SELECT );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU23_LINK_SELECT               , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU23_LINK_SELECT );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU45_LINK_SELECT               , 34  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU45_LINK_SELECT );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU67_LINK_SELECT               , 35  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU67_LINK_SELECT );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT0_MODE             , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU0145_EVENT0_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT0_MODE_LEN         , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU0145_EVENT0_MODE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT1_MODE             , 38  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU0145_EVENT1_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT1_MODE_LEN         , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU0145_EVENT1_MODE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT2_MODE             , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU0145_EVENT2_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT2_MODE_LEN         , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU0145_EVENT2_MODE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT3_MODE             , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU0145_EVENT3_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT3_MODE_LEN         , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU0145_EVENT3_MODE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT0_MODE             , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU2367_EVENT0_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT0_MODE_LEN         , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU2367_EVENT0_MODE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT1_MODE             , 46  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU2367_EVENT1_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT1_MODE_LEN         , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU2367_EVENT1_MODE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT2_MODE             , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU2367_EVENT2_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT2_MODE_LEN         , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU2367_EVENT2_MODE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT3_MODE             , 50  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU2367_EVENT3_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT3_MODE_LEN         , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU2367_EVENT3_MODE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_ENABLE_GLOBAL_RUN               , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE_GLOBAL_RUN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_GLOBAL_RUN_MODE                 , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GLOBAL_RUN_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_SPARE                           , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SPARE      );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_SPARE_LEN                       , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_SET                        , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SET        );
+REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_SET_LEN                    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SET_LEN    );
+REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_STAT                       , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STAT       );
+REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_STAT_LEN                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STAT_LEN   );
+
+REG64_FLD( PU_PB_FP01_CFG_FP0_CREDIT_PRIORITY_4_NOT_8              , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP0_CREDIT_PRIORITY_4_NOT_8 );
+REG64_FLD( PU_PB_FP01_CFG_FP0_DISABLE_GATHERING                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP0_DISABLE_GATHERING );
+REG64_FLD( PU_PB_FP01_CFG_FP0_DISABLE_CMD_COMPRESSION              , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP0_DISABLE_CMD_COMPRESSION );
+REG64_FLD( PU_PB_FP01_CFG_FP0_DISABLE_PRSP_COMPRESSION             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP0_DISABLE_PRSP_COMPRESSION );
+REG64_FLD( PU_PB_FP01_CFG_FP0_LL_CREDIT_LO_LIMIT                   , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP0_LL_CREDIT_LO_LIMIT );
+REG64_FLD( PU_PB_FP01_CFG_FP0_LL_CREDIT_LO_LIMIT_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP0_LL_CREDIT_LO_LIMIT_LEN );
+REG64_FLD( PU_PB_FP01_CFG_FP0_LL_CREDIT_HI_LIMIT                   , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP0_LL_CREDIT_HI_LIMIT );
+REG64_FLD( PU_PB_FP01_CFG_FP0_LL_CREDIT_HI_LIMIT_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP0_LL_CREDIT_HI_LIMIT_LEN );
+REG64_FLD( PU_PB_FP01_CFG_FP0_FMR_DISABLE                          , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP0_FMR_DISABLE );
+REG64_FLD( PU_PB_FP01_CFG_FP0_FMR_SPARE                            , 21  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP0_FMR_SPARE );
+REG64_FLD( PU_PB_FP01_CFG_FP0_FMR_SPARE_LEN                        , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP0_FMR_SPARE_LEN );
+REG64_FLD( PU_PB_FP01_CFG_FP0_RUN_AFTER_FRAME_ERROR                , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP0_RUN_AFTER_FRAME_ERROR );
+REG64_FLD( PU_PB_FP01_CFG_FP0_PRS_DISABLE                          , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP0_PRS_DISABLE );
+REG64_FLD( PU_PB_FP01_CFG_FP0_PRS_SPARE                            , 26  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP0_PRS_SPARE );
+REG64_FLD( PU_PB_FP01_CFG_FP0_PRS_SPARE_LEN                        , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP0_PRS_SPARE_LEN );
+REG64_FLD( PU_PB_FP01_CFG_FP1_CREDIT_PRIORITY_4_NOT_8              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP1_CREDIT_PRIORITY_4_NOT_8 );
+REG64_FLD( PU_PB_FP01_CFG_FP1_DISABLE_GATHERING                    , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP1_DISABLE_GATHERING );
+REG64_FLD( PU_PB_FP01_CFG_FP1_DISABLE_CMD_COMPRESSION              , 34  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP1_DISABLE_CMD_COMPRESSION );
+REG64_FLD( PU_PB_FP01_CFG_FP1_DISABLE_PRSP_COMPRESSION             , 35  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP1_DISABLE_PRSP_COMPRESSION );
+REG64_FLD( PU_PB_FP01_CFG_FP1_LL_CREDIT_LO_LIMIT                   , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP1_LL_CREDIT_LO_LIMIT );
+REG64_FLD( PU_PB_FP01_CFG_FP1_LL_CREDIT_LO_LIMIT_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP1_LL_CREDIT_LO_LIMIT_LEN );
+REG64_FLD( PU_PB_FP01_CFG_FP1_LL_CREDIT_HI_LIMIT                   , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP1_LL_CREDIT_HI_LIMIT );
+REG64_FLD( PU_PB_FP01_CFG_FP1_LL_CREDIT_HI_LIMIT_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP1_LL_CREDIT_HI_LIMIT_LEN );
+REG64_FLD( PU_PB_FP01_CFG_FP1_FMR_DISABLE                          , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP1_FMR_DISABLE );
+REG64_FLD( PU_PB_FP01_CFG_FP1_FMR_SPARE                            , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP1_FMR_SPARE );
+REG64_FLD( PU_PB_FP01_CFG_FP1_FMR_SPARE_LEN                        , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP1_FMR_SPARE_LEN );
+REG64_FLD( PU_PB_FP01_CFG_FP1_RUN_AFTER_FRAME_ERROR                , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP1_RUN_AFTER_FRAME_ERROR );
+REG64_FLD( PU_PB_FP01_CFG_FP1_PRS_DISABLE                          , 57  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP1_PRS_DISABLE );
+REG64_FLD( PU_PB_FP01_CFG_FP1_PRS_SPARE                            , 58  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP1_PRS_SPARE );
+REG64_FLD( PU_PB_FP01_CFG_FP1_PRS_SPARE_LEN                        , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP1_PRS_SPARE_LEN );
+
+REG64_FLD( PU_PB_FP23_CFG_FP2_CREDIT_PRIORITY_4_NOT_8              , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP2_CREDIT_PRIORITY_4_NOT_8 );
+REG64_FLD( PU_PB_FP23_CFG_FP2_DISABLE_GATHERING                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP2_DISABLE_GATHERING );
+REG64_FLD( PU_PB_FP23_CFG_FP2_DISABLE_CMD_COMPRESSION              , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP2_DISABLE_CMD_COMPRESSION );
+REG64_FLD( PU_PB_FP23_CFG_FP2_DISABLE_PRSP_COMPRESSION             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP2_DISABLE_PRSP_COMPRESSION );
+REG64_FLD( PU_PB_FP23_CFG_FP2_LL_CREDIT_LO_LIMIT                   , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP2_LL_CREDIT_LO_LIMIT );
+REG64_FLD( PU_PB_FP23_CFG_FP2_LL_CREDIT_LO_LIMIT_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP2_LL_CREDIT_LO_LIMIT_LEN );
+REG64_FLD( PU_PB_FP23_CFG_FP2_LL_CREDIT_HI_LIMIT                   , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP2_LL_CREDIT_HI_LIMIT );
+REG64_FLD( PU_PB_FP23_CFG_FP2_LL_CREDIT_HI_LIMIT_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP2_LL_CREDIT_HI_LIMIT_LEN );
+REG64_FLD( PU_PB_FP23_CFG_FP2_FMR_DISABLE                          , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP2_FMR_DISABLE );
+REG64_FLD( PU_PB_FP23_CFG_FP2_FMR_SPARE                            , 21  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP2_FMR_SPARE );
+REG64_FLD( PU_PB_FP23_CFG_FP2_FMR_SPARE_LEN                        , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP2_FMR_SPARE_LEN );
+REG64_FLD( PU_PB_FP23_CFG_FP2_RUN_AFTER_FRAME_ERROR                , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP2_RUN_AFTER_FRAME_ERROR );
+REG64_FLD( PU_PB_FP23_CFG_FP2_PRS_DISABLE                          , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP2_PRS_DISABLE );
+REG64_FLD( PU_PB_FP23_CFG_FP2_PRS_SPARE                            , 26  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP2_PRS_SPARE );
+REG64_FLD( PU_PB_FP23_CFG_FP2_PRS_SPARE_LEN                        , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP2_PRS_SPARE_LEN );
+REG64_FLD( PU_PB_FP23_CFG_FP3_CREDIT_PRIORITY_4_NOT_8              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP3_CREDIT_PRIORITY_4_NOT_8 );
+REG64_FLD( PU_PB_FP23_CFG_FP3_DISABLE_GATHERING                    , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP3_DISABLE_GATHERING );
+REG64_FLD( PU_PB_FP23_CFG_FP3_DISABLE_CMD_COMPRESSION              , 34  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP3_DISABLE_CMD_COMPRESSION );
+REG64_FLD( PU_PB_FP23_CFG_FP3_DISABLE_PRSP_COMPRESSION             , 35  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP3_DISABLE_PRSP_COMPRESSION );
+REG64_FLD( PU_PB_FP23_CFG_FP3_LL_CREDIT_LO_LIMIT                   , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP3_LL_CREDIT_LO_LIMIT );
+REG64_FLD( PU_PB_FP23_CFG_FP3_LL_CREDIT_LO_LIMIT_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP3_LL_CREDIT_LO_LIMIT_LEN );
+REG64_FLD( PU_PB_FP23_CFG_FP3_LL_CREDIT_HI_LIMIT                   , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP3_LL_CREDIT_HI_LIMIT );
+REG64_FLD( PU_PB_FP23_CFG_FP3_LL_CREDIT_HI_LIMIT_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP3_LL_CREDIT_HI_LIMIT_LEN );
+REG64_FLD( PU_PB_FP23_CFG_FP3_FMR_DISABLE                          , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP3_FMR_DISABLE );
+REG64_FLD( PU_PB_FP23_CFG_FP3_FMR_SPARE                            , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP3_FMR_SPARE );
+REG64_FLD( PU_PB_FP23_CFG_FP3_FMR_SPARE_LEN                        , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP3_FMR_SPARE_LEN );
+REG64_FLD( PU_PB_FP23_CFG_FP3_RUN_AFTER_FRAME_ERROR                , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP3_RUN_AFTER_FRAME_ERROR );
+REG64_FLD( PU_PB_FP23_CFG_FP3_PRS_DISABLE                          , 57  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP3_PRS_DISABLE );
+REG64_FLD( PU_PB_FP23_CFG_FP3_PRS_SPARE                            , 58  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP3_PRS_SPARE );
+REG64_FLD( PU_PB_FP23_CFG_FP3_PRS_SPARE_LEN                        , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP3_PRS_SPARE_LEN );
+
+REG64_FLD( PU_PB_FP45_CFG_FP4_CREDIT_PRIORITY_4_NOT_8              , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP4_CREDIT_PRIORITY_4_NOT_8 );
+REG64_FLD( PU_PB_FP45_CFG_FP4_DISABLE_GATHERING                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP4_DISABLE_GATHERING );
+REG64_FLD( PU_PB_FP45_CFG_FP4_DISABLE_CMD_COMPRESSION              , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP4_DISABLE_CMD_COMPRESSION );
+REG64_FLD( PU_PB_FP45_CFG_FP4_DISABLE_PRSP_COMPRESSION             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP4_DISABLE_PRSP_COMPRESSION );
+REG64_FLD( PU_PB_FP45_CFG_FP4_LL_CREDIT_LO_LIMIT                   , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP4_LL_CREDIT_LO_LIMIT );
+REG64_FLD( PU_PB_FP45_CFG_FP4_LL_CREDIT_LO_LIMIT_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP4_LL_CREDIT_LO_LIMIT_LEN );
+REG64_FLD( PU_PB_FP45_CFG_FP4_LL_CREDIT_HI_LIMIT                   , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP4_LL_CREDIT_HI_LIMIT );
+REG64_FLD( PU_PB_FP45_CFG_FP4_LL_CREDIT_HI_LIMIT_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP4_LL_CREDIT_HI_LIMIT_LEN );
+REG64_FLD( PU_PB_FP45_CFG_FP4_FMR_DISABLE                          , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP4_FMR_DISABLE );
+REG64_FLD( PU_PB_FP45_CFG_FP4_FMR_SPARE                            , 21  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP4_FMR_SPARE );
+REG64_FLD( PU_PB_FP45_CFG_FP4_FMR_SPARE_LEN                        , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP4_FMR_SPARE_LEN );
+REG64_FLD( PU_PB_FP45_CFG_FP4_RUN_AFTER_FRAME_ERROR                , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP4_RUN_AFTER_FRAME_ERROR );
+REG64_FLD( PU_PB_FP45_CFG_FP4_PRS_DISABLE                          , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP4_PRS_DISABLE );
+REG64_FLD( PU_PB_FP45_CFG_FP4_PRS_SPARE                            , 26  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP4_PRS_SPARE );
+REG64_FLD( PU_PB_FP45_CFG_FP4_PRS_SPARE_LEN                        , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP4_PRS_SPARE_LEN );
+REG64_FLD( PU_PB_FP45_CFG_FP5_CREDIT_PRIORITY_4_NOT_8              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP5_CREDIT_PRIORITY_4_NOT_8 );
+REG64_FLD( PU_PB_FP45_CFG_FP5_DISABLE_GATHERING                    , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP5_DISABLE_GATHERING );
+REG64_FLD( PU_PB_FP45_CFG_FP5_DISABLE_CMD_COMPRESSION              , 34  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP5_DISABLE_CMD_COMPRESSION );
+REG64_FLD( PU_PB_FP45_CFG_FP5_DISABLE_PRSP_COMPRESSION             , 35  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP5_DISABLE_PRSP_COMPRESSION );
+REG64_FLD( PU_PB_FP45_CFG_FP5_LL_CREDIT_LO_LIMIT                   , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP5_LL_CREDIT_LO_LIMIT );
+REG64_FLD( PU_PB_FP45_CFG_FP5_LL_CREDIT_LO_LIMIT_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP5_LL_CREDIT_LO_LIMIT_LEN );
+REG64_FLD( PU_PB_FP45_CFG_FP5_LL_CREDIT_HI_LIMIT                   , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP5_LL_CREDIT_HI_LIMIT );
+REG64_FLD( PU_PB_FP45_CFG_FP5_LL_CREDIT_HI_LIMIT_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP5_LL_CREDIT_HI_LIMIT_LEN );
+REG64_FLD( PU_PB_FP45_CFG_FP5_FMR_DISABLE                          , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP5_FMR_DISABLE );
+REG64_FLD( PU_PB_FP45_CFG_FP5_FMR_SPARE                            , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP5_FMR_SPARE );
+REG64_FLD( PU_PB_FP45_CFG_FP5_FMR_SPARE_LEN                        , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP5_FMR_SPARE_LEN );
+REG64_FLD( PU_PB_FP45_CFG_FP5_RUN_AFTER_FRAME_ERROR                , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP5_RUN_AFTER_FRAME_ERROR );
+REG64_FLD( PU_PB_FP45_CFG_FP5_PRS_DISABLE                          , 57  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP5_PRS_DISABLE );
+REG64_FLD( PU_PB_FP45_CFG_FP5_PRS_SPARE                            , 58  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP5_PRS_SPARE );
+REG64_FLD( PU_PB_FP45_CFG_FP5_PRS_SPARE_LEN                        , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP5_PRS_SPARE_LEN );
+
+REG64_FLD( PU_PB_FP67_CFG_FP6_CREDIT_PRIORITY_4_NOT_8              , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP6_CREDIT_PRIORITY_4_NOT_8 );
+REG64_FLD( PU_PB_FP67_CFG_FP6_DISABLE_GATHERING                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP6_DISABLE_GATHERING );
+REG64_FLD( PU_PB_FP67_CFG_FP6_DISABLE_CMD_COMPRESSION              , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP6_DISABLE_CMD_COMPRESSION );
+REG64_FLD( PU_PB_FP67_CFG_FP6_DISABLE_PRSP_COMPRESSION             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP6_DISABLE_PRSP_COMPRESSION );
+REG64_FLD( PU_PB_FP67_CFG_FP6_LL_CREDIT_LO_LIMIT                   , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP6_LL_CREDIT_LO_LIMIT );
+REG64_FLD( PU_PB_FP67_CFG_FP6_LL_CREDIT_LO_LIMIT_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP6_LL_CREDIT_LO_LIMIT_LEN );
+REG64_FLD( PU_PB_FP67_CFG_FP6_LL_CREDIT_HI_LIMIT                   , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP6_LL_CREDIT_HI_LIMIT );
+REG64_FLD( PU_PB_FP67_CFG_FP6_LL_CREDIT_HI_LIMIT_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP6_LL_CREDIT_HI_LIMIT_LEN );
+REG64_FLD( PU_PB_FP67_CFG_FP6_FMR_DISABLE                          , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP6_FMR_DISABLE );
+REG64_FLD( PU_PB_FP67_CFG_FP6_FMR_SPARE                            , 21  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP6_FMR_SPARE );
+REG64_FLD( PU_PB_FP67_CFG_FP6_FMR_SPARE_LEN                        , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP6_FMR_SPARE_LEN );
+REG64_FLD( PU_PB_FP67_CFG_FP6_RUN_AFTER_FRAME_ERROR                , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP6_RUN_AFTER_FRAME_ERROR );
+REG64_FLD( PU_PB_FP67_CFG_FP6_PRS_DISABLE                          , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP6_PRS_DISABLE );
+REG64_FLD( PU_PB_FP67_CFG_FP6_PRS_SPARE                            , 26  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP6_PRS_SPARE );
+REG64_FLD( PU_PB_FP67_CFG_FP6_PRS_SPARE_LEN                        , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP6_PRS_SPARE_LEN );
+REG64_FLD( PU_PB_FP67_CFG_FP7_CREDIT_PRIORITY_4_NOT_8              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP7_CREDIT_PRIORITY_4_NOT_8 );
+REG64_FLD( PU_PB_FP67_CFG_FP7_DISABLE_GATHERING                    , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP7_DISABLE_GATHERING );
+REG64_FLD( PU_PB_FP67_CFG_FP7_DISABLE_CMD_COMPRESSION              , 34  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP7_DISABLE_CMD_COMPRESSION );
+REG64_FLD( PU_PB_FP67_CFG_FP7_DISABLE_PRSP_COMPRESSION             , 35  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP7_DISABLE_PRSP_COMPRESSION );
+REG64_FLD( PU_PB_FP67_CFG_FP7_LL_CREDIT_LO_LIMIT                   , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP7_LL_CREDIT_LO_LIMIT );
+REG64_FLD( PU_PB_FP67_CFG_FP7_LL_CREDIT_LO_LIMIT_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP7_LL_CREDIT_LO_LIMIT_LEN );
+REG64_FLD( PU_PB_FP67_CFG_FP7_LL_CREDIT_HI_LIMIT                   , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP7_LL_CREDIT_HI_LIMIT );
+REG64_FLD( PU_PB_FP67_CFG_FP7_LL_CREDIT_HI_LIMIT_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP7_LL_CREDIT_HI_LIMIT_LEN );
+REG64_FLD( PU_PB_FP67_CFG_FP7_FMR_DISABLE                          , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP7_FMR_DISABLE );
+REG64_FLD( PU_PB_FP67_CFG_FP7_FMR_SPARE                            , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP7_FMR_SPARE );
+REG64_FLD( PU_PB_FP67_CFG_FP7_FMR_SPARE_LEN                        , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP7_FMR_SPARE_LEN );
+REG64_FLD( PU_PB_FP67_CFG_FP7_RUN_AFTER_FRAME_ERROR                , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP7_RUN_AFTER_FRAME_ERROR );
+REG64_FLD( PU_PB_FP67_CFG_FP7_PRS_DISABLE                          , 57  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP7_PRS_DISABLE );
+REG64_FLD( PU_PB_FP67_CFG_FP7_PRS_SPARE                            , 58  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP7_PRS_SPARE );
+REG64_FLD( PU_PB_FP67_CFG_FP7_PRS_SPARE_LEN                        , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_FP7_PRS_SPARE_LEN );
+
+REG64_FLD( PU_PB_IOE_FIR_ACTION0_REG_ACTION0                       , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACTION0    );
+REG64_FLD( PU_PB_IOE_FIR_ACTION0_REG_ACTION0_LEN                   , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_PB_IOE_FIR_ACTION1_REG_ACTION1                       , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACTION1    );
+REG64_FLD( PU_PB_IOE_FIR_ACTION1_REG_ACTION1_LEN                   , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FMR00_TRAINED                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR00_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FMR01_TRAINED                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR01_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FMR02_TRAINED                    , 2   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR02_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FMR03_TRAINED                    , 3   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR03_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FMR04_TRAINED                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR04_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FMR05_TRAINED                    , 5   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR05_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV6                             , 6   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RSV6       );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV7                             , 7   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RSV7       );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB01_UE                         , 8   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB01_UE   );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB01_CE                         , 9   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB01_CE   );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB01_SUE                        , 10  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB01_SUE  );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB23_UE                         , 11  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB23_UE   );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB23_CE                         , 12  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB23_CE   );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB23_SUE                        , 13  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB23_SUE  );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB45_UE                         , 14  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB45_UE   );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB45_CE                         , 15  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB45_CE   );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB45_SUE                        , 16  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB45_SUE  );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV17                            , 17  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RSV17      );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV18                            , 18  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RSV18      );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV19                            , 19  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RSV19      );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FRAMER00_ATTN                    , 20  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER00_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FRAMER01_ATTN                    , 21  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER01_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FRAMER02_ATTN                    , 22  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER02_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FRAMER03_ATTN                    , 23  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER03_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FRAMER04_ATTN                    , 24  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER04_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FRAMER05_ATTN                    , 25  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER05_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV26                            , 26  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RSV26      );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV27                            , 27  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RSV27      );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_PARSER00_ATTN                    , 28  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER00_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_PARSER01_ATTN                    , 29  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER01_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_PARSER02_ATTN                    , 30  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER02_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_PARSER03_ATTN                    , 31  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER03_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_PARSER04_ATTN                    , 32  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER04_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_PARSER05_ATTN                    , 33  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER05_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV34                            , 34  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RSV34      );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV35                            , 35  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RSV35      );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB00_SPATTN                      , 36  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB00_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB01_SPATTN                      , 37  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB01_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB10_SPATTN                      , 38  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB10_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB11_SPATTN                      , 39  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB11_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB20_SPATTN                      , 40  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB20_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB21_SPATTN                      , 41  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB21_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB30_SPATTN                      , 42  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB30_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB31_SPATTN                      , 43  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB31_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB40_SPATTN                      , 44  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB40_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB41_SPATTN                      , 45  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB41_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB50_SPATTN                      , 46  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB50_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB51_SPATTN                      , 47  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB51_SPATTN );
+
+REG64_FLD( PU_PB_IOE_FIR_REG_FMR00_TRAINED                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR00_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_REG_FMR01_TRAINED                         , 1   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR01_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_REG_FMR02_TRAINED                         , 2   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR02_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_REG_FMR03_TRAINED                         , 3   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR03_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_REG_FMR04_TRAINED                         , 4   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR04_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_REG_FMR05_TRAINED                         , 5   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR05_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_REG_RSV6                                  , 6   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RSV6       );
+REG64_FLD( PU_PB_IOE_FIR_REG_RSV7                                  , 7   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RSV7       );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB01_UE                              , 8   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB01_UE   );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB01_CE                              , 9   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB01_CE   );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB01_SUE                             , 10  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB01_SUE  );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB23_UE                              , 11  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB23_UE   );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB23_CE                              , 12  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB23_CE   );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB23_SUE                             , 13  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB23_SUE  );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB45_UE                              , 14  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB45_UE   );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB45_CE                              , 15  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB45_CE   );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB45_SUE                             , 16  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB45_SUE  );
+REG64_FLD( PU_PB_IOE_FIR_REG_RSV17                                 , 17  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RSV17      );
+REG64_FLD( PU_PB_IOE_FIR_REG_RSV18                                 , 18  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RSV18      );
+REG64_FLD( PU_PB_IOE_FIR_REG_RSV19                                 , 19  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RSV19      );
+REG64_FLD( PU_PB_IOE_FIR_REG_FRAMER00_ATTN                         , 20  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER00_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_FRAMER01_ATTN                         , 21  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER01_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_FRAMER02_ATTN                         , 22  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER02_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_FRAMER03_ATTN                         , 23  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER03_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_FRAMER04_ATTN                         , 24  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER04_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_FRAMER05_ATTN                         , 25  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER05_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_RSV26                                 , 26  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RSV26      );
+REG64_FLD( PU_PB_IOE_FIR_REG_RSV27                                 , 27  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RSV27      );
+REG64_FLD( PU_PB_IOE_FIR_REG_PARSER00_ATTN                         , 28  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER00_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_PARSER01_ATTN                         , 29  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER01_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_PARSER02_ATTN                         , 30  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER02_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_PARSER03_ATTN                         , 31  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER03_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_PARSER04_ATTN                         , 32  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER04_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_PARSER05_ATTN                         , 33  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER05_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_RSV34                                 , 34  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RSV34      );
+REG64_FLD( PU_PB_IOE_FIR_REG_RSV35                                 , 35  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RSV35      );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB00_SPATTN                           , 36  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB00_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB01_SPATTN                           , 37  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB01_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB10_SPATTN                           , 38  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB10_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB11_SPATTN                           , 39  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB11_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB20_SPATTN                           , 40  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB20_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB21_SPATTN                           , 41  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB21_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB30_SPATTN                           , 42  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB30_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB31_SPATTN                           , 43  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB31_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB40_SPATTN                           , 44  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB40_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB41_SPATTN                           , 45  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB41_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB50_SPATTN                           , 46  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB50_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB51_SPATTN                           , 47  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB51_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB01_ERR                             , 52  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB01_ERR  );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB23_ERR                             , 53  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB23_ERR  );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB45_ERR                             , 54  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB45_ERR  );
+REG64_FLD( PU_PB_IOE_FIR_REG_DIB01_ERR                             , 56  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DIB01_ERR  );
+REG64_FLD( PU_PB_IOE_FIR_REG_DIB23_ERR                             , 57  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DIB23_ERR  );
+REG64_FLD( PU_PB_IOE_FIR_REG_DIB45_ERR                             , 58  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DIB45_ERR  );
+REG64_FLD( PU_PB_IOE_FIR_REG_SCOM_ERR_DUP                          , 62  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP );
+REG64_FLD( PU_PB_IOE_FIR_REG_SCOM_ERR                              , 63  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR   );
+
+REG64_FLD( PU_PB_IOO_FIR_ACTION0_REG_ACTION0                       , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACTION0    );
+REG64_FLD( PU_PB_IOO_FIR_ACTION0_REG_ACTION0_LEN                   , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_PB_IOO_FIR_ACTION1_REG_ACTION1                       , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACTION1    );
+REG64_FLD( PU_PB_IOO_FIR_ACTION1_REG_ACTION1_LEN                   , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_FMR00_TRAINED                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR00_TRAINED );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_FMR01_TRAINED                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR01_TRAINED );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_FMR02_TRAINED                    , 2   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR02_TRAINED );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_FMR03_TRAINED                    , 3   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR03_TRAINED );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_FMR04_TRAINED                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR04_TRAINED );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_FMR05_TRAINED                    , 5   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR05_TRAINED );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_FMR06_TRAINED                    , 6   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR06_TRAINED );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_FMR07_TRAINED                    , 7   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR07_TRAINED );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_DOB01_UE                         , 8   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB01_UE   );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_DOB01_CE                         , 9   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB01_CE   );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_DOB01_SUE                        , 10  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB01_SUE  );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_DOB23_UE                         , 11  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB23_UE   );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_DOB23_CE                         , 12  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB23_CE   );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_DOB23_SUE                        , 13  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB23_SUE  );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_DOB45_UE                         , 14  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB45_UE   );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_DOB45_CE                         , 15  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB45_CE   );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_DOB45_SUE                        , 16  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB45_SUE  );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_DOB67_UE                         , 17  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB67_UE   );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_DOB67_CE                         , 18  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB67_CE   );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_DOB67_SUE                        , 19  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB67_SUE  );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_FRAMER00_ATTN                    , 20  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER00_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_FRAMER01_ATTN                    , 21  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER01_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_FRAMER02_ATTN                    , 22  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER02_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_FRAMER03_ATTN                    , 23  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER03_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_FRAMER04_ATTN                    , 24  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER04_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_FRAMER05_ATTN                    , 25  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER05_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_FRAMER06_ATTN                    , 26  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER06_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_FRAMER07_ATTN                    , 27  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER07_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_PARSER00_ATTN                    , 28  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER00_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_PARSER01_ATTN                    , 29  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER01_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_PARSER02_ATTN                    , 30  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER02_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_PARSER03_ATTN                    , 31  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER03_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_PARSER04_ATTN                    , 32  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER04_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_PARSER05_ATTN                    , 33  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER05_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_PARSER06_ATTN                    , 34  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER06_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_PARSER07_ATTN                    , 35  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER07_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_MB00_SPATTN                      , 36  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB00_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_MB01_SPATTN                      , 37  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB01_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_MB10_SPATTN                      , 38  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB10_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_MB11_SPATTN                      , 39  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB11_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_MB20_SPATTN                      , 40  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB20_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_MB21_SPATTN                      , 41  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB21_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_MB30_SPATTN                      , 42  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB30_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_MB31_SPATTN                      , 43  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB31_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_MB40_SPATTN                      , 44  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB40_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_MB41_SPATTN                      , 45  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB41_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_MB50_SPATTN                      , 46  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB50_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_MB51_SPATTN                      , 47  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB51_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_MB60_SPATTN                      , 48  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB60_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_MB61_SPATTN                      , 49  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB61_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_MB70_SPATTN                      , 50  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB70_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_MASK_REG_MB71_SPATTN                      , 51  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB71_SPATTN );
+
+REG64_FLD( PU_PB_IOO_FIR_REG_FMR00_TRAINED                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR00_TRAINED );
+REG64_FLD( PU_PB_IOO_FIR_REG_FMR01_TRAINED                         , 1   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR01_TRAINED );
+REG64_FLD( PU_PB_IOO_FIR_REG_FMR02_TRAINED                         , 2   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR02_TRAINED );
+REG64_FLD( PU_PB_IOO_FIR_REG_FMR03_TRAINED                         , 3   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR03_TRAINED );
+REG64_FLD( PU_PB_IOO_FIR_REG_FMR04_TRAINED                         , 4   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR04_TRAINED );
+REG64_FLD( PU_PB_IOO_FIR_REG_FMR05_TRAINED                         , 5   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR05_TRAINED );
+REG64_FLD( PU_PB_IOO_FIR_REG_FMR06_TRAINED                         , 6   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR06_TRAINED );
+REG64_FLD( PU_PB_IOO_FIR_REG_FMR07_TRAINED                         , 7   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FMR07_TRAINED );
+REG64_FLD( PU_PB_IOO_FIR_REG_DOB01_UE                              , 8   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB01_UE   );
+REG64_FLD( PU_PB_IOO_FIR_REG_DOB01_CE                              , 9   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB01_CE   );
+REG64_FLD( PU_PB_IOO_FIR_REG_DOB01_SUE                             , 10  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB01_SUE  );
+REG64_FLD( PU_PB_IOO_FIR_REG_DOB23_UE                              , 11  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB23_UE   );
+REG64_FLD( PU_PB_IOO_FIR_REG_DOB23_CE                              , 12  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB23_CE   );
+REG64_FLD( PU_PB_IOO_FIR_REG_DOB23_SUE                             , 13  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB23_SUE  );
+REG64_FLD( PU_PB_IOO_FIR_REG_DOB45_UE                              , 14  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB45_UE   );
+REG64_FLD( PU_PB_IOO_FIR_REG_DOB45_CE                              , 15  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB45_CE   );
+REG64_FLD( PU_PB_IOO_FIR_REG_DOB45_SUE                             , 16  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB45_SUE  );
+REG64_FLD( PU_PB_IOO_FIR_REG_DOB67_UE                              , 17  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB67_UE   );
+REG64_FLD( PU_PB_IOO_FIR_REG_DOB67_CE                              , 18  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB67_CE   );
+REG64_FLD( PU_PB_IOO_FIR_REG_DOB67_SUE                             , 19  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB67_SUE  );
+REG64_FLD( PU_PB_IOO_FIR_REG_FRAMER00_ATTN                         , 20  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER00_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_FRAMER01_ATTN                         , 21  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER01_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_FRAMER02_ATTN                         , 22  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER02_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_FRAMER03_ATTN                         , 23  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER03_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_FRAMER04_ATTN                         , 24  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER04_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_FRAMER05_ATTN                         , 25  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER05_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_FRAMER06_ATTN                         , 26  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER06_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_FRAMER07_ATTN                         , 27  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FRAMER07_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_PARSER00_ATTN                         , 28  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER00_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_PARSER01_ATTN                         , 29  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER01_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_PARSER02_ATTN                         , 30  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER02_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_PARSER03_ATTN                         , 31  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER03_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_PARSER04_ATTN                         , 32  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER04_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_PARSER05_ATTN                         , 33  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER05_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_PARSER06_ATTN                         , 34  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER06_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_PARSER07_ATTN                         , 35  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARSER07_ATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_MB00_SPATTN                           , 36  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB00_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_MB01_SPATTN                           , 37  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB01_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_MB10_SPATTN                           , 38  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB10_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_MB11_SPATTN                           , 39  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB11_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_MB20_SPATTN                           , 40  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB20_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_MB21_SPATTN                           , 41  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB21_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_MB30_SPATTN                           , 42  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB30_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_MB31_SPATTN                           , 43  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB31_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_MB40_SPATTN                           , 44  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB40_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_MB41_SPATTN                           , 45  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB41_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_MB50_SPATTN                           , 46  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB50_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_MB51_SPATTN                           , 47  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB51_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_MB60_SPATTN                           , 48  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB60_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_MB61_SPATTN                           , 49  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB61_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_MB70_SPATTN                           , 50  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB70_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_MB71_SPATTN                           , 51  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MB71_SPATTN );
+REG64_FLD( PU_PB_IOO_FIR_REG_DOB01_ERR                             , 52  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB01_ERR  );
+REG64_FLD( PU_PB_IOO_FIR_REG_DOB23_ERR                             , 53  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB23_ERR  );
+REG64_FLD( PU_PB_IOO_FIR_REG_DOB45_ERR                             , 54  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB45_ERR  );
+REG64_FLD( PU_PB_IOO_FIR_REG_DOB67_ERR                             , 55  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOB67_ERR  );
+REG64_FLD( PU_PB_IOO_FIR_REG_DIB01_ERR                             , 56  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DIB01_ERR  );
+REG64_FLD( PU_PB_IOO_FIR_REG_DIB23_ERR                             , 57  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DIB23_ERR  );
+REG64_FLD( PU_PB_IOO_FIR_REG_DIB45_ERR                             , 58  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DIB45_ERR  );
+REG64_FLD( PU_PB_IOO_FIR_REG_DIB67_ERR                             , 59  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DIB67_ERR  );
+REG64_FLD( PU_PB_IOO_FIR_REG_SCOM_ERR_DUP                          , 62  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP );
+REG64_FLD( PU_PB_IOO_FIR_REG_SCOM_ERR                              , 63  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR   );
+
+REG64_FLD( PU_PB_MISC_CFG_IOE01_IS_LOGICAL_PAIR                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IOE01_IS_LOGICAL_PAIR );
+REG64_FLD( PU_PB_MISC_CFG_IOE23_IS_LOGICAL_PAIR                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IOE23_IS_LOGICAL_PAIR );
+REG64_FLD( PU_PB_MISC_CFG_IOE45_IS_LOGICAL_PAIR                    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IOE45_IS_LOGICAL_PAIR );
+REG64_FLD( PU_PB_MISC_CFG_SPARE3                                   , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SPARE3     );
+REG64_FLD( PU_PB_MISC_CFG_SCOM_LINK01_RESET_KEEPER                 , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SCOM_LINK01_RESET_KEEPER );
+REG64_FLD( PU_PB_MISC_CFG_SCOM_LINK23_RESET_KEEPER                 , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SCOM_LINK23_RESET_KEEPER );
+REG64_FLD( PU_PB_MISC_CFG_SCOM_LINK45_RESET_KEEPER                 , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SCOM_LINK45_RESET_KEEPER );
+REG64_FLD( PU_PB_MISC_CFG_SPARE7                                   , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SPARE7     );
+REG64_FLD( PU_PB_MISC_CFG_SPARE8                                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SPARE8     );
+REG64_FLD( PU_PB_MISC_CFG_SPARE9                                   , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SPARE9     );
+REG64_FLD( PU_PB_MISC_CFG_SPARE10                                  , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SPARE10    );
+REG64_FLD( PU_PB_MISC_CFG_SPARE11                                  , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SPARE11    );
+REG64_FLD( PU_PB_MISC_CFG_LINK_AVP_MODE                            , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LINK_AVP_MODE );
+REG64_FLD( PU_PB_MISC_CFG_SPARE13                                  , 13  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SPARE13    );
+REG64_FLD( PU_PB_MISC_CFG_SPARE14                                  , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SPARE14    );
+REG64_FLD( PU_PB_MISC_CFG_SPARE15                                  , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SPARE15    );
+
+REG64_FLD( PU_PB_OLINK_DATA_01_CFG_REG_LINK01_CAPP_MODE            , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK01_CAPP_MODE );
+REG64_FLD( PU_PB_OLINK_DATA_01_CFG_REG_LINK01_HRB_INIT_STATE       , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK01_HRB_INIT_STATE );
+REG64_FLD( PU_PB_OLINK_DATA_01_CFG_REG_LINK0_SPARE                 , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK0_SPARE );
+REG64_FLD( PU_PB_OLINK_DATA_01_CFG_REG_LINK0_SPARE_LEN             , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK0_SPARE_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_VC0_LIMIT         , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK0_DOB_VC0_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_VC0_LIMIT_LEN     , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK0_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_VC1_LIMIT         , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK0_DOB_VC1_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_VC1_LIMIT_LEN     , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK0_DOB_VC1_LIMIT_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_01_CFG_REG_LINK01_DIB_VC_LIMIT         , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK01_DIB_VC_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_01_CFG_REG_LINK01_DIB_VC_LIMIT_LEN     , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK01_DIB_VC_LIMIT_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_01_CFG_REG_DIB01_SPARE                 , 29  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIB01_SPARE );
+REG64_FLD( PU_PB_OLINK_DATA_01_CFG_REG_DIB01_SPARE_LEN             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIB01_SPARE_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_01_CFG_REG_LINK1_SPARE                 , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK1_SPARE );
+REG64_FLD( PU_PB_OLINK_DATA_01_CFG_REG_LINK1_SPARE_LEN             , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK1_SPARE_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_VC0_LIMIT         , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK1_DOB_VC0_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_VC0_LIMIT_LEN     , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK1_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_VC1_LIMIT         , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK1_DOB_VC1_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_VC1_LIMIT_LEN     , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK1_DOB_VC1_LIMIT_LEN );
+
+REG64_FLD( PU_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_LIMIT             , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK2_DOB_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_LIMIT_LEN         , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK2_DOB_LIMIT_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_VC0_LIMIT         , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK2_DOB_VC0_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_VC0_LIMIT_LEN     , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK2_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_VC1_LIMIT         , 17  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK2_DOB_VC1_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_VC1_LIMIT_LEN     , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK2_DOB_VC1_LIMIT_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_23_CFG_REG_LINK23_DIB_VC_LIMIT         , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK23_DIB_VC_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_23_CFG_REG_LINK23_DIB_VC_LIMIT_LEN     , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK23_DIB_VC_LIMIT_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_LIMIT             , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK3_DOB_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_LIMIT_LEN         , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK3_DOB_LIMIT_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_VC0_LIMIT         , 41  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK3_DOB_VC0_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_VC0_LIMIT_LEN     , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK3_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_VC1_LIMIT         , 49  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK3_DOB_VC1_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_VC1_LIMIT_LEN     , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK3_DOB_VC1_LIMIT_LEN );
+
+REG64_FLD( PU_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_LIMIT             , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK4_DOB_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_LIMIT_LEN         , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK4_DOB_LIMIT_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_VC0_LIMIT         , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK4_DOB_VC0_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_VC0_LIMIT_LEN     , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK4_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_VC1_LIMIT         , 17  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK4_DOB_VC1_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_VC1_LIMIT_LEN     , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK4_DOB_VC1_LIMIT_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_45_CFG_REG_LINK45_DIB_VC_LIMIT         , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK45_DIB_VC_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_45_CFG_REG_LINK45_DIB_VC_LIMIT_LEN     , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK45_DIB_VC_LIMIT_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_LIMIT             , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK5_DOB_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_LIMIT_LEN         , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK5_DOB_LIMIT_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_VC0_LIMIT         , 41  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK5_DOB_VC0_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_VC0_LIMIT_LEN     , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK5_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT         , 49  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK5_DOB_VC1_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT_LEN     , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK5_DOB_VC1_LIMIT_LEN );
+
+REG64_FLD( PU_PB_OLINK_DATA_67_CFG_REG_LINK67_CAPP_MODE            , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK67_CAPP_MODE );
+REG64_FLD( PU_PB_OLINK_DATA_67_CFG_REG_LINK67_HRB_INIT_STATE       , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK67_HRB_INIT_STATE );
+REG64_FLD( PU_PB_OLINK_DATA_67_CFG_REG_LINK6_SPARE                 , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK6_SPARE );
+REG64_FLD( PU_PB_OLINK_DATA_67_CFG_REG_LINK6_SPARE_LEN             , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK6_SPARE_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_VC0_LIMIT         , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK6_DOB_VC0_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_VC0_LIMIT_LEN     , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK6_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_VC1_LIMIT         , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK6_DOB_VC1_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_VC1_LIMIT_LEN     , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK6_DOB_VC1_LIMIT_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_67_CFG_REG_LINK67_DIB_VC_LIMIT         , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK67_DIB_VC_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_67_CFG_REG_LINK67_DIB_VC_LIMIT_LEN     , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK67_DIB_VC_LIMIT_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_67_CFG_REG_DIB67_SPARE                 , 29  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIB67_SPARE );
+REG64_FLD( PU_PB_OLINK_DATA_67_CFG_REG_DIB67_SPARE_LEN             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DIB67_SPARE_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_67_CFG_REG_LINK7_SPARE                 , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK7_SPARE );
+REG64_FLD( PU_PB_OLINK_DATA_67_CFG_REG_LINK7_SPARE_LEN             , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK7_SPARE_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC0_LIMIT         , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK7_DOB_VC0_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC0_LIMIT_LEN     , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK7_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC1_LIMIT         , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK7_DOB_VC1_LIMIT );
+REG64_FLD( PU_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC1_LIMIT_LEN     , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK7_DOB_VC1_LIMIT_LEN );
+
+REG64_FLD( PU_PB_OLINK_PMU0_COUNTER0                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_OLINK_PMU0_COUNTER0_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_OLINK_PMU0_COUNTER1                               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_OLINK_PMU0_COUNTER1_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_OLINK_PMU0_COUNTER2                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_OLINK_PMU0_COUNTER2_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_OLINK_PMU0_COUNTER3                               , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_OLINK_PMU0_COUNTER3_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_OLINK_PMU1_COUNTER0                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_OLINK_PMU1_COUNTER0_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_OLINK_PMU1_COUNTER1                               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_OLINK_PMU1_COUNTER1_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_OLINK_PMU1_COUNTER2                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_OLINK_PMU1_COUNTER2_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_OLINK_PMU1_COUNTER3                               , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_OLINK_PMU1_COUNTER3_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_OLINK_PMU2_COUNTER0                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_OLINK_PMU2_COUNTER0_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_OLINK_PMU2_COUNTER1                               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_OLINK_PMU2_COUNTER1_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_OLINK_PMU2_COUNTER2                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_OLINK_PMU2_COUNTER2_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_OLINK_PMU2_COUNTER3                               , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_OLINK_PMU2_COUNTER3_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_OLINK_PMU3_COUNTER0                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_OLINK_PMU3_COUNTER0_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_OLINK_PMU3_COUNTER1                               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_OLINK_PMU3_COUNTER1_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_OLINK_PMU3_COUNTER2                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_OLINK_PMU3_COUNTER2_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_OLINK_PMU3_COUNTER3                               , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_OLINK_PMU3_COUNTER3_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_OLINK_PMU4_COUNTER0                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_OLINK_PMU4_COUNTER0_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_OLINK_PMU4_COUNTER1                               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_OLINK_PMU4_COUNTER1_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_OLINK_PMU4_COUNTER2                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_OLINK_PMU4_COUNTER2_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_OLINK_PMU4_COUNTER3                               , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_OLINK_PMU4_COUNTER3_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_OLINK_PMU5_COUNTER0                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_OLINK_PMU5_COUNTER0_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_OLINK_PMU5_COUNTER1                               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_OLINK_PMU5_COUNTER1_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_OLINK_PMU5_COUNTER2                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_OLINK_PMU5_COUNTER2_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_OLINK_PMU5_COUNTER3                               , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_OLINK_PMU5_COUNTER3_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_OLINK_PMU6_COUNTER0                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_OLINK_PMU6_COUNTER0_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_OLINK_PMU6_COUNTER1                               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_OLINK_PMU6_COUNTER1_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_OLINK_PMU6_COUNTER2                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_OLINK_PMU6_COUNTER2_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_OLINK_PMU6_COUNTER3                               , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_OLINK_PMU6_COUNTER3_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_OLINK_PMU7_COUNTER0                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_OLINK_PMU7_COUNTER0_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_OLINK_PMU7_COUNTER1                               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_OLINK_PMU7_COUNTER1_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_OLINK_PMU7_COUNTER2                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_OLINK_PMU7_COUNTER2_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_OLINK_PMU7_COUNTER3                               , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_OLINK_PMU7_COUNTER3_LEN                           , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU0_ENABLE                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU0_ENABLE );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU1_ENABLE                     , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU1_ENABLE );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU2_ENABLE                     , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU2_ENABLE );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU3_ENABLE                     , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU3_ENABLE );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU4_ENABLE                     , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU4_ENABLE );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU5_ENABLE                     , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU5_ENABLE );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU6_ENABLE                     , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU6_ENABLE );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU7_ENABLE                     , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU7_ENABLE );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMULET_FREEZE_MODE              , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMULET_FREEZE_MODE );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_COMMON_FREEZE_MODE              , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_COMMON_FREEZE_MODE );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMULET_RESET_MODE               , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMULET_RESET_MODE );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_EVENT0_SEL                      , 11  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EVENT0_SEL );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_EVENT1_SEL                      , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EVENT1_SEL );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_EVENT1_SEL_LEN                  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EVENT1_SEL_LEN );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_EVENT2_SEL                      , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EVENT2_SEL );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_EVENT2_SEL_LEN                  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EVENT2_SEL_LEN );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_EVENT3_SEL                      , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EVENT3_SEL );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_EVENT3_SEL_LEN                  , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EVENT3_SEL_LEN );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU0_SIZE                       , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU0_SIZE  );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU0_SIZE_LEN                   , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU0_SIZE_LEN );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU1_SIZE                       , 26  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU1_SIZE  );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU1_SIZE_LEN                   , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU1_SIZE_LEN );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU2_SIZE                       , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU2_SIZE  );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU2_SIZE_LEN                   , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU2_SIZE_LEN );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU3_SIZE                       , 30  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU3_SIZE  );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU3_SIZE_LEN                   , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU3_SIZE_LEN );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU01_LINK_SELECT               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU01_LINK_SELECT );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU23_LINK_SELECT               , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU23_LINK_SELECT );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU45_LINK_SELECT               , 34  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU45_LINK_SELECT );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU67_LINK_SELECT               , 35  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU67_LINK_SELECT );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT0_MODE             , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU0145_EVENT0_MODE );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT0_MODE_LEN         , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU0145_EVENT0_MODE_LEN );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT1_MODE             , 38  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU0145_EVENT1_MODE );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT1_MODE_LEN         , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU0145_EVENT1_MODE_LEN );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT2_MODE             , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU0145_EVENT2_MODE );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT2_MODE_LEN         , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU0145_EVENT2_MODE_LEN );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT3_MODE             , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU0145_EVENT3_MODE );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT3_MODE_LEN         , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU0145_EVENT3_MODE_LEN );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT0_MODE             , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU2367_EVENT0_MODE );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT0_MODE_LEN         , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU2367_EVENT0_MODE_LEN );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT1_MODE             , 46  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU2367_EVENT1_MODE );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT1_MODE_LEN         , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU2367_EVENT1_MODE_LEN );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT2_MODE             , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU2367_EVENT2_MODE );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT2_MODE_LEN         , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU2367_EVENT2_MODE_LEN );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT3_MODE             , 50  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU2367_EVENT3_MODE );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT3_MODE_LEN         , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PMU2367_EVENT3_MODE_LEN );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_ENABLE_GLOBAL_RUN               , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE_GLOBAL_RUN );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_GLOBAL_RUN_MODE                 , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GLOBAL_RUN_MODE );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_SPARE                           , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SPARE      );
+REG64_FLD( PU_PB_OLINK_PMU_CTL_REG_SPARE_LEN                       , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_PB_OLINK_RT_DELAY_CTL_REG_SET                        , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SET        );
+REG64_FLD( PU_PB_OLINK_RT_DELAY_CTL_REG_SET_LEN                    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SET_LEN    );
+REG64_FLD( PU_PB_OLINK_RT_DELAY_CTL_REG_STAT                       , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STAT       );
+REG64_FLD( PU_PB_OLINK_RT_DELAY_CTL_REG_STAT_LEN                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STAT_LEN   );
+
+REG64_FLD( PU_PB_TRACE_CFG_LINK00_HI                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK00_HI  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK00_HI_LEN                           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK00_HI_LEN );
+REG64_FLD( PU_PB_TRACE_CFG_LINK00_LO                               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK00_LO  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK00_LO_LEN                           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK00_LO_LEN );
+REG64_FLD( PU_PB_TRACE_CFG_LINK01_HI                               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK01_HI  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK01_HI_LEN                           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK01_HI_LEN );
+REG64_FLD( PU_PB_TRACE_CFG_LINK01_LO                               , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK01_LO  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK01_LO_LEN                           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK01_LO_LEN );
+REG64_FLD( PU_PB_TRACE_CFG_LINK02_HI                               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK02_HI  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK02_HI_LEN                           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK02_HI_LEN );
+REG64_FLD( PU_PB_TRACE_CFG_LINK02_LO                               , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK02_LO  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK02_LO_LEN                           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK02_LO_LEN );
+REG64_FLD( PU_PB_TRACE_CFG_LINK03_HI                               , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK03_HI  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK03_HI_LEN                           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK03_HI_LEN );
+REG64_FLD( PU_PB_TRACE_CFG_LINK03_LO                               , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK03_LO  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK03_LO_LEN                           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK03_LO_LEN );
+REG64_FLD( PU_PB_TRACE_CFG_LINK04_HI                               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK04_HI  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK04_HI_LEN                           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK04_HI_LEN );
+REG64_FLD( PU_PB_TRACE_CFG_LINK04_LO                               , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK04_LO  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK04_LO_LEN                           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK04_LO_LEN );
+REG64_FLD( PU_PB_TRACE_CFG_LINK05_HI                               , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK05_HI  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK05_HI_LEN                           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK05_HI_LEN );
+REG64_FLD( PU_PB_TRACE_CFG_LINK05_LO                               , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK05_LO  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK05_LO_LEN                           , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LINK05_LO_LEN );
+
+REG64_FLD( PU_IOP1_PCS_M1_CONTROL_REG_CONTROL                      , 48  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM     , SH_FLD_CONTROL    );
+REG64_FLD( PU_IOP1_PCS_M1_CONTROL_REG_CONTROL_LEN                  , 16  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM     , SH_FLD_CONTROL_LEN );
+
+REG64_FLD( PU_IOP0_PCS_M1_CONTROL_REG_CONTROL                      , 48  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM     , SH_FLD_CONTROL    );
+REG64_FLD( PU_IOP0_PCS_M1_CONTROL_REG_CONTROL_LEN                  , 16  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM     , SH_FLD_CONTROL_LEN );
+
+REG64_FLD( PU_IOP2_PCS_M1_CONTROL_REG_CONTROL                      , 48  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM     , SH_FLD_CONTROL    );
+REG64_FLD( PU_IOP2_PCS_M1_CONTROL_REG_CONTROL_LEN                  , 16  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM     , SH_FLD_CONTROL_LEN );
+
+REG64_FLD( PU_IOP1_PCS_M2_CONTROL_REG_CONTROL                      , 48  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM     , SH_FLD_CONTROL    );
+REG64_FLD( PU_IOP1_PCS_M2_CONTROL_REG_CONTROL_LEN                  , 16  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM     , SH_FLD_CONTROL_LEN );
+
+REG64_FLD( PU_IOP0_PCS_M2_CONTROL_REG_CONTROL                      , 48  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM     , SH_FLD_CONTROL    );
+REG64_FLD( PU_IOP0_PCS_M2_CONTROL_REG_CONTROL_LEN                  , 16  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM     , SH_FLD_CONTROL_LEN );
+
+REG64_FLD( PU_IOP2_PCS_M2_CONTROL_REG_CONTROL                      , 48  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM     , SH_FLD_CONTROL    );
+REG64_FLD( PU_IOP2_PCS_M2_CONTROL_REG_CONTROL_LEN                  , 16  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM     , SH_FLD_CONTROL_LEN );
+
+REG64_FLD( PU_IOP1_PCS_M3_CONTROL_REG_CONTROL                      , 48  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM     , SH_FLD_CONTROL    );
+REG64_FLD( PU_IOP1_PCS_M3_CONTROL_REG_CONTROL_LEN                  , 16  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM     , SH_FLD_CONTROL_LEN );
+
+REG64_FLD( PU_IOP0_PCS_M3_CONTROL_REG_CONTROL                      , 48  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM     , SH_FLD_CONTROL    );
+REG64_FLD( PU_IOP0_PCS_M3_CONTROL_REG_CONTROL_LEN                  , 16  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM     , SH_FLD_CONTROL_LEN );
+
+REG64_FLD( PU_IOP2_PCS_M3_CONTROL_REG_CONTROL                      , 48  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM     , SH_FLD_CONTROL    );
+REG64_FLD( PU_IOP2_PCS_M3_CONTROL_REG_CONTROL_LEN                  , 16  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM     , SH_FLD_CONTROL_LEN );
+
+REG64_FLD( PU_IOP1_PCS_M4_CONTROL_REG_CONTROL                      , 48  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM     , SH_FLD_CONTROL    );
+REG64_FLD( PU_IOP1_PCS_M4_CONTROL_REG_CONTROL_LEN                  , 16  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM     , SH_FLD_CONTROL_LEN );
+
+REG64_FLD( PU_IOP0_PCS_M4_CONTROL_REG_CONTROL                      , 48  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM     , SH_FLD_CONTROL    );
+REG64_FLD( PU_IOP0_PCS_M4_CONTROL_REG_CONTROL_LEN                  , 16  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM     , SH_FLD_CONTROL_LEN );
+
+REG64_FLD( PU_IOP2_PCS_M4_CONTROL_REG_CONTROL                      , 48  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM     , SH_FLD_CONTROL    );
+REG64_FLD( PU_IOP2_PCS_M4_CONTROL_REG_CONTROL_LEN                  , 16  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM     , SH_FLD_CONTROL_LEN );
+
+REG64_FLD( PU_IOP1_PCS_SYS_CONTROL_REG_CONTROL                     , 48  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM     , SH_FLD_CONTROL    );
+REG64_FLD( PU_IOP1_PCS_SYS_CONTROL_REG_CONTROL_LEN                 , 16  ,
+           SH_UNT_PU_IOP1  , SH_ACS_SCOM     , SH_FLD_CONTROL_LEN );
+
+REG64_FLD( PU_IOP0_PCS_SYS_CONTROL_REG_CONTROL                     , 48  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM     , SH_FLD_CONTROL    );
+REG64_FLD( PU_IOP0_PCS_SYS_CONTROL_REG_CONTROL_LEN                 , 16  ,
+           SH_UNT_PU_IOP0  , SH_ACS_SCOM     , SH_FLD_CONTROL_LEN );
+
+REG64_FLD( PU_IOP2_PCS_SYS_CONTROL_REG_CONTROL                     , 48  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM     , SH_FLD_CONTROL    );
+REG64_FLD( PU_IOP2_PCS_SYS_CONTROL_REG_CONTROL_LEN                 , 16  ,
+           SH_UNT_PU_IOP2  , SH_ACS_SCOM     , SH_FLD_CONTROL_LEN );
+
+REG64_FLD( PU_PBAIB1_PECAPP_CNTL_REG_PE_CAPP_EN                    , 0   ,
+           SH_UNT_PU_PBAIB1, SH_ACS_SCOM_RW  , SH_FLD_PE_CAPP_EN );
+REG64_FLD( PU_PBAIB1_PECAPP_CNTL_REG_PE_CAPP_DMA                   , 1   ,
+           SH_UNT_PU_PBAIB1, SH_ACS_SCOM_RW  , SH_FLD_PE_CAPP_DMA );
+REG64_FLD( PU_PBAIB1_PECAPP_CNTL_REG_PE_CAPP_256                   , 2   ,
+           SH_UNT_PU_PBAIB1, SH_ACS_SCOM_RW  , SH_FLD_PE_CAPP_256 );
+REG64_FLD( PU_PBAIB1_PECAPP_CNTL_REG_PE_CAPP_P8_MODE               , 3   ,
+           SH_UNT_PU_PBAIB1, SH_ACS_SCOM_RW  , SH_FLD_PE_CAPP_P8_MODE );
+
+REG64_FLD( PU_PBAIB2_PECAPP_CNTL_REG_PE_CAPP_EN                    , 0   ,
+           SH_UNT_PU_PBAIB2, SH_ACS_SCOM_RW  , SH_FLD_PE_CAPP_EN );
+REG64_FLD( PU_PBAIB2_PECAPP_CNTL_REG_PE_CAPP_DMA                   , 1   ,
+           SH_UNT_PU_PBAIB2, SH_ACS_SCOM_RW  , SH_FLD_PE_CAPP_DMA );
+REG64_FLD( PU_PBAIB2_PECAPP_CNTL_REG_PE_CAPP_256                   , 2   ,
+           SH_UNT_PU_PBAIB2, SH_ACS_SCOM_RW  , SH_FLD_PE_CAPP_256 );
+REG64_FLD( PU_PBAIB2_PECAPP_CNTL_REG_PE_CAPP_P8_MODE               , 3   ,
+           SH_UNT_PU_PBAIB2, SH_ACS_SCOM_RW  , SH_FLD_PE_CAPP_P8_MODE );
+
+REG64_FLD( PU_PBAIB0_PECAPP_CNTL_REG_PE_CAPP_EN                    , 0   ,
+           SH_UNT_PU_PBAIB0, SH_ACS_SCOM_RW  , SH_FLD_PE_CAPP_EN );
+REG64_FLD( PU_PBAIB0_PECAPP_CNTL_REG_PE_CAPP_DMA                   , 1   ,
+           SH_UNT_PU_PBAIB0, SH_ACS_SCOM_RW  , SH_FLD_PE_CAPP_DMA );
+REG64_FLD( PU_PBAIB0_PECAPP_CNTL_REG_PE_CAPP_256                   , 2   ,
+           SH_UNT_PU_PBAIB0, SH_ACS_SCOM_RW  , SH_FLD_PE_CAPP_256 );
+REG64_FLD( PU_PBAIB0_PECAPP_CNTL_REG_PE_CAPP_P8_MODE               , 3   ,
+           SH_UNT_PU_PBAIB0, SH_ACS_SCOM_RW  , SH_FLD_PE_CAPP_P8_MODE );
+
+REG64_FLD( PU_PBAIB1_PECAPP_SEC_BAR_PE_CAPP                        , 0   ,
+           SH_UNT_PU_PBAIB1, SH_ACS_SCOM     , SH_FLD_PE_CAPP    );
+REG64_FLD( PU_PBAIB1_PECAPP_SEC_BAR_PE_CAPP_LEN                    , 26  ,
+           SH_UNT_PU_PBAIB1, SH_ACS_SCOM     , SH_FLD_PE_CAPP_LEN );
+
+REG64_FLD( PU_PBAIB2_PECAPP_SEC_BAR_PE_CAPP                        , 0   ,
+           SH_UNT_PU_PBAIB2, SH_ACS_SCOM     , SH_FLD_PE_CAPP    );
+REG64_FLD( PU_PBAIB2_PECAPP_SEC_BAR_PE_CAPP_LEN                    , 26  ,
+           SH_UNT_PU_PBAIB2, SH_ACS_SCOM     , SH_FLD_PE_CAPP_LEN );
+
+REG64_FLD( PU_PBAIB0_PECAPP_SEC_BAR_PE_CAPP                        , 0   ,
+           SH_UNT_PU_PBAIB0, SH_ACS_SCOM     , SH_FLD_PE_CAPP    );
+REG64_FLD( PU_PBAIB0_PECAPP_SEC_BAR_PE_CAPP_LEN                    , 26  ,
+           SH_UNT_PU_PBAIB0, SH_ACS_SCOM     , SH_FLD_PE_CAPP_LEN );
+
+REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_RESERVED1                       , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_RESERVED1_LEN                   , 63  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_ACT                             , 63  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_RESERVED1                       , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_RESERVED1_LEN                   , 63  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_ACT                             , 63  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_RESERVED1                       , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_RESERVED1_LEN                   , 63  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_ACT                             , 63  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_RESERVED1                       , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_RESERVED1_LEN                   , 63  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_ACT                             , 63  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_RESERVED1                       , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_RESERVED1_LEN                   , 63  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_ACT                             , 63  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_RESERVED1                       , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_RESERVED1_LEN                   , 63  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_ACT                             , 63  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_RESERVED1                       , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_RESERVED1_LEN                   , 63  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_ACT                             , 63  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_RESERVED1                       , 0   ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_RESERVED1_LEN                   , 63  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_ACT                             , 63  ,
+           SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_RESERVED1                       , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_RESERVED1_LEN                   , 63  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_ACT                             , 63  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_RESERVED1                       , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_RESERVED1_LEN                   , 63  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_ACT                             , 63  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_RESERVED1                       , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_RESERVED1_LEN                   , 63  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_ACT                             , 63  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_RESERVED1                       , 0   ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_RESERVED1_LEN                   , 63  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_ACT                             , 63  ,
+           SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_RESERVED1                       , 0   ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_RESERVED1_LEN                   , 63  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_ACT                             , 63  ,
+           SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_RESERVED1                       , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_RESERVED1_LEN                   , 63  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_ACT                             , 63  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_RESERVED1                       , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_RESERVED1_LEN                   , 63  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_ACT                             , 63  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_ACT        );
+
+REG64_FLD( PEC_STACK2_PHBBAR_REG_PE_PHB_BAR                        , 0   ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM     , SH_FLD_PE_PHB_BAR );
+REG64_FLD( PEC_STACK2_PHBBAR_REG_PE_PHB_BAR_LEN                    , 42  ,
+           SH_UNT_PEC_STACK2, SH_ACS_SCOM     , SH_FLD_PE_PHB_BAR_LEN );
+
+REG64_FLD( PEC_STACK1_PHBBAR_REG_PE_PHB_BAR                        , 0   ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM     , SH_FLD_PE_PHB_BAR );
+REG64_FLD( PEC_STACK1_PHBBAR_REG_PE_PHB_BAR_LEN                    , 42  ,
+           SH_UNT_PEC_STACK1, SH_ACS_SCOM     , SH_FLD_PE_PHB_BAR_LEN );
+
+REG64_FLD( PEC_STACK0_PHBBAR_REG_PE_PHB_BAR                        , 0   ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM     , SH_FLD_PE_PHB_BAR );
+REG64_FLD( PEC_STACK0_PHBBAR_REG_PE_PHB_BAR_LEN                    , 42  ,
+           SH_UNT_PEC_STACK0, SH_ACS_SCOM     , SH_FLD_PE_PHB_BAR_LEN );
+
+REG64_FLD( PU_PBAIB_STACK7_PHBRESET_REG_PE_ETU_RESET               , 0   ,
+           SH_UNT_PU_PBAIB_STACK7, SH_ACS_SCOM_RW  , SH_FLD_PE_ETU_RESET );
+
+REG64_FLD( PU_PBAIB_STACK8_PHBRESET_REG_PE_ETU_RESET               , 0   ,
+           SH_UNT_PU_PBAIB_STACK8, SH_ACS_SCOM_RW  , SH_FLD_PE_ETU_RESET );
+
+REG64_FLD( PU_PBAIB_STACK5_PHBRESET_REG_PE_ETU_RESET               , 0   ,
+           SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RW  , SH_FLD_PE_ETU_RESET );
+
+REG64_FLD( PU_PBAIB_STACK4_PHBRESET_REG_PE_ETU_RESET               , 0   ,
+           SH_UNT_PU_PBAIB_STACK4, SH_ACS_SCOM_RW  , SH_FLD_PE_ETU_RESET );
+
+REG64_FLD( PU_PBAIB_STACK3_PHBRESET_REG_PE_ETU_RESET               , 0   ,
+           SH_UNT_PU_PBAIB_STACK3, SH_ACS_SCOM_RW  , SH_FLD_PE_ETU_RESET );
+
+REG64_FLD( PU_PBAIB_STACK0_PHBRESET_REG_PE_ETU_RESET               , 0   ,
+           SH_UNT_PU_PBAIB_STACK0, SH_ACS_SCOM_RW  , SH_FLD_PE_ETU_RESET );
+
+REG64_FLD( PU_PBAIB_STACK2_PHBRESET_REG_PE_ETU_RESET               , 0   ,
+           SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RW  , SH_FLD_PE_ETU_RESET );
+
+REG64_FLD( PU_PBAIB_STACK1_PHBRESET_REG_PE_ETU_RESET               , 0   ,
+           SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RW  , SH_FLD_PE_ETU_RESET );
+
+REG64_FLD( PU_PBAIB_STACK6_PHBRESET_REG_PE_ETU_RESET               , 0   ,
+           SH_UNT_PU_PBAIB_STACK6, SH_ACS_SCOM_RW  , SH_FLD_PE_ETU_RESET );
+
+REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM0_PHY_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_ADDR_LEN                     , 21  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM0_PHY_BAR_RESERVED2                           , 23  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM2_PHY_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_ADDR_LEN                     , 21  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM2_PHY_BAR_RESERVED2                           , 23  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM3_PHY_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_ADDR_LEN                     , 21  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM3_PHY_BAR_RESERVED2                           , 23  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM3_PHY_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_ADDR_LEN                     , 21  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM3_PHY_BAR_RESERVED2                           , 23  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM3_PHY_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_ADDR_LEN                     , 21  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM3_PHY_BAR_RESERVED2                           , 23  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM1_PHY_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_ADDR_LEN                     , 21  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM1_PHY_BAR_RESERVED2                           , 23  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM2_PHY_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_ADDR_LEN                     , 21  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM2_PHY_BAR_RESERVED2                           , 23  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM1_PHY_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_ADDR_LEN                     , 21  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM1_PHY_BAR_RESERVED2                           , 23  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM2_PHY_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_ADDR_LEN                     , 21  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM2_PHY_BAR_RESERVED2                           , 23  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM0_PHY_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_ADDR_LEN                     , 21  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM0_PHY_BAR_RESERVED2                           , 23  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM1_PHY_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_ADDR_LEN                     , 21  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM1_PHY_BAR_RESERVED2                           , 23  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_ENABLE                       , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM0_PHY_BAR_RESERVED1                           , 1   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_ADDR                         , 2   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_ADDR_LEN                     , 21  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM0_PHY_BAR_RESERVED2                           , 23  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_PIBMEM_ADDRESS_REGISTER_POINTER                      , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_POINTER    );
+REG64_FLD( PU_PIBMEM_ADDRESS_REGISTER_POINTER_LEN                  , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_POINTER_LEN );
+
+REG64_FLD( PU_PIBMEM_ADDRESS_REGISTER_FA_POINTER                   , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_POINTER    );
+REG64_FLD( PU_PIBMEM_ADDRESS_REGISTER_FA_POINTER_LEN               , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_POINTER_LEN );
+
+REG64_FLD( PU_PIBMEM_CONTROL_REGISTER_AUTO_PRE_INCREMENT_PIB       , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_AUTO_PRE_INCREMENT_PIB );
+REG64_FLD( PU_PIBMEM_CONTROL_REGISTER_AUTO_POST_DECREMENT_PIB      , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_AUTO_POST_DECREMENT_PIB );
+REG64_FLD( PU_PIBMEM_CONTROL_REGISTER_DISABLE_ECC                  , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_ECC );
+REG64_FLD( PU_PIBMEM_CONTROL_REGISTER_AUTO_PRE_INCREMENT_FACES     , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_AUTO_PRE_INCREMENT_FACES );
+REG64_FLD( PU_PIBMEM_CONTROL_REGISTER_AUTO_POST_DECREMENT_FACES    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_AUTO_POST_DECREMENT_FACES );
+
+REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_0_DATA                        , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DATA       );
+REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_0_DATA_LEN                    , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_1_DATA                        , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DATA       );
+REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_1_DATA_LEN                    , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_2_DATA                        , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DATA       );
+REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_2_DATA_LEN                    , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_PIBMEM_RESET_REGISTER_RESET                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESET      );
+REG64_FLD( PU_PIBMEM_RESET_REGISTER_RESET_LEN                      , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESET_LEN  );
+
+REG64_FLD( PU_PIBMEM_STATUS_REG_ADDR_INVALID_PIB                   , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADDR_INVALID_PIB );
+REG64_FLD( PU_PIBMEM_STATUS_REG_WRITE_INVALID_PIB                  , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WRITE_INVALID_PIB );
+REG64_FLD( PU_PIBMEM_STATUS_REG_READ_INVALID_PIB                   , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_READ_INVALID_PIB );
+REG64_FLD( PU_PIBMEM_STATUS_REG_ECC_UNCORRECTED_ERROR_PIB          , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_UNCORRECTED_ERROR_PIB );
+REG64_FLD( PU_PIBMEM_STATUS_REG_ECC_CORRECTED_ERROR_PIB            , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_CORRECTED_ERROR_PIB );
+REG64_FLD( PU_PIBMEM_STATUS_REG_WRITE_RST_INTERRUPT_PIB            , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WRITE_RST_INTERRUPT_PIB );
+REG64_FLD( PU_PIBMEM_STATUS_REG_READ_RST_INTERRUPT_PIB             , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_READ_RST_INTERRUPT_PIB );
+REG64_FLD( PU_PIBMEM_STATUS_REG_FSM_PRESENT_STATE                  , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FSM_PRESENT_STATE );
+REG64_FLD( PU_PIBMEM_STATUS_REG_FSM_PRESENT_STATE_LEN              , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FSM_PRESENT_STATE_LEN );
+REG64_FLD( PU_PIBMEM_STATUS_REG_ADDR_INVALID_FACES                 , 19  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADDR_INVALID_FACES );
+REG64_FLD( PU_PIBMEM_STATUS_REG_WRITE_INVALID_FACES                , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WRITE_INVALID_FACES );
+REG64_FLD( PU_PIBMEM_STATUS_REG_READ_INVALID_FACES                 , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_READ_INVALID_FACES );
+REG64_FLD( PU_PIBMEM_STATUS_REG_ECC_UNCORRECTED_ERROR_FACES        , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_UNCORRECTED_ERROR_FACES );
+REG64_FLD( PU_PIBMEM_STATUS_REG_ECC_CORRECTED_ERROR_FACES          , 23  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_CORRECTED_ERROR_FACES );
+REG64_FLD( PU_PIBMEM_STATUS_REG_BAD_ARRAY_ADDRESS_FACES            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BAD_ARRAY_ADDRESS_FACES );
+REG64_FLD( PU_PIBMEM_STATUS_REG_WRITE_RST_INTERRUPT_FACES          , 25  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WRITE_RST_INTERRUPT_FACES );
+REG64_FLD( PU_PIBMEM_STATUS_REG_READ_RST_INTERRUPT_FACES           , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_READ_RST_INTERRUPT_FACES );
+REG64_FLD( PU_PIBMEM_STATUS_REG_ADDR_RESET_INTR_PIB                , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADDR_RESET_INTR_PIB );
+REG64_FLD( PU_PIBMEM_STATUS_REG_ADDR_RESET_INTR_PIB_LEN            , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADDR_RESET_INTR_PIB_LEN );
+REG64_FLD( PU_PIBMEM_STATUS_REG_ADDR_RESET_INTR_FACES              , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADDR_RESET_INTR_FACES );
+REG64_FLD( PU_PIBMEM_STATUS_REG_ADDR_RESET_INTR_FACES_LEN          , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADDR_RESET_INTR_FACES_LEN );
+
+REG64_FLD( PU_PIB_CMD_REG_RNW                                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RNW        );
+REG64_FLD( PU_PIB_CMD_REG_ADR                                      , 30  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADR        );
+REG64_FLD( PU_PIB_CMD_REG_ADR_LEN                                  , 31  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADR_LEN    );
+
+REG64_FLD( PU_PIB_DATA_REG_DATA                                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_PIB_DATA_REG_DATA_LEN                                , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_PIB_RESET_REG_RESET                                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESET      );
+REG64_FLD( PU_PIB_RESET_REG_STATE                                  , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STATE      );
+REG64_FLD( PU_PIB_RESET_REG_ABORTED_CMD                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ABORTED_CMD );
+
+REG64_FLD( PEC_PMONCTL_REG_PE_PERFMON_EN                           , 0   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_PERFMON_EN );
+REG64_FLD( PEC_PMONCTL_REG_PE_PERFMON_EN_LEN                       , 32  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_PERFMON_EN_LEN );
+REG64_FLD( PEC_PMONCTL_REG_PE_PERFMON_READ_TYPE                    , 32  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_PERFMON_READ_TYPE );
+REG64_FLD( PEC_PMONCTL_REG_PE_PERFMON_READ_TYPE_LEN                , 2   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_PERFMON_READ_TYPE_LEN );
+REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE0                       , 36  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_PMON_MUX_BYTE0 );
+REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE0_LEN                   , 4   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_PMON_MUX_BYTE0_LEN );
+REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE1                       , 40  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_PMON_MUX_BYTE1 );
+REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE1_LEN                   , 4   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_PMON_MUX_BYTE1_LEN );
+REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE2                       , 44  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_PMON_MUX_BYTE2 );
+REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE2_LEN                   , 4   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_PMON_MUX_BYTE2_LEN );
+REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE3                       , 48  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_PMON_MUX_BYTE3 );
+REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE3_LEN                   , 4   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_PMON_MUX_BYTE3_LEN );
+
+REG64_FLD( PU_PMU_CONTROL_2_MUX_SELECT                             , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MUX_SELECT );
+REG64_FLD( PU_PMU_CONTROL_2_MUX_SELECT_LEN                         , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MUX_SELECT_LEN );
+
+REG64_FLD( PU_GPE2_PPE_XIDBGPRO_NULL_MSR_SIBRC                     , 9   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE2_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN                 , 3   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE2_PPE_XIDBGPRO_NULL_MSR_WE                        , 14  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE2_PPE_XIDBGPRO_NULL_MSR_LP                        , 20  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_LP );
+
+REG64_FLD( PU_GPE1_PPE_XIDBGPRO_NULL_MSR_SIBRC                     , 9   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE1_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN                 , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE1_PPE_XIDBGPRO_NULL_MSR_WE                        , 14  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE1_PPE_XIDBGPRO_NULL_MSR_LP                        , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_LP );
+
+REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_SIBRC                          , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN                      , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_WE                             , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_LP                             , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NULL_MSR_LP );
+
+REG64_FLD( PU_GPE3_PPE_XIDBGPRO_NULL_MSR_SIBRC                     , 9   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE3_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN                 , 3   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE3_PPE_XIDBGPRO_NULL_MSR_WE                        , 14  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE3_PPE_XIDBGPRO_NULL_MSR_LP                        , 20  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_LP );
+
+REG64_FLD( PU_GPE0_PPE_XIDBGPRO_NULL_MSR_SIBRC                     , 9   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE0_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN                 , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE0_PPE_XIDBGPRO_NULL_MSR_WE                        , 14  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE0_PPE_XIDBGPRO_NULL_MSR_LP                        , 20  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_LP );
+
+REG64_FLD( PU_GPE2_PPE_XIRAMDBG_NULL_MSR_SIBRC                     , 9   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE2_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN                 , 3   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE2_PPE_XIRAMDBG_NULL_MSR_WE                        , 14  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE2_PPE_XIRAMDBG_NULL_MSR_LP                        , 20  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_LP );
+REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XIRAMRA_SPRG0                      , 32  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM     , SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN                  , 32  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM     , SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE1_PPE_XIRAMDBG_NULL_MSR_SIBRC                     , 9   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE1_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN                 , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE1_PPE_XIRAMDBG_NULL_MSR_WE                        , 14  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE1_PPE_XIRAMDBG_NULL_MSR_LP                        , 20  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_LP );
+REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XIRAMRA_SPRG0                      , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM     , SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN                  , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM     , SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_PPE_XIRAMDBG_NULL_MSR_SIBRC                          , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN                      , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_PPE_XIRAMDBG_NULL_MSR_WE                             , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_PPE_XIRAMDBG_NULL_MSR_LP                             , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NULL_MSR_LP );
+REG64_FLD( PU_PPE_XIRAMDBG_XIRAMRA_SPRG0                           , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( PU_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN                       , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE3_PPE_XIRAMDBG_NULL_MSR_SIBRC                     , 9   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE3_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN                 , 3   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE3_PPE_XIRAMDBG_NULL_MSR_WE                        , 14  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE3_PPE_XIRAMDBG_NULL_MSR_LP                        , 20  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_LP );
+REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XIRAMRA_SPRG0                      , 32  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM     , SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN                  , 32  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM     , SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE0_PPE_XIRAMDBG_NULL_MSR_SIBRC                     , 9   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE0_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN                 , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE0_PPE_XIRAMDBG_NULL_MSR_WE                        , 14  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE0_PPE_XIRAMDBG_NULL_MSR_LP                        , 20  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM     , SH_FLD_NULL_MSR_LP );
+REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XIRAMRA_SPRG0                      , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM     , SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN                  , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM     , SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE2_PPE_XIRAMEDR_XIRAMGA_IR                         , 0   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM     , SH_FLD_XIRAMGA_IR );
+REG64_FLD( PU_GPE2_PPE_XIRAMEDR_XIRAMGA_IR_LEN                     , 32  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM     , SH_FLD_XIRAMGA_IR_LEN );
+REG64_FLD( PU_GPE2_PPE_XIRAMEDR_EDR                                , 32  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM     , SH_FLD_EDR        );
+REG64_FLD( PU_GPE2_PPE_XIRAMEDR_EDR_LEN                            , 32  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM     , SH_FLD_EDR_LEN    );
+
+REG64_FLD( PU_GPE1_PPE_XIRAMEDR_XIRAMGA_IR                         , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM     , SH_FLD_XIRAMGA_IR );
+REG64_FLD( PU_GPE1_PPE_XIRAMEDR_XIRAMGA_IR_LEN                     , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM     , SH_FLD_XIRAMGA_IR_LEN );
+REG64_FLD( PU_GPE1_PPE_XIRAMEDR_EDR                                , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM     , SH_FLD_EDR        );
+REG64_FLD( PU_GPE1_PPE_XIRAMEDR_EDR_LEN                            , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM     , SH_FLD_EDR_LEN    );
+
+REG64_FLD( PU_PPE_XIRAMEDR_XIRAMGA_IR                              , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_XIRAMGA_IR );
+REG64_FLD( PU_PPE_XIRAMEDR_XIRAMGA_IR_LEN                          , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_XIRAMGA_IR_LEN );
+REG64_FLD( PU_PPE_XIRAMEDR_EDR                                     , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_EDR        );
+REG64_FLD( PU_PPE_XIRAMEDR_EDR_LEN                                 , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_EDR_LEN    );
+
+REG64_FLD( PU_GPE3_PPE_XIRAMEDR_XIRAMGA_IR                         , 0   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM     , SH_FLD_XIRAMGA_IR );
+REG64_FLD( PU_GPE3_PPE_XIRAMEDR_XIRAMGA_IR_LEN                     , 32  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM     , SH_FLD_XIRAMGA_IR_LEN );
+REG64_FLD( PU_GPE3_PPE_XIRAMEDR_EDR                                , 32  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM     , SH_FLD_EDR        );
+REG64_FLD( PU_GPE3_PPE_XIRAMEDR_EDR_LEN                            , 32  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM     , SH_FLD_EDR_LEN    );
+
+REG64_FLD( PU_GPE0_PPE_XIRAMEDR_XIRAMGA_IR                         , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM     , SH_FLD_XIRAMGA_IR );
+REG64_FLD( PU_GPE0_PPE_XIRAMEDR_XIRAMGA_IR_LEN                     , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM     , SH_FLD_XIRAMGA_IR_LEN );
+REG64_FLD( PU_GPE0_PPE_XIRAMEDR_EDR                                , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM     , SH_FLD_EDR        );
+REG64_FLD( PU_GPE0_PPE_XIRAMEDR_EDR_LEN                            , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM     , SH_FLD_EDR_LEN    );
+
+REG64_FLD( PU_GPE2_PPE_XIRAMGA_IR                                  , 0   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_WO  , SH_FLD_IR         );
+REG64_FLD( PU_GPE2_PPE_XIRAMGA_IR_LEN                              , 32  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_WO  , SH_FLD_IR_LEN     );
+REG64_FLD( PU_GPE2_PPE_XIRAMGA_XIRAMRA_SPRG0                       , 32  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_WO  , SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE2_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN                   , 32  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_WO  , SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE1_PPE_XIRAMGA_IR                                  , 0   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_WO  , SH_FLD_IR         );
+REG64_FLD( PU_GPE1_PPE_XIRAMGA_IR_LEN                              , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_WO  , SH_FLD_IR_LEN     );
+REG64_FLD( PU_GPE1_PPE_XIRAMGA_XIRAMRA_SPRG0                       , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_WO  , SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE1_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN                   , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_WO  , SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_PPE_XIRAMGA_IR                                       , 0   ,
+           SH_UNT          , SH_ACS_SCOM_WO  , SH_FLD_IR         );
+REG64_FLD( PU_PPE_XIRAMGA_IR_LEN                                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM_WO  , SH_FLD_IR_LEN     );
+REG64_FLD( PU_PPE_XIRAMGA_XIRAMRA_SPRG0                            , 32  ,
+           SH_UNT          , SH_ACS_SCOM_WO  , SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( PU_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN                        , 32  ,
+           SH_UNT          , SH_ACS_SCOM_WO  , SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE3_PPE_XIRAMGA_IR                                  , 0   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_WO  , SH_FLD_IR         );
+REG64_FLD( PU_GPE3_PPE_XIRAMGA_IR_LEN                              , 32  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_WO  , SH_FLD_IR_LEN     );
+REG64_FLD( PU_GPE3_PPE_XIRAMGA_XIRAMRA_SPRG0                       , 32  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_WO  , SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE3_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN                   , 32  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_WO  , SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE0_PPE_XIRAMGA_IR                                  , 0   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_WO  , SH_FLD_IR         );
+REG64_FLD( PU_GPE0_PPE_XIRAMGA_IR_LEN                              , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_WO  , SH_FLD_IR_LEN     );
+REG64_FLD( PU_GPE0_PPE_XIRAMGA_XIRAMRA_SPRG0                       , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_WO  , SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE0_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN                   , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_WO  , SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE2_PPE_XIRAMRA_XIXCR_XCR                           , 1   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_WO  , SH_FLD_XIXCR_XCR  );
+REG64_FLD( PU_GPE2_PPE_XIRAMRA_XIXCR_XCR_LEN                       , 3   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_WO  , SH_FLD_XIXCR_XCR_LEN );
+REG64_FLD( PU_GPE2_PPE_XIRAMRA_SPRG0                               , 32  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_WO  , SH_FLD_SPRG0      );
+REG64_FLD( PU_GPE2_PPE_XIRAMRA_SPRG0_LEN                           , 32  ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_WO  , SH_FLD_SPRG0_LEN  );
+
+REG64_FLD( PU_GPE1_PPE_XIRAMRA_XIXCR_XCR                           , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_WO  , SH_FLD_XIXCR_XCR  );
+REG64_FLD( PU_GPE1_PPE_XIRAMRA_XIXCR_XCR_LEN                       , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_WO  , SH_FLD_XIXCR_XCR_LEN );
+REG64_FLD( PU_GPE1_PPE_XIRAMRA_SPRG0                               , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_WO  , SH_FLD_SPRG0      );
+REG64_FLD( PU_GPE1_PPE_XIRAMRA_SPRG0_LEN                           , 32  ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_WO  , SH_FLD_SPRG0_LEN  );
+
+REG64_FLD( PU_PPE_XIRAMRA_XIXCR_XCR                                , 1   ,
+           SH_UNT          , SH_ACS_SCOM_WO  , SH_FLD_XIXCR_XCR  );
+REG64_FLD( PU_PPE_XIRAMRA_XIXCR_XCR_LEN                            , 3   ,
+           SH_UNT          , SH_ACS_SCOM_WO  , SH_FLD_XIXCR_XCR_LEN );
+REG64_FLD( PU_PPE_XIRAMRA_SPRG0                                    , 32  ,
+           SH_UNT          , SH_ACS_SCOM_WO  , SH_FLD_SPRG0      );
+REG64_FLD( PU_PPE_XIRAMRA_SPRG0_LEN                                , 32  ,
+           SH_UNT          , SH_ACS_SCOM_WO  , SH_FLD_SPRG0_LEN  );
+
+REG64_FLD( PU_GPE3_PPE_XIRAMRA_XIXCR_XCR                           , 1   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_WO  , SH_FLD_XIXCR_XCR  );
+REG64_FLD( PU_GPE3_PPE_XIRAMRA_XIXCR_XCR_LEN                       , 3   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_WO  , SH_FLD_XIXCR_XCR_LEN );
+REG64_FLD( PU_GPE3_PPE_XIRAMRA_SPRG0                               , 32  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_WO  , SH_FLD_SPRG0      );
+REG64_FLD( PU_GPE3_PPE_XIRAMRA_SPRG0_LEN                           , 32  ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_WO  , SH_FLD_SPRG0_LEN  );
+
+REG64_FLD( PU_GPE0_PPE_XIRAMRA_XIXCR_XCR                           , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_WO  , SH_FLD_XIXCR_XCR  );
+REG64_FLD( PU_GPE0_PPE_XIRAMRA_XIXCR_XCR_LEN                       , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_WO  , SH_FLD_XIXCR_XCR_LEN );
+REG64_FLD( PU_GPE0_PPE_XIRAMRA_SPRG0                               , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_WO  , SH_FLD_SPRG0      );
+REG64_FLD( PU_GPE0_PPE_XIRAMRA_SPRG0_LEN                           , 32  ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_WO  , SH_FLD_SPRG0_LEN  );
+
+REG64_FLD( PU_GPE2_PPE_XIXCR_XCR                                   , 1   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_WO  , SH_FLD_XCR        );
+REG64_FLD( PU_GPE2_PPE_XIXCR_XCR_LEN                               , 3   ,
+           SH_UNT_PU_GPE2  , SH_ACS_SCOM_WO  , SH_FLD_XCR_LEN    );
+
+REG64_FLD( PU_GPE1_PPE_XIXCR_XCR                                   , 1   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_WO  , SH_FLD_XCR        );
+REG64_FLD( PU_GPE1_PPE_XIXCR_XCR_LEN                               , 3   ,
+           SH_UNT_PU_GPE1  , SH_ACS_SCOM_WO  , SH_FLD_XCR_LEN    );
+
+REG64_FLD( PU_PPE_XIXCR_XCR                                        , 1   ,
+           SH_UNT          , SH_ACS_SCOM_WO  , SH_FLD_XCR        );
+REG64_FLD( PU_PPE_XIXCR_XCR_LEN                                    , 3   ,
+           SH_UNT          , SH_ACS_SCOM_WO  , SH_FLD_XCR_LEN    );
+
+REG64_FLD( PU_GPE3_PPE_XIXCR_XCR                                   , 1   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_WO  , SH_FLD_XCR        );
+REG64_FLD( PU_GPE3_PPE_XIXCR_XCR_LEN                               , 3   ,
+           SH_UNT_PU_GPE3  , SH_ACS_SCOM_WO  , SH_FLD_XCR_LEN    );
+
+REG64_FLD( PU_GPE0_PPE_XIXCR_XCR                                   , 1   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_WO  , SH_FLD_XCR        );
+REG64_FLD( PU_GPE0_PPE_XIXCR_XCR_LEN                               , 3   ,
+           SH_UNT_PU_GPE0  , SH_ACS_SCOM_WO  , SH_FLD_XCR_LEN    );
+
+REG64_FLD( PEC_PREDV_REG_PE_RD_TIMEOUT_MASK                        , 0   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_RD_TIMEOUT_MASK );
+REG64_FLD( PEC_PREDV_REG_PE_RD_TIMEOUT_MASK_LEN                    , 8   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_RD_TIMEOUT_MASK_LEN );
+REG64_FLD( PEC_PREDV_REG_PE_WR_TIMEOUT_MASK                        , 8   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_WR_TIMEOUT_MASK );
+REG64_FLD( PEC_PREDV_REG_PE_WR_TIMEOUT_MASK_LEN                    , 8   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_WR_TIMEOUT_MASK_LEN );
+
+REG64_FLD( PU_PRGM_REGISTER_PRGM_ADDR                              , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRGM_ADDR  );
+REG64_FLD( PU_PRGM_REGISTER_PRGM_ADDR_LEN                          , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRGM_ADDR_LEN );
+REG64_FLD( PU_PRGM_REGISTER_PRG_BIT_LOCATION                       , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRG_BIT_LOCATION );
+REG64_FLD( PU_PRGM_REGISTER_PRG_BIT_LOCATION_LEN                   , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRG_BIT_LOCATION_LEN );
+
+REG64_FLD( PU_PROBE_PROTECT_STATUS_BITS                            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BITS       );
+REG64_FLD( PU_PROBE_PROTECT_STATUS_BITS_LEN                        , 42  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2FSP_INJ_ERR_BITS               , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIHB2FSP_INJ_ERR_BITS );
+REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2FSP_INJ_ERR_BITS_LEN           , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIHB2FSP_INJ_ERR_BITS_LEN );
+REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2FSP_INJ_ONCE                   , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIHB2FSP_INJ_ONCE );
+REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2FSP_INJ_CONST                  , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIHB2FSP_INJ_CONST );
+REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2PB_INJ_ERR_BITS                , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIHB2PB_INJ_ERR_BITS );
+REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2PB_INJ_ERR_BITS_LEN            , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIHB2PB_INJ_ERR_BITS_LEN );
+REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2PB_INJ_ONCE                    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIHB2PB_INJ_ONCE );
+REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2PB_INJ_CONST                   , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIHB2PB_INJ_CONST );
+REG64_FLD( PU_PSIHB_DEBUG_REG_TRACE_SEL                            , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRACE_SEL  );
+REG64_FLD( PU_PSIHB_DEBUG_REG_TRACE_SEL_LEN                        , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRACE_SEL_LEN );
+
+REG64_FLD( PU_PSIHB_ERROR_MASK_REG_DISABLE_1                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_1  );
+REG64_FLD( PU_PSIHB_ERROR_MASK_REG_DISABLE_1_LEN                   , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_1_LEN );
+REG64_FLD( PU_PSIHB_ERROR_MASK_REG_INTERRUPT_DISABLE               , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INTERRUPT_DISABLE );
+REG64_FLD( PU_PSIHB_ERROR_MASK_REG_INTERRUPT_DISABLE_LEN           , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INTERRUPT_DISABLE_LEN );
+REG64_FLD( PU_PSIHB_ERROR_MASK_REG_DISABLE_2                       , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_2  );
+REG64_FLD( PU_PSIHB_ERROR_MASK_REG_DISABLE_2_LEN                   , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_2_LEN );
+
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_PB_ECC_ERR_CE                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PB_ECC_ERR_CE );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_PB_ECC_ERR_UE                  , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PB_ECC_ERR_UE );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_PB_ECC_ERR_SUE                 , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PB_ECC_ERR_SUE );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT_FROM_ERROR           , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INTERRUPT_FROM_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT_FROM_FSP             , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INTERRUPT_FROM_FSP );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_FSP_ECC_ERR_CE                 , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_FSP_ECC_ERR_CE );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_FSP_ECC_ERR_UE                 , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_FSP_ECC_ERR_UE );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_ERROR_STATE                    , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ERROR_STATE );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INVALID_TTYPE                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INVALID_TTYPE );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INVALID_CRESP                  , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INVALID_CRESP );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_PB_DATA_TIME_OUT               , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PB_DATA_TIME_OUT );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_PB_PARITY_ERROR                , 11  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PB_PARITY_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_FSP_ACCESS_TRUSTED_SPACE       , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_FSP_ACCESS_TRUSTED_SPACE );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_UNEXPECTED_PB                  , 13  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UNEXPECTED_PB );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT_CHANGE_WHILE_ACTIVE  , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INTERRUPT_CHANGE_WHILE_ACTIVE );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT0_ADDRESS_ERROR       , 15  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INTERRUPT0_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT1_ADDRESS_ERROR       , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INTERRUPT1_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT2_ADDRESS_ERROR       , 17  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INTERRUPT2_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT3_ADDRESS_ERROR       , 18  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INTERRUPT3_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT4_ADDRESS_ERROR       , 19  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INTERRUPT4_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT5_ADDRESS_ERROR       , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INTERRUPT5_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_TCBR_TP_PSI_GLB_ERR_0          , 21  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_TCBR_TP_PSI_GLB_ERR_0 );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_TCBR_TP_PSI_GLB_ERR_1          , 22  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_TCBR_TP_PSI_GLB_ERR_1 );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_UPSTREAM                       , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UPSTREAM   );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_SPARE                          , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SPARE      );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_SPARE_LEN                      , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_SCOM_ERROR                     , 27  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SCOM_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_PARITY_ERROR                   , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PARITY_ERROR );
+
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_PB_ECC_ERR_CE                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PB_ECC_ERR_CE );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_PB_ECC_ERR_UE                  , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PB_ECC_ERR_UE );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_PB_ECC_ERR_SUE                 , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PB_ECC_ERR_SUE );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT_FROM_ERROR           , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INTERRUPT_FROM_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT_FROM_FSP             , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INTERRUPT_FROM_FSP );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_FSP_ECC_ERR_CE                 , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_FSP_ECC_ERR_CE );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_FSP_ECC_ERR_UE                 , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_FSP_ECC_ERR_UE );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_ERROR_STATE                    , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ERROR_STATE );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INVALID_TTYPE                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INVALID_TTYPE );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INVALID_CRESP                  , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INVALID_CRESP );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_PB_DATA_TIME_OUT               , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PB_DATA_TIME_OUT );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_PB_PARITY_ERROR                , 11  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PB_PARITY_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_FSP_ACCESS_TRUSTED_SPACE       , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_FSP_ACCESS_TRUSTED_SPACE );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_UNEXPECTED_PB                  , 13  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UNEXPECTED_PB );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT_CHANGE_WHILE_ACTIVE  , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INTERRUPT_CHANGE_WHILE_ACTIVE );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT0_ADDRESS_ERROR       , 15  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INTERRUPT0_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT1_ADDRESS_ERROR       , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INTERRUPT1_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT2_ADDRESS_ERROR       , 17  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INTERRUPT2_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT3_ADDRESS_ERROR       , 18  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INTERRUPT3_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT4_ADDRESS_ERROR       , 19  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INTERRUPT4_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT5_ADDRESS_ERROR       , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INTERRUPT5_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_TCBR_TP_PSI_GLB_ERR_0          , 21  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_TCBR_TP_PSI_GLB_ERR_0 );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_TCBR_TP_PSI_GLB_ERR_1          , 22  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_TCBR_TP_PSI_GLB_ERR_1 );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_UPSTREAM                       , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_UPSTREAM   );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_SPARE                          , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SPARE      );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_SPARE_LEN                      , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_SCOM_ERROR                     , 27  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SCOM_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_PARITY_ERROR                   , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PARITY_ERROR );
+
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_PB_ECC_ERR_CE                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_ECC_ERR_CE );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_PB_ECC_ERR_UE                     , 1   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_ECC_ERR_UE );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_PB_ECC_ERR_SUE                    , 2   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_ECC_ERR_SUE );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT_FROM_ERROR              , 3   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_FROM_ERROR );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT_FROM_FSP                , 4   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_FROM_FSP );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_FSP_ECC_ERR_CE                    , 5   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FSP_ECC_ERR_CE );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_FSP_ECC_ERR_UE                    , 6   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FSP_ECC_ERR_UE );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_ERROR_STATE                       , 7   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_ERROR_STATE );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_INVALID_TTYPE                     , 8   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INVALID_TTYPE );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_INVALID_CRESP                     , 9   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INVALID_CRESP );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_PB_DATA_TIME_OUT                  , 10  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_DATA_TIME_OUT );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_PB_PARITY_ERROR                   , 11  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_PARITY_ERROR );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_FSP_ACCESS_TRUSTED_SPACE          , 12  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FSP_ACCESS_TRUSTED_SPACE );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_UNEXPECTED_PB                     , 13  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UNEXPECTED_PB );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT_CHANGE_WHILE_ACTIVE     , 14  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_CHANGE_WHILE_ACTIVE );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT0_ADDRESS_ERROR          , 15  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT0_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT1_ADDRESS_ERROR          , 16  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT1_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT2_ADDRESS_ERROR          , 17  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT2_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT3_ADDRESS_ERROR          , 18  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT3_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT4_ADDRESS_ERROR          , 19  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT4_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT5_ADDRESS_ERROR          , 20  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT5_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_TCBR_TP_PSI_GLB_ERR_0             , 21  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_TCBR_TP_PSI_GLB_ERR_0 );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_TCBR_TP_PSI_GLB_ERR_1             , 22  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_TCBR_TP_PSI_GLB_ERR_1 );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_UPSTREAM                          , 23  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UPSTREAM   );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_SPARE                             , 24  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_SPARE      );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_SPARE_LEN                         , 3   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_SCOM_ERROR                        , 27  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERROR );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_PARITY_ERROR                      , 28  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERROR );
+
+REG64_FLD( PU_PSIHB_FIR_REG_PB_ECC_ERR_CE                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_ECC_ERR_CE );
+REG64_FLD( PU_PSIHB_FIR_REG_PB_ECC_ERR_UE                          , 1   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_ECC_ERR_UE );
+REG64_FLD( PU_PSIHB_FIR_REG_PB_ECC_ERR_SUE                         , 2   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_ECC_ERR_SUE );
+REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT_FROM_ERROR                   , 3   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_FROM_ERROR );
+REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT_FROM_FSP                     , 4   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_FROM_FSP );
+REG64_FLD( PU_PSIHB_FIR_REG_FSP_ECC_ERR_CE                         , 5   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FSP_ECC_ERR_CE );
+REG64_FLD( PU_PSIHB_FIR_REG_FSP_ECC_ERR_UE                         , 6   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FSP_ECC_ERR_UE );
+REG64_FLD( PU_PSIHB_FIR_REG_ERROR_STATE                            , 7   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_ERROR_STATE );
+REG64_FLD( PU_PSIHB_FIR_REG_INVALID_TTYPE                          , 8   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INVALID_TTYPE );
+REG64_FLD( PU_PSIHB_FIR_REG_INVALID_CRESP                          , 9   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INVALID_CRESP );
+REG64_FLD( PU_PSIHB_FIR_REG_PB_DATA_TIME_OUT                       , 10  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_DATA_TIME_OUT );
+REG64_FLD( PU_PSIHB_FIR_REG_PB_PARITY_ERROR                        , 11  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PB_PARITY_ERROR );
+REG64_FLD( PU_PSIHB_FIR_REG_FSP_ACCESS_TRUSTED_SPACE               , 12  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FSP_ACCESS_TRUSTED_SPACE );
+REG64_FLD( PU_PSIHB_FIR_REG_UNEXPECTED_PB                          , 13  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UNEXPECTED_PB );
+REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT_CHANGE_WHILE_ACTIVE          , 14  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_CHANGE_WHILE_ACTIVE );
+REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT0_ADDRESS_ERROR               , 15  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT0_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT1_ADDRESS_ERROR               , 16  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT1_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT2_ADDRESS_ERROR               , 17  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT2_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT3_ADDRESS_ERROR               , 18  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT3_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT4_ADDRESS_ERROR               , 19  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT4_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT5_ADDRESS_ERROR               , 20  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT5_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_REG_TCBR_TP_PSI_GLB_ERR_0                  , 21  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_TCBR_TP_PSI_GLB_ERR_0 );
+REG64_FLD( PU_PSIHB_FIR_REG_TCBR_TP_PSI_GLB_ERR_1                  , 22  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_TCBR_TP_PSI_GLB_ERR_1 );
+REG64_FLD( PU_PSIHB_FIR_REG_UPSTREAM                               , 23  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_UPSTREAM   );
+REG64_FLD( PU_PSIHB_FIR_REG_SPARE                                  , 24  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_SPARE      );
+REG64_FLD( PU_PSIHB_FIR_REG_SPARE_LEN                              , 3   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_PSIHB_FIR_REG_SCOM_ERROR                             , 27  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERROR );
+REG64_FLD( PU_PSIHB_FIR_REG_PARITY_ERROR                           , 28  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERROR );
+
+REG64_FLD( PU_PSIHB_INTERRUPT_CONTROL_ESB_OR_LSI_INTERRUPTS        , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ESB_OR_LSI_INTERRUPTS );
+REG64_FLD( PU_PSIHB_INTERRUPT_CONTROL_SM_RESET                     , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SM_RESET   );
+
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_CMD_ENABLE                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_FSP_CMD_ENABLE );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_MMIO_ENABLE                 , 1   ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_FSP_MMIO_ENABLE );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PHBCSR_SPARE                    , 2   ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_PHBCSR_SPARE );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_INT_ENABLE                  , 3   ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_FSP_INT_ENABLE );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_ERR_RSP_ENABLE              , 4   ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_FSP_ERR_RSP_ENABLE );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSI_LINK_ENABLE                 , 5   ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_PSI_LINK_ENABLE );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_RESET                       , 6   ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_FSP_RESET  );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIHBC_RESET                    , 7   ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_PSIHBC_RESET );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_MMIO_MASK                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_FSP_MMIO_MASK );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_MMIO_MASK_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_FSP_MMIO_MASK_LEN );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_CEC_PSI_INTERRUPT               , 16  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_CEC_PSI_INTERRUPT );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_INTERRUPT                   , 17  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_FSP_INTERRUPT );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_LINK_ACTIVE                 , 18  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_FSP_LINK_ACTIVE );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_OUTBOUND_ACTIVE             , 19  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_FSP_OUTBOUND_ACTIVE );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_INBOUND_ACTIVE              , 20  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_FSP_INBOUND_ACTIVE );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_LOAD_OUTSTANDING         , 21  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_PSIFSP_LOAD_OUTSTANDING );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_DMAR_OUTSTANDING         , 22  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_PSIFSP_DMAR_OUTSTANDING );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_INT_BUSY                 , 23  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_PSIFSP_INT_BUSY );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSI_XMIT_ERROR                  , 32  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_PSI_XMIT_ERROR );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSI_LINK_INACTIVE_TRANS         , 33  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_PSI_LINK_INACTIVE_TRANS );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_ACK_TIMEOUT              , 34  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_PSIFSP_ACK_TIMEOUT );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_MMIO_LOAD_TIMEOUT        , 35  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_PSIFSP_MMIO_LOAD_TIMEOUT );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_MMIO_LENGTH_ERR          , 36  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_PSIFSP_MMIO_LENGTH_ERR );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_MMIO_ADDR_ERR            , 37  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_PSIFSP_MMIO_ADDR_ERR );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_MMIO_TYPE_ERR            , 38  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_PSIFSP_MMIO_TYPE_ERR );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSI_UE                          , 39  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_PSI_UE     );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_PERR                     , 40  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_PSIFSP_PERR );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSI_ALERT1                      , 41  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_PSI_ALERT1 );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSI_ALERT2                      , 42  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_PSI_ALERT2 );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_DMA_ERR                  , 43  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_PSIFSP_DMA_ERR );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_DMA_ADDR_ERR             , 48  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_PSIFSP_DMA_ADDR_ERR );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_TCE_EXTENT_ERR           , 49  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_PSIFSP_TCE_EXTENT_ERR );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_PAGE_FAULT               , 50  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_PSIFSP_PAGE_FAULT );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_INV_OP                   , 51  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_PSIFSP_INV_OP );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_INV_READ                    , 52  ,
+           SH_UNT          , SH_ACS_SCOM2    , SH_FLD_FSP_INV_READ );
+
+REG64_FLD( PU_PSI_BRIDGE_BAR_REG_BAR                               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BAR        );
+REG64_FLD( PU_PSI_BRIDGE_BAR_REG_BAR_LEN                           , 36  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BAR_LEN    );
+REG64_FLD( PU_PSI_BRIDGE_BAR_REG_EN                                , 63  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_EN         );
+
+REG64_FLD( PU_PSI_BRIDGE_FSP_BAR_REG_BAR                           , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BAR        );
+REG64_FLD( PU_PSI_BRIDGE_FSP_BAR_REG_BAR_LEN                       , 36  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BAR_LEN    );
+
+REG64_FLD( PU_PSI_FSP_MMR_REG_MMR                                  , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MMR        );
+REG64_FLD( PU_PSI_FSP_MMR_REG_MMR_LEN                              , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MMR_LEN    );
+
+REG64_FLD( PU_PSI_TCE_ADDR_REG_ADDR                                , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADDR       );
+REG64_FLD( PU_PSI_TCE_ADDR_REG_ADDR_LEN                            , 34  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_PSI_TCE_ADDR_REG_ENTRIES                             , 61  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENTRIES    );
+REG64_FLD( PU_PSI_TCE_ADDR_REG_ENTRIES_LEN                         , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENTRIES_LEN );
+
+REG64_FLD( PU_PSU_HOST_SBE_MBOX0_REG_MBOX0                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MBOX0      );
+REG64_FLD( PU_PSU_HOST_SBE_MBOX0_REG_MBOX0_LEN                     , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MBOX0_LEN  );
+
+REG64_FLD( PU_PSU_HOST_SBE_MBOX1_REG_MBOX1                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MBOX1      );
+REG64_FLD( PU_PSU_HOST_SBE_MBOX1_REG_MBOX1_LEN                     , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MBOX1_LEN  );
+
+REG64_FLD( PU_PSU_HOST_SBE_MBOX2_REG_MBOX2                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MBOX2      );
+REG64_FLD( PU_PSU_HOST_SBE_MBOX2_REG_MBOX2_LEN                     , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MBOX2_LEN  );
+
+REG64_FLD( PU_PSU_HOST_SBE_MBOX3_REG_MBOX3                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MBOX3      );
+REG64_FLD( PU_PSU_HOST_SBE_MBOX3_REG_MBOX3_LEN                     , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MBOX3_LEN  );
+
+REG64_FLD( PU_PSU_HOST_SBE_MBOX4_REG_MBOX4                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MBOX4      );
+REG64_FLD( PU_PSU_HOST_SBE_MBOX4_REG_MBOX4_LEN                     , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MBOX4_LEN  );
+
+REG64_FLD( PU_PSU_HOST_SBE_MBOX5_REG_MBOX5                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MBOX5      );
+REG64_FLD( PU_PSU_HOST_SBE_MBOX5_REG_MBOX5_LEN                     , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MBOX5_LEN  );
+
+REG64_FLD( PU_PSU_HOST_SBE_MBOX6_REG_MBOX6                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MBOX6      );
+REG64_FLD( PU_PSU_HOST_SBE_MBOX6_REG_MBOX6_LEN                     , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MBOX6_LEN  );
+
+REG64_FLD( PU_PSU_HOST_SBE_MBOX7_REG_MBOX7                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MBOX7      );
+REG64_FLD( PU_PSU_HOST_SBE_MBOX7_REG_MBOX7_LEN                     , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MBOX7_LEN  );
+
+REG64_FLD( PU_PSU_INSTR0_ACTCYCLECNT_REG_ACTCYCLECNT               , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ACTCYCLECNT );
+REG64_FLD( PU_PSU_INSTR0_ACTCYCLECNT_REG_ACTCYCLECNT_LEN           , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ACTCYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR0_CYCLECNT_REG_CYCLECNT                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CYCLECNT   );
+REG64_FLD( PU_PSU_INSTR0_CYCLECNT_REG_CYCLECNT_LEN                 , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR0_EVENTCNT_REG_EVENTCNT                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_EVENTCNT   );
+REG64_FLD( PU_PSU_INSTR0_EVENTCNT_REG_EVENTCNT_LEN                 , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_EVENTCNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR0_FILTER_REG_CONTENT                        , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CONTENT    );
+REG64_FLD( PU_PSU_INSTR0_FILTER_REG_CONTENT_LEN                    , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CONTENT_LEN );
+REG64_FLD( PU_PSU_INSTR0_FILTER_REG_MASK                           , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASK       );
+REG64_FLD( PU_PSU_INSTR0_FILTER_REG_MASK_LEN                       , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASK_LEN   );
+
+REG64_FLD( PU_PSU_INSTR0_MAXCYCLECNT_REG_MAXCYCLECNT               , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAXCYCLECNT );
+REG64_FLD( PU_PSU_INSTR0_MAXCYCLECNT_REG_MAXCYCLECNT_LEN           , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAXCYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR0_MINCYCLECNT_REG_MINCYCLECNT               , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MINCYCLECNT );
+REG64_FLD( PU_PSU_INSTR0_MINCYCLECNT_REG_MINCYCLECNT_LEN           , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MINCYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR0_STOP_TIMER_REG_TIMER                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TIMER      );
+REG64_FLD( PU_PSU_INSTR0_STOP_TIMER_REG_TIMER_LEN                  , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TIMER_LEN  );
+
+REG64_FLD( PU_PSU_INSTR1_ACTCYCLECNT_REG_ACTCYCLECNT               , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ACTCYCLECNT );
+REG64_FLD( PU_PSU_INSTR1_ACTCYCLECNT_REG_ACTCYCLECNT_LEN           , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ACTCYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR1_CYCLECNT_REG_CYCLECNT                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CYCLECNT   );
+REG64_FLD( PU_PSU_INSTR1_CYCLECNT_REG_CYCLECNT_LEN                 , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR1_EVENTCNT_REG_EVENTCNT                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_EVENTCNT   );
+REG64_FLD( PU_PSU_INSTR1_EVENTCNT_REG_EVENTCNT_LEN                 , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_EVENTCNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR1_FILTER_REG_CONTENT                        , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CONTENT    );
+REG64_FLD( PU_PSU_INSTR1_FILTER_REG_CONTENT_LEN                    , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CONTENT_LEN );
+REG64_FLD( PU_PSU_INSTR1_FILTER_REG_MASK                           , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASK       );
+REG64_FLD( PU_PSU_INSTR1_FILTER_REG_MASK_LEN                       , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASK_LEN   );
+
+REG64_FLD( PU_PSU_INSTR1_MAXCYCLECNT_REG_MAXCYCLECNT               , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAXCYCLECNT );
+REG64_FLD( PU_PSU_INSTR1_MAXCYCLECNT_REG_MAXCYCLECNT_LEN           , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAXCYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR1_MINCYCLECNT_REG_MINCYCLECNT               , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MINCYCLECNT );
+REG64_FLD( PU_PSU_INSTR1_MINCYCLECNT_REG_MINCYCLECNT_LEN           , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MINCYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR1_STOP_TIMER_REG_TIMER                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TIMER      );
+REG64_FLD( PU_PSU_INSTR1_STOP_TIMER_REG_TIMER_LEN                  , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TIMER_LEN  );
+
+REG64_FLD( PU_PSU_INSTR2_ACTCYCLECNT_REG_ACTCYCLECNT               , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ACTCYCLECNT );
+REG64_FLD( PU_PSU_INSTR2_ACTCYCLECNT_REG_ACTCYCLECNT_LEN           , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ACTCYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR2_CYCLECNT_REG_CYCLECNT                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CYCLECNT   );
+REG64_FLD( PU_PSU_INSTR2_CYCLECNT_REG_CYCLECNT_LEN                 , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR2_EVENTCNT_REG_EVENTCNT                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_EVENTCNT   );
+REG64_FLD( PU_PSU_INSTR2_EVENTCNT_REG_EVENTCNT_LEN                 , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_EVENTCNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR2_FILTER_REG_CONTENT                        , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CONTENT    );
+REG64_FLD( PU_PSU_INSTR2_FILTER_REG_CONTENT_LEN                    , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CONTENT_LEN );
+REG64_FLD( PU_PSU_INSTR2_FILTER_REG_MASK                           , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASK       );
+REG64_FLD( PU_PSU_INSTR2_FILTER_REG_MASK_LEN                       , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASK_LEN   );
+
+REG64_FLD( PU_PSU_INSTR2_MAXCYCLECNT_REG_MAXCYCLECNT               , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAXCYCLECNT );
+REG64_FLD( PU_PSU_INSTR2_MAXCYCLECNT_REG_MAXCYCLECNT_LEN           , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAXCYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR2_MINCYCLECNT_REG_MINCYCLECNT               , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MINCYCLECNT );
+REG64_FLD( PU_PSU_INSTR2_MINCYCLECNT_REG_MINCYCLECNT_LEN           , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MINCYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR2_STOP_TIMER_REG_TIMER                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TIMER      );
+REG64_FLD( PU_PSU_INSTR2_STOP_TIMER_REG_TIMER_LEN                  , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TIMER_LEN  );
+
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_MODE                , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR0_MODE );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_MODE_LEN            , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR0_MODE_LEN );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOP_TIMER_EN       , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR0_STOP_TIMER_EN );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOP_ON_ERROR_GT    , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR0_STOP_ON_ERROR_GT );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOP_ON_ERROR_GT_LEN , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR0_STOP_ON_ERROR_GT_LEN );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_START               , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR0_START );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOP                , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR0_STOP );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_MODE                , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR1_MODE );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_MODE_LEN            , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR1_MODE_LEN );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOP_TIMER_EN       , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR1_STOP_TIMER_EN );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOP_ON_ERROR_GT    , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR1_STOP_ON_ERROR_GT );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOP_ON_ERROR_GT_LEN , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR1_STOP_ON_ERROR_GT_LEN );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_START               , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR1_START );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOP                , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR1_STOP );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_MODE                , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR2_MODE );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_MODE_LEN            , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR2_MODE_LEN );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOP_TIMER_EN       , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR2_STOP_TIMER_EN );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOP_ON_ERROR_GT    , 19  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR2_STOP_ON_ERROR_GT );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOP_ON_ERROR_GT_LEN , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR2_STOP_ON_ERROR_GT_LEN );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_START               , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR2_START );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOP                , 23  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR2_STOP );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_CYCLECNT_RUNNING    , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR0_CYCLECNT_RUNNING );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_BUSYCNT_RUNNING     , 25  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR0_BUSYCNT_RUNNING );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_CYCLECNT_RUNNING    , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR1_CYCLECNT_RUNNING );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_BUSYCNT_RUNNING     , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR1_BUSYCNT_RUNNING );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_CYCLECNT_RUNNING    , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR2_CYCLECNT_RUNNING );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_BUSYCNT_RUNNING     , 29  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR2_BUSYCNT_RUNNING );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOPPED_ON_ERROR    , 30  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR0_STOPPED_ON_ERROR );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOPPED_ON_ERROR    , 31  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR1_STOPPED_ON_ERROR );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOPPED_ON_ERROR    , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR2_STOPPED_ON_ERROR );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_RESET               , 33  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR0_RESET );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_RESET               , 34  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR1_RESET );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_RESET               , 35  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INSTR2_RESET );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INCLUDE_TRAFFIC            , 36  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INCLUDE_TRAFFIC );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_RESERVED                   , 37  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_RESERVED_LEN               , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_PSU_PIBHIST_2NDLAST_ADDR_TRACE_REG_HIST              , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST       );
+REG64_FLD( PU_PSU_PIBHIST_2NDLAST_ADDR_TRACE_REG_HIST_LEN          , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST_LEN   );
+
+REG64_FLD( PU_PSU_PIBHIST_2NDLAST_REQDATA_TRACE_REG_HIST           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST       );
+REG64_FLD( PU_PSU_PIBHIST_2NDLAST_REQDATA_TRACE_REG_HIST_LEN       , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST_LEN   );
+
+REG64_FLD( PU_PSU_PIBHIST_2NDLAST_RSPDATA_TRACE_REG_HIST           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST       );
+REG64_FLD( PU_PSU_PIBHIST_2NDLAST_RSPDATA_TRACE_REG_HIST_LEN       , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST_LEN   );
+
+REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_MANUAL_MODE_EN      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST_MANUAL_MODE_EN );
+REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_START_NOT_STOP      , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST_START_NOT_STOP );
+REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_FREEZE_HISTORY      , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST_FREEZE_HISTORY );
+REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_RESET_HISTORY       , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST_RESET_HISTORY );
+REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_TRACE_TRAFFIC       , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST_TRACE_TRAFFIC );
+REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_STOP_ON_ERROR_GT    , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST_STOP_ON_ERROR_GT );
+REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_STOP_ON_ERROR_GT_LEN , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST_STOP_ON_ERROR_GT_LEN );
+REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_RESERVED            , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST_RESERVED );
+REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_RESERVED_LEN        , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST_RESERVED_LEN );
+
+REG64_FLD( PU_PSU_PIBHIST_FILTER_REG_HIST_ADDRESS                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST_ADDRESS );
+REG64_FLD( PU_PSU_PIBHIST_FILTER_REG_HIST_ADDRESS_LEN              , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST_ADDRESS_LEN );
+REG64_FLD( PU_PSU_PIBHIST_FILTER_REG_HIST_MASK                     , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST_MASK  );
+REG64_FLD( PU_PSU_PIBHIST_FILTER_REG_HIST_MASK_LEN                 , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST_MASK_LEN );
+
+REG64_FLD( PU_PSU_PIBHIST_LAST_ADDR_TRACE_REG_HIST                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST       );
+REG64_FLD( PU_PSU_PIBHIST_LAST_ADDR_TRACE_REG_HIST_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST_LEN   );
+
+REG64_FLD( PU_PSU_PIBHIST_LAST_REQDATA_TRACE_REG_HIST              , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST       );
+REG64_FLD( PU_PSU_PIBHIST_LAST_REQDATA_TRACE_REG_HIST_LEN          , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST_LEN   );
+
+REG64_FLD( PU_PSU_PIBHIST_LAST_RSPDATA_TRACE_REG_HIST              , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST       );
+REG64_FLD( PU_PSU_PIBHIST_LAST_RSPDATA_TRACE_REG_HIST_LEN          , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HIST_LEN   );
+
+REG64_FLD( PU_PSU_SBE_DOORBELL0_REG_DOORBELL0                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOORBELL0  );
+REG64_FLD( PU_PSU_SBE_DOORBELL0_REG_FLAG                           , 1   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FLAG       );
+
+REG64_FLD( PU_PSU_SBE_DOORBELL1_REG_DOORBELL1                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DOORBELL1  );
+REG64_FLD( PU_PSU_SBE_DOORBELL1_REG_FLAG                           , 1   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_FLAG       );
+
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP0                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP0 );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP0_LEN             , 8   ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP0_LEN );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP1                 , 8   ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP1 );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP1_LEN             , 8   ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP1_LEN );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP2                 , 16  ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP2 );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP2_LEN             , 8   ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP2_LEN );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP3                 , 24  ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP3 );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP3_LEN             , 8   ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP3_LEN );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP4                 , 32  ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP4 );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP4_LEN             , 8   ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP4_LEN );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP5                 , 40  ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP5 );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP5_LEN             , 8   ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP5_LEN );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP6                 , 48  ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP6 );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP6_LEN             , 8   ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP6_LEN );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP7                 , 56  ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP7 );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP7_LEN             , 8   ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP7_LEN );
+
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP8                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP8 );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP8_LEN             , 8   ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP8_LEN );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP9                 , 8   ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP9 );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP9_LEN             , 8   ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP9_LEN );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP10                , 16  ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP10 );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP10_LEN            , 8   ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP10_LEN );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP11                , 24  ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP11 );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP11_LEN            , 8   ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP11_LEN );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP12                , 32  ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP12 );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP12_LEN            , 8   ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP12_LEN );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP13                , 40  ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP13 );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP13_LEN            , 8   ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP13_LEN );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP14                , 48  ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP14 );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP14_LEN            , 8   ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP14_LEN );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP15                , 56  ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP15 );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP15_LEN            , 8   ,
+           SH_UNT          , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP15_LEN );
+
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_CL_DMA_W                 , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_CL_DMA_W_HP              , 1   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W_HP );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_CL_DMA_INJ               , 2   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_INJ );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U          , 3   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S          , 4   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U          , 5   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S          , 6   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U         , 7   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S         , 8   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U         , 9   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S         , 10  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_PR_DMA_INJ               , 11  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PR_DMA_INJ );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_DMA_PR_W                 , 12  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_DMA_PR_W );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMW_ADD                 , 13  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_ADD );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMW_AND                 , 14  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_AND );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMW_OR                  , 15  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_OR );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMW_XOR                 , 16  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_XOR );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMWF_ADD                , 17  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_ADD );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMWF_AND                , 18  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_AND );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMWF_OR                 , 19  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_OR );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMWF_XOR                , 20  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_XOR );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_E              , 21  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_E );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_U              , 22  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_U );
+REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_RESERVED1                       , 23  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_CL_DMA_W                 , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_CL_DMA_W_HP              , 1   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W_HP );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_CL_DMA_INJ               , 2   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_INJ );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U          , 3   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S          , 4   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U          , 5   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S          , 6   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U         , 7   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S         , 8   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U         , 9   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S         , 10  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_PR_DMA_INJ               , 11  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PR_DMA_INJ );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_DMA_PR_W                 , 12  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_DMA_PR_W );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMW_ADD                 , 13  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_ADD );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMW_AND                 , 14  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_AND );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMW_OR                  , 15  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_OR );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMW_XOR                 , 16  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_XOR );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMWF_ADD                , 17  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_ADD );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMWF_AND                , 18  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_AND );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMWF_OR                 , 19  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_OR );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMWF_XOR                , 20  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_XOR );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_E              , 21  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_E );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_U              , 22  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_U );
+REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_RESERVED1                       , 23  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_CL_DMA_W                 , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_CL_DMA_W_HP              , 1   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W_HP );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_CL_DMA_INJ               , 2   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_INJ );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U          , 3   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S          , 4   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U          , 5   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S          , 6   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U         , 7   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S         , 8   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U         , 9   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S         , 10  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_PR_DMA_INJ               , 11  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PR_DMA_INJ );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_DMA_PR_W                 , 12  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_DMA_PR_W );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMW_ADD                 , 13  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_ADD );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMW_AND                 , 14  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_AND );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMW_OR                  , 15  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_OR );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMW_XOR                 , 16  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_XOR );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMWF_ADD                , 17  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_ADD );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMWF_AND                , 18  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_AND );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMWF_OR                 , 19  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_OR );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMWF_XOR                , 20  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_XOR );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_E              , 21  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_E );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_U              , 22  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_U );
+REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_RESERVED1                       , 23  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_CL_DMA_W                 , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_CL_DMA_W_HP              , 1   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W_HP );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_CL_DMA_INJ               , 2   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_INJ );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U          , 3   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S          , 4   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U          , 5   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S          , 6   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U         , 7   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S         , 8   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U         , 9   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S         , 10  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_PR_DMA_INJ               , 11  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PR_DMA_INJ );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_DMA_PR_W                 , 12  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_DMA_PR_W );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMW_ADD                 , 13  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_ADD );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMW_AND                 , 14  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_AND );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMW_OR                  , 15  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_OR );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMW_XOR                 , 16  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_XOR );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMWF_ADD                , 17  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_ADD );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMWF_AND                , 18  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_AND );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMWF_OR                 , 19  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_OR );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMWF_XOR                , 20  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_XOR );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_E              , 21  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_E );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_U              , 22  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_U );
+REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_RESERVED1                       , 23  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_CL_DMA_W                 , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_CL_DMA_W_HP              , 1   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W_HP );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_CL_DMA_INJ               , 2   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_INJ );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U          , 3   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S          , 4   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U          , 5   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S          , 6   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U         , 7   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S         , 8   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U         , 9   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S         , 10  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_PR_DMA_INJ               , 11  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PR_DMA_INJ );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_DMA_PR_W                 , 12  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_DMA_PR_W );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMW_ADD                 , 13  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_ADD );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMW_AND                 , 14  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_AND );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMW_OR                  , 15  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_OR );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMW_XOR                 , 16  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_XOR );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMWF_ADD                , 17  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_ADD );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMWF_AND                , 18  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_AND );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMWF_OR                 , 19  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_OR );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMWF_XOR                , 20  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_XOR );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_E              , 21  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_E );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_U              , 22  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_U );
+REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_RESERVED1                       , 23  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_CL_DMA_W                 , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_CL_DMA_W_HP              , 1   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W_HP );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_CL_DMA_INJ               , 2   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_INJ );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U          , 3   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S          , 4   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U          , 5   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S          , 6   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U         , 7   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S         , 8   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U         , 9   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S         , 10  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_PR_DMA_INJ               , 11  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PR_DMA_INJ );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_DMA_PR_W                 , 12  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_DMA_PR_W );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMW_ADD                 , 13  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_ADD );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMW_AND                 , 14  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_AND );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMW_OR                  , 15  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_OR );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMW_XOR                 , 16  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_XOR );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMWF_ADD                , 17  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_ADD );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMWF_AND                , 18  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_AND );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMWF_OR                 , 19  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_OR );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMWF_XOR                , 20  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_XOR );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_E              , 21  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_E );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_U              , 22  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_U );
+REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_RESERVED1                       , 23  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_CL_DMA_W                 , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_CL_DMA_W_HP              , 1   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W_HP );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_CL_DMA_INJ               , 2   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_INJ );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U          , 3   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S          , 4   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U          , 5   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S          , 6   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U         , 7   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S         , 8   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U         , 9   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S         , 10  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_PR_DMA_INJ               , 11  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PR_DMA_INJ );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_DMA_PR_W                 , 12  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_DMA_PR_W );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMW_ADD                 , 13  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_ADD );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMW_AND                 , 14  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_AND );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMW_OR                  , 15  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_OR );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMW_XOR                 , 16  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_XOR );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMWF_ADD                , 17  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_ADD );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMWF_AND                , 18  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_AND );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMWF_OR                 , 19  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_OR );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMWF_XOR                , 20  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_XOR );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_E              , 21  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_E );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_U              , 22  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_U );
+REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_RESERVED1                       , 23  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_CL_DMA_W                 , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_CL_DMA_W_HP              , 1   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W_HP );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_CL_DMA_INJ               , 2   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_INJ );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U          , 3   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S          , 4   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U          , 5   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S          , 6   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U         , 7   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S         , 8   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U         , 9   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S         , 10  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_PR_DMA_INJ               , 11  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PR_DMA_INJ );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_DMA_PR_W                 , 12  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_DMA_PR_W );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMW_ADD                 , 13  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_ADD );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMW_AND                 , 14  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_AND );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMW_OR                  , 15  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_OR );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMW_XOR                 , 16  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_XOR );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMWF_ADD                , 17  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_ADD );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMWF_AND                , 18  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_AND );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMWF_OR                 , 19  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_OR );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMWF_XOR                , 20  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_XOR );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_E              , 21  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_E );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_U              , 22  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_U );
+REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_RESERVED1                       , 23  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_CL_DMA_W                 , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_CL_DMA_W_HP              , 1   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W_HP );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_CL_DMA_INJ               , 2   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_INJ );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U          , 3   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S          , 4   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U          , 5   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S          , 6   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U         , 7   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S         , 8   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U         , 9   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S         , 10  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_PR_DMA_INJ               , 11  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PR_DMA_INJ );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_DMA_PR_W                 , 12  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_DMA_PR_W );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMW_ADD                 , 13  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_ADD );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMW_AND                 , 14  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_AND );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMW_OR                  , 15  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_OR );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMW_XOR                 , 16  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_XOR );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMWF_ADD                , 17  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_ADD );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMWF_AND                , 18  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_AND );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMWF_OR                 , 19  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_OR );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMWF_XOR                , 20  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_XOR );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_E              , 21  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_E );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_U              , 22  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_U );
+REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_RESERVED1                       , 23  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_CL_DMA_W                 , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_CL_DMA_W_HP              , 1   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W_HP );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_CL_DMA_INJ               , 2   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_INJ );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U          , 3   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S          , 4   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U          , 5   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S          , 6   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U         , 7   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S         , 8   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U         , 9   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S         , 10  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_PR_DMA_INJ               , 11  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PR_DMA_INJ );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_DMA_PR_W                 , 12  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_DMA_PR_W );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMW_ADD                 , 13  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_ADD );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMW_AND                 , 14  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_AND );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMW_OR                  , 15  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_OR );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMW_XOR                 , 16  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_XOR );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMWF_ADD                , 17  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_ADD );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMWF_AND                , 18  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_AND );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMWF_OR                 , 19  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_OR );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMWF_XOR                , 20  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_XOR );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_E              , 21  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_E );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_U              , 22  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_U );
+REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_RESERVED1                       , 23  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_CL_DMA_W                 , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_CL_DMA_W_HP              , 1   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W_HP );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_CL_DMA_INJ               , 2   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_INJ );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U          , 3   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S          , 4   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U          , 5   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S          , 6   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U         , 7   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S         , 8   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U         , 9   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S         , 10  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_PR_DMA_INJ               , 11  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PR_DMA_INJ );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_DMA_PR_W                 , 12  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_DMA_PR_W );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMW_ADD                 , 13  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_ADD );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMW_AND                 , 14  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_AND );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMW_OR                  , 15  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_OR );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMW_XOR                 , 16  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_XOR );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMWF_ADD                , 17  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_ADD );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMWF_AND                , 18  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_AND );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMWF_OR                 , 19  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_OR );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMWF_XOR                , 20  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_XOR );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_E              , 21  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_E );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_U              , 22  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_U );
+REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_RESERVED1                       , 23  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_CL_DMA_W                 , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_CL_DMA_W_HP              , 1   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_W_HP );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_CL_DMA_INJ               , 2   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_CL_DMA_INJ );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U          , 3   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S          , 4   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U          , 5   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S          , 6   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U         , 7   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S         , 8   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U         , 9   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S         , 10  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_PR_DMA_INJ               , 11  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PR_DMA_INJ );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_DMA_PR_W                 , 12  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_DMA_PR_W );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMW_ADD                 , 13  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_ADD );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMW_AND                 , 14  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_AND );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMW_OR                  , 15  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_OR );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMW_XOR                 , 16  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMW_XOR );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMWF_ADD                , 17  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_ADD );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMWF_AND                , 18  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_AND );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMWF_OR                 , 19  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_OR );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMWF_XOR                , 20  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_XOR );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_E              , 21  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_E );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_U              , 22  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_ARMWF_CAS_U );
+REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_RESERVED1                       , 23  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU0_SM0_RELAXED_SOURCE_CONFIG_PCIE                  , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE );
+REG64_FLD( PU_NPU0_SM0_RELAXED_SOURCE_CONFIG_PCIE_LEN              , 24  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE_LEN );
+REG64_FLD( PU_NPU0_SM0_RELAXED_SOURCE_CONFIG_NPU                   , 24  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_NPU );
+REG64_FLD( PU_NPU0_SM0_RELAXED_SOURCE_CONFIG_VAS                   , 25  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_VAS );
+REG64_FLD( PU_NPU0_SM0_RELAXED_SOURCE_CONFIG_NX                    , 26  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_NX  );
+REG64_FLD( PU_NPU0_SM0_RELAXED_SOURCE_CONFIG_L2L3NCU               , 27  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_L2L3NCU );
+REG64_FLD( PU_NPU0_SM0_RELAXED_SOURCE_RESERVED1                    , 28  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM0_RELAXED_SOURCE_RESERVED1_LEN                , 4   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU1_SM2_RELAXED_SOURCE_CONFIG_PCIE                  , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE );
+REG64_FLD( PU_NPU1_SM2_RELAXED_SOURCE_CONFIG_PCIE_LEN              , 24  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE_LEN );
+REG64_FLD( PU_NPU1_SM2_RELAXED_SOURCE_CONFIG_NPU                   , 24  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_NPU );
+REG64_FLD( PU_NPU1_SM2_RELAXED_SOURCE_CONFIG_VAS                   , 25  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_VAS );
+REG64_FLD( PU_NPU1_SM2_RELAXED_SOURCE_CONFIG_NX                    , 26  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_NX  );
+REG64_FLD( PU_NPU1_SM2_RELAXED_SOURCE_CONFIG_L2L3NCU               , 27  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_L2L3NCU );
+REG64_FLD( PU_NPU1_SM2_RELAXED_SOURCE_RESERVED1                    , 28  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM2_RELAXED_SOURCE_RESERVED1_LEN                , 4   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU2_SM3_RELAXED_SOURCE_CONFIG_PCIE                  , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE );
+REG64_FLD( PU_NPU2_SM3_RELAXED_SOURCE_CONFIG_PCIE_LEN              , 24  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE_LEN );
+REG64_FLD( PU_NPU2_SM3_RELAXED_SOURCE_CONFIG_NPU                   , 24  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_NPU );
+REG64_FLD( PU_NPU2_SM3_RELAXED_SOURCE_CONFIG_VAS                   , 25  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_VAS );
+REG64_FLD( PU_NPU2_SM3_RELAXED_SOURCE_CONFIG_NX                    , 26  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_NX  );
+REG64_FLD( PU_NPU2_SM3_RELAXED_SOURCE_CONFIG_L2L3NCU               , 27  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_L2L3NCU );
+REG64_FLD( PU_NPU2_SM3_RELAXED_SOURCE_RESERVED1                    , 28  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM3_RELAXED_SOURCE_RESERVED1_LEN                , 4   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU1_SM3_RELAXED_SOURCE_CONFIG_PCIE                  , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE );
+REG64_FLD( PU_NPU1_SM3_RELAXED_SOURCE_CONFIG_PCIE_LEN              , 24  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE_LEN );
+REG64_FLD( PU_NPU1_SM3_RELAXED_SOURCE_CONFIG_NPU                   , 24  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_NPU );
+REG64_FLD( PU_NPU1_SM3_RELAXED_SOURCE_CONFIG_VAS                   , 25  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_VAS );
+REG64_FLD( PU_NPU1_SM3_RELAXED_SOURCE_CONFIG_NX                    , 26  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_NX  );
+REG64_FLD( PU_NPU1_SM3_RELAXED_SOURCE_CONFIG_L2L3NCU               , 27  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_L2L3NCU );
+REG64_FLD( PU_NPU1_SM3_RELAXED_SOURCE_RESERVED1                    , 28  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM3_RELAXED_SOURCE_RESERVED1_LEN                , 4   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU0_SM3_RELAXED_SOURCE_CONFIG_PCIE                  , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE );
+REG64_FLD( PU_NPU0_SM3_RELAXED_SOURCE_CONFIG_PCIE_LEN              , 24  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE_LEN );
+REG64_FLD( PU_NPU0_SM3_RELAXED_SOURCE_CONFIG_NPU                   , 24  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_NPU );
+REG64_FLD( PU_NPU0_SM3_RELAXED_SOURCE_CONFIG_VAS                   , 25  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_VAS );
+REG64_FLD( PU_NPU0_SM3_RELAXED_SOURCE_CONFIG_NX                    , 26  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_NX  );
+REG64_FLD( PU_NPU0_SM3_RELAXED_SOURCE_CONFIG_L2L3NCU               , 27  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_CONFIG_L2L3NCU );
+REG64_FLD( PU_NPU0_SM3_RELAXED_SOURCE_RESERVED1                    , 28  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM3_RELAXED_SOURCE_RESERVED1_LEN                , 4   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU1_SM1_RELAXED_SOURCE_CONFIG_PCIE                  , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE );
+REG64_FLD( PU_NPU1_SM1_RELAXED_SOURCE_CONFIG_PCIE_LEN              , 24  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE_LEN );
+REG64_FLD( PU_NPU1_SM1_RELAXED_SOURCE_CONFIG_NPU                   , 24  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_NPU );
+REG64_FLD( PU_NPU1_SM1_RELAXED_SOURCE_CONFIG_VAS                   , 25  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_VAS );
+REG64_FLD( PU_NPU1_SM1_RELAXED_SOURCE_CONFIG_NX                    , 26  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_NX  );
+REG64_FLD( PU_NPU1_SM1_RELAXED_SOURCE_CONFIG_L2L3NCU               , 27  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_L2L3NCU );
+REG64_FLD( PU_NPU1_SM1_RELAXED_SOURCE_RESERVED1                    , 28  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM1_RELAXED_SOURCE_RESERVED1_LEN                , 4   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU2_SM2_RELAXED_SOURCE_CONFIG_PCIE                  , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE );
+REG64_FLD( PU_NPU2_SM2_RELAXED_SOURCE_CONFIG_PCIE_LEN              , 24  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE_LEN );
+REG64_FLD( PU_NPU2_SM2_RELAXED_SOURCE_CONFIG_NPU                   , 24  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_NPU );
+REG64_FLD( PU_NPU2_SM2_RELAXED_SOURCE_CONFIG_VAS                   , 25  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_VAS );
+REG64_FLD( PU_NPU2_SM2_RELAXED_SOURCE_CONFIG_NX                    , 26  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_NX  );
+REG64_FLD( PU_NPU2_SM2_RELAXED_SOURCE_CONFIG_L2L3NCU               , 27  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_L2L3NCU );
+REG64_FLD( PU_NPU2_SM2_RELAXED_SOURCE_RESERVED1                    , 28  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM2_RELAXED_SOURCE_RESERVED1_LEN                , 4   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU2_SM1_RELAXED_SOURCE_CONFIG_PCIE                  , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE );
+REG64_FLD( PU_NPU2_SM1_RELAXED_SOURCE_CONFIG_PCIE_LEN              , 24  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE_LEN );
+REG64_FLD( PU_NPU2_SM1_RELAXED_SOURCE_CONFIG_NPU                   , 24  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_NPU );
+REG64_FLD( PU_NPU2_SM1_RELAXED_SOURCE_CONFIG_VAS                   , 25  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_VAS );
+REG64_FLD( PU_NPU2_SM1_RELAXED_SOURCE_CONFIG_NX                    , 26  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_NX  );
+REG64_FLD( PU_NPU2_SM1_RELAXED_SOURCE_CONFIG_L2L3NCU               , 27  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_L2L3NCU );
+REG64_FLD( PU_NPU2_SM1_RELAXED_SOURCE_RESERVED1                    , 28  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM1_RELAXED_SOURCE_RESERVED1_LEN                , 4   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU0_SM2_RELAXED_SOURCE_CONFIG_PCIE                  , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE );
+REG64_FLD( PU_NPU0_SM2_RELAXED_SOURCE_CONFIG_PCIE_LEN              , 24  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE_LEN );
+REG64_FLD( PU_NPU0_SM2_RELAXED_SOURCE_CONFIG_NPU                   , 24  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_NPU );
+REG64_FLD( PU_NPU0_SM2_RELAXED_SOURCE_CONFIG_VAS                   , 25  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_VAS );
+REG64_FLD( PU_NPU0_SM2_RELAXED_SOURCE_CONFIG_NX                    , 26  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_NX  );
+REG64_FLD( PU_NPU0_SM2_RELAXED_SOURCE_CONFIG_L2L3NCU               , 27  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_CONFIG_L2L3NCU );
+REG64_FLD( PU_NPU0_SM2_RELAXED_SOURCE_RESERVED1                    , 28  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM2_RELAXED_SOURCE_RESERVED1_LEN                , 4   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU2_SM0_RELAXED_SOURCE_CONFIG_PCIE                  , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE );
+REG64_FLD( PU_NPU2_SM0_RELAXED_SOURCE_CONFIG_PCIE_LEN              , 24  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE_LEN );
+REG64_FLD( PU_NPU2_SM0_RELAXED_SOURCE_CONFIG_NPU                   , 24  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_NPU );
+REG64_FLD( PU_NPU2_SM0_RELAXED_SOURCE_CONFIG_VAS                   , 25  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_VAS );
+REG64_FLD( PU_NPU2_SM0_RELAXED_SOURCE_CONFIG_NX                    , 26  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_NX  );
+REG64_FLD( PU_NPU2_SM0_RELAXED_SOURCE_CONFIG_L2L3NCU               , 27  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_L2L3NCU );
+REG64_FLD( PU_NPU2_SM0_RELAXED_SOURCE_RESERVED1                    , 28  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM0_RELAXED_SOURCE_RESERVED1_LEN                , 4   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU0_SM1_RELAXED_SOURCE_CONFIG_PCIE                  , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE );
+REG64_FLD( PU_NPU0_SM1_RELAXED_SOURCE_CONFIG_PCIE_LEN              , 24  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE_LEN );
+REG64_FLD( PU_NPU0_SM1_RELAXED_SOURCE_CONFIG_NPU                   , 24  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_NPU );
+REG64_FLD( PU_NPU0_SM1_RELAXED_SOURCE_CONFIG_VAS                   , 25  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_VAS );
+REG64_FLD( PU_NPU0_SM1_RELAXED_SOURCE_CONFIG_NX                    , 26  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_NX  );
+REG64_FLD( PU_NPU0_SM1_RELAXED_SOURCE_CONFIG_L2L3NCU               , 27  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_CONFIG_L2L3NCU );
+REG64_FLD( PU_NPU0_SM1_RELAXED_SOURCE_RESERVED1                    , 28  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM1_RELAXED_SOURCE_RESERVED1_LEN                , 4   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU1_SM0_RELAXED_SOURCE_CONFIG_PCIE                  , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE );
+REG64_FLD( PU_NPU1_SM0_RELAXED_SOURCE_CONFIG_PCIE_LEN              , 24  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_PCIE_LEN );
+REG64_FLD( PU_NPU1_SM0_RELAXED_SOURCE_CONFIG_NPU                   , 24  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_NPU );
+REG64_FLD( PU_NPU1_SM0_RELAXED_SOURCE_CONFIG_VAS                   , 25  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_VAS );
+REG64_FLD( PU_NPU1_SM0_RELAXED_SOURCE_CONFIG_NX                    , 26  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_NX  );
+REG64_FLD( PU_NPU1_SM0_RELAXED_SOURCE_CONFIG_L2L3NCU               , 27  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_CONFIG_L2L3NCU );
+REG64_FLD( PU_NPU1_SM0_RELAXED_SOURCE_RESERVED1                    , 28  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM0_RELAXED_SOURCE_RESERVED1_LEN                , 4   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_RESID_FE_LEN_0  , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESID_FE_LEN_0 );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_RESID_FE_LEN_0_LEN , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESID_FE_LEN_0_LEN );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_PEEK_DATA1_0    , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_PEEK_DATA1_0_LEN , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_LBUS_PARITY_ERR1_0 , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_RESID_FE_LEN_1  , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESID_FE_LEN_1 );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_RESID_FE_LEN_1_LEN , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESID_FE_LEN_1_LEN );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_PEEK_DATA1_1    , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_PEEK_DATA1_1_LEN , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_LBUS_PARITY_ERR1_1 , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_RESID_FE_LEN_2  , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESID_FE_LEN_2 );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_RESID_FE_LEN_2_LEN , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESID_FE_LEN_2_LEN );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_PEEK_DATA1_2    , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_PEEK_DATA1_2_LEN , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_LBUS_PARITY_ERR1_2 , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_RESID_FE_LEN_3  , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESID_FE_LEN_3 );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_RESID_FE_LEN_3_LEN , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESID_FE_LEN_3_LEN );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_PEEK_DATA1_3    , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_PEEK_DATA1_3_LEN , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_LBUS_PARITY_ERR1_3 , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK0_CLUSTER                      , 0   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_BRK0_CLUSTER );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK0_CLUSTER_LEN                  , 3   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_BRK0_CLUSTER_LEN );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK1_CLUSTER                      , 3   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_BRK1_CLUSTER );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK1_CLUSTER_LEN                  , 3   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_BRK1_CLUSTER_LEN );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK2_CLUSTER                      , 6   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_BRK2_CLUSTER );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK2_CLUSTER_LEN                  , 3   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_BRK2_CLUSTER_LEN );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK3_CLUSTER                      , 9   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_BRK3_CLUSTER );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK3_CLUSTER_LEN                  , 3   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_BRK3_CLUSTER_LEN );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK4_CLUSTER                      , 12  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_BRK4_CLUSTER );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK4_CLUSTER_LEN                  , 3   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_BRK4_CLUSTER_LEN );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK5_CLUSTER                      , 15  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_BRK5_CLUSTER );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK5_CLUSTER_LEN                  , 3   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_BRK5_CLUSTER_LEN );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_RESERVED1                         , 18  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_RESERVED1_LEN                     , 2   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_SYNC_BRK                          , 20  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_SYNC_BRK   );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_SYNC_BRK_LEN                      , 6   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_SYNC_BRK_LEN );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_IDIAL_ISSYNC                      , 26  ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_ISSYNC );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_IDIAL_ISSYNC_LEN                  , 6   ,
+           SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     , SH_FLD_IDIAL_ISSYNC_LEN );
+
+REG64_FLD( PU_RNG_FAILED_INT_ENABLE                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PU_RNG_FAILED_INT_ADDRESS                               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADDRESS    );
+REG64_FLD( PU_RNG_FAILED_INT_ADDRESS_LEN                           , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_RX_CTRL_STAT_REG_ENABLE_SCWR_TO_RXRF                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE_SCWR_TO_RXRF );
+REG64_FLD( PU_RX_CTRL_STAT_REG_DISABLE_ECC_COR_RXRF_PSI            , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_ECC_COR_RXRF_PSI );
+REG64_FLD( PU_RX_CTRL_STAT_REG_CRC_MODE                            , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CRC_MODE   );
+REG64_FLD( PU_RX_CTRL_STAT_REG_ENABLE_SCRD_FR_RXRF                 , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE_SCRD_FR_RXRF );
+REG64_FLD( PU_RX_CTRL_STAT_REG_ENABLE_STREAMING_MODE               , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE_STREAMING_MODE );
+REG64_FLD( PU_RX_CTRL_STAT_REG_CHIP_INTERFACEMODE                  , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CHIP_INTERFACEMODE );
+REG64_FLD( PU_RX_CTRL_STAT_REG_CHIP_PERSONALISATION                , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CHIP_PERSONALISATION );
+
+REG64_FLD( PU_RX_MASK_REG_PSIRXINS_RFGSHIFT_PCK                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRXINS_RFGSHIFT_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXINS_RZRTMP_PCK                      , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRXINS_RZRTMP_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXINS_DATA_PCK                        , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRXINS_DATA_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXEI_SHIFT_PCK                        , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRXEI_SHIFT_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXEI_TRANSMIT_PCK                     , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRXEI_TRANSMIT_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXINS_OVERRUN                         , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRXINS_OVERRUN );
+REG64_FLD( PU_RX_MASK_REG_PSIRXBFF_DATA_PCK                        , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRXBFF_DATA_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXBFF_DATAO_PCK                       , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRXBFF_DATAO_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXBFF_RFC_PCK                         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRXBFF_RFC_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXLC_FSM_PCK                          , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRXLC_FSM_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXLC_DATA_BUFF_PCK                    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRXLC_DATA_BUFF_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXLC_DATA_PCK                         , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRXLC_DATA_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXLC_RADDR_PCK                        , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRXLC_RADDR_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXLC_RCTRL_PCK                        , 13  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRXLC_RCTRL_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXLC_UE_RF                            , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRXLC_UE_RF );
+REG64_FLD( PU_RX_MASK_REG_PSIRXLC_CE_RF                            , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRXLC_CE_RF );
+REG64_FLD( PU_RX_MASK_REG_PSIRXLC_DATA_GXST1_PCK_2N                , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRXLC_DATA_GXST1_PCK_2N );
+REG64_FLD( PU_RX_MASK_REG_PSIRFACC_RADDR_PCK                       , 17  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRFACC_RADDR_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRFACC_RCTRL_PCK                       , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRFACC_RCTRL_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRFACC_RFSM_PCK                        , 19  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRFACC_RFSM_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRFACC_RDL_FSM_PCK                     , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRFACC_RDL_FSM_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRFACC_RXSC_PCK                        , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRFACC_RXSC_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRFACC_RLINK_STATE_LT_02               , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRFACC_RLINK_STATE_LT_02 );
+REG64_FLD( PU_RX_MASK_REG_PSIRFACC_C_RXDATA_RDY_ERR                , 23  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRFACC_C_RXDATA_RDY_ERR );
+
+REG64_FLD( PU_RX_PSI_CNTL_PATTERN_CHECK_EN                         , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERN_CHECK_EN );
+REG64_FLD( PU_RX_PSI_CNTL_PATTERN_SEL                              , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERN_SEL );
+REG64_FLD( PU_RX_PSI_CNTL_PATTERN_SEL_LEN                          , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERN_SEL_LEN );
+REG64_FLD( PU_RX_PSI_CNTL_CLK_INVERT                               , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CLK_INVERT );
+REG64_FLD( PU_RX_PSI_CNTL_LANE_INVERT                              , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LANE_INVERT );
+REG64_FLD( PU_RX_PSI_CNTL_PDWN                                     , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PDWN       );
+REG64_FLD( PU_RX_PSI_CNTL_CLK_DLY                                  , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CLK_DLY    );
+REG64_FLD( PU_RX_PSI_CNTL_CLK_DLY_LEN                              , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CLK_DLY_LEN );
+REG64_FLD( PU_RX_PSI_CNTL_DATA_DLY                                 , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DATA_DLY   );
+REG64_FLD( PU_RX_PSI_CNTL_DATA_DLY_LEN                             , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DATA_DLY_LEN );
+REG64_FLD( PU_RX_PSI_CNTL_DEGLITCH_CLK_DLY                         , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DEGLITCH_CLK_DLY );
+REG64_FLD( PU_RX_PSI_CNTL_DEGLITCH_CLK_DLY_LEN                     , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DEGLITCH_CLK_DLY_LEN );
+REG64_FLD( PU_RX_PSI_CNTL_DEGLITCH_DATA_DLY                        , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DEGLITCH_DATA_DLY );
+REG64_FLD( PU_RX_PSI_CNTL_DEGLITCH_DATA_DLY_LEN                    , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DEGLITCH_DATA_DLY_LEN );
+
+REG64_FLD( PU_RX_PSI_MODE_VREF                                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_VREF       );
+REG64_FLD( PU_RX_PSI_MODE_VREF_LEN                                 , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_VREF_LEN   );
+REG64_FLD( PU_RX_PSI_MODE_TERM_TEST                                , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TERM_TEST  );
+REG64_FLD( PU_RX_PSI_MODE_TERM_ENC                                 , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TERM_ENC   );
+REG64_FLD( PU_RX_PSI_MODE_TERM_ENC_LEN                             , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TERM_ENC_LEN );
+REG64_FLD( PU_RX_PSI_MODE_SPARE                                    , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SPARE      );
+REG64_FLD( PU_RX_PSI_MODE_SPARE_LEN                                , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_RX_PSI_STATUS_LD_UNLD_DLY                            , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LD_UNLD_DLY );
+REG64_FLD( PU_RX_PSI_STATUS_LD_UNLD_DLY_LEN                        , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LD_UNLD_DLY_LEN );
+REG64_FLD( PU_RX_PSI_STATUS_OVER_OR_UNDERRUN_ERR                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OVER_OR_UNDERRUN_ERR );
+REG64_FLD( PU_RX_PSI_STATUS_CLEAR                                  , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CLEAR      );
+REG64_FLD( PU_RX_PSI_STATUS_SPARE                                  , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SPARE      );
+REG64_FLD( PU_RX_PSI_STATUS_SPARE_LEN                              , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_NPU0_SCRATCH0_IDIAL                                  , 0   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SCRATCH0_IDIAL_LEN                              , 64  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SCRATCH0_IDIAL                                  , 0   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SCRATCH0_IDIAL_LEN                              , 64  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SCRATCH0_IDIAL                                  , 0   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SCRATCH0_IDIAL_LEN                              , 64  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_NTL0_SCRATCH1_IDIAL                             , 0   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_NTL0_SCRATCH1_IDIAL_LEN                         , 64  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_NTL0_SCRATCH1_IDIAL                             , 0   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_NTL0_SCRATCH1_IDIAL_LEN                         , 64  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_NTL1_SCRATCH1_IDIAL                             , 0   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_NTL1_SCRATCH1_IDIAL_LEN                         , 64  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_NTL1_SCRATCH1_IDIAL                             , 0   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_NTL1_SCRATCH1_IDIAL_LEN                         , 64  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_NTL1_SCRATCH1_IDIAL                             , 0   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_NTL1_SCRATCH1_IDIAL_LEN                         , 64  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_DAT_SCRATCH1_IDIAL                              , 0   ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_DAT_SCRATCH1_IDIAL_LEN                          , 64  ,
+           SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_DAT_SCRATCH1_IDIAL                              , 0   ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_DAT_SCRATCH1_IDIAL_LEN                          , 64  ,
+           SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_DAT_SCRATCH1_IDIAL                              , 0   ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_DAT_SCRATCH1_IDIAL_LEN                          , 64  ,
+           SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_NTL0_SCRATCH1_IDIAL                             , 0   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_NTL0_SCRATCH1_IDIAL_LEN                         , 64  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_NTL0_SCRATCH2_IDIAL                             , 0   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_NTL0_SCRATCH2_IDIAL_LEN                         , 64  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_NTL1_SCRATCH2_IDIAL                             , 0   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_NTL1_SCRATCH2_IDIAL_LEN                         , 64  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_NTL0_SCRATCH2_IDIAL                             , 0   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_NTL0_SCRATCH2_IDIAL_LEN                         , 64  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_NTL1_SCRATCH2_IDIAL                             , 0   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_NTL1_SCRATCH2_IDIAL_LEN                         , 64  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_NTL1_SCRATCH2_IDIAL                             , 0   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_NTL1_SCRATCH2_IDIAL_LEN                         , 64  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_NTL0_SCRATCH2_IDIAL                             , 0   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_NTL0_SCRATCH2_IDIAL_LEN                         , 64  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_NTL0_SCRATCH3_IDIAL                             , 0   ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_NTL0_SCRATCH3_IDIAL_LEN                         , 64  ,
+           SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_NTL1_SCRATCH3_IDIAL                             , 0   ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_NTL1_SCRATCH3_IDIAL_LEN                         , 64  ,
+           SH_UNT_PU_NPU0_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_NTL0_SCRATCH3_IDIAL                             , 0   ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_NTL0_SCRATCH3_IDIAL_LEN                         , 64  ,
+           SH_UNT_PU_NPU1_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_NTL1_SCRATCH3_IDIAL                             , 0   ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_NTL1_SCRATCH3_IDIAL_LEN                         , 64  ,
+           SH_UNT_PU_NPU1_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_NTL1_SCRATCH3_IDIAL                             , 0   ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_NTL1_SCRATCH3_IDIAL_LEN                         , 64  ,
+           SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_NTL0_SCRATCH3_IDIAL                             , 0   ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_NTL0_SCRATCH3_IDIAL_LEN                         , 64  ,
+           SH_UNT_PU_NPU0_NTL0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_SECURE_ACCESS               , 0   ,
+           SH_UNT          , SH_ACS_SCOM1    , SH_FLD_SECURE_ACCESS );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_LATE_LAUNCH_PRIMARY         , 1   ,
+           SH_UNT          , SH_ACS_SCOM1    , SH_FLD_LATE_LAUNCH_PRIMARY );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_LATE_LAUNCH_SECONDARY       , 2   ,
+           SH_UNT          , SH_ACS_SCOM1    , SH_FLD_LATE_LAUNCH_SECONDARY );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_LOCAL_QUIESCE_ACHIEVED      , 3   ,
+           SH_UNT          , SH_ACS_SCOM1    , SH_FLD_LOCAL_QUIESCE_ACHIEVED );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_SEEPROM_UPDATE_LOCK         , 4   ,
+           SH_UNT          , SH_ACS_SCOM1    , SH_FLD_SEEPROM_UPDATE_LOCK );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_LOCALITY_4_ACCESS           , 5   ,
+           SH_UNT          , SH_ACS_SCOM1    , SH_FLD_LOCALITY_4_ACCESS );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_SECURE_DEBUG                , 6   ,
+           SH_UNT          , SH_ACS_SCOM1    , SH_FLD_SECURE_DEBUG );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_CMFSI_ACCESS_PROTCT         , 7   ,
+           SH_UNT          , SH_ACS_SCOM1    , SH_FLD_CMFSI_ACCESS_PROTCT );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_I2C_EXTENDER                , 8   ,
+           SH_UNT          , SH_ACS_SCOM1    , SH_FLD_I2C_EXTENDER );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_SECURE_MODE                 , 9   ,
+           SH_UNT          , SH_ACS_SCOM1    , SH_FLD_SECURE_MODE );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_EX_SPARE0              , 10  ,
+           SH_UNT          , SH_ACS_SCOM1    , SH_FLD_PROT_EX_SPARE0 );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_EX_SPARE1              , 11  ,
+           SH_UNT          , SH_ACS_SCOM1    , SH_FLD_PROT_EX_SPARE1 );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_RESERVED_0                  , 12  ,
+           SH_UNT          , SH_ACS_SCOM1    , SH_FLD_RESERVED_0 );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_TP_SPARE0              , 13  ,
+           SH_UNT          , SH_ACS_SCOM1    , SH_FLD_PROT_TP_SPARE0 );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_TP_SPARE1              , 14  ,
+           SH_UNT          , SH_ACS_SCOM1    , SH_FLD_PROT_TP_SPARE1 );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_TP_SPARE2              , 15  ,
+           SH_UNT          , SH_ACS_SCOM1    , SH_FLD_PROT_TP_SPARE2 );
+
+REG64_FLD( PU_SEND_WC_BASE_ADDR_BAR                                , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BAR        );
+REG64_FLD( PU_SEND_WC_BASE_ADDR_BAR_LEN                            , 33  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BAR_LEN    );
+
+REG64_FLD( PU_NPU0_SM0_SM_HOLD_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM0_SM_HOLD_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM2_SM_HOLD_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM2_SM_HOLD_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM3_SM_HOLD_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM3_SM_HOLD_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM3_SM_HOLD_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM3_SM_HOLD_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM3_SM_HOLD_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM3_SM_HOLD_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM1_SM_HOLD_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM1_SM_HOLD_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM2_SM_HOLD_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM2_SM_HOLD_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM1_SM_HOLD_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM1_SM_HOLD_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM2_SM_HOLD_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM2_SM_HOLD_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM0_SM_HOLD_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM0_SM_HOLD_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM1_SM_HOLD_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM1_SM_HOLD_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM0_SM_HOLD_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM0_SM_HOLD_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM0_SM_MASK_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM0_SM_MASK_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM2_SM_MASK_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM2_SM_MASK_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM3_SM_MASK_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM3_SM_MASK_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM3_SM_MASK_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM3_SM_MASK_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM3_SM_MASK_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM3_SM_MASK_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM1_SM_MASK_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM1_SM_MASK_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM2_SM_MASK_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM2_SM_MASK_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM1_SM_MASK_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM1_SM_MASK_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM2_SM_MASK_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM2_SM_MASK_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM0_SM_MASK_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SM0_SM_MASK_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_SM1_SM_MASK_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SM1_SM_MASK_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_SM0_SM_MASK_IDIAL                               , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SM0_SM_MASK_IDIAL_LEN                           , 20  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_SND_MODE_REG_ENABLE_TRC_GLB_TRIG0                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE_TRC_GLB_TRIG0 );
+REG64_FLD( PU_SND_MODE_REG_ENABLE_TRC_GLB_TRIG1                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE_TRC_GLB_TRIG1 );
+REG64_FLD( PU_SND_MODE_REG_ENABLE_GLB_PULSE                        , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE_GLB_PULSE );
+REG64_FLD( PU_SND_MODE_REG_SINGLE_OUTSTANDING_CMD                  , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SINGLE_OUTSTANDING_CMD );
+REG64_FLD( PU_SND_MODE_REG_PROG_REQ_DELAY                          , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PROG_REQ_DELAY );
+REG64_FLD( PU_SND_MODE_REG_PROG_REQ_DELAY_LEN                      , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PROG_REQ_DELAY_LEN );
+REG64_FLD( PU_SND_MODE_REG_DISABLE_ERR_CMD                         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_ERR_CMD );
+REG64_FLD( PU_SND_MODE_REG_DISABLE_HTM_CMD                         , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_HTM_CMD );
+REG64_FLD( PU_SND_MODE_REG_DISABLE_TRACE_CMD                       , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_TRACE_CMD );
+REG64_FLD( PU_SND_MODE_REG_DISABLE_TOD_CMD                         , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_TOD_CMD );
+REG64_FLD( PU_SND_MODE_REG_DISABLE_XSCOM_CMD                       , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_XSCOM_CMD );
+REG64_FLD( PU_SND_MODE_REG_ENABLE_CLR_ERR_CMD                      , 13  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE_CLR_ERR_CMD );
+REG64_FLD( PU_SND_MODE_REG_OVERRIDE_PBINIT_ERR_CMD                 , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OVERRIDE_PBINIT_ERR_CMD );
+REG64_FLD( PU_SND_MODE_REG_OVERRIDE_PBINIT_HTM_CMD                 , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OVERRIDE_PBINIT_HTM_CMD );
+REG64_FLD( PU_SND_MODE_REG_OVERRIDE_PBINIT_TRACE_CMD               , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OVERRIDE_PBINIT_TRACE_CMD );
+REG64_FLD( PU_SND_MODE_REG_OVERRIDE_PBINIT_TOD_CMD                 , 17  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OVERRIDE_PBINIT_TOD_CMD );
+REG64_FLD( PU_SND_MODE_REG_OVERRIDE_PBINIT_XSCOM_CMD               , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OVERRIDE_PBINIT_XSCOM_CMD );
+REG64_FLD( PU_SND_MODE_REG_DISABLE_CHECKSTOP                       , 19  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_CHECKSTOP );
+REG64_FLD( PU_SND_MODE_REG_MANUAL_SET_PB_STOP                      , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MANUAL_SET_PB_STOP );
+REG64_FLD( PU_SND_MODE_REG_MANUAL_CLR_PB_STOP                      , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MANUAL_CLR_PB_STOP );
+REG64_FLD( PU_SND_MODE_REG_PB_STOP                                 , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PB_STOP    );
+REG64_FLD( PU_SND_MODE_REG_MANUAL_PB_SWITCH_ABCD                   , 25  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MANUAL_PB_SWITCH_ABCD );
+REG64_FLD( PU_SND_MODE_REG_ENABLE_RECEIVE_OWN_TRIGGER              , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE_RECEIVE_OWN_TRIGGER );
+REG64_FLD( PU_SND_MODE_REG_ENABLE_RECEIVE_OWN_TRIGGER_LEN          , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE_RECEIVE_OWN_TRIGGER_LEN );
+REG64_FLD( PU_SND_MODE_REG_ENABLE_RECEIVE_OWN_TOD                  , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE_RECEIVE_OWN_TOD );
+REG64_FLD( PU_SND_MODE_REG_RESET_TOD_STATE                         , 29  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESET_TOD_STATE );
+REG64_FLD( PU_SND_MODE_REG_ENABLE_PB_SWITCH_AB                     , 30  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE_PB_SWITCH_AB );
+REG64_FLD( PU_SND_MODE_REG_ENABLE_PB_SWITCH_CD                     , 31  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE_PB_SWITCH_CD );
+
+REG64_FLD( PU_SND_STAT_REG_ERR_CMD_OVERRUN                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERR_CMD_OVERRUN );
+REG64_FLD( PU_SND_STAT_REG_TRC_CMD_OVERRUN                         , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRC_CMD_OVERRUN );
+REG64_FLD( PU_SND_STAT_REG_XSC_CMD_OVERRUN                         , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_XSC_CMD_OVERRUN );
+REG64_FLD( PU_SND_STAT_REG_HTM_CMD_OVERRUN                         , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HTM_CMD_OVERRUN );
+REG64_FLD( PU_SND_STAT_REG_TOD_CMD_OVERRUN                         , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TOD_CMD_OVERRUN );
+REG64_FLD( PU_SND_STAT_REG_CMD_COUNT_ERR                           , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMD_COUNT_ERR );
+REG64_FLD( PU_SND_STAT_REG_PB_OP_HANG_ERR                          , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PB_OP_HANG_ERR );
+REG64_FLD( PU_SND_STAT_REG_INVALID_CRESP_ERR                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INVALID_CRESP_ERR );
+REG64_FLD( PU_SND_STAT_REG_RCV_TTAG_PARITY_ERR                     , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RCV_TTAG_PARITY_ERR );
+REG64_FLD( PU_SND_STAT_REG_RCV_PB_OP_HANG_ERR                      , 33  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RCV_PB_OP_HANG_ERR );
+REG64_FLD( PU_SND_STAT_REG_TOD_HANG_ERR                            , 34  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TOD_HANG_ERR );
+REG64_FLD( PU_SND_STAT_REG_RCV_TOD_STATE                           , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RCV_TOD_STATE );
+REG64_FLD( PU_SND_STAT_REG_RCV_TOD_STATE_LEN                       , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RCV_TOD_STATE_LEN );
+
+REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_FRAME_SIZE              , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_FRAME_SIZE );
+REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_FRAME_SIZE_LEN          , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_FRAME_SIZE_LEN );
+REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_OUT_COUNT               , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_OUT_COUNT );
+REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_OUT_COUNT_LEN           , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_OUT_COUNT_LEN );
+REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_IN_DELAY                , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_IN_DELAY );
+REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_IN_DELAY_LEN            , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_IN_DELAY_LEN );
+REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_IN_COUNT                , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_IN_COUNT );
+REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_IN_COUNT_LEN            , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_IN_COUNT_LEN );
+
+REG64_FLD( PU_SPIPSS_100NS_REG_OUT                                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OUT        );
+REG64_FLD( PU_SPIPSS_100NS_REG_OUT_LEN                             , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OUT_LEN    );
+
+REG64_FLD( PU_SPIPSS_ADC_CMD_REG_HWCTRL_START_SAMPLING             , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_START_SAMPLING );
+
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_FSM_ENABLE               , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_FSM_ENABLE );
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_DEVICE                   , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_DEVICE );
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_CPOL                     , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_CPOL );
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_CPHA                     , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_CPHA );
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_CLOCK_DIVIDER            , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_CLOCK_DIVIDER );
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_CLOCK_DIVIDER_LEN        , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_CLOCK_DIVIDER_LEN );
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_NR_OF_FRAMES             , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_NR_OF_FRAMES );
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_NR_OF_FRAMES_LEN         , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_NR_OF_FRAMES_LEN );
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN ,
+           18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN );
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_BUSY_RESPONSE_CODE              , 19  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUSY_RESPONSE_CODE );
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_BUSY_RESPONSE_CODE_LEN          , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUSY_RESPONSE_CODE_LEN );
+
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG2_HWCTRL_INTER_FRAME_DELAY        , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_INTER_FRAME_DELAY );
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG2_HWCTRL_INTER_FRAME_DELAY_LEN    , 17  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_INTER_FRAME_DELAY_LEN );
+
+REG64_FLD( PU_SPIPSS_ADC_RDATA_REG0_HWCTRL_RDATA0                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_RDATA0 );
+REG64_FLD( PU_SPIPSS_ADC_RDATA_REG0_HWCTRL_RDATA0_LEN              , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_RDATA0_LEN );
+
+REG64_FLD( PU_SPIPSS_ADC_RDATA_REG1_HWCTRL_RDATA1                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_RDATA1 );
+REG64_FLD( PU_SPIPSS_ADC_RDATA_REG1_HWCTRL_RDATA1_LEN              , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_RDATA1_LEN );
+
+REG64_FLD( PU_SPIPSS_ADC_RDATA_REG2_HWCTRL_RDATA2                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_RDATA2 );
+REG64_FLD( PU_SPIPSS_ADC_RDATA_REG2_HWCTRL_RDATA2_LEN              , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_RDATA2_LEN );
+
+REG64_FLD( PU_SPIPSS_ADC_RDATA_REG3_HWCTRL_RDATA3                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_RDATA3 );
+REG64_FLD( PU_SPIPSS_ADC_RDATA_REG3_HWCTRL_RDATA3_LEN              , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_RDATA3_LEN );
+
+REG64_FLD( PU_SPIPSS_ADC_RESET_REGISTER_HWCTRL                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL     );
+REG64_FLD( PU_SPIPSS_ADC_RESET_REGISTER_HWCTRL_LEN                 , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_LEN );
+
+REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_HWCTRL_ONGOING                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_ONGOING );
+REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_RESERVED_1                     , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_1 );
+REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_RESERVED_2                     , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_2 );
+REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_RESERVED_3                     , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_3 );
+REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_HWCTRL_INVALID_NUMBER_OF_FRAMES , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_INVALID_NUMBER_OF_FRAMES );
+REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_HWCTRL_WRITE_WHILE_FSM_BUSY_ERR , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_WRITE_WHILE_FSM_BUSY_ERR );
+REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_RESERVED_6                     , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_6 );
+REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_HWCTRL_FSM_ERR                 , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_FSM_ERR );
+
+REG64_FLD( PU_SPIPSS_ADC_WDATA_REG_HWCTRL                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL     );
+REG64_FLD( PU_SPIPSS_ADC_WDATA_REG_HWCTRL_LEN                      , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HWCTRL_LEN );
+
+REG64_FLD( PU_SPIPSS_P2S_COMMAND_REG_START                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_START      );
+
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_FRAME_SIZE                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FRAME_SIZE );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_FRAME_SIZE_LEN                  , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FRAME_SIZE_LEN );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_OUT_COUNT1                      , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OUT_COUNT1 );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_OUT_COUNT1_LEN                  , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OUT_COUNT1_LEN );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_DELAY1                       , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IN_DELAY1  );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_DELAY1_LEN                   , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IN_DELAY1_LEN );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_COUNT1                       , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IN_COUNT1  );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_COUNT1_LEN                   , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IN_COUNT1_LEN );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_OUT_COUNT2                      , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OUT_COUNT2 );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_OUT_COUNT2_LEN                  , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_OUT_COUNT2_LEN );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_DELAY2                       , 30  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IN_DELAY2  );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_DELAY2_LEN                   , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IN_DELAY2_LEN );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_COUNT2                       , 36  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IN_COUNT2  );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_COUNT2_LEN                   , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IN_COUNT2_LEN );
+
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_BRIDGE_ENABLE                   , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BRIDGE_ENABLE );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_DEVICE                          , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DEVICE     );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_CPOL                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CPOL       );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_CPHA                            , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CPHA       );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_CLOCK_DIVIDER                   , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CLOCK_DIVIDER );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_CLOCK_DIVIDER_LEN               , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CLOCK_DIVIDER_LEN );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_RESERVED                        , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED   );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_RESERVED_LEN                    , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_NR_OF_FRAMES                    , 17  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NR_OF_FRAMES );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_BUSY_RESPONSE_CODE_NO_1         , 19  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUSY_RESPONSE_CODE_NO_1 );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_BUSY_RESPONSE_CODE_NO_1_LEN     , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUSY_RESPONSE_CODE_NO_1_LEN );
+
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG2_INTER_FRAME_DELAY               , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INTER_FRAME_DELAY );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG2_INTER_FRAME_DELAY_LEN           , 17  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INTER_FRAME_DELAY_LEN );
+
+REG64_FLD( PU_SPIPSS_P2S_RDATA_REG_RDATA                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RDATA      );
+REG64_FLD( PU_SPIPSS_P2S_RDATA_REG_RDATA_LEN                       , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RDATA_LEN  );
+
+REG64_FLD( PU_SPIPSS_P2S_RESET_REGISTER_RESET                      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESET      );
+REG64_FLD( PU_SPIPSS_P2S_RESET_REGISTER_RESET_LEN                  , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESET_LEN  );
+
+REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_ONGOING                        , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ONGOING    );
+REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_RESERVED_1                     , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_1 );
+REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_RESERVED_2                     , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_2 );
+REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_RESERVED_3                     , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_3 );
+REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_RESERVED_4                     , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED_4 );
+REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_WRITE_WHILE_BRIDGE_BUSY_ERR    , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WRITE_WHILE_BRIDGE_BUSY_ERR );
+REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_RESERVED6                      , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESERVED6  );
+REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_FSM_ERR                        , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FSM_ERR    );
+
+REG64_FLD( PU_SPIPSS_P2S_WDATA_REG_WDATA                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WDATA      );
+REG64_FLD( PU_SPIPSS_P2S_WDATA_REG_WDATA_LEN                       , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WDATA_LEN  );
+
+REG64_FLD( PU_GPE5_SRAM_SRBV0_BOOT_VECTOR_WORD0                    , 0   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_BOOT_VECTOR_WORD0 );
+REG64_FLD( PU_GPE5_SRAM_SRBV0_BOOT_VECTOR_WORD0_LEN                , 32  ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_BOOT_VECTOR_WORD0_LEN );
+
+REG64_FLD( PU_GPE5_SRAM_SRBV1_BOOT_VECTOR_WORD1                    , 0   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_BOOT_VECTOR_WORD1 );
+REG64_FLD( PU_GPE5_SRAM_SRBV1_BOOT_VECTOR_WORD1_LEN                , 32  ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_BOOT_VECTOR_WORD1_LEN );
+
+REG64_FLD( PU_GPE5_SRAM_SRBV2_BOOT_VECTOR_WORD2                    , 0   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_BOOT_VECTOR_WORD2 );
+REG64_FLD( PU_GPE5_SRAM_SRBV2_BOOT_VECTOR_WORD2_LEN                , 32  ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_BOOT_VECTOR_WORD2_LEN );
+
+REG64_FLD( PU_GPE5_SRAM_SRBV3_BOOT_VECTOR_WORD3                    , 0   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_BOOT_VECTOR_WORD3 );
+REG64_FLD( PU_GPE5_SRAM_SRBV3_BOOT_VECTOR_WORD3_LEN                , 32  ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_BOOT_VECTOR_WORD3_LEN );
+
+REG64_FLD( PU_GPE5_SRAM_SRCHSW_CHKSW_WRFSM_DLY_DIS                 , 0   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_CHKSW_WRFSM_DLY_DIS );
+REG64_FLD( PU_GPE5_SRAM_SRCHSW_CHKSW_ALLOW1_RD                     , 1   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_CHKSW_ALLOW1_RD );
+REG64_FLD( PU_GPE5_SRAM_SRCHSW_CHKSW_ALLOW1_WR                     , 2   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_CHKSW_ALLOW1_WR );
+REG64_FLD( PU_GPE5_SRAM_SRCHSW_CHKSW_ALLOW1_RDWR                   , 3   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_CHKSW_ALLOW1_RDWR );
+REG64_FLD( PU_GPE5_SRAM_SRCHSW_CHKSW_OCI_PARCHK_DIS                , 4   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_CHKSW_OCI_PARCHK_DIS );
+REG64_FLD( PU_GPE5_SRAM_SRCHSW_CHKSW_TANK_RDDATA_PARCHK_DIS        , 5   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_CHKSW_TANK_RDDATA_PARCHK_DIS );
+REG64_FLD( PU_GPE5_SRAM_SRCHSW_CHKSW_SPARE_6                       , 6   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_CHKSW_SPARE_6 );
+REG64_FLD( PU_GPE5_SRAM_SRCHSW_CHKSW_VAL_BE_ADDR_CHK_DIS           , 7   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_CHKSW_VAL_BE_ADDR_CHK_DIS );
+REG64_FLD( PU_GPE5_SRAM_SRCHSW_CHKSW_SO_SPARE                      , 8   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_CHKSW_SO_SPARE );
+REG64_FLD( PU_GPE5_SRAM_SRCHSW_CHKSW_SO_SPARE_LEN                  , 2   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_CHKSW_SO_SPARE_LEN );
+
+REG64_FLD( PU_GPE5_SRAM_SREAR_ERROR_ADDRESS                        , 0   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_ERROR_ADDRESS );
+REG64_FLD( PU_GPE5_SRAM_SREAR_ERROR_ADDRESS_LEN                    , 16  ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_ERROR_ADDRESS_LEN );
+
+REG64_FLD( PU_GPE5_SRAM_SRMAP_REMAP_SOURCE                         , 0   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_REMAP_SOURCE );
+REG64_FLD( PU_GPE5_SRAM_SRMAP_REMAP_SOURCE_LEN                     , 14  ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_REMAP_SOURCE_LEN );
+REG64_FLD( PU_GPE5_SRAM_SRMAP_REMAP_DEST                           , 16  ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_REMAP_DEST );
+REG64_FLD( PU_GPE5_SRAM_SRMAP_REMAP_DEST_LEN                       , 14  ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_REMAP_DEST_LEN );
+
+REG64_FLD( PU_GPE5_SRAM_SRMR_ENABLE_REMAP                          , 0   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_ENABLE_REMAP );
+REG64_FLD( PU_GPE5_SRAM_SRMR_ARB_EN_SEND_ALL_WRITES                , 1   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_ARB_EN_SEND_ALL_WRITES );
+REG64_FLD( PU_GPE5_SRAM_SRMR_DISABLE_LFSR                          , 2   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_DISABLE_LFSR );
+REG64_FLD( PU_GPE5_SRAM_SRMR_LFSR_FAIRNESS_MASK                    , 3   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_LFSR_FAIRNESS_MASK );
+REG64_FLD( PU_GPE5_SRAM_SRMR_LFSR_FAIRNESS_MASK_LEN                , 5   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_LFSR_FAIRNESS_MASK_LEN );
+REG64_FLD( PU_GPE5_SRAM_SRMR_ERROR_INJECT_ENABLE                   , 8   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_ERROR_INJECT_ENABLE );
+REG64_FLD( PU_GPE5_SRAM_SRMR_CTL_TRACE_EN                          , 9   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_CTL_TRACE_EN );
+REG64_FLD( PU_GPE5_SRAM_SRMR_CTL_TRACE_SEL                         , 10  ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_CTL_TRACE_SEL );
+REG64_FLD( PU_GPE5_SRAM_SRMR_SPARE                                 , 11  ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_SPARE      );
+REG64_FLD( PU_GPE5_SRAM_SRMR_SPARE_LEN                             , 5   ,
+           SH_UNT_PU_GPE5  , SH_ACS_SCOM_RW  , SH_FLD_SPARE_LEN  );
+
+REG32_FLD( PU_STATUS_REGISTER_ADDR_NVLD                            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADDR_NVLD  );
+REG32_FLD( PU_STATUS_REGISTER_WRITE_NVLD                           , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WRITE_NVLD );
+REG32_FLD( PU_STATUS_REGISTER_READ_NVLD                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_READ_NVLD  );
+REG32_FLD( PU_STATUS_REGISTER_INVLD_CMD_ERR                        , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INVLD_CMD_ERR );
+REG32_FLD( PU_STATUS_REGISTER_CORR_ERR                             , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CORR_ERR   );
+REG32_FLD( PU_STATUS_REGISTER_UNCORR_ERROR                         , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNCORR_ERROR );
+REG32_FLD( PU_STATUS_REGISTER_DATA_REG_0_31                        , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DATA_REG_0_31 );
+REG32_FLD( PU_STATUS_REGISTER_DATA_REG_0_31_LEN                    , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DATA_REG_0_31_LEN );
+REG32_FLD( PU_STATUS_REGISTER_UNUSED_39_43                         , 39  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED_39_43 );
+REG32_FLD( PU_STATUS_REGISTER_UNUSED_39_43_LEN                     , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED_39_43_LEN );
+REG32_FLD( PU_STATUS_REGISTER_CTRL_BUSY                            , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CTRL_BUSY  );
+REG32_FLD( PU_STATUS_REGISTER_DCOMP_ERR                            , 45  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DCOMP_ERR  );
+REG32_FLD( PU_STATUS_REGISTER_INVLD_PRGM_ERR                       , 46  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INVLD_PRGM_ERR );
+REG32_FLD( PU_STATUS_REGISTER_UNUSED_47_51                         , 47  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED_47_51 );
+REG32_FLD( PU_STATUS_REGISTER_UNUSED_47_51_LEN                     , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED_47_51_LEN );
+REG32_FLD( PU_STATUS_REGISTER_COMMAND_COMPLETE                     , 52  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_COMMAND_COMPLETE );
+REG32_FLD( PU_STATUS_REGISTER_UNUSED_53                            , 53  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_UNUSED_53  );
+REG32_FLD( PU_STATUS_REGISTER_RDWR_OP_BUSY                         , 54  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RDWR_OP_BUSY );
+REG32_FLD( PU_STATUS_REGISTER_DCOMP_ENGINE_BUSY                    , 55  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DCOMP_ENGINE_BUSY );
+REG32_FLD( PU_STATUS_REGISTER_RD_DATA_COUNT                        , 56  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RD_DATA_COUNT );
+REG32_FLD( PU_STATUS_REGISTER_RD_DATA_COUNT_LEN                    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RD_DATA_COUNT_LEN );
+
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_ADDR_NVLD_0                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_ADDR_NVLD_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_WRITE_NVLD_0                   , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_WRITE_NVLD_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_READ_NVLD_0                    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_READ_NVLD_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_ADDR_P_ERR_0                   , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_ADDR_P_ERR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_PAR_ERR_0                      , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_PAR_ERR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_LB_PARITY_ERROR_0              , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_LB_PARITY_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_PIB_DATA0TO7_0                     , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_DATA0TO7_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_PIB_DATA0TO7_0_LEN                 , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_DATA0TO7_0_LEN );
+REG64_FLD( PU_STATUS_REGISTER_B_ECC_CORRECTED_ERROR_0              , 41  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_CORRECTED_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_ECC_UNCORRECTED_ERROR_0            , 42  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_UNCORRECTED_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_ECC_CONFIG_ERROR_0                 , 43  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_CONFIG_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_BUSY_0                         , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_BUSY_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_INVALID_COMMAND_0              , 45  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_INVALID_COMMAND_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_PARITY_ERROR_0                 , 46  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_PARITY_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_BACK_END_OVERRUN_ERROR_0       , 47  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_BACK_END_OVERRUN_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_BACK_END_ACCESS_ERROR_0        , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_BACK_END_ACCESS_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_ARBITRATION_LOST_ERROR_0       , 49  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_ARBITRATION_LOST_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_NACK_RECEIVED_ERROR_0          , 50  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_NACK_RECEIVED_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_DATA_REQUEST_0                 , 51  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_DATA_REQUEST_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_COMMAND_COMPLETE_0             , 52  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_COMMAND_COMPLETE_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_STOP_ERROR_0                   , 53  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_STOP_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_I2C_PORT_BUSY_0                , 54  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_I2C_PORT_BUSY_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_I2C_INTERFACE_BUSY_0           , 55  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_I2C_INTERFACE_BUSY_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_FIFO_ENTRY_COUNT_0             , 56  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_FIFO_ENTRY_COUNT_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_FIFO_ENTRY_COUNT_0_LEN         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_FIFO_ENTRY_COUNT_0_LEN );
+
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_ADDR_NVLD_1                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_ADDR_NVLD_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_WRITE_NVLD_1                   , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_WRITE_NVLD_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_READ_NVLD_1                    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_READ_NVLD_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_ADDR_P_ERR_1                   , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_ADDR_P_ERR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_PAR_ERR_1                      , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_PAR_ERR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_LB_PARITY_ERROR_1              , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_LB_PARITY_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_PIB_DATA0TO7_1                     , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_DATA0TO7_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_PIB_DATA0TO7_1_LEN                 , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_DATA0TO7_1_LEN );
+REG64_FLD( PU_STATUS_REGISTER_C_ECC_CORRECTED_ERROR_1              , 41  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_CORRECTED_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_ECC_UNCORRECTED_ERROR_1            , 42  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_UNCORRECTED_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_ECC_CONFIG_ERROR_1                 , 43  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_CONFIG_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_BUSY_1                         , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_BUSY_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_INVALID_COMMAND_1              , 45  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_INVALID_COMMAND_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_PARITY_ERROR_1                 , 46  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_PARITY_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_BACK_END_OVERRUN_ERROR_1       , 47  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_BACK_END_OVERRUN_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_BACK_END_ACCESS_ERROR_1        , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_BACK_END_ACCESS_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_ARBITRATION_LOST_ERROR_1       , 49  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_ARBITRATION_LOST_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_NACK_RECEIVED_ERROR_1          , 50  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_NACK_RECEIVED_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_DATA_REQUEST_1                 , 51  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_DATA_REQUEST_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_COMMAND_COMPLETE_1             , 52  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_COMMAND_COMPLETE_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_STOP_ERROR_1                   , 53  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_STOP_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_I2C_PORT_BUSY_1                , 54  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_I2C_PORT_BUSY_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_I2C_INTERFACE_BUSY_1           , 55  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_I2C_INTERFACE_BUSY_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_FIFO_ENTRY_COUNT_1             , 56  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_FIFO_ENTRY_COUNT_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_FIFO_ENTRY_COUNT_1_LEN         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_FIFO_ENTRY_COUNT_1_LEN );
+
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_ADDR_NVLD_2                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_ADDR_NVLD_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_WRITE_NVLD_2                   , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_WRITE_NVLD_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_READ_NVLD_2                    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_READ_NVLD_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_ADDR_P_ERR_2                   , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_ADDR_P_ERR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_PAR_ERR_2                      , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_PAR_ERR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_LB_PARITY_ERROR_2              , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_LB_PARITY_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_PIB_DATA0TO7_2                     , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_DATA0TO7_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_PIB_DATA0TO7_2_LEN                 , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_DATA0TO7_2_LEN );
+REG64_FLD( PU_STATUS_REGISTER_D_ECC_CORRECTED_ERROR_2              , 41  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_CORRECTED_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_ECC_UNCORRECTED_ERROR_2            , 42  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_UNCORRECTED_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_ECC_CONFIG_ERROR_2                 , 43  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_CONFIG_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_BUSY_2                         , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_BUSY_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_INVALID_COMMAND_2              , 45  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_INVALID_COMMAND_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_PARITY_ERROR_2                 , 46  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_PARITY_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_BACK_END_OVERRUN_ERROR_2       , 47  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_BACK_END_OVERRUN_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_BACK_END_ACCESS_ERROR_2        , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_BACK_END_ACCESS_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_ARBITRATION_LOST_ERROR_2       , 49  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_ARBITRATION_LOST_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_NACK_RECEIVED_ERROR_2          , 50  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_NACK_RECEIVED_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_DATA_REQUEST_2                 , 51  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_DATA_REQUEST_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_COMMAND_COMPLETE_2             , 52  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_COMMAND_COMPLETE_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_STOP_ERROR_2                   , 53  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_STOP_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_I2C_PORT_BUSY_2                , 54  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_I2C_PORT_BUSY_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_I2C_INTERFACE_BUSY_2           , 55  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_I2C_INTERFACE_BUSY_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_FIFO_ENTRY_COUNT_2             , 56  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_FIFO_ENTRY_COUNT_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_FIFO_ENTRY_COUNT_2_LEN         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_FIFO_ENTRY_COUNT_2_LEN );
+
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_ADDR_NVLD_3                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_ADDR_NVLD_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_WRITE_NVLD_3                   , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_WRITE_NVLD_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_READ_NVLD_3                    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_READ_NVLD_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_ADDR_P_ERR_3                   , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_ADDR_P_ERR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_PAR_ERR_3                      , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_PAR_ERR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_LB_PARITY_ERROR_3              , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_LB_PARITY_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_PIB_DATA0TO7_3                     , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_DATA0TO7_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_PIB_DATA0TO7_3_LEN                 , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_DATA0TO7_3_LEN );
+REG64_FLD( PU_STATUS_REGISTER_E_ECC_CORRECTED_ERROR_3              , 41  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_CORRECTED_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_ECC_UNCORRECTED_ERROR_3            , 42  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_UNCORRECTED_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_ECC_CONFIG_ERROR_3                 , 43  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ECC_CONFIG_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_BUSY_3                         , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_BUSY_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_INVALID_COMMAND_3              , 45  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_INVALID_COMMAND_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_PARITY_ERROR_3                 , 46  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_PARITY_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_BACK_END_OVERRUN_ERROR_3       , 47  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_BACK_END_OVERRUN_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_BACK_END_ACCESS_ERROR_3        , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_BACK_END_ACCESS_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_ARBITRATION_LOST_ERROR_3       , 49  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_ARBITRATION_LOST_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_NACK_RECEIVED_ERROR_3          , 50  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_NACK_RECEIVED_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_DATA_REQUEST_3                 , 51  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_DATA_REQUEST_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_COMMAND_COMPLETE_3             , 52  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_COMMAND_COMPLETE_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_STOP_ERROR_3                   , 53  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_STOP_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_I2C_PORT_BUSY_3                , 54  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_I2C_PORT_BUSY_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_I2C_INTERFACE_BUSY_3           , 55  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_I2C_INTERFACE_BUSY_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_FIFO_ENTRY_COUNT_3             , 56  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_FIFO_ENTRY_COUNT_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_FIFO_ENTRY_COUNT_3_LEN         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUS_FIFO_ENTRY_COUNT_3_LEN );
+
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_INVALID_CMD_0               , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INVALID_CMD_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_LBUS_PARITY_ERROR_0         , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_BE_OV_ERROR_0               , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BE_OV_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_BE_ACC_ERROR_0              , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BE_ACC_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_ARBITRATION_LOST_ERROR_0    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ARBITRATION_LOST_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_NACK_RECEIVED_ERROR_0       , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NACK_RECEIVED_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_DATA_REQUEST_0              , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DATA_REQUEST_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_STOP_ERROR_0                , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STOP_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_BUSY                        , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUSY       );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_SELF_BUSY_0                 , 23  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SELF_BUSY_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_FIFO_ENTRY_COUNT_0          , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_ENTRY_COUNT_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_FIFO_ENTRY_COUNT_0_LEN      , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_ENTRY_COUNT_0_LEN );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_PEEK_DATA1_0                , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_PEEK_DATA1_0_LEN            , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_LBUS_PARITY_ERR1_0          , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_INVALID_CMD_1               , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INVALID_CMD_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_LBUS_PARITY_ERROR_1         , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_BE_OV_ERROR_1               , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BE_OV_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_BE_ACC_ERROR_1              , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BE_ACC_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_ARBITRATION_LOST_ERROR_1    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ARBITRATION_LOST_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_NACK_RECEIVED_ERROR_1       , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NACK_RECEIVED_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_DATA_REQUEST_1              , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DATA_REQUEST_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_STOP_ERROR_1                , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STOP_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_BUSY                        , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUSY       );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_SELF_BUSY_1                 , 23  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SELF_BUSY_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_FIFO_ENTRY_COUNT_1          , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_ENTRY_COUNT_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_FIFO_ENTRY_COUNT_1_LEN      , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_ENTRY_COUNT_1_LEN );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_PEEK_DATA1_1                , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_PEEK_DATA1_1_LEN            , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_LBUS_PARITY_ERR1_1          , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_INVALID_CMD_2               , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INVALID_CMD_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_LBUS_PARITY_ERROR_2         , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_BE_OV_ERROR_2               , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BE_OV_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_BE_ACC_ERROR_2              , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BE_ACC_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_ARBITRATION_LOST_ERROR_2    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ARBITRATION_LOST_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_NACK_RECEIVED_ERROR_2       , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NACK_RECEIVED_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_DATA_REQUEST_2              , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DATA_REQUEST_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_STOP_ERROR_2                , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STOP_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_BUSY                        , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUSY       );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_SELF_BUSY_2                 , 23  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SELF_BUSY_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_FIFO_ENTRY_COUNT_2          , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_ENTRY_COUNT_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_FIFO_ENTRY_COUNT_2_LEN      , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_ENTRY_COUNT_2_LEN );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_PEEK_DATA1_2                , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_PEEK_DATA1_2_LEN            , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_LBUS_PARITY_ERR1_2          , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_INVALID_CMD_3               , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_INVALID_CMD_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_LBUS_PARITY_ERROR_3         , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_BE_OV_ERROR_3               , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BE_OV_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_BE_ACC_ERROR_3              , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BE_ACC_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_ARBITRATION_LOST_ERROR_3    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ARBITRATION_LOST_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_NACK_RECEIVED_ERROR_3       , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_NACK_RECEIVED_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_DATA_REQUEST_3              , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DATA_REQUEST_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_STOP_ERROR_3                , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STOP_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_BUSY                        , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BUSY       );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_SELF_BUSY_3                 , 23  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SELF_BUSY_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_FIFO_ENTRY_COUNT_3          , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_ENTRY_COUNT_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_FIFO_ENTRY_COUNT_3_LEN      , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FIFO_ENTRY_COUNT_3_LEN );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_PEEK_DATA1_3                , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_PEEK_DATA1_3_LEN            , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_LBUS_PARITY_ERR1_3          , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( PU_PIB2OPB1_STAT_RDDAT_ERRES_CMD_PARITY_ERROR           , 1   ,
+           SH_UNT_PU_PIB2OPB1, SH_ACS_SCOM_RO  , SH_FLD_CMD_PARITY_ERROR );
+REG64_FLD( PU_PIB2OPB1_STAT_RDDAT_ERRES_WR_DATA_PARITY_ERROR       , 2   ,
+           SH_UNT_PU_PIB2OPB1, SH_ACS_SCOM_RO  , SH_FLD_WR_DATA_PARITY_ERROR );
+REG64_FLD( PU_PIB2OPB1_STAT_RDDAT_ERRES_RD_DATA_PARITY_ERROR       , 3   ,
+           SH_UNT_PU_PIB2OPB1, SH_ACS_SCOM_RO  , SH_FLD_RD_DATA_PARITY_ERROR );
+REG64_FLD( PU_PIB2OPB1_STAT_RDDAT_ERRES_LCK_STATUS_PARITY_ERROR    , 4   ,
+           SH_UNT_PU_PIB2OPB1, SH_ACS_SCOM_RO  , SH_FLD_LCK_STATUS_PARITY_ERROR );
+REG64_FLD( PU_PIB2OPB1_STAT_RDDAT_ERRES_FSM_PARITY_ERROR           , 5   ,
+           SH_UNT_PU_PIB2OPB1, SH_ACS_SCOM_RO  , SH_FLD_FSM_PARITY_ERROR );
+REG64_FLD( PU_PIB2OPB1_STAT_RDDAT_ERRES_OPB_PARITY_ERROR           , 8   ,
+           SH_UNT_PU_PIB2OPB1, SH_ACS_SCOM_RO  , SH_FLD_OPB_PARITY_ERROR );
+
+REG64_FLD( PU_PIB2OPB0_STAT_RDDAT_ERRES_CMD_PARITY_ERROR           , 1   ,
+           SH_UNT_PU_PIB2OPB0, SH_ACS_SCOM_RO  , SH_FLD_CMD_PARITY_ERROR );
+REG64_FLD( PU_PIB2OPB0_STAT_RDDAT_ERRES_WR_DATA_PARITY_ERROR       , 2   ,
+           SH_UNT_PU_PIB2OPB0, SH_ACS_SCOM_RO  , SH_FLD_WR_DATA_PARITY_ERROR );
+REG64_FLD( PU_PIB2OPB0_STAT_RDDAT_ERRES_RD_DATA_PARITY_ERROR       , 3   ,
+           SH_UNT_PU_PIB2OPB0, SH_ACS_SCOM_RO  , SH_FLD_RD_DATA_PARITY_ERROR );
+REG64_FLD( PU_PIB2OPB0_STAT_RDDAT_ERRES_LCK_STATUS_PARITY_ERROR    , 4   ,
+           SH_UNT_PU_PIB2OPB0, SH_ACS_SCOM_RO  , SH_FLD_LCK_STATUS_PARITY_ERROR );
+REG64_FLD( PU_PIB2OPB0_STAT_RDDAT_ERRES_FSM_PARITY_ERROR           , 5   ,
+           SH_UNT_PU_PIB2OPB0, SH_ACS_SCOM_RO  , SH_FLD_FSM_PARITY_ERROR );
+REG64_FLD( PU_PIB2OPB0_STAT_RDDAT_ERRES_OPB_PARITY_ERROR           , 8   ,
+           SH_UNT_PU_PIB2OPB0, SH_ACS_SCOM_RO  , SH_FLD_OPB_PARITY_ERROR );
+
+REG64_FLD( PU_SU_CRB_KILL_REQ_ENABLE                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE     );
+REG64_FLD( PU_SU_CRB_KILL_REQ_DONE                                 , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DONE       );
+REG64_FLD( PU_SU_CRB_KILL_REQ_SUMMARY                              , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SUMMARY    );
+REG64_FLD( PU_SU_CRB_KILL_REQ_DISPATCH_SLOT_KILLED_CNT             , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DISPATCH_SLOT_KILLED_CNT );
+REG64_FLD( PU_SU_CRB_KILL_REQ_DISPATCH_SLOT_KILLED_CNT_LEN         , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DISPATCH_SLOT_KILLED_CNT_LEN );
+REG64_FLD( PU_SU_CRB_KILL_REQ_PREFETCH_CHANNEL_CNT                 , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PREFETCH_CHANNEL_CNT );
+REG64_FLD( PU_SU_CRB_KILL_REQ_PREFETCH_CHANNEL_CNT_LEN             , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PREFETCH_CHANNEL_CNT_LEN );
+REG64_FLD( PU_SU_CRB_KILL_REQ_ACTIVE_CHANNEL_CNT                   , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACTIVE_CHANNEL_CNT );
+REG64_FLD( PU_SU_CRB_KILL_REQ_ACTIVE_CHANNEL_CNT_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACTIVE_CHANNEL_CNT_LEN );
+REG64_FLD( PU_SU_CRB_KILL_REQ_SWC_VALUE                            , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SWC_VALUE  );
+REG64_FLD( PU_SU_CRB_KILL_REQ_SWC_VALUE_LEN                        , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SWC_VALUE_LEN );
+
+REG64_FLD( PU_SU_DMA_ERROR_REPORT_0_0                              , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_0          );
+REG64_FLD( PU_SU_DMA_ERROR_REPORT_0_0_LEN                          , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_0_LEN      );
+
+REG64_FLD( PU_SU_DMA_ERROR_REPORT_1_1                              , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_1          );
+REG64_FLD( PU_SU_DMA_ERROR_REPORT_1_1_LEN                          , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_1_LEN      );
+
+REG64_FLD( PU_SU_ENGINE_ENABLE_ALLOW_CRYPTO                        , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ALLOW_CRYPTO );
+REG64_FLD( PU_SU_ENGINE_ENABLE_CH3_SYM                             , 57  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CH3_SYM    );
+REG64_FLD( PU_SU_ENGINE_ENABLE_CH2_SYM                             , 58  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CH2_SYM    );
+REG64_FLD( PU_SU_ENGINE_ENABLE_CH4_GZIP                            , 61  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CH4_GZIP   );
+REG64_FLD( PU_SU_ENGINE_ENABLE_CH1_EFT                             , 62  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CH1_EFT    );
+REG64_FLD( PU_SU_ENGINE_ENABLE_CH0_EFT                             , 63  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CH0_EFT    );
+
+REG64_FLD( PU_SU_ERAT_ERROR_RPT_RPT                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RPT        );
+REG64_FLD( PU_SU_ERAT_ERROR_RPT_RPT_LEN                            , 46  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RPT_LEN    );
+
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_GZIPCOMP_MAX_INRD           , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GZIPCOMP_MAX_INRD );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_GZIPCOMP_MAX_INRD_LEN       , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GZIPCOMP_MAX_INRD_LEN );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_GZIPDECOMP_MAX_INRD         , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GZIPDECOMP_MAX_INRD );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_GZIPDECOMP_MAX_INRD_LEN     , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GZIPDECOMP_MAX_INRD_LEN );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_GZIP_COMP_PREFETCH_ENABLE   , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GZIP_COMP_PREFETCH_ENABLE );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_GZIP_DECOMP_PREFETCH_ENABLE , 17  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GZIP_DECOMP_PREFETCH_ENABLE );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_EFT_COMP_PREFETCH_ENABLE    , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EFT_COMP_PREFETCH_ENABLE );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_EFT_DECOMP_PREFETCH_ENABLE  , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EFT_DECOMP_PREFETCH_ENABLE );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_SYM_MAX_INRD                , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SYM_MAX_INRD );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_SYM_MAX_INRD_LEN            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SYM_MAX_INRD_LEN );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_EFTCOMP_MAX_INRD            , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EFTCOMP_MAX_INRD );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_EFTCOMP_MAX_INRD_LEN        , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EFTCOMP_MAX_INRD_LEN );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_EFTDECOMP_MAX_INRD          , 37  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EFTDECOMP_MAX_INRD );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_EFTDECOMP_MAX_INRD_LEN      , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EFTDECOMP_MAX_INRD_LEN );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_SYM_CPB_CHECK_DISABLE       , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SYM_CPB_CHECK_DISABLE );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_EFT_SPBC_ENABLE             , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EFT_SPBC_ENABLE );
+
+REG64_FLD( PU_SU_MARKER_TRACE_CONTROL_46_55                        , 46  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_46_55      );
+REG64_FLD( PU_SU_MARKER_TRACE_CONTROL_46_55_LEN                    , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_46_55_LEN  );
+
+REG64_FLD( PU_SU_PERFMON_CONTROL_0_LPID                            , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LPID       );
+REG64_FLD( PU_SU_PERFMON_CONTROL_0_LPID_LEN                        , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LPID_LEN   );
+REG64_FLD( PU_SU_PERFMON_CONTROL_0_LPID_MASK                       , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LPID_MASK  );
+REG64_FLD( PU_SU_PERFMON_CONTROL_0_LPID_MASK_LEN                   , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LPID_MASK_LEN );
+REG64_FLD( PU_SU_PERFMON_CONTROL_0_PID                             , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PID        );
+REG64_FLD( PU_SU_PERFMON_CONTROL_0_PID_LEN                         , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PID_LEN    );
+REG64_FLD( PU_SU_PERFMON_CONTROL_0_PID_MASK                        , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PID_MASK   );
+REG64_FLD( PU_SU_PERFMON_CONTROL_0_PID_MASK_LEN                    , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PID_MASK_LEN );
+
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_GZIP_FC_SELECT                  , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GZIP_FC_SELECT );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_GZIP_FC_SELECT_LEN              , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GZIP_FC_SELECT_LEN );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_842_FC_SELECT                   , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_842_FC_SELECT );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_842_FC_SELECT_LEN               , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_842_FC_SELECT_LEN );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_MUX_SELECT                      , 46  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MUX_SELECT );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_MUX_SELECT_LEN                  , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MUX_SELECT_LEN );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_SHA_LATENCY_CFG                 , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SHA_LATENCY_CFG );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_MD5_LATENCY_CFG                 , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_MD5_LATENCY_CFG );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_AES_LATENCY_CFG                 , 56  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_AES_LATENCY_CFG );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_AESSHA_LATENCY_CFG              , 58  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_AESSHA_LATENCY_CFG );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_GZIP_LATENCY_CFG                , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_GZIP_LATENCY_CFG );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_842_LATENCY_CFG                 , 62  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_842_LATENCY_CFG );
+
+REG64_FLD( PU_SU_STATUS_HMI_ACTIVE                                 , 54  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HMI_ACTIVE );
+REG64_FLD( PU_SU_STATUS_PBI_IDLE                                   , 55  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PBI_IDLE   );
+REG64_FLD( PU_SU_STATUS_DMA_CH0_IDLE                               , 56  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DMA_CH0_IDLE );
+REG64_FLD( PU_SU_STATUS_DMA_CH1_IDLE                               , 57  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DMA_CH1_IDLE );
+REG64_FLD( PU_SU_STATUS_DMA_CH2_IDLE                               , 58  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DMA_CH2_IDLE );
+REG64_FLD( PU_SU_STATUS_DMA_CH3_IDLE                               , 59  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DMA_CH3_IDLE );
+REG64_FLD( PU_SU_STATUS_DMA_CH4_IDLE                               , 60  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DMA_CH4_IDLE );
+
+REG64_FLD( PU_SU_UMAC_ERROR_RPT_RPT                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RPT        );
+REG64_FLD( PU_SU_UMAC_ERROR_RPT_RPT_LEN                            , 62  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RPT_LEN    );
+
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID              , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_LPID );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN          , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_LPID_LEN );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID               , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_PID );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN           , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_PID_LEN );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID               , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_TID );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN           , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_TID_LEN );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE            , 63  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_ENABLE );
+
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_BAR_PRIORITY                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY   );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN               , 46  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_LEN );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE              , 54  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_SIZE );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN          , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_SIZE_LEN );
+
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET      , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_READ_OFFSET );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_READ_OFFSET_LEN );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED           , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_QUEUED );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN       , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_QUEUED_LEN );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX           , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_PRIMAX );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX_LEN       , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_PRIMAX_LEN );
+
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID              , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_LPID );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN          , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_LPID_LEN );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID               , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_PID );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN           , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_PID_LEN );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID               , 44  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_TID );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN           , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_TID_LEN );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE            , 63  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_ENABLE );
+
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_BAR_PRIORITY                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY   );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN               , 46  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_LEN );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE              , 54  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_SIZE );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN          , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_SIZE_LEN );
+
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET      , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_READ_OFFSET );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_READ_OFFSET_LEN );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED           , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_QUEUED );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN       , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PRIORITY_QUEUED_LEN );
+
+REG64_FLD( PU_SYM_MAX_BYTE_CNT_LIMIT                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LIMIT      );
+REG64_FLD( PU_SYM_MAX_BYTE_CNT_LIMIT_LEN                           , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_LIMIT_LEN  );
+REG64_FLD( PU_SYM_MAX_BYTE_CNT_SRC_DDE                             , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SRC_DDE    );
+REG64_FLD( PU_SYM_MAX_BYTE_CNT_SRC_DDE_LEN                         , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SRC_DDE_LEN );
+REG64_FLD( PU_SYM_MAX_BYTE_CNT_TARGET_DDE                          , 13  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_TARGET_DDE );
+REG64_FLD( PU_SYM_MAX_BYTE_CNT_TARGET_DDE_LEN                      , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_TARGET_DDE_LEN );
+
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_INVALID_TRANSFER_SIZE           , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INVALID_TRANSFER_SIZE );
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_INVALID_COMMAND                 , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INVALID_COMMAND );
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_INVALID_ADDRESS_ALIGNMENT       , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INVALID_ADDRESS_ALIGNMENT );
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_OPB_ERROR                       , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_OPB_ERROR  );
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_OPB_TIMEOUT                     , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_OPB_TIMEOUT );
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_OPB_MASTER_HANG_TIMEOUT         , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_OPB_MASTER_HANG_TIMEOUT );
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_CMD_BUFFER_PAR_ERR              , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CMD_BUFFER_PAR_ERR );
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_DAT_BUFFER_PAR_ERR              , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DAT_BUFFER_PAR_ERR );
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_RETURNQ_ERR                     , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RETURNQ_ERR );
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_RESERVED                        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RESERVED   );
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_SCOM_PARITY_ERR2                , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SCOM_PARITY_ERR2 );
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_SCOM_PARITY_ERR                 , 11  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SCOM_PARITY_ERR );
+
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_INVALID_TRANSFER_SIZE           , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INVALID_TRANSFER_SIZE );
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_INVALID_COMMAND                 , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INVALID_COMMAND );
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_INVALID_ADDRESS_ALIGNMENT       , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_INVALID_ADDRESS_ALIGNMENT );
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_OPB_ERROR                       , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_OPB_ERROR  );
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_OPB_TIMEOUT                     , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_OPB_TIMEOUT );
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_OPB_MASTER_HANG_TIMEOUT         , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_OPB_MASTER_HANG_TIMEOUT );
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_CMD_BUFFER_PAR_ERR              , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_CMD_BUFFER_PAR_ERR );
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_DAT_BUFFER_PAR_ERR              , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DAT_BUFFER_PAR_ERR );
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_RETURNQ_ERR                     , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RETURNQ_ERR );
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_RESERVED                        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RESERVED   );
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_SCOM_PARITY_ERR2                , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SCOM_PARITY_ERR2 );
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_SCOM_PARITY_ERR                 , 11  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_SCOM_PARITY_ERR );
+
+REG64_FLD( PU_SYNC_FIR_MASK_REG_INVALID_TRANSFER_SIZE              , 0   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INVALID_TRANSFER_SIZE );
+REG64_FLD( PU_SYNC_FIR_MASK_REG_INVALID_COMMAND                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INVALID_COMMAND );
+REG64_FLD( PU_SYNC_FIR_MASK_REG_INVALID_ADDRESS_ALIGNMENT          , 2   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INVALID_ADDRESS_ALIGNMENT );
+REG64_FLD( PU_SYNC_FIR_MASK_REG_OPB_ERROR                          , 3   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_OPB_ERROR  );
+REG64_FLD( PU_SYNC_FIR_MASK_REG_OPB_TIMEOUT                        , 4   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_OPB_TIMEOUT );
+REG64_FLD( PU_SYNC_FIR_MASK_REG_OPB_MASTER_HANG_TIMEOUT            , 5   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_OPB_MASTER_HANG_TIMEOUT );
+REG64_FLD( PU_SYNC_FIR_MASK_REG_CMD_BUFFER_PAR_ERR                 , 6   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CMD_BUFFER_PAR_ERR );
+REG64_FLD( PU_SYNC_FIR_MASK_REG_DAT_BUFFER_PAR_ERR                 , 7   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DAT_BUFFER_PAR_ERR );
+REG64_FLD( PU_SYNC_FIR_MASK_REG_RETURNQ_ERR                        , 8   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RETURNQ_ERR );
+REG64_FLD( PU_SYNC_FIR_MASK_REG_RESERVED                           , 9   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED   );
+REG64_FLD( PU_SYNC_FIR_MASK_REG_SCOM_PARITY_ERR2                   , 10  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PARITY_ERR2 );
+REG64_FLD( PU_SYNC_FIR_MASK_REG_SCOM_PARITY_ERR                    , 11  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PARITY_ERR );
+
+REG64_FLD( PU_SYNC_FIR_REG_INVALID_TRANSFER_SIZE                   , 0   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INVALID_TRANSFER_SIZE );
+REG64_FLD( PU_SYNC_FIR_REG_INVALID_COMMAND                         , 1   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INVALID_COMMAND );
+REG64_FLD( PU_SYNC_FIR_REG_INVALID_ADDRESS_ALIGNMENT               , 2   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INVALID_ADDRESS_ALIGNMENT );
+REG64_FLD( PU_SYNC_FIR_REG_OPB_ERROR                               , 3   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_OPB_ERROR  );
+REG64_FLD( PU_SYNC_FIR_REG_OPB_TIMEOUT                             , 4   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_OPB_TIMEOUT );
+REG64_FLD( PU_SYNC_FIR_REG_OPB_MASTER_HANG_TIMEOUT                 , 5   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_OPB_MASTER_HANG_TIMEOUT );
+REG64_FLD( PU_SYNC_FIR_REG_CMD_BUFFER_PAR_ERR                      , 6   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CMD_BUFFER_PAR_ERR );
+REG64_FLD( PU_SYNC_FIR_REG_DAT_BUFFER_PAR_ERR                      , 7   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DAT_BUFFER_PAR_ERR );
+REG64_FLD( PU_SYNC_FIR_REG_RETURNQ_ERR                             , 8   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RETURNQ_ERR );
+REG64_FLD( PU_SYNC_FIR_REG_RESERVED                                , 9   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RESERVED   );
+REG64_FLD( PU_SYNC_FIR_REG_PARITY_ERR2                             , 10  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERR2 );
+REG64_FLD( PU_SYNC_FIR_REG_PARITY_ERR                              , 11  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERR );
+
+REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_ALL                      , 0   ,
+           SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     , SH_FLD_INVALIDATE_ALL );
+REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_ONE                      , 2   ,
+           SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     , SH_FLD_INVALIDATE_ONE );
+REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_PE_NUMBER                , 4   ,
+           SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     , SH_FLD_INVALIDATE_PE_NUMBER );
+REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_PE_NUMBER_LEN            , 4   ,
+           SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     , SH_FLD_INVALIDATE_PE_NUMBER_LEN );
+REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_ADDRESS                  , 15  ,
+           SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     , SH_FLD_INVALIDATE_ADDRESS );
+REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_ADDRESS_LEN              , 37  ,
+           SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     , SH_FLD_INVALIDATE_ADDRESS_LEN );
+
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_HI_DATA_REG_DATA              , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_HI_DATA_REG_DATA_LEN          , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_DATA              , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_DATA_LEN          , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_ADDRESS           , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_ADDRESS_LEN       , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_LAST_BANK         , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_LAST_BANK_LEN     , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_LAST_BANK_VALID   , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_WRITE_ON_RUN      , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_RUNNING           , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS      , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN  , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN ,
+           22  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN ,
+           64  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 ,
+           0   , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN  , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB      , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN  , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN  , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND      , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN  , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_4_MASKA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_4_MASKA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_4_MASKB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_4_MASKB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_5_MASKC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_5_MASKC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_5_MASKD         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_5_MASKD_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK ,
+    1   , SH_UNT          , SH_ACS_SCOM     ,
+    SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_HI_DATA_REG_DATA              , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_HI_DATA_REG_DATA_LEN          , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_LO_DATA_REG_DATA              , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_LO_DATA_REG_DATA_LEN          , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_LO_DATA_REG_ADDRESS           , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_LO_DATA_REG_ADDRESS_LEN       , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_LO_DATA_REG_LAST_BANK         , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_LO_DATA_REG_LAST_BANK_LEN     , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_LO_DATA_REG_LAST_BANK_VALID   , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_LO_DATA_REG_WRITE_ON_RUN      , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_LO_DATA_REG_RUNNING           , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS      , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN  , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN ,
+           22  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN ,
+           64  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 ,
+           0   , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN  , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB      , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN  , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC      , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN  , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND      , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN  , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_4_MASKA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_4_MASKA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_4_MASKB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_4_MASKB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_5_MASKC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_5_MASKC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_5_MASKD         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_5_MASKD_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK ,
+    1   , SH_UNT          , SH_ACS_SCOM     ,
+    SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN0_TRA1_TRACE_HI_DATA_REG_DATA                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN0_TRA1_TRACE_HI_DATA_REG_DATA_LEN                 , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN0_TRA1_TRACE_LO_DATA_REG_DATA                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN0_TRA1_TRACE_LO_DATA_REG_DATA_LEN                 , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN0_TRA1_TRACE_LO_DATA_REG_ADDRESS                  , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN0_TRA1_TRACE_LO_DATA_REG_ADDRESS_LEN              , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN0_TRA1_TRACE_LO_DATA_REG_LAST_BANK                , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN0_TRA1_TRACE_LO_DATA_REG_LAST_BANK_LEN            , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN0_TRA1_TRACE_LO_DATA_REG_LAST_BANK_VALID          , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN0_TRA1_TRACE_LO_DATA_REG_WRITE_ON_RUN             , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN0_TRA1_TRACE_LO_DATA_REG_RUNNING                  , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN0_TRA1_TRACE_LO_DATA_REG_HOLD_ADDRESS             , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN0_TRA1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN         , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE     , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63   , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNA             , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNB             , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_3_PATTERNC             , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_3_PATTERND             , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_4_MASKA                , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_4_MASKA_LEN            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_4_MASKB                , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_4_MASKB_LEN            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_5_MASKC                , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_5_MASKC_LEN            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_5_MASKD                , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_5_MASKD_LEN            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION  , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK ,
+           1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL        , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL        , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL        , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL        , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK        , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK       , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN   , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK        , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK       , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN   , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE       , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE       , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE       , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN0_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN   , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA4_TRACE_HI_DATA_REG_DATA                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA4_TRACE_HI_DATA_REG_DATA_LEN                 , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN3_TRA4_TRACE_LO_DATA_REG_DATA                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA4_TRACE_LO_DATA_REG_DATA_LEN                 , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN3_TRA4_TRACE_LO_DATA_REG_ADDRESS                  , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN3_TRA4_TRACE_LO_DATA_REG_ADDRESS_LEN              , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN3_TRA4_TRACE_LO_DATA_REG_LAST_BANK                , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN3_TRA4_TRACE_LO_DATA_REG_LAST_BANK_LEN            , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN3_TRA4_TRACE_LO_DATA_REG_LAST_BANK_VALID          , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN3_TRA4_TRACE_LO_DATA_REG_WRITE_ON_RUN             , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN3_TRA4_TRACE_LO_DATA_REG_RUNNING                  , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN3_TRA4_TRACE_LO_DATA_REG_HOLD_ADDRESS             , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN3_TRA4_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN         , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE     , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63   , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_2_PATTERNA             , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_2_PATTERNB             , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_3_PATTERNC             , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_3_PATTERND             , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_3_PATTERND_LEN         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_4_MASKA                , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_4_MASKA_LEN            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_4_MASKB                , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_4_MASKB_LEN            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_5_MASKC                , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_5_MASKC_LEN            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_5_MASKD                , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_5_MASKD_LEN            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION  , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK ,
+           1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL        , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL        , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL        , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL        , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK        , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK       , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN   , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK        , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK       , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN   , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE       , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE       , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE       , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA4_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN   , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_HI_DATA_REG_DATA                   , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_HI_DATA_REG_DATA_LEN               , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_LO_DATA_REG_DATA                   , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_LO_DATA_REG_DATA_LEN               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_LO_DATA_REG_ADDRESS                , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_LO_DATA_REG_ADDRESS_LEN            , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_LO_DATA_REG_LAST_BANK              , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_LO_DATA_REG_LAST_BANK_LEN          , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_LO_DATA_REG_LAST_BANK_VALID        , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_LO_DATA_REG_WRITE_ON_RUN           , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_LO_DATA_REG_RUNNING                , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS           , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN       , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE   , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN       , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB           , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN       , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN       , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND           , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN       , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_4_MASKA              , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_4_MASKA_LEN          , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_4_MASKB              , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_4_MASKB_LEN          , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_5_MASKC              , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_5_MASKC_LEN          , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_5_MASKD              , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_5_MASKD_LEN          , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK
+           , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL      , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN  , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL      , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN  , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL      , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN  , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL      , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN  , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK      , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN  , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK     , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK      , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN  , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK     , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE     , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE     , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE     , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCPCI0_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_HI_DATA_REG_DATA                   , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_HI_DATA_REG_DATA_LEN               , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_LO_DATA_REG_DATA                   , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_LO_DATA_REG_DATA_LEN               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_LO_DATA_REG_ADDRESS                , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_LO_DATA_REG_ADDRESS_LEN            , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_LO_DATA_REG_LAST_BANK              , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_LO_DATA_REG_LAST_BANK_LEN          , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_LO_DATA_REG_LAST_BANK_VALID        , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_LO_DATA_REG_WRITE_ON_RUN           , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_LO_DATA_REG_RUNNING                , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS           , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN       , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE   , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN       , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB           , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN       , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN       , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND           , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN       , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_4_MASKA              , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_4_MASKA_LEN          , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_4_MASKB              , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_4_MASKB_LEN          , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_5_MASKC              , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_5_MASKC_LEN          , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_5_MASKD              , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_5_MASKD_LEN          , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK
+           , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL      , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN  , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL      , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN  , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL      , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN  , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL      , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN  , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK      , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN  , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK     , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK      , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN  , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK     , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE     , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE     , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE     , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCPCI1_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_HI_DATA_REG_DATA                   , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_HI_DATA_REG_DATA_LEN               , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_LO_DATA_REG_DATA                   , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_LO_DATA_REG_DATA_LEN               , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_LO_DATA_REG_ADDRESS                , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_LO_DATA_REG_ADDRESS_LEN            , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_LO_DATA_REG_LAST_BANK              , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_LO_DATA_REG_LAST_BANK_LEN          , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_LO_DATA_REG_LAST_BANK_VALID        , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_LO_DATA_REG_WRITE_ON_RUN           , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_LO_DATA_REG_RUNNING                , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS           , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN       , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE   , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN       , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB           , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN       , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN       , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND           , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN       , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_4_MASKA              , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_4_MASKA_LEN          , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_4_MASKB              , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_4_MASKB_LEN          , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_5_MASKC              , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_5_MASKC_LEN          , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_5_MASKD              , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_5_MASKD_LEN          , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK
+           , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL      , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN  , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL      , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN  , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL      , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN  , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL      , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN  , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK      , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN  , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK     , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK      , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN  , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK     , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE     , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE     , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE     , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCPCI2_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_HI_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_DATA                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCXB_TRA1_TRACE_HI_DATA_REG_DATA                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCXB_TRA1_TRACE_HI_DATA_REG_DATA_LEN                 , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCXB_TRA1_TRACE_LO_DATA_REG_DATA                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TCXB_TRA1_TRACE_LO_DATA_REG_DATA_LEN                 , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCXB_TRA1_TRACE_LO_DATA_REG_ADDRESS                  , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCXB_TRA1_TRACE_LO_DATA_REG_ADDRESS_LEN              , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCXB_TRA1_TRACE_LO_DATA_REG_LAST_BANK                , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCXB_TRA1_TRACE_LO_DATA_REG_LAST_BANK_LEN            , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCXB_TRA1_TRACE_LO_DATA_REG_LAST_BANK_VALID          , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCXB_TRA1_TRACE_LO_DATA_REG_WRITE_ON_RUN             , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCXB_TRA1_TRACE_LO_DATA_REG_RUNNING                  , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TCXB_TRA1_TRACE_LO_DATA_REG_HOLD_ADDRESS             , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCXB_TRA1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN         , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE     , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63   , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNA             , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNB             , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_3_PATTERNC             , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_3_PATTERND             , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN         , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_4_MASKA                , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_4_MASKA_LEN            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_4_MASKB                , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_4_MASKB_LEN            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_5_MASKC                , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_5_MASKC_LEN            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_5_MASKD                , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_5_MASKD_LEN            , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION  , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK ,
+           1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL        , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL        , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL        , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL        , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK        , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK       , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN   , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK        , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK       , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN   , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE       , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE       , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE       , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCXB_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN   , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_NPU0_TEST_CERR_REGSEL                                , 56  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_REGSEL     );
+REG64_FLD( PU_NPU0_TEST_CERR_REGSEL_LEN                            , 2   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_REGSEL_LEN );
+REG64_FLD( PU_NPU0_TEST_CERR_BITSEL                                , 58  ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_BITSEL     );
+REG64_FLD( PU_NPU0_TEST_CERR_BITSEL_LEN                            , 6   ,
+           SH_UNT_PU_NPU0  , SH_ACS_SCOM     , SH_FLD_BITSEL_LEN );
+
+REG64_FLD( PU_NPU1_TEST_CERR_REGSEL                                , 56  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_REGSEL     );
+REG64_FLD( PU_NPU1_TEST_CERR_REGSEL_LEN                            , 2   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_REGSEL_LEN );
+REG64_FLD( PU_NPU1_TEST_CERR_BITSEL                                , 58  ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_BITSEL     );
+REG64_FLD( PU_NPU1_TEST_CERR_BITSEL_LEN                            , 6   ,
+           SH_UNT_PU_NPU1  , SH_ACS_SCOM     , SH_FLD_BITSEL_LEN );
+
+REG64_FLD( PU_NPU2_TEST_CERR_REGSEL                                , 56  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_REGSEL     );
+REG64_FLD( PU_NPU2_TEST_CERR_REGSEL_LEN                            , 2   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_REGSEL_LEN );
+REG64_FLD( PU_NPU2_TEST_CERR_BITSEL                                , 58  ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_BITSEL     );
+REG64_FLD( PU_NPU2_TEST_CERR_BITSEL_LEN                            , 6   ,
+           SH_UNT_PU_NPU2  , SH_ACS_SCOM     , SH_FLD_BITSEL_LEN );
+
+REG64_FLD( PU_TOD_CMD_REG_ADR                                      , 30  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADR        );
+REG64_FLD( PU_TOD_CMD_REG_ADR_LEN                                  , 31  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADR_LEN    );
+
+REG64_FLD( PU_TOD_DATA_RCV_REG_PCB                                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PCB        );
+REG64_FLD( PU_TOD_DATA_RCV_REG_PCB_LEN                             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_PCB_LEN    );
+
+REG64_FLD( PU_TOD_DATA_SND_REG_PCB                                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PCB        );
+REG64_FLD( PU_TOD_DATA_SND_REG_PCB_LEN                             , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PCB_LEN    );
+
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_HI_DATA_REG_DATA               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN           , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_DATA               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN           , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS            , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN        , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK          , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN      , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID    , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN       , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING            , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS       , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN   , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN ,
+           64  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 ,
+           0   , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA       , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN   , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB       , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN   , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC       , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN   , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND       , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN   , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA          , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN      , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB          , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN      , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC          , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN      , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD          , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN      , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL  , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL  , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL  , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK  , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK  , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_HI_DATA_REG_DATA               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN           , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_DATA               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA       );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN           , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS            , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS    );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN        , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK          , 42  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN      , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID    , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN       , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING            , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_RUNNING    );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS       , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN   , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN ,
+           64  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 ,
+           0   , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN ,
+           24  , SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA       , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA   );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN   , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB       , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB   );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN   , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC       , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC   );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN   , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND       , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND   );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN   , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA          , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA      );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN      , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB          , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB      );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN      , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC          , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC      );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN      , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD          , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD      );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN      , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD(
+    PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   ,
+    SH_UNT          , SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL  , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL  , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL  , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK  , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK  , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TRUST_CONTROL_FSP_TCE_ENABLE                         , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FSP_TCE_ENABLE );
+
+REG64_FLD( PEC_TUNNEL_BAR_REG_PE                                   , 0   ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE         );
+REG64_FLD( PEC_TUNNEL_BAR_REG_PE_LEN                               , 43  ,
+           SH_UNT_PEC      , SH_ACS_SCOM_RW  , SH_FLD_PE_LEN     );
+
+REG64_FLD( PU_TX_CTRL_STAT_REG_ENABLE_SCWR_TO_TXRF                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE_SCWR_TO_TXRF );
+REG64_FLD( PU_TX_CTRL_STAT_REG_DISABLE_ECC_COR_GXC_PSI             , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_ECC_COR_GXC_PSI );
+REG64_FLD( PU_TX_CTRL_STAT_REG_DISABLE_ECC_COR_TXRF_PSI            , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_ECC_COR_TXRF_PSI );
+REG64_FLD( PU_TX_CTRL_STAT_REG_CRC_MODE                            , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CRC_MODE   );
+REG64_FLD( PU_TX_CTRL_STAT_REG_CHIP_PERSONALISATION                , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CHIP_PERSONALISATION );
+REG64_FLD( PU_TX_CTRL_STAT_REG_ENABLE_STREAMING_MODE               , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ENABLE_STREAMING_MODE );
+REG64_FLD( PU_TX_CTRL_STAT_REG_CHIP_INTERFACEMODE                  , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CHIP_INTERFACEMODE );
+REG64_FLD( PU_TX_CTRL_STAT_REG_DISABLE_TIMEOUT_AND_RETRY           , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DISABLE_TIMEOUT_AND_RETRY );
+REG64_FLD( PU_TX_CTRL_STAT_REG_FENCE_IO_INTERFACE                  , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FENCE_IO_INTERFACE );
+REG64_FLD( PU_TX_CTRL_STAT_REG_FENCE_GX_INTERFACE                  , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FENCE_GX_INTERFACE );
+REG64_FLD( PU_TX_CTRL_STAT_REG_GX_ENABLE_OVERWRITE                 , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_GX_ENABLE_OVERWRITE );
+
+REG64_FLD( PU_TX_MASK_REG_PSITXINS_DATA_PCK                        , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSITXINS_DATA_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXINS_TZRTMP_PCK                      , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSITXINS_TZRTMP_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXEI_SHIFT_PCK                        , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSITXEI_SHIFT_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXEI_TRANSMIT_PCK                     , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSITXEI_TRANSMIT_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXINS_PARITY                          , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSITXINS_PARITY );
+REG64_FLD( PU_TX_MASK_REG_PSITXINS_UNDERRUN                        , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSITXINS_UNDERRUN );
+REG64_FLD( PU_TX_MASK_REG_PSITXBFF_DATA_PCK                        , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSITXBFF_DATA_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXBFF_TDO_PCK                         , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSITXBFF_TDO_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXBFF_TFC_PCK                         , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSITXBFF_TFC_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXLC_FSM_PCK                          , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSITXLC_FSM_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXLC_DATA_BUFF_PCK                    , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSITXLC_DATA_BUFF_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXLC_TDO_PCK                          , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSITXLC_TDO_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXLC_TADDR_PCK                        , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSITXLC_TADDR_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXLC_TCTRL_PCK                        , 13  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSITXLC_TCTRL_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXLC_UE_RF                            , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSITXLC_UE_RF );
+REG64_FLD( PU_TX_MASK_REG_PSITXLC_CE_RF                            , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSITXLC_CE_RF );
+REG64_FLD( PU_TX_MASK_REG_PSITXLC_UE_GX_2N                         , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSITXLC_UE_GX_2N );
+REG64_FLD( PU_TX_MASK_REG_PSITXLC_CE_GX_2N                         , 17  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSITXLC_CE_GX_2N );
+REG64_FLD( PU_TX_MASK_REG_PSITXLC_DATA_GXST2_PCK_2N                , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSITXLC_DATA_GXST2_PCK_2N );
+REG64_FLD( PU_TX_MASK_REG_PSITXLC_DATA_GXST3_PCK_2N                , 19  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSITXLC_DATA_GXST3_PCK_2N );
+REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TADDR_PCK                       , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRFACC_TADDR_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TCTRL_PCK                       , 21  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRFACC_TCTRL_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TDL_CMD_CTRL_PCK                , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRFACC_TDL_CMD_CTRL_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TDL_RSP_CTRL_PCK                , 23  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRFACC_TDL_RSP_CTRL_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TFSM_PCK                        , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRFACC_TFSM_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TDL_FSM_PCK                     , 25  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRFACC_TDL_FSM_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TXSC_PCK                        , 26  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRFACC_TXSC_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TDL_RETRY_ERR                   , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PSIRFACC_TDL_RETRY_ERR );
+
+REG64_FLD( PU_TX_PSI_CNTL_DRV_PATTERN_EN                           , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_DRV_PATTERN_EN );
+REG64_FLD( PU_TX_PSI_CNTL_PATTERN_SEL                              , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERN_SEL );
+REG64_FLD( PU_TX_PSI_CNTL_PATTERN_SEL_LEN                          , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PATTERN_SEL_LEN );
+REG64_FLD( PU_TX_PSI_CNTL_CLK_QUIESCE_P                            , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CLK_QUIESCE_P );
+REG64_FLD( PU_TX_PSI_CNTL_CLK_QUIESCE_P_LEN                        , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CLK_QUIESCE_P_LEN );
+REG64_FLD( PU_TX_PSI_CNTL_CLK_QUIESCE_N                            , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CLK_QUIESCE_N );
+REG64_FLD( PU_TX_PSI_CNTL_CLK_QUIESCE_N_LEN                        , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CLK_QUIESCE_N_LEN );
+REG64_FLD( PU_TX_PSI_CNTL_LANE_QUIESCE                             , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LANE_QUIESCE );
+REG64_FLD( PU_TX_PSI_CNTL_LANE_QUIESCE_LEN                         , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( PU_TX_PSI_CNTL_CLK_INVERT                               , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CLK_INVERT );
+REG64_FLD( PU_TX_PSI_CNTL_LANE_INVERT                              , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LANE_INVERT );
+REG64_FLD( PU_TX_PSI_CNTL_PDWN                                     , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PDWN       );
+REG64_FLD( PU_TX_PSI_CNTL_BIST_EN                                  , 13  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BIST_EN    );
+REG64_FLD( PU_TX_PSI_CNTL_SPARE                                    , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SPARE      );
+REG64_FLD( PU_TX_PSI_CNTL_SPARE_LEN                                , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_TX_PSI_MODE_PC_TEST                                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PC_TEST    );
+REG64_FLD( PU_TX_PSI_MODE_MAIN_SLICE_EN_ENC                        , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAIN_SLICE_EN_ENC );
+REG64_FLD( PU_TX_PSI_MODE_MAIN_SLICE_EN_ENC_LEN                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MAIN_SLICE_EN_ENC_LEN );
+REG64_FLD( PU_TX_PSI_MODE_PC_SLICE_EN_ENC                          , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PC_SLICE_EN_ENC );
+REG64_FLD( PU_TX_PSI_MODE_PC_SLICE_EN_ENC_LEN                      , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PC_SLICE_EN_ENC_LEN );
+REG64_FLD( PU_TX_PSI_MODE_SLEWCTL                                  , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SLEWCTL    );
+REG64_FLD( PU_TX_PSI_MODE_SLEWCTL_LEN                              , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SLEWCTL_LEN );
+REG64_FLD( PU_TX_PSI_MODE_PVTNL_ENC                                , 24  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PVTNL_ENC  );
+REG64_FLD( PU_TX_PSI_MODE_PVTNL_ENC_LEN                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PVTNL_ENC_LEN );
+REG64_FLD( PU_TX_PSI_MODE_PVTPL_ENC                                , 28  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PVTPL_ENC  );
+REG64_FLD( PU_TX_PSI_MODE_PVTPL_ENC_LEN                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PVTPL_ENC_LEN );
+
+REG64_FLD( PU_TX_PSI_STATUS_SPARE                                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SPARE      );
+REG64_FLD( PU_TX_PSI_STATUS_SPARE_LEN                              , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_TX_PSI_STATUS_BIST_ERROR                             , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BIST_ERROR );
+REG64_FLD( PU_TX_PSI_STATUS_BIST_ERROR_LEN                         , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BIST_ERROR_LEN );
+
+REG64_FLD( PU_TX_TO_RT_REG_TIMEOUT_VALUE                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TIMEOUT_VALUE );
+REG64_FLD( PU_TX_TO_RT_REG_TIMEOUT_VALUE_LEN                       , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TIMEOUT_VALUE_LEN );
+REG64_FLD( PU_TX_TO_RT_REG_RETRY_VALUE                             , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RETRY_VALUE );
+REG64_FLD( PU_TX_TO_RT_REG_RETRY_VALUE_LEN                         , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RETRY_VALUE_LEN );
+
+REG64_FLD( PU_UMAC_STATUS_CONTROL_CRB_READS_ENBL                   , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CRB_READS_ENBL );
+REG64_FLD( PU_UMAC_STATUS_CONTROL_CRB_READS_HALTED                 , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CRB_READS_HALTED );
+REG64_FLD( PU_UMAC_STATUS_CONTROL_IDLE                             , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IDLE       );
+REG64_FLD( PU_UMAC_STATUS_CONTROL_QUIESCE_REQUEST                  , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_QUIESCE_REQUEST );
+REG64_FLD( PU_UMAC_STATUS_CONTROL_QUIESCE_ACHEIVED                 , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_QUIESCE_ACHEIVED );
+REG64_FLD( PU_UMAC_STATUS_CONTROL_QUIESCE_FAILED                   , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_QUIESCE_FAILED );
+REG64_FLD( PU_UMAC_STATUS_CONTROL_QUIESCED                         , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_QUIESCED   );
+REG64_FLD( PU_UMAC_STATUS_CONTROL_PASTE_ADDR_ALIGN                 , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PASTE_ADDR_ALIGN );
+
+REG64_FLD( PU_VAS_BUFCTL_TOTAL_FREE_BUF_COUNT                      , 49  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TOTAL_FREE_BUF_COUNT );
+REG64_FLD( PU_VAS_BUFCTL_TOTAL_FREE_BUF_COUNT_LEN                  , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_TOTAL_FREE_BUF_COUNT_LEN );
+REG64_FLD( PU_VAS_BUFCTL_CONSUMED_BUF_COUNT                        , 57  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CONSUMED_BUF_COUNT );
+REG64_FLD( PU_VAS_BUFCTL_CONSUMED_BUF_COUNT_LEN                    , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CONSUMED_BUF_COUNT_LEN );
+
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_RESET                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CQ_CERR_RESET );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BITS                            , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CQ_CERR_BITS );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BITS_LEN                        , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CQ_CERR_BITS_LEN );
+
+REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRACE_DATA_LO                    , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SEL_RG_TRACE_DATA_LO );
+REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRACE_DATA_LO_LEN                , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SEL_RG_TRACE_DATA_LO_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRACE_DATA_HI                    , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SEL_RG_TRACE_DATA_HI );
+REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRACE_DATA_HI_LEN                , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SEL_RG_TRACE_DATA_HI_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRIGGERS_01                      , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SEL_RG_TRIGGERS_01 );
+REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRIGGERS_01_LEN                  , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SEL_RG_TRIGGERS_01_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRIGGERS_23                      , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SEL_RG_TRIGGERS_23 );
+REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRIGGERS_23_LEN                  , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SEL_RG_TRIGGERS_23_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_GROUP_SEL_LO                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_IN_TRACE_GROUP_SEL_LO );
+REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_GROUP_SEL_LO_LEN               , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_IN_TRACE_GROUP_SEL_LO_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_GROUP_SEL_HI                   , 11  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_IN_TRACE_GROUP_SEL_HI );
+REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_GROUP_SEL_HI_LEN               , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_IN_TRACE_GROUP_SEL_HI_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_TRIGGER_SEL_01                 , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_IN_TRACE_TRIGGER_SEL_01 );
+REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_TRIGGER_SEL_01_LEN             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_IN_TRACE_TRIGGER_SEL_01_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_TRIGGER_SEL_23                 , 17  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_IN_TRACE_TRIGGER_SEL_23 );
+REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_TRIGGER_SEL_23_LEN             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_IN_TRACE_TRIGGER_SEL_23_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_GROUP_SEL_LO                   , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RG_TRACE_GROUP_SEL_LO );
+REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_GROUP_SEL_LO_LEN               , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RG_TRACE_GROUP_SEL_LO_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_GROUP_SEL_HI                   , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RG_TRACE_GROUP_SEL_HI );
+REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_GROUP_SEL_HI_LEN               , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RG_TRACE_GROUP_SEL_HI_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_TRIGGER_SEL_01                 , 26  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RG_TRACE_TRIGGER_SEL_01 );
+REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_TRIGGER_SEL_01_LEN             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RG_TRACE_TRIGGER_SEL_01_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_TRIGGER_SEL_23                 , 29  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RG_TRACE_TRIGGER_SEL_23 );
+REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_TRIGGER_SEL_23_LEN             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RG_TRACE_TRIGGER_SEL_23_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_ENABLE_IN_TRACE                         , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE_IN_TRACE );
+REG64_FLD( PU_VAS_DBGNORTH_ENABLE_RG_TRACE                         , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE_RG_TRACE );
+REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_PMU_DATA_LO                      , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SEL_RG_PMU_DATA_LO );
+REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_PMU_DATA_LO_LEN                  , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SEL_RG_PMU_DATA_LO_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_PMU_DATA_HI                      , 38  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SEL_RG_PMU_DATA_HI );
+REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_PMU_DATA_HI_LEN                  , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SEL_RG_PMU_DATA_HI_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_ENABLE_IN_PMU_COUNTING                  , 40  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE_IN_PMU_COUNTING );
+REG64_FLD( PU_VAS_DBGNORTH_ENABLE_RG_PMU_COUNTING                  , 41  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE_RG_PMU_COUNTING );
+
+REG64_FLD( PU_VAS_DBGSOUTH_PASS_WC_INT_TRACE_DATA_LO               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PASS_WC_INT_TRACE_DATA_LO );
+REG64_FLD( PU_VAS_DBGSOUTH_PASS_WC_INT_TRACE_DATA_HI               , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PASS_WC_INT_TRACE_DATA_HI );
+REG64_FLD( PU_VAS_DBGSOUTH_PASS_CQ_INT_TRACE_DATA_LO               , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PASS_CQ_INT_TRACE_DATA_LO );
+REG64_FLD( PU_VAS_DBGSOUTH_PASS_CQ_INT_TRACE_DATA_HI               , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PASS_CQ_INT_TRACE_DATA_HI );
+REG64_FLD( PU_VAS_DBGSOUTH_PASS_WC_INT_TRACE_TRIG_01               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PASS_WC_INT_TRACE_TRIG_01 );
+REG64_FLD( PU_VAS_DBGSOUTH_PASS_WC_INT_TRACE_TRIG_23               , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PASS_WC_INT_TRACE_TRIG_23 );
+REG64_FLD( PU_VAS_DBGSOUTH_PASS_CQ_INT_TRACE_TRIG_01               , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PASS_CQ_INT_TRACE_TRIG_01 );
+REG64_FLD( PU_VAS_DBGSOUTH_PASS_CQ_INT_TRACE_TRIG_23               , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PASS_CQ_INT_TRACE_TRIG_23 );
+REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_LO                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EG_TRACE_GROUP_SEL_LO );
+REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_LO_LEN               , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EG_TRACE_GROUP_SEL_LO_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_HI                   , 11  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EG_TRACE_GROUP_SEL_HI );
+REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_HI_LEN               , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EG_TRACE_GROUP_SEL_HI_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_01                 , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EG_TRACE_TRIGGER_SEL_01 );
+REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_01_LEN             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EG_TRACE_TRIGGER_SEL_01_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_23                 , 17  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EG_TRACE_TRIGGER_SEL_23 );
+REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_23_LEN             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_EG_TRACE_TRIGGER_SEL_23_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_GROUP_SEL_LO                   , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WC_TRACE_GROUP_SEL_LO );
+REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_GROUP_SEL_LO_LEN               , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WC_TRACE_GROUP_SEL_LO_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_GROUP_SEL_HI                   , 23  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WC_TRACE_GROUP_SEL_HI );
+REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_GROUP_SEL_HI_LEN               , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WC_TRACE_GROUP_SEL_HI_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_TRIGGER_SEL_01                 , 26  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WC_TRACE_TRIGGER_SEL_01 );
+REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_TRIGGER_SEL_01_LEN             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WC_TRACE_TRIGGER_SEL_01_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_TRIGGER_SEL_23                 , 29  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WC_TRACE_TRIGGER_SEL_23 );
+REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_TRIGGER_SEL_23_LEN             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WC_TRACE_TRIGGER_SEL_23_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_GROUP_SEL_LO                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CQ_TRACE_GROUP_SEL_LO );
+REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_GROUP_SEL_LO_LEN               , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CQ_TRACE_GROUP_SEL_LO_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_GROUP_SEL_HI                   , 35  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CQ_TRACE_GROUP_SEL_HI );
+REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_GROUP_SEL_HI_LEN               , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CQ_TRACE_GROUP_SEL_HI_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_TRIGGER_SEL_01                 , 38  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CQ_TRACE_TRIGGER_SEL_01 );
+REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_TRIGGER_SEL_01_LEN             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CQ_TRACE_TRIGGER_SEL_01_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_TRIGGER_SEL_23                 , 41  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CQ_TRACE_TRIGGER_SEL_23 );
+REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_TRIGGER_SEL_23_LEN             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CQ_TRACE_TRIGGER_SEL_23_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_ENABLE_EG_TRACE                         , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE_EG_TRACE );
+REG64_FLD( PU_VAS_DBGSOUTH_ENABLE_WC_TRACE                         , 45  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE_WC_TRACE );
+REG64_FLD( PU_VAS_DBGSOUTH_ENABLE_CQ_TRACE                         , 46  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE_CQ_TRACE );
+REG64_FLD( PU_VAS_DBGSOUTH_PASS_WC_INT_PMU_DATA_LO                 , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PASS_WC_INT_PMU_DATA_LO );
+REG64_FLD( PU_VAS_DBGSOUTH_PASS_WC_INT_PMU_DATA_HI                 , 49  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PASS_WC_INT_PMU_DATA_HI );
+REG64_FLD( PU_VAS_DBGSOUTH_PASS_CQ_INT_PMU_DATA_LO                 , 50  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PASS_CQ_INT_PMU_DATA_LO );
+REG64_FLD( PU_VAS_DBGSOUTH_PASS_CQ_INT_PMU_DATA_HI                 , 51  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PASS_CQ_INT_PMU_DATA_HI );
+REG64_FLD( PU_VAS_DBGSOUTH_ENABLE_EG_PMU_COUNTING                  , 52  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE_EG_PMU_COUNTING );
+REG64_FLD( PU_VAS_DBGSOUTH_ENABLE_WC_PMU_COUNTING                  , 53  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE_WC_PMU_COUNTING );
+REG64_FLD( PU_VAS_DBGSOUTH_ENABLE_CQ_PMU_COUNTING                  , 54  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ENABLE_CQ_PMU_COUNTING );
+
+REG64_FLD( PU_VAS_DBGTRIG_TRACE_BUS_BITS_64_87                     , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_TRACE_BUS_BITS_64_87 );
+REG64_FLD( PU_VAS_DBGTRIG_TRACE_BUS_BITS_64_87_LEN                 , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_TRACE_BUS_BITS_64_87_LEN );
+REG64_FLD( PU_VAS_DBGTRIG_TRACE_BUS_TRIGGER_BITS                   , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_TRACE_BUS_TRIGGER_BITS );
+REG64_FLD( PU_VAS_DBGTRIG_TRACE_BUS_TRIGGER_BITS_LEN               , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RO  , SH_FLD_TRACE_BUS_TRIGGER_BITS_LEN );
+
+REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_RESET                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_EG_CERR_RESET );
+REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BITS                            , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_EG_CERR_BITS );
+REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BITS_LEN                        , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_EG_CERR_BITS_LEN );
+
+REG64_FLD( PU_VAS_ERRINJ_ECC_ERR_INJ_WC_ENA                        , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ECC_ERR_INJ_WC_ENA );
+REG64_FLD( PU_VAS_ERRINJ_ECC_ERR_INJ_WC_TYP                        , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ECC_ERR_INJ_WC_TYP );
+REG64_FLD( PU_VAS_ERRINJ_ECC_ERR_INJ_WC_FRQ                        , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ECC_ERR_INJ_WC_FRQ );
+REG64_FLD( PU_VAS_ERRINJ_ECC_ERR_INJ_WC_SEL                        , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ECC_ERR_INJ_WC_SEL );
+REG64_FLD( PU_VAS_ERRINJ_ECC_ERR_INJ_WC_SEL_LEN                    , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ECC_ERR_INJ_WC_SEL_LEN );
+REG64_FLD( PU_VAS_ERRINJ_ECC_ERR_INJ_EG_ENA                        , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ECC_ERR_INJ_EG_ENA );
+REG64_FLD( PU_VAS_ERRINJ_ECC_ERR_INJ_EG_TYP                        , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ECC_ERR_INJ_EG_TYP );
+REG64_FLD( PU_VAS_ERRINJ_ECC_ERR_INJ_EG_FRQ                        , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ECC_ERR_INJ_EG_FRQ );
+REG64_FLD( PU_VAS_ERRINJ_ECC_ERR_INJ_EG_SEL                        , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ECC_ERR_INJ_EG_SEL );
+
+REG64_FLD( PU_VAS_FIR_ACTION0_REG_ACTION0                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACTION0    );
+REG64_FLD( PU_VAS_FIR_ACTION0_REG_ACTION0_LEN                      , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_VAS_FIR_ACTION1_REG_ACTION1                          , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACTION1    );
+REG64_FLD( PU_VAS_FIR_ACTION1_REG_ACTION1_LEN                      , 48  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_VAS_FIR_MASK_REG_EG_LOGIC_HW_ERROR                   , 0   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_EG_LOGIC_HW_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_IN_LOGIC_HW_ERROR                   , 1   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_IN_LOGIC_HW_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_LOGIC_HW_ERROR                   , 2   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_LOGIC_HW_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_WC_LOGIC_HW_ERROR                   , 3   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_WC_LOGIC_HW_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_RG_LOGIC_HW_ERROR                   , 4   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RG_LOGIC_HW_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_PARITY_ERROR                  , 5   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_PARITY_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_RD_ADDR_ERROR                 , 6   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_RD_ADDR_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_WR_ADDR_ERROR                 , 7   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_WR_ADDR_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_EG_ECC_CE_ERROR                     , 8   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_EG_ECC_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_IN_ECC_CE_ERROR                     , 9   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_IN_ECC_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_ECC_CE_ERROR                     , 10  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_ECC_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_WC_ECC_CE_ERROR                     , 11  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_WC_ECC_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_RG_ECC_CE_ERROR                     , 12  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RG_ECC_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_OB_CE_ERROR                   , 13  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_OB_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_OB_UE_ERROR                   , 14  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_OB_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_MASTER_FSM_HANG               , 15  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_MASTER_FSM_HANG );
+REG64_FLD( PU_VAS_FIR_MASK_REG_EG_ECC_UE_ERROR                     , 16  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_EG_ECC_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_IN_ECC_UE_ERROR                     , 17  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_IN_ECC_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_ECC_UE_ERROR                     , 18  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_ECC_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_WC_ECC_UE_ERROR                     , 19  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_WC_ECC_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_RG_ECC_UE_ERROR                     , 20  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RG_ECC_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_IN_PARITY_ERROR                     , 21  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_IN_PARITY_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_IN_SW_CAST_ERROR                    , 22  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_IN_SW_CAST_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_EG_ECC_SUE_ERROR                    , 24  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_EG_ECC_SUE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_IN_ECC_SUE_ERROR                    , 25  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_IN_ECC_SUE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_ECC_SUE_ERROR                    , 26  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_ECC_SUE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_WC_ECC_SUE_ERROR                    , 27  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_WC_ECC_SUE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_RG_ECC_SUE_ERROR                    , 28  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RG_ECC_SUE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_RD_LINK_ERROR                 , 29  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_RD_LINK_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_WR_LINK_ERROR                 , 30  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_WR_LINK_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_LINK_ABORT                    , 31  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_LINK_ABORT );
+REG64_FLD( PU_VAS_FIR_MASK_REG_MMIO_HYP_RD_ADDR_ERR                , 32  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MMIO_HYP_RD_ADDR_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_MMIO_OS_RD_ADDR_ERR                 , 33  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MMIO_OS_RD_ADDR_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_MMIO_HYP_WR_ADDR_ERR                , 34  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MMIO_HYP_WR_ADDR_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_MMIO_OS_WR_ADDR_ERR                 , 35  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MMIO_OS_WR_ADDR_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_MMIO_NON8B_HYP_ERR                  , 36  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MMIO_NON8B_HYP_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_MMIO_NON8B_OS_ERR                   , 37  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MMIO_NON8B_OS_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_WM_WIN_NOT_OPEN_ERR                 , 38  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_WM_WIN_NOT_OPEN_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_WM_MULTIHIT_ERR                     , 39  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_WM_MULTIHIT_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_PG_MIG_DISABLED_ERR                 , 40  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PG_MIG_DISABLED_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_PG_MIG_SIZE_MISMATCH_ERR            , 41  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PG_MIG_SIZE_MISMATCH_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_NOTIFY_FAILED_ERR                   , 42  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_NOTIFY_FAILED_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_WR_MON_NOT_DISABLED_ERR             , 43  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_WR_MON_NOT_DISABLED_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_REJECTED_PASTE_CMD                  , 44  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_REJECTED_PASTE_CMD );
+REG64_FLD( PU_VAS_FIR_MASK_REG_DATA_HANG_DETECTED                  , 45  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DATA_HANG_DETECTED );
+REG64_FLD( PU_VAS_FIR_MASK_REG_INCOMING_PB_PARITY_ERR              , 46  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INCOMING_PB_PARITY_ERR );
+
+REG64_FLD( PU_VAS_FIR_REG_EG_LOGIC_HW_ERROR                        , 0   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_EG_LOGIC_HW_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_IN_LOGIC_HW_ERROR                        , 1   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_IN_LOGIC_HW_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_LOGIC_HW_ERROR                        , 2   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_LOGIC_HW_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_WC_LOGIC_HW_ERROR                        , 3   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_WC_LOGIC_HW_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_RG_LOGIC_HW_ERROR                        , 4   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RG_LOGIC_HW_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_PB_PARITY_ERROR                       , 5   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_PARITY_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_PB_RD_ADDR_ERROR                      , 6   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_RD_ADDR_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_PB_WR_ADDR_ERROR                      , 7   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_WR_ADDR_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_EG_ECC_CE_ERROR                          , 8   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_EG_ECC_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_IN_ECC_CE_ERROR                          , 9   ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_IN_ECC_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_ECC_CE_ERROR                          , 10  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_ECC_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_WC_ECC_CE_ERROR                          , 11  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_WC_ECC_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_RG_ECC_CE_ERROR                          , 12  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RG_ECC_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_PB_OB_CE_ERROR                        , 13  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_OB_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_PB_OB_UE_ERROR                        , 14  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_OB_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_PB_MASTER_FSM_HANG                    , 15  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_MASTER_FSM_HANG );
+REG64_FLD( PU_VAS_FIR_REG_EG_ECC_UE_ERROR                          , 16  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_EG_ECC_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_IN_ECC_UE_ERROR                          , 17  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_IN_ECC_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_ECC_UE_ERROR                          , 18  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_ECC_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_WC_ECC_UE_ERROR                          , 19  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_WC_ECC_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_RG_ECC_UE_ERROR                          , 20  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RG_ECC_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_IN_PARITY_ERROR                          , 21  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_IN_PARITY_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_IN_SW_CAST_ERROR                         , 22  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_IN_SW_CAST_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_EG_ECC_SUE_ERROR                         , 24  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_EG_ECC_SUE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_IN_ECC_SUE_ERROR                         , 25  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_IN_ECC_SUE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_ECC_SUE_ERROR                         , 26  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_ECC_SUE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_WC_ECC_SUE_ERROR                         , 27  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_WC_ECC_SUE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_RG_ECC_SUE_ERROR                         , 28  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_RG_ECC_SUE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_PB_RD_LINK_ERROR                      , 29  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_RD_LINK_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_PB_WR_LINK_ERROR                      , 30  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_WR_LINK_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_PB_LINK_ABORT                         , 31  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_LINK_ABORT );
+REG64_FLD( PU_VAS_FIR_REG_MMIO_HYP_RD_ADDR_ERR                     , 32  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MMIO_HYP_RD_ADDR_ERR );
+REG64_FLD( PU_VAS_FIR_REG_MMIO_OS_RD_ADDR_ERR                      , 33  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MMIO_OS_RD_ADDR_ERR );
+REG64_FLD( PU_VAS_FIR_REG_MMIO_HYP_WR_ADDR_ERR                     , 34  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MMIO_HYP_WR_ADDR_ERR );
+REG64_FLD( PU_VAS_FIR_REG_MMIO_OS_WR_ADDR_ERR                      , 35  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MMIO_OS_WR_ADDR_ERR );
+REG64_FLD( PU_VAS_FIR_REG_MMIO_NON8B_HYP_ERR                       , 36  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MMIO_NON8B_HYP_ERR );
+REG64_FLD( PU_VAS_FIR_REG_MMIO_NON8B_OS_ERR                        , 37  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_MMIO_NON8B_OS_ERR );
+REG64_FLD( PU_VAS_FIR_REG_WM_WIN_NOT_OPEN_ERR                      , 38  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_WM_WIN_NOT_OPEN_ERR );
+REG64_FLD( PU_VAS_FIR_REG_WM_MULTIHIT_ERR                          , 39  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_WM_MULTIHIT_ERR );
+REG64_FLD( PU_VAS_FIR_REG_PG_MIG_DISABLED_ERR                      , 40  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PG_MIG_DISABLED_ERR );
+REG64_FLD( PU_VAS_FIR_REG_PG_MIG_SIZE_MISMATCH_ERR                 , 41  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_PG_MIG_SIZE_MISMATCH_ERR );
+REG64_FLD( PU_VAS_FIR_REG_NOTIFY_FAILED_ERR                        , 42  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_NOTIFY_FAILED_ERR );
+REG64_FLD( PU_VAS_FIR_REG_WR_MON_NOT_DISABLED_ERR                  , 43  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_WR_MON_NOT_DISABLED_ERR );
+REG64_FLD( PU_VAS_FIR_REG_REJECTED_PASTE_CMD                       , 44  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_REJECTED_PASTE_CMD );
+REG64_FLD( PU_VAS_FIR_REG_DATA_HANG_DETECTED                       , 45  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_DATA_HANG_DETECTED );
+REG64_FLD( PU_VAS_FIR_REG_INCOMING_PB_PARITY_ERR                   , 46  ,
+           SH_UNT          , SH_ACS_SCOM2_OR , SH_FLD_INCOMING_PB_PARITY_ERR );
+
+REG64_FLD( PU_VAS_FIR_WOF_REG_WOF                                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF        );
+REG64_FLD( PU_VAS_FIR_WOF_REG_WOF_LEN                              , 48  ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LEN    );
+
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_RESET                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IN_CERR_RESET );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BITS                            , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IN_CERR_BITS );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BITS_LEN                        , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_IN_CERR_BITS_LEN );
+
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_4VS64                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MISC_CTL_4VS64 );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_ACCEPT_PASTE                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MISC_CTL_ACCEPT_PASTE );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_ENABLE_WRMON                    , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MISC_CTL_ENABLE_WRMON );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_INVALIDATE_CAM_LOC              , 47  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MISC_CTL_INVALIDATE_CAM_LOC );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_INVALIDATE_CAM_ALL              , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MISC_CTL_INVALIDATE_CAM_ALL );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_CAM_LOCATION                    , 49  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MISC_CTL_CAM_LOCATION );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_CAM_LOCATION_LEN                , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MISC_CTL_CAM_LOCATION_LEN );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_RG_IS_IDLE                      , 59  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MISC_CTL_RG_IS_IDLE );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_IN_IS_IDLE                      , 60  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MISC_CTL_IN_IS_IDLE );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_WC_IS_IDLE                      , 61  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MISC_CTL_WC_IS_IDLE );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_CQ_IS_IDLE                      , 62  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MISC_CTL_CQ_IS_IDLE );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_EG_IS_IDLE                      , 63  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MISC_CTL_EG_IS_IDLE );
+
+REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_INIT                            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MMIO_CTL_INIT );
+REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_COMP                            , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MMIO_CTL_COMP );
+REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_OPTYPE                          , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MMIO_CTL_OPTYPE );
+REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_ACTYPE                          , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MMIO_CTL_ACTYPE );
+REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_UNUSED                          , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MMIO_CTL_UNUSED );
+REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_UNUSED_LEN                      , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MMIO_CTL_UNUSED_LEN );
+REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_OFFSET                          , 36  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MMIO_CTL_OFFSET );
+REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_OFFSET_LEN                      , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MMIO_CTL_OFFSET_LEN );
+REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_WINID                           , 48  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MMIO_CTL_WINID );
+REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_WINID_LEN                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_MMIO_CTL_WINID_LEN );
+
+REG64_FLD( PU_VAS_MMIO_BASE_ADDR_BAR                               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BAR        );
+REG64_FLD( PU_VAS_MMIO_BASE_ADDR_BAR_LEN                           , 31  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BAR_LEN    );
+
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_EPSILON                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBCFG_0_EPSILON );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_EPSILON_LEN                       , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBCFG_0_EPSILON_LEN );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_HANG_POLL_MAX_CNT                 , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBCFG_0_HANG_POLL_MAX_CNT );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_HANG_POLL_MAX_CNT_LEN             , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBCFG_0_HANG_POLL_MAX_CNT_LEN );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_UNUSED1                           , 11  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBCFG_0_UNUSED1 );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_UNUSED1_LEN                       , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBCFG_0_UNUSED1_LEN );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_HANG_NX_MAX_CNT                   , 15  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBCFG_0_HANG_NX_MAX_CNT );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_HANG_NX_MAX_CNT_LEN               , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBCFG_0_HANG_NX_MAX_CNT_LEN );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_UNUSED2                           , 19  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBCFG_0_UNUSED2 );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_UNUSED2_LEN                       , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBCFG_0_UNUSED2_LEN );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_UNUSED3                           , 26  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBCFG_0_UNUSED3 );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_UNUSED3_LEN                       , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBCFG_0_UNUSED3_LEN );
+
+REG64_FLD( PU_VAS_PBCFG1_DISABLE_LN_WR                             , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DISABLE_LN_WR );
+REG64_FLD( PU_VAS_PBCFG1_DISABLE_G_WR                              , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DISABLE_G_WR );
+REG64_FLD( PU_VAS_PBCFG1_DISABLE_VG_WR                             , 2   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DISABLE_VG_WR );
+REG64_FLD( PU_VAS_PBCFG1_DISABLE_NN_WR                             , 3   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DISABLE_NN_WR );
+REG64_FLD( PU_VAS_PBCFG1_DISABLE_LN_RD                             , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DISABLE_LN_RD );
+REG64_FLD( PU_VAS_PBCFG1_DISABLE_G_RD                              , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DISABLE_G_RD );
+REG64_FLD( PU_VAS_PBCFG1_DISABLE_VG_RD                             , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DISABLE_VG_RD );
+REG64_FLD( PU_VAS_PBCFG1_DISABLE_NN_RD                             , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DISABLE_NN_RD );
+REG64_FLD( PU_VAS_PBCFG1_PBCFG_1_UNUSED1                           , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBCFG_1_UNUSED1 );
+REG64_FLD( PU_VAS_PBCFG1_PBCFG_1_UNUSED1_LEN                       , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBCFG_1_UNUSED1_LEN );
+REG64_FLD( PU_VAS_PBCFG1_RD_GO_M_QOS                               , 12  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RD_GO_M_QOS );
+REG64_FLD( PU_VAS_PBCFG1_ADDR_BAR_MODE                             , 13  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_ADDR_BAR_MODE );
+REG64_FLD( PU_VAS_PBCFG1_SKIP_G                                    , 14  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_SKIP_G     );
+REG64_FLD( PU_VAS_PBCFG1_HANG_SM_ON_ARE                            , 15  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HANG_SM_ON_ARE );
+REG64_FLD( PU_VAS_PBCFG1_HANG_SM_ON_LINK_FAIL                      , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_HANG_SM_ON_LINK_FAIL );
+REG64_FLD( PU_VAS_PBCFG1_CFG_PUMP_MODE                             , 17  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CFG_PUMP_MODE );
+REG64_FLD( PU_VAS_PBCFG1_DMA_WR_NOT_INJ                            , 18  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_WR_NOT_INJ );
+REG64_FLD( PU_VAS_PBCFG1_DMA_PART_WR_NOT_INJ                       , 19  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_PART_WR_NOT_INJ );
+REG64_FLD( PU_VAS_PBCFG1_DMA_RD_VG_RST_TMASK                       , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_RD_VG_RST_TMASK );
+REG64_FLD( PU_VAS_PBCFG1_DMA_RD_VG_RST_TMASK_LEN                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_RD_VG_RST_TMASK_LEN );
+REG64_FLD( PU_VAS_PBCFG1_DMA_WR_VG_RST_TMASK                       , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_WR_VG_RST_TMASK );
+REG64_FLD( PU_VAS_PBCFG1_DMA_WR_VG_RST_TMASK_LEN                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_WR_VG_RST_TMASK_LEN );
+REG64_FLD( PU_VAS_PBCFG1_PBCFG_1_UNUSED2                           , 36  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBCFG_1_UNUSED2 );
+REG64_FLD( PU_VAS_PBCFG1_PBCFG_1_UNUSED2_LEN                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PBCFG_1_UNUSED2_LEN );
+
+REG64_FLD( PU_VAS_PGMIG1_PGMIGR1_VAL                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR1_VAL );
+REG64_FLD( PU_VAS_PGMIG1_PGMIGR1_BAR                               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR1_BAR );
+REG64_FLD( PU_VAS_PGMIG1_PGMIGR1_BAR_LEN                           , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR1_BAR_LEN );
+REG64_FLD( PU_VAS_PGMIG1_PGMIGR1_PGSZ                              , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR1_PGSZ );
+REG64_FLD( PU_VAS_PGMIG1_PGMIGR1_PGSZ_LEN                          , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR1_PGSZ_LEN );
+
+REG64_FLD( PU_VAS_PGMIG2_PGMIGR2_VAL                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR2_VAL );
+REG64_FLD( PU_VAS_PGMIG2_PGMIGR2_BAR                               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR2_BAR );
+REG64_FLD( PU_VAS_PGMIG2_PGMIGR2_BAR_LEN                           , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR2_BAR_LEN );
+REG64_FLD( PU_VAS_PGMIG2_PGMIGR2_PGSZ                              , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR2_PGSZ );
+REG64_FLD( PU_VAS_PGMIG2_PGMIGR2_PGSZ_LEN                          , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR2_PGSZ_LEN );
+
+REG64_FLD( PU_VAS_PGMIG3_PGMIGR3_VAL                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR3_VAL );
+REG64_FLD( PU_VAS_PGMIG3_PGMIGR3_BAR                               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR3_BAR );
+REG64_FLD( PU_VAS_PGMIG3_PGMIGR3_BAR_LEN                           , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR3_BAR_LEN );
+REG64_FLD( PU_VAS_PGMIG3_PGMIGR3_PGSZ                              , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR3_PGSZ );
+REG64_FLD( PU_VAS_PGMIG3_PGMIGR3_PGSZ_LEN                          , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR3_PGSZ_LEN );
+
+REG64_FLD( PU_VAS_PGMIG4_PGMIGR4_VAL                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR4_VAL );
+REG64_FLD( PU_VAS_PGMIG4_PGMIGR4_BAR                               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR4_BAR );
+REG64_FLD( PU_VAS_PGMIG4_PGMIGR4_BAR_LEN                           , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR4_BAR_LEN );
+REG64_FLD( PU_VAS_PGMIG4_PGMIGR4_PGSZ                              , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR4_PGSZ );
+REG64_FLD( PU_VAS_PGMIG4_PGMIGR4_PGSZ_LEN                          , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR4_PGSZ_LEN );
+
+REG64_FLD( PU_VAS_PGMIG5_PGMIGR5_VAL                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR5_VAL );
+REG64_FLD( PU_VAS_PGMIG5_PGMIGR5_BAR                               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR5_BAR );
+REG64_FLD( PU_VAS_PGMIG5_PGMIGR5_BAR_LEN                           , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR5_BAR_LEN );
+REG64_FLD( PU_VAS_PGMIG5_PGMIGR5_PGSZ                              , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR5_PGSZ );
+REG64_FLD( PU_VAS_PGMIG5_PGMIGR5_PGSZ_LEN                          , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR5_PGSZ_LEN );
+
+REG64_FLD( PU_VAS_PGMIG6_PGMIGR6_VAL                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR6_VAL );
+REG64_FLD( PU_VAS_PGMIG6_PGMIGR6_BAR                               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR6_BAR );
+REG64_FLD( PU_VAS_PGMIG6_PGMIGR6_BAR_LEN                           , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR6_BAR_LEN );
+REG64_FLD( PU_VAS_PGMIG6_PGMIGR6_PGSZ                              , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR6_PGSZ );
+REG64_FLD( PU_VAS_PGMIG6_PGMIGR6_PGSZ_LEN                          , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR6_PGSZ_LEN );
+
+REG64_FLD( PU_VAS_PGMIG7_PGMIGR7_VAL                               , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR7_VAL );
+REG64_FLD( PU_VAS_PGMIG7_PGMIGR7_BAR                               , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR7_BAR );
+REG64_FLD( PU_VAS_PGMIG7_PGMIGR7_BAR_LEN                           , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR7_BAR_LEN );
+REG64_FLD( PU_VAS_PGMIG7_PGMIGR7_PGSZ                              , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR7_PGSZ );
+REG64_FLD( PU_VAS_PGMIG7_PGMIGR7_PGSZ_LEN                          , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PGMIGR7_PGSZ_LEN );
+
+REG64_FLD( PU_VAS_PMCNTL_PU_BIT_ENABLES                            , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PU_BIT_ENABLES );
+REG64_FLD( PU_VAS_PMCNTL_PU_BIT_ENABLES_LEN                        , 32  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_PU_BIT_ENABLES_LEN );
+
+REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_RESET                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RG_CERR_RESET );
+REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BITS                            , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RG_CERR_BITS );
+REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BITS_LEN                        , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RG_CERR_BITS_LEN );
+
+REG64_FLD( PU_VAS_RMABAR_RMA_BAR                                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RMA_BAR    );
+REG64_FLD( PU_VAS_RMABAR_RMA_BAR_LEN                               , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RMA_BAR_LEN );
+
+REG64_FLD( PU_VAS_RMABARM_RMA_BAR_MASK                             , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RMA_BAR_MASK );
+REG64_FLD( PU_VAS_RMABARM_RMA_BAR_MASK_LEN                         , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_RMA_BAR_MASK_LEN );
+
+REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_DISABLE_WC_SCRUB              , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SOUTH_CTL_DISABLE_WC_SCRUB );
+REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_DISABLE_WC_ECC                , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SOUTH_CTL_DISABLE_WC_ECC );
+REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_EG_SINGLE_THREAD              , 2   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SOUTH_CTL_EG_SINGLE_THREAD );
+REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_EG_WM_CTX_UPDATE_MODE         , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SOUTH_CTL_EG_WM_CTX_UPDATE_MODE );
+
+REG64_FLD( PU_VAS_UWMBAR_BASE_ADDR                                 , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BASE_ADDR  );
+REG64_FLD( PU_VAS_UWMBAR_BASE_ADDR_LEN                             , 28  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BASE_ADDR_LEN );
+
+REG64_FLD( PU_VAS_WCBSBAR_WC_BS_BAR                                , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WC_BS_BAR  );
+REG64_FLD( PU_VAS_WCBSBAR_WC_BS_BAR_LEN                            , 33  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WC_BS_BAR_LEN );
+
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_RESET                           , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WC_CERR_RESET );
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BITS                            , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WC_CERR_BITS );
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BITS_LEN                        , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WC_CERR_BITS_LEN );
+
+REG64_FLD( PU_VAS_WCMBAR_BASE_ADDR                                 , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BASE_ADDR  );
+REG64_FLD( PU_VAS_WCMBAR_BASE_ADDR_LEN                             , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_BASE_ADDR_LEN );
+
+REG64_FLD( PU_VAS_WRMON0BAR_WRMON_BAR0_BA                          , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR0_BA );
+REG64_FLD( PU_VAS_WRMON0BAR_WRMON_BAR0_BA_LEN                      , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR0_BA_LEN );
+REG64_FLD( PU_VAS_WRMON0BAR_WRMON_BAR0_SIZE                        , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR0_SIZE );
+REG64_FLD( PU_VAS_WRMON0BAR_WRMON_BAR0_SIZE_LEN                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR0_SIZE_LEN );
+
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_VAL                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP0_VAL );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TTYPEDIS                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP0_TTYPEDIS );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TTYPEDIS_LEN                , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP0_TTYPEDIS_LEN );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_ENADTTYPE                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP0_ENADTTYPE );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TTYPE                       , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP0_TTYPE );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TTYPE_LEN                   , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP0_TTYPE_LEN );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TSIZE                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP0_TSIZE );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TSIZE_LEN                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP0_TSIZE_LEN );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TTYPEMSK                    , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP0_TTYPEMSK );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TTYPEMSK_LEN                , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP0_TTYPEMSK_LEN );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TSIZEMSK                    , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP0_TSIZEMSK );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TSIZEMSK_LEN                , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP0_TSIZEMSK_LEN );
+
+REG64_FLD( PU_VAS_WRMON0WID_WRMON_WID0                             , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_WID0 );
+REG64_FLD( PU_VAS_WRMON0WID_WRMON_WID0_LEN                         , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_WID0_LEN );
+
+REG64_FLD( PU_VAS_WRMON1BAR_WRMON_BAR1_BA                          , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR1_BA );
+REG64_FLD( PU_VAS_WRMON1BAR_WRMON_BAR1_BA_LEN                      , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR1_BA_LEN );
+REG64_FLD( PU_VAS_WRMON1BAR_WRMON_BAR1_SIZE                        , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR1_SIZE );
+REG64_FLD( PU_VAS_WRMON1BAR_WRMON_BAR1_SIZE_LEN                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR1_SIZE_LEN );
+
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_VAL                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP1_VAL );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TTYPEDIS                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP1_TTYPEDIS );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TTYPEDIS_LEN                , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP1_TTYPEDIS_LEN );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_ENADTTYPE                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP1_ENADTTYPE );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TTYPE                       , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP1_TTYPE );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TTYPE_LEN                   , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP1_TTYPE_LEN );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TSIZE                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP1_TSIZE );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TSIZE_LEN                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP1_TSIZE_LEN );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TTYPEMSK                    , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP1_TTYPEMSK );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TTYPEMSK_LEN                , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP1_TTYPEMSK_LEN );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TSIZEMSK                    , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP1_TSIZEMSK );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TSIZEMSK_LEN                , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP1_TSIZEMSK_LEN );
+
+REG64_FLD( PU_VAS_WRMON1WID_WRMON_WID1                             , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_WID1 );
+REG64_FLD( PU_VAS_WRMON1WID_WRMON_WID1_LEN                         , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_WID1_LEN );
+
+REG64_FLD( PU_VAS_WRMON2BAR_WRMON_BAR2_BA                          , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR2_BA );
+REG64_FLD( PU_VAS_WRMON2BAR_WRMON_BAR2_BA_LEN                      , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR2_BA_LEN );
+REG64_FLD( PU_VAS_WRMON2BAR_WRMON_BAR2_SIZE                        , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR2_SIZE );
+REG64_FLD( PU_VAS_WRMON2BAR_WRMON_BAR2_SIZE_LEN                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR2_SIZE_LEN );
+
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_VAL                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP2_VAL );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TTYPEDIS                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP2_TTYPEDIS );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TTYPEDIS_LEN                , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP2_TTYPEDIS_LEN );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_ENADTTYPE                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP2_ENADTTYPE );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TTYPE                       , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP2_TTYPE );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TTYPE_LEN                   , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP2_TTYPE_LEN );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TSIZE                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP2_TSIZE );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TSIZE_LEN                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP2_TSIZE_LEN );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TTYPEMSK                    , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP2_TTYPEMSK );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TTYPEMSK_LEN                , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP2_TTYPEMSK_LEN );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TSIZEMSK                    , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP2_TSIZEMSK );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TSIZEMSK_LEN                , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP2_TSIZEMSK_LEN );
+
+REG64_FLD( PU_VAS_WRMON2WID_WRMON_WID2                             , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_WID2 );
+REG64_FLD( PU_VAS_WRMON2WID_WRMON_WID2_LEN                         , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_WID2_LEN );
+
+REG64_FLD( PU_VAS_WRMON3BAR_WRMON_BAR3_BA                          , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR3_BA );
+REG64_FLD( PU_VAS_WRMON3BAR_WRMON_BAR3_BA_LEN                      , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR3_BA_LEN );
+REG64_FLD( PU_VAS_WRMON3BAR_WRMON_BAR3_SIZE                        , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR3_SIZE );
+REG64_FLD( PU_VAS_WRMON3BAR_WRMON_BAR3_SIZE_LEN                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR3_SIZE_LEN );
+
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_VAL                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP3_VAL );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TTYPEDIS                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP3_TTYPEDIS );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TTYPEDIS_LEN                , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP3_TTYPEDIS_LEN );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_ENADTTYPE                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP3_ENADTTYPE );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TTYPE                       , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP3_TTYPE );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TTYPE_LEN                   , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP3_TTYPE_LEN );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TSIZE                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP3_TSIZE );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TSIZE_LEN                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP3_TSIZE_LEN );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TTYPEMSK                    , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP3_TTYPEMSK );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TTYPEMSK_LEN                , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP3_TTYPEMSK_LEN );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TSIZEMSK                    , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP3_TSIZEMSK );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TSIZEMSK_LEN                , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP3_TSIZEMSK_LEN );
+
+REG64_FLD( PU_VAS_WRMON3WID_WRMON_WID3                             , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_WID3 );
+REG64_FLD( PU_VAS_WRMON3WID_WRMON_WID3_LEN                         , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_WID3_LEN );
+
+REG64_FLD( PU_VAS_WRMON4BAR_WRMON_BAR4_BA                          , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR4_BA );
+REG64_FLD( PU_VAS_WRMON4BAR_WRMON_BAR4_BA_LEN                      , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR4_BA_LEN );
+REG64_FLD( PU_VAS_WRMON4BAR_WRMON_BAR4_SIZE                        , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR4_SIZE );
+REG64_FLD( PU_VAS_WRMON4BAR_WRMON_BAR4_SIZE_LEN                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR4_SIZE_LEN );
+
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_VAL                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP4_VAL );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TTYPEDIS                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP4_TTYPEDIS );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TTYPEDIS_LEN                , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP4_TTYPEDIS_LEN );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_ENADTTYPE                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP4_ENADTTYPE );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TTYPE                       , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP4_TTYPE );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TTYPE_LEN                   , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP4_TTYPE_LEN );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TSIZE                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP4_TSIZE );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TSIZE_LEN                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP4_TSIZE_LEN );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TTYPEMSK                    , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP4_TTYPEMSK );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TTYPEMSK_LEN                , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP4_TTYPEMSK_LEN );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TSIZEMSK                    , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP4_TSIZEMSK );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TSIZEMSK_LEN                , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP4_TSIZEMSK_LEN );
+
+REG64_FLD( PU_VAS_WRMON4WID_WRMON_WID4                             , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_WID4 );
+REG64_FLD( PU_VAS_WRMON4WID_WRMON_WID4_LEN                         , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_WID4_LEN );
+
+REG64_FLD( PU_VAS_WRMON5BAR_WRMON_BAR5_BA                          , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR5_BA );
+REG64_FLD( PU_VAS_WRMON5BAR_WRMON_BAR5_BA_LEN                      , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR5_BA_LEN );
+REG64_FLD( PU_VAS_WRMON5BAR_WRMON_BAR5_SIZE                        , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR5_SIZE );
+REG64_FLD( PU_VAS_WRMON5BAR_WRMON_BAR5_SIZE_LEN                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR5_SIZE_LEN );
+
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_VAL                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP5_VAL );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TTYPEDIS                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP5_TTYPEDIS );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TTYPEDIS_LEN                , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP5_TTYPEDIS_LEN );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_ENADTTYPE                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP5_ENADTTYPE );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TTYPE                       , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP5_TTYPE );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TTYPE_LEN                   , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP5_TTYPE_LEN );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TSIZE                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP5_TSIZE );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TSIZE_LEN                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP5_TSIZE_LEN );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TTYPEMSK                    , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP5_TTYPEMSK );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TTYPEMSK_LEN                , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP5_TTYPEMSK_LEN );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TSIZEMSK                    , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP5_TSIZEMSK );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TSIZEMSK_LEN                , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP5_TSIZEMSK_LEN );
+
+REG64_FLD( PU_VAS_WRMON5WID_WRMON_WID5                             , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_WID5 );
+REG64_FLD( PU_VAS_WRMON5WID_WRMON_WID5_LEN                         , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_WID5_LEN );
+
+REG64_FLD( PU_VAS_WRMON6BAR_WRMON_BAR6_BA                          , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR6_BA );
+REG64_FLD( PU_VAS_WRMON6BAR_WRMON_BAR6_BA_LEN                      , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR6_BA_LEN );
+REG64_FLD( PU_VAS_WRMON6BAR_WRMON_BAR6_SIZE                        , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR6_SIZE );
+REG64_FLD( PU_VAS_WRMON6BAR_WRMON_BAR6_SIZE_LEN                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR6_SIZE_LEN );
+
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_VAL                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP6_VAL );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TTYPEDIS                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP6_TTYPEDIS );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TTYPEDIS_LEN                , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP6_TTYPEDIS_LEN );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_ENADTTYPE                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP6_ENADTTYPE );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TTYPE                       , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP6_TTYPE );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TTYPE_LEN                   , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP6_TTYPE_LEN );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TSIZE                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP6_TSIZE );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TSIZE_LEN                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP6_TSIZE_LEN );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TTYPEMSK                    , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP6_TTYPEMSK );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TTYPEMSK_LEN                , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP6_TTYPEMSK_LEN );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TSIZEMSK                    , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP6_TSIZEMSK );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TSIZEMSK_LEN                , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP6_TSIZEMSK_LEN );
+
+REG64_FLD( PU_VAS_WRMON6WID_WRMON_WID6                             , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_WID6 );
+REG64_FLD( PU_VAS_WRMON6WID_WRMON_WID6_LEN                         , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_WID6_LEN );
+
+REG64_FLD( PU_VAS_WRMON7BAR_WRMON_BAR7_BA                          , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR7_BA );
+REG64_FLD( PU_VAS_WRMON7BAR_WRMON_BAR7_BA_LEN                      , 44  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR7_BA_LEN );
+REG64_FLD( PU_VAS_WRMON7BAR_WRMON_BAR7_SIZE                        , 60  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR7_SIZE );
+REG64_FLD( PU_VAS_WRMON7BAR_WRMON_BAR7_SIZE_LEN                    , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_BAR7_SIZE_LEN );
+
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_VAL                         , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP7_VAL );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TTYPEDIS                    , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP7_TTYPEDIS );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TTYPEDIS_LEN                , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP7_TTYPEDIS_LEN );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_ENADTTYPE                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP7_ENADTTYPE );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TTYPE                       , 9   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP7_TTYPE );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TTYPE_LEN                   , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP7_TTYPE_LEN );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TSIZE                       , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP7_TSIZE );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TSIZE_LEN                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP7_TSIZE_LEN );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TTYPEMSK                    , 24  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP7_TTYPEMSK );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TTYPEMSK_LEN                , 7   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP7_TTYPEMSK_LEN );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TSIZEMSK                    , 31  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP7_TSIZEMSK );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TSIZEMSK_LEN                , 8   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_CMP7_TSIZEMSK_LEN );
+
+REG64_FLD( PU_VAS_WRMON7WID_WRMON_WID7                             , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_WID7 );
+REG64_FLD( PU_VAS_WRMON7WID_WRMON_WID7_LEN                         , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_WRMON_WID7_LEN );
+
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH0_TIMER_ENBL             , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH0_TIMER_ENBL );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH0_REF_DIV                , 1   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH0_REF_DIV );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH0_REF_DIV_LEN            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH0_REF_DIV_LEN );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH1_TIMER_ENBL             , 5   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH1_TIMER_ENBL );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH1_REF_DIV                , 6   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH1_REF_DIV );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH1_REF_DIV_LEN            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH1_REF_DIV_LEN );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH2_TIMER_ENBL             , 10  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH2_TIMER_ENBL );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH2_REF_DIV                , 11  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH2_REF_DIV );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH2_REF_DIV_LEN            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH2_REF_DIV_LEN );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH3_TIMER_ENBL             , 15  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH3_TIMER_ENBL );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH3_REF_DIV                , 16  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH3_REF_DIV );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH3_REF_DIV_LEN            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH3_REF_DIV_LEN );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH4_TIMER_ENBL             , 20  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH4_TIMER_ENBL );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH4_REF_DIV                , 21  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH4_REF_DIV );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH4_REF_DIV_LEN            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_CH4_REF_DIV_LEN );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_DMA_TIMER_ENBL             , 25  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_TIMER_ENBL );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_DMA_TIMER_REF_DIV          , 26  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_TIMER_REF_DIV );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_DMA_TIMER_REF_DIV_LEN      , 4   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DMA_TIMER_REF_DIV_LEN );
+
+REG64_FLD( PU_WATER_MARK_REGISTER_B_WATERMARK_REG_0                , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WATERMARK_REG_0 );
+REG64_FLD( PU_WATER_MARK_REGISTER_B_WATERMARK_REG_0_LEN            , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WATERMARK_REG_0_LEN );
+REG64_FLD( PU_WATER_MARK_REGISTER_B_PEEK_DATA1_0                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_WATER_MARK_REGISTER_B_PEEK_DATA1_0_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_WATER_MARK_REGISTER_B_LBUS_PARITY_ERR1_0             , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_WATER_MARK_REGISTER_C_WATERMARK_REG_1                , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WATERMARK_REG_1 );
+REG64_FLD( PU_WATER_MARK_REGISTER_C_WATERMARK_REG_1_LEN            , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WATERMARK_REG_1_LEN );
+REG64_FLD( PU_WATER_MARK_REGISTER_C_PEEK_DATA1_1                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_WATER_MARK_REGISTER_C_PEEK_DATA1_1_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_WATER_MARK_REGISTER_C_LBUS_PARITY_ERR1_1             , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_WATER_MARK_REGISTER_D_WATERMARK_REG_2                , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WATERMARK_REG_2 );
+REG64_FLD( PU_WATER_MARK_REGISTER_D_WATERMARK_REG_2_LEN            , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WATERMARK_REG_2_LEN );
+REG64_FLD( PU_WATER_MARK_REGISTER_D_PEEK_DATA1_2                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_WATER_MARK_REGISTER_D_PEEK_DATA1_2_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_WATER_MARK_REGISTER_D_LBUS_PARITY_ERR1_2             , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_WATER_MARK_REGISTER_E_WATERMARK_REG_3                , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WATERMARK_REG_3 );
+REG64_FLD( PU_WATER_MARK_REGISTER_E_WATERMARK_REG_3_LEN            , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WATERMARK_REG_3_LEN );
+REG64_FLD( PU_WATER_MARK_REGISTER_E_PEEK_DATA1_3                   , 32  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_WATER_MARK_REGISTER_E_PEEK_DATA1_3_LEN               , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_WATER_MARK_REGISTER_E_LBUS_PARITY_ERR1_3             , 40  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( PU_XSCOM_BASE_REG_FBC                                   , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC        );
+REG64_FLD( PU_XSCOM_BASE_REG_FBC_LEN                               , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_LEN    );
+REG64_FLD( PU_XSCOM_BASE_REG_FBC_RESET                             , 61  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_RESET  );
+REG64_FLD( PU_XSCOM_BASE_REG_FBC_DISABLE                           , 62  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_DISABLE );
+REG64_FLD( PU_XSCOM_BASE_REG_FBC_DISABLE_LOCAL_SHORTCUT            , 63  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FBC_DISABLE_LOCAL_SHORTCUT );
+
+REG64_FLD( PU_XSCOM_DAT0_REG_DAT0                                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DAT0       );
+REG64_FLD( PU_XSCOM_DAT0_REG_DAT0_LEN                              , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DAT0_LEN   );
+
+REG64_FLD( PU_XSCOM_DAT1_REG_DAT1                                  , 0   ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DAT1       );
+REG64_FLD( PU_XSCOM_DAT1_REG_DAT1_LEN                              , 64  ,
+           SH_UNT          , SH_ACS_SCOM_RW  , SH_FLD_DAT1_LEN   );
+
+REG64_FLD( PU_XSCOM_ERR_REG_ADDRESS                                , 0   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_ADDRESS    );
+REG64_FLD( PU_XSCOM_ERR_REG_TSIZE                                  , 1   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_TSIZE      );
+REG64_FLD( PU_XSCOM_ERR_REG_RC_TTAG_PAR                            , 2   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_RC_TTAG_PAR );
+REG64_FLD( PU_XSCOM_ERR_REG_CR_TTAG_PAR                            , 3   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_CR_TTAG_PAR );
+REG64_FLD( PU_XSCOM_ERR_REG_CR_ATAG_PAR                            , 4   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_CR_ATAG_PAR );
+REG64_FLD( PU_XSCOM_ERR_REG_RC_ADDR_PAR                            , 5   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_RC_ADDR_PAR );
+REG64_FLD( PU_XSCOM_ERR_REG_PB_ECC_CE                              , 8   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_PB_ECC_CE  );
+REG64_FLD( PU_XSCOM_ERR_REG_PB_ECC_UE                              , 9   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_PB_ECC_UE  );
+REG64_FLD( PU_XSCOM_ERR_REG_PB_ECC_SUE                             , 10  ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_PB_ECC_SUE );
+REG64_FLD( PU_XSCOM_ERR_REG_RTAG_PARITY                            , 11  ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_RTAG_PARITY );
+REG64_FLD( PU_XSCOM_ERR_REG_CRESP_HANG                             , 12  ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_CRESP_HANG );
+REG64_FLD( PU_XSCOM_ERR_REG_PIB_HANG                               , 13  ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_PIB_HANG   );
+REG64_FLD( PU_XSCOM_ERR_REG_PBDATA_HANG                            , 14  ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_PBDATA_HANG );
+REG64_FLD( PU_XSCOM_ERR_REG_ADS_HANG                               , 15  ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_ADS_HANG   );
+REG64_FLD( PU_XSCOM_ERR_REG_FSM_PERR                               , 16  ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_FSM_PERR   );
+REG64_FLD( PU_XSCOM_ERR_REG_SPARE0                                 , 17  ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_SPARE0     );
+REG64_FLD( PU_XSCOM_ERR_REG_SPARE1                                 , 18  ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_SPARE1     );
+REG64_FLD( PU_XSCOM_ERR_REG_UNEXPECT_DATA                          , 19  ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_UNEXPECT_DATA );
+REG64_FLD( PU_XSCOM_ERR_REG_ILL_CRESP                              , 20  ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_ILL_CRESP  );
+
+REG64_FLD( PU_XSCOM_LOG_REG_CMD_IN_PROG                            , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMD_IN_PROG );
+REG64_FLD( PU_XSCOM_LOG_REG_CMD_STATUS                             , 1   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMD_STATUS );
+REG64_FLD( PU_XSCOM_LOG_REG_CMD_STATUS_LEN                         , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_CMD_STATUS_LEN );
+REG64_FLD( PU_XSCOM_LOG_REG_WRITE_CMD                              , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_WRITE_CMD  );
+REG64_FLD( PU_XSCOM_LOG_REG_ADDR_TAG                               , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADDR_TAG   );
+REG64_FLD( PU_XSCOM_LOG_REG_ADDR_TAG_LEN                           , 22  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_ADDR_TAG_LEN );
+REG64_FLD( PU_XSCOM_LOG_REG_THR_ID                                 , 27  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_THR_ID     );
+REG64_FLD( PU_XSCOM_LOG_REG_THR_ID_LEN                             , 3   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_THR_ID_LEN );
+REG64_FLD( PU_XSCOM_LOG_REG_PIB_COMPONENT_BUSY                     , 31  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_COMPONENT_BUSY );
+REG64_FLD( PU_XSCOM_LOG_REG_PIB_ADDR                               , 33  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_ADDR   );
+REG64_FLD( PU_XSCOM_LOG_REG_PIB_ADDR_LEN                           , 31  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_PIB_ADDR_LEN );
+
+REG64_FLD( PU_XSCOM_MODE_REG_SPARE                                 , 0   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SPARE      );
+REG64_FLD( PU_XSCOM_MODE_REG_SPARE_LEN                             , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR1                     , 4   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BAR_PIB_ON_ERROR1 );
+REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR2                     , 5   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BAR_PIB_ON_ERROR2 );
+REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR3                     , 6   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BAR_PIB_ON_ERROR3 );
+REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR4                     , 7   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BAR_PIB_ON_ERROR4 );
+REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR5                     , 8   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BAR_PIB_ON_ERROR5 );
+REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR6                     , 9   ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BAR_PIB_ON_ERROR6 );
+REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR7                     , 10  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_BAR_PIB_ON_ERROR7 );
+REG64_FLD( PU_XSCOM_MODE_REG_HANG_PIB_RESET                        , 11  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HANG_PIB_RESET );
+REG64_FLD( PU_XSCOM_MODE_REG_HANG_RESET                            , 12  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_HANG_RESET );
+REG64_FLD( PU_XSCOM_MODE_REG_RESET_ON_PARITY                       , 13  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_RESET_ON_PARITY );
+REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR1                  , 14  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FREEZE_LOG_ON_ERROR1 );
+REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR2                  , 15  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FREEZE_LOG_ON_ERROR2 );
+REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR3                  , 16  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FREEZE_LOG_ON_ERROR3 );
+REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR4                  , 17  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FREEZE_LOG_ON_ERROR4 );
+REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR5                  , 18  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FREEZE_LOG_ON_ERROR5 );
+REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR6                  , 19  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FREEZE_LOG_ON_ERROR6 );
+REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR7                  , 20  ,
+           SH_UNT          , SH_ACS_SCOM     , SH_FLD_FREEZE_LOG_ON_ERROR7 );
+
+REG64_FLD( PU_XSCOM_RCVED_STAT_REG_DONE                            , 0   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_DONE       );
+REG64_FLD( PU_XSCOM_RCVED_STAT_REG_RESULT                          , 1   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_RESULT     );
+REG64_FLD( PU_XSCOM_RCVED_STAT_REG_RESULT_LEN                      , 3   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_RESULT_LEN );
+REG64_FLD( PU_XSCOM_RCVED_STAT_REG_COREID                          , 4   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_COREID     );
+REG64_FLD( PU_XSCOM_RCVED_STAT_REG_COREID_LEN                      , 6   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_COREID_LEN );
+REG64_FLD( PU_XSCOM_RCVED_STAT_REG_THRID                           , 10  ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_THRID      );
+REG64_FLD( PU_XSCOM_RCVED_STAT_REG_THRID_LEN                       , 3   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_THRID_LEN  );
+REG64_FLD( PU_XSCOM_RCVED_STAT_REG_DEST_GROUPID                    , 13  ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_DEST_GROUPID );
+REG64_FLD( PU_XSCOM_RCVED_STAT_REG_DEST_GROUPID_LEN                , 4   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_DEST_GROUPID_LEN );
+REG64_FLD( PU_XSCOM_RCVED_STAT_REG_DEST_CHIPID                     , 17  ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_DEST_CHIPID );
+REG64_FLD( PU_XSCOM_RCVED_STAT_REG_DEST_CHIPID_LEN                 , 3   ,
+           SH_UNT          , SH_ACS_SCOM_WCLRREG, SH_FLD_DEST_CHIPID_LEN );
+
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE1                  , 0   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE2                  , 2   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE3                  , 8   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   ,
+           SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2_LEN );
+
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_RATE1                  , 0   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_RATE2                  , 2   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_RATE3                  , 8   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   ,
+           SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2_LEN );
+
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_RATE1                  , 0   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_RATE2                  , 2   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_RATE3                  , 8   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   ,
+           SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2_LEN );
+
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_RATE1                  , 0   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_RATE2                  , 2   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_RATE3                  , 8   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   ,
+           SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2_LEN );
+
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_RATE1                  , 0   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_RATE2                  , 2   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_RATE3                  , 8   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   ,
+           SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2_LEN );
+
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_RATE1                  , 0   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_RATE2                  , 2   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_RATE3                  , 8   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   ,
+           SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2_LEN );
+
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_RATE1                  , 0   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_RATE2                  , 2   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_RATE3                  , 8   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   ,
+           SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2_LEN );
+
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_RATE1                  , 0   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_RATE2                  , 2   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_RATE3                  , 8   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   ,
+           SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2_LEN );
+
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_RATE1                  , 0   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_RATE2                  , 2   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_RATE3                  , 8   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   ,
+           SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2_LEN );
+
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_RATE1                  , 0   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_RATE2                  , 2   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_RATE3                  , 8   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   ,
+           SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2_LEN );
+
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_RATE1                  , 0   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_RATE2                  , 2   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_RATE3                  , 8   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   ,
+           SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2_LEN );
+
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_RATE1                  , 0   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_RATE2                  , 2   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_RATE3                  , 8   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   ,
+           SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     , SH_FLD_FWD_PROG_RATE2_LEN );
+
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_BRAZOS                            , 0   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_BRAZOS     );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_MMIOSD                            , 1   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_MMIOSD     );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_BIG_RSP                           , 2   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_BIG_RSP    );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_CHOP1G                            , 3   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_CHOP1G     );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_DIS_NCNP                          , 4   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_DIS_NCNP   );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED1                           , 5   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_UNUSED1    );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED1_LEN                       , 11  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_UNUSED1_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TLBIE_DEC_RATE                    , 16  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_TLBIE_DEC_RATE );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TLBIE_DEC_RATE_LEN                , 8   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_TLBIE_DEC_RATE_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TLBIE_INC_RATE                    , 24  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_TLBIE_INC_RATE );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TLBIE_INC_RATE_LEN                , 8   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_TLBIE_INC_RATE_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TLBIE_CNT_THRESH                  , 32  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_TLBIE_CNT_THRESH );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TLBIE_CNT_THRESH_LEN              , 8   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_TLBIE_CNT_THRESH_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED2                           , 40  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_UNUSED2    );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_TIMEOUT                      , 41  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_PREF_TIMEOUT );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_TIMEOUT_LEN                  , 3   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_PREF_TIMEOUT_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_DEPTH                        , 44  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_PREF_DEPTH );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_DEPTH_LEN                    , 4   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_PREF_DEPTH_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH0                       , 48  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_PREF_THRSH0 );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH0_LEN                   , 4   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_PREF_THRSH0_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH1                       , 52  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_PREF_THRSH1 );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH1_LEN                   , 4   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_PREF_THRSH1_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH2                       , 56  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_PREF_THRSH2 );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH2_LEN                   , 4   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_PREF_THRSH2_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH3                       , 60  ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_PREF_THRSH3 );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH3_LEN                   , 4   ,
+           SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     , SH_FLD_PREF_THRSH3_LEN );
+
+#endif
+
diff --git a/src/ppe/importtemp/common/include/misc_scom_addresses_fld_fixes.H b/src/ppe/importtemp/common/include/misc_scom_addresses_fld_fixes.H
new file mode 100644
index 0000000..1271a7a
--- /dev/null
+++ b/src/ppe/importtemp/common/include/misc_scom_addresses_fld_fixes.H
@@ -0,0 +1,49 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/common/include/misc_scom_addresses_fld_fixes.H $ */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file misc_scom_addresses_fld_fixes.H
+/// @brief The *scom_addresses_fld.H files are generated form figtree,
+///        but the figree can be wrong.  This file is included in
+///        *_scom_addresses_fld.H and allows incorrect constants to be
+///        fixed manually.
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: ? <?>
+// *HWP Team: SAO
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#ifndef __MISC_SCOM_ADDRESSES_FLD_FIXES_H
+#define __MISC_SCOM_ADDRESSES_FLD_FIXES_H
+
+//Example
+//Copy the whole line from the *scom_addresses_fld.H file.  Then add FIX in front of REG
+//and add another paramter that is the new value you want.
+//
+//FIXREG64_FLD( PU_ALTD_CMD_REG_FBC_WITH_TM_QUIESCE, 24, SH_UNT, SH_ACS_SCOM, SH_FLD_FBC_WITH_TM_QUIESCE,
+//              12);
+
+
+#endif
diff --git a/src/ppe/importtemp/common/include/perv_scom_addresses.H b/src/ppe/importtemp/common/include/perv_scom_addresses.H
new file mode 100644
index 0000000..d43b264
--- /dev/null
+++ b/src/ppe/importtemp/common/include/perv_scom_addresses.H
@@ -0,0 +1,15467 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/common/include/perv_scom_addresses.H $     */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file perv_scom_addresses.H
+/// @brief  Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+/*---------------------------------------------------------------
+ *
+ *---------------------------------------------------------------
+ *
+ *  Issues:
+ *    MC regs with same address.        HW323435 (matteo)
+ *         Duplicate IOM registers.          HW320456 (designers)
+ *    OSC/perv regs same address.       HW323437
+ *    TOD reg same address.             HW323439
+ *    PHB registers need fixed.         HW320416  ( all regs commented out now )
+ *    IO0 registers need fixed.         HW320437
+ *
+ * Closed
+ *    PB.PB_PPE registers need fixed.   HW320435
+ *    EX05 registers need fixed.        HW320427  (9020) - L2 ring id's are incorrect
+ *    IOFPPE registers need fixed.      HW320424  (9020) - Investigate NULL scope
+ *    PEC addresses are wrong.          HW322598  (9020)
+ *    MC registers need fixed.          HW320433
+ *    VA.VA_NORTH registers need fixed. HW320436
+ *
+ * Format:
+ *
+ *  <UNIT>_<SUBUNIT>_<INSTANCE>_<REGISTER>_<ACCESS/TYPE>
+ *
+ *  Notes: Subunits are only added to make names unique when
+ *  there are name collisions.
+ *  Only units with more than one instance has instance numbers.
+ *  If there is only one, the instance number is omitted.
+ *
+ *  Instance numbers are chiplet id's for the PERV unit.  The
+ *  chiplet id's are mapped to their name and used instead of
+ *  instance numbers.  See bellow.
+ *
+ *  For registers with a single access type the type and access
+ *  methods are omitted.
+ *
+ *  For access types where all bits have the same access methods, the
+ *  access method is appended to the name.  If the access methods
+ *  are different for some bits, the access type is appended to the
+ *  name _SCOM instead of _RO.  The _RW(X) access method is omitted
+ *  and assumed to be default.
+ *
+ *  Valid units / subunits
+ *    PU                    : No unit chip level
+ *        MCD0[0..1]        : mcd subunit
+ *        PIB2OPB[0..1]     : PIB2OPB subunit
+ *        OTPROM[0..1]      : otprom subunit
+ *        NPU               : common npu subunit
+ *        NPU[0..2]         : Npu stacks 0 to 2
+ *          CTL             : Npu CTL subunit
+ *          DAT             : Npu DAT subunit
+ *          SM[0..3]        : Npu SM subunits
+ *          NTL[0..1]       : Npu NTL subunit
+ *    PERV                  : Pervasive
+ *        FSI2PIB           : subunit
+ *        FSISHIFT          : subunit
+ *        FSII2C            : subunit
+ *        FSB               : subunit
+ *    EX                    : Ex unit (1/2 quad, 2 cores)
+ *        L2                : L2 subunit
+ *        L3                : L3 subunit
+ *    PEC                   : PCI Pec unit
+ *        STACK0            : subunit
+ *        STACK1            : subunit
+ *        STACK2            : subunit
+ *    C                     : core
+ *    EQ                    : quad
+ *    OBUS                  : obus
+ *    CAPP                  : capp
+ *    MCBIST                : mcbist
+ *    MCA                   : mca
+ *    NVBUS                 : (not implemented yet)
+ *    PHB                   : (not implemented yet)
+ *    MI                    : (not implemented yet)
+ *    DMI                   : (not implemented yet)
+ *    MCS                   : (not implemented yet)
+ *    OCC                   : (not implemented yet)
+ *    PPE                   : (not implemented yet)
+ *    SBE                   : (not implemented yet)
+ *    XBUS                  : (not implemented yet)
+ *
+ * Pervasive instance names follow chiplet id.
+ *
+ * Instance/  | Chiplet
+ * Chiplet    | name
+ * -----------+-----------
+ * 0x00       | PIB
+ * 0x01       | TP
+ * 0x02       | N0
+ * 0x03       | N1
+ * 0x04       | N2
+ * 0x05       | N3
+ * 0x06       | XB
+ * 0x07       | MC01
+ * 0x08       | MC23
+ * 0x09       | OB0
+ * 0x0A       | OB1
+ * 0x0B       | OB2
+ * 0x0C       | OB3
+ * 0x0D       | PCI0
+ * 0x0E       | PCI1
+ * 0x0F       | PCI2
+ * 0x10       | EP00
+ * 0x11       | EP01
+ * 0x12       | EP02
+ * 0x13       | EP03
+ * 0x14       | EP04
+ * 0x15       | EP05
+ * 0x20       | EC00
+ * 0x21       | EC01
+ * 0x22       | EC02
+ * 0x23       | EC03
+ * 0x24       | EC04
+ * 0x25       | EC05
+ * 0x26       | EC06
+ * 0x27       | EC07
+ * 0x28       | EC08
+ * 0x29       | EC09
+ * 0x2A       | EC10
+ * 0x2B       | EC11
+ * 0x2C       | EC12
+ * 0x2D       | EC13
+ * 0x2E       | EC14
+ * 0x2F       | EC15
+ * 0x30       | EC16
+ * 0x31       | EC17
+ * 0x32       | EC18
+ * 0x33       | EC19
+ * 0x34       | EC20
+ * 0x35       | EC21
+ * 0x36       | EC22
+ * 0x37       | EC23
+ *
+ *
+ *---------------------------------------------------------------
+ *
+ * NOTES:
+ *
+ * there is a SPR ring that goes around the chip with an
+ * address(0:9)/tid(0:1) (thread id)/mfspr_data(0:63) and return mfspr_data_v/mfspr_data(0:63)
+ *
+ *    Add PU_<SUBUNITS>  (only if there are conflicts on these registers)
+ *       0x0001XXXX OTPROM
+ *       0x0002XXXX FSIM0
+ *       0x0003XXXX FSIM1
+ *       0x0004XXXX TOD
+ *       0x0005XXXX FSI_MBOX
+ *       0x0006XXXX OCI_BRIDGE
+ *       0x0007XXXX SPI_ADC
+ *       0x0008XXXX PIBMEM
+ *       0x0009XXXX ADU
+ *       0x000AXXXX I2CM
+ *       0x000BXXXX SBE_FIFO
+ *       0x000DXXXX PSU
+ *       0x000EXXXX SBE
+ *
+ * 0x0000100A for FSI2PIB  => PERV_FSI2PIB
+ * 0x00000Cxx for FSISHIFT =>  PERV_FSISHIFT
+ * 0x000018xx for FSI I2C =>  PERV_FSII2C
+ * 0x000024xx for FSI SBEFIFO => PERV_FSB
+ *
+ * 0x00000400 PEEK_TABLE
+ * 0x00000800 FSI_SLAVE
+ * 0x00000C00 FSI_SHIFT
+ * 0x00001000 FSI2PIB
+ * 0x00001400 FSI_SCRATCHPAD
+ * 0x00001800 FSI_I2CM
+ * 0x00002400 FSI_SBE_FIFO
+ *
+ * address fields
+ * 0xCCRPxxxx
+ *
+ * CC=chiplet
+ * R=always 0?
+ * P=port
+ *   0=gpregs
+ *   1=normal unit scom ring (exclude)
+ *   3=clock controller
+ *   4=firs
+ *   5=cpm
+ *
+ * =============================================================================
+ * Compiling
+ *
+ * Precompile the header to save time on subsquent compiles:
+ * g++ -I. -c scom_addresses.H
+ *
+ * Use these options to help reduce the binary size
+ * g++ -I. -Os -fdata-sections -ffunction-sections <file>.C -o <output> -Wl,--gc-sections
+ *
+ *
+ *---------------------------------------------------------------
+ */
+
+#include <const_common.H>
+
+
+#ifndef __PERV_SCOM_ADDRESSES_H
+#define __PERV_SCOM_ADDRESSES_H
+
+
+#include <scom_template_consts.H>
+#include <perv_scom_addresses_fixes.H>
+
+
+REG64( PERV_ASSIST_INTERRUPT_REG                               ,
+       RULL(0x000F0011), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_ASSIST_INTERRUPT_REG                            ,
+       RULL(0x010F0011), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_ASSIST_INTERRUPT_REG                            ,
+       RULL(0x020F0011), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_ASSIST_INTERRUPT_REG                            ,
+       RULL(0x030F0011), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_ASSIST_INTERRUPT_REG                            ,
+       RULL(0x040F0011), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_ASSIST_INTERRUPT_REG                            ,
+       RULL(0x050F0011), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_ASSIST_INTERRUPT_REG                            ,
+       RULL(0x060F0011), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x070F0011), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x080F0011), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_ASSIST_INTERRUPT_REG                           ,
+       RULL(0x090F0011), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_ASSIST_INTERRUPT_REG                           ,
+       RULL(0x0C0F0011), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x0D0F0011), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x0E0F0011), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x0F0F0011), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x100F0011), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x110F0011), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x120F0011), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x130F0011), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x140F0011), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x150F0011), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x200F0011), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x210F0011), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x220F0011), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x230F0011), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x240F0011), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x250F0011), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x260F0011), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x270F0011), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x280F0011), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x290F0011), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x2A0F0011), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x2B0F0011), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x2C0F0011), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x2D0F0011), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x2E0F0011), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x2F0F0011), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x300F0011), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x310F0011), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x320F0011), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x330F0011), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x340F0011), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x350F0011), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x360F0011), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_ASSIST_INTERRUPT_REG                          ,
+       RULL(0x370F0011), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_ATOMIC_LOCK_REG                                    ,
+       RULL(0x000F03FF), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_ATOMIC_LOCK_REG                                 ,
+       RULL(0x010F03FF), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_ATOMIC_LOCK_REG                                 ,
+       RULL(0x020F03FF), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_ATOMIC_LOCK_REG                                 ,
+       RULL(0x030F03FF), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_ATOMIC_LOCK_REG                                 ,
+       RULL(0x040F03FF), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_ATOMIC_LOCK_REG                                 ,
+       RULL(0x050F03FF), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_ATOMIC_LOCK_REG                                 ,
+       RULL(0x060F03FF), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_ATOMIC_LOCK_REG                               ,
+       RULL(0x070F03FF), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_ATOMIC_LOCK_REG                               ,
+       RULL(0x080F03FF), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_ATOMIC_LOCK_REG                                ,
+       RULL(0x090F03FF), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_ATOMIC_LOCK_REG                                ,
+       RULL(0x0C0F03FF), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_ATOMIC_LOCK_REG                               ,
+       RULL(0x0D0F03FF), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_ATOMIC_LOCK_REG                               ,
+       RULL(0x0E0F03FF), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_ATOMIC_LOCK_REG                               ,
+       RULL(0x0F0F03FF), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_ATOMIC_LOCK_REG                               ,
+       RULL(0x100F03FF), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_ATOMIC_LOCK_REG                               ,
+       RULL(0x110F03FF), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_ATOMIC_LOCK_REG                               ,
+       RULL(0x120F03FF), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_ATOMIC_LOCK_REG                               ,
+       RULL(0x130F03FF), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_ATOMIC_LOCK_REG                               ,
+       RULL(0x140F03FF), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_ATOMIC_LOCK_REG                               ,
+       RULL(0x150F03FF), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_ATOMIC_LOCK_REG                               ,
+       RULL(0x200F03FF), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_ATOMIC_LOCK_REG                               ,
+       RULL(0x210F03FF), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_ATOMIC_LOCK_REG                               ,
+       RULL(0x220F03FF), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_ATOMIC_LOCK_REG                               ,
+       RULL(0x230F03FF), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_ATOMIC_LOCK_REG                               ,
+       RULL(0x240F03FF), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_ATOMIC_LOCK_REG                               ,
+       RULL(0x250F03FF), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_ATOMIC_LOCK_REG                               ,
+       RULL(0x260F03FF), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_ATOMIC_LOCK_REG                               ,
+       RULL(0x270F03FF), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_ATOMIC_LOCK_REG                               ,
+       RULL(0x280F03FF), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_ATOMIC_LOCK_REG                               ,
+       RULL(0x290F03FF), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_ATOMIC_LOCK_REG                               ,
+       RULL(0x2A0F03FF), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_ATOMIC_LOCK_REG                               ,
+       RULL(0x2B0F03FF), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_ATOMIC_LOCK_REG                               ,
+       RULL(0x2C0F03FF), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_ATOMIC_LOCK_REG                               ,
+       RULL(0x2D0F03FF), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_ATOMIC_LOCK_REG                               ,
+       RULL(0x2E0F03FF), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_ATOMIC_LOCK_REG                               ,
+       RULL(0x2F0F03FF), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_ATOMIC_LOCK_REG                               ,
+       RULL(0x300F03FF), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_ATOMIC_LOCK_REG                               ,
+       RULL(0x310F03FF), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_ATOMIC_LOCK_REG                               ,
+       RULL(0x320F03FF), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_ATOMIC_LOCK_REG                               ,
+       RULL(0x330F03FF), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_ATOMIC_LOCK_REG                               ,
+       RULL(0x340F03FF), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_ATOMIC_LOCK_REG                               ,
+       RULL(0x350F03FF), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_ATOMIC_LOCK_REG                               ,
+       RULL(0x360F03FF), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_ATOMIC_LOCK_REG                               ,
+       RULL(0x370F03FF), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_ATTN_INTERRUPT_REG                                 ,
+       RULL(0x000F001A), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_ATTN_INTERRUPT_REG                              ,
+       RULL(0x010F001A), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_ATTN_INTERRUPT_REG                              ,
+       RULL(0x020F001A), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_ATTN_INTERRUPT_REG                              ,
+       RULL(0x030F001A), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_ATTN_INTERRUPT_REG                              ,
+       RULL(0x040F001A), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_ATTN_INTERRUPT_REG                              ,
+       RULL(0x050F001A), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_ATTN_INTERRUPT_REG                              ,
+       RULL(0x060F001A), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_ATTN_INTERRUPT_REG                            ,
+       RULL(0x070F001A), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_ATTN_INTERRUPT_REG                            ,
+       RULL(0x080F001A), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_ATTN_INTERRUPT_REG                             ,
+       RULL(0x090F001A), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_ATTN_INTERRUPT_REG                             ,
+       RULL(0x0C0F001A), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_ATTN_INTERRUPT_REG                            ,
+       RULL(0x0D0F001A), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_ATTN_INTERRUPT_REG                            ,
+       RULL(0x0E0F001A), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_ATTN_INTERRUPT_REG                            ,
+       RULL(0x0F0F001A), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_ATTN_INTERRUPT_REG                            ,
+       RULL(0x100F001A), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_ATTN_INTERRUPT_REG                            ,
+       RULL(0x110F001A), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_ATTN_INTERRUPT_REG                            ,
+       RULL(0x120F001A), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_ATTN_INTERRUPT_REG                            ,
+       RULL(0x130F001A), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_ATTN_INTERRUPT_REG                            ,
+       RULL(0x140F001A), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_ATTN_INTERRUPT_REG                            ,
+       RULL(0x150F001A), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_ATTN_INTERRUPT_REG                            ,
+       RULL(0x200F001A), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_ATTN_INTERRUPT_REG                            ,
+       RULL(0x210F001A), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_ATTN_INTERRUPT_REG                            ,
+       RULL(0x220F001A), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_ATTN_INTERRUPT_REG                            ,
+       RULL(0x230F001A), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_ATTN_INTERRUPT_REG                            ,
+       RULL(0x240F001A), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_ATTN_INTERRUPT_REG                            ,
+       RULL(0x250F001A), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_ATTN_INTERRUPT_REG                            ,
+       RULL(0x260F001A), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_ATTN_INTERRUPT_REG                            ,
+       RULL(0x270F001A), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_ATTN_INTERRUPT_REG                            ,
+       RULL(0x280F001A), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_ATTN_INTERRUPT_REG                            ,
+       RULL(0x290F001A), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_ATTN_INTERRUPT_REG                            ,
+       RULL(0x2A0F001A), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_ATTN_INTERRUPT_REG                            ,
+       RULL(0x2B0F001A), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_ATTN_INTERRUPT_REG                            ,
+       RULL(0x2C0F001A), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_ATTN_INTERRUPT_REG                            ,
+       RULL(0x2D0F001A), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_ATTN_INTERRUPT_REG                            ,
+       RULL(0x2E0F001A), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_ATTN_INTERRUPT_REG                            ,
+       RULL(0x2F0F001A), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_ATTN_INTERRUPT_REG                            ,
+       RULL(0x300F001A), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_ATTN_INTERRUPT_REG                            ,
+       RULL(0x310F001A), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_ATTN_INTERRUPT_REG                            ,
+       RULL(0x320F001A), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_ATTN_INTERRUPT_REG                            ,
+       RULL(0x330F001A), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_ATTN_INTERRUPT_REG                            ,
+       RULL(0x340F001A), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_ATTN_INTERRUPT_REG                            ,
+       RULL(0x350F001A), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_ATTN_INTERRUPT_REG                            ,
+       RULL(0x360F001A), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_ATTN_INTERRUPT_REG                            ,
+       RULL(0x370F001A), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_BIST                                               ,
+       RULL(0x0003000B), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_BIST                                            ,
+       RULL(0x0103000B), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_BIST                                            ,
+       RULL(0x0203000B), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_BIST                                            ,
+       RULL(0x0303000B), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_BIST                                            ,
+       RULL(0x0403000B), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_BIST                                            ,
+       RULL(0x0503000B), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_BIST                                            ,
+       RULL(0x0603000B), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_BIST                                          ,
+       RULL(0x0703000B), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_BIST                                          ,
+       RULL(0x0803000B), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_BIST                                           ,
+       RULL(0x0903000B), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_BIST                                           ,
+       RULL(0x0C03000B), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_BIST                                          ,
+       RULL(0x0D03000B), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_BIST                                          ,
+       RULL(0x0E03000B), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_BIST                                          ,
+       RULL(0x0F03000B), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_BIST                                          ,
+       RULL(0x1003000B), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_BIST                                          ,
+       RULL(0x1103000B), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_BIST                                          ,
+       RULL(0x1203000B), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_BIST                                          ,
+       RULL(0x1303000B), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_BIST                                          ,
+       RULL(0x1403000B), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_BIST                                          ,
+       RULL(0x1503000B), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_BIST                                          ,
+       RULL(0x2003000B), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_BIST                                          ,
+       RULL(0x2103000B), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_BIST                                          ,
+       RULL(0x2203000B), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_BIST                                          ,
+       RULL(0x2303000B), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_BIST                                          ,
+       RULL(0x2403000B), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_BIST                                          ,
+       RULL(0x2503000B), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_BIST                                          ,
+       RULL(0x2603000B), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_BIST                                          ,
+       RULL(0x2703000B), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_BIST                                          ,
+       RULL(0x2803000B), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_BIST                                          ,
+       RULL(0x2903000B), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_BIST                                          ,
+       RULL(0x2A03000B), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_BIST                                          ,
+       RULL(0x2B03000B), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_BIST                                          ,
+       RULL(0x2C03000B), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_BIST                                          ,
+       RULL(0x2D03000B), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_BIST                                          ,
+       RULL(0x2E03000B), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_BIST                                          ,
+       RULL(0x2F03000B), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_BIST                                          ,
+       RULL(0x3003000B), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_BIST                                          ,
+       RULL(0x3103000B), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_BIST                                          ,
+       RULL(0x3203000B), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_BIST                                          ,
+       RULL(0x3303000B), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_BIST                                          ,
+       RULL(0x3403000B), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_BIST                                          ,
+       RULL(0x3503000B), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_BIST                                          ,
+       RULL(0x3603000B), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_BIST                                          ,
+       RULL(0x3703000B), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_BIT_SEL_REG_2                                      ,
+       RULL(0x000F0008), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_BIT_SEL_REG_2                                  ,
+       RULL(0x000F0008), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_CBS_CS_FSI                                         ,
+       RULL(0x00002801), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_CBS_CS_FSI_BYTE                                    ,
+       RULL(0x00002804), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_CBS_CS_SCOM                                        ,
+       RULL(0x00050001), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_CBS_CS                                         ,
+       RULL(0x00050001), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_CBS_EL_FSI                                         ,
+       RULL(0x00002803), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_CBS_EL_FSI_BYTE                                    ,
+       RULL(0x0000280C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_CBS_EL_SCOM                                        ,
+       RULL(0x00050003), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_CBS_EL                                         ,
+       RULL(0x00050003), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_CBS_EL_HIST_FSI                                    ,
+       RULL(0x00002806), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_CBS_EL_HIST_FSI_BYTE                               ,
+       RULL(0x00002818), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_CBS_EL_HIST_SCOM                                   ,
+       RULL(0x00050006), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_CBS_EL_HIST                                    ,
+       RULL(0x00050006), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_CBS_TR_FSI                                         ,
+       RULL(0x00002802), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_CBS_TR_FSI_BYTE                                    ,
+       RULL(0x00002808), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_CBS_TR_SCOM                                        ,
+       RULL(0x00050002), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_CBS_TR                                         ,
+       RULL(0x00050002), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_CBS_TR_HIST_FSI                                    ,
+       RULL(0x00002805), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_CBS_TR_HIST_FSI_BYTE                               ,
+       RULL(0x00002814), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_CBS_TR_HIST_SCOM                                   ,
+       RULL(0x00050005), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_CBS_TR_HIST                                    ,
+       RULL(0x00050005), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_CC_ATOMIC_LOCK_REG                                 ,
+       RULL(0x000303FF), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_CC_ATOMIC_LOCK_REG                              ,
+       RULL(0x010303FF), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_CC_ATOMIC_LOCK_REG                              ,
+       RULL(0x020303FF), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_CC_ATOMIC_LOCK_REG                              ,
+       RULL(0x030303FF), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_CC_ATOMIC_LOCK_REG                              ,
+       RULL(0x040303FF), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_CC_ATOMIC_LOCK_REG                              ,
+       RULL(0x050303FF), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_CC_ATOMIC_LOCK_REG                              ,
+       RULL(0x060303FF), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x070303FF), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x080303FF), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_CC_ATOMIC_LOCK_REG                             ,
+       RULL(0x090303FF), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_CC_ATOMIC_LOCK_REG                             ,
+       RULL(0x0C0303FF), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x0D0303FF), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x0E0303FF), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x0F0303FF), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x100303FF), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x110303FF), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x120303FF), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x130303FF), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x140303FF), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x150303FF), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x200303FF), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x210303FF), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x220303FF), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x230303FF), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x240303FF), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x250303FF), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x260303FF), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x270303FF), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x280303FF), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x290303FF), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x2A0303FF), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x2B0303FF), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x2C0303FF), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x2D0303FF), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x2E0303FF), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x2F0303FF), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x300303FF), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x310303FF), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x320303FF), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x330303FF), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x340303FF), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x350303FF), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x360303FF), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CC_ATOMIC_LOCK_REG                            ,
+       RULL(0x370303FF), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_CC_PROTECT_MODE_REG                                ,
+       RULL(0x000303FE), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_CC_PROTECT_MODE_REG                             ,
+       RULL(0x010303FE), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_CC_PROTECT_MODE_REG                             ,
+       RULL(0x020303FE), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_CC_PROTECT_MODE_REG                             ,
+       RULL(0x030303FE), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_CC_PROTECT_MODE_REG                             ,
+       RULL(0x040303FE), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_CC_PROTECT_MODE_REG                             ,
+       RULL(0x050303FE), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_CC_PROTECT_MODE_REG                             ,
+       RULL(0x060303FE), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_CC_PROTECT_MODE_REG                           ,
+       RULL(0x070303FE), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_CC_PROTECT_MODE_REG                           ,
+       RULL(0x080303FE), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_CC_PROTECT_MODE_REG                            ,
+       RULL(0x090303FE), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_CC_PROTECT_MODE_REG                            ,
+       RULL(0x0C0303FE), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_CC_PROTECT_MODE_REG                           ,
+       RULL(0x0D0303FE), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_CC_PROTECT_MODE_REG                           ,
+       RULL(0x0E0303FE), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_CC_PROTECT_MODE_REG                           ,
+       RULL(0x0F0303FE), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_CC_PROTECT_MODE_REG                           ,
+       RULL(0x100303FE), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_CC_PROTECT_MODE_REG                           ,
+       RULL(0x110303FE), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_CC_PROTECT_MODE_REG                           ,
+       RULL(0x120303FE), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_CC_PROTECT_MODE_REG                           ,
+       RULL(0x130303FE), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_CC_PROTECT_MODE_REG                           ,
+       RULL(0x140303FE), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_CC_PROTECT_MODE_REG                           ,
+       RULL(0x150303FE), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_CC_PROTECT_MODE_REG                           ,
+       RULL(0x200303FE), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CC_PROTECT_MODE_REG                           ,
+       RULL(0x210303FE), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CC_PROTECT_MODE_REG                           ,
+       RULL(0x220303FE), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CC_PROTECT_MODE_REG                           ,
+       RULL(0x230303FE), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CC_PROTECT_MODE_REG                           ,
+       RULL(0x240303FE), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CC_PROTECT_MODE_REG                           ,
+       RULL(0x250303FE), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CC_PROTECT_MODE_REG                           ,
+       RULL(0x260303FE), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CC_PROTECT_MODE_REG                           ,
+       RULL(0x270303FE), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CC_PROTECT_MODE_REG                           ,
+       RULL(0x280303FE), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CC_PROTECT_MODE_REG                           ,
+       RULL(0x290303FE), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CC_PROTECT_MODE_REG                           ,
+       RULL(0x2A0303FE), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CC_PROTECT_MODE_REG                           ,
+       RULL(0x2B0303FE), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CC_PROTECT_MODE_REG                           ,
+       RULL(0x2C0303FE), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CC_PROTECT_MODE_REG                           ,
+       RULL(0x2D0303FE), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CC_PROTECT_MODE_REG                           ,
+       RULL(0x2E0303FE), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CC_PROTECT_MODE_REG                           ,
+       RULL(0x2F0303FE), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CC_PROTECT_MODE_REG                           ,
+       RULL(0x300303FE), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CC_PROTECT_MODE_REG                           ,
+       RULL(0x310303FE), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CC_PROTECT_MODE_REG                           ,
+       RULL(0x320303FE), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CC_PROTECT_MODE_REG                           ,
+       RULL(0x330303FE), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CC_PROTECT_MODE_REG                           ,
+       RULL(0x340303FE), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CC_PROTECT_MODE_REG                           ,
+       RULL(0x350303FE), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CC_PROTECT_MODE_REG                           ,
+       RULL(0x360303FE), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CC_PROTECT_MODE_REG                           ,
+       RULL(0x370303FE), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG32( PERV_FSI2PIB_CHIPID_FSI                                 ,
+       RULL(0x0000100A), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI       );
+REG32( PERV_FSI2PIB_CHIPID_FSI_BYTE                            ,
+       RULL(0x00001028), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_CHIP_ID_FSI                               ,
+       RULL(0x00000C09), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_CHIP_ID_FSI_BYTE                          ,
+       RULL(0x00000C24), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE  );
+
+REG64( PERV_CLK_REGION                                         ,
+       RULL(0x00030006), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_CLK_REGION                                      ,
+       RULL(0x01030006), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_CLK_REGION                                      ,
+       RULL(0x02030006), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_CLK_REGION                                      ,
+       RULL(0x03030006), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_CLK_REGION                                      ,
+       RULL(0x04030006), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_CLK_REGION                                      ,
+       RULL(0x05030006), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_CLK_REGION                                      ,
+       RULL(0x06030006), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_CLK_REGION                                    ,
+       RULL(0x07030006), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_CLK_REGION                                    ,
+       RULL(0x08030006), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_CLK_REGION                                     ,
+       RULL(0x09030006), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_CLK_REGION                                     ,
+       RULL(0x0C030006), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_CLK_REGION                                    ,
+       RULL(0x0D030006), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_CLK_REGION                                    ,
+       RULL(0x0E030006), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_CLK_REGION                                    ,
+       RULL(0x0F030006), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_CLK_REGION                                    ,
+       RULL(0x10030006), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_CLK_REGION                                    ,
+       RULL(0x11030006), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_CLK_REGION                                    ,
+       RULL(0x12030006), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_CLK_REGION                                    ,
+       RULL(0x13030006), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_CLK_REGION                                    ,
+       RULL(0x14030006), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_CLK_REGION                                    ,
+       RULL(0x15030006), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_CLK_REGION                                    ,
+       RULL(0x20030006), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CLK_REGION                                    ,
+       RULL(0x21030006), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CLK_REGION                                    ,
+       RULL(0x22030006), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CLK_REGION                                    ,
+       RULL(0x23030006), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CLK_REGION                                    ,
+       RULL(0x24030006), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CLK_REGION                                    ,
+       RULL(0x25030006), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CLK_REGION                                    ,
+       RULL(0x26030006), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CLK_REGION                                    ,
+       RULL(0x27030006), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CLK_REGION                                    ,
+       RULL(0x28030006), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CLK_REGION                                    ,
+       RULL(0x29030006), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CLK_REGION                                    ,
+       RULL(0x2A030006), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CLK_REGION                                    ,
+       RULL(0x2B030006), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CLK_REGION                                    ,
+       RULL(0x2C030006), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CLK_REGION                                    ,
+       RULL(0x2D030006), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CLK_REGION                                    ,
+       RULL(0x2E030006), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CLK_REGION                                    ,
+       RULL(0x2F030006), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CLK_REGION                                    ,
+       RULL(0x30030006), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CLK_REGION                                    ,
+       RULL(0x31030006), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CLK_REGION                                    ,
+       RULL(0x32030006), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CLK_REGION                                    ,
+       RULL(0x33030006), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CLK_REGION                                    ,
+       RULL(0x34030006), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CLK_REGION                                    ,
+       RULL(0x35030006), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CLK_REGION                                    ,
+       RULL(0x36030006), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CLK_REGION                                    ,
+       RULL(0x37030006), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_CLOCK_STAT_ARY                                     ,
+       RULL(0x0003000A), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_CLOCK_STAT_ARY                                  ,
+       RULL(0x0103000A), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_CLOCK_STAT_ARY                                  ,
+       RULL(0x0203000A), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_CLOCK_STAT_ARY                                  ,
+       RULL(0x0303000A), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_CLOCK_STAT_ARY                                  ,
+       RULL(0x0403000A), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_CLOCK_STAT_ARY                                  ,
+       RULL(0x0503000A), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_CLOCK_STAT_ARY                                  ,
+       RULL(0x0603000A), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_CLOCK_STAT_ARY                                ,
+       RULL(0x0703000A), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_CLOCK_STAT_ARY                                ,
+       RULL(0x0803000A), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_CLOCK_STAT_ARY                                 ,
+       RULL(0x0903000A), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_CLOCK_STAT_ARY                                 ,
+       RULL(0x0C03000A), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_CLOCK_STAT_ARY                                ,
+       RULL(0x0D03000A), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_CLOCK_STAT_ARY                                ,
+       RULL(0x0E03000A), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_CLOCK_STAT_ARY                                ,
+       RULL(0x0F03000A), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_CLOCK_STAT_ARY                                ,
+       RULL(0x1003000A), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_CLOCK_STAT_ARY                                ,
+       RULL(0x1103000A), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_CLOCK_STAT_ARY                                ,
+       RULL(0x1203000A), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_CLOCK_STAT_ARY                                ,
+       RULL(0x1303000A), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_CLOCK_STAT_ARY                                ,
+       RULL(0x1403000A), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_CLOCK_STAT_ARY                                ,
+       RULL(0x1503000A), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_CLOCK_STAT_ARY                                ,
+       RULL(0x2003000A), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CLOCK_STAT_ARY                                ,
+       RULL(0x2103000A), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CLOCK_STAT_ARY                                ,
+       RULL(0x2203000A), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CLOCK_STAT_ARY                                ,
+       RULL(0x2303000A), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CLOCK_STAT_ARY                                ,
+       RULL(0x2403000A), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CLOCK_STAT_ARY                                ,
+       RULL(0x2503000A), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CLOCK_STAT_ARY                                ,
+       RULL(0x2603000A), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CLOCK_STAT_ARY                                ,
+       RULL(0x2703000A), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CLOCK_STAT_ARY                                ,
+       RULL(0x2803000A), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CLOCK_STAT_ARY                                ,
+       RULL(0x2903000A), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CLOCK_STAT_ARY                                ,
+       RULL(0x2A03000A), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CLOCK_STAT_ARY                                ,
+       RULL(0x2B03000A), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CLOCK_STAT_ARY                                ,
+       RULL(0x2C03000A), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CLOCK_STAT_ARY                                ,
+       RULL(0x2D03000A), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CLOCK_STAT_ARY                                ,
+       RULL(0x2E03000A), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CLOCK_STAT_ARY                                ,
+       RULL(0x2F03000A), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CLOCK_STAT_ARY                                ,
+       RULL(0x3003000A), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CLOCK_STAT_ARY                                ,
+       RULL(0x3103000A), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CLOCK_STAT_ARY                                ,
+       RULL(0x3203000A), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CLOCK_STAT_ARY                                ,
+       RULL(0x3303000A), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CLOCK_STAT_ARY                                ,
+       RULL(0x3403000A), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CLOCK_STAT_ARY                                ,
+       RULL(0x3503000A), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CLOCK_STAT_ARY                                ,
+       RULL(0x3603000A), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CLOCK_STAT_ARY                                ,
+       RULL(0x3703000A), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_CLOCK_STAT_NSL                                     ,
+       RULL(0x00030009), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_CLOCK_STAT_NSL                                  ,
+       RULL(0x01030009), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_CLOCK_STAT_NSL                                  ,
+       RULL(0x02030009), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_CLOCK_STAT_NSL                                  ,
+       RULL(0x03030009), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_CLOCK_STAT_NSL                                  ,
+       RULL(0x04030009), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_CLOCK_STAT_NSL                                  ,
+       RULL(0x05030009), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_CLOCK_STAT_NSL                                  ,
+       RULL(0x06030009), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_CLOCK_STAT_NSL                                ,
+       RULL(0x07030009), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_CLOCK_STAT_NSL                                ,
+       RULL(0x08030009), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_CLOCK_STAT_NSL                                 ,
+       RULL(0x09030009), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_CLOCK_STAT_NSL                                 ,
+       RULL(0x0C030009), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_CLOCK_STAT_NSL                                ,
+       RULL(0x0D030009), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_CLOCK_STAT_NSL                                ,
+       RULL(0x0E030009), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_CLOCK_STAT_NSL                                ,
+       RULL(0x0F030009), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_CLOCK_STAT_NSL                                ,
+       RULL(0x10030009), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_CLOCK_STAT_NSL                                ,
+       RULL(0x11030009), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_CLOCK_STAT_NSL                                ,
+       RULL(0x12030009), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_CLOCK_STAT_NSL                                ,
+       RULL(0x13030009), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_CLOCK_STAT_NSL                                ,
+       RULL(0x14030009), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_CLOCK_STAT_NSL                                ,
+       RULL(0x15030009), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_CLOCK_STAT_NSL                                ,
+       RULL(0x20030009), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CLOCK_STAT_NSL                                ,
+       RULL(0x21030009), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CLOCK_STAT_NSL                                ,
+       RULL(0x22030009), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CLOCK_STAT_NSL                                ,
+       RULL(0x23030009), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CLOCK_STAT_NSL                                ,
+       RULL(0x24030009), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CLOCK_STAT_NSL                                ,
+       RULL(0x25030009), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CLOCK_STAT_NSL                                ,
+       RULL(0x26030009), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CLOCK_STAT_NSL                                ,
+       RULL(0x27030009), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CLOCK_STAT_NSL                                ,
+       RULL(0x28030009), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CLOCK_STAT_NSL                                ,
+       RULL(0x29030009), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CLOCK_STAT_NSL                                ,
+       RULL(0x2A030009), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CLOCK_STAT_NSL                                ,
+       RULL(0x2B030009), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CLOCK_STAT_NSL                                ,
+       RULL(0x2C030009), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CLOCK_STAT_NSL                                ,
+       RULL(0x2D030009), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CLOCK_STAT_NSL                                ,
+       RULL(0x2E030009), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CLOCK_STAT_NSL                                ,
+       RULL(0x2F030009), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CLOCK_STAT_NSL                                ,
+       RULL(0x30030009), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CLOCK_STAT_NSL                                ,
+       RULL(0x31030009), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CLOCK_STAT_NSL                                ,
+       RULL(0x32030009), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CLOCK_STAT_NSL                                ,
+       RULL(0x33030009), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CLOCK_STAT_NSL                                ,
+       RULL(0x34030009), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CLOCK_STAT_NSL                                ,
+       RULL(0x35030009), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CLOCK_STAT_NSL                                ,
+       RULL(0x36030009), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CLOCK_STAT_NSL                                ,
+       RULL(0x37030009), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_CLOCK_STAT_SL                                      ,
+       RULL(0x00030008), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_CLOCK_STAT_SL                                   ,
+       RULL(0x01030008), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_CLOCK_STAT_SL                                   ,
+       RULL(0x02030008), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_CLOCK_STAT_SL                                   ,
+       RULL(0x03030008), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_CLOCK_STAT_SL                                   ,
+       RULL(0x04030008), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_CLOCK_STAT_SL                                   ,
+       RULL(0x05030008), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_CLOCK_STAT_SL                                   ,
+       RULL(0x06030008), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_CLOCK_STAT_SL                                 ,
+       RULL(0x07030008), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_CLOCK_STAT_SL                                 ,
+       RULL(0x08030008), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_CLOCK_STAT_SL                                  ,
+       RULL(0x09030008), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_CLOCK_STAT_SL                                  ,
+       RULL(0x0C030008), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_CLOCK_STAT_SL                                 ,
+       RULL(0x0D030008), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_CLOCK_STAT_SL                                 ,
+       RULL(0x0E030008), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_CLOCK_STAT_SL                                 ,
+       RULL(0x0F030008), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_CLOCK_STAT_SL                                 ,
+       RULL(0x10030008), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_CLOCK_STAT_SL                                 ,
+       RULL(0x11030008), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_CLOCK_STAT_SL                                 ,
+       RULL(0x12030008), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_CLOCK_STAT_SL                                 ,
+       RULL(0x13030008), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_CLOCK_STAT_SL                                 ,
+       RULL(0x14030008), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_CLOCK_STAT_SL                                 ,
+       RULL(0x15030008), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_CLOCK_STAT_SL                                 ,
+       RULL(0x20030008), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CLOCK_STAT_SL                                 ,
+       RULL(0x21030008), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CLOCK_STAT_SL                                 ,
+       RULL(0x22030008), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CLOCK_STAT_SL                                 ,
+       RULL(0x23030008), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CLOCK_STAT_SL                                 ,
+       RULL(0x24030008), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CLOCK_STAT_SL                                 ,
+       RULL(0x25030008), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CLOCK_STAT_SL                                 ,
+       RULL(0x26030008), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CLOCK_STAT_SL                                 ,
+       RULL(0x27030008), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CLOCK_STAT_SL                                 ,
+       RULL(0x28030008), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CLOCK_STAT_SL                                 ,
+       RULL(0x29030008), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CLOCK_STAT_SL                                 ,
+       RULL(0x2A030008), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CLOCK_STAT_SL                                 ,
+       RULL(0x2B030008), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CLOCK_STAT_SL                                 ,
+       RULL(0x2C030008), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CLOCK_STAT_SL                                 ,
+       RULL(0x2D030008), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CLOCK_STAT_SL                                 ,
+       RULL(0x2E030008), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CLOCK_STAT_SL                                 ,
+       RULL(0x2F030008), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CLOCK_STAT_SL                                 ,
+       RULL(0x30030008), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CLOCK_STAT_SL                                 ,
+       RULL(0x31030008), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CLOCK_STAT_SL                                 ,
+       RULL(0x32030008), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CLOCK_STAT_SL                                 ,
+       RULL(0x33030008), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CLOCK_STAT_SL                                 ,
+       RULL(0x34030008), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CLOCK_STAT_SL                                 ,
+       RULL(0x35030008), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CLOCK_STAT_SL                                 ,
+       RULL(0x36030008), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CLOCK_STAT_SL                                 ,
+       RULL(0x37030008), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_CMD_WRDAT                                          ,
+       RULL(0x00030000), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_CMD_WRDAT                                      ,
+       RULL(0x00030000), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_0_FSII2C_COMMAND_REGISTER                          ,
+       RULL(0x00001801), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM      );
+REG32( PERV_FSI2PIB_COMMAND_REGISTER_FSI                       ,
+       RULL(0x00001002), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI       );
+REG32( PERV_FSI2PIB_COMMAND_REGISTER_FSI_BYTE                  ,
+       RULL(0x00001008), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE  );
+REG32( PERV_FSII2C_COMMAND_REGISTER                            ,
+       RULL(0x00001801), SH_UNT_PERV_FSII2C, SH_ACS_SCOM      );
+REG32( PERV_FSISHIFT_COMMAND_REGISTER_FSI                      ,
+       RULL(0x00000C01), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_COMMAND_REGISTER_FSI_BYTE                 ,
+       RULL(0x00000C04), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSI2PIB_COMPLEMENT_MASK_FSI                        ,
+       RULL(0x0000100C), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI       );
+REG32( PERV_FSI2PIB_COMPLEMENT_MASK_FSI_BYTE                   ,
+       RULL(0x00001030), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE  );
+REG32( PERV_FSISHIFT_COMPLEMENT_MASK_FSI                       ,
+       RULL(0x00000C0C), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_COMPLEMENT_MASK_FSI_BYTE                  ,
+       RULL(0x00000C30), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE  );
+
+REG64( PERV_CONTROL_REG                                        ,
+       RULL(0x00050012), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_CONTROL_REG                                     ,
+       RULL(0x01050012), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_CONTROL_REG                                     ,
+       RULL(0x02050012), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_CONTROL_REG                                     ,
+       RULL(0x03050012), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_CONTROL_REG                                     ,
+       RULL(0x04050012), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_CONTROL_REG                                     ,
+       RULL(0x05050012), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_CONTROL_REG                                     ,
+       RULL(0x06050012), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_CONTROL_REG                                   ,
+       RULL(0x07050012), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_CONTROL_REG                                   ,
+       RULL(0x08050012), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_CONTROL_REG                                    ,
+       RULL(0x09050012), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_CONTROL_REG                                    ,
+       RULL(0x0C050012), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_CONTROL_REG                                   ,
+       RULL(0x0D050012), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_CONTROL_REG                                   ,
+       RULL(0x0E050012), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_CONTROL_REG                                   ,
+       RULL(0x0F050012), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_CONTROL_REG                                   ,
+       RULL(0x10050012), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_CONTROL_REG                                   ,
+       RULL(0x11050012), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_CONTROL_REG                                   ,
+       RULL(0x12050012), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_CONTROL_REG                                   ,
+       RULL(0x13050012), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_CONTROL_REG                                   ,
+       RULL(0x14050012), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_CONTROL_REG                                   ,
+       RULL(0x15050012), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_CONTROL_REG                                   ,
+       RULL(0x20050012), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CONTROL_REG                                   ,
+       RULL(0x21050012), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CONTROL_REG                                   ,
+       RULL(0x22050012), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CONTROL_REG                                   ,
+       RULL(0x23050012), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CONTROL_REG                                   ,
+       RULL(0x24050012), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CONTROL_REG                                   ,
+       RULL(0x25050012), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CONTROL_REG                                   ,
+       RULL(0x26050012), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CONTROL_REG                                   ,
+       RULL(0x27050012), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CONTROL_REG                                   ,
+       RULL(0x28050012), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CONTROL_REG                                   ,
+       RULL(0x29050012), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CONTROL_REG                                   ,
+       RULL(0x2A050012), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CONTROL_REG                                   ,
+       RULL(0x2B050012), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CONTROL_REG                                   ,
+       RULL(0x2C050012), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CONTROL_REG                                   ,
+       RULL(0x2D050012), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CONTROL_REG                                   ,
+       RULL(0x2E050012), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CONTROL_REG                                   ,
+       RULL(0x2F050012), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CONTROL_REG                                   ,
+       RULL(0x30050012), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CONTROL_REG                                   ,
+       RULL(0x31050012), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CONTROL_REG                                   ,
+       RULL(0x32050012), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CONTROL_REG                                   ,
+       RULL(0x33050012), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CONTROL_REG                                   ,
+       RULL(0x34050012), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CONTROL_REG                                   ,
+       RULL(0x35050012), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CONTROL_REG                                   ,
+       RULL(0x36050012), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CONTROL_REG                                   ,
+       RULL(0x37050012), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_CPLT_CONF0                                         ,
+       RULL(0x00000008), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_CPLT_CONF0                                      ,
+       RULL(0x01000008), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_CPLT_CONF0_OR                                      ,
+       RULL(0x00000018), SH_UNT_PERV_1   , SH_ACS_SCOM1_OR  );
+REG64( PERV_TP_CPLT_CONF0_OR                                   ,
+       RULL(0x01000018), SH_UNT_PERV_1   , SH_ACS_SCOM1_OR  );
+REG64( PERV_CPLT_CONF0_CLEAR                                   ,
+       RULL(0x00000028), SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_TP_CPLT_CONF0_CLEAR                                ,
+       RULL(0x01000028), SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N0_CPLT_CONF0                                      ,
+       RULL(0x02000008), SH_UNT_PERV_2   , SH_ACS_SCOM_RW   );
+REG64( PERV_N0_CPLT_CONF0_OR                                   ,
+       RULL(0x02000018), SH_UNT_PERV_2   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N0_CPLT_CONF0_CLEAR                                ,
+       RULL(0x02000028), SH_UNT_PERV_2   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N1_CPLT_CONF0                                      ,
+       RULL(0x03000008), SH_UNT_PERV_3   , SH_ACS_SCOM_RW   );
+REG64( PERV_N1_CPLT_CONF0_OR                                   ,
+       RULL(0x03000018), SH_UNT_PERV_3   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N1_CPLT_CONF0_CLEAR                                ,
+       RULL(0x03000028), SH_UNT_PERV_3   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N2_CPLT_CONF0                                      ,
+       RULL(0x04000008), SH_UNT_PERV_4   , SH_ACS_SCOM_RW   );
+REG64( PERV_N2_CPLT_CONF0_OR                                   ,
+       RULL(0x04000018), SH_UNT_PERV_4   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N2_CPLT_CONF0_CLEAR                                ,
+       RULL(0x04000028), SH_UNT_PERV_4   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N3_CPLT_CONF0                                      ,
+       RULL(0x05000008), SH_UNT_PERV_5   , SH_ACS_SCOM_RW   );
+REG64( PERV_N3_CPLT_CONF0_OR                                   ,
+       RULL(0x05000018), SH_UNT_PERV_5   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N3_CPLT_CONF0_CLEAR                                ,
+       RULL(0x05000028), SH_UNT_PERV_5   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_XB_CPLT_CONF0                                      ,
+       RULL(0x06000008), SH_UNT_PERV_6   , SH_ACS_SCOM_RW   );
+REG64( PERV_XB_CPLT_CONF0_OR                                   ,
+       RULL(0x06000018), SH_UNT_PERV_6   , SH_ACS_SCOM1_OR  );
+REG64( PERV_XB_CPLT_CONF0_CLEAR                                ,
+       RULL(0x06000028), SH_UNT_PERV_6   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_MC01_CPLT_CONF0                                    ,
+       RULL(0x07000008), SH_UNT_PERV_7   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC01_CPLT_CONF0_OR                                 ,
+       RULL(0x07000018), SH_UNT_PERV_7   , SH_ACS_SCOM1_OR  );
+REG64( PERV_MC01_CPLT_CONF0_CLEAR                              ,
+       RULL(0x07000028), SH_UNT_PERV_7   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_MC23_CPLT_CONF0                                    ,
+       RULL(0x08000008), SH_UNT_PERV_8   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC23_CPLT_CONF0_OR                                 ,
+       RULL(0x08000018), SH_UNT_PERV_8   , SH_ACS_SCOM1_OR  );
+REG64( PERV_MC23_CPLT_CONF0_CLEAR                              ,
+       RULL(0x08000028), SH_UNT_PERV_8   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_OB0_CPLT_CONF0                                     ,
+       RULL(0x09000008), SH_UNT_PERV_9   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB0_CPLT_CONF0_OR                                  ,
+       RULL(0x09000018), SH_UNT_PERV_9   , SH_ACS_SCOM1_OR  );
+REG64( PERV_OB0_CPLT_CONF0_CLEAR                               ,
+       RULL(0x09000028), SH_UNT_PERV_9   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_OB3_CPLT_CONF0                                     ,
+       RULL(0x0C000008), SH_UNT_PERV_12  , SH_ACS_SCOM_RW   );
+REG64( PERV_OB3_CPLT_CONF0_OR                                  ,
+       RULL(0x0C000018), SH_UNT_PERV_12  , SH_ACS_SCOM1_OR  );
+REG64( PERV_OB3_CPLT_CONF0_CLEAR                               ,
+       RULL(0x0C000028), SH_UNT_PERV_12  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI0_CPLT_CONF0                                    ,
+       RULL(0x0D000008), SH_UNT_PERV_13  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI0_CPLT_CONF0_OR                                 ,
+       RULL(0x0D000018), SH_UNT_PERV_13  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI0_CPLT_CONF0_CLEAR                              ,
+       RULL(0x0D000028), SH_UNT_PERV_13  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI1_CPLT_CONF0                                    ,
+       RULL(0x0E000008), SH_UNT_PERV_14  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI1_CPLT_CONF0_OR                                 ,
+       RULL(0x0E000018), SH_UNT_PERV_14  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI1_CPLT_CONF0_CLEAR                              ,
+       RULL(0x0E000028), SH_UNT_PERV_14  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI2_CPLT_CONF0                                    ,
+       RULL(0x0F000008), SH_UNT_PERV_15  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI2_CPLT_CONF0_OR                                 ,
+       RULL(0x0F000018), SH_UNT_PERV_15  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI2_CPLT_CONF0_CLEAR                              ,
+       RULL(0x0F000028), SH_UNT_PERV_15  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP00_CPLT_CONF0                                    ,
+       RULL(0x10000008), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_CPLT_CONF0_OR                                 ,
+       RULL(0x10000018), SH_UNT_PERV_16  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP00_CPLT_CONF0_CLEAR                              ,
+       RULL(0x10000028), SH_UNT_PERV_16  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP01_CPLT_CONF0                                    ,
+       RULL(0x11000008), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_CPLT_CONF0_OR                                 ,
+       RULL(0x11000018), SH_UNT_PERV_17  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP01_CPLT_CONF0_CLEAR                              ,
+       RULL(0x11000028), SH_UNT_PERV_17  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP02_CPLT_CONF0                                    ,
+       RULL(0x12000008), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_CPLT_CONF0_OR                                 ,
+       RULL(0x12000018), SH_UNT_PERV_18  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP02_CPLT_CONF0_CLEAR                              ,
+       RULL(0x12000028), SH_UNT_PERV_18  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP03_CPLT_CONF0                                    ,
+       RULL(0x13000008), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_CPLT_CONF0_OR                                 ,
+       RULL(0x13000018), SH_UNT_PERV_19  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP03_CPLT_CONF0_CLEAR                              ,
+       RULL(0x13000028), SH_UNT_PERV_19  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP04_CPLT_CONF0                                    ,
+       RULL(0x14000008), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_CPLT_CONF0_OR                                 ,
+       RULL(0x14000018), SH_UNT_PERV_20  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP04_CPLT_CONF0_CLEAR                              ,
+       RULL(0x14000028), SH_UNT_PERV_20  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP05_CPLT_CONF0                                    ,
+       RULL(0x15000008), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_CPLT_CONF0_OR                                 ,
+       RULL(0x15000018), SH_UNT_PERV_21  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP05_CPLT_CONF0_CLEAR                              ,
+       RULL(0x15000028), SH_UNT_PERV_21  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC00_CPLT_CONF0                                    ,
+       RULL(0x20000008), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPLT_CONF0_OR                                 ,
+       RULL(0x20000018), SH_UNT_PERV_32  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC00_CPLT_CONF0_CLEAR                              ,
+       RULL(0x20000028), SH_UNT_PERV_32  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC01_CPLT_CONF0                                    ,
+       RULL(0x21000008), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPLT_CONF0_OR                                 ,
+       RULL(0x21000018), SH_UNT_PERV_33  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC01_CPLT_CONF0_CLEAR                              ,
+       RULL(0x21000028), SH_UNT_PERV_33  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC02_CPLT_CONF0                                    ,
+       RULL(0x22000008), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPLT_CONF0_OR                                 ,
+       RULL(0x22000018), SH_UNT_PERV_34  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC02_CPLT_CONF0_CLEAR                              ,
+       RULL(0x22000028), SH_UNT_PERV_34  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC03_CPLT_CONF0                                    ,
+       RULL(0x23000008), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPLT_CONF0_OR                                 ,
+       RULL(0x23000018), SH_UNT_PERV_35  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC03_CPLT_CONF0_CLEAR                              ,
+       RULL(0x23000028), SH_UNT_PERV_35  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC04_CPLT_CONF0                                    ,
+       RULL(0x24000008), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPLT_CONF0_OR                                 ,
+       RULL(0x24000018), SH_UNT_PERV_36  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC04_CPLT_CONF0_CLEAR                              ,
+       RULL(0x24000028), SH_UNT_PERV_36  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC05_CPLT_CONF0                                    ,
+       RULL(0x25000008), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPLT_CONF0_OR                                 ,
+       RULL(0x25000018), SH_UNT_PERV_37  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC05_CPLT_CONF0_CLEAR                              ,
+       RULL(0x25000028), SH_UNT_PERV_37  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC06_CPLT_CONF0                                    ,
+       RULL(0x26000008), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPLT_CONF0_OR                                 ,
+       RULL(0x26000018), SH_UNT_PERV_38  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC06_CPLT_CONF0_CLEAR                              ,
+       RULL(0x26000028), SH_UNT_PERV_38  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC07_CPLT_CONF0                                    ,
+       RULL(0x27000008), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPLT_CONF0_OR                                 ,
+       RULL(0x27000018), SH_UNT_PERV_39  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC07_CPLT_CONF0_CLEAR                              ,
+       RULL(0x27000028), SH_UNT_PERV_39  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC08_CPLT_CONF0                                    ,
+       RULL(0x28000008), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPLT_CONF0_OR                                 ,
+       RULL(0x28000018), SH_UNT_PERV_40  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC08_CPLT_CONF0_CLEAR                              ,
+       RULL(0x28000028), SH_UNT_PERV_40  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC09_CPLT_CONF0                                    ,
+       RULL(0x29000008), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPLT_CONF0_OR                                 ,
+       RULL(0x29000018), SH_UNT_PERV_41  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC09_CPLT_CONF0_CLEAR                              ,
+       RULL(0x29000028), SH_UNT_PERV_41  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC10_CPLT_CONF0                                    ,
+       RULL(0x2A000008), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPLT_CONF0_OR                                 ,
+       RULL(0x2A000018), SH_UNT_PERV_42  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC10_CPLT_CONF0_CLEAR                              ,
+       RULL(0x2A000028), SH_UNT_PERV_42  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC11_CPLT_CONF0                                    ,
+       RULL(0x2B000008), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPLT_CONF0_OR                                 ,
+       RULL(0x2B000018), SH_UNT_PERV_43  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC11_CPLT_CONF0_CLEAR                              ,
+       RULL(0x2B000028), SH_UNT_PERV_43  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC12_CPLT_CONF0                                    ,
+       RULL(0x2C000008), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPLT_CONF0_OR                                 ,
+       RULL(0x2C000018), SH_UNT_PERV_44  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC12_CPLT_CONF0_CLEAR                              ,
+       RULL(0x2C000028), SH_UNT_PERV_44  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC13_CPLT_CONF0                                    ,
+       RULL(0x2D000008), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPLT_CONF0_OR                                 ,
+       RULL(0x2D000018), SH_UNT_PERV_45  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC13_CPLT_CONF0_CLEAR                              ,
+       RULL(0x2D000028), SH_UNT_PERV_45  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC14_CPLT_CONF0                                    ,
+       RULL(0x2E000008), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPLT_CONF0_OR                                 ,
+       RULL(0x2E000018), SH_UNT_PERV_46  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC14_CPLT_CONF0_CLEAR                              ,
+       RULL(0x2E000028), SH_UNT_PERV_46  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC15_CPLT_CONF0                                    ,
+       RULL(0x2F000008), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPLT_CONF0_OR                                 ,
+       RULL(0x2F000018), SH_UNT_PERV_47  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC15_CPLT_CONF0_CLEAR                              ,
+       RULL(0x2F000028), SH_UNT_PERV_47  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC16_CPLT_CONF0                                    ,
+       RULL(0x30000008), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPLT_CONF0_OR                                 ,
+       RULL(0x30000018), SH_UNT_PERV_48  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC16_CPLT_CONF0_CLEAR                              ,
+       RULL(0x30000028), SH_UNT_PERV_48  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC17_CPLT_CONF0                                    ,
+       RULL(0x31000008), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPLT_CONF0_OR                                 ,
+       RULL(0x31000018), SH_UNT_PERV_49  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC17_CPLT_CONF0_CLEAR                              ,
+       RULL(0x31000028), SH_UNT_PERV_49  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC18_CPLT_CONF0                                    ,
+       RULL(0x32000008), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPLT_CONF0_OR                                 ,
+       RULL(0x32000018), SH_UNT_PERV_50  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC18_CPLT_CONF0_CLEAR                              ,
+       RULL(0x32000028), SH_UNT_PERV_50  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC19_CPLT_CONF0                                    ,
+       RULL(0x33000008), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPLT_CONF0_OR                                 ,
+       RULL(0x33000018), SH_UNT_PERV_51  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC19_CPLT_CONF0_CLEAR                              ,
+       RULL(0x33000028), SH_UNT_PERV_51  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC20_CPLT_CONF0                                    ,
+       RULL(0x34000008), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPLT_CONF0_OR                                 ,
+       RULL(0x34000018), SH_UNT_PERV_52  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC20_CPLT_CONF0_CLEAR                              ,
+       RULL(0x34000028), SH_UNT_PERV_52  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC21_CPLT_CONF0                                    ,
+       RULL(0x35000008), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPLT_CONF0_OR                                 ,
+       RULL(0x35000018), SH_UNT_PERV_53  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC21_CPLT_CONF0_CLEAR                              ,
+       RULL(0x35000028), SH_UNT_PERV_53  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC22_CPLT_CONF0                                    ,
+       RULL(0x36000008), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPLT_CONF0_OR                                 ,
+       RULL(0x36000018), SH_UNT_PERV_54  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC22_CPLT_CONF0_CLEAR                              ,
+       RULL(0x36000028), SH_UNT_PERV_54  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC23_CPLT_CONF0                                    ,
+       RULL(0x37000008), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPLT_CONF0_OR                                 ,
+       RULL(0x37000018), SH_UNT_PERV_55  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC23_CPLT_CONF0_CLEAR                              ,
+       RULL(0x37000028), SH_UNT_PERV_55  , SH_ACS_SCOM2_CLEAR );
+
+REG64( PERV_CPLT_CONF1                                         ,
+       RULL(0x00000009), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_CPLT_CONF1                                      ,
+       RULL(0x01000009), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_CPLT_CONF1_OR                                      ,
+       RULL(0x00000019), SH_UNT_PERV_1   , SH_ACS_SCOM1_OR  );
+REG64( PERV_TP_CPLT_CONF1_OR                                   ,
+       RULL(0x01000019), SH_UNT_PERV_1   , SH_ACS_SCOM1_OR  );
+REG64( PERV_CPLT_CONF1_CLEAR                                   ,
+       RULL(0x00000029), SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_TP_CPLT_CONF1_CLEAR                                ,
+       RULL(0x01000029), SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N0_CPLT_CONF1                                      ,
+       RULL(0x02000009), SH_UNT_PERV_2   , SH_ACS_SCOM_RW   );
+REG64( PERV_N0_CPLT_CONF1_OR                                   ,
+       RULL(0x02000019), SH_UNT_PERV_2   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N0_CPLT_CONF1_CLEAR                                ,
+       RULL(0x02000029), SH_UNT_PERV_2   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N1_CPLT_CONF1                                      ,
+       RULL(0x03000009), SH_UNT_PERV_3   , SH_ACS_SCOM_RW   );
+REG64( PERV_N1_CPLT_CONF1_OR                                   ,
+       RULL(0x03000019), SH_UNT_PERV_3   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N1_CPLT_CONF1_CLEAR                                ,
+       RULL(0x03000029), SH_UNT_PERV_3   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N2_CPLT_CONF1                                      ,
+       RULL(0x04000009), SH_UNT_PERV_4   , SH_ACS_SCOM_RW   );
+REG64( PERV_N2_CPLT_CONF1_OR                                   ,
+       RULL(0x04000019), SH_UNT_PERV_4   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N2_CPLT_CONF1_CLEAR                                ,
+       RULL(0x04000029), SH_UNT_PERV_4   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N3_CPLT_CONF1                                      ,
+       RULL(0x05000009), SH_UNT_PERV_5   , SH_ACS_SCOM_RW   );
+REG64( PERV_N3_CPLT_CONF1_OR                                   ,
+       RULL(0x05000019), SH_UNT_PERV_5   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N3_CPLT_CONF1_CLEAR                                ,
+       RULL(0x05000029), SH_UNT_PERV_5   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_XB_CPLT_CONF1                                      ,
+       RULL(0x06000009), SH_UNT_PERV_6   , SH_ACS_SCOM_RW   );
+REG64( PERV_XB_CPLT_CONF1_OR                                   ,
+       RULL(0x06000019), SH_UNT_PERV_6   , SH_ACS_SCOM1_OR  );
+REG64( PERV_XB_CPLT_CONF1_CLEAR                                ,
+       RULL(0x06000029), SH_UNT_PERV_6   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_MC01_CPLT_CONF1                                    ,
+       RULL(0x07000009), SH_UNT_PERV_7   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC01_CPLT_CONF1_OR                                 ,
+       RULL(0x07000019), SH_UNT_PERV_7   , SH_ACS_SCOM1_OR  );
+REG64( PERV_MC01_CPLT_CONF1_CLEAR                              ,
+       RULL(0x07000029), SH_UNT_PERV_7   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_MC23_CPLT_CONF1                                    ,
+       RULL(0x08000009), SH_UNT_PERV_8   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC23_CPLT_CONF1_OR                                 ,
+       RULL(0x08000019), SH_UNT_PERV_8   , SH_ACS_SCOM1_OR  );
+REG64( PERV_MC23_CPLT_CONF1_CLEAR                              ,
+       RULL(0x08000029), SH_UNT_PERV_8   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_OB0_CPLT_CONF1                                     ,
+       RULL(0x09000009), SH_UNT_PERV_9   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB0_CPLT_CONF1_OR                                  ,
+       RULL(0x09000019), SH_UNT_PERV_9   , SH_ACS_SCOM1_OR  );
+REG64( PERV_OB0_CPLT_CONF1_CLEAR                               ,
+       RULL(0x09000029), SH_UNT_PERV_9   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_OB3_CPLT_CONF1                                     ,
+       RULL(0x0C000009), SH_UNT_PERV_12  , SH_ACS_SCOM_RW   );
+REG64( PERV_OB3_CPLT_CONF1_OR                                  ,
+       RULL(0x0C000019), SH_UNT_PERV_12  , SH_ACS_SCOM1_OR  );
+REG64( PERV_OB3_CPLT_CONF1_CLEAR                               ,
+       RULL(0x0C000029), SH_UNT_PERV_12  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI0_CPLT_CONF1                                    ,
+       RULL(0x0D000009), SH_UNT_PERV_13  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI0_CPLT_CONF1_OR                                 ,
+       RULL(0x0D000019), SH_UNT_PERV_13  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI0_CPLT_CONF1_CLEAR                              ,
+       RULL(0x0D000029), SH_UNT_PERV_13  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI1_CPLT_CONF1                                    ,
+       RULL(0x0E000009), SH_UNT_PERV_14  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI1_CPLT_CONF1_OR                                 ,
+       RULL(0x0E000019), SH_UNT_PERV_14  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI1_CPLT_CONF1_CLEAR                              ,
+       RULL(0x0E000029), SH_UNT_PERV_14  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI2_CPLT_CONF1                                    ,
+       RULL(0x0F000009), SH_UNT_PERV_15  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI2_CPLT_CONF1_OR                                 ,
+       RULL(0x0F000019), SH_UNT_PERV_15  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI2_CPLT_CONF1_CLEAR                              ,
+       RULL(0x0F000029), SH_UNT_PERV_15  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP00_CPLT_CONF1                                    ,
+       RULL(0x10000009), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_CPLT_CONF1_OR                                 ,
+       RULL(0x10000019), SH_UNT_PERV_16  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP00_CPLT_CONF1_CLEAR                              ,
+       RULL(0x10000029), SH_UNT_PERV_16  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP01_CPLT_CONF1                                    ,
+       RULL(0x11000009), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_CPLT_CONF1_OR                                 ,
+       RULL(0x11000019), SH_UNT_PERV_17  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP01_CPLT_CONF1_CLEAR                              ,
+       RULL(0x11000029), SH_UNT_PERV_17  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP02_CPLT_CONF1                                    ,
+       RULL(0x12000009), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_CPLT_CONF1_OR                                 ,
+       RULL(0x12000019), SH_UNT_PERV_18  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP02_CPLT_CONF1_CLEAR                              ,
+       RULL(0x12000029), SH_UNT_PERV_18  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP03_CPLT_CONF1                                    ,
+       RULL(0x13000009), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_CPLT_CONF1_OR                                 ,
+       RULL(0x13000019), SH_UNT_PERV_19  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP03_CPLT_CONF1_CLEAR                              ,
+       RULL(0x13000029), SH_UNT_PERV_19  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP04_CPLT_CONF1                                    ,
+       RULL(0x14000009), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_CPLT_CONF1_OR                                 ,
+       RULL(0x14000019), SH_UNT_PERV_20  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP04_CPLT_CONF1_CLEAR                              ,
+       RULL(0x14000029), SH_UNT_PERV_20  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP05_CPLT_CONF1                                    ,
+       RULL(0x15000009), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_CPLT_CONF1_OR                                 ,
+       RULL(0x15000019), SH_UNT_PERV_21  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP05_CPLT_CONF1_CLEAR                              ,
+       RULL(0x15000029), SH_UNT_PERV_21  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC00_CPLT_CONF1                                    ,
+       RULL(0x20000009), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPLT_CONF1_OR                                 ,
+       RULL(0x20000019), SH_UNT_PERV_32  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC00_CPLT_CONF1_CLEAR                              ,
+       RULL(0x20000029), SH_UNT_PERV_32  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC01_CPLT_CONF1                                    ,
+       RULL(0x21000009), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPLT_CONF1_OR                                 ,
+       RULL(0x21000019), SH_UNT_PERV_33  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC01_CPLT_CONF1_CLEAR                              ,
+       RULL(0x21000029), SH_UNT_PERV_33  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC02_CPLT_CONF1                                    ,
+       RULL(0x22000009), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPLT_CONF1_OR                                 ,
+       RULL(0x22000019), SH_UNT_PERV_34  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC02_CPLT_CONF1_CLEAR                              ,
+       RULL(0x22000029), SH_UNT_PERV_34  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC03_CPLT_CONF1                                    ,
+       RULL(0x23000009), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPLT_CONF1_OR                                 ,
+       RULL(0x23000019), SH_UNT_PERV_35  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC03_CPLT_CONF1_CLEAR                              ,
+       RULL(0x23000029), SH_UNT_PERV_35  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC04_CPLT_CONF1                                    ,
+       RULL(0x24000009), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPLT_CONF1_OR                                 ,
+       RULL(0x24000019), SH_UNT_PERV_36  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC04_CPLT_CONF1_CLEAR                              ,
+       RULL(0x24000029), SH_UNT_PERV_36  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC05_CPLT_CONF1                                    ,
+       RULL(0x25000009), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPLT_CONF1_OR                                 ,
+       RULL(0x25000019), SH_UNT_PERV_37  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC05_CPLT_CONF1_CLEAR                              ,
+       RULL(0x25000029), SH_UNT_PERV_37  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC06_CPLT_CONF1                                    ,
+       RULL(0x26000009), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPLT_CONF1_OR                                 ,
+       RULL(0x26000019), SH_UNT_PERV_38  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC06_CPLT_CONF1_CLEAR                              ,
+       RULL(0x26000029), SH_UNT_PERV_38  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC07_CPLT_CONF1                                    ,
+       RULL(0x27000009), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPLT_CONF1_OR                                 ,
+       RULL(0x27000019), SH_UNT_PERV_39  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC07_CPLT_CONF1_CLEAR                              ,
+       RULL(0x27000029), SH_UNT_PERV_39  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC08_CPLT_CONF1                                    ,
+       RULL(0x28000009), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPLT_CONF1_OR                                 ,
+       RULL(0x28000019), SH_UNT_PERV_40  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC08_CPLT_CONF1_CLEAR                              ,
+       RULL(0x28000029), SH_UNT_PERV_40  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC09_CPLT_CONF1                                    ,
+       RULL(0x29000009), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPLT_CONF1_OR                                 ,
+       RULL(0x29000019), SH_UNT_PERV_41  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC09_CPLT_CONF1_CLEAR                              ,
+       RULL(0x29000029), SH_UNT_PERV_41  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC10_CPLT_CONF1                                    ,
+       RULL(0x2A000009), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPLT_CONF1_OR                                 ,
+       RULL(0x2A000019), SH_UNT_PERV_42  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC10_CPLT_CONF1_CLEAR                              ,
+       RULL(0x2A000029), SH_UNT_PERV_42  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC11_CPLT_CONF1                                    ,
+       RULL(0x2B000009), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPLT_CONF1_OR                                 ,
+       RULL(0x2B000019), SH_UNT_PERV_43  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC11_CPLT_CONF1_CLEAR                              ,
+       RULL(0x2B000029), SH_UNT_PERV_43  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC12_CPLT_CONF1                                    ,
+       RULL(0x2C000009), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPLT_CONF1_OR                                 ,
+       RULL(0x2C000019), SH_UNT_PERV_44  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC12_CPLT_CONF1_CLEAR                              ,
+       RULL(0x2C000029), SH_UNT_PERV_44  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC13_CPLT_CONF1                                    ,
+       RULL(0x2D000009), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPLT_CONF1_OR                                 ,
+       RULL(0x2D000019), SH_UNT_PERV_45  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC13_CPLT_CONF1_CLEAR                              ,
+       RULL(0x2D000029), SH_UNT_PERV_45  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC14_CPLT_CONF1                                    ,
+       RULL(0x2E000009), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPLT_CONF1_OR                                 ,
+       RULL(0x2E000019), SH_UNT_PERV_46  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC14_CPLT_CONF1_CLEAR                              ,
+       RULL(0x2E000029), SH_UNT_PERV_46  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC15_CPLT_CONF1                                    ,
+       RULL(0x2F000009), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPLT_CONF1_OR                                 ,
+       RULL(0x2F000019), SH_UNT_PERV_47  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC15_CPLT_CONF1_CLEAR                              ,
+       RULL(0x2F000029), SH_UNT_PERV_47  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC16_CPLT_CONF1                                    ,
+       RULL(0x30000009), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPLT_CONF1_OR                                 ,
+       RULL(0x30000019), SH_UNT_PERV_48  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC16_CPLT_CONF1_CLEAR                              ,
+       RULL(0x30000029), SH_UNT_PERV_48  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC17_CPLT_CONF1                                    ,
+       RULL(0x31000009), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPLT_CONF1_OR                                 ,
+       RULL(0x31000019), SH_UNT_PERV_49  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC17_CPLT_CONF1_CLEAR                              ,
+       RULL(0x31000029), SH_UNT_PERV_49  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC18_CPLT_CONF1                                    ,
+       RULL(0x32000009), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPLT_CONF1_OR                                 ,
+       RULL(0x32000019), SH_UNT_PERV_50  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC18_CPLT_CONF1_CLEAR                              ,
+       RULL(0x32000029), SH_UNT_PERV_50  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC19_CPLT_CONF1                                    ,
+       RULL(0x33000009), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPLT_CONF1_OR                                 ,
+       RULL(0x33000019), SH_UNT_PERV_51  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC19_CPLT_CONF1_CLEAR                              ,
+       RULL(0x33000029), SH_UNT_PERV_51  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC20_CPLT_CONF1                                    ,
+       RULL(0x34000009), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPLT_CONF1_OR                                 ,
+       RULL(0x34000019), SH_UNT_PERV_52  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC20_CPLT_CONF1_CLEAR                              ,
+       RULL(0x34000029), SH_UNT_PERV_52  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC21_CPLT_CONF1                                    ,
+       RULL(0x35000009), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPLT_CONF1_OR                                 ,
+       RULL(0x35000019), SH_UNT_PERV_53  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC21_CPLT_CONF1_CLEAR                              ,
+       RULL(0x35000029), SH_UNT_PERV_53  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC22_CPLT_CONF1                                    ,
+       RULL(0x36000009), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPLT_CONF1_OR                                 ,
+       RULL(0x36000019), SH_UNT_PERV_54  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC22_CPLT_CONF1_CLEAR                              ,
+       RULL(0x36000029), SH_UNT_PERV_54  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC23_CPLT_CONF1                                    ,
+       RULL(0x37000009), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPLT_CONF1_OR                                 ,
+       RULL(0x37000019), SH_UNT_PERV_55  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC23_CPLT_CONF1_CLEAR                              ,
+       RULL(0x37000029), SH_UNT_PERV_55  , SH_ACS_SCOM2_CLEAR );
+
+REG64( PERV_CPLT_CTRL0                                         ,
+       RULL(0x00000000), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_CPLT_CTRL0                                      ,
+       RULL(0x01000000), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_CPLT_CTRL0_OR                                      ,
+       RULL(0x00000010), SH_UNT_PERV_1   , SH_ACS_SCOM1_OR  );
+REG64( PERV_TP_CPLT_CTRL0_OR                                   ,
+       RULL(0x01000010), SH_UNT_PERV_1   , SH_ACS_SCOM1_OR  );
+REG64( PERV_CPLT_CTRL0_CLEAR                                   ,
+       RULL(0x00000020), SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_TP_CPLT_CTRL0_CLEAR                                ,
+       RULL(0x01000020), SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N0_CPLT_CTRL0                                      ,
+       RULL(0x02000000), SH_UNT_PERV_2   , SH_ACS_SCOM_RW   );
+REG64( PERV_N0_CPLT_CTRL0_OR                                   ,
+       RULL(0x02000010), SH_UNT_PERV_2   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N0_CPLT_CTRL0_CLEAR                                ,
+       RULL(0x02000020), SH_UNT_PERV_2   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N1_CPLT_CTRL0                                      ,
+       RULL(0x03000000), SH_UNT_PERV_3   , SH_ACS_SCOM_RW   );
+REG64( PERV_N1_CPLT_CTRL0_OR                                   ,
+       RULL(0x03000010), SH_UNT_PERV_3   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N1_CPLT_CTRL0_CLEAR                                ,
+       RULL(0x03000020), SH_UNT_PERV_3   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N2_CPLT_CTRL0                                      ,
+       RULL(0x04000000), SH_UNT_PERV_4   , SH_ACS_SCOM_RW   );
+REG64( PERV_N2_CPLT_CTRL0_OR                                   ,
+       RULL(0x04000010), SH_UNT_PERV_4   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N2_CPLT_CTRL0_CLEAR                                ,
+       RULL(0x04000020), SH_UNT_PERV_4   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N3_CPLT_CTRL0                                      ,
+       RULL(0x05000000), SH_UNT_PERV_5   , SH_ACS_SCOM_RW   );
+REG64( PERV_N3_CPLT_CTRL0_OR                                   ,
+       RULL(0x05000010), SH_UNT_PERV_5   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N3_CPLT_CTRL0_CLEAR                                ,
+       RULL(0x05000020), SH_UNT_PERV_5   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_XB_CPLT_CTRL0                                      ,
+       RULL(0x06000000), SH_UNT_PERV_6   , SH_ACS_SCOM_RW   );
+REG64( PERV_XB_CPLT_CTRL0_OR                                   ,
+       RULL(0x06000010), SH_UNT_PERV_6   , SH_ACS_SCOM1_OR  );
+REG64( PERV_XB_CPLT_CTRL0_CLEAR                                ,
+       RULL(0x06000020), SH_UNT_PERV_6   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_MC01_CPLT_CTRL0                                    ,
+       RULL(0x07000000), SH_UNT_PERV_7   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC01_CPLT_CTRL0_OR                                 ,
+       RULL(0x07000010), SH_UNT_PERV_7   , SH_ACS_SCOM1_OR  );
+REG64( PERV_MC01_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x07000020), SH_UNT_PERV_7   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_MC23_CPLT_CTRL0                                    ,
+       RULL(0x08000000), SH_UNT_PERV_8   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC23_CPLT_CTRL0_OR                                 ,
+       RULL(0x08000010), SH_UNT_PERV_8   , SH_ACS_SCOM1_OR  );
+REG64( PERV_MC23_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x08000020), SH_UNT_PERV_8   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_OB0_CPLT_CTRL0                                     ,
+       RULL(0x09000000), SH_UNT_PERV_9   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB0_CPLT_CTRL0_OR                                  ,
+       RULL(0x09000010), SH_UNT_PERV_9   , SH_ACS_SCOM1_OR  );
+REG64( PERV_OB0_CPLT_CTRL0_CLEAR                               ,
+       RULL(0x09000020), SH_UNT_PERV_9   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_OB3_CPLT_CTRL0                                     ,
+       RULL(0x0C000000), SH_UNT_PERV_12  , SH_ACS_SCOM_RW   );
+REG64( PERV_OB3_CPLT_CTRL0_OR                                  ,
+       RULL(0x0C000010), SH_UNT_PERV_12  , SH_ACS_SCOM1_OR  );
+REG64( PERV_OB3_CPLT_CTRL0_CLEAR                               ,
+       RULL(0x0C000020), SH_UNT_PERV_12  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI0_CPLT_CTRL0                                    ,
+       RULL(0x0D000000), SH_UNT_PERV_13  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI0_CPLT_CTRL0_OR                                 ,
+       RULL(0x0D000010), SH_UNT_PERV_13  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI0_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x0D000020), SH_UNT_PERV_13  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI1_CPLT_CTRL0                                    ,
+       RULL(0x0E000000), SH_UNT_PERV_14  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI1_CPLT_CTRL0_OR                                 ,
+       RULL(0x0E000010), SH_UNT_PERV_14  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI1_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x0E000020), SH_UNT_PERV_14  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI2_CPLT_CTRL0                                    ,
+       RULL(0x0F000000), SH_UNT_PERV_15  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI2_CPLT_CTRL0_OR                                 ,
+       RULL(0x0F000010), SH_UNT_PERV_15  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI2_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x0F000020), SH_UNT_PERV_15  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP00_CPLT_CTRL0                                    ,
+       RULL(0x10000000), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_CPLT_CTRL0_OR                                 ,
+       RULL(0x10000010), SH_UNT_PERV_16  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP00_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x10000020), SH_UNT_PERV_16  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP01_CPLT_CTRL0                                    ,
+       RULL(0x11000000), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_CPLT_CTRL0_OR                                 ,
+       RULL(0x11000010), SH_UNT_PERV_17  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP01_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x11000020), SH_UNT_PERV_17  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP02_CPLT_CTRL0                                    ,
+       RULL(0x12000000), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_CPLT_CTRL0_OR                                 ,
+       RULL(0x12000010), SH_UNT_PERV_18  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP02_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x12000020), SH_UNT_PERV_18  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP03_CPLT_CTRL0                                    ,
+       RULL(0x13000000), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_CPLT_CTRL0_OR                                 ,
+       RULL(0x13000010), SH_UNT_PERV_19  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP03_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x13000020), SH_UNT_PERV_19  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP04_CPLT_CTRL0                                    ,
+       RULL(0x14000000), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_CPLT_CTRL0_OR                                 ,
+       RULL(0x14000010), SH_UNT_PERV_20  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP04_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x14000020), SH_UNT_PERV_20  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP05_CPLT_CTRL0                                    ,
+       RULL(0x15000000), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_CPLT_CTRL0_OR                                 ,
+       RULL(0x15000010), SH_UNT_PERV_21  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP05_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x15000020), SH_UNT_PERV_21  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC00_CPLT_CTRL0                                    ,
+       RULL(0x20000000), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPLT_CTRL0_OR                                 ,
+       RULL(0x20000010), SH_UNT_PERV_32  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC00_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x20000020), SH_UNT_PERV_32  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC01_CPLT_CTRL0                                    ,
+       RULL(0x21000000), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPLT_CTRL0_OR                                 ,
+       RULL(0x21000010), SH_UNT_PERV_33  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC01_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x21000020), SH_UNT_PERV_33  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC02_CPLT_CTRL0                                    ,
+       RULL(0x22000000), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPLT_CTRL0_OR                                 ,
+       RULL(0x22000010), SH_UNT_PERV_34  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC02_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x22000020), SH_UNT_PERV_34  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC03_CPLT_CTRL0                                    ,
+       RULL(0x23000000), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPLT_CTRL0_OR                                 ,
+       RULL(0x23000010), SH_UNT_PERV_35  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC03_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x23000020), SH_UNT_PERV_35  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC04_CPLT_CTRL0                                    ,
+       RULL(0x24000000), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPLT_CTRL0_OR                                 ,
+       RULL(0x24000010), SH_UNT_PERV_36  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC04_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x24000020), SH_UNT_PERV_36  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC05_CPLT_CTRL0                                    ,
+       RULL(0x25000000), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPLT_CTRL0_OR                                 ,
+       RULL(0x25000010), SH_UNT_PERV_37  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC05_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x25000020), SH_UNT_PERV_37  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC06_CPLT_CTRL0                                    ,
+       RULL(0x26000000), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPLT_CTRL0_OR                                 ,
+       RULL(0x26000010), SH_UNT_PERV_38  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC06_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x26000020), SH_UNT_PERV_38  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC07_CPLT_CTRL0                                    ,
+       RULL(0x27000000), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPLT_CTRL0_OR                                 ,
+       RULL(0x27000010), SH_UNT_PERV_39  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC07_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x27000020), SH_UNT_PERV_39  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC08_CPLT_CTRL0                                    ,
+       RULL(0x28000000), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPLT_CTRL0_OR                                 ,
+       RULL(0x28000010), SH_UNT_PERV_40  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC08_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x28000020), SH_UNT_PERV_40  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC09_CPLT_CTRL0                                    ,
+       RULL(0x29000000), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPLT_CTRL0_OR                                 ,
+       RULL(0x29000010), SH_UNT_PERV_41  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC09_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x29000020), SH_UNT_PERV_41  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC10_CPLT_CTRL0                                    ,
+       RULL(0x2A000000), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPLT_CTRL0_OR                                 ,
+       RULL(0x2A000010), SH_UNT_PERV_42  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC10_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x2A000020), SH_UNT_PERV_42  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC11_CPLT_CTRL0                                    ,
+       RULL(0x2B000000), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPLT_CTRL0_OR                                 ,
+       RULL(0x2B000010), SH_UNT_PERV_43  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC11_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x2B000020), SH_UNT_PERV_43  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC12_CPLT_CTRL0                                    ,
+       RULL(0x2C000000), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPLT_CTRL0_OR                                 ,
+       RULL(0x2C000010), SH_UNT_PERV_44  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC12_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x2C000020), SH_UNT_PERV_44  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC13_CPLT_CTRL0                                    ,
+       RULL(0x2D000000), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPLT_CTRL0_OR                                 ,
+       RULL(0x2D000010), SH_UNT_PERV_45  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC13_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x2D000020), SH_UNT_PERV_45  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC14_CPLT_CTRL0                                    ,
+       RULL(0x2E000000), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPLT_CTRL0_OR                                 ,
+       RULL(0x2E000010), SH_UNT_PERV_46  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC14_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x2E000020), SH_UNT_PERV_46  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC15_CPLT_CTRL0                                    ,
+       RULL(0x2F000000), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPLT_CTRL0_OR                                 ,
+       RULL(0x2F000010), SH_UNT_PERV_47  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC15_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x2F000020), SH_UNT_PERV_47  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC16_CPLT_CTRL0                                    ,
+       RULL(0x30000000), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPLT_CTRL0_OR                                 ,
+       RULL(0x30000010), SH_UNT_PERV_48  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC16_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x30000020), SH_UNT_PERV_48  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC17_CPLT_CTRL0                                    ,
+       RULL(0x31000000), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPLT_CTRL0_OR                                 ,
+       RULL(0x31000010), SH_UNT_PERV_49  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC17_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x31000020), SH_UNT_PERV_49  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC18_CPLT_CTRL0                                    ,
+       RULL(0x32000000), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPLT_CTRL0_OR                                 ,
+       RULL(0x32000010), SH_UNT_PERV_50  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC18_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x32000020), SH_UNT_PERV_50  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC19_CPLT_CTRL0                                    ,
+       RULL(0x33000000), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPLT_CTRL0_OR                                 ,
+       RULL(0x33000010), SH_UNT_PERV_51  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC19_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x33000020), SH_UNT_PERV_51  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC20_CPLT_CTRL0                                    ,
+       RULL(0x34000000), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPLT_CTRL0_OR                                 ,
+       RULL(0x34000010), SH_UNT_PERV_52  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC20_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x34000020), SH_UNT_PERV_52  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC21_CPLT_CTRL0                                    ,
+       RULL(0x35000000), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPLT_CTRL0_OR                                 ,
+       RULL(0x35000010), SH_UNT_PERV_53  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC21_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x35000020), SH_UNT_PERV_53  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC22_CPLT_CTRL0                                    ,
+       RULL(0x36000000), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPLT_CTRL0_OR                                 ,
+       RULL(0x36000010), SH_UNT_PERV_54  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC22_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x36000020), SH_UNT_PERV_54  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC23_CPLT_CTRL0                                    ,
+       RULL(0x37000000), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPLT_CTRL0_OR                                 ,
+       RULL(0x37000010), SH_UNT_PERV_55  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC23_CPLT_CTRL0_CLEAR                              ,
+       RULL(0x37000020), SH_UNT_PERV_55  , SH_ACS_SCOM2_CLEAR );
+
+REG64( PERV_CPLT_CTRL1                                         ,
+       RULL(0x00000001), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_CPLT_CTRL1                                      ,
+       RULL(0x01000001), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_CPLT_CTRL1_OR                                      ,
+       RULL(0x00000011), SH_UNT_PERV_1   , SH_ACS_SCOM1_OR  );
+REG64( PERV_TP_CPLT_CTRL1_OR                                   ,
+       RULL(0x01000011), SH_UNT_PERV_1   , SH_ACS_SCOM1_OR  );
+REG64( PERV_CPLT_CTRL1_CLEAR                                   ,
+       RULL(0x00000021), SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_TP_CPLT_CTRL1_CLEAR                                ,
+       RULL(0x01000021), SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N0_CPLT_CTRL1                                      ,
+       RULL(0x02000001), SH_UNT_PERV_2   , SH_ACS_SCOM_RW   );
+REG64( PERV_N0_CPLT_CTRL1_OR                                   ,
+       RULL(0x02000011), SH_UNT_PERV_2   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N0_CPLT_CTRL1_CLEAR                                ,
+       RULL(0x02000021), SH_UNT_PERV_2   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N1_CPLT_CTRL1                                      ,
+       RULL(0x03000001), SH_UNT_PERV_3   , SH_ACS_SCOM_RW   );
+REG64( PERV_N1_CPLT_CTRL1_OR                                   ,
+       RULL(0x03000011), SH_UNT_PERV_3   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N1_CPLT_CTRL1_CLEAR                                ,
+       RULL(0x03000021), SH_UNT_PERV_3   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N2_CPLT_CTRL1                                      ,
+       RULL(0x04000001), SH_UNT_PERV_4   , SH_ACS_SCOM_RW   );
+REG64( PERV_N2_CPLT_CTRL1_OR                                   ,
+       RULL(0x04000011), SH_UNT_PERV_4   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N2_CPLT_CTRL1_CLEAR                                ,
+       RULL(0x04000021), SH_UNT_PERV_4   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N3_CPLT_CTRL1                                      ,
+       RULL(0x05000001), SH_UNT_PERV_5   , SH_ACS_SCOM_RW   );
+REG64( PERV_N3_CPLT_CTRL1_OR                                   ,
+       RULL(0x05000011), SH_UNT_PERV_5   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N3_CPLT_CTRL1_CLEAR                                ,
+       RULL(0x05000021), SH_UNT_PERV_5   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_XB_CPLT_CTRL1                                      ,
+       RULL(0x06000001), SH_UNT_PERV_6   , SH_ACS_SCOM_RW   );
+REG64( PERV_XB_CPLT_CTRL1_OR                                   ,
+       RULL(0x06000011), SH_UNT_PERV_6   , SH_ACS_SCOM1_OR  );
+REG64( PERV_XB_CPLT_CTRL1_CLEAR                                ,
+       RULL(0x06000021), SH_UNT_PERV_6   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_MC01_CPLT_CTRL1                                    ,
+       RULL(0x07000001), SH_UNT_PERV_7   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC01_CPLT_CTRL1_OR                                 ,
+       RULL(0x07000011), SH_UNT_PERV_7   , SH_ACS_SCOM1_OR  );
+REG64( PERV_MC01_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x07000021), SH_UNT_PERV_7   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_MC23_CPLT_CTRL1                                    ,
+       RULL(0x08000001), SH_UNT_PERV_8   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC23_CPLT_CTRL1_OR                                 ,
+       RULL(0x08000011), SH_UNT_PERV_8   , SH_ACS_SCOM1_OR  );
+REG64( PERV_MC23_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x08000021), SH_UNT_PERV_8   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_OB0_CPLT_CTRL1                                     ,
+       RULL(0x09000001), SH_UNT_PERV_9   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB0_CPLT_CTRL1_OR                                  ,
+       RULL(0x09000011), SH_UNT_PERV_9   , SH_ACS_SCOM1_OR  );
+REG64( PERV_OB0_CPLT_CTRL1_CLEAR                               ,
+       RULL(0x09000021), SH_UNT_PERV_9   , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_OB3_CPLT_CTRL1                                     ,
+       RULL(0x0C000001), SH_UNT_PERV_12  , SH_ACS_SCOM_RW   );
+REG64( PERV_OB3_CPLT_CTRL1_OR                                  ,
+       RULL(0x0C000011), SH_UNT_PERV_12  , SH_ACS_SCOM1_OR  );
+REG64( PERV_OB3_CPLT_CTRL1_CLEAR                               ,
+       RULL(0x0C000021), SH_UNT_PERV_12  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI0_CPLT_CTRL1                                    ,
+       RULL(0x0D000001), SH_UNT_PERV_13  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI0_CPLT_CTRL1_OR                                 ,
+       RULL(0x0D000011), SH_UNT_PERV_13  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI0_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x0D000021), SH_UNT_PERV_13  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI1_CPLT_CTRL1                                    ,
+       RULL(0x0E000001), SH_UNT_PERV_14  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI1_CPLT_CTRL1_OR                                 ,
+       RULL(0x0E000011), SH_UNT_PERV_14  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI1_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x0E000021), SH_UNT_PERV_14  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI2_CPLT_CTRL1                                    ,
+       RULL(0x0F000001), SH_UNT_PERV_15  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI2_CPLT_CTRL1_OR                                 ,
+       RULL(0x0F000011), SH_UNT_PERV_15  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI2_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x0F000021), SH_UNT_PERV_15  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP00_CPLT_CTRL1                                    ,
+       RULL(0x10000001), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_CPLT_CTRL1_OR                                 ,
+       RULL(0x10000011), SH_UNT_PERV_16  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP00_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x10000021), SH_UNT_PERV_16  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP01_CPLT_CTRL1                                    ,
+       RULL(0x11000001), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_CPLT_CTRL1_OR                                 ,
+       RULL(0x11000011), SH_UNT_PERV_17  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP01_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x11000021), SH_UNT_PERV_17  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP02_CPLT_CTRL1                                    ,
+       RULL(0x12000001), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_CPLT_CTRL1_OR                                 ,
+       RULL(0x12000011), SH_UNT_PERV_18  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP02_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x12000021), SH_UNT_PERV_18  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP03_CPLT_CTRL1                                    ,
+       RULL(0x13000001), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_CPLT_CTRL1_OR                                 ,
+       RULL(0x13000011), SH_UNT_PERV_19  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP03_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x13000021), SH_UNT_PERV_19  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP04_CPLT_CTRL1                                    ,
+       RULL(0x14000001), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_CPLT_CTRL1_OR                                 ,
+       RULL(0x14000011), SH_UNT_PERV_20  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP04_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x14000021), SH_UNT_PERV_20  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP05_CPLT_CTRL1                                    ,
+       RULL(0x15000001), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_CPLT_CTRL1_OR                                 ,
+       RULL(0x15000011), SH_UNT_PERV_21  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP05_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x15000021), SH_UNT_PERV_21  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC00_CPLT_CTRL1                                    ,
+       RULL(0x20000001), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPLT_CTRL1_OR                                 ,
+       RULL(0x20000011), SH_UNT_PERV_32  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC00_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x20000021), SH_UNT_PERV_32  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC01_CPLT_CTRL1                                    ,
+       RULL(0x21000001), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPLT_CTRL1_OR                                 ,
+       RULL(0x21000011), SH_UNT_PERV_33  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC01_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x21000021), SH_UNT_PERV_33  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC02_CPLT_CTRL1                                    ,
+       RULL(0x22000001), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPLT_CTRL1_OR                                 ,
+       RULL(0x22000011), SH_UNT_PERV_34  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC02_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x22000021), SH_UNT_PERV_34  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC03_CPLT_CTRL1                                    ,
+       RULL(0x23000001), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPLT_CTRL1_OR                                 ,
+       RULL(0x23000011), SH_UNT_PERV_35  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC03_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x23000021), SH_UNT_PERV_35  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC04_CPLT_CTRL1                                    ,
+       RULL(0x24000001), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPLT_CTRL1_OR                                 ,
+       RULL(0x24000011), SH_UNT_PERV_36  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC04_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x24000021), SH_UNT_PERV_36  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC05_CPLT_CTRL1                                    ,
+       RULL(0x25000001), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPLT_CTRL1_OR                                 ,
+       RULL(0x25000011), SH_UNT_PERV_37  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC05_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x25000021), SH_UNT_PERV_37  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC06_CPLT_CTRL1                                    ,
+       RULL(0x26000001), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPLT_CTRL1_OR                                 ,
+       RULL(0x26000011), SH_UNT_PERV_38  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC06_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x26000021), SH_UNT_PERV_38  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC07_CPLT_CTRL1                                    ,
+       RULL(0x27000001), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPLT_CTRL1_OR                                 ,
+       RULL(0x27000011), SH_UNT_PERV_39  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC07_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x27000021), SH_UNT_PERV_39  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC08_CPLT_CTRL1                                    ,
+       RULL(0x28000001), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPLT_CTRL1_OR                                 ,
+       RULL(0x28000011), SH_UNT_PERV_40  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC08_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x28000021), SH_UNT_PERV_40  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC09_CPLT_CTRL1                                    ,
+       RULL(0x29000001), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPLT_CTRL1_OR                                 ,
+       RULL(0x29000011), SH_UNT_PERV_41  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC09_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x29000021), SH_UNT_PERV_41  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC10_CPLT_CTRL1                                    ,
+       RULL(0x2A000001), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPLT_CTRL1_OR                                 ,
+       RULL(0x2A000011), SH_UNT_PERV_42  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC10_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x2A000021), SH_UNT_PERV_42  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC11_CPLT_CTRL1                                    ,
+       RULL(0x2B000001), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPLT_CTRL1_OR                                 ,
+       RULL(0x2B000011), SH_UNT_PERV_43  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC11_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x2B000021), SH_UNT_PERV_43  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC12_CPLT_CTRL1                                    ,
+       RULL(0x2C000001), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPLT_CTRL1_OR                                 ,
+       RULL(0x2C000011), SH_UNT_PERV_44  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC12_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x2C000021), SH_UNT_PERV_44  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC13_CPLT_CTRL1                                    ,
+       RULL(0x2D000001), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPLT_CTRL1_OR                                 ,
+       RULL(0x2D000011), SH_UNT_PERV_45  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC13_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x2D000021), SH_UNT_PERV_45  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC14_CPLT_CTRL1                                    ,
+       RULL(0x2E000001), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPLT_CTRL1_OR                                 ,
+       RULL(0x2E000011), SH_UNT_PERV_46  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC14_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x2E000021), SH_UNT_PERV_46  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC15_CPLT_CTRL1                                    ,
+       RULL(0x2F000001), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPLT_CTRL1_OR                                 ,
+       RULL(0x2F000011), SH_UNT_PERV_47  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC15_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x2F000021), SH_UNT_PERV_47  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC16_CPLT_CTRL1                                    ,
+       RULL(0x30000001), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPLT_CTRL1_OR                                 ,
+       RULL(0x30000011), SH_UNT_PERV_48  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC16_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x30000021), SH_UNT_PERV_48  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC17_CPLT_CTRL1                                    ,
+       RULL(0x31000001), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPLT_CTRL1_OR                                 ,
+       RULL(0x31000011), SH_UNT_PERV_49  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC17_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x31000021), SH_UNT_PERV_49  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC18_CPLT_CTRL1                                    ,
+       RULL(0x32000001), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPLT_CTRL1_OR                                 ,
+       RULL(0x32000011), SH_UNT_PERV_50  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC18_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x32000021), SH_UNT_PERV_50  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC19_CPLT_CTRL1                                    ,
+       RULL(0x33000001), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPLT_CTRL1_OR                                 ,
+       RULL(0x33000011), SH_UNT_PERV_51  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC19_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x33000021), SH_UNT_PERV_51  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC20_CPLT_CTRL1                                    ,
+       RULL(0x34000001), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPLT_CTRL1_OR                                 ,
+       RULL(0x34000011), SH_UNT_PERV_52  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC20_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x34000021), SH_UNT_PERV_52  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC21_CPLT_CTRL1                                    ,
+       RULL(0x35000001), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPLT_CTRL1_OR                                 ,
+       RULL(0x35000011), SH_UNT_PERV_53  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC21_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x35000021), SH_UNT_PERV_53  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC22_CPLT_CTRL1                                    ,
+       RULL(0x36000001), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPLT_CTRL1_OR                                 ,
+       RULL(0x36000011), SH_UNT_PERV_54  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC22_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x36000021), SH_UNT_PERV_54  , SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC23_CPLT_CTRL1                                    ,
+       RULL(0x37000001), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPLT_CTRL1_OR                                 ,
+       RULL(0x37000011), SH_UNT_PERV_55  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC23_CPLT_CTRL1_CLEAR                              ,
+       RULL(0x37000021), SH_UNT_PERV_55  , SH_ACS_SCOM2_CLEAR );
+
+REG64( PERV_CPLT_MASK0                                         ,
+       RULL(0x00000101), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_CPLT_MASK0                                      ,
+       RULL(0x01000101), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_CPLT_MASK0                                      ,
+       RULL(0x02000101), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_CPLT_MASK0                                      ,
+       RULL(0x03000101), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_CPLT_MASK0                                      ,
+       RULL(0x04000101), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_CPLT_MASK0                                      ,
+       RULL(0x05000101), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_CPLT_MASK0                                      ,
+       RULL(0x06000101), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_CPLT_MASK0                                    ,
+       RULL(0x07000101), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_CPLT_MASK0                                    ,
+       RULL(0x08000101), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_CPLT_MASK0                                     ,
+       RULL(0x09000101), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_CPLT_MASK0                                     ,
+       RULL(0x0C000101), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_CPLT_MASK0                                    ,
+       RULL(0x0D000101), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_CPLT_MASK0                                    ,
+       RULL(0x0E000101), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_CPLT_MASK0                                    ,
+       RULL(0x0F000101), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_CPLT_MASK0                                    ,
+       RULL(0x10000101), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_CPLT_MASK0                                    ,
+       RULL(0x11000101), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_CPLT_MASK0                                    ,
+       RULL(0x12000101), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_CPLT_MASK0                                    ,
+       RULL(0x13000101), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_CPLT_MASK0                                    ,
+       RULL(0x14000101), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_CPLT_MASK0                                    ,
+       RULL(0x15000101), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_CPLT_MASK0                                    ,
+       RULL(0x20000101), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CPLT_MASK0                                    ,
+       RULL(0x21000101), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CPLT_MASK0                                    ,
+       RULL(0x22000101), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CPLT_MASK0                                    ,
+       RULL(0x23000101), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CPLT_MASK0                                    ,
+       RULL(0x24000101), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CPLT_MASK0                                    ,
+       RULL(0x25000101), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CPLT_MASK0                                    ,
+       RULL(0x26000101), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CPLT_MASK0                                    ,
+       RULL(0x27000101), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CPLT_MASK0                                    ,
+       RULL(0x28000101), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CPLT_MASK0                                    ,
+       RULL(0x29000101), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CPLT_MASK0                                    ,
+       RULL(0x2A000101), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CPLT_MASK0                                    ,
+       RULL(0x2B000101), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CPLT_MASK0                                    ,
+       RULL(0x2C000101), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CPLT_MASK0                                    ,
+       RULL(0x2D000101), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CPLT_MASK0                                    ,
+       RULL(0x2E000101), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CPLT_MASK0                                    ,
+       RULL(0x2F000101), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CPLT_MASK0                                    ,
+       RULL(0x30000101), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CPLT_MASK0                                    ,
+       RULL(0x31000101), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CPLT_MASK0                                    ,
+       RULL(0x32000101), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CPLT_MASK0                                    ,
+       RULL(0x33000101), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CPLT_MASK0                                    ,
+       RULL(0x34000101), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CPLT_MASK0                                    ,
+       RULL(0x35000101), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CPLT_MASK0                                    ,
+       RULL(0x36000101), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CPLT_MASK0                                    ,
+       RULL(0x37000101), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_CPLT_STAT0                                         ,
+       RULL(0x00000100), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_CPLT_STAT0                                      ,
+       RULL(0x01000100), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_CPLT_STAT0                                      ,
+       RULL(0x02000100), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_CPLT_STAT0                                      ,
+       RULL(0x03000100), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_CPLT_STAT0                                      ,
+       RULL(0x04000100), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_CPLT_STAT0                                      ,
+       RULL(0x05000100), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_CPLT_STAT0                                      ,
+       RULL(0x06000100), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_CPLT_STAT0                                    ,
+       RULL(0x07000100), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_CPLT_STAT0                                    ,
+       RULL(0x08000100), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_CPLT_STAT0                                     ,
+       RULL(0x09000100), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_CPLT_STAT0                                     ,
+       RULL(0x0C000100), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_CPLT_STAT0                                    ,
+       RULL(0x0D000100), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_CPLT_STAT0                                    ,
+       RULL(0x0E000100), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_CPLT_STAT0                                    ,
+       RULL(0x0F000100), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_CPLT_STAT0                                    ,
+       RULL(0x10000100), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_CPLT_STAT0                                    ,
+       RULL(0x11000100), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_CPLT_STAT0                                    ,
+       RULL(0x12000100), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_CPLT_STAT0                                    ,
+       RULL(0x13000100), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_CPLT_STAT0                                    ,
+       RULL(0x14000100), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_CPLT_STAT0                                    ,
+       RULL(0x15000100), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_CPLT_STAT0                                    ,
+       RULL(0x20000100), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CPLT_STAT0                                    ,
+       RULL(0x21000100), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CPLT_STAT0                                    ,
+       RULL(0x22000100), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CPLT_STAT0                                    ,
+       RULL(0x23000100), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CPLT_STAT0                                    ,
+       RULL(0x24000100), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CPLT_STAT0                                    ,
+       RULL(0x25000100), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CPLT_STAT0                                    ,
+       RULL(0x26000100), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CPLT_STAT0                                    ,
+       RULL(0x27000100), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CPLT_STAT0                                    ,
+       RULL(0x28000100), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CPLT_STAT0                                    ,
+       RULL(0x29000100), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CPLT_STAT0                                    ,
+       RULL(0x2A000100), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CPLT_STAT0                                    ,
+       RULL(0x2B000100), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CPLT_STAT0                                    ,
+       RULL(0x2C000100), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CPLT_STAT0                                    ,
+       RULL(0x2D000100), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CPLT_STAT0                                    ,
+       RULL(0x2E000100), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CPLT_STAT0                                    ,
+       RULL(0x2F000100), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CPLT_STAT0                                    ,
+       RULL(0x30000100), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CPLT_STAT0                                    ,
+       RULL(0x31000100), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CPLT_STAT0                                    ,
+       RULL(0x32000100), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CPLT_STAT0                                    ,
+       RULL(0x33000100), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CPLT_STAT0                                    ,
+       RULL(0x34000100), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CPLT_STAT0                                    ,
+       RULL(0x35000100), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CPLT_STAT0                                    ,
+       RULL(0x36000100), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CPLT_STAT0                                    ,
+       RULL(0x37000100), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_EC00_CPPM_CACCR                                    ,
+       RULL(0x200F0168), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPPM_CACCR_CLEAR                              ,
+       RULL(0x200F0169), SH_UNT_PERV_32  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC00_CPPM_CACCR_OR                                 ,
+       RULL(0x200F016A), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_CPPM_CACCR                                    ,
+       RULL(0x210F0168), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_CACCR_CLEAR                              ,
+       RULL(0x210F0169), SH_UNT_PERV_33  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC01_CPPM_CACCR_OR                                 ,
+       RULL(0x210F016A), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_CPPM_CACCR                                    ,
+       RULL(0x220F0168), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_CACCR_CLEAR                              ,
+       RULL(0x220F0169), SH_UNT_PERV_34  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC02_CPPM_CACCR_OR                                 ,
+       RULL(0x220F016A), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_CPPM_CACCR                                    ,
+       RULL(0x230F0168), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_CACCR_CLEAR                              ,
+       RULL(0x230F0169), SH_UNT_PERV_35  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC03_CPPM_CACCR_OR                                 ,
+       RULL(0x230F016A), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_CPPM_CACCR                                    ,
+       RULL(0x240F0168), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_CACCR_CLEAR                              ,
+       RULL(0x240F0169), SH_UNT_PERV_36  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC04_CPPM_CACCR_OR                                 ,
+       RULL(0x240F016A), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_CPPM_CACCR                                    ,
+       RULL(0x250F0168), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_CACCR_CLEAR                              ,
+       RULL(0x250F0169), SH_UNT_PERV_37  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC05_CPPM_CACCR_OR                                 ,
+       RULL(0x250F016A), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_CPPM_CACCR                                    ,
+       RULL(0x260F0168), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_CACCR_CLEAR                              ,
+       RULL(0x260F0169), SH_UNT_PERV_38  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC06_CPPM_CACCR_OR                                 ,
+       RULL(0x260F016A), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_CPPM_CACCR                                    ,
+       RULL(0x270F0168), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_CACCR_CLEAR                              ,
+       RULL(0x270F0169), SH_UNT_PERV_39  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC07_CPPM_CACCR_OR                                 ,
+       RULL(0x270F016A), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_CPPM_CACCR                                    ,
+       RULL(0x280F0168), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_CACCR_CLEAR                              ,
+       RULL(0x280F0169), SH_UNT_PERV_40  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC08_CPPM_CACCR_OR                                 ,
+       RULL(0x280F016A), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_CPPM_CACCR                                    ,
+       RULL(0x290F0168), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_CACCR_CLEAR                              ,
+       RULL(0x290F0169), SH_UNT_PERV_41  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC09_CPPM_CACCR_OR                                 ,
+       RULL(0x290F016A), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_CPPM_CACCR                                    ,
+       RULL(0x2A0F0168), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_CACCR_CLEAR                              ,
+       RULL(0x2A0F0169), SH_UNT_PERV_42  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC10_CPPM_CACCR_OR                                 ,
+       RULL(0x2A0F016A), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_CPPM_CACCR                                    ,
+       RULL(0x2B0F0168), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_CACCR_CLEAR                              ,
+       RULL(0x2B0F0169), SH_UNT_PERV_43  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC11_CPPM_CACCR_OR                                 ,
+       RULL(0x2B0F016A), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_CPPM_CACCR                                    ,
+       RULL(0x2C0F0168), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_CACCR_CLEAR                              ,
+       RULL(0x2C0F0169), SH_UNT_PERV_44  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC12_CPPM_CACCR_OR                                 ,
+       RULL(0x2C0F016A), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_CPPM_CACCR                                    ,
+       RULL(0x2D0F0168), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_CACCR_CLEAR                              ,
+       RULL(0x2D0F0169), SH_UNT_PERV_45  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC13_CPPM_CACCR_OR                                 ,
+       RULL(0x2D0F016A), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_CPPM_CACCR                                    ,
+       RULL(0x2E0F0168), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_CACCR_CLEAR                              ,
+       RULL(0x2E0F0169), SH_UNT_PERV_46  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC14_CPPM_CACCR_OR                                 ,
+       RULL(0x2E0F016A), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_CPPM_CACCR                                    ,
+       RULL(0x2F0F0168), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_CACCR_CLEAR                              ,
+       RULL(0x2F0F0169), SH_UNT_PERV_47  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC15_CPPM_CACCR_OR                                 ,
+       RULL(0x2F0F016A), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_CPPM_CACCR                                    ,
+       RULL(0x300F0168), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_CACCR_CLEAR                              ,
+       RULL(0x300F0169), SH_UNT_PERV_48  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC16_CPPM_CACCR_OR                                 ,
+       RULL(0x300F016A), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_CPPM_CACCR                                    ,
+       RULL(0x310F0168), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_CACCR_CLEAR                              ,
+       RULL(0x310F0169), SH_UNT_PERV_49  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC17_CPPM_CACCR_OR                                 ,
+       RULL(0x310F016A), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_CPPM_CACCR                                    ,
+       RULL(0x320F0168), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_CACCR_CLEAR                              ,
+       RULL(0x320F0169), SH_UNT_PERV_50  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC18_CPPM_CACCR_OR                                 ,
+       RULL(0x320F016A), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_CPPM_CACCR                                    ,
+       RULL(0x330F0168), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_CACCR_CLEAR                              ,
+       RULL(0x330F0169), SH_UNT_PERV_51  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC19_CPPM_CACCR_OR                                 ,
+       RULL(0x330F016A), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_CPPM_CACCR                                    ,
+       RULL(0x340F0168), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_CACCR_CLEAR                              ,
+       RULL(0x340F0169), SH_UNT_PERV_52  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC20_CPPM_CACCR_OR                                 ,
+       RULL(0x340F016A), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_CPPM_CACCR                                    ,
+       RULL(0x350F0168), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_CACCR_CLEAR                              ,
+       RULL(0x350F0169), SH_UNT_PERV_53  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC21_CPPM_CACCR_OR                                 ,
+       RULL(0x350F016A), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_CPPM_CACCR                                    ,
+       RULL(0x360F0168), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_CACCR_CLEAR                              ,
+       RULL(0x360F0169), SH_UNT_PERV_54  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC22_CPPM_CACCR_OR                                 ,
+       RULL(0x360F016A), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_CPPM_CACCR                                    ,
+       RULL(0x370F0168), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_CACCR_CLEAR                              ,
+       RULL(0x370F0169), SH_UNT_PERV_55  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC23_CPPM_CACCR_OR                                 ,
+       RULL(0x370F016A), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EC00_CPPM_CACSR                                    ,
+       RULL(0x200F016B), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_CPPM_CACSR                                    ,
+       RULL(0x210F016B), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_CPPM_CACSR                                    ,
+       RULL(0x220F016B), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_CPPM_CACSR                                    ,
+       RULL(0x230F016B), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_CPPM_CACSR                                    ,
+       RULL(0x240F016B), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_CPPM_CACSR                                    ,
+       RULL(0x250F016B), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_CPPM_CACSR                                    ,
+       RULL(0x260F016B), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_CPPM_CACSR                                    ,
+       RULL(0x270F016B), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_CPPM_CACSR                                    ,
+       RULL(0x280F016B), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_CPPM_CACSR                                    ,
+       RULL(0x290F016B), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_CPPM_CACSR                                    ,
+       RULL(0x2A0F016B), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_CPPM_CACSR                                    ,
+       RULL(0x2B0F016B), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_CPPM_CACSR                                    ,
+       RULL(0x2C0F016B), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_CPPM_CACSR                                    ,
+       RULL(0x2D0F016B), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_CPPM_CACSR                                    ,
+       RULL(0x2E0F016B), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_CPPM_CACSR                                    ,
+       RULL(0x2F0F016B), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_CPPM_CACSR                                    ,
+       RULL(0x300F016B), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_CPPM_CACSR                                    ,
+       RULL(0x310F016B), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_CPPM_CACSR                                    ,
+       RULL(0x320F016B), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_CPPM_CACSR                                    ,
+       RULL(0x330F016B), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_CPPM_CACSR                                    ,
+       RULL(0x340F016B), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_CPPM_CACSR                                    ,
+       RULL(0x350F016B), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_CPPM_CACSR                                    ,
+       RULL(0x360F016B), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_CPPM_CACSR                                    ,
+       RULL(0x370F016B), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_EC00_CPPM_CISR                                     ,
+       RULL(0x200F01AE), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_CPPM_CISR                                     ,
+       RULL(0x210F01AE), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_CPPM_CISR                                     ,
+       RULL(0x220F01AE), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_CPPM_CISR                                     ,
+       RULL(0x230F01AE), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_CPPM_CISR                                     ,
+       RULL(0x240F01AE), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_CPPM_CISR                                     ,
+       RULL(0x250F01AE), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_CPPM_CISR                                     ,
+       RULL(0x260F01AE), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_CPPM_CISR                                     ,
+       RULL(0x270F01AE), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_CPPM_CISR                                     ,
+       RULL(0x280F01AE), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_CPPM_CISR                                     ,
+       RULL(0x290F01AE), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_CPPM_CISR                                     ,
+       RULL(0x2A0F01AE), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_CPPM_CISR                                     ,
+       RULL(0x2B0F01AE), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_CPPM_CISR                                     ,
+       RULL(0x2C0F01AE), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_CPPM_CISR                                     ,
+       RULL(0x2D0F01AE), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_CPPM_CISR                                     ,
+       RULL(0x2E0F01AE), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_CPPM_CISR                                     ,
+       RULL(0x2F0F01AE), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_CPPM_CISR                                     ,
+       RULL(0x300F01AE), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_CPPM_CISR                                     ,
+       RULL(0x310F01AE), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_CPPM_CISR                                     ,
+       RULL(0x320F01AE), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_CPPM_CISR                                     ,
+       RULL(0x330F01AE), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_CPPM_CISR                                     ,
+       RULL(0x340F01AE), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_CPPM_CISR                                     ,
+       RULL(0x350F01AE), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_CPPM_CISR                                     ,
+       RULL(0x360F01AE), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_CPPM_CISR                                     ,
+       RULL(0x370F01AE), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_EC00_CPPM_CIVRMLCR                                 ,
+       RULL(0x200F01B7), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_CIVRMLCR                                 ,
+       RULL(0x210F01B7), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_CIVRMLCR                                 ,
+       RULL(0x220F01B7), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_CIVRMLCR                                 ,
+       RULL(0x230F01B7), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_CIVRMLCR                                 ,
+       RULL(0x240F01B7), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_CIVRMLCR                                 ,
+       RULL(0x250F01B7), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_CIVRMLCR                                 ,
+       RULL(0x260F01B7), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_CIVRMLCR                                 ,
+       RULL(0x270F01B7), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_CIVRMLCR                                 ,
+       RULL(0x280F01B7), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_CIVRMLCR                                 ,
+       RULL(0x290F01B7), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_CIVRMLCR                                 ,
+       RULL(0x2A0F01B7), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_CIVRMLCR                                 ,
+       RULL(0x2B0F01B7), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_CIVRMLCR                                 ,
+       RULL(0x2C0F01B7), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_CIVRMLCR                                 ,
+       RULL(0x2D0F01B7), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_CIVRMLCR                                 ,
+       RULL(0x2E0F01B7), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_CIVRMLCR                                 ,
+       RULL(0x2F0F01B7), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_CIVRMLCR                                 ,
+       RULL(0x300F01B7), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_CIVRMLCR                                 ,
+       RULL(0x310F01B7), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_CIVRMLCR                                 ,
+       RULL(0x320F01B7), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_CIVRMLCR                                 ,
+       RULL(0x330F01B7), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_CIVRMLCR                                 ,
+       RULL(0x340F01B7), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_CIVRMLCR                                 ,
+       RULL(0x350F01B7), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_CIVRMLCR                                 ,
+       RULL(0x360F01B7), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_CIVRMLCR                                 ,
+       RULL(0x370F01B7), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EC00_CPPM_CMEDATA                                  ,
+       RULL(0x200F01A8), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x200F01A9), SH_UNT_PERV_32  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC00_CPPM_CMEDATA_OR                               ,
+       RULL(0x200F01AA), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_CPPM_CMEDATA                                  ,
+       RULL(0x210F01A8), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x210F01A9), SH_UNT_PERV_33  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC01_CPPM_CMEDATA_OR                               ,
+       RULL(0x210F01AA), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_CPPM_CMEDATA                                  ,
+       RULL(0x220F01A8), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x220F01A9), SH_UNT_PERV_34  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC02_CPPM_CMEDATA_OR                               ,
+       RULL(0x220F01AA), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_CPPM_CMEDATA                                  ,
+       RULL(0x230F01A8), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x230F01A9), SH_UNT_PERV_35  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC03_CPPM_CMEDATA_OR                               ,
+       RULL(0x230F01AA), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_CPPM_CMEDATA                                  ,
+       RULL(0x240F01A8), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x240F01A9), SH_UNT_PERV_36  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC04_CPPM_CMEDATA_OR                               ,
+       RULL(0x240F01AA), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_CPPM_CMEDATA                                  ,
+       RULL(0x250F01A8), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x250F01A9), SH_UNT_PERV_37  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC05_CPPM_CMEDATA_OR                               ,
+       RULL(0x250F01AA), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_CPPM_CMEDATA                                  ,
+       RULL(0x260F01A8), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x260F01A9), SH_UNT_PERV_38  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC06_CPPM_CMEDATA_OR                               ,
+       RULL(0x260F01AA), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_CPPM_CMEDATA                                  ,
+       RULL(0x270F01A8), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x270F01A9), SH_UNT_PERV_39  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC07_CPPM_CMEDATA_OR                               ,
+       RULL(0x270F01AA), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_CPPM_CMEDATA                                  ,
+       RULL(0x280F01A8), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x280F01A9), SH_UNT_PERV_40  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC08_CPPM_CMEDATA_OR                               ,
+       RULL(0x280F01AA), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_CPPM_CMEDATA                                  ,
+       RULL(0x290F01A8), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x290F01A9), SH_UNT_PERV_41  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC09_CPPM_CMEDATA_OR                               ,
+       RULL(0x290F01AA), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_CPPM_CMEDATA                                  ,
+       RULL(0x2A0F01A8), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x2A0F01A9), SH_UNT_PERV_42  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC10_CPPM_CMEDATA_OR                               ,
+       RULL(0x2A0F01AA), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_CPPM_CMEDATA                                  ,
+       RULL(0x2B0F01A8), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x2B0F01A9), SH_UNT_PERV_43  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC11_CPPM_CMEDATA_OR                               ,
+       RULL(0x2B0F01AA), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_CPPM_CMEDATA                                  ,
+       RULL(0x2C0F01A8), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x2C0F01A9), SH_UNT_PERV_44  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC12_CPPM_CMEDATA_OR                               ,
+       RULL(0x2C0F01AA), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_CPPM_CMEDATA                                  ,
+       RULL(0x2D0F01A8), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x2D0F01A9), SH_UNT_PERV_45  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC13_CPPM_CMEDATA_OR                               ,
+       RULL(0x2D0F01AA), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_CPPM_CMEDATA                                  ,
+       RULL(0x2E0F01A8), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x2E0F01A9), SH_UNT_PERV_46  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC14_CPPM_CMEDATA_OR                               ,
+       RULL(0x2E0F01AA), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_CPPM_CMEDATA                                  ,
+       RULL(0x2F0F01A8), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x2F0F01A9), SH_UNT_PERV_47  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC15_CPPM_CMEDATA_OR                               ,
+       RULL(0x2F0F01AA), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_CPPM_CMEDATA                                  ,
+       RULL(0x300F01A8), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x300F01A9), SH_UNT_PERV_48  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC16_CPPM_CMEDATA_OR                               ,
+       RULL(0x300F01AA), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_CPPM_CMEDATA                                  ,
+       RULL(0x310F01A8), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x310F01A9), SH_UNT_PERV_49  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC17_CPPM_CMEDATA_OR                               ,
+       RULL(0x310F01AA), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_CPPM_CMEDATA                                  ,
+       RULL(0x320F01A8), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x320F01A9), SH_UNT_PERV_50  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC18_CPPM_CMEDATA_OR                               ,
+       RULL(0x320F01AA), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_CPPM_CMEDATA                                  ,
+       RULL(0x330F01A8), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x330F01A9), SH_UNT_PERV_51  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC19_CPPM_CMEDATA_OR                               ,
+       RULL(0x330F01AA), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_CPPM_CMEDATA                                  ,
+       RULL(0x340F01A8), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x340F01A9), SH_UNT_PERV_52  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC20_CPPM_CMEDATA_OR                               ,
+       RULL(0x340F01AA), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_CPPM_CMEDATA                                  ,
+       RULL(0x350F01A8), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x350F01A9), SH_UNT_PERV_53  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC21_CPPM_CMEDATA_OR                               ,
+       RULL(0x350F01AA), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_CPPM_CMEDATA                                  ,
+       RULL(0x360F01A8), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x360F01A9), SH_UNT_PERV_54  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC22_CPPM_CMEDATA_OR                               ,
+       RULL(0x360F01AA), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_CPPM_CMEDATA                                  ,
+       RULL(0x370F01A8), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_CMEDATA_CLEAR                            ,
+       RULL(0x370F01A9), SH_UNT_PERV_55  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC23_CPPM_CMEDATA_OR                               ,
+       RULL(0x370F01AA), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EC00_CPPM_CMEDB0                                   ,
+       RULL(0x200F0190), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x200F0191), SH_UNT_PERV_32  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC00_CPPM_CMEDB0_OR                                ,
+       RULL(0x200F0192), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_CPPM_CMEDB0                                   ,
+       RULL(0x210F0190), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x210F0191), SH_UNT_PERV_33  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC01_CPPM_CMEDB0_OR                                ,
+       RULL(0x210F0192), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_CPPM_CMEDB0                                   ,
+       RULL(0x220F0190), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x220F0191), SH_UNT_PERV_34  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC02_CPPM_CMEDB0_OR                                ,
+       RULL(0x220F0192), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_CPPM_CMEDB0                                   ,
+       RULL(0x230F0190), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x230F0191), SH_UNT_PERV_35  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC03_CPPM_CMEDB0_OR                                ,
+       RULL(0x230F0192), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_CPPM_CMEDB0                                   ,
+       RULL(0x240F0190), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x240F0191), SH_UNT_PERV_36  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC04_CPPM_CMEDB0_OR                                ,
+       RULL(0x240F0192), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_CPPM_CMEDB0                                   ,
+       RULL(0x250F0190), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x250F0191), SH_UNT_PERV_37  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC05_CPPM_CMEDB0_OR                                ,
+       RULL(0x250F0192), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_CPPM_CMEDB0                                   ,
+       RULL(0x260F0190), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x260F0191), SH_UNT_PERV_38  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC06_CPPM_CMEDB0_OR                                ,
+       RULL(0x260F0192), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_CPPM_CMEDB0                                   ,
+       RULL(0x270F0190), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x270F0191), SH_UNT_PERV_39  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC07_CPPM_CMEDB0_OR                                ,
+       RULL(0x270F0192), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_CPPM_CMEDB0                                   ,
+       RULL(0x280F0190), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x280F0191), SH_UNT_PERV_40  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC08_CPPM_CMEDB0_OR                                ,
+       RULL(0x280F0192), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_CPPM_CMEDB0                                   ,
+       RULL(0x290F0190), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x290F0191), SH_UNT_PERV_41  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC09_CPPM_CMEDB0_OR                                ,
+       RULL(0x290F0192), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_CPPM_CMEDB0                                   ,
+       RULL(0x2A0F0190), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x2A0F0191), SH_UNT_PERV_42  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC10_CPPM_CMEDB0_OR                                ,
+       RULL(0x2A0F0192), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_CPPM_CMEDB0                                   ,
+       RULL(0x2B0F0190), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x2B0F0191), SH_UNT_PERV_43  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC11_CPPM_CMEDB0_OR                                ,
+       RULL(0x2B0F0192), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_CPPM_CMEDB0                                   ,
+       RULL(0x2C0F0190), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x2C0F0191), SH_UNT_PERV_44  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC12_CPPM_CMEDB0_OR                                ,
+       RULL(0x2C0F0192), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_CPPM_CMEDB0                                   ,
+       RULL(0x2D0F0190), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x2D0F0191), SH_UNT_PERV_45  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC13_CPPM_CMEDB0_OR                                ,
+       RULL(0x2D0F0192), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_CPPM_CMEDB0                                   ,
+       RULL(0x2E0F0190), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x2E0F0191), SH_UNT_PERV_46  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC14_CPPM_CMEDB0_OR                                ,
+       RULL(0x2E0F0192), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_CPPM_CMEDB0                                   ,
+       RULL(0x2F0F0190), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x2F0F0191), SH_UNT_PERV_47  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC15_CPPM_CMEDB0_OR                                ,
+       RULL(0x2F0F0192), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_CPPM_CMEDB0                                   ,
+       RULL(0x300F0190), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x300F0191), SH_UNT_PERV_48  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC16_CPPM_CMEDB0_OR                                ,
+       RULL(0x300F0192), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_CPPM_CMEDB0                                   ,
+       RULL(0x310F0190), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x310F0191), SH_UNT_PERV_49  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC17_CPPM_CMEDB0_OR                                ,
+       RULL(0x310F0192), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_CPPM_CMEDB0                                   ,
+       RULL(0x320F0190), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x320F0191), SH_UNT_PERV_50  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC18_CPPM_CMEDB0_OR                                ,
+       RULL(0x320F0192), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_CPPM_CMEDB0                                   ,
+       RULL(0x330F0190), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x330F0191), SH_UNT_PERV_51  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC19_CPPM_CMEDB0_OR                                ,
+       RULL(0x330F0192), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_CPPM_CMEDB0                                   ,
+       RULL(0x340F0190), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x340F0191), SH_UNT_PERV_52  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC20_CPPM_CMEDB0_OR                                ,
+       RULL(0x340F0192), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_CPPM_CMEDB0                                   ,
+       RULL(0x350F0190), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x350F0191), SH_UNT_PERV_53  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC21_CPPM_CMEDB0_OR                                ,
+       RULL(0x350F0192), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_CPPM_CMEDB0                                   ,
+       RULL(0x360F0190), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x360F0191), SH_UNT_PERV_54  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC22_CPPM_CMEDB0_OR                                ,
+       RULL(0x360F0192), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_CPPM_CMEDB0                                   ,
+       RULL(0x370F0190), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_CMEDB0_CLEAR                             ,
+       RULL(0x370F0191), SH_UNT_PERV_55  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC23_CPPM_CMEDB0_OR                                ,
+       RULL(0x370F0192), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EC00_CPPM_CMEDB1                                   ,
+       RULL(0x200F0194), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x200F0195), SH_UNT_PERV_32  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC00_CPPM_CMEDB1_OR                                ,
+       RULL(0x200F0196), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_CPPM_CMEDB1                                   ,
+       RULL(0x210F0194), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x210F0195), SH_UNT_PERV_33  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC01_CPPM_CMEDB1_OR                                ,
+       RULL(0x210F0196), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_CPPM_CMEDB1                                   ,
+       RULL(0x220F0194), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x220F0195), SH_UNT_PERV_34  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC02_CPPM_CMEDB1_OR                                ,
+       RULL(0x220F0196), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_CPPM_CMEDB1                                   ,
+       RULL(0x230F0194), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x230F0195), SH_UNT_PERV_35  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC03_CPPM_CMEDB1_OR                                ,
+       RULL(0x230F0196), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_CPPM_CMEDB1                                   ,
+       RULL(0x240F0194), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x240F0195), SH_UNT_PERV_36  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC04_CPPM_CMEDB1_OR                                ,
+       RULL(0x240F0196), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_CPPM_CMEDB1                                   ,
+       RULL(0x250F0194), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x250F0195), SH_UNT_PERV_37  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC05_CPPM_CMEDB1_OR                                ,
+       RULL(0x250F0196), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_CPPM_CMEDB1                                   ,
+       RULL(0x260F0194), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x260F0195), SH_UNT_PERV_38  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC06_CPPM_CMEDB1_OR                                ,
+       RULL(0x260F0196), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_CPPM_CMEDB1                                   ,
+       RULL(0x270F0194), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x270F0195), SH_UNT_PERV_39  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC07_CPPM_CMEDB1_OR                                ,
+       RULL(0x270F0196), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_CPPM_CMEDB1                                   ,
+       RULL(0x280F0194), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x280F0195), SH_UNT_PERV_40  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC08_CPPM_CMEDB1_OR                                ,
+       RULL(0x280F0196), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_CPPM_CMEDB1                                   ,
+       RULL(0x290F0194), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x290F0195), SH_UNT_PERV_41  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC09_CPPM_CMEDB1_OR                                ,
+       RULL(0x290F0196), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_CPPM_CMEDB1                                   ,
+       RULL(0x2A0F0194), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x2A0F0195), SH_UNT_PERV_42  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC10_CPPM_CMEDB1_OR                                ,
+       RULL(0x2A0F0196), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_CPPM_CMEDB1                                   ,
+       RULL(0x2B0F0194), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x2B0F0195), SH_UNT_PERV_43  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC11_CPPM_CMEDB1_OR                                ,
+       RULL(0x2B0F0196), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_CPPM_CMEDB1                                   ,
+       RULL(0x2C0F0194), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x2C0F0195), SH_UNT_PERV_44  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC12_CPPM_CMEDB1_OR                                ,
+       RULL(0x2C0F0196), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_CPPM_CMEDB1                                   ,
+       RULL(0x2D0F0194), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x2D0F0195), SH_UNT_PERV_45  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC13_CPPM_CMEDB1_OR                                ,
+       RULL(0x2D0F0196), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_CPPM_CMEDB1                                   ,
+       RULL(0x2E0F0194), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x2E0F0195), SH_UNT_PERV_46  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC14_CPPM_CMEDB1_OR                                ,
+       RULL(0x2E0F0196), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_CPPM_CMEDB1                                   ,
+       RULL(0x2F0F0194), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x2F0F0195), SH_UNT_PERV_47  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC15_CPPM_CMEDB1_OR                                ,
+       RULL(0x2F0F0196), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_CPPM_CMEDB1                                   ,
+       RULL(0x300F0194), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x300F0195), SH_UNT_PERV_48  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC16_CPPM_CMEDB1_OR                                ,
+       RULL(0x300F0196), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_CPPM_CMEDB1                                   ,
+       RULL(0x310F0194), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x310F0195), SH_UNT_PERV_49  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC17_CPPM_CMEDB1_OR                                ,
+       RULL(0x310F0196), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_CPPM_CMEDB1                                   ,
+       RULL(0x320F0194), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x320F0195), SH_UNT_PERV_50  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC18_CPPM_CMEDB1_OR                                ,
+       RULL(0x320F0196), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_CPPM_CMEDB1                                   ,
+       RULL(0x330F0194), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x330F0195), SH_UNT_PERV_51  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC19_CPPM_CMEDB1_OR                                ,
+       RULL(0x330F0196), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_CPPM_CMEDB1                                   ,
+       RULL(0x340F0194), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x340F0195), SH_UNT_PERV_52  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC20_CPPM_CMEDB1_OR                                ,
+       RULL(0x340F0196), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_CPPM_CMEDB1                                   ,
+       RULL(0x350F0194), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x350F0195), SH_UNT_PERV_53  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC21_CPPM_CMEDB1_OR                                ,
+       RULL(0x350F0196), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_CPPM_CMEDB1                                   ,
+       RULL(0x360F0194), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x360F0195), SH_UNT_PERV_54  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC22_CPPM_CMEDB1_OR                                ,
+       RULL(0x360F0196), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_CPPM_CMEDB1                                   ,
+       RULL(0x370F0194), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_CMEDB1_CLEAR                             ,
+       RULL(0x370F0195), SH_UNT_PERV_55  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC23_CPPM_CMEDB1_OR                                ,
+       RULL(0x370F0196), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EC00_CPPM_CMEDB2                                   ,
+       RULL(0x200F0198), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x200F0199), SH_UNT_PERV_32  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC00_CPPM_CMEDB2_OR                                ,
+       RULL(0x200F019A), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_CPPM_CMEDB2                                   ,
+       RULL(0x210F0198), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x210F0199), SH_UNT_PERV_33  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC01_CPPM_CMEDB2_OR                                ,
+       RULL(0x210F019A), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_CPPM_CMEDB2                                   ,
+       RULL(0x220F0198), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x220F0199), SH_UNT_PERV_34  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC02_CPPM_CMEDB2_OR                                ,
+       RULL(0x220F019A), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_CPPM_CMEDB2                                   ,
+       RULL(0x230F0198), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x230F0199), SH_UNT_PERV_35  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC03_CPPM_CMEDB2_OR                                ,
+       RULL(0x230F019A), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_CPPM_CMEDB2                                   ,
+       RULL(0x240F0198), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x240F0199), SH_UNT_PERV_36  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC04_CPPM_CMEDB2_OR                                ,
+       RULL(0x240F019A), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_CPPM_CMEDB2                                   ,
+       RULL(0x250F0198), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x250F0199), SH_UNT_PERV_37  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC05_CPPM_CMEDB2_OR                                ,
+       RULL(0x250F019A), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_CPPM_CMEDB2                                   ,
+       RULL(0x260F0198), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x260F0199), SH_UNT_PERV_38  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC06_CPPM_CMEDB2_OR                                ,
+       RULL(0x260F019A), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_CPPM_CMEDB2                                   ,
+       RULL(0x270F0198), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x270F0199), SH_UNT_PERV_39  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC07_CPPM_CMEDB2_OR                                ,
+       RULL(0x270F019A), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_CPPM_CMEDB2                                   ,
+       RULL(0x280F0198), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x280F0199), SH_UNT_PERV_40  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC08_CPPM_CMEDB2_OR                                ,
+       RULL(0x280F019A), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_CPPM_CMEDB2                                   ,
+       RULL(0x290F0198), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x290F0199), SH_UNT_PERV_41  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC09_CPPM_CMEDB2_OR                                ,
+       RULL(0x290F019A), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_CPPM_CMEDB2                                   ,
+       RULL(0x2A0F0198), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x2A0F0199), SH_UNT_PERV_42  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC10_CPPM_CMEDB2_OR                                ,
+       RULL(0x2A0F019A), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_CPPM_CMEDB2                                   ,
+       RULL(0x2B0F0198), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x2B0F0199), SH_UNT_PERV_43  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC11_CPPM_CMEDB2_OR                                ,
+       RULL(0x2B0F019A), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_CPPM_CMEDB2                                   ,
+       RULL(0x2C0F0198), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x2C0F0199), SH_UNT_PERV_44  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC12_CPPM_CMEDB2_OR                                ,
+       RULL(0x2C0F019A), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_CPPM_CMEDB2                                   ,
+       RULL(0x2D0F0198), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x2D0F0199), SH_UNT_PERV_45  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC13_CPPM_CMEDB2_OR                                ,
+       RULL(0x2D0F019A), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_CPPM_CMEDB2                                   ,
+       RULL(0x2E0F0198), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x2E0F0199), SH_UNT_PERV_46  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC14_CPPM_CMEDB2_OR                                ,
+       RULL(0x2E0F019A), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_CPPM_CMEDB2                                   ,
+       RULL(0x2F0F0198), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x2F0F0199), SH_UNT_PERV_47  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC15_CPPM_CMEDB2_OR                                ,
+       RULL(0x2F0F019A), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_CPPM_CMEDB2                                   ,
+       RULL(0x300F0198), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x300F0199), SH_UNT_PERV_48  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC16_CPPM_CMEDB2_OR                                ,
+       RULL(0x300F019A), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_CPPM_CMEDB2                                   ,
+       RULL(0x310F0198), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x310F0199), SH_UNT_PERV_49  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC17_CPPM_CMEDB2_OR                                ,
+       RULL(0x310F019A), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_CPPM_CMEDB2                                   ,
+       RULL(0x320F0198), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x320F0199), SH_UNT_PERV_50  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC18_CPPM_CMEDB2_OR                                ,
+       RULL(0x320F019A), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_CPPM_CMEDB2                                   ,
+       RULL(0x330F0198), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x330F0199), SH_UNT_PERV_51  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC19_CPPM_CMEDB2_OR                                ,
+       RULL(0x330F019A), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_CPPM_CMEDB2                                   ,
+       RULL(0x340F0198), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x340F0199), SH_UNT_PERV_52  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC20_CPPM_CMEDB2_OR                                ,
+       RULL(0x340F019A), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_CPPM_CMEDB2                                   ,
+       RULL(0x350F0198), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x350F0199), SH_UNT_PERV_53  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC21_CPPM_CMEDB2_OR                                ,
+       RULL(0x350F019A), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_CPPM_CMEDB2                                   ,
+       RULL(0x360F0198), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x360F0199), SH_UNT_PERV_54  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC22_CPPM_CMEDB2_OR                                ,
+       RULL(0x360F019A), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_CPPM_CMEDB2                                   ,
+       RULL(0x370F0198), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_CMEDB2_CLEAR                             ,
+       RULL(0x370F0199), SH_UNT_PERV_55  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC23_CPPM_CMEDB2_OR                                ,
+       RULL(0x370F019A), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EC00_CPPM_CMEDB3                                   ,
+       RULL(0x200F019C), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x200F019D), SH_UNT_PERV_32  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC00_CPPM_CMEDB3_OR                                ,
+       RULL(0x200F019E), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_CPPM_CMEDB3                                   ,
+       RULL(0x210F019C), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x210F019D), SH_UNT_PERV_33  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC01_CPPM_CMEDB3_OR                                ,
+       RULL(0x210F019E), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_CPPM_CMEDB3                                   ,
+       RULL(0x220F019C), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x220F019D), SH_UNT_PERV_34  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC02_CPPM_CMEDB3_OR                                ,
+       RULL(0x220F019E), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_CPPM_CMEDB3                                   ,
+       RULL(0x230F019C), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x230F019D), SH_UNT_PERV_35  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC03_CPPM_CMEDB3_OR                                ,
+       RULL(0x230F019E), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_CPPM_CMEDB3                                   ,
+       RULL(0x240F019C), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x240F019D), SH_UNT_PERV_36  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC04_CPPM_CMEDB3_OR                                ,
+       RULL(0x240F019E), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_CPPM_CMEDB3                                   ,
+       RULL(0x250F019C), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x250F019D), SH_UNT_PERV_37  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC05_CPPM_CMEDB3_OR                                ,
+       RULL(0x250F019E), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_CPPM_CMEDB3                                   ,
+       RULL(0x260F019C), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x260F019D), SH_UNT_PERV_38  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC06_CPPM_CMEDB3_OR                                ,
+       RULL(0x260F019E), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_CPPM_CMEDB3                                   ,
+       RULL(0x270F019C), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x270F019D), SH_UNT_PERV_39  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC07_CPPM_CMEDB3_OR                                ,
+       RULL(0x270F019E), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_CPPM_CMEDB3                                   ,
+       RULL(0x280F019C), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x280F019D), SH_UNT_PERV_40  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC08_CPPM_CMEDB3_OR                                ,
+       RULL(0x280F019E), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_CPPM_CMEDB3                                   ,
+       RULL(0x290F019C), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x290F019D), SH_UNT_PERV_41  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC09_CPPM_CMEDB3_OR                                ,
+       RULL(0x290F019E), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_CPPM_CMEDB3                                   ,
+       RULL(0x2A0F019C), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x2A0F019D), SH_UNT_PERV_42  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC10_CPPM_CMEDB3_OR                                ,
+       RULL(0x2A0F019E), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_CPPM_CMEDB3                                   ,
+       RULL(0x2B0F019C), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x2B0F019D), SH_UNT_PERV_43  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC11_CPPM_CMEDB3_OR                                ,
+       RULL(0x2B0F019E), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_CPPM_CMEDB3                                   ,
+       RULL(0x2C0F019C), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x2C0F019D), SH_UNT_PERV_44  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC12_CPPM_CMEDB3_OR                                ,
+       RULL(0x2C0F019E), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_CPPM_CMEDB3                                   ,
+       RULL(0x2D0F019C), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x2D0F019D), SH_UNT_PERV_45  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC13_CPPM_CMEDB3_OR                                ,
+       RULL(0x2D0F019E), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_CPPM_CMEDB3                                   ,
+       RULL(0x2E0F019C), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x2E0F019D), SH_UNT_PERV_46  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC14_CPPM_CMEDB3_OR                                ,
+       RULL(0x2E0F019E), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_CPPM_CMEDB3                                   ,
+       RULL(0x2F0F019C), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x2F0F019D), SH_UNT_PERV_47  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC15_CPPM_CMEDB3_OR                                ,
+       RULL(0x2F0F019E), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_CPPM_CMEDB3                                   ,
+       RULL(0x300F019C), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x300F019D), SH_UNT_PERV_48  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC16_CPPM_CMEDB3_OR                                ,
+       RULL(0x300F019E), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_CPPM_CMEDB3                                   ,
+       RULL(0x310F019C), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x310F019D), SH_UNT_PERV_49  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC17_CPPM_CMEDB3_OR                                ,
+       RULL(0x310F019E), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_CPPM_CMEDB3                                   ,
+       RULL(0x320F019C), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x320F019D), SH_UNT_PERV_50  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC18_CPPM_CMEDB3_OR                                ,
+       RULL(0x320F019E), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_CPPM_CMEDB3                                   ,
+       RULL(0x330F019C), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x330F019D), SH_UNT_PERV_51  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC19_CPPM_CMEDB3_OR                                ,
+       RULL(0x330F019E), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_CPPM_CMEDB3                                   ,
+       RULL(0x340F019C), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x340F019D), SH_UNT_PERV_52  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC20_CPPM_CMEDB3_OR                                ,
+       RULL(0x340F019E), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_CPPM_CMEDB3                                   ,
+       RULL(0x350F019C), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x350F019D), SH_UNT_PERV_53  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC21_CPPM_CMEDB3_OR                                ,
+       RULL(0x350F019E), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_CPPM_CMEDB3                                   ,
+       RULL(0x360F019C), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x360F019D), SH_UNT_PERV_54  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC22_CPPM_CMEDB3_OR                                ,
+       RULL(0x360F019E), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_CPPM_CMEDB3                                   ,
+       RULL(0x370F019C), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_CMEDB3_CLEAR                             ,
+       RULL(0x370F019D), SH_UNT_PERV_55  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC23_CPPM_CMEDB3_OR                                ,
+       RULL(0x370F019E), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EC00_CPPM_CMEMSG                                   ,
+       RULL(0x200F01AB), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_CMEMSG                                   ,
+       RULL(0x210F01AB), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_CMEMSG                                   ,
+       RULL(0x220F01AB), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_CMEMSG                                   ,
+       RULL(0x230F01AB), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_CMEMSG                                   ,
+       RULL(0x240F01AB), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_CMEMSG                                   ,
+       RULL(0x250F01AB), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_CMEMSG                                   ,
+       RULL(0x260F01AB), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_CMEMSG                                   ,
+       RULL(0x270F01AB), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_CMEMSG                                   ,
+       RULL(0x280F01AB), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_CMEMSG                                   ,
+       RULL(0x290F01AB), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_CMEMSG                                   ,
+       RULL(0x2A0F01AB), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_CMEMSG                                   ,
+       RULL(0x2B0F01AB), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_CMEMSG                                   ,
+       RULL(0x2C0F01AB), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_CMEMSG                                   ,
+       RULL(0x2D0F01AB), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_CMEMSG                                   ,
+       RULL(0x2E0F01AB), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_CMEMSG                                   ,
+       RULL(0x2F0F01AB), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_CMEMSG                                   ,
+       RULL(0x300F01AB), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_CMEMSG                                   ,
+       RULL(0x310F01AB), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_CMEMSG                                   ,
+       RULL(0x320F01AB), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_CMEMSG                                   ,
+       RULL(0x330F01AB), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_CMEMSG                                   ,
+       RULL(0x340F01AB), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_CMEMSG                                   ,
+       RULL(0x350F01AB), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_CMEMSG                                   ,
+       RULL(0x360F01AB), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_CMEMSG                                   ,
+       RULL(0x370F01AB), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EC00_CPPM_CPMMR                                    ,
+       RULL(0x200F0106), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x200F0107), SH_UNT_PERV_32  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC00_CPPM_CPMMR_OR                                 ,
+       RULL(0x200F0108), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_CPPM_CPMMR                                    ,
+       RULL(0x210F0106), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x210F0107), SH_UNT_PERV_33  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC01_CPPM_CPMMR_OR                                 ,
+       RULL(0x210F0108), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_CPPM_CPMMR                                    ,
+       RULL(0x220F0106), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x220F0107), SH_UNT_PERV_34  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC02_CPPM_CPMMR_OR                                 ,
+       RULL(0x220F0108), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_CPPM_CPMMR                                    ,
+       RULL(0x230F0106), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x230F0107), SH_UNT_PERV_35  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC03_CPPM_CPMMR_OR                                 ,
+       RULL(0x230F0108), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_CPPM_CPMMR                                    ,
+       RULL(0x240F0106), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x240F0107), SH_UNT_PERV_36  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC04_CPPM_CPMMR_OR                                 ,
+       RULL(0x240F0108), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_CPPM_CPMMR                                    ,
+       RULL(0x250F0106), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x250F0107), SH_UNT_PERV_37  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC05_CPPM_CPMMR_OR                                 ,
+       RULL(0x250F0108), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_CPPM_CPMMR                                    ,
+       RULL(0x260F0106), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x260F0107), SH_UNT_PERV_38  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC06_CPPM_CPMMR_OR                                 ,
+       RULL(0x260F0108), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_CPPM_CPMMR                                    ,
+       RULL(0x270F0106), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x270F0107), SH_UNT_PERV_39  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC07_CPPM_CPMMR_OR                                 ,
+       RULL(0x270F0108), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_CPPM_CPMMR                                    ,
+       RULL(0x280F0106), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x280F0107), SH_UNT_PERV_40  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC08_CPPM_CPMMR_OR                                 ,
+       RULL(0x280F0108), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_CPPM_CPMMR                                    ,
+       RULL(0x290F0106), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x290F0107), SH_UNT_PERV_41  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC09_CPPM_CPMMR_OR                                 ,
+       RULL(0x290F0108), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_CPPM_CPMMR                                    ,
+       RULL(0x2A0F0106), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x2A0F0107), SH_UNT_PERV_42  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC10_CPPM_CPMMR_OR                                 ,
+       RULL(0x2A0F0108), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_CPPM_CPMMR                                    ,
+       RULL(0x2B0F0106), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x2B0F0107), SH_UNT_PERV_43  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC11_CPPM_CPMMR_OR                                 ,
+       RULL(0x2B0F0108), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_CPPM_CPMMR                                    ,
+       RULL(0x2C0F0106), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x2C0F0107), SH_UNT_PERV_44  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC12_CPPM_CPMMR_OR                                 ,
+       RULL(0x2C0F0108), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_CPPM_CPMMR                                    ,
+       RULL(0x2D0F0106), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x2D0F0107), SH_UNT_PERV_45  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC13_CPPM_CPMMR_OR                                 ,
+       RULL(0x2D0F0108), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_CPPM_CPMMR                                    ,
+       RULL(0x2E0F0106), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x2E0F0107), SH_UNT_PERV_46  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC14_CPPM_CPMMR_OR                                 ,
+       RULL(0x2E0F0108), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_CPPM_CPMMR                                    ,
+       RULL(0x2F0F0106), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x2F0F0107), SH_UNT_PERV_47  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC15_CPPM_CPMMR_OR                                 ,
+       RULL(0x2F0F0108), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_CPPM_CPMMR                                    ,
+       RULL(0x300F0106), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x300F0107), SH_UNT_PERV_48  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC16_CPPM_CPMMR_OR                                 ,
+       RULL(0x300F0108), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_CPPM_CPMMR                                    ,
+       RULL(0x310F0106), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x310F0107), SH_UNT_PERV_49  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC17_CPPM_CPMMR_OR                                 ,
+       RULL(0x310F0108), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_CPPM_CPMMR                                    ,
+       RULL(0x320F0106), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x320F0107), SH_UNT_PERV_50  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC18_CPPM_CPMMR_OR                                 ,
+       RULL(0x320F0108), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_CPPM_CPMMR                                    ,
+       RULL(0x330F0106), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x330F0107), SH_UNT_PERV_51  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC19_CPPM_CPMMR_OR                                 ,
+       RULL(0x330F0108), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_CPPM_CPMMR                                    ,
+       RULL(0x340F0106), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x340F0107), SH_UNT_PERV_52  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC20_CPPM_CPMMR_OR                                 ,
+       RULL(0x340F0108), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_CPPM_CPMMR                                    ,
+       RULL(0x350F0106), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x350F0107), SH_UNT_PERV_53  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC21_CPPM_CPMMR_OR                                 ,
+       RULL(0x350F0108), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_CPPM_CPMMR                                    ,
+       RULL(0x360F0106), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x360F0107), SH_UNT_PERV_54  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC22_CPPM_CPMMR_OR                                 ,
+       RULL(0x360F0108), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_CPPM_CPMMR                                    ,
+       RULL(0x370F0106), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_CPMMR_CLEAR                              ,
+       RULL(0x370F0107), SH_UNT_PERV_55  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC23_CPPM_CPMMR_OR                                 ,
+       RULL(0x370F0108), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EC00_CPPM_CSAR                                     ,
+       RULL(0x200F0138), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPPM_CSAR_CLEAR                               ,
+       RULL(0x200F0139), SH_UNT_PERV_32  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC00_CPPM_CSAR_OR                                  ,
+       RULL(0x200F013A), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_CPPM_CSAR                                     ,
+       RULL(0x210F0138), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_CSAR_CLEAR                               ,
+       RULL(0x210F0139), SH_UNT_PERV_33  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC01_CPPM_CSAR_OR                                  ,
+       RULL(0x210F013A), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_CPPM_CSAR                                     ,
+       RULL(0x220F0138), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_CSAR_CLEAR                               ,
+       RULL(0x220F0139), SH_UNT_PERV_34  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC02_CPPM_CSAR_OR                                  ,
+       RULL(0x220F013A), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_CPPM_CSAR                                     ,
+       RULL(0x230F0138), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_CSAR_CLEAR                               ,
+       RULL(0x230F0139), SH_UNT_PERV_35  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC03_CPPM_CSAR_OR                                  ,
+       RULL(0x230F013A), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_CPPM_CSAR                                     ,
+       RULL(0x240F0138), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_CSAR_CLEAR                               ,
+       RULL(0x240F0139), SH_UNT_PERV_36  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC04_CPPM_CSAR_OR                                  ,
+       RULL(0x240F013A), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_CPPM_CSAR                                     ,
+       RULL(0x250F0138), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_CSAR_CLEAR                               ,
+       RULL(0x250F0139), SH_UNT_PERV_37  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC05_CPPM_CSAR_OR                                  ,
+       RULL(0x250F013A), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_CPPM_CSAR                                     ,
+       RULL(0x260F0138), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_CSAR_CLEAR                               ,
+       RULL(0x260F0139), SH_UNT_PERV_38  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC06_CPPM_CSAR_OR                                  ,
+       RULL(0x260F013A), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_CPPM_CSAR                                     ,
+       RULL(0x270F0138), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_CSAR_CLEAR                               ,
+       RULL(0x270F0139), SH_UNT_PERV_39  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC07_CPPM_CSAR_OR                                  ,
+       RULL(0x270F013A), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_CPPM_CSAR                                     ,
+       RULL(0x280F0138), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_CSAR_CLEAR                               ,
+       RULL(0x280F0139), SH_UNT_PERV_40  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC08_CPPM_CSAR_OR                                  ,
+       RULL(0x280F013A), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_CPPM_CSAR                                     ,
+       RULL(0x290F0138), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_CSAR_CLEAR                               ,
+       RULL(0x290F0139), SH_UNT_PERV_41  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC09_CPPM_CSAR_OR                                  ,
+       RULL(0x290F013A), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_CPPM_CSAR                                     ,
+       RULL(0x2A0F0138), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_CSAR_CLEAR                               ,
+       RULL(0x2A0F0139), SH_UNT_PERV_42  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC10_CPPM_CSAR_OR                                  ,
+       RULL(0x2A0F013A), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_CPPM_CSAR                                     ,
+       RULL(0x2B0F0138), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_CSAR_CLEAR                               ,
+       RULL(0x2B0F0139), SH_UNT_PERV_43  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC11_CPPM_CSAR_OR                                  ,
+       RULL(0x2B0F013A), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_CPPM_CSAR                                     ,
+       RULL(0x2C0F0138), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_CSAR_CLEAR                               ,
+       RULL(0x2C0F0139), SH_UNT_PERV_44  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC12_CPPM_CSAR_OR                                  ,
+       RULL(0x2C0F013A), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_CPPM_CSAR                                     ,
+       RULL(0x2D0F0138), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_CSAR_CLEAR                               ,
+       RULL(0x2D0F0139), SH_UNT_PERV_45  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC13_CPPM_CSAR_OR                                  ,
+       RULL(0x2D0F013A), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_CPPM_CSAR                                     ,
+       RULL(0x2E0F0138), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_CSAR_CLEAR                               ,
+       RULL(0x2E0F0139), SH_UNT_PERV_46  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC14_CPPM_CSAR_OR                                  ,
+       RULL(0x2E0F013A), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_CPPM_CSAR                                     ,
+       RULL(0x2F0F0138), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_CSAR_CLEAR                               ,
+       RULL(0x2F0F0139), SH_UNT_PERV_47  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC15_CPPM_CSAR_OR                                  ,
+       RULL(0x2F0F013A), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_CPPM_CSAR                                     ,
+       RULL(0x300F0138), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_CSAR_CLEAR                               ,
+       RULL(0x300F0139), SH_UNT_PERV_48  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC16_CPPM_CSAR_OR                                  ,
+       RULL(0x300F013A), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_CPPM_CSAR                                     ,
+       RULL(0x310F0138), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_CSAR_CLEAR                               ,
+       RULL(0x310F0139), SH_UNT_PERV_49  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC17_CPPM_CSAR_OR                                  ,
+       RULL(0x310F013A), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_CPPM_CSAR                                     ,
+       RULL(0x320F0138), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_CSAR_CLEAR                               ,
+       RULL(0x320F0139), SH_UNT_PERV_50  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC18_CPPM_CSAR_OR                                  ,
+       RULL(0x320F013A), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_CPPM_CSAR                                     ,
+       RULL(0x330F0138), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_CSAR_CLEAR                               ,
+       RULL(0x330F0139), SH_UNT_PERV_51  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC19_CPPM_CSAR_OR                                  ,
+       RULL(0x330F013A), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_CPPM_CSAR                                     ,
+       RULL(0x340F0138), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_CSAR_CLEAR                               ,
+       RULL(0x340F0139), SH_UNT_PERV_52  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC20_CPPM_CSAR_OR                                  ,
+       RULL(0x340F013A), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_CPPM_CSAR                                     ,
+       RULL(0x350F0138), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_CSAR_CLEAR                               ,
+       RULL(0x350F0139), SH_UNT_PERV_53  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC21_CPPM_CSAR_OR                                  ,
+       RULL(0x350F013A), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_CPPM_CSAR                                     ,
+       RULL(0x360F0138), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_CSAR_CLEAR                               ,
+       RULL(0x360F0139), SH_UNT_PERV_54  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC22_CPPM_CSAR_OR                                  ,
+       RULL(0x360F013A), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_CPPM_CSAR                                     ,
+       RULL(0x370F0138), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_CSAR_CLEAR                               ,
+       RULL(0x370F0139), SH_UNT_PERV_55  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC23_CPPM_CSAR_OR                                  ,
+       RULL(0x370F013A), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EC00_CPPM_ERR                                      ,
+       RULL(0x200F0121), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CPPM_ERR                                      ,
+       RULL(0x210F0121), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CPPM_ERR                                      ,
+       RULL(0x220F0121), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CPPM_ERR                                      ,
+       RULL(0x230F0121), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CPPM_ERR                                      ,
+       RULL(0x240F0121), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CPPM_ERR                                      ,
+       RULL(0x250F0121), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CPPM_ERR                                      ,
+       RULL(0x260F0121), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CPPM_ERR                                      ,
+       RULL(0x270F0121), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CPPM_ERR                                      ,
+       RULL(0x280F0121), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CPPM_ERR                                      ,
+       RULL(0x290F0121), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CPPM_ERR                                      ,
+       RULL(0x2A0F0121), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CPPM_ERR                                      ,
+       RULL(0x2B0F0121), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CPPM_ERR                                      ,
+       RULL(0x2C0F0121), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CPPM_ERR                                      ,
+       RULL(0x2D0F0121), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CPPM_ERR                                      ,
+       RULL(0x2E0F0121), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CPPM_ERR                                      ,
+       RULL(0x2F0F0121), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CPPM_ERR                                      ,
+       RULL(0x300F0121), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CPPM_ERR                                      ,
+       RULL(0x310F0121), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CPPM_ERR                                      ,
+       RULL(0x320F0121), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CPPM_ERR                                      ,
+       RULL(0x330F0121), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CPPM_ERR                                      ,
+       RULL(0x340F0121), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CPPM_ERR                                      ,
+       RULL(0x350F0121), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CPPM_ERR                                      ,
+       RULL(0x360F0121), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CPPM_ERR                                      ,
+       RULL(0x370F0121), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_EC00_CPPM_ERRMSK                                   ,
+       RULL(0x200F0122), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_ERRMSK                                   ,
+       RULL(0x210F0122), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_ERRMSK                                   ,
+       RULL(0x220F0122), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_ERRMSK                                   ,
+       RULL(0x230F0122), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_ERRMSK                                   ,
+       RULL(0x240F0122), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_ERRMSK                                   ,
+       RULL(0x250F0122), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_ERRMSK                                   ,
+       RULL(0x260F0122), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_ERRMSK                                   ,
+       RULL(0x270F0122), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_ERRMSK                                   ,
+       RULL(0x280F0122), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_ERRMSK                                   ,
+       RULL(0x290F0122), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_ERRMSK                                   ,
+       RULL(0x2A0F0122), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_ERRMSK                                   ,
+       RULL(0x2B0F0122), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_ERRMSK                                   ,
+       RULL(0x2C0F0122), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_ERRMSK                                   ,
+       RULL(0x2D0F0122), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_ERRMSK                                   ,
+       RULL(0x2E0F0122), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_ERRMSK                                   ,
+       RULL(0x2F0F0122), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_ERRMSK                                   ,
+       RULL(0x300F0122), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_ERRMSK                                   ,
+       RULL(0x310F0122), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_ERRMSK                                   ,
+       RULL(0x320F0122), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_ERRMSK                                   ,
+       RULL(0x330F0122), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_ERRMSK                                   ,
+       RULL(0x340F0122), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_ERRMSK                                   ,
+       RULL(0x350F0122), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_ERRMSK                                   ,
+       RULL(0x360F0122), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_ERRMSK                                   ,
+       RULL(0x370F0122), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EC00_CPPM_IPPMCMD                                  ,
+       RULL(0x200F01C0), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_IPPMCMD                                  ,
+       RULL(0x210F01C0), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_IPPMCMD                                  ,
+       RULL(0x220F01C0), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_IPPMCMD                                  ,
+       RULL(0x230F01C0), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_IPPMCMD                                  ,
+       RULL(0x240F01C0), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_IPPMCMD                                  ,
+       RULL(0x250F01C0), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_IPPMCMD                                  ,
+       RULL(0x260F01C0), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_IPPMCMD                                  ,
+       RULL(0x270F01C0), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_IPPMCMD                                  ,
+       RULL(0x280F01C0), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_IPPMCMD                                  ,
+       RULL(0x290F01C0), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_IPPMCMD                                  ,
+       RULL(0x2A0F01C0), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_IPPMCMD                                  ,
+       RULL(0x2B0F01C0), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_IPPMCMD                                  ,
+       RULL(0x2C0F01C0), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_IPPMCMD                                  ,
+       RULL(0x2D0F01C0), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_IPPMCMD                                  ,
+       RULL(0x2E0F01C0), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_IPPMCMD                                  ,
+       RULL(0x2F0F01C0), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_IPPMCMD                                  ,
+       RULL(0x300F01C0), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_IPPMCMD                                  ,
+       RULL(0x310F01C0), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_IPPMCMD                                  ,
+       RULL(0x320F01C0), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_IPPMCMD                                  ,
+       RULL(0x330F01C0), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_IPPMCMD                                  ,
+       RULL(0x340F01C0), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_IPPMCMD                                  ,
+       RULL(0x350F01C0), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_IPPMCMD                                  ,
+       RULL(0x360F01C0), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_IPPMCMD                                  ,
+       RULL(0x370F01C0), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EC00_CPPM_IPPMRDATA                                ,
+       RULL(0x200F01C3), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_IPPMRDATA                                ,
+       RULL(0x210F01C3), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_IPPMRDATA                                ,
+       RULL(0x220F01C3), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_IPPMRDATA                                ,
+       RULL(0x230F01C3), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_IPPMRDATA                                ,
+       RULL(0x240F01C3), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_IPPMRDATA                                ,
+       RULL(0x250F01C3), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_IPPMRDATA                                ,
+       RULL(0x260F01C3), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_IPPMRDATA                                ,
+       RULL(0x270F01C3), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_IPPMRDATA                                ,
+       RULL(0x280F01C3), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_IPPMRDATA                                ,
+       RULL(0x290F01C3), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_IPPMRDATA                                ,
+       RULL(0x2A0F01C3), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_IPPMRDATA                                ,
+       RULL(0x2B0F01C3), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_IPPMRDATA                                ,
+       RULL(0x2C0F01C3), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_IPPMRDATA                                ,
+       RULL(0x2D0F01C3), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_IPPMRDATA                                ,
+       RULL(0x2E0F01C3), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_IPPMRDATA                                ,
+       RULL(0x2F0F01C3), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_IPPMRDATA                                ,
+       RULL(0x300F01C3), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_IPPMRDATA                                ,
+       RULL(0x310F01C3), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_IPPMRDATA                                ,
+       RULL(0x320F01C3), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_IPPMRDATA                                ,
+       RULL(0x330F01C3), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_IPPMRDATA                                ,
+       RULL(0x340F01C3), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_IPPMRDATA                                ,
+       RULL(0x350F01C3), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_IPPMRDATA                                ,
+       RULL(0x360F01C3), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_IPPMRDATA                                ,
+       RULL(0x370F01C3), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EC00_CPPM_IPPMSTAT                                 ,
+       RULL(0x200F01C1), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_CPPM_IPPMSTAT                                 ,
+       RULL(0x210F01C1), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_CPPM_IPPMSTAT                                 ,
+       RULL(0x220F01C1), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_CPPM_IPPMSTAT                                 ,
+       RULL(0x230F01C1), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_CPPM_IPPMSTAT                                 ,
+       RULL(0x240F01C1), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_CPPM_IPPMSTAT                                 ,
+       RULL(0x250F01C1), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_CPPM_IPPMSTAT                                 ,
+       RULL(0x260F01C1), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_CPPM_IPPMSTAT                                 ,
+       RULL(0x270F01C1), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_CPPM_IPPMSTAT                                 ,
+       RULL(0x280F01C1), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_CPPM_IPPMSTAT                                 ,
+       RULL(0x290F01C1), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_CPPM_IPPMSTAT                                 ,
+       RULL(0x2A0F01C1), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_CPPM_IPPMSTAT                                 ,
+       RULL(0x2B0F01C1), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_CPPM_IPPMSTAT                                 ,
+       RULL(0x2C0F01C1), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_CPPM_IPPMSTAT                                 ,
+       RULL(0x2D0F01C1), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_CPPM_IPPMSTAT                                 ,
+       RULL(0x2E0F01C1), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_CPPM_IPPMSTAT                                 ,
+       RULL(0x2F0F01C1), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_CPPM_IPPMSTAT                                 ,
+       RULL(0x300F01C1), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_CPPM_IPPMSTAT                                 ,
+       RULL(0x310F01C1), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_CPPM_IPPMSTAT                                 ,
+       RULL(0x320F01C1), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_CPPM_IPPMSTAT                                 ,
+       RULL(0x330F01C1), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_CPPM_IPPMSTAT                                 ,
+       RULL(0x340F01C1), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_CPPM_IPPMSTAT                                 ,
+       RULL(0x350F01C1), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_CPPM_IPPMSTAT                                 ,
+       RULL(0x360F01C1), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_CPPM_IPPMSTAT                                 ,
+       RULL(0x370F01C1), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_EC00_CPPM_IPPMWDATA                                ,
+       RULL(0x200F01C2), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_IPPMWDATA                                ,
+       RULL(0x210F01C2), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_IPPMWDATA                                ,
+       RULL(0x220F01C2), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_IPPMWDATA                                ,
+       RULL(0x230F01C2), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_IPPMWDATA                                ,
+       RULL(0x240F01C2), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_IPPMWDATA                                ,
+       RULL(0x250F01C2), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_IPPMWDATA                                ,
+       RULL(0x260F01C2), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_IPPMWDATA                                ,
+       RULL(0x270F01C2), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_IPPMWDATA                                ,
+       RULL(0x280F01C2), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_IPPMWDATA                                ,
+       RULL(0x290F01C2), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_IPPMWDATA                                ,
+       RULL(0x2A0F01C2), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_IPPMWDATA                                ,
+       RULL(0x2B0F01C2), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_IPPMWDATA                                ,
+       RULL(0x2C0F01C2), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_IPPMWDATA                                ,
+       RULL(0x2D0F01C2), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_IPPMWDATA                                ,
+       RULL(0x2E0F01C2), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_IPPMWDATA                                ,
+       RULL(0x2F0F01C2), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_IPPMWDATA                                ,
+       RULL(0x300F01C2), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_IPPMWDATA                                ,
+       RULL(0x310F01C2), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_IPPMWDATA                                ,
+       RULL(0x320F01C2), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_IPPMWDATA                                ,
+       RULL(0x330F01C2), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_IPPMWDATA                                ,
+       RULL(0x340F01C2), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_IPPMWDATA                                ,
+       RULL(0x350F01C2), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_IPPMWDATA                                ,
+       RULL(0x360F01C2), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_IPPMWDATA                                ,
+       RULL(0x370F01C2), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EC00_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x200F0130), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x200F0131), SH_UNT_PERV_32  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC00_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x200F0132), SH_UNT_PERV_32  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC01_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x210F0130), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x210F0131), SH_UNT_PERV_33  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC01_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x210F0132), SH_UNT_PERV_33  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC02_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x220F0130), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x220F0131), SH_UNT_PERV_34  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC02_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x220F0132), SH_UNT_PERV_34  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC03_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x230F0130), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x230F0131), SH_UNT_PERV_35  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC03_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x230F0132), SH_UNT_PERV_35  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC04_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x240F0130), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x240F0131), SH_UNT_PERV_36  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC04_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x240F0132), SH_UNT_PERV_36  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC05_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x250F0130), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x250F0131), SH_UNT_PERV_37  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC05_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x250F0132), SH_UNT_PERV_37  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC06_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x260F0130), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x260F0131), SH_UNT_PERV_38  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC06_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x260F0132), SH_UNT_PERV_38  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC07_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x270F0130), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x270F0131), SH_UNT_PERV_39  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC07_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x270F0132), SH_UNT_PERV_39  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC08_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x280F0130), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x280F0131), SH_UNT_PERV_40  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC08_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x280F0132), SH_UNT_PERV_40  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC09_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x290F0130), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x290F0131), SH_UNT_PERV_41  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC09_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x290F0132), SH_UNT_PERV_41  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC10_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x2A0F0130), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x2A0F0131), SH_UNT_PERV_42  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC10_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x2A0F0132), SH_UNT_PERV_42  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC11_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x2B0F0130), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x2B0F0131), SH_UNT_PERV_43  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC11_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x2B0F0132), SH_UNT_PERV_43  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC12_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x2C0F0130), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x2C0F0131), SH_UNT_PERV_44  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC12_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x2C0F0132), SH_UNT_PERV_44  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC13_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x2D0F0130), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x2D0F0131), SH_UNT_PERV_45  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC13_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x2D0F0132), SH_UNT_PERV_45  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC14_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x2E0F0130), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x2E0F0131), SH_UNT_PERV_46  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC14_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x2E0F0132), SH_UNT_PERV_46  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC15_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x2F0F0130), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x2F0F0131), SH_UNT_PERV_47  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC15_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x2F0F0132), SH_UNT_PERV_47  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC16_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x300F0130), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x300F0131), SH_UNT_PERV_48  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC16_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x300F0132), SH_UNT_PERV_48  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC17_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x310F0130), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x310F0131), SH_UNT_PERV_49  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC17_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x310F0132), SH_UNT_PERV_49  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC18_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x320F0130), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x320F0131), SH_UNT_PERV_50  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC18_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x320F0132), SH_UNT_PERV_50  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC19_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x330F0130), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x330F0131), SH_UNT_PERV_51  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC19_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x330F0132), SH_UNT_PERV_51  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC20_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x340F0130), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x340F0131), SH_UNT_PERV_52  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC20_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x340F0132), SH_UNT_PERV_52  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC21_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x350F0130), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x350F0131), SH_UNT_PERV_53  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC21_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x350F0132), SH_UNT_PERV_53  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC22_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x360F0130), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x360F0131), SH_UNT_PERV_54  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC22_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x360F0132), SH_UNT_PERV_54  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC23_CPPM_NC0INDIR_SCOM                            ,
+       RULL(0x370F0130), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_CPPM_NC0INDIR_SCOM1                           ,
+       RULL(0x370F0131), SH_UNT_PERV_55  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC23_CPPM_NC0INDIR_SCOM2                           ,
+       RULL(0x370F0132), SH_UNT_PERV_55  , SH_ACS_SCOM2_NC  );
+
+REG64( PERV_EC00_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x200F0133), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x200F0134), SH_UNT_PERV_32  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC00_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x200F0135), SH_UNT_PERV_32  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC01_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x210F0133), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x210F0134), SH_UNT_PERV_33  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC01_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x210F0135), SH_UNT_PERV_33  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC02_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x220F0133), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x220F0134), SH_UNT_PERV_34  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC02_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x220F0135), SH_UNT_PERV_34  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC03_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x230F0133), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x230F0134), SH_UNT_PERV_35  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC03_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x230F0135), SH_UNT_PERV_35  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC04_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x240F0133), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x240F0134), SH_UNT_PERV_36  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC04_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x240F0135), SH_UNT_PERV_36  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC05_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x250F0133), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x250F0134), SH_UNT_PERV_37  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC05_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x250F0135), SH_UNT_PERV_37  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC06_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x260F0133), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x260F0134), SH_UNT_PERV_38  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC06_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x260F0135), SH_UNT_PERV_38  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC07_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x270F0133), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x270F0134), SH_UNT_PERV_39  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC07_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x270F0135), SH_UNT_PERV_39  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC08_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x280F0133), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x280F0134), SH_UNT_PERV_40  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC08_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x280F0135), SH_UNT_PERV_40  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC09_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x290F0133), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x290F0134), SH_UNT_PERV_41  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC09_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x290F0135), SH_UNT_PERV_41  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC10_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x2A0F0133), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x2A0F0134), SH_UNT_PERV_42  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC10_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x2A0F0135), SH_UNT_PERV_42  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC11_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x2B0F0133), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x2B0F0134), SH_UNT_PERV_43  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC11_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x2B0F0135), SH_UNT_PERV_43  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC12_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x2C0F0133), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x2C0F0134), SH_UNT_PERV_44  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC12_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x2C0F0135), SH_UNT_PERV_44  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC13_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x2D0F0133), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x2D0F0134), SH_UNT_PERV_45  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC13_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x2D0F0135), SH_UNT_PERV_45  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC14_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x2E0F0133), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x2E0F0134), SH_UNT_PERV_46  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC14_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x2E0F0135), SH_UNT_PERV_46  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC15_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x2F0F0133), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x2F0F0134), SH_UNT_PERV_47  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC15_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x2F0F0135), SH_UNT_PERV_47  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC16_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x300F0133), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x300F0134), SH_UNT_PERV_48  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC16_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x300F0135), SH_UNT_PERV_48  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC17_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x310F0133), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x310F0134), SH_UNT_PERV_49  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC17_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x310F0135), SH_UNT_PERV_49  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC18_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x320F0133), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x320F0134), SH_UNT_PERV_50  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC18_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x320F0135), SH_UNT_PERV_50  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC19_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x330F0133), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x330F0134), SH_UNT_PERV_51  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC19_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x330F0135), SH_UNT_PERV_51  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC20_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x340F0133), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x340F0134), SH_UNT_PERV_52  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC20_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x340F0135), SH_UNT_PERV_52  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC21_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x350F0133), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x350F0134), SH_UNT_PERV_53  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC21_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x350F0135), SH_UNT_PERV_53  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC22_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x360F0133), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x360F0134), SH_UNT_PERV_54  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC22_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x360F0135), SH_UNT_PERV_54  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC23_CPPM_NC1INDIR_SCOM                            ,
+       RULL(0x370F0133), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_CPPM_NC1INDIR_SCOM1                           ,
+       RULL(0x370F0134), SH_UNT_PERV_55  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC23_CPPM_NC1INDIR_SCOM2                           ,
+       RULL(0x370F0135), SH_UNT_PERV_55  , SH_ACS_SCOM2_NC  );
+
+REG64( PERV_EC00_CPPM_PECES                                    ,
+       RULL(0x200F01AF), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CPPM_PECES                                    ,
+       RULL(0x210F01AF), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CPPM_PECES                                    ,
+       RULL(0x220F01AF), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CPPM_PECES                                    ,
+       RULL(0x230F01AF), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CPPM_PECES                                    ,
+       RULL(0x240F01AF), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CPPM_PECES                                    ,
+       RULL(0x250F01AF), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CPPM_PECES                                    ,
+       RULL(0x260F01AF), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CPPM_PECES                                    ,
+       RULL(0x270F01AF), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CPPM_PECES                                    ,
+       RULL(0x280F01AF), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CPPM_PECES                                    ,
+       RULL(0x290F01AF), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CPPM_PECES                                    ,
+       RULL(0x2A0F01AF), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CPPM_PECES                                    ,
+       RULL(0x2B0F01AF), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CPPM_PECES                                    ,
+       RULL(0x2C0F01AF), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CPPM_PECES                                    ,
+       RULL(0x2D0F01AF), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CPPM_PECES                                    ,
+       RULL(0x2E0F01AF), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CPPM_PECES                                    ,
+       RULL(0x2F0F01AF), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CPPM_PECES                                    ,
+       RULL(0x300F01AF), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CPPM_PECES                                    ,
+       RULL(0x310F01AF), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CPPM_PECES                                    ,
+       RULL(0x320F01AF), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CPPM_PECES                                    ,
+       RULL(0x330F01AF), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CPPM_PECES                                    ,
+       RULL(0x340F01AF), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CPPM_PECES                                    ,
+       RULL(0x350F01AF), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CPPM_PECES                                    ,
+       RULL(0x360F01AF), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CPPM_PECES                                    ,
+       RULL(0x370F01AF), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_EC00_CPPM_PERRSUM                                  ,
+       RULL(0x200F0120), SH_UNT_PERV_32  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC01_CPPM_PERRSUM                                  ,
+       RULL(0x210F0120), SH_UNT_PERV_33  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC02_CPPM_PERRSUM                                  ,
+       RULL(0x220F0120), SH_UNT_PERV_34  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC03_CPPM_PERRSUM                                  ,
+       RULL(0x230F0120), SH_UNT_PERV_35  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC04_CPPM_PERRSUM                                  ,
+       RULL(0x240F0120), SH_UNT_PERV_36  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC05_CPPM_PERRSUM                                  ,
+       RULL(0x250F0120), SH_UNT_PERV_37  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC06_CPPM_PERRSUM                                  ,
+       RULL(0x260F0120), SH_UNT_PERV_38  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC07_CPPM_PERRSUM                                  ,
+       RULL(0x270F0120), SH_UNT_PERV_39  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC08_CPPM_PERRSUM                                  ,
+       RULL(0x280F0120), SH_UNT_PERV_40  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC09_CPPM_PERRSUM                                  ,
+       RULL(0x290F0120), SH_UNT_PERV_41  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC10_CPPM_PERRSUM                                  ,
+       RULL(0x2A0F0120), SH_UNT_PERV_42  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC11_CPPM_PERRSUM                                  ,
+       RULL(0x2B0F0120), SH_UNT_PERV_43  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC12_CPPM_PERRSUM                                  ,
+       RULL(0x2C0F0120), SH_UNT_PERV_44  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC13_CPPM_PERRSUM                                  ,
+       RULL(0x2D0F0120), SH_UNT_PERV_45  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC14_CPPM_PERRSUM                                  ,
+       RULL(0x2E0F0120), SH_UNT_PERV_46  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC15_CPPM_PERRSUM                                  ,
+       RULL(0x2F0F0120), SH_UNT_PERV_47  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC16_CPPM_PERRSUM                                  ,
+       RULL(0x300F0120), SH_UNT_PERV_48  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC17_CPPM_PERRSUM                                  ,
+       RULL(0x310F0120), SH_UNT_PERV_49  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC18_CPPM_PERRSUM                                  ,
+       RULL(0x320F0120), SH_UNT_PERV_50  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC19_CPPM_PERRSUM                                  ,
+       RULL(0x330F0120), SH_UNT_PERV_51  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC20_CPPM_PERRSUM                                  ,
+       RULL(0x340F0120), SH_UNT_PERV_52  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC21_CPPM_PERRSUM                                  ,
+       RULL(0x350F0120), SH_UNT_PERV_53  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC22_CPPM_PERRSUM                                  ,
+       RULL(0x360F0120), SH_UNT_PERV_54  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EC23_CPPM_PERRSUM                                  ,
+       RULL(0x370F0120), SH_UNT_PERV_55  , SH_ACS_SCOM_WCLRPART );
+
+REG64( PERV_CRSIC                                              ,
+       RULL(0x00030005), SH_UNT_PERV     , SH_ACS_SCOM_WCLEAR );
+REG64( PERV_PIB_CRSIC                                          ,
+       RULL(0x00030005), SH_UNT_PERV_0   , SH_ACS_SCOM_WCLEAR );
+
+REG64( PERV_CRSIM                                              ,
+       RULL(0x00030006), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_CRSIM                                          ,
+       RULL(0x00030006), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_CRSIS                                              ,
+       RULL(0x00030007), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_CRSIS                                          ,
+       RULL(0x00030007), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+
+REG64( PERV_CTRL_ATOMIC_LOCK_REG                               ,
+       RULL(0x000003FF), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_CTRL_ATOMIC_LOCK_REG                            ,
+       RULL(0x010003FF), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_CTRL_ATOMIC_LOCK_REG                            ,
+       RULL(0x020003FF), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_CTRL_ATOMIC_LOCK_REG                            ,
+       RULL(0x030003FF), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_CTRL_ATOMIC_LOCK_REG                            ,
+       RULL(0x040003FF), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_CTRL_ATOMIC_LOCK_REG                            ,
+       RULL(0x050003FF), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_CTRL_ATOMIC_LOCK_REG                            ,
+       RULL(0x060003FF), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x070003FF), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x080003FF), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_CTRL_ATOMIC_LOCK_REG                           ,
+       RULL(0x090003FF), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_CTRL_ATOMIC_LOCK_REG                           ,
+       RULL(0x0C0003FF), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x0D0003FF), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x0E0003FF), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x0F0003FF), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x100003FF), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x110003FF), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x120003FF), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x130003FF), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x140003FF), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x150003FF), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x200003FF), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x210003FF), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x220003FF), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x230003FF), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x240003FF), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x250003FF), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x260003FF), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x270003FF), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x280003FF), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x290003FF), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x2A0003FF), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x2B0003FF), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x2C0003FF), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x2D0003FF), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x2E0003FF), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x2F0003FF), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x300003FF), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x310003FF), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x320003FF), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x330003FF), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x340003FF), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x350003FF), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x360003FF), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CTRL_ATOMIC_LOCK_REG                          ,
+       RULL(0x370003FF), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_CTRL_PROTECT_MODE_REG                              ,
+       RULL(0x000003FE), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_CTRL_PROTECT_MODE_REG                           ,
+       RULL(0x010003FE), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_CTRL_PROTECT_MODE_REG                           ,
+       RULL(0x020003FE), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_CTRL_PROTECT_MODE_REG                           ,
+       RULL(0x030003FE), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_CTRL_PROTECT_MODE_REG                           ,
+       RULL(0x040003FE), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_CTRL_PROTECT_MODE_REG                           ,
+       RULL(0x050003FE), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_CTRL_PROTECT_MODE_REG                           ,
+       RULL(0x060003FE), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x070003FE), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x080003FE), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_CTRL_PROTECT_MODE_REG                          ,
+       RULL(0x090003FE), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_CTRL_PROTECT_MODE_REG                          ,
+       RULL(0x0C0003FE), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x0D0003FE), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x0E0003FE), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x0F0003FE), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x100003FE), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x110003FE), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x120003FE), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x130003FE), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x140003FE), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x150003FE), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x200003FE), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x210003FE), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x220003FE), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x230003FE), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x240003FE), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x250003FE), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x260003FE), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x270003FE), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x280003FE), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x290003FE), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x2A0003FE), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x2B0003FE), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x2C0003FE), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x2D0003FE), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x2E0003FE), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x2F0003FE), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x300003FE), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x310003FE), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x320003FE), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x330003FE), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x340003FE), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x350003FE), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x360003FE), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CTRL_PROTECT_MODE_REG                         ,
+       RULL(0x370003FE), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG32( PERV_FSI2PIB_DATA_REGISTER_0_FSI                        ,
+       RULL(0x00001000), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI       );
+
+REG32( PERV_FSI2PIB_DATA_REGISTER_1_FSI                        ,
+       RULL(0x00001001), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI       );
+REG32( PERV_FSI2PIB_DATA_REGISTER_1_FSI_BYTE                   ,
+       RULL(0x00001004), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE  );
+
+REG64( PERV_DBG_CBS_CC                                         ,
+       RULL(0x00030013), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_DBG_CBS_CC                                      ,
+       RULL(0x01030013), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_DBG_CBS_CC                                      ,
+       RULL(0x02030013), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_DBG_CBS_CC                                      ,
+       RULL(0x03030013), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_DBG_CBS_CC                                      ,
+       RULL(0x04030013), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_DBG_CBS_CC                                      ,
+       RULL(0x05030013), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_DBG_CBS_CC                                      ,
+       RULL(0x06030013), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_DBG_CBS_CC                                    ,
+       RULL(0x07030013), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_DBG_CBS_CC                                    ,
+       RULL(0x08030013), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_DBG_CBS_CC                                     ,
+       RULL(0x09030013), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_DBG_CBS_CC                                     ,
+       RULL(0x0C030013), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_DBG_CBS_CC                                    ,
+       RULL(0x0D030013), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_DBG_CBS_CC                                    ,
+       RULL(0x0E030013), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_DBG_CBS_CC                                    ,
+       RULL(0x0F030013), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_DBG_CBS_CC                                    ,
+       RULL(0x10030013), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_DBG_CBS_CC                                    ,
+       RULL(0x11030013), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_DBG_CBS_CC                                    ,
+       RULL(0x12030013), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_DBG_CBS_CC                                    ,
+       RULL(0x13030013), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_DBG_CBS_CC                                    ,
+       RULL(0x14030013), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_DBG_CBS_CC                                    ,
+       RULL(0x15030013), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_DBG_CBS_CC                                    ,
+       RULL(0x20030013), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_DBG_CBS_CC                                    ,
+       RULL(0x21030013), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_DBG_CBS_CC                                    ,
+       RULL(0x22030013), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_DBG_CBS_CC                                    ,
+       RULL(0x23030013), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_DBG_CBS_CC                                    ,
+       RULL(0x24030013), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_DBG_CBS_CC                                    ,
+       RULL(0x25030013), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_DBG_CBS_CC                                    ,
+       RULL(0x26030013), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_DBG_CBS_CC                                    ,
+       RULL(0x27030013), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_DBG_CBS_CC                                    ,
+       RULL(0x28030013), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_DBG_CBS_CC                                    ,
+       RULL(0x29030013), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_DBG_CBS_CC                                    ,
+       RULL(0x2A030013), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_DBG_CBS_CC                                    ,
+       RULL(0x2B030013), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_DBG_CBS_CC                                    ,
+       RULL(0x2C030013), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_DBG_CBS_CC                                    ,
+       RULL(0x2D030013), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_DBG_CBS_CC                                    ,
+       RULL(0x2E030013), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_DBG_CBS_CC                                    ,
+       RULL(0x2F030013), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_DBG_CBS_CC                                    ,
+       RULL(0x30030013), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_DBG_CBS_CC                                    ,
+       RULL(0x31030013), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_DBG_CBS_CC                                    ,
+       RULL(0x32030013), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_DBG_CBS_CC                                    ,
+       RULL(0x33030013), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_DBG_CBS_CC                                    ,
+       RULL(0x34030013), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_DBG_CBS_CC                                    ,
+       RULL(0x35030013), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_DBG_CBS_CC                                    ,
+       RULL(0x36030013), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_DBG_CBS_CC                                    ,
+       RULL(0x37030013), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_DEVICE_ID_REG                                      ,
+       RULL(0x000F000F), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_DEVICE_ID_REG                                  ,
+       RULL(0x000F000F), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_FSISHIFT_DMA_ERROR_PTR_REGISTER_FSI                ,
+       RULL(0x00000C21), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_DMA_ERROR_PTR_REGISTER_FSI_BYTE           ,
+       RULL(0x00000C84), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_DMA_MODE_REGISTER_FSI                     ,
+       RULL(0x00000C19), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_DMA_MODE_REGISTER_FSI_BYTE                ,
+       RULL(0x00000C64), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_DMA_OP_BLOCKSIZE_REGISTER_FSI             ,
+       RULL(0x00000C1B), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_DMA_OP_BLOCKSIZE_REGISTER_FSI_BYTE        ,
+       RULL(0x00000C6C), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_DMA_PIB_RCV_BUFFER0_REGISTER_FSI          ,
+       RULL(0x00000C1F), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_DMA_PIB_RCV_BUFFER0_REGISTER_FSI_BYTE     ,
+       RULL(0x00000C7C), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_DMA_PIB_RCV_BUFFER1_REGISTER_FSI          ,
+       RULL(0x00000C20), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_DMA_PIB_RCV_BUFFER1_REGISTER_FSI_BYTE     ,
+       RULL(0x00000C80), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_DMA_PIB_SND_BUFFER0_REGISTER_FSI          ,
+       RULL(0x00000C1D), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_DMA_PIB_SND_BUFFER0_REGISTER_FSI_BYTE     ,
+       RULL(0x00000C74), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_DMA_PIB_SND_BUFFER1_REGISTER_FSI          ,
+       RULL(0x00000C1E), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_DMA_PIB_SND_BUFFER1_REGISTER_FSI_BYTE     ,
+       RULL(0x00000C78), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_DMA_REM_SIZE_REGISTER_FSI                 ,
+       RULL(0x00000C1C), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_DMA_REM_SIZE_REGISTER_FSI_BYTE            ,
+       RULL(0x00000C70), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_DMA_SCOM_CMD_REGISTER_FSI                 ,
+       RULL(0x00000C22), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_DMA_SCOM_CMD_REGISTER_FSI_BYTE            ,
+       RULL(0x00000C88), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_DMA_STAT_COMP_MASK_REGISTER_FSI           ,
+       RULL(0x00000C1A), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_DMA_STAT_COMP_MASK_REGISTER_FSI_BYTE      ,
+       RULL(0x00000C68), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE  );
+
+REG32( PERV_DOORBELL_STATUS_CONTROL_1A_FSI                     ,
+       RULL(0x00002824), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_DOORBELL_STATUS_CONTROL_1A_FSI_BYTE                ,
+       RULL(0x00002890), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_DOORBELL_STATUS_CONTROL_1A_SCOM                    ,
+       RULL(0x00050020), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_DOORBELL_STATUS_CONTROL_1A                     ,
+       RULL(0x00050020), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_DOORBELL_STATUS_CONTROL_2A_FSI                     ,
+       RULL(0x0000282C), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_DOORBELL_STATUS_CONTROL_2A_FSI_BYTE                ,
+       RULL(0x000028B0), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_DOORBELL_STATUS_CONTROL_2A_SCOM                    ,
+       RULL(0x00050028), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_DOORBELL_STATUS_CONTROL_2A                     ,
+       RULL(0x00050028), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_DTS_RESULT0                                        ,
+       RULL(0x00050000), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_DTS_RESULT0                                     ,
+       RULL(0x01050000), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_N0_DTS_RESULT0                                     ,
+       RULL(0x02050000), SH_UNT_PERV_2   , SH_ACS_SCOM_RO   );
+REG64( PERV_N1_DTS_RESULT0                                     ,
+       RULL(0x03050000), SH_UNT_PERV_3   , SH_ACS_SCOM_RO   );
+REG64( PERV_N2_DTS_RESULT0                                     ,
+       RULL(0x04050000), SH_UNT_PERV_4   , SH_ACS_SCOM_RO   );
+REG64( PERV_N3_DTS_RESULT0                                     ,
+       RULL(0x05050000), SH_UNT_PERV_5   , SH_ACS_SCOM_RO   );
+REG64( PERV_XB_DTS_RESULT0                                     ,
+       RULL(0x06050000), SH_UNT_PERV_6   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC01_DTS_RESULT0                                   ,
+       RULL(0x07050000), SH_UNT_PERV_7   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC23_DTS_RESULT0                                   ,
+       RULL(0x08050000), SH_UNT_PERV_8   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB0_DTS_RESULT0                                    ,
+       RULL(0x09050000), SH_UNT_PERV_9   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB3_DTS_RESULT0                                    ,
+       RULL(0x0C050000), SH_UNT_PERV_12  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI0_DTS_RESULT0                                   ,
+       RULL(0x0D050000), SH_UNT_PERV_13  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI1_DTS_RESULT0                                   ,
+       RULL(0x0E050000), SH_UNT_PERV_14  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI2_DTS_RESULT0                                   ,
+       RULL(0x0F050000), SH_UNT_PERV_15  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP00_DTS_RESULT0                                   ,
+       RULL(0x10050000), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_DTS_RESULT0                                   ,
+       RULL(0x11050000), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_DTS_RESULT0                                   ,
+       RULL(0x12050000), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_DTS_RESULT0                                   ,
+       RULL(0x13050000), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_DTS_RESULT0                                   ,
+       RULL(0x14050000), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_DTS_RESULT0                                   ,
+       RULL(0x15050000), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_DTS_RESULT0                                   ,
+       RULL(0x20050000), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_DTS_RESULT0                                   ,
+       RULL(0x21050000), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_DTS_RESULT0                                   ,
+       RULL(0x22050000), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_DTS_RESULT0                                   ,
+       RULL(0x23050000), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_DTS_RESULT0                                   ,
+       RULL(0x24050000), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_DTS_RESULT0                                   ,
+       RULL(0x25050000), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_DTS_RESULT0                                   ,
+       RULL(0x26050000), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_DTS_RESULT0                                   ,
+       RULL(0x27050000), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_DTS_RESULT0                                   ,
+       RULL(0x28050000), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_DTS_RESULT0                                   ,
+       RULL(0x29050000), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_DTS_RESULT0                                   ,
+       RULL(0x2A050000), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_DTS_RESULT0                                   ,
+       RULL(0x2B050000), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_DTS_RESULT0                                   ,
+       RULL(0x2C050000), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_DTS_RESULT0                                   ,
+       RULL(0x2D050000), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_DTS_RESULT0                                   ,
+       RULL(0x2E050000), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_DTS_RESULT0                                   ,
+       RULL(0x2F050000), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_DTS_RESULT0                                   ,
+       RULL(0x30050000), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_DTS_RESULT0                                   ,
+       RULL(0x31050000), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_DTS_RESULT0                                   ,
+       RULL(0x32050000), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_DTS_RESULT0                                   ,
+       RULL(0x33050000), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_DTS_RESULT0                                   ,
+       RULL(0x34050000), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_DTS_RESULT0                                   ,
+       RULL(0x35050000), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_DTS_RESULT0                                   ,
+       RULL(0x36050000), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_DTS_RESULT0                                   ,
+       RULL(0x37050000), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_DTS_TRC_RESULT                                     ,
+       RULL(0x00050003), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_DTS_TRC_RESULT                                  ,
+       RULL(0x01050003), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_N0_DTS_TRC_RESULT                                  ,
+       RULL(0x02050003), SH_UNT_PERV_2   , SH_ACS_SCOM_RO   );
+REG64( PERV_N1_DTS_TRC_RESULT                                  ,
+       RULL(0x03050003), SH_UNT_PERV_3   , SH_ACS_SCOM_RO   );
+REG64( PERV_N2_DTS_TRC_RESULT                                  ,
+       RULL(0x04050003), SH_UNT_PERV_4   , SH_ACS_SCOM_RO   );
+REG64( PERV_N3_DTS_TRC_RESULT                                  ,
+       RULL(0x05050003), SH_UNT_PERV_5   , SH_ACS_SCOM_RO   );
+REG64( PERV_XB_DTS_TRC_RESULT                                  ,
+       RULL(0x06050003), SH_UNT_PERV_6   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC01_DTS_TRC_RESULT                                ,
+       RULL(0x07050003), SH_UNT_PERV_7   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC23_DTS_TRC_RESULT                                ,
+       RULL(0x08050003), SH_UNT_PERV_8   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB0_DTS_TRC_RESULT                                 ,
+       RULL(0x09050003), SH_UNT_PERV_9   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB3_DTS_TRC_RESULT                                 ,
+       RULL(0x0C050003), SH_UNT_PERV_12  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI0_DTS_TRC_RESULT                                ,
+       RULL(0x0D050003), SH_UNT_PERV_13  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI1_DTS_TRC_RESULT                                ,
+       RULL(0x0E050003), SH_UNT_PERV_14  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI2_DTS_TRC_RESULT                                ,
+       RULL(0x0F050003), SH_UNT_PERV_15  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP00_DTS_TRC_RESULT                                ,
+       RULL(0x10050003), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_DTS_TRC_RESULT                                ,
+       RULL(0x11050003), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_DTS_TRC_RESULT                                ,
+       RULL(0x12050003), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_DTS_TRC_RESULT                                ,
+       RULL(0x13050003), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_DTS_TRC_RESULT                                ,
+       RULL(0x14050003), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_DTS_TRC_RESULT                                ,
+       RULL(0x15050003), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_DTS_TRC_RESULT                                ,
+       RULL(0x20050003), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_DTS_TRC_RESULT                                ,
+       RULL(0x21050003), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_DTS_TRC_RESULT                                ,
+       RULL(0x22050003), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_DTS_TRC_RESULT                                ,
+       RULL(0x23050003), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_DTS_TRC_RESULT                                ,
+       RULL(0x24050003), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_DTS_TRC_RESULT                                ,
+       RULL(0x25050003), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_DTS_TRC_RESULT                                ,
+       RULL(0x26050003), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_DTS_TRC_RESULT                                ,
+       RULL(0x27050003), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_DTS_TRC_RESULT                                ,
+       RULL(0x28050003), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_DTS_TRC_RESULT                                ,
+       RULL(0x29050003), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_DTS_TRC_RESULT                                ,
+       RULL(0x2A050003), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_DTS_TRC_RESULT                                ,
+       RULL(0x2B050003), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_DTS_TRC_RESULT                                ,
+       RULL(0x2C050003), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_DTS_TRC_RESULT                                ,
+       RULL(0x2D050003), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_DTS_TRC_RESULT                                ,
+       RULL(0x2E050003), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_DTS_TRC_RESULT                                ,
+       RULL(0x2F050003), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_DTS_TRC_RESULT                                ,
+       RULL(0x30050003), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_DTS_TRC_RESULT                                ,
+       RULL(0x31050003), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_DTS_TRC_RESULT                                ,
+       RULL(0x32050003), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_DTS_TRC_RESULT                                ,
+       RULL(0x33050003), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_DTS_TRC_RESULT                                ,
+       RULL(0x34050003), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_DTS_TRC_RESULT                                ,
+       RULL(0x35050003), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_DTS_TRC_RESULT                                ,
+       RULL(0x36050003), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_DTS_TRC_RESULT                                ,
+       RULL(0x37050003), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_ERROR_REG                                          ,
+       RULL(0x000F001F), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ERROR_REG                                      ,
+       RULL(0x000F001F), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+REG64( PERV_TP_ERROR_REG                                       ,
+       RULL(0x010F001F), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_ERROR_REG                                       ,
+       RULL(0x020F001F), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_ERROR_REG                                       ,
+       RULL(0x030F001F), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_ERROR_REG                                       ,
+       RULL(0x040F001F), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_ERROR_REG                                       ,
+       RULL(0x050F001F), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_ERROR_REG                                       ,
+       RULL(0x060F001F), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_ERROR_REG                                     ,
+       RULL(0x070F001F), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_ERROR_REG                                     ,
+       RULL(0x080F001F), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_ERROR_REG                                      ,
+       RULL(0x090F001F), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_ERROR_REG                                      ,
+       RULL(0x0C0F001F), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_ERROR_REG                                     ,
+       RULL(0x0D0F001F), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_ERROR_REG                                     ,
+       RULL(0x0E0F001F), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_ERROR_REG                                     ,
+       RULL(0x0F0F001F), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_ERROR_REG                                     ,
+       RULL(0x100F001F), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_ERROR_REG                                     ,
+       RULL(0x110F001F), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_ERROR_REG                                     ,
+       RULL(0x120F001F), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_ERROR_REG                                     ,
+       RULL(0x130F001F), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_ERROR_REG                                     ,
+       RULL(0x140F001F), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_ERROR_REG                                     ,
+       RULL(0x150F001F), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_ERROR_REG                                     ,
+       RULL(0x200F001F), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_ERROR_REG                                     ,
+       RULL(0x210F001F), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_ERROR_REG                                     ,
+       RULL(0x220F001F), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_ERROR_REG                                     ,
+       RULL(0x230F001F), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_ERROR_REG                                     ,
+       RULL(0x240F001F), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_ERROR_REG                                     ,
+       RULL(0x250F001F), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_ERROR_REG                                     ,
+       RULL(0x260F001F), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_ERROR_REG                                     ,
+       RULL(0x270F001F), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_ERROR_REG                                     ,
+       RULL(0x280F001F), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_ERROR_REG                                     ,
+       RULL(0x290F001F), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_ERROR_REG                                     ,
+       RULL(0x2A0F001F), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_ERROR_REG                                     ,
+       RULL(0x2B0F001F), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_ERROR_REG                                     ,
+       RULL(0x2C0F001F), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_ERROR_REG                                     ,
+       RULL(0x2D0F001F), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_ERROR_REG                                     ,
+       RULL(0x2E0F001F), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_ERROR_REG                                     ,
+       RULL(0x2F0F001F), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_ERROR_REG                                     ,
+       RULL(0x300F001F), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_ERROR_REG                                     ,
+       RULL(0x310F001F), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_ERROR_REG                                     ,
+       RULL(0x320F001F), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_ERROR_REG                                     ,
+       RULL(0x330F001F), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_ERROR_REG                                     ,
+       RULL(0x340F001F), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_ERROR_REG                                     ,
+       RULL(0x350F001F), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_ERROR_REG                                     ,
+       RULL(0x360F001F), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_ERROR_REG                                     ,
+       RULL(0x370F001F), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_ERROR_STATUS                                       ,
+       RULL(0x0003000F), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_ERROR_STATUS                                    ,
+       RULL(0x0103000F), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_ERROR_STATUS                                    ,
+       RULL(0x0203000F), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_ERROR_STATUS                                    ,
+       RULL(0x0303000F), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_ERROR_STATUS                                    ,
+       RULL(0x0403000F), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_ERROR_STATUS                                    ,
+       RULL(0x0503000F), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_ERROR_STATUS                                    ,
+       RULL(0x0603000F), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_ERROR_STATUS                                  ,
+       RULL(0x0703000F), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_ERROR_STATUS                                  ,
+       RULL(0x0803000F), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_ERROR_STATUS                                   ,
+       RULL(0x0903000F), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_ERROR_STATUS                                   ,
+       RULL(0x0C03000F), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_ERROR_STATUS                                  ,
+       RULL(0x0D03000F), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_ERROR_STATUS                                  ,
+       RULL(0x0E03000F), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_ERROR_STATUS                                  ,
+       RULL(0x0F03000F), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_ERROR_STATUS                                  ,
+       RULL(0x1003000F), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_ERROR_STATUS                                  ,
+       RULL(0x1103000F), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_ERROR_STATUS                                  ,
+       RULL(0x1203000F), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_ERROR_STATUS                                  ,
+       RULL(0x1303000F), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_ERROR_STATUS                                  ,
+       RULL(0x1403000F), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_ERROR_STATUS                                  ,
+       RULL(0x1503000F), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_ERROR_STATUS                                  ,
+       RULL(0x2003000F), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_ERROR_STATUS                                  ,
+       RULL(0x2103000F), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_ERROR_STATUS                                  ,
+       RULL(0x2203000F), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_ERROR_STATUS                                  ,
+       RULL(0x2303000F), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_ERROR_STATUS                                  ,
+       RULL(0x2403000F), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_ERROR_STATUS                                  ,
+       RULL(0x2503000F), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_ERROR_STATUS                                  ,
+       RULL(0x2603000F), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_ERROR_STATUS                                  ,
+       RULL(0x2703000F), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_ERROR_STATUS                                  ,
+       RULL(0x2803000F), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_ERROR_STATUS                                  ,
+       RULL(0x2903000F), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_ERROR_STATUS                                  ,
+       RULL(0x2A03000F), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_ERROR_STATUS                                  ,
+       RULL(0x2B03000F), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_ERROR_STATUS                                  ,
+       RULL(0x2C03000F), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_ERROR_STATUS                                  ,
+       RULL(0x2D03000F), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_ERROR_STATUS                                  ,
+       RULL(0x2E03000F), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_ERROR_STATUS                                  ,
+       RULL(0x2F03000F), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_ERROR_STATUS                                  ,
+       RULL(0x3003000F), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_ERROR_STATUS                                  ,
+       RULL(0x3103000F), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_ERROR_STATUS                                  ,
+       RULL(0x3203000F), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_ERROR_STATUS                                  ,
+       RULL(0x3303000F), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_ERROR_STATUS                                  ,
+       RULL(0x3403000F), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_ERROR_STATUS                                  ,
+       RULL(0x3503000F), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_ERROR_STATUS                                  ,
+       RULL(0x3603000F), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_ERROR_STATUS                                  ,
+       RULL(0x3703000F), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_ERROR_STATUS_REG                                   ,
+       RULL(0x000F0034), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ERROR_STATUS_REG                               ,
+       RULL(0x000F0034), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_ERR_STATUS_REG                                     ,
+       RULL(0x00050013), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_ERR_STATUS_REG                                  ,
+       RULL(0x01050013), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_N0_ERR_STATUS_REG                                  ,
+       RULL(0x02050013), SH_UNT_PERV_2   , SH_ACS_SCOM_RO   );
+REG64( PERV_N1_ERR_STATUS_REG                                  ,
+       RULL(0x03050013), SH_UNT_PERV_3   , SH_ACS_SCOM_RO   );
+REG64( PERV_N2_ERR_STATUS_REG                                  ,
+       RULL(0x04050013), SH_UNT_PERV_4   , SH_ACS_SCOM_RO   );
+REG64( PERV_N3_ERR_STATUS_REG                                  ,
+       RULL(0x05050013), SH_UNT_PERV_5   , SH_ACS_SCOM_RO   );
+REG64( PERV_XB_ERR_STATUS_REG                                  ,
+       RULL(0x06050013), SH_UNT_PERV_6   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC01_ERR_STATUS_REG                                ,
+       RULL(0x07050013), SH_UNT_PERV_7   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC23_ERR_STATUS_REG                                ,
+       RULL(0x08050013), SH_UNT_PERV_8   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB0_ERR_STATUS_REG                                 ,
+       RULL(0x09050013), SH_UNT_PERV_9   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB3_ERR_STATUS_REG                                 ,
+       RULL(0x0C050013), SH_UNT_PERV_12  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI0_ERR_STATUS_REG                                ,
+       RULL(0x0D050013), SH_UNT_PERV_13  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI1_ERR_STATUS_REG                                ,
+       RULL(0x0E050013), SH_UNT_PERV_14  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI2_ERR_STATUS_REG                                ,
+       RULL(0x0F050013), SH_UNT_PERV_15  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP00_ERR_STATUS_REG                                ,
+       RULL(0x10050013), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_ERR_STATUS_REG                                ,
+       RULL(0x11050013), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_ERR_STATUS_REG                                ,
+       RULL(0x12050013), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_ERR_STATUS_REG                                ,
+       RULL(0x13050013), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_ERR_STATUS_REG                                ,
+       RULL(0x14050013), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_ERR_STATUS_REG                                ,
+       RULL(0x15050013), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_ERR_STATUS_REG                                ,
+       RULL(0x20050013), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_ERR_STATUS_REG                                ,
+       RULL(0x21050013), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_ERR_STATUS_REG                                ,
+       RULL(0x22050013), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_ERR_STATUS_REG                                ,
+       RULL(0x23050013), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_ERR_STATUS_REG                                ,
+       RULL(0x24050013), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_ERR_STATUS_REG                                ,
+       RULL(0x25050013), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_ERR_STATUS_REG                                ,
+       RULL(0x26050013), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_ERR_STATUS_REG                                ,
+       RULL(0x27050013), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_ERR_STATUS_REG                                ,
+       RULL(0x28050013), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_ERR_STATUS_REG                                ,
+       RULL(0x29050013), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_ERR_STATUS_REG                                ,
+       RULL(0x2A050013), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_ERR_STATUS_REG                                ,
+       RULL(0x2B050013), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_ERR_STATUS_REG                                ,
+       RULL(0x2C050013), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_ERR_STATUS_REG                                ,
+       RULL(0x2D050013), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_ERR_STATUS_REG                                ,
+       RULL(0x2E050013), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_ERR_STATUS_REG                                ,
+       RULL(0x2F050013), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_ERR_STATUS_REG                                ,
+       RULL(0x30050013), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_ERR_STATUS_REG                                ,
+       RULL(0x31050013), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_ERR_STATUS_REG                                ,
+       RULL(0x32050013), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_ERR_STATUS_REG                                ,
+       RULL(0x33050013), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_ERR_STATUS_REG                                ,
+       RULL(0x34050013), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_ERR_STATUS_REG                                ,
+       RULL(0x35050013), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_ERR_STATUS_REG                                ,
+       RULL(0x36050013), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_ERR_STATUS_REG                                ,
+       RULL(0x37050013), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_0_FSII2C_EXTENDED_STATUS                           ,
+       RULL(0x00001808), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM      );
+REG32( PERV_FSII2C_EXTENDED_STATUS                             ,
+       RULL(0x00001808), SH_UNT_PERV_FSII2C, SH_ACS_SCOM      );
+REG32( PERV_FSISHIFT_EXTENDED_STATUS_FSI                       ,
+       RULL(0x00000C08), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_EXTENDED_STATUS_FSI_BYTE                  ,
+       RULL(0x00000C20), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE  );
+
+REG64( PERV_FI2C_CFG_PPE                                       ,
+       RULL(0x00000800), SH_UNT_PERV     , SH_ACS_PPE       );
+REG64( PERV_FI2C_CFG_PPE1                                      ,
+       RULL(0x00000810), SH_UNT_PERV     , SH_ACS_PPE1      );
+REG64( PERV_FI2C_CFG_PPE2                                      ,
+       RULL(0x00000818), SH_UNT_PERV     , SH_ACS_PPE2      );
+
+REG64( PERV_FI2C_SCFG0_PPE                                     ,
+       RULL(0x00000860), SH_UNT_PERV     , SH_ACS_PPE       );
+REG64( PERV_FI2C_SCFG0_PPE1                                    ,
+       RULL(0x00000870), SH_UNT_PERV     , SH_ACS_PPE1      );
+REG64( PERV_FI2C_SCFG0_PPE2                                    ,
+       RULL(0x00000878), SH_UNT_PERV     , SH_ACS_PPE2      );
+
+REG64( PERV_FI2C_SCFG1_PPE                                     ,
+       RULL(0x00000880), SH_UNT_PERV     , SH_ACS_PPE       );
+REG64( PERV_FI2C_SCFG1_PPE1                                    ,
+       RULL(0x00000890), SH_UNT_PERV     , SH_ACS_PPE1      );
+REG64( PERV_FI2C_SCFG1_PPE2                                    ,
+       RULL(0x00000898), SH_UNT_PERV     , SH_ACS_PPE2      );
+
+REG64( PERV_FI2C_SCFG2_PPE                                     ,
+       RULL(0x000008A0), SH_UNT_PERV     , SH_ACS_PPE       );
+REG64( PERV_FI2C_SCFG2_PPE1                                    ,
+       RULL(0x000008B0), SH_UNT_PERV     , SH_ACS_PPE1      );
+REG64( PERV_FI2C_SCFG2_PPE2                                    ,
+       RULL(0x000008B8), SH_UNT_PERV     , SH_ACS_PPE2      );
+
+REG64( PERV_FI2C_SCFG3_PPE                                     ,
+       RULL(0x000008C0), SH_UNT_PERV     , SH_ACS_PPE       );
+REG64( PERV_FI2C_SCFG3_PPE1                                    ,
+       RULL(0x000008D0), SH_UNT_PERV     , SH_ACS_PPE1      );
+REG64( PERV_FI2C_SCFG3_PPE2                                    ,
+       RULL(0x000008D8), SH_UNT_PERV     , SH_ACS_PPE2      );
+
+REG64( PERV_FI2C_STAT_PPE                                      ,
+       RULL(0x00000820), SH_UNT_PERV     , SH_ACS_PPE       );
+
+REG64( PERV_0_FSII2C_FIFO_REGISTER                             ,
+       RULL(0x00001800), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM      );
+REG32( PERV_FSII2C_FIFO_REGISTER                               ,
+       RULL(0x00001800), SH_UNT_PERV_FSII2C, SH_ACS_SCOM      );
+
+REG64( PERV_FIRST_ERR_REG                                      ,
+       RULL(0x000F001E), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_FIRST_ERR_REG                                  ,
+       RULL(0x000F001E), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_FIRST_REPLY_REG                                    ,
+       RULL(0x000F0018), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_FIRST_REPLY_REG                                ,
+       RULL(0x000F0018), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_FSISHIFT_FRONT_END_LENGTH_REGISTER_FSI             ,
+       RULL(0x00000C02), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_FRONT_END_LENGTH_REGISTER_FSI_BYTE        ,
+       RULL(0x00000C08), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSB_FSB_DNFIFO_DATA_OUT_FSI                        ,
+       RULL(0x00002410), SH_UNT_PERV_FSB , SH_ACS_FSI       );
+REG64( PERV_FSB_FSB_DNFIFO_DATA_OUT_FSI_BYTE                   ,
+       RULL(0x00002440), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSB_FSB_DOWNFIFO_ACK_EOT_FSI                       ,
+       RULL(0x00002415), SH_UNT_PERV_FSB , SH_ACS_FSI       );
+REG64( PERV_FSB_FSB_DOWNFIFO_ACK_EOT_FSI_BYTE                  ,
+       RULL(0x00002454), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSB_FSB_DOWNFIFO_RESET_FSI                         ,
+       RULL(0x00002414), SH_UNT_PERV_FSB , SH_ACS_FSI       );
+REG64( PERV_FSB_FSB_DOWNFIFO_RESET_FSI_BYTE                    ,
+       RULL(0x00002450), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSB_FSB_DOWNFIFO_STATUS_FSI                        ,
+       RULL(0x00002411), SH_UNT_PERV_FSB , SH_ACS_FSI       );
+REG64( PERV_FSB_FSB_DOWNFIFO_STATUS_FSI_BYTE                   ,
+       RULL(0x00002444), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSB_FSB_UPFIFO_DATA_IN_FSI                         ,
+       RULL(0x00002400), SH_UNT_PERV_FSB , SH_ACS_FSI       );
+
+REG32( PERV_FSB_FSB_UPFIFO_REQ_RESET_FSI                       ,
+       RULL(0x00002403), SH_UNT_PERV_FSB , SH_ACS_FSI       );
+REG64( PERV_FSB_FSB_UPFIFO_REQ_RESET_FSI_BYTE                  ,
+       RULL(0x0000240C), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSB_FSB_UPFIFO_SIG_EOT_FSI                         ,
+       RULL(0x00002402), SH_UNT_PERV_FSB , SH_ACS_FSI       );
+REG64( PERV_FSB_FSB_UPFIFO_SIG_EOT_FSI_BYTE                    ,
+       RULL(0x00002408), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSB_FSB_UPFIFO_STATUS_FSI                          ,
+       RULL(0x00002401), SH_UNT_PERV_FSB , SH_ACS_FSI       );
+REG64( PERV_FSB_FSB_UPFIFO_STATUS_FSI_BYTE                     ,
+       RULL(0x00002404), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISCRPD_FSI                                       ,
+       RULL(0x00001401), SH_UNT_PERV     , SH_ACS_FSI       );
+REG32( PERV_FSISCRPD_FSI_BYTE                                  ,
+       RULL(0x00001404), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSI_A_LLMOD_FSI0                                   ,
+       RULL(0x00000900), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_LLSTAT_FSI0                                  ,
+       RULL(0x00000904), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_MST_0_MAEB_FSI0                              ,
+       RULL(0x00003070), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MAEB                          ,
+       RULL(0x00000C1C), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MAESP0_FSI0                            ,
+       RULL(0x00003050), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MAESP0                        ,
+       RULL(0x00000C14), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_0_MAESP1_FSI0                            ,
+       RULL(0x00003054), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MAESP1                        ,
+       RULL(0x00000C15), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MAESP2_FSI0                            ,
+       RULL(0x00003058), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MAESP2                        ,
+       RULL(0x00000C16), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MAESP3_FSI0                            ,
+       RULL(0x0000305C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MAESP3                        ,
+       RULL(0x00000C17), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MAESP4_FSI0                            ,
+       RULL(0x00003060), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MAESP4                        ,
+       RULL(0x00000C18), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MAESP5_FSI0                            ,
+       RULL(0x00003064), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MAESP5                        ,
+       RULL(0x00000C19), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MAESP6_FSI0                            ,
+       RULL(0x00003068), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MAESP6                        ,
+       RULL(0x00000C1A), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MAESP7_FSI0                            ,
+       RULL(0x0000306C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MAESP7                        ,
+       RULL(0x00000C1B), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MATRB0_FSI0                            ,
+       RULL(0x000031D8), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MATRB0                        ,
+       RULL(0x00000C76), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_0_MCENP0_FSI0                            ,
+       RULL(0x00003020), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MCENP0                        ,
+       RULL(0x00000C08), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MCRSP0_FSI0                            ,
+       RULL(0x00003008), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MCRSP0                        ,
+       RULL(0x00000C02), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MCRSP1_FSI0                            ,
+       RULL(0x0000300C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MCRSP1                        ,
+       RULL(0x00000C03), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MCSIEP0_FSI0                           ,
+       RULL(0x00003070), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MCSIEP0                       ,
+       RULL(0x00000C1C), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_CLEAR );
+
+REG32( PERV_FSI_A_MST_0_MDLYR_FSI0                             ,
+       RULL(0x00003004), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MDLYR                         ,
+       RULL(0x00000C01), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MDTRB0_FSI0                            ,
+       RULL(0x000031DC), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MDTRB0                        ,
+       RULL(0x00000C77), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_0_MECTRL_FSI0                            ,
+       RULL(0x000032E0), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MECTRL                        ,
+       RULL(0x00000CB8), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MENP0_FSI0                             ,
+       RULL(0x00003010), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MENP0                         ,
+       RULL(0x00000C04), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MENP1_FSI0                             ,
+       RULL(0x00003014), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MENP1                         ,
+       RULL(0x00000C05), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MESRB0_FSI0                            ,
+       RULL(0x000031D0), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MESRB0                        ,
+       RULL(0x00000C74), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MLEVP0_FSI0                            ,
+       RULL(0x00003018), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MLEVP0                        ,
+       RULL(0x00000C06), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_0_MLEVP1_FSI0                            ,
+       RULL(0x0000301C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MLEVP1                        ,
+       RULL(0x00000C07), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_0_MMODE_FSI0                             ,
+       RULL(0x00003000), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MMODE                         ,
+       RULL(0x00000C00), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MREFP0_FSI0                            ,
+       RULL(0x00003020), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MREFP0                        ,
+       RULL(0x00000C08), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_0_MREFP1_FSI0                            ,
+       RULL(0x00003024), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MREFP1                        ,
+       RULL(0x00000C09), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_0_MRESB0_FSI0                            ,
+       RULL(0x000031D0), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MRESB0                        ,
+       RULL(0x00000C74), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_0_MRESP0_FSI0                            ,
+       RULL(0x000030D0), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MRESP0                        ,
+       RULL(0x00000C34), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MRESP1_FSI0                            ,
+       RULL(0x000030D4), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MRESP1                        ,
+       RULL(0x00000C35), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MRESP2_FSI0                            ,
+       RULL(0x000030D8), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MRESP2                        ,
+       RULL(0x00000C36), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MRESP3_FSI0                            ,
+       RULL(0x000030DC), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MRESP3                        ,
+       RULL(0x00000C37), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MRESP4_FSI0                            ,
+       RULL(0x000030E0), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MRESP4                        ,
+       RULL(0x00000C38), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MRESP5_FSI0                            ,
+       RULL(0x000030E4), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MRESP5                        ,
+       RULL(0x00000C39), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MRESP6_FSI0                            ,
+       RULL(0x000030E8), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MRESP6                        ,
+       RULL(0x00000C3A), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MRESP7_FSI0                            ,
+       RULL(0x000030EC), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MRESP7                        ,
+       RULL(0x00000C3B), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MSCSB0_FSI0                            ,
+       RULL(0x000031D4), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSCSB0                        ,
+       RULL(0x00000C75), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_0_MSENP0_FSI0                            ,
+       RULL(0x00003018), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSENP0                        ,
+       RULL(0x00000C06), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MSIEP0_FSI0                            ,
+       RULL(0x00003030), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSIEP0                        ,
+       RULL(0x00000C0C), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RW );
+
+REG32( PERV_FSI_A_MST_0_MSIEP1_FSI0                            ,
+       RULL(0x00003034), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSIEP1                        ,
+       RULL(0x00000C0D), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MSIEP2_FSI0                            ,
+       RULL(0x00003038), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSIEP2                        ,
+       RULL(0x00000C0E), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MSIEP3_FSI0                            ,
+       RULL(0x0000303C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSIEP3                        ,
+       RULL(0x00000C0F), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MSIEP4_FSI0                            ,
+       RULL(0x00003040), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSIEP4                        ,
+       RULL(0x00000C10), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MSIEP5_FSI0                            ,
+       RULL(0x00003044), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSIEP5                        ,
+       RULL(0x00000C11), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MSIEP6_FSI0                            ,
+       RULL(0x00003048), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSIEP6                        ,
+       RULL(0x00000C12), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MSIEP7_FSI0                            ,
+       RULL(0x0000304C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSIEP7                        ,
+       RULL(0x00000C13), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MSSIEP0_FSI0                           ,
+       RULL(0x00003050), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSSIEP0                       ,
+       RULL(0x00000C14), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_OR );
+
+REG32( PERV_FSI_A_MST_0_MSTAP0_FSI0                            ,
+       RULL(0x000030D0), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSTAP0                        ,
+       RULL(0x00000C34), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_0_MSTAP1_FSI0                            ,
+       RULL(0x000030D4), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSTAP1                        ,
+       RULL(0x00000C35), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_0_MSTAP2_FSI0                            ,
+       RULL(0x000030D8), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSTAP2                        ,
+       RULL(0x00000C36), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_0_MSTAP3_FSI0                            ,
+       RULL(0x000030DC), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSTAP3                        ,
+       RULL(0x00000C37), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_0_MSTAP4_FSI0                            ,
+       RULL(0x000030E0), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSTAP4                        ,
+       RULL(0x00000C38), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_0_MSTAP5_FSI0                            ,
+       RULL(0x000030E4), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSTAP5                        ,
+       RULL(0x00000C39), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_0_MSTAP6_FSI0                            ,
+       RULL(0x000030E8), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSTAP6                        ,
+       RULL(0x00000C3A), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_0_MSTAP7_FSI0                            ,
+       RULL(0x000030EC), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSTAP7                        ,
+       RULL(0x00000C3B), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_0_MVER_FSI0                              ,
+       RULL(0x00003074), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MVER                          ,
+       RULL(0x00000C1D), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MAEB_FSI0                              ,
+       RULL(0x00003470), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MAEB_SCOMFSI0                          ,
+       RULL(0x00000D1C), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MAESP0_FSI0                            ,
+       RULL(0x00003450), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MAESP0_SCOMFSI0                        ,
+       RULL(0x00000D14), SH_UNT_PERV     , SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_1_MAESP1_FSI0                            ,
+       RULL(0x00003454), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MAESP1_SCOMFSI0                        ,
+       RULL(0x00000D15), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MAESP2_FSI0                            ,
+       RULL(0x00003458), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MAESP2_SCOMFSI0                        ,
+       RULL(0x00000D16), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MAESP3_FSI0                            ,
+       RULL(0x0000345C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MAESP3_SCOMFSI0                        ,
+       RULL(0x00000D17), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MAESP4_FSI0                            ,
+       RULL(0x00003460), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MAESP4_SCOMFSI0                        ,
+       RULL(0x00000D18), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MAESP5_FSI0                            ,
+       RULL(0x00003464), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MAESP5_SCOMFSI0                        ,
+       RULL(0x00000D19), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MAESP6_FSI0                            ,
+       RULL(0x00003468), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MAESP6_SCOMFSI0                        ,
+       RULL(0x00000D1A), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MAESP7_FSI0                            ,
+       RULL(0x0000346C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MAESP7_SCOMFSI0                        ,
+       RULL(0x00000D1B), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MATRB0_FSI0                            ,
+       RULL(0x000035D8), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MATRB0_SCOMFSI0                        ,
+       RULL(0x00000D76), SH_UNT_PERV     , SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_1_MCENP0_FSI0                            ,
+       RULL(0x00003420), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MCENP0_SCOMFSI0                        ,
+       RULL(0x00000D08), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MCRSP0_FSI0                            ,
+       RULL(0x00003408), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MCRSP0_SCOMFSI0                        ,
+       RULL(0x00000D02), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MCRSP1_FSI0                            ,
+       RULL(0x0000340C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MCRSP1_SCOMFSI0                        ,
+       RULL(0x00000D03), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MCSIEP0_FSI0                           ,
+       RULL(0x00003470), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MCSIEP0_SCOMFSI0                       ,
+       RULL(0x00000D1C), SH_UNT_PERV     , SH_ACS_SCOMFSI0_CLEAR );
+
+REG32( PERV_FSI_A_MST_1_MDLYR_FSI0                             ,
+       RULL(0x00003404), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MDLYR_SCOMFSI0                         ,
+       RULL(0x00000D01), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MDTRB0_FSI0                            ,
+       RULL(0x000035DC), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MDTRB0_SCOMFSI0                        ,
+       RULL(0x00000D77), SH_UNT_PERV     , SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_1_MECTRL_FSI0                            ,
+       RULL(0x000036E0), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MECTRL_SCOMFSI0                        ,
+       RULL(0x00000DB8), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MENP0_FSI0                             ,
+       RULL(0x00003410), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MENP0_SCOMFSI0                         ,
+       RULL(0x00000D04), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MENP1_FSI0                             ,
+       RULL(0x00003414), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MENP1_SCOMFSI0                         ,
+       RULL(0x00000D05), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MESRB0_FSI0                            ,
+       RULL(0x000035D0), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MESRB0_SCOMFSI0                        ,
+       RULL(0x00000D74), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MLEVP0_FSI0                            ,
+       RULL(0x00003418), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MLEVP0_SCOMFSI0                        ,
+       RULL(0x00000D06), SH_UNT_PERV     , SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_1_MLEVP1_FSI0                            ,
+       RULL(0x0000341C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MLEVP1_SCOMFSI0                        ,
+       RULL(0x00000D07), SH_UNT_PERV     , SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_1_MMODE_FSI0                             ,
+       RULL(0x00003400), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MMODE_SCOMFSI0                         ,
+       RULL(0x00000D00), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MREFP0_FSI0                            ,
+       RULL(0x00003420), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MREFP0_SCOMFSI0                        ,
+       RULL(0x00000D08), SH_UNT_PERV     , SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_1_MREFP1_FSI0                            ,
+       RULL(0x00003424), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MREFP1_SCOMFSI0                        ,
+       RULL(0x00000D09), SH_UNT_PERV     , SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_1_MRESB0_FSI0                            ,
+       RULL(0x000035D0), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MRESB0_SCOMFSI0                        ,
+       RULL(0x00000D74), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_1_MRESP0_FSI0                            ,
+       RULL(0x000034D0), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MRESP0_SCOMFSI0                        ,
+       RULL(0x00000D34), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MRESP1_FSI0                            ,
+       RULL(0x000034D4), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MRESP1_SCOMFSI0                        ,
+       RULL(0x00000D35), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MRESP2_FSI0                            ,
+       RULL(0x000034D8), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MRESP2_SCOMFSI0                        ,
+       RULL(0x00000D36), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MRESP3_FSI0                            ,
+       RULL(0x000034DC), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MRESP3_SCOMFSI0                        ,
+       RULL(0x00000D37), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MRESP4_FSI0                            ,
+       RULL(0x000034E0), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MRESP4_SCOMFSI0                        ,
+       RULL(0x00000D38), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MRESP5_FSI0                            ,
+       RULL(0x000034E4), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MRESP5_SCOMFSI0                        ,
+       RULL(0x00000D39), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MRESP6_FSI0                            ,
+       RULL(0x000034E8), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MRESP6_SCOMFSI0                        ,
+       RULL(0x00000D3A), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MRESP7_FSI0                            ,
+       RULL(0x000034EC), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MRESP7_SCOMFSI0                        ,
+       RULL(0x00000D3B), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MSCSB0_FSI0                            ,
+       RULL(0x000035D4), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MSCSB0_SCOMFSI0                        ,
+       RULL(0x00000D75), SH_UNT_PERV     , SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_1_MSENP0_FSI0                            ,
+       RULL(0x00003418), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MSENP0_SCOMFSI0                        ,
+       RULL(0x00000D06), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MSIEP0_FSI0                            ,
+       RULL(0x00003430), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MSIEP0_SCOMFSI0                        ,
+       RULL(0x00000D0C), SH_UNT_PERV     , SH_ACS_SCOMFSI0_RW );
+
+REG32( PERV_FSI_A_MST_1_MSIEP1_FSI0                            ,
+       RULL(0x00003434), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MSIEP1_SCOMFSI0                        ,
+       RULL(0x00000D0D), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MSIEP2_FSI0                            ,
+       RULL(0x00003438), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MSIEP2_SCOMFSI0                        ,
+       RULL(0x00000D0E), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MSIEP3_FSI0                            ,
+       RULL(0x0000343C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MSIEP3_SCOMFSI0                        ,
+       RULL(0x00000D0F), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MSIEP4_FSI0                            ,
+       RULL(0x00003440), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MSIEP4_SCOMFSI0                        ,
+       RULL(0x00000D10), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MSIEP5_FSI0                            ,
+       RULL(0x00003444), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MSIEP5_SCOMFSI0                        ,
+       RULL(0x00000D11), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MSIEP6_FSI0                            ,
+       RULL(0x00003448), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MSIEP6_SCOMFSI0                        ,
+       RULL(0x00000D12), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MSIEP7_FSI0                            ,
+       RULL(0x0000344C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MSIEP7_SCOMFSI0                        ,
+       RULL(0x00000D13), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MSSIEP0_FSI0                           ,
+       RULL(0x00003450), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MSSIEP0_SCOMFSI0                       ,
+       RULL(0x00000D14), SH_UNT_PERV     , SH_ACS_SCOMFSI0_OR );
+
+REG32( PERV_FSI_A_MST_1_MSTAP0_FSI0                            ,
+       RULL(0x000034D0), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MSTAP0_SCOMFSI0                        ,
+       RULL(0x00000D34), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_1_MSTAP1_FSI0                            ,
+       RULL(0x000034D4), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MSTAP1_SCOMFSI0                        ,
+       RULL(0x00000D35), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_1_MSTAP2_FSI0                            ,
+       RULL(0x000034D8), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MSTAP2_SCOMFSI0                        ,
+       RULL(0x00000D36), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_1_MSTAP3_FSI0                            ,
+       RULL(0x000034DC), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MSTAP3_SCOMFSI0                        ,
+       RULL(0x00000D37), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_1_MSTAP4_FSI0                            ,
+       RULL(0x000034E0), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MSTAP4_SCOMFSI0                        ,
+       RULL(0x00000D38), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_1_MSTAP5_FSI0                            ,
+       RULL(0x000034E4), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MSTAP5_SCOMFSI0                        ,
+       RULL(0x00000D39), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_1_MSTAP6_FSI0                            ,
+       RULL(0x000034E8), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MSTAP6_SCOMFSI0                        ,
+       RULL(0x00000D3A), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_1_MSTAP7_FSI0                            ,
+       RULL(0x000034EC), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MSTAP7_SCOMFSI0                        ,
+       RULL(0x00000D3B), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_1_MVER_FSI0                              ,
+       RULL(0x00003474), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MVER_SCOMFSI0                          ,
+       RULL(0x00000D1D), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_SCI1M_FSI0                                   ,
+       RULL(0x00000820), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SCI2CM_FSI0                                  ,
+       RULL(0x0000082C), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SCISC_FSI0                                   ,
+       RULL(0x00000808), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SCISM_FSI0                                   ,
+       RULL(0x00000814), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SCMBL_FSI0                                   ,
+       RULL(0x00000840), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SCMBR_FSI0                                   ,
+       RULL(0x0000084C), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SCMDT_FSI0                                   ,
+       RULL(0x0000082C), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_SCRSIC0_FSI0                                 ,
+       RULL(0x00000850), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SCRSIC4_FSI0                                 ,
+       RULL(0x00000854), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SCRSIM0_FSI0                                 ,
+       RULL(0x00000858), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SCRSIM4_FSI0                                 ,
+       RULL(0x0000085C), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SCRSIS0_FSI0                                 ,
+       RULL(0x00000860), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SCRSIS4_FSI0                                 ,
+       RULL(0x00000864), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SDATA_FSI0                                   ,
+       RULL(0x00000830), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SDMA_FSI0                                    ,
+       RULL(0x00000804), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SI1M_FSI0                                    ,
+       RULL(0x00000818), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SI1S_FSI0                                    ,
+       RULL(0x0000081C), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SI2M_FSI0                                    ,
+       RULL(0x00000824), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SI2S_FSI0                                    ,
+       RULL(0x00000828), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SIC_FSI0                                     ,
+       RULL(0x00000820), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_SISC_FSI0                                    ,
+       RULL(0x00000808), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_SISM_FSI0                                    ,
+       RULL(0x0000080C), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SISS_FSI0                                    ,
+       RULL(0x00000810), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SLASTD_SRES_FSI0                             ,
+       RULL(0x00000834), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SLBUS_FSI0                                   ,
+       RULL(0x00000830), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_SMBL_FSI0                                    ,
+       RULL(0x00000838), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SMBR_FSI0                                    ,
+       RULL(0x00000844), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SMODE_FSI0                                   ,
+       RULL(0x00000800), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SNML_FSI0                                    ,
+       RULL(0x00000840), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_SNMR_FSI0                                    ,
+       RULL(0x0000084C), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_SOML_FSI0                                    ,
+       RULL(0x0000083C), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SOMR_FSI0                                    ,
+       RULL(0x00000848), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SRSIC0_FSI0                                  ,
+       RULL(0x00000868), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SRSIC4_FSI0                                  ,
+       RULL(0x0000086C), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SRSIM0_FSI0                                  ,
+       RULL(0x00000870), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SRSIM4_FSI0                                  ,
+       RULL(0x00000874), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SRSIS0_FSI0                                  ,
+       RULL(0x00000878), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SRSIS4_FSI0                                  ,
+       RULL(0x0000087C), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SSI1M_FSI0                                   ,
+       RULL(0x0000081C), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_SSI2M_FSI0                                   ,
+       RULL(0x00000828), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_SSISM_FSI0                                   ,
+       RULL(0x00000810), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_SSMBL_FSI0                                   ,
+       RULL(0x0000083C), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_SSMBR_FSI0                                   ,
+       RULL(0x00000848), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_SSTAT_FSI0                                   ,
+       RULL(0x00000814), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_LLMOD_FSI1                                   ,
+       RULL(0x00000900), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_LLSTAT_FSI1                                  ,
+       RULL(0x00000904), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_MST_0_MAEB_FSI1                              ,
+       RULL(0x00003070), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MAEB                          ,
+       RULL(0x00000C1C), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MAESP0_FSI1                            ,
+       RULL(0x00003050), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MAESP0                        ,
+       RULL(0x00000C14), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO );
+
+REG32( PERV_FSI_B_MST_0_MAESP1_FSI1                            ,
+       RULL(0x00003054), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MAESP1                        ,
+       RULL(0x00000C15), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MAESP2_FSI1                            ,
+       RULL(0x00003058), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MAESP2                        ,
+       RULL(0x00000C16), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MAESP3_FSI1                            ,
+       RULL(0x0000305C), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MAESP3                        ,
+       RULL(0x00000C17), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MAESP4_FSI1                            ,
+       RULL(0x00003060), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MAESP4                        ,
+       RULL(0x00000C18), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MAESP5_FSI1                            ,
+       RULL(0x00003064), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MAESP5                        ,
+       RULL(0x00000C19), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MAESP6_FSI1                            ,
+       RULL(0x00003068), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MAESP6                        ,
+       RULL(0x00000C1A), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MAESP7_FSI1                            ,
+       RULL(0x0000306C), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MAESP7                        ,
+       RULL(0x00000C1B), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MATRB0_FSI1                            ,
+       RULL(0x000031D8), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MATRB0                        ,
+       RULL(0x00000C76), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO );
+
+REG32( PERV_FSI_B_MST_0_MCENP0_FSI1                            ,
+       RULL(0x00003020), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MCENP0                        ,
+       RULL(0x00000C08), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MCRSP0_FSI1                            ,
+       RULL(0x00003008), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MCRSP0                        ,
+       RULL(0x00000C02), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MCRSP1_FSI1                            ,
+       RULL(0x0000300C), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MCRSP1                        ,
+       RULL(0x00000C03), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MCSIEP0_FSI1                           ,
+       RULL(0x00003070), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MCSIEP0                       ,
+       RULL(0x00000C1C), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_CLEAR );
+
+REG32( PERV_FSI_B_MST_0_MDLYR_FSI1                             ,
+       RULL(0x00003004), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MDLYR                         ,
+       RULL(0x00000C01), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MDTRB0_FSI1                            ,
+       RULL(0x000031DC), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MDTRB0                        ,
+       RULL(0x00000C77), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO );
+
+REG32( PERV_FSI_B_MST_0_MECTRL_FSI1                            ,
+       RULL(0x000032E0), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MECTRL                        ,
+       RULL(0x00000CB8), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MENP0_FSI1                             ,
+       RULL(0x00003010), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MENP0                         ,
+       RULL(0x00000C04), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MENP1_FSI1                             ,
+       RULL(0x00003014), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MENP1                         ,
+       RULL(0x00000C05), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MESRB0_FSI1                            ,
+       RULL(0x000031D0), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MESRB0                        ,
+       RULL(0x00000C74), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MLEVP0_FSI1                            ,
+       RULL(0x00003018), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MLEVP0                        ,
+       RULL(0x00000C06), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO );
+
+REG32( PERV_FSI_B_MST_0_MLEVP1_FSI1                            ,
+       RULL(0x0000301C), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MLEVP1                        ,
+       RULL(0x00000C07), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO );
+
+REG32( PERV_FSI_B_MST_0_MMODE_FSI1                             ,
+       RULL(0x00003000), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MMODE                         ,
+       RULL(0x00000C00), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MREFP0_FSI1                            ,
+       RULL(0x00003020), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MREFP0                        ,
+       RULL(0x00000C08), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO );
+
+REG32( PERV_FSI_B_MST_0_MREFP1_FSI1                            ,
+       RULL(0x00003024), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MREFP1                        ,
+       RULL(0x00000C09), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO );
+
+REG32( PERV_FSI_B_MST_0_MRESB0_FSI1                            ,
+       RULL(0x000031D0), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MRESB0                        ,
+       RULL(0x00000C74), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_MST_0_MRESP0_FSI1                            ,
+       RULL(0x000030D0), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MRESP0                        ,
+       RULL(0x00000C34), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MRESP1_FSI1                            ,
+       RULL(0x000030D4), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MRESP1                        ,
+       RULL(0x00000C35), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MRESP2_FSI1                            ,
+       RULL(0x000030D8), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MRESP2                        ,
+       RULL(0x00000C36), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MRESP3_FSI1                            ,
+       RULL(0x000030DC), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MRESP3                        ,
+       RULL(0x00000C37), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MRESP4_FSI1                            ,
+       RULL(0x000030E0), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MRESP4                        ,
+       RULL(0x00000C38), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MRESP5_FSI1                            ,
+       RULL(0x000030E4), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MRESP5                        ,
+       RULL(0x00000C39), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MRESP6_FSI1                            ,
+       RULL(0x000030E8), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MRESP6                        ,
+       RULL(0x00000C3A), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MRESP7_FSI1                            ,
+       RULL(0x000030EC), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MRESP7                        ,
+       RULL(0x00000C3B), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MSCSB0_FSI1                            ,
+       RULL(0x000031D4), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSCSB0                        ,
+       RULL(0x00000C75), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO );
+
+REG32( PERV_FSI_B_MST_0_MSENP0_FSI1                            ,
+       RULL(0x00003018), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSENP0                        ,
+       RULL(0x00000C06), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MSIEP0_FSI1                            ,
+       RULL(0x00003030), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSIEP0                        ,
+       RULL(0x00000C0C), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RW );
+
+REG32( PERV_FSI_B_MST_0_MSIEP1_FSI1                            ,
+       RULL(0x00003034), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSIEP1                        ,
+       RULL(0x00000C0D), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MSIEP2_FSI1                            ,
+       RULL(0x00003038), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSIEP2                        ,
+       RULL(0x00000C0E), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MSIEP3_FSI1                            ,
+       RULL(0x0000303C), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSIEP3                        ,
+       RULL(0x00000C0F), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MSIEP4_FSI1                            ,
+       RULL(0x00003040), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSIEP4                        ,
+       RULL(0x00000C10), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MSIEP5_FSI1                            ,
+       RULL(0x00003044), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSIEP5                        ,
+       RULL(0x00000C11), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MSIEP6_FSI1                            ,
+       RULL(0x00003048), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSIEP6                        ,
+       RULL(0x00000C12), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MSIEP7_FSI1                            ,
+       RULL(0x0000304C), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSIEP7                        ,
+       RULL(0x00000C13), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MSSIEP0_FSI1                           ,
+       RULL(0x00003050), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSSIEP0                       ,
+       RULL(0x00000C14), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_OR );
+
+REG32( PERV_FSI_B_MST_0_MSTAP0_FSI1                            ,
+       RULL(0x000030D0), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSTAP0                        ,
+       RULL(0x00000C34), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_MST_0_MSTAP1_FSI1                            ,
+       RULL(0x000030D4), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSTAP1                        ,
+       RULL(0x00000C35), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_MST_0_MSTAP2_FSI1                            ,
+       RULL(0x000030D8), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSTAP2                        ,
+       RULL(0x00000C36), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_MST_0_MSTAP3_FSI1                            ,
+       RULL(0x000030DC), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSTAP3                        ,
+       RULL(0x00000C37), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_MST_0_MSTAP4_FSI1                            ,
+       RULL(0x000030E0), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSTAP4                        ,
+       RULL(0x00000C38), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_MST_0_MSTAP5_FSI1                            ,
+       RULL(0x000030E4), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSTAP5                        ,
+       RULL(0x00000C39), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_MST_0_MSTAP6_FSI1                            ,
+       RULL(0x000030E8), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSTAP6                        ,
+       RULL(0x00000C3A), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_MST_0_MSTAP7_FSI1                            ,
+       RULL(0x000030EC), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSTAP7                        ,
+       RULL(0x00000C3B), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_MST_0_MVER_FSI1                              ,
+       RULL(0x00003074), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MVER                          ,
+       RULL(0x00000C1D), SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_SCI1M_FSI1                                   ,
+       RULL(0x00000820), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SCI2CM_FSI1                                  ,
+       RULL(0x0000082C), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SCISC_FSI1                                   ,
+       RULL(0x00000808), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SCISM_FSI1                                   ,
+       RULL(0x00000814), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SCMBL_FSI1                                   ,
+       RULL(0x00000840), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SCMBR_FSI1                                   ,
+       RULL(0x0000084C), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SCMDT_FSI1                                   ,
+       RULL(0x0000082C), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_SCRSIC0_FSI1                                 ,
+       RULL(0x00000850), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SCRSIC4_FSI1                                 ,
+       RULL(0x00000854), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SCRSIM0_FSI1                                 ,
+       RULL(0x00000858), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SCRSIM4_FSI1                                 ,
+       RULL(0x0000085C), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SCRSIS0_FSI1                                 ,
+       RULL(0x00000860), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SCRSIS4_FSI1                                 ,
+       RULL(0x00000864), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SDATA_FSI1                                   ,
+       RULL(0x00000830), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SDMA_FSI1                                    ,
+       RULL(0x00000804), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SI1M_FSI1                                    ,
+       RULL(0x00000818), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SI1S_FSI1                                    ,
+       RULL(0x0000081C), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SI2M_FSI1                                    ,
+       RULL(0x00000824), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SI2S_FSI1                                    ,
+       RULL(0x00000828), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SIC_FSI1                                     ,
+       RULL(0x00000820), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_SISC_FSI1                                    ,
+       RULL(0x00000808), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_SISM_FSI1                                    ,
+       RULL(0x0000080C), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SISS_FSI1                                    ,
+       RULL(0x00000810), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SLASTD_SRES_FSI1                             ,
+       RULL(0x00000834), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SLBUS_FSI1                                   ,
+       RULL(0x00000830), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_SMBL_FSI1                                    ,
+       RULL(0x00000838), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SMBR_FSI1                                    ,
+       RULL(0x00000844), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SMODE_FSI1                                   ,
+       RULL(0x00000800), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SNML_FSI1                                    ,
+       RULL(0x00000840), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_SNMR_FSI1                                    ,
+       RULL(0x0000084C), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_SOML_FSI1                                    ,
+       RULL(0x0000083C), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SOMR_FSI1                                    ,
+       RULL(0x00000848), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SRSIC0_FSI1                                  ,
+       RULL(0x00000868), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SRSIC4_FSI1                                  ,
+       RULL(0x0000086C), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SRSIM0_FSI1                                  ,
+       RULL(0x00000870), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SRSIM4_FSI1                                  ,
+       RULL(0x00000874), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SRSIS0_FSI1                                  ,
+       RULL(0x00000878), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SRSIS4_FSI1                                  ,
+       RULL(0x0000087C), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SSI1M_FSI1                                   ,
+       RULL(0x0000081C), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_SSI2M_FSI1                                   ,
+       RULL(0x00000828), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_SSISM_FSI1                                   ,
+       RULL(0x00000810), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_SSMBL_FSI1                                   ,
+       RULL(0x0000083C), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_SSMBR_FSI1                                   ,
+       RULL(0x00000848), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_SSTAT_FSI1                                   ,
+       RULL(0x00000814), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_GPWRP_FSI                                          ,
+       RULL(0x0000281F), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_GPWRP_FSI_BYTE                                     ,
+       RULL(0x0000287C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_GPWRP_SCOM                                         ,
+       RULL(0x0005001F), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_GPWRP                                          ,
+       RULL(0x0005001F), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_HANG_PULSE_0_REG                                   ,
+       RULL(0x000F0020), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_HANG_PULSE_0_REG                                ,
+       RULL(0x010F0020), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_HANG_PULSE_0_REG                                ,
+       RULL(0x020F0020), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_HANG_PULSE_0_REG                                ,
+       RULL(0x030F0020), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_HANG_PULSE_0_REG                                ,
+       RULL(0x040F0020), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_HANG_PULSE_0_REG                                ,
+       RULL(0x050F0020), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_HANG_PULSE_0_REG                                ,
+       RULL(0x060F0020), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_HANG_PULSE_0_REG                              ,
+       RULL(0x070F0020), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_HANG_PULSE_0_REG                              ,
+       RULL(0x080F0020), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_HANG_PULSE_0_REG                               ,
+       RULL(0x090F0020), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_HANG_PULSE_0_REG                               ,
+       RULL(0x0C0F0020), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_HANG_PULSE_0_REG                              ,
+       RULL(0x0D0F0020), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_HANG_PULSE_0_REG                              ,
+       RULL(0x0E0F0020), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_HANG_PULSE_0_REG                              ,
+       RULL(0x0F0F0020), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_HANG_PULSE_0_REG                              ,
+       RULL(0x100F0020), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_HANG_PULSE_0_REG                              ,
+       RULL(0x110F0020), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_HANG_PULSE_0_REG                              ,
+       RULL(0x120F0020), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_HANG_PULSE_0_REG                              ,
+       RULL(0x130F0020), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_HANG_PULSE_0_REG                              ,
+       RULL(0x140F0020), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_HANG_PULSE_0_REG                              ,
+       RULL(0x150F0020), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_HANG_PULSE_0_REG                              ,
+       RULL(0x200F0020), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_HANG_PULSE_0_REG                              ,
+       RULL(0x210F0020), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_HANG_PULSE_0_REG                              ,
+       RULL(0x220F0020), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_HANG_PULSE_0_REG                              ,
+       RULL(0x230F0020), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_HANG_PULSE_0_REG                              ,
+       RULL(0x240F0020), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_HANG_PULSE_0_REG                              ,
+       RULL(0x250F0020), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_HANG_PULSE_0_REG                              ,
+       RULL(0x260F0020), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_HANG_PULSE_0_REG                              ,
+       RULL(0x270F0020), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_HANG_PULSE_0_REG                              ,
+       RULL(0x280F0020), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_HANG_PULSE_0_REG                              ,
+       RULL(0x290F0020), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_HANG_PULSE_0_REG                              ,
+       RULL(0x2A0F0020), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_HANG_PULSE_0_REG                              ,
+       RULL(0x2B0F0020), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_HANG_PULSE_0_REG                              ,
+       RULL(0x2C0F0020), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_HANG_PULSE_0_REG                              ,
+       RULL(0x2D0F0020), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_HANG_PULSE_0_REG                              ,
+       RULL(0x2E0F0020), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_HANG_PULSE_0_REG                              ,
+       RULL(0x2F0F0020), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_HANG_PULSE_0_REG                              ,
+       RULL(0x300F0020), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_HANG_PULSE_0_REG                              ,
+       RULL(0x310F0020), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_HANG_PULSE_0_REG                              ,
+       RULL(0x320F0020), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_HANG_PULSE_0_REG                              ,
+       RULL(0x330F0020), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_HANG_PULSE_0_REG                              ,
+       RULL(0x340F0020), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_HANG_PULSE_0_REG                              ,
+       RULL(0x350F0020), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_HANG_PULSE_0_REG                              ,
+       RULL(0x360F0020), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_HANG_PULSE_0_REG                              ,
+       RULL(0x370F0020), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_HANG_PULSE_1_REG                                   ,
+       RULL(0x000F0021), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_HANG_PULSE_1_REG                                ,
+       RULL(0x010F0021), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_HANG_PULSE_1_REG                                ,
+       RULL(0x020F0021), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_HANG_PULSE_1_REG                                ,
+       RULL(0x030F0021), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_HANG_PULSE_1_REG                                ,
+       RULL(0x040F0021), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_HANG_PULSE_1_REG                                ,
+       RULL(0x050F0021), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_HANG_PULSE_1_REG                                ,
+       RULL(0x060F0021), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_HANG_PULSE_1_REG                              ,
+       RULL(0x070F0021), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_HANG_PULSE_1_REG                              ,
+       RULL(0x080F0021), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_HANG_PULSE_1_REG                               ,
+       RULL(0x090F0021), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_HANG_PULSE_1_REG                               ,
+       RULL(0x0C0F0021), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_HANG_PULSE_1_REG                              ,
+       RULL(0x0D0F0021), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_HANG_PULSE_1_REG                              ,
+       RULL(0x0E0F0021), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_HANG_PULSE_1_REG                              ,
+       RULL(0x0F0F0021), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_HANG_PULSE_1_REG                              ,
+       RULL(0x100F0021), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_HANG_PULSE_1_REG                              ,
+       RULL(0x110F0021), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_HANG_PULSE_1_REG                              ,
+       RULL(0x120F0021), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_HANG_PULSE_1_REG                              ,
+       RULL(0x130F0021), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_HANG_PULSE_1_REG                              ,
+       RULL(0x140F0021), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_HANG_PULSE_1_REG                              ,
+       RULL(0x150F0021), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_HANG_PULSE_1_REG                              ,
+       RULL(0x200F0021), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_HANG_PULSE_1_REG                              ,
+       RULL(0x210F0021), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_HANG_PULSE_1_REG                              ,
+       RULL(0x220F0021), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_HANG_PULSE_1_REG                              ,
+       RULL(0x230F0021), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_HANG_PULSE_1_REG                              ,
+       RULL(0x240F0021), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_HANG_PULSE_1_REG                              ,
+       RULL(0x250F0021), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_HANG_PULSE_1_REG                              ,
+       RULL(0x260F0021), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_HANG_PULSE_1_REG                              ,
+       RULL(0x270F0021), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_HANG_PULSE_1_REG                              ,
+       RULL(0x280F0021), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_HANG_PULSE_1_REG                              ,
+       RULL(0x290F0021), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_HANG_PULSE_1_REG                              ,
+       RULL(0x2A0F0021), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_HANG_PULSE_1_REG                              ,
+       RULL(0x2B0F0021), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_HANG_PULSE_1_REG                              ,
+       RULL(0x2C0F0021), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_HANG_PULSE_1_REG                              ,
+       RULL(0x2D0F0021), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_HANG_PULSE_1_REG                              ,
+       RULL(0x2E0F0021), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_HANG_PULSE_1_REG                              ,
+       RULL(0x2F0F0021), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_HANG_PULSE_1_REG                              ,
+       RULL(0x300F0021), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_HANG_PULSE_1_REG                              ,
+       RULL(0x310F0021), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_HANG_PULSE_1_REG                              ,
+       RULL(0x320F0021), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_HANG_PULSE_1_REG                              ,
+       RULL(0x330F0021), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_HANG_PULSE_1_REG                              ,
+       RULL(0x340F0021), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_HANG_PULSE_1_REG                              ,
+       RULL(0x350F0021), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_HANG_PULSE_1_REG                              ,
+       RULL(0x360F0021), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_HANG_PULSE_1_REG                              ,
+       RULL(0x370F0021), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_HANG_PULSE_2_REG                                   ,
+       RULL(0x000F0022), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_HANG_PULSE_2_REG                                ,
+       RULL(0x010F0022), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_HANG_PULSE_2_REG                                ,
+       RULL(0x020F0022), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_HANG_PULSE_2_REG                                ,
+       RULL(0x030F0022), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_HANG_PULSE_2_REG                                ,
+       RULL(0x040F0022), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_HANG_PULSE_2_REG                                ,
+       RULL(0x050F0022), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_HANG_PULSE_2_REG                                ,
+       RULL(0x060F0022), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_HANG_PULSE_2_REG                              ,
+       RULL(0x070F0022), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_HANG_PULSE_2_REG                              ,
+       RULL(0x080F0022), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_HANG_PULSE_2_REG                               ,
+       RULL(0x090F0022), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_HANG_PULSE_2_REG                               ,
+       RULL(0x0C0F0022), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_HANG_PULSE_2_REG                              ,
+       RULL(0x0D0F0022), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_HANG_PULSE_2_REG                              ,
+       RULL(0x0E0F0022), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_HANG_PULSE_2_REG                              ,
+       RULL(0x0F0F0022), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_HANG_PULSE_2_REG                              ,
+       RULL(0x100F0022), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_HANG_PULSE_2_REG                              ,
+       RULL(0x110F0022), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_HANG_PULSE_2_REG                              ,
+       RULL(0x120F0022), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_HANG_PULSE_2_REG                              ,
+       RULL(0x130F0022), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_HANG_PULSE_2_REG                              ,
+       RULL(0x140F0022), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_HANG_PULSE_2_REG                              ,
+       RULL(0x150F0022), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_HANG_PULSE_2_REG                              ,
+       RULL(0x200F0022), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_HANG_PULSE_2_REG                              ,
+       RULL(0x210F0022), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_HANG_PULSE_2_REG                              ,
+       RULL(0x220F0022), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_HANG_PULSE_2_REG                              ,
+       RULL(0x230F0022), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_HANG_PULSE_2_REG                              ,
+       RULL(0x240F0022), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_HANG_PULSE_2_REG                              ,
+       RULL(0x250F0022), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_HANG_PULSE_2_REG                              ,
+       RULL(0x260F0022), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_HANG_PULSE_2_REG                              ,
+       RULL(0x270F0022), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_HANG_PULSE_2_REG                              ,
+       RULL(0x280F0022), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_HANG_PULSE_2_REG                              ,
+       RULL(0x290F0022), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_HANG_PULSE_2_REG                              ,
+       RULL(0x2A0F0022), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_HANG_PULSE_2_REG                              ,
+       RULL(0x2B0F0022), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_HANG_PULSE_2_REG                              ,
+       RULL(0x2C0F0022), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_HANG_PULSE_2_REG                              ,
+       RULL(0x2D0F0022), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_HANG_PULSE_2_REG                              ,
+       RULL(0x2E0F0022), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_HANG_PULSE_2_REG                              ,
+       RULL(0x2F0F0022), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_HANG_PULSE_2_REG                              ,
+       RULL(0x300F0022), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_HANG_PULSE_2_REG                              ,
+       RULL(0x310F0022), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_HANG_PULSE_2_REG                              ,
+       RULL(0x320F0022), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_HANG_PULSE_2_REG                              ,
+       RULL(0x330F0022), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_HANG_PULSE_2_REG                              ,
+       RULL(0x340F0022), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_HANG_PULSE_2_REG                              ,
+       RULL(0x350F0022), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_HANG_PULSE_2_REG                              ,
+       RULL(0x360F0022), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_HANG_PULSE_2_REG                              ,
+       RULL(0x370F0022), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_HANG_PULSE_3_REG                                   ,
+       RULL(0x000F0023), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_HANG_PULSE_3_REG                                ,
+       RULL(0x010F0023), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_HANG_PULSE_3_REG                                ,
+       RULL(0x020F0023), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_HANG_PULSE_3_REG                                ,
+       RULL(0x030F0023), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_HANG_PULSE_3_REG                                ,
+       RULL(0x040F0023), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_HANG_PULSE_3_REG                                ,
+       RULL(0x050F0023), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_HANG_PULSE_3_REG                                ,
+       RULL(0x060F0023), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_HANG_PULSE_3_REG                              ,
+       RULL(0x070F0023), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_HANG_PULSE_3_REG                              ,
+       RULL(0x080F0023), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_HANG_PULSE_3_REG                               ,
+       RULL(0x090F0023), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_HANG_PULSE_3_REG                               ,
+       RULL(0x0C0F0023), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_HANG_PULSE_3_REG                              ,
+       RULL(0x0D0F0023), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_HANG_PULSE_3_REG                              ,
+       RULL(0x0E0F0023), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_HANG_PULSE_3_REG                              ,
+       RULL(0x0F0F0023), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_HANG_PULSE_3_REG                              ,
+       RULL(0x100F0023), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_HANG_PULSE_3_REG                              ,
+       RULL(0x110F0023), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_HANG_PULSE_3_REG                              ,
+       RULL(0x120F0023), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_HANG_PULSE_3_REG                              ,
+       RULL(0x130F0023), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_HANG_PULSE_3_REG                              ,
+       RULL(0x140F0023), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_HANG_PULSE_3_REG                              ,
+       RULL(0x150F0023), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_HANG_PULSE_3_REG                              ,
+       RULL(0x200F0023), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_HANG_PULSE_3_REG                              ,
+       RULL(0x210F0023), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_HANG_PULSE_3_REG                              ,
+       RULL(0x220F0023), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_HANG_PULSE_3_REG                              ,
+       RULL(0x230F0023), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_HANG_PULSE_3_REG                              ,
+       RULL(0x240F0023), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_HANG_PULSE_3_REG                              ,
+       RULL(0x250F0023), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_HANG_PULSE_3_REG                              ,
+       RULL(0x260F0023), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_HANG_PULSE_3_REG                              ,
+       RULL(0x270F0023), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_HANG_PULSE_3_REG                              ,
+       RULL(0x280F0023), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_HANG_PULSE_3_REG                              ,
+       RULL(0x290F0023), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_HANG_PULSE_3_REG                              ,
+       RULL(0x2A0F0023), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_HANG_PULSE_3_REG                              ,
+       RULL(0x2B0F0023), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_HANG_PULSE_3_REG                              ,
+       RULL(0x2C0F0023), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_HANG_PULSE_3_REG                              ,
+       RULL(0x2D0F0023), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_HANG_PULSE_3_REG                              ,
+       RULL(0x2E0F0023), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_HANG_PULSE_3_REG                              ,
+       RULL(0x2F0F0023), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_HANG_PULSE_3_REG                              ,
+       RULL(0x300F0023), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_HANG_PULSE_3_REG                              ,
+       RULL(0x310F0023), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_HANG_PULSE_3_REG                              ,
+       RULL(0x320F0023), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_HANG_PULSE_3_REG                              ,
+       RULL(0x330F0023), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_HANG_PULSE_3_REG                              ,
+       RULL(0x340F0023), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_HANG_PULSE_3_REG                              ,
+       RULL(0x350F0023), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_HANG_PULSE_3_REG                              ,
+       RULL(0x360F0023), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_HANG_PULSE_3_REG                              ,
+       RULL(0x370F0023), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_HANG_PULSE_4_REG                                   ,
+       RULL(0x000F0024), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_HANG_PULSE_4_REG                                ,
+       RULL(0x010F0024), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_HANG_PULSE_4_REG                                ,
+       RULL(0x020F0024), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_HANG_PULSE_4_REG                                ,
+       RULL(0x030F0024), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_HANG_PULSE_4_REG                                ,
+       RULL(0x040F0024), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_HANG_PULSE_4_REG                                ,
+       RULL(0x050F0024), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_HANG_PULSE_4_REG                                ,
+       RULL(0x060F0024), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_HANG_PULSE_4_REG                              ,
+       RULL(0x070F0024), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_HANG_PULSE_4_REG                              ,
+       RULL(0x080F0024), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_HANG_PULSE_4_REG                               ,
+       RULL(0x090F0024), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_HANG_PULSE_4_REG                               ,
+       RULL(0x0C0F0024), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_HANG_PULSE_4_REG                              ,
+       RULL(0x0D0F0024), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_HANG_PULSE_4_REG                              ,
+       RULL(0x0E0F0024), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_HANG_PULSE_4_REG                              ,
+       RULL(0x0F0F0024), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_HANG_PULSE_4_REG                              ,
+       RULL(0x100F0024), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_HANG_PULSE_4_REG                              ,
+       RULL(0x110F0024), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_HANG_PULSE_4_REG                              ,
+       RULL(0x120F0024), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_HANG_PULSE_4_REG                              ,
+       RULL(0x130F0024), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_HANG_PULSE_4_REG                              ,
+       RULL(0x140F0024), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_HANG_PULSE_4_REG                              ,
+       RULL(0x150F0024), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_HANG_PULSE_4_REG                              ,
+       RULL(0x200F0024), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_HANG_PULSE_4_REG                              ,
+       RULL(0x210F0024), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_HANG_PULSE_4_REG                              ,
+       RULL(0x220F0024), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_HANG_PULSE_4_REG                              ,
+       RULL(0x230F0024), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_HANG_PULSE_4_REG                              ,
+       RULL(0x240F0024), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_HANG_PULSE_4_REG                              ,
+       RULL(0x250F0024), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_HANG_PULSE_4_REG                              ,
+       RULL(0x260F0024), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_HANG_PULSE_4_REG                              ,
+       RULL(0x270F0024), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_HANG_PULSE_4_REG                              ,
+       RULL(0x280F0024), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_HANG_PULSE_4_REG                              ,
+       RULL(0x290F0024), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_HANG_PULSE_4_REG                              ,
+       RULL(0x2A0F0024), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_HANG_PULSE_4_REG                              ,
+       RULL(0x2B0F0024), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_HANG_PULSE_4_REG                              ,
+       RULL(0x2C0F0024), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_HANG_PULSE_4_REG                              ,
+       RULL(0x2D0F0024), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_HANG_PULSE_4_REG                              ,
+       RULL(0x2E0F0024), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_HANG_PULSE_4_REG                              ,
+       RULL(0x2F0F0024), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_HANG_PULSE_4_REG                              ,
+       RULL(0x300F0024), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_HANG_PULSE_4_REG                              ,
+       RULL(0x310F0024), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_HANG_PULSE_4_REG                              ,
+       RULL(0x320F0024), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_HANG_PULSE_4_REG                              ,
+       RULL(0x330F0024), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_HANG_PULSE_4_REG                              ,
+       RULL(0x340F0024), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_HANG_PULSE_4_REG                              ,
+       RULL(0x350F0024), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_HANG_PULSE_4_REG                              ,
+       RULL(0x360F0024), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_HANG_PULSE_4_REG                              ,
+       RULL(0x370F0024), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_HANG_PULSE_5_REG                                   ,
+       RULL(0x000F0025), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_HANG_PULSE_5_REG                                ,
+       RULL(0x010F0025), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_HANG_PULSE_5_REG                                ,
+       RULL(0x020F0025), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_HANG_PULSE_5_REG                                ,
+       RULL(0x030F0025), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_HANG_PULSE_5_REG                                ,
+       RULL(0x040F0025), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_HANG_PULSE_5_REG                                ,
+       RULL(0x050F0025), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_HANG_PULSE_5_REG                                ,
+       RULL(0x060F0025), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_HANG_PULSE_5_REG                              ,
+       RULL(0x070F0025), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_HANG_PULSE_5_REG                              ,
+       RULL(0x080F0025), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_HANG_PULSE_5_REG                               ,
+       RULL(0x090F0025), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_HANG_PULSE_5_REG                               ,
+       RULL(0x0C0F0025), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_HANG_PULSE_5_REG                              ,
+       RULL(0x0D0F0025), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_HANG_PULSE_5_REG                              ,
+       RULL(0x0E0F0025), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_HANG_PULSE_5_REG                              ,
+       RULL(0x0F0F0025), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_HANG_PULSE_5_REG                              ,
+       RULL(0x100F0025), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_HANG_PULSE_5_REG                              ,
+       RULL(0x110F0025), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_HANG_PULSE_5_REG                              ,
+       RULL(0x120F0025), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_HANG_PULSE_5_REG                              ,
+       RULL(0x130F0025), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_HANG_PULSE_5_REG                              ,
+       RULL(0x140F0025), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_HANG_PULSE_5_REG                              ,
+       RULL(0x150F0025), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_HANG_PULSE_5_REG                              ,
+       RULL(0x200F0025), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_HANG_PULSE_5_REG                              ,
+       RULL(0x210F0025), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_HANG_PULSE_5_REG                              ,
+       RULL(0x220F0025), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_HANG_PULSE_5_REG                              ,
+       RULL(0x230F0025), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_HANG_PULSE_5_REG                              ,
+       RULL(0x240F0025), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_HANG_PULSE_5_REG                              ,
+       RULL(0x250F0025), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_HANG_PULSE_5_REG                              ,
+       RULL(0x260F0025), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_HANG_PULSE_5_REG                              ,
+       RULL(0x270F0025), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_HANG_PULSE_5_REG                              ,
+       RULL(0x280F0025), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_HANG_PULSE_5_REG                              ,
+       RULL(0x290F0025), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_HANG_PULSE_5_REG                              ,
+       RULL(0x2A0F0025), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_HANG_PULSE_5_REG                              ,
+       RULL(0x2B0F0025), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_HANG_PULSE_5_REG                              ,
+       RULL(0x2C0F0025), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_HANG_PULSE_5_REG                              ,
+       RULL(0x2D0F0025), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_HANG_PULSE_5_REG                              ,
+       RULL(0x2E0F0025), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_HANG_PULSE_5_REG                              ,
+       RULL(0x2F0F0025), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_HANG_PULSE_5_REG                              ,
+       RULL(0x300F0025), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_HANG_PULSE_5_REG                              ,
+       RULL(0x310F0025), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_HANG_PULSE_5_REG                              ,
+       RULL(0x320F0025), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_HANG_PULSE_5_REG                              ,
+       RULL(0x330F0025), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_HANG_PULSE_5_REG                              ,
+       RULL(0x340F0025), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_HANG_PULSE_5_REG                              ,
+       RULL(0x350F0025), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_HANG_PULSE_5_REG                              ,
+       RULL(0x360F0025), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_HANG_PULSE_5_REG                              ,
+       RULL(0x370F0025), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_HANG_PULSE_6_REG                                   ,
+       RULL(0x000F0026), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_HANG_PULSE_6_REG                                ,
+       RULL(0x010F0026), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_HANG_PULSE_6_REG                                ,
+       RULL(0x020F0026), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_HANG_PULSE_6_REG                                ,
+       RULL(0x030F0026), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_HANG_PULSE_6_REG                                ,
+       RULL(0x040F0026), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_HANG_PULSE_6_REG                                ,
+       RULL(0x050F0026), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_HANG_PULSE_6_REG                                ,
+       RULL(0x060F0026), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_HANG_PULSE_6_REG                              ,
+       RULL(0x070F0026), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_HANG_PULSE_6_REG                              ,
+       RULL(0x080F0026), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_HANG_PULSE_6_REG                               ,
+       RULL(0x090F0026), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_HANG_PULSE_6_REG                               ,
+       RULL(0x0C0F0026), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_HANG_PULSE_6_REG                              ,
+       RULL(0x0D0F0026), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_HANG_PULSE_6_REG                              ,
+       RULL(0x0E0F0026), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_HANG_PULSE_6_REG                              ,
+       RULL(0x0F0F0026), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_HANG_PULSE_6_REG                              ,
+       RULL(0x100F0026), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_HANG_PULSE_6_REG                              ,
+       RULL(0x110F0026), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_HANG_PULSE_6_REG                              ,
+       RULL(0x120F0026), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_HANG_PULSE_6_REG                              ,
+       RULL(0x130F0026), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_HANG_PULSE_6_REG                              ,
+       RULL(0x140F0026), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_HANG_PULSE_6_REG                              ,
+       RULL(0x150F0026), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_HANG_PULSE_6_REG                              ,
+       RULL(0x200F0026), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_HANG_PULSE_6_REG                              ,
+       RULL(0x210F0026), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_HANG_PULSE_6_REG                              ,
+       RULL(0x220F0026), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_HANG_PULSE_6_REG                              ,
+       RULL(0x230F0026), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_HANG_PULSE_6_REG                              ,
+       RULL(0x240F0026), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_HANG_PULSE_6_REG                              ,
+       RULL(0x250F0026), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_HANG_PULSE_6_REG                              ,
+       RULL(0x260F0026), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_HANG_PULSE_6_REG                              ,
+       RULL(0x270F0026), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_HANG_PULSE_6_REG                              ,
+       RULL(0x280F0026), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_HANG_PULSE_6_REG                              ,
+       RULL(0x290F0026), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_HANG_PULSE_6_REG                              ,
+       RULL(0x2A0F0026), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_HANG_PULSE_6_REG                              ,
+       RULL(0x2B0F0026), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_HANG_PULSE_6_REG                              ,
+       RULL(0x2C0F0026), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_HANG_PULSE_6_REG                              ,
+       RULL(0x2D0F0026), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_HANG_PULSE_6_REG                              ,
+       RULL(0x2E0F0026), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_HANG_PULSE_6_REG                              ,
+       RULL(0x2F0F0026), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_HANG_PULSE_6_REG                              ,
+       RULL(0x300F0026), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_HANG_PULSE_6_REG                              ,
+       RULL(0x310F0026), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_HANG_PULSE_6_REG                              ,
+       RULL(0x320F0026), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_HANG_PULSE_6_REG                              ,
+       RULL(0x330F0026), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_HANG_PULSE_6_REG                              ,
+       RULL(0x340F0026), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_HANG_PULSE_6_REG                              ,
+       RULL(0x350F0026), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_HANG_PULSE_6_REG                              ,
+       RULL(0x360F0026), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_HANG_PULSE_6_REG                              ,
+       RULL(0x370F0026), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_HEARTBEAT_REG                                      ,
+       RULL(0x000F0018), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_HEARTBEAT_REG                                   ,
+       RULL(0x010F0018), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_HEARTBEAT_REG                                   ,
+       RULL(0x020F0018), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_HEARTBEAT_REG                                   ,
+       RULL(0x030F0018), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_HEARTBEAT_REG                                   ,
+       RULL(0x040F0018), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_HEARTBEAT_REG                                   ,
+       RULL(0x050F0018), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_HEARTBEAT_REG                                   ,
+       RULL(0x060F0018), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_HEARTBEAT_REG                                 ,
+       RULL(0x070F0018), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_HEARTBEAT_REG                                 ,
+       RULL(0x080F0018), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_HEARTBEAT_REG                                  ,
+       RULL(0x090F0018), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_HEARTBEAT_REG                                  ,
+       RULL(0x0C0F0018), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_HEARTBEAT_REG                                 ,
+       RULL(0x0D0F0018), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_HEARTBEAT_REG                                 ,
+       RULL(0x0E0F0018), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_HEARTBEAT_REG                                 ,
+       RULL(0x0F0F0018), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_HEARTBEAT_REG                                 ,
+       RULL(0x100F0018), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_HEARTBEAT_REG                                 ,
+       RULL(0x110F0018), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_HEARTBEAT_REG                                 ,
+       RULL(0x120F0018), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_HEARTBEAT_REG                                 ,
+       RULL(0x130F0018), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_HEARTBEAT_REG                                 ,
+       RULL(0x140F0018), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_HEARTBEAT_REG                                 ,
+       RULL(0x150F0018), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_HEARTBEAT_REG                                 ,
+       RULL(0x200F0018), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_HEARTBEAT_REG                                 ,
+       RULL(0x210F0018), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_HEARTBEAT_REG                                 ,
+       RULL(0x220F0018), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_HEARTBEAT_REG                                 ,
+       RULL(0x230F0018), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_HEARTBEAT_REG                                 ,
+       RULL(0x240F0018), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_HEARTBEAT_REG                                 ,
+       RULL(0x250F0018), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_HEARTBEAT_REG                                 ,
+       RULL(0x260F0018), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_HEARTBEAT_REG                                 ,
+       RULL(0x270F0018), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_HEARTBEAT_REG                                 ,
+       RULL(0x280F0018), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_HEARTBEAT_REG                                 ,
+       RULL(0x290F0018), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_HEARTBEAT_REG                                 ,
+       RULL(0x2A0F0018), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_HEARTBEAT_REG                                 ,
+       RULL(0x2B0F0018), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_HEARTBEAT_REG                                 ,
+       RULL(0x2C0F0018), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_HEARTBEAT_REG                                 ,
+       RULL(0x2D0F0018), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_HEARTBEAT_REG                                 ,
+       RULL(0x2E0F0018), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_HEARTBEAT_REG                                 ,
+       RULL(0x2F0F0018), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_HEARTBEAT_REG                                 ,
+       RULL(0x300F0018), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_HEARTBEAT_REG                                 ,
+       RULL(0x310F0018), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_HEARTBEAT_REG                                 ,
+       RULL(0x320F0018), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_HEARTBEAT_REG                                 ,
+       RULL(0x330F0018), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_HEARTBEAT_REG                                 ,
+       RULL(0x340F0018), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_HEARTBEAT_REG                                 ,
+       RULL(0x350F0018), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_HEARTBEAT_REG                                 ,
+       RULL(0x360F0018), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_HEARTBEAT_REG                                 ,
+       RULL(0x370F0018), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_HOST_MASK_REG                                      ,
+       RULL(0x000F0033), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_HOST_MASK_REG                                  ,
+       RULL(0x000F0033), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_IGNORE_PAR_REG                                     ,
+       RULL(0x000F001C), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_IGNORE_PAR_REG                                 ,
+       RULL(0x000F001C), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_0_FSII2C_IMM_RESET_ERR                             ,
+       RULL(0x00001808), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSII2C_IMM_RESET_ERR                               ,
+       RULL(0x00001808), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PERV_0_FSII2C_IMM_RESET_I2C                             ,
+       RULL(0x00001807), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM      );
+REG32( PERV_FSII2C_IMM_RESET_I2C                               ,
+       RULL(0x00001807), SH_UNT_PERV_FSII2C, SH_ACS_SCOM      );
+
+REG64( PERV_0_FSII2C_IMM_RESET_S_SCL                           ,
+       RULL(0x0000180B), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM      );
+REG32( PERV_FSII2C_IMM_RESET_S_SCL                             ,
+       RULL(0x0000180B), SH_UNT_PERV_FSII2C, SH_ACS_SCOM      );
+
+REG64( PERV_0_FSII2C_IMM_RESET_S_SDA                           ,
+       RULL(0x0000180D), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM      );
+REG32( PERV_FSII2C_IMM_RESET_S_SDA                             ,
+       RULL(0x0000180D), SH_UNT_PERV_FSII2C, SH_ACS_SCOM      );
+
+REG64( PERV_0_FSII2C_IMM_SET_S_SCL                             ,
+       RULL(0x00001809), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM      );
+REG32( PERV_FSII2C_IMM_SET_S_SCL                               ,
+       RULL(0x00001809), SH_UNT_PERV_FSII2C, SH_ACS_SCOM      );
+
+REG64( PERV_0_FSII2C_IMM_SET_S_SDA                             ,
+       RULL(0x0000180C), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM      );
+REG32( PERV_FSII2C_IMM_SET_S_SDA                               ,
+       RULL(0x0000180C), SH_UNT_PERV_FSII2C, SH_ACS_SCOM      );
+
+REG64( PERV_INJECT_REG                                         ,
+       RULL(0x00050011), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_INJECT_REG                                      ,
+       RULL(0x01050011), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_INJECT_REG                                      ,
+       RULL(0x02050011), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_INJECT_REG                                      ,
+       RULL(0x03050011), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_INJECT_REG                                      ,
+       RULL(0x04050011), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_INJECT_REG                                      ,
+       RULL(0x05050011), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_INJECT_REG                                      ,
+       RULL(0x06050011), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_INJECT_REG                                    ,
+       RULL(0x07050011), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_INJECT_REG                                    ,
+       RULL(0x08050011), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_INJECT_REG                                     ,
+       RULL(0x09050011), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_INJECT_REG                                     ,
+       RULL(0x0C050011), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_INJECT_REG                                    ,
+       RULL(0x0D050011), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_INJECT_REG                                    ,
+       RULL(0x0E050011), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_INJECT_REG                                    ,
+       RULL(0x0F050011), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_INJECT_REG                                    ,
+       RULL(0x10050011), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_INJECT_REG                                    ,
+       RULL(0x11050011), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_INJECT_REG                                    ,
+       RULL(0x12050011), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_INJECT_REG                                    ,
+       RULL(0x13050011), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_INJECT_REG                                    ,
+       RULL(0x14050011), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_INJECT_REG                                    ,
+       RULL(0x15050011), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_INJECT_REG                                    ,
+       RULL(0x20050011), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_INJECT_REG                                    ,
+       RULL(0x21050011), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_INJECT_REG                                    ,
+       RULL(0x22050011), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_INJECT_REG                                    ,
+       RULL(0x23050011), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_INJECT_REG                                    ,
+       RULL(0x24050011), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_INJECT_REG                                    ,
+       RULL(0x25050011), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_INJECT_REG                                    ,
+       RULL(0x26050011), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_INJECT_REG                                    ,
+       RULL(0x27050011), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_INJECT_REG                                    ,
+       RULL(0x28050011), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_INJECT_REG                                    ,
+       RULL(0x29050011), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_INJECT_REG                                    ,
+       RULL(0x2A050011), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_INJECT_REG                                    ,
+       RULL(0x2B050011), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_INJECT_REG                                    ,
+       RULL(0x2C050011), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_INJECT_REG                                    ,
+       RULL(0x2D050011), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_INJECT_REG                                    ,
+       RULL(0x2E050011), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_INJECT_REG                                    ,
+       RULL(0x2F050011), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_INJECT_REG                                    ,
+       RULL(0x30050011), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_INJECT_REG                                    ,
+       RULL(0x31050011), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_INJECT_REG                                    ,
+       RULL(0x32050011), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_INJECT_REG                                    ,
+       RULL(0x33050011), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_INJECT_REG                                    ,
+       RULL(0x34050011), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_INJECT_REG                                    ,
+       RULL(0x35050011), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_INJECT_REG                                    ,
+       RULL(0x36050011), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_INJECT_REG                                    ,
+       RULL(0x37050011), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG32( PERV_FSI2PIB_INTERRUPT_FSI                              ,
+       RULL(0x0000100B), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI       );
+REG32( PERV_FSI2PIB_INTERRUPT_FSI_BYTE                         ,
+       RULL(0x0000102C), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE  );
+
+REG64( PERV_INTERRUPT1_REG                                     ,
+       RULL(0x000F0020), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_INTERRUPT1_REG_OR                                  ,
+       RULL(0x000F0021), SH_UNT_PERV     , SH_ACS_SCOM1_OR  );
+REG64( PERV_INTERRUPT1_REG_AND                                 ,
+       RULL(0x000F0022), SH_UNT_PERV     , SH_ACS_SCOM2_AND );
+REG64( PERV_PIB_INTERRUPT1_REG                                 ,
+       RULL(0x000F0020), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_INTERRUPT1_REG_OR                              ,
+       RULL(0x000F0021), SH_UNT_PERV_0   , SH_ACS_SCOM1_OR  );
+REG64( PERV_PIB_INTERRUPT1_REG_AND                             ,
+       RULL(0x000F0022), SH_UNT_PERV_0   , SH_ACS_SCOM2_AND );
+
+REG64( PERV_INTERRUPT2_REG                                     ,
+       RULL(0x000F0023), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_INTERRUPT2_REG_OR                                  ,
+       RULL(0x000F0024), SH_UNT_PERV     , SH_ACS_SCOM1_OR  );
+REG64( PERV_INTERRUPT2_REG_AND                                 ,
+       RULL(0x000F0025), SH_UNT_PERV     , SH_ACS_SCOM2_AND );
+REG64( PERV_PIB_INTERRUPT2_REG                                 ,
+       RULL(0x000F0023), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_INTERRUPT2_REG_OR                              ,
+       RULL(0x000F0024), SH_UNT_PERV_0   , SH_ACS_SCOM1_OR  );
+REG64( PERV_PIB_INTERRUPT2_REG_AND                             ,
+       RULL(0x000F0025), SH_UNT_PERV_0   , SH_ACS_SCOM2_AND );
+
+REG64( PERV_INTERRUPT3_REG                                     ,
+       RULL(0x000F0026), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_INTERRUPT3_REG_OR                                  ,
+       RULL(0x000F0027), SH_UNT_PERV     , SH_ACS_SCOM1_OR  );
+REG64( PERV_INTERRUPT3_REG_AND                                 ,
+       RULL(0x000F0028), SH_UNT_PERV     , SH_ACS_SCOM2_AND );
+REG64( PERV_PIB_INTERRUPT3_REG                                 ,
+       RULL(0x000F0026), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_INTERRUPT3_REG_OR                              ,
+       RULL(0x000F0027), SH_UNT_PERV_0   , SH_ACS_SCOM1_OR  );
+REG64( PERV_PIB_INTERRUPT3_REG_AND                             ,
+       RULL(0x000F0028), SH_UNT_PERV_0   , SH_ACS_SCOM2_AND );
+
+REG64( PERV_INTERRUPT4_REG                                     ,
+       RULL(0x000F0029), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_INTERRUPT4_REG_OR                                  ,
+       RULL(0x000F002A), SH_UNT_PERV     , SH_ACS_SCOM1_OR  );
+REG64( PERV_INTERRUPT4_REG_AND                                 ,
+       RULL(0x000F002B), SH_UNT_PERV     , SH_ACS_SCOM2_AND );
+REG64( PERV_PIB_INTERRUPT4_REG                                 ,
+       RULL(0x000F0029), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_INTERRUPT4_REG_OR                              ,
+       RULL(0x000F002A), SH_UNT_PERV_0   , SH_ACS_SCOM1_OR  );
+REG64( PERV_PIB_INTERRUPT4_REG_AND                             ,
+       RULL(0x000F002B), SH_UNT_PERV_0   , SH_ACS_SCOM2_AND );
+
+REG64( PERV_0_FSII2C_INTERRUPTS                                ,
+       RULL(0x00001806), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM      );
+REG32( PERV_FSII2C_INTERRUPTS                                  ,
+       RULL(0x00001806), SH_UNT_PERV_FSII2C, SH_ACS_SCOM      );
+
+REG64( PERV_0_FSII2C_INTERRUPT_COND                            ,
+       RULL(0x00001805), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM      );
+REG32( PERV_FSII2C_INTERRUPT_COND                              ,
+       RULL(0x00001805), SH_UNT_PERV_FSII2C, SH_ACS_SCOM      );
+
+REG64( PERV_INTERRUPT_CONF_REG                                 ,
+       RULL(0x000F002F), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_INTERRUPT_CONF_REG_WOR                             ,
+       RULL(0x000F0030), SH_UNT_PERV     , SH_ACS_SCOM1_WOR );
+REG64( PERV_INTERRUPT_CONF_REG_WAND                            ,
+       RULL(0x000F0031), SH_UNT_PERV     , SH_ACS_SCOM2_WAND );
+REG64( PERV_PIB_INTERRUPT_CONF_REG                             ,
+       RULL(0x000F002F), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_INTERRUPT_CONF_REG_WOR                         ,
+       RULL(0x000F0030), SH_UNT_PERV_0   , SH_ACS_SCOM1_WOR );
+REG64( PERV_PIB_INTERRUPT_CONF_REG_WAND                        ,
+       RULL(0x000F0031), SH_UNT_PERV_0   , SH_ACS_SCOM2_WAND );
+
+REG64( PERV_INTERRUPT_HOLD_REG                                 ,
+       RULL(0x000F0032), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_INTERRUPT_HOLD_REG                             ,
+       RULL(0x000F0032), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_0_FSII2C_INTERRUPT_MASK_REGISTER                   ,
+       RULL(0x00001804), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM_RW   );
+REG64( PERV_0_FSII2C_INTERRUPT_MASK_REGISTER_OR                ,
+       RULL(0x00001805), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM1_OR  );
+REG64( PERV_0_FSII2C_INTERRUPT_MASK_REGISTER_AND               ,
+       RULL(0x00001806), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM2_AND );
+REG32( PERV_FSII2C_INTERRUPT_MASK_REGISTER                     ,
+       RULL(0x00001804), SH_UNT_PERV_FSII2C, SH_ACS_SCOM_RW   );
+REG32( PERV_FSII2C_INTERRUPT_MASK_REGISTER_OR                  ,
+       RULL(0x00001805), SH_UNT_PERV_FSII2C, SH_ACS_SCOM1_OR  );
+REG32( PERV_FSII2C_INTERRUPT_MASK_REGISTER_AND                 ,
+       RULL(0x00001806), SH_UNT_PERV_FSII2C, SH_ACS_SCOM2_AND );
+
+REG64( PERV_INTERRUPT_TYPE_MASK_REG                            ,
+       RULL(0x000F002C), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_INTERRUPT_TYPE_MASK_REG_WOR                        ,
+       RULL(0x000F002D), SH_UNT_PERV     , SH_ACS_SCOM1_WOR );
+REG64( PERV_INTERRUPT_TYPE_MASK_REG_WAND                       ,
+       RULL(0x000F002E), SH_UNT_PERV     , SH_ACS_SCOM2_WAND );
+REG64( PERV_PIB_INTERRUPT_TYPE_MASK_REG                        ,
+       RULL(0x000F002C), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_INTERRUPT_TYPE_MASK_REG_WOR                    ,
+       RULL(0x000F002D), SH_UNT_PERV_0   , SH_ACS_SCOM1_WOR );
+REG64( PERV_PIB_INTERRUPT_TYPE_MASK_REG_WAND                   ,
+       RULL(0x000F002E), SH_UNT_PERV_0   , SH_ACS_SCOM2_WAND );
+
+REG64( PERV_INTERRUPT_TYPE_REG                                 ,
+       RULL(0x000F001A), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_INTERRUPT_TYPE_REG                             ,
+       RULL(0x000F001A), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_LOCAL_FIR_ACTION0                                  ,
+       RULL(0x00040010), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_LOCAL_FIR_ACTION0                               ,
+       RULL(0x01040010), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_LOCAL_FIR_ACTION0                               ,
+       RULL(0x02040010), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_LOCAL_FIR_ACTION0                               ,
+       RULL(0x03040010), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_LOCAL_FIR_ACTION0                               ,
+       RULL(0x04040010), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_LOCAL_FIR_ACTION0                               ,
+       RULL(0x05040010), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_LOCAL_FIR_ACTION0                               ,
+       RULL(0x06040010), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_LOCAL_FIR_ACTION0                             ,
+       RULL(0x07040010), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_LOCAL_FIR_ACTION0                             ,
+       RULL(0x08040010), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_LOCAL_FIR_ACTION0                              ,
+       RULL(0x09040010), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_LOCAL_FIR_ACTION0                              ,
+       RULL(0x0C040010), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_LOCAL_FIR_ACTION0                             ,
+       RULL(0x0D040010), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_LOCAL_FIR_ACTION0                             ,
+       RULL(0x0E040010), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_LOCAL_FIR_ACTION0                             ,
+       RULL(0x0F040010), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_LOCAL_FIR_ACTION0                             ,
+       RULL(0x10040010), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_LOCAL_FIR_ACTION0                             ,
+       RULL(0x11040010), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_LOCAL_FIR_ACTION0                             ,
+       RULL(0x12040010), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_LOCAL_FIR_ACTION0                             ,
+       RULL(0x13040010), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_LOCAL_FIR_ACTION0                             ,
+       RULL(0x14040010), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_LOCAL_FIR_ACTION0                             ,
+       RULL(0x15040010), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_LOCAL_FIR_ACTION0                             ,
+       RULL(0x20040010), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_LOCAL_FIR_ACTION0                             ,
+       RULL(0x21040010), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_LOCAL_FIR_ACTION0                             ,
+       RULL(0x22040010), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_LOCAL_FIR_ACTION0                             ,
+       RULL(0x23040010), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_LOCAL_FIR_ACTION0                             ,
+       RULL(0x24040010), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_LOCAL_FIR_ACTION0                             ,
+       RULL(0x25040010), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_LOCAL_FIR_ACTION0                             ,
+       RULL(0x26040010), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_LOCAL_FIR_ACTION0                             ,
+       RULL(0x27040010), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_LOCAL_FIR_ACTION0                             ,
+       RULL(0x28040010), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_LOCAL_FIR_ACTION0                             ,
+       RULL(0x29040010), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_LOCAL_FIR_ACTION0                             ,
+       RULL(0x2A040010), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_LOCAL_FIR_ACTION0                             ,
+       RULL(0x2B040010), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_LOCAL_FIR_ACTION0                             ,
+       RULL(0x2C040010), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_LOCAL_FIR_ACTION0                             ,
+       RULL(0x2D040010), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_LOCAL_FIR_ACTION0                             ,
+       RULL(0x2E040010), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_LOCAL_FIR_ACTION0                             ,
+       RULL(0x2F040010), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_LOCAL_FIR_ACTION0                             ,
+       RULL(0x30040010), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_LOCAL_FIR_ACTION0                             ,
+       RULL(0x31040010), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_LOCAL_FIR_ACTION0                             ,
+       RULL(0x32040010), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_LOCAL_FIR_ACTION0                             ,
+       RULL(0x33040010), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_LOCAL_FIR_ACTION0                             ,
+       RULL(0x34040010), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_LOCAL_FIR_ACTION0                             ,
+       RULL(0x35040010), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_LOCAL_FIR_ACTION0                             ,
+       RULL(0x36040010), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_LOCAL_FIR_ACTION0                             ,
+       RULL(0x37040010), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_LOCAL_FIR_ACTION1                                  ,
+       RULL(0x00040011), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_LOCAL_FIR_ACTION1                               ,
+       RULL(0x01040011), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_LOCAL_FIR_ACTION1                               ,
+       RULL(0x02040011), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_LOCAL_FIR_ACTION1                               ,
+       RULL(0x03040011), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_LOCAL_FIR_ACTION1                               ,
+       RULL(0x04040011), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_LOCAL_FIR_ACTION1                               ,
+       RULL(0x05040011), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_LOCAL_FIR_ACTION1                               ,
+       RULL(0x06040011), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_LOCAL_FIR_ACTION1                             ,
+       RULL(0x07040011), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_LOCAL_FIR_ACTION1                             ,
+       RULL(0x08040011), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_LOCAL_FIR_ACTION1                              ,
+       RULL(0x09040011), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_LOCAL_FIR_ACTION1                              ,
+       RULL(0x0C040011), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_LOCAL_FIR_ACTION1                             ,
+       RULL(0x0D040011), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_LOCAL_FIR_ACTION1                             ,
+       RULL(0x0E040011), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_LOCAL_FIR_ACTION1                             ,
+       RULL(0x0F040011), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_LOCAL_FIR_ACTION1                             ,
+       RULL(0x10040011), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_LOCAL_FIR_ACTION1                             ,
+       RULL(0x11040011), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_LOCAL_FIR_ACTION1                             ,
+       RULL(0x12040011), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_LOCAL_FIR_ACTION1                             ,
+       RULL(0x13040011), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_LOCAL_FIR_ACTION1                             ,
+       RULL(0x14040011), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_LOCAL_FIR_ACTION1                             ,
+       RULL(0x15040011), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_LOCAL_FIR_ACTION1                             ,
+       RULL(0x20040011), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_LOCAL_FIR_ACTION1                             ,
+       RULL(0x21040011), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_LOCAL_FIR_ACTION1                             ,
+       RULL(0x22040011), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_LOCAL_FIR_ACTION1                             ,
+       RULL(0x23040011), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_LOCAL_FIR_ACTION1                             ,
+       RULL(0x24040011), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_LOCAL_FIR_ACTION1                             ,
+       RULL(0x25040011), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_LOCAL_FIR_ACTION1                             ,
+       RULL(0x26040011), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_LOCAL_FIR_ACTION1                             ,
+       RULL(0x27040011), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_LOCAL_FIR_ACTION1                             ,
+       RULL(0x28040011), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_LOCAL_FIR_ACTION1                             ,
+       RULL(0x29040011), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_LOCAL_FIR_ACTION1                             ,
+       RULL(0x2A040011), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_LOCAL_FIR_ACTION1                             ,
+       RULL(0x2B040011), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_LOCAL_FIR_ACTION1                             ,
+       RULL(0x2C040011), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_LOCAL_FIR_ACTION1                             ,
+       RULL(0x2D040011), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_LOCAL_FIR_ACTION1                             ,
+       RULL(0x2E040011), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_LOCAL_FIR_ACTION1                             ,
+       RULL(0x2F040011), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_LOCAL_FIR_ACTION1                             ,
+       RULL(0x30040011), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_LOCAL_FIR_ACTION1                             ,
+       RULL(0x31040011), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_LOCAL_FIR_ACTION1                             ,
+       RULL(0x32040011), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_LOCAL_FIR_ACTION1                             ,
+       RULL(0x33040011), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_LOCAL_FIR_ACTION1                             ,
+       RULL(0x34040011), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_LOCAL_FIR_ACTION1                             ,
+       RULL(0x35040011), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_LOCAL_FIR_ACTION1                             ,
+       RULL(0x36040011), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_LOCAL_FIR_ACTION1                             ,
+       RULL(0x37040011), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_LOCAL_FIR_MASK                                     ,
+       RULL(0x0004000D), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_LOCAL_FIR_MASK                                  ,
+       RULL(0x0104000D), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_LOCAL_FIR_MASK_AND                                 ,
+       RULL(0x0004000E), SH_UNT_PERV_1   , SH_ACS_SCOM1_AND );
+REG64( PERV_TP_LOCAL_FIR_MASK_AND                              ,
+       RULL(0x0104000E), SH_UNT_PERV_1   , SH_ACS_SCOM1_AND );
+REG64( PERV_LOCAL_FIR_MASK_OR                                  ,
+       RULL(0x0004000F), SH_UNT_PERV_1   , SH_ACS_SCOM2_OR  );
+REG64( PERV_TP_LOCAL_FIR_MASK_OR                               ,
+       RULL(0x0104000F), SH_UNT_PERV_1   , SH_ACS_SCOM2_OR  );
+REG64( PERV_N0_LOCAL_FIR_MASK                                  ,
+       RULL(0x0204000D), SH_UNT_PERV_2   , SH_ACS_SCOM_RW   );
+REG64( PERV_N0_LOCAL_FIR_MASK_AND                              ,
+       RULL(0x0204000E), SH_UNT_PERV_2   , SH_ACS_SCOM1_AND );
+REG64( PERV_N0_LOCAL_FIR_MASK_OR                               ,
+       RULL(0x0204000F), SH_UNT_PERV_2   , SH_ACS_SCOM2_OR  );
+REG64( PERV_N1_LOCAL_FIR_MASK                                  ,
+       RULL(0x0304000D), SH_UNT_PERV_3   , SH_ACS_SCOM_RW   );
+REG64( PERV_N1_LOCAL_FIR_MASK_AND                              ,
+       RULL(0x0304000E), SH_UNT_PERV_3   , SH_ACS_SCOM1_AND );
+REG64( PERV_N1_LOCAL_FIR_MASK_OR                               ,
+       RULL(0x0304000F), SH_UNT_PERV_3   , SH_ACS_SCOM2_OR  );
+REG64( PERV_N2_LOCAL_FIR_MASK                                  ,
+       RULL(0x0404000D), SH_UNT_PERV_4   , SH_ACS_SCOM_RW   );
+REG64( PERV_N2_LOCAL_FIR_MASK_AND                              ,
+       RULL(0x0404000E), SH_UNT_PERV_4   , SH_ACS_SCOM1_AND );
+REG64( PERV_N2_LOCAL_FIR_MASK_OR                               ,
+       RULL(0x0404000F), SH_UNT_PERV_4   , SH_ACS_SCOM2_OR  );
+REG64( PERV_N3_LOCAL_FIR_MASK                                  ,
+       RULL(0x0504000D), SH_UNT_PERV_5   , SH_ACS_SCOM_RW   );
+REG64( PERV_N3_LOCAL_FIR_MASK_AND                              ,
+       RULL(0x0504000E), SH_UNT_PERV_5   , SH_ACS_SCOM1_AND );
+REG64( PERV_N3_LOCAL_FIR_MASK_OR                               ,
+       RULL(0x0504000F), SH_UNT_PERV_5   , SH_ACS_SCOM2_OR  );
+REG64( PERV_XB_LOCAL_FIR_MASK                                  ,
+       RULL(0x0604000D), SH_UNT_PERV_6   , SH_ACS_SCOM_RW   );
+REG64( PERV_XB_LOCAL_FIR_MASK_AND                              ,
+       RULL(0x0604000E), SH_UNT_PERV_6   , SH_ACS_SCOM1_AND );
+REG64( PERV_XB_LOCAL_FIR_MASK_OR                               ,
+       RULL(0x0604000F), SH_UNT_PERV_6   , SH_ACS_SCOM2_OR  );
+REG64( PERV_MC01_LOCAL_FIR_MASK                                ,
+       RULL(0x0704000D), SH_UNT_PERV_7   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC01_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x0704000E), SH_UNT_PERV_7   , SH_ACS_SCOM1_AND );
+REG64( PERV_MC01_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x0704000F), SH_UNT_PERV_7   , SH_ACS_SCOM2_OR  );
+REG64( PERV_MC23_LOCAL_FIR_MASK                                ,
+       RULL(0x0804000D), SH_UNT_PERV_8   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC23_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x0804000E), SH_UNT_PERV_8   , SH_ACS_SCOM1_AND );
+REG64( PERV_MC23_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x0804000F), SH_UNT_PERV_8   , SH_ACS_SCOM2_OR  );
+REG64( PERV_OB0_LOCAL_FIR_MASK                                 ,
+       RULL(0x0904000D), SH_UNT_PERV_9   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB0_LOCAL_FIR_MASK_AND                             ,
+       RULL(0x0904000E), SH_UNT_PERV_9   , SH_ACS_SCOM1_AND );
+REG64( PERV_OB0_LOCAL_FIR_MASK_OR                              ,
+       RULL(0x0904000F), SH_UNT_PERV_9   , SH_ACS_SCOM2_OR  );
+REG64( PERV_OB3_LOCAL_FIR_MASK                                 ,
+       RULL(0x0C04000D), SH_UNT_PERV_12  , SH_ACS_SCOM_RW   );
+REG64( PERV_OB3_LOCAL_FIR_MASK_AND                             ,
+       RULL(0x0C04000E), SH_UNT_PERV_12  , SH_ACS_SCOM1_AND );
+REG64( PERV_OB3_LOCAL_FIR_MASK_OR                              ,
+       RULL(0x0C04000F), SH_UNT_PERV_12  , SH_ACS_SCOM2_OR  );
+REG64( PERV_PCI0_LOCAL_FIR_MASK                                ,
+       RULL(0x0D04000D), SH_UNT_PERV_13  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI0_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x0D04000E), SH_UNT_PERV_13  , SH_ACS_SCOM1_AND );
+REG64( PERV_PCI0_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x0D04000F), SH_UNT_PERV_13  , SH_ACS_SCOM2_OR  );
+REG64( PERV_PCI1_LOCAL_FIR_MASK                                ,
+       RULL(0x0E04000D), SH_UNT_PERV_14  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI1_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x0E04000E), SH_UNT_PERV_14  , SH_ACS_SCOM1_AND );
+REG64( PERV_PCI1_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x0E04000F), SH_UNT_PERV_14  , SH_ACS_SCOM2_OR  );
+REG64( PERV_PCI2_LOCAL_FIR_MASK                                ,
+       RULL(0x0F04000D), SH_UNT_PERV_15  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI2_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x0F04000E), SH_UNT_PERV_15  , SH_ACS_SCOM1_AND );
+REG64( PERV_PCI2_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x0F04000F), SH_UNT_PERV_15  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP00_LOCAL_FIR_MASK                                ,
+       RULL(0x1004000D), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x1004000E), SH_UNT_PERV_16  , SH_ACS_SCOM1_AND );
+REG64( PERV_EP00_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x1004000F), SH_UNT_PERV_16  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP01_LOCAL_FIR_MASK                                ,
+       RULL(0x1104000D), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x1104000E), SH_UNT_PERV_17  , SH_ACS_SCOM1_AND );
+REG64( PERV_EP01_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x1104000F), SH_UNT_PERV_17  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP02_LOCAL_FIR_MASK                                ,
+       RULL(0x1204000D), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x1204000E), SH_UNT_PERV_18  , SH_ACS_SCOM1_AND );
+REG64( PERV_EP02_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x1204000F), SH_UNT_PERV_18  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP03_LOCAL_FIR_MASK                                ,
+       RULL(0x1304000D), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x1304000E), SH_UNT_PERV_19  , SH_ACS_SCOM1_AND );
+REG64( PERV_EP03_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x1304000F), SH_UNT_PERV_19  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP04_LOCAL_FIR_MASK                                ,
+       RULL(0x1404000D), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x1404000E), SH_UNT_PERV_20  , SH_ACS_SCOM1_AND );
+REG64( PERV_EP04_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x1404000F), SH_UNT_PERV_20  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP05_LOCAL_FIR_MASK                                ,
+       RULL(0x1504000D), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x1504000E), SH_UNT_PERV_21  , SH_ACS_SCOM1_AND );
+REG64( PERV_EP05_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x1504000F), SH_UNT_PERV_21  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC00_LOCAL_FIR_MASK                                ,
+       RULL(0x2004000D), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x2004000E), SH_UNT_PERV_32  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC00_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x2004000F), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_LOCAL_FIR_MASK                                ,
+       RULL(0x2104000D), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x2104000E), SH_UNT_PERV_33  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC01_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x2104000F), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_LOCAL_FIR_MASK                                ,
+       RULL(0x2204000D), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x2204000E), SH_UNT_PERV_34  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC02_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x2204000F), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_LOCAL_FIR_MASK                                ,
+       RULL(0x2304000D), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x2304000E), SH_UNT_PERV_35  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC03_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x2304000F), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_LOCAL_FIR_MASK                                ,
+       RULL(0x2404000D), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x2404000E), SH_UNT_PERV_36  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC04_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x2404000F), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_LOCAL_FIR_MASK                                ,
+       RULL(0x2504000D), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x2504000E), SH_UNT_PERV_37  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC05_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x2504000F), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_LOCAL_FIR_MASK                                ,
+       RULL(0x2604000D), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x2604000E), SH_UNT_PERV_38  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC06_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x2604000F), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_LOCAL_FIR_MASK                                ,
+       RULL(0x2704000D), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x2704000E), SH_UNT_PERV_39  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC07_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x2704000F), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_LOCAL_FIR_MASK                                ,
+       RULL(0x2804000D), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x2804000E), SH_UNT_PERV_40  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC08_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x2804000F), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_LOCAL_FIR_MASK                                ,
+       RULL(0x2904000D), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x2904000E), SH_UNT_PERV_41  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC09_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x2904000F), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_LOCAL_FIR_MASK                                ,
+       RULL(0x2A04000D), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x2A04000E), SH_UNT_PERV_42  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC10_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x2A04000F), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_LOCAL_FIR_MASK                                ,
+       RULL(0x2B04000D), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x2B04000E), SH_UNT_PERV_43  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC11_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x2B04000F), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_LOCAL_FIR_MASK                                ,
+       RULL(0x2C04000D), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x2C04000E), SH_UNT_PERV_44  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC12_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x2C04000F), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_LOCAL_FIR_MASK                                ,
+       RULL(0x2D04000D), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x2D04000E), SH_UNT_PERV_45  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC13_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x2D04000F), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_LOCAL_FIR_MASK                                ,
+       RULL(0x2E04000D), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x2E04000E), SH_UNT_PERV_46  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC14_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x2E04000F), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_LOCAL_FIR_MASK                                ,
+       RULL(0x2F04000D), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x2F04000E), SH_UNT_PERV_47  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC15_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x2F04000F), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_LOCAL_FIR_MASK                                ,
+       RULL(0x3004000D), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x3004000E), SH_UNT_PERV_48  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC16_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x3004000F), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_LOCAL_FIR_MASK                                ,
+       RULL(0x3104000D), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x3104000E), SH_UNT_PERV_49  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC17_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x3104000F), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_LOCAL_FIR_MASK                                ,
+       RULL(0x3204000D), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x3204000E), SH_UNT_PERV_50  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC18_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x3204000F), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_LOCAL_FIR_MASK                                ,
+       RULL(0x3304000D), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x3304000E), SH_UNT_PERV_51  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC19_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x3304000F), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_LOCAL_FIR_MASK                                ,
+       RULL(0x3404000D), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x3404000E), SH_UNT_PERV_52  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC20_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x3404000F), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_LOCAL_FIR_MASK                                ,
+       RULL(0x3504000D), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x3504000E), SH_UNT_PERV_53  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC21_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x3504000F), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_LOCAL_FIR_MASK                                ,
+       RULL(0x3604000D), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x3604000E), SH_UNT_PERV_54  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC22_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x3604000F), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_LOCAL_FIR_MASK                                ,
+       RULL(0x3704000D), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_LOCAL_FIR_MASK_AND                            ,
+       RULL(0x3704000E), SH_UNT_PERV_55  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC23_LOCAL_FIR_MASK_OR                             ,
+       RULL(0x3704000F), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_LSTAT                                              ,
+       RULL(0x00030002), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_LSTAT                                          ,
+       RULL(0x00030002), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+
+REG32( PERV_M1A_DATA_AREA_0_FSI                                ,
+       RULL(0x00002840), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_0_FSI_BYTE                           ,
+       RULL(0x00002900), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_0_SCOM                               ,
+       RULL(0x00050040), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_0                                ,
+       RULL(0x00050040), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_1_FSI                                ,
+       RULL(0x00002841), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_1_FSI_BYTE                           ,
+       RULL(0x00002904), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_1_SCOM                               ,
+       RULL(0x00050041), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_1                                ,
+       RULL(0x00050041), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_10_FSI                               ,
+       RULL(0x0000284A), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_10_FSI_BYTE                          ,
+       RULL(0x00002928), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_10_SCOM                              ,
+       RULL(0x0005004A), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_10                               ,
+       RULL(0x0005004A), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_11_FSI                               ,
+       RULL(0x0000284B), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_11_FSI_BYTE                          ,
+       RULL(0x0000292C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_11_SCOM                              ,
+       RULL(0x0005004B), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_11                               ,
+       RULL(0x0005004B), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_12_FSI                               ,
+       RULL(0x0000284C), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_12_FSI_BYTE                          ,
+       RULL(0x00002930), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_12_SCOM                              ,
+       RULL(0x0005004C), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_12                               ,
+       RULL(0x0005004C), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_13_FSI                               ,
+       RULL(0x0000284D), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_13_FSI_BYTE                          ,
+       RULL(0x00002934), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_13_SCOM                              ,
+       RULL(0x0005004D), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_13                               ,
+       RULL(0x0005004D), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_14_FSI                               ,
+       RULL(0x0000284E), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_14_FSI_BYTE                          ,
+       RULL(0x00002938), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_14_SCOM                              ,
+       RULL(0x0005004E), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_14                               ,
+       RULL(0x0005004E), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_15_FSI                               ,
+       RULL(0x0000284F), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_15_FSI_BYTE                          ,
+       RULL(0x0000293C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_15_SCOM                              ,
+       RULL(0x0005004F), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_15                               ,
+       RULL(0x0005004F), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_2_FSI                                ,
+       RULL(0x00002842), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_2_FSI_BYTE                           ,
+       RULL(0x00002908), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_2_SCOM                               ,
+       RULL(0x00050042), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_2                                ,
+       RULL(0x00050042), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_3_FSI                                ,
+       RULL(0x00002843), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_3_FSI_BYTE                           ,
+       RULL(0x0000290C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_3_SCOM                               ,
+       RULL(0x00050043), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_3                                ,
+       RULL(0x00050043), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_4_FSI                                ,
+       RULL(0x00002844), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_4_FSI_BYTE                           ,
+       RULL(0x00002910), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_4_SCOM                               ,
+       RULL(0x00050044), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_4                                ,
+       RULL(0x00050044), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_5_FSI                                ,
+       RULL(0x00002845), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_5_FSI_BYTE                           ,
+       RULL(0x00002914), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_5_SCOM                               ,
+       RULL(0x00050045), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_5                                ,
+       RULL(0x00050045), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_6_FSI                                ,
+       RULL(0x00002846), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_6_FSI_BYTE                           ,
+       RULL(0x00002918), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_6_SCOM                               ,
+       RULL(0x00050046), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_6                                ,
+       RULL(0x00050046), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_7_FSI                                ,
+       RULL(0x00002847), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_7_FSI_BYTE                           ,
+       RULL(0x0000291C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_7_SCOM                               ,
+       RULL(0x00050047), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_7                                ,
+       RULL(0x00050047), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_8_FSI                                ,
+       RULL(0x00002848), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_8_FSI_BYTE                           ,
+       RULL(0x00002920), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_8_SCOM                               ,
+       RULL(0x00050048), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_8                                ,
+       RULL(0x00050048), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_9_FSI                                ,
+       RULL(0x00002849), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_9_FSI_BYTE                           ,
+       RULL(0x00002924), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_9_SCOM                               ,
+       RULL(0x00050049), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_9                                ,
+       RULL(0x00050049), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_0_FSI                                ,
+       RULL(0x00002880), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_0_FSI_BYTE                           ,
+       RULL(0x00002A00), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_0_SCOM                               ,
+       RULL(0x00050080), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_0                                ,
+       RULL(0x00050080), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_1_FSI                                ,
+       RULL(0x00002881), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_1_FSI_BYTE                           ,
+       RULL(0x00002A04), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_1_SCOM                               ,
+       RULL(0x00050081), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_1                                ,
+       RULL(0x00050081), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_10_FSI                               ,
+       RULL(0x0000288A), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_10_FSI_BYTE                          ,
+       RULL(0x00002A28), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_10_SCOM                              ,
+       RULL(0x0005008A), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_10                               ,
+       RULL(0x0005008A), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_11_FSI                               ,
+       RULL(0x0000288B), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_11_FSI_BYTE                          ,
+       RULL(0x00002A2C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_11_SCOM                              ,
+       RULL(0x0005008B), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_11                               ,
+       RULL(0x0005008B), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_12_FSI                               ,
+       RULL(0x0000288C), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_12_FSI_BYTE                          ,
+       RULL(0x00002A30), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_12_SCOM                              ,
+       RULL(0x0005008C), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_12                               ,
+       RULL(0x0005008C), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_13_FSI                               ,
+       RULL(0x0000288D), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_13_FSI_BYTE                          ,
+       RULL(0x00002A34), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_13_SCOM                              ,
+       RULL(0x0005008D), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_13                               ,
+       RULL(0x0005008D), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_14_FSI                               ,
+       RULL(0x0000288E), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_14_FSI_BYTE                          ,
+       RULL(0x00002A38), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_14_SCOM                              ,
+       RULL(0x0005008E), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_14                               ,
+       RULL(0x0005008E), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_15_FSI                               ,
+       RULL(0x0000288F), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_15_FSI_BYTE                          ,
+       RULL(0x00002A3C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_15_SCOM                              ,
+       RULL(0x0005008F), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_15                               ,
+       RULL(0x0005008F), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_2_FSI                                ,
+       RULL(0x00002882), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_2_FSI_BYTE                           ,
+       RULL(0x00002A08), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_2_SCOM                               ,
+       RULL(0x00050082), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_2                                ,
+       RULL(0x00050082), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_3_FSI                                ,
+       RULL(0x00002883), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_3_FSI_BYTE                           ,
+       RULL(0x00002A0C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_3_SCOM                               ,
+       RULL(0x00050083), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_3                                ,
+       RULL(0x00050083), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_4_FSI                                ,
+       RULL(0x00002884), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_4_FSI_BYTE                           ,
+       RULL(0x00002A10), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_4_SCOM                               ,
+       RULL(0x00050084), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_4                                ,
+       RULL(0x00050084), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_5_FSI                                ,
+       RULL(0x00002885), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_5_FSI_BYTE                           ,
+       RULL(0x00002A14), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_5_SCOM                               ,
+       RULL(0x00050085), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_5                                ,
+       RULL(0x00050085), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_6_FSI                                ,
+       RULL(0x00002886), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_6_FSI_BYTE                           ,
+       RULL(0x00002A18), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_6_SCOM                               ,
+       RULL(0x00050086), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_6                                ,
+       RULL(0x00050086), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_7_FSI                                ,
+       RULL(0x00002887), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_7_FSI_BYTE                           ,
+       RULL(0x00002A1C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_7_SCOM                               ,
+       RULL(0x00050087), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_7                                ,
+       RULL(0x00050087), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_8_FSI                                ,
+       RULL(0x00002888), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_8_FSI_BYTE                           ,
+       RULL(0x00002A20), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_8_SCOM                               ,
+       RULL(0x00050088), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_8                                ,
+       RULL(0x00050088), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_9_FSI                                ,
+       RULL(0x00002889), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_9_FSI_BYTE                           ,
+       RULL(0x00002A24), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_9_SCOM                               ,
+       RULL(0x00050089), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_9                                ,
+       RULL(0x00050089), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_0_FSI                                ,
+       RULL(0x000028C0), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_0_FSI_BYTE                           ,
+       RULL(0x00002B00), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_0_SCOM                               ,
+       RULL(0x000500C0), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_0                                ,
+       RULL(0x000500C0), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_1_FSI                                ,
+       RULL(0x000028C1), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_1_FSI_BYTE                           ,
+       RULL(0x00002B04), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_1_SCOM                               ,
+       RULL(0x000500C1), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_1                                ,
+       RULL(0x000500C1), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_10_FSI                               ,
+       RULL(0x000028CA), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_10_FSI_BYTE                          ,
+       RULL(0x00002B28), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_10_SCOM                              ,
+       RULL(0x000500CA), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_10                               ,
+       RULL(0x000500CA), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_11_FSI                               ,
+       RULL(0x000028CB), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_11_FSI_BYTE                          ,
+       RULL(0x00002B2C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_11_SCOM                              ,
+       RULL(0x000500CB), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_11                               ,
+       RULL(0x000500CB), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_12_FSI                               ,
+       RULL(0x000028CC), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_12_FSI_BYTE                          ,
+       RULL(0x00002B30), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_12_SCOM                              ,
+       RULL(0x000500CC), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_12                               ,
+       RULL(0x000500CC), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_13_FSI                               ,
+       RULL(0x000028CD), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_13_FSI_BYTE                          ,
+       RULL(0x00002B34), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_13_SCOM                              ,
+       RULL(0x000500CD), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_13                               ,
+       RULL(0x000500CD), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_14_FSI                               ,
+       RULL(0x000028CE), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_14_FSI_BYTE                          ,
+       RULL(0x00002B38), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_14_SCOM                              ,
+       RULL(0x000500CE), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_14                               ,
+       RULL(0x000500CE), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_15_FSI                               ,
+       RULL(0x000028CF), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_15_FSI_BYTE                          ,
+       RULL(0x00002B3C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_15_SCOM                              ,
+       RULL(0x000500CF), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_15                               ,
+       RULL(0x000500CF), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_2_FSI                                ,
+       RULL(0x000028C2), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_2_FSI_BYTE                           ,
+       RULL(0x00002B08), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_2_SCOM                               ,
+       RULL(0x000500C2), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_2                                ,
+       RULL(0x000500C2), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_3_FSI                                ,
+       RULL(0x000028C3), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_3_FSI_BYTE                           ,
+       RULL(0x00002B0C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_3_SCOM                               ,
+       RULL(0x000500C3), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_3                                ,
+       RULL(0x000500C3), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_4_FSI                                ,
+       RULL(0x000028C4), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_4_FSI_BYTE                           ,
+       RULL(0x00002B10), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_4_SCOM                               ,
+       RULL(0x000500C4), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_4                                ,
+       RULL(0x000500C4), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_5_FSI                                ,
+       RULL(0x000028C5), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_5_FSI_BYTE                           ,
+       RULL(0x00002B14), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_5_SCOM                               ,
+       RULL(0x000500C5), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_5                                ,
+       RULL(0x000500C5), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_6_FSI                                ,
+       RULL(0x000028C6), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_6_FSI_BYTE                           ,
+       RULL(0x00002B18), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_6_SCOM                               ,
+       RULL(0x000500C6), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_6                                ,
+       RULL(0x000500C6), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_7_FSI                                ,
+       RULL(0x000028C7), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_7_FSI_BYTE                           ,
+       RULL(0x00002B1C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_7_SCOM                               ,
+       RULL(0x000500C7), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_7                                ,
+       RULL(0x000500C7), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_8_FSI                                ,
+       RULL(0x000028C8), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_8_FSI_BYTE                           ,
+       RULL(0x00002B20), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_8_SCOM                               ,
+       RULL(0x000500C8), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_8                                ,
+       RULL(0x000500C8), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_9_FSI                                ,
+       RULL(0x000028C9), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_9_FSI_BYTE                           ,
+       RULL(0x00002B24), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_9_SCOM                               ,
+       RULL(0x000500C9), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_9                                ,
+       RULL(0x000500C9), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_0_FSI                                ,
+       RULL(0x00002900), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_0_FSI_BYTE                           ,
+       RULL(0x00002C00), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_0_SCOM                               ,
+       RULL(0x00050100), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_0                                ,
+       RULL(0x00050100), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_1_FSI                                ,
+       RULL(0x00002901), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_1_FSI_BYTE                           ,
+       RULL(0x00002C04), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_1_SCOM                               ,
+       RULL(0x00050101), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_1                                ,
+       RULL(0x00050101), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_10_FSI                               ,
+       RULL(0x0000290A), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_10_FSI_BYTE                          ,
+       RULL(0x00002C28), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_10_SCOM                              ,
+       RULL(0x0005010A), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_10                               ,
+       RULL(0x0005010A), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_11_FSI                               ,
+       RULL(0x0000290B), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_11_FSI_BYTE                          ,
+       RULL(0x00002C2C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_11_SCOM                              ,
+       RULL(0x0005010B), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_11                               ,
+       RULL(0x0005010B), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_12_FSI                               ,
+       RULL(0x0000290C), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_12_FSI_BYTE                          ,
+       RULL(0x00002C30), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_12_SCOM                              ,
+       RULL(0x0005010C), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_12                               ,
+       RULL(0x0005010C), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_13_FSI                               ,
+       RULL(0x0000290D), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_13_FSI_BYTE                          ,
+       RULL(0x00002C34), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_13_SCOM                              ,
+       RULL(0x0005010D), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_13                               ,
+       RULL(0x0005010D), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_14_FSI                               ,
+       RULL(0x0000290E), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_14_FSI_BYTE                          ,
+       RULL(0x00002C38), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_14_SCOM                              ,
+       RULL(0x0005010E), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_14                               ,
+       RULL(0x0005010E), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_15_FSI                               ,
+       RULL(0x0000290F), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_15_FSI_BYTE                          ,
+       RULL(0x00002C3C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_15_SCOM                              ,
+       RULL(0x0005010F), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_15                               ,
+       RULL(0x0005010F), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_2_FSI                                ,
+       RULL(0x00002902), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_2_FSI_BYTE                           ,
+       RULL(0x00002C08), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_2_SCOM                               ,
+       RULL(0x00050102), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_2                                ,
+       RULL(0x00050102), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_3_FSI                                ,
+       RULL(0x00002903), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_3_FSI_BYTE                           ,
+       RULL(0x00002C0C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_3_SCOM                               ,
+       RULL(0x00050103), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_3                                ,
+       RULL(0x00050103), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_4_FSI                                ,
+       RULL(0x00002904), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_4_FSI_BYTE                           ,
+       RULL(0x00002C10), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_4_SCOM                               ,
+       RULL(0x00050104), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_4                                ,
+       RULL(0x00050104), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_5_FSI                                ,
+       RULL(0x00002905), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_5_FSI_BYTE                           ,
+       RULL(0x00002C14), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_5_SCOM                               ,
+       RULL(0x00050105), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_5                                ,
+       RULL(0x00050105), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_6_FSI                                ,
+       RULL(0x00002906), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_6_FSI_BYTE                           ,
+       RULL(0x00002C18), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_6_SCOM                               ,
+       RULL(0x00050106), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_6                                ,
+       RULL(0x00050106), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_7_FSI                                ,
+       RULL(0x00002907), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_7_FSI_BYTE                           ,
+       RULL(0x00002C1C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_7_SCOM                               ,
+       RULL(0x00050107), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_7                                ,
+       RULL(0x00050107), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_8_FSI                                ,
+       RULL(0x00002908), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_8_FSI_BYTE                           ,
+       RULL(0x00002C20), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_8_SCOM                               ,
+       RULL(0x00050108), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_8                                ,
+       RULL(0x00050108), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_9_FSI                                ,
+       RULL(0x00002909), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_9_FSI_BYTE                           ,
+       RULL(0x00002C24), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_9_SCOM                               ,
+       RULL(0x00050109), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_9                                ,
+       RULL(0x00050109), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_MAILBOX_1_HEADER_COMMAND_0_A_FSI                   ,
+       RULL(0x00002821), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_0_A_FSI_BYTE              ,
+       RULL(0x00002884), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_0_A_SCOM                  ,
+       RULL(0x00050021), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_MAILBOX_1_HEADER_COMMAND_0_A                   ,
+       RULL(0x00050021), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG32( PERV_MAILBOX_1_HEADER_COMMAND_0_B_FSI                   ,
+       RULL(0x00002825), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_0_B_FSI_BYTE              ,
+       RULL(0x00002894), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_0_B_SCOM                  ,
+       RULL(0x00050025), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_MAILBOX_1_HEADER_COMMAND_0_B                   ,
+       RULL(0x00050025), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+
+REG32( PERV_MAILBOX_1_HEADER_COMMAND_1_A_FSI                   ,
+       RULL(0x00002822), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_1_A_FSI_BYTE              ,
+       RULL(0x00002888), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_1_A_SCOM                  ,
+       RULL(0x00050022), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_MAILBOX_1_HEADER_COMMAND_1_A                   ,
+       RULL(0x00050022), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG32( PERV_MAILBOX_1_HEADER_COMMAND_1_B_FSI                   ,
+       RULL(0x00002826), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_1_B_FSI_BYTE              ,
+       RULL(0x00002898), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_1_B_SCOM                  ,
+       RULL(0x00050026), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_MAILBOX_1_HEADER_COMMAND_1_B                   ,
+       RULL(0x00050026), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+
+REG32( PERV_MAILBOX_1_HEADER_COMMAND_2_A_FSI                   ,
+       RULL(0x00002823), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_2_A_FSI_BYTE              ,
+       RULL(0x0000288C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_2_A_SCOM                  ,
+       RULL(0x00050023), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_MAILBOX_1_HEADER_COMMAND_2_A                   ,
+       RULL(0x00050023), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG32( PERV_MAILBOX_1_HEADER_COMMAND_2_B_FSI                   ,
+       RULL(0x00002827), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_2_B_FSI_BYTE              ,
+       RULL(0x0000289C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_2_B_SCOM                  ,
+       RULL(0x00050027), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_MAILBOX_1_HEADER_COMMAND_2_B                   ,
+       RULL(0x00050027), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+
+REG32( PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_FSI    ,
+       RULL(0x00002833), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_FSI_BYTE ,
+       RULL(0x000028CC), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_SCOM   ,
+       RULL(0x00050033), SH_UNT_PERV     , SH_ACS_SCOM_WOR  );
+REG64( PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_SCOM1  ,
+       RULL(0x00050034), SH_UNT_PERV     , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_PIB_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_WOR ,
+       RULL(0x00050033), SH_UNT_PERV_0   , SH_ACS_SCOM_WOR  );
+REG64( PERV_PIB_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_CLEAR ,
+       RULL(0x00050034), SH_UNT_PERV_0   , SH_ACS_SCOM1_CLEAR );
+
+REG32( PERV_MAILBOX_2_HEADER_COMMAND_0_A_FSI                   ,
+       RULL(0x00002829), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_0_A_FSI_BYTE              ,
+       RULL(0x000028A4), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_0_A_SCOM                  ,
+       RULL(0x00050029), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_MAILBOX_2_HEADER_COMMAND_0_A                   ,
+       RULL(0x00050029), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG32( PERV_MAILBOX_2_HEADER_COMMAND_0_B_FSI                   ,
+       RULL(0x0000282D), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_0_B_FSI_BYTE              ,
+       RULL(0x000028B4), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_0_B_SCOM                  ,
+       RULL(0x0005002D), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_MAILBOX_2_HEADER_COMMAND_0_B                   ,
+       RULL(0x0005002D), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+
+REG32( PERV_MAILBOX_2_HEADER_COMMAND_1_A_FSI                   ,
+       RULL(0x0000282A), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_1_A_FSI_BYTE              ,
+       RULL(0x000028A8), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_1_A_SCOM                  ,
+       RULL(0x0005002A), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_MAILBOX_2_HEADER_COMMAND_1_A                   ,
+       RULL(0x0005002A), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG32( PERV_MAILBOX_2_HEADER_COMMAND_1_B_FSI                   ,
+       RULL(0x0000282E), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_1_B_FSI_BYTE              ,
+       RULL(0x000028B8), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_1_B_SCOM                  ,
+       RULL(0x0005002E), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_MAILBOX_2_HEADER_COMMAND_1_B                   ,
+       RULL(0x0005002E), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+
+REG32( PERV_MAILBOX_2_HEADER_COMMAND_2_A_FSI                   ,
+       RULL(0x0000282B), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_2_A_FSI_BYTE              ,
+       RULL(0x000028AC), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_2_A_SCOM                  ,
+       RULL(0x0005002B), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_MAILBOX_2_HEADER_COMMAND_2_A                   ,
+       RULL(0x0005002B), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG32( PERV_MAILBOX_2_HEADER_COMMAND_2_B_FSI                   ,
+       RULL(0x0000282F), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_2_B_FSI_BYTE              ,
+       RULL(0x000028BC), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_2_B_SCOM                  ,
+       RULL(0x0005002F), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_MAILBOX_2_HEADER_COMMAND_2_B                   ,
+       RULL(0x0005002F), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+
+REG32( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_FSI          ,
+       RULL(0x00002831), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_FSI_BYTE     ,
+       RULL(0x000028C4), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_SCOM         ,
+       RULL(0x00050031), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS          ,
+       RULL(0x00050031), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_FSI             ,
+       RULL(0x00002832), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_FSI_BYTE        ,
+       RULL(0x000028C8), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_SCOM            ,
+       RULL(0x00050032), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT             ,
+       RULL(0x00050032), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_FSI          ,
+       RULL(0x00002830), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_FSI_BYTE     ,
+       RULL(0x000028C0), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_SCOM         ,
+       RULL(0x00050030), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS          ,
+       RULL(0x00050030), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_FSI             ,
+       RULL(0x00002835), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_FSI_BYTE        ,
+       RULL(0x000028D4), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_SCOM            ,
+       RULL(0x00050035), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT             ,
+       RULL(0x00050035), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_FSI      ,
+       RULL(0x00002836), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_FSI0     ,
+       RULL(0x00002837), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_FSI_BYTE ,
+       RULL(0x000028D8), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_SCOM     ,
+       RULL(0x00050036), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1      ,
+       RULL(0x00050036), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+
+REG64( PERV_MCAST_COMP_MASK_REG                                ,
+       RULL(0x000F0017), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MCAST_COMP_MASK_REG                            ,
+       RULL(0x000F0017), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_MCAST_COMP_REG                                     ,
+       RULL(0x000F0015), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MCAST_COMP_REG                                 ,
+       RULL(0x000F0015), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_MCAST_COMP_VAL_REG                                 ,
+       RULL(0x000F0016), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MCAST_COMP_VAL_REG                             ,
+       RULL(0x000F0016), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_MCAST_GRP_0_SLAVES_REG                             ,
+       RULL(0x000F0000), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MCAST_GRP_0_SLAVES_REG                         ,
+       RULL(0x000F0000), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_MCAST_GRP_1_SLAVES_REG                             ,
+       RULL(0x000F0001), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MCAST_GRP_1_SLAVES_REG                         ,
+       RULL(0x000F0001), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_MCAST_GRP_2_SLAVES_REG                             ,
+       RULL(0x000F0002), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MCAST_GRP_2_SLAVES_REG                         ,
+       RULL(0x000F0002), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_MCAST_GRP_3_SLAVES_REG                             ,
+       RULL(0x000F0003), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MCAST_GRP_3_SLAVES_REG                         ,
+       RULL(0x000F0003), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_MCAST_GRP_4_SLAVES_REG                             ,
+       RULL(0x000F0004), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MCAST_GRP_4_SLAVES_REG                         ,
+       RULL(0x000F0004), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_MCAST_GRP_5_SLAVES_REG                             ,
+       RULL(0x000F0005), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MCAST_GRP_5_SLAVES_REG                         ,
+       RULL(0x000F0005), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_MCAST_GRP_6_SLAVES_REG                             ,
+       RULL(0x000F0006), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MCAST_GRP_6_SLAVES_REG                         ,
+       RULL(0x000F0006), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_MIB_XIICAC                                         ,
+       RULL(0x00000419), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_MIB_XIICAC                                     ,
+       RULL(0x00000419), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+
+REG64( PERV_MIB_XIMEM                                          ,
+       RULL(0x00000417), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_MIB_XIMEM                                      ,
+       RULL(0x00000417), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+
+REG64( PERV_MIB_XISGB                                          ,
+       RULL(0x00000418), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_MIB_XISGB                                      ,
+       RULL(0x00000418), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+
+REG64( PERV_MIB_XISIB                                          ,
+       RULL(0x00000416), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_MIB_XISIB                                      ,
+       RULL(0x00000416), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+
+REG64( PERV_MODE_REG                                           ,
+       RULL(0x00040008), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_MODE_REG                                        ,
+       RULL(0x01040008), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_MODE_REG                                        ,
+       RULL(0x02040008), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_MODE_REG                                        ,
+       RULL(0x03040008), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_MODE_REG                                        ,
+       RULL(0x04040008), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_MODE_REG                                        ,
+       RULL(0x05040008), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_MODE_REG                                        ,
+       RULL(0x06040008), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_MODE_REG                                      ,
+       RULL(0x07040008), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_MODE_REG                                      ,
+       RULL(0x08040008), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_MODE_REG                                       ,
+       RULL(0x09040008), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_MODE_REG                                       ,
+       RULL(0x0C040008), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_MODE_REG                                      ,
+       RULL(0x0D040008), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_MODE_REG                                      ,
+       RULL(0x0E040008), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_MODE_REG                                      ,
+       RULL(0x0F040008), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_MODE_REG                                      ,
+       RULL(0x10040008), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_MODE_REG                                      ,
+       RULL(0x11040008), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_MODE_REG                                      ,
+       RULL(0x12040008), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_MODE_REG                                      ,
+       RULL(0x13040008), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_MODE_REG                                      ,
+       RULL(0x14040008), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_MODE_REG                                      ,
+       RULL(0x15040008), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_MODE_REG                                      ,
+       RULL(0x20040008), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_MODE_REG                                      ,
+       RULL(0x21040008), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_MODE_REG                                      ,
+       RULL(0x22040008), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_MODE_REG                                      ,
+       RULL(0x23040008), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_MODE_REG                                      ,
+       RULL(0x24040008), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_MODE_REG                                      ,
+       RULL(0x25040008), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_MODE_REG                                      ,
+       RULL(0x26040008), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_MODE_REG                                      ,
+       RULL(0x27040008), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_MODE_REG                                      ,
+       RULL(0x28040008), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_MODE_REG                                      ,
+       RULL(0x29040008), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_MODE_REG                                      ,
+       RULL(0x2A040008), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_MODE_REG                                      ,
+       RULL(0x2B040008), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_MODE_REG                                      ,
+       RULL(0x2C040008), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_MODE_REG                                      ,
+       RULL(0x2D040008), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_MODE_REG                                      ,
+       RULL(0x2E040008), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_MODE_REG                                      ,
+       RULL(0x2F040008), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_MODE_REG                                      ,
+       RULL(0x30040008), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_MODE_REG                                      ,
+       RULL(0x31040008), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_MODE_REG                                      ,
+       RULL(0x32040008), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_MODE_REG                                      ,
+       RULL(0x33040008), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_MODE_REG                                      ,
+       RULL(0x34040008), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_MODE_REG                                      ,
+       RULL(0x35040008), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_MODE_REG                                      ,
+       RULL(0x36040008), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_MODE_REG                                      ,
+       RULL(0x37040008), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_0_FSII2C_MODE_REGISTER                             ,
+       RULL(0x00001802), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM      );
+REG32( PERV_FSII2C_MODE_REGISTER                               ,
+       RULL(0x00001802), SH_UNT_PERV_FSII2C, SH_ACS_SCOM      );
+
+REG64( PERV_MULTICAST_GROUP_1                                  ,
+       RULL(0x000F0001), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_MULTICAST_GROUP_1                               ,
+       RULL(0x010F0001), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_MULTICAST_GROUP_1                               ,
+       RULL(0x020F0001), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_MULTICAST_GROUP_1                               ,
+       RULL(0x030F0001), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_MULTICAST_GROUP_1                               ,
+       RULL(0x040F0001), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_MULTICAST_GROUP_1                               ,
+       RULL(0x050F0001), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_MULTICAST_GROUP_1                               ,
+       RULL(0x060F0001), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_MULTICAST_GROUP_1                             ,
+       RULL(0x070F0001), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_MULTICAST_GROUP_1                             ,
+       RULL(0x080F0001), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_MULTICAST_GROUP_1                              ,
+       RULL(0x090F0001), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_MULTICAST_GROUP_1                              ,
+       RULL(0x0C0F0001), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_MULTICAST_GROUP_1                             ,
+       RULL(0x0D0F0001), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_MULTICAST_GROUP_1                             ,
+       RULL(0x0E0F0001), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_MULTICAST_GROUP_1                             ,
+       RULL(0x0F0F0001), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_MULTICAST_GROUP_1                             ,
+       RULL(0x100F0001), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_MULTICAST_GROUP_1                             ,
+       RULL(0x110F0001), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_MULTICAST_GROUP_1                             ,
+       RULL(0x120F0001), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_MULTICAST_GROUP_1                             ,
+       RULL(0x130F0001), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_MULTICAST_GROUP_1                             ,
+       RULL(0x140F0001), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_MULTICAST_GROUP_1                             ,
+       RULL(0x150F0001), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_MULTICAST_GROUP_1                             ,
+       RULL(0x200F0001), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_MULTICAST_GROUP_1                             ,
+       RULL(0x210F0001), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_MULTICAST_GROUP_1                             ,
+       RULL(0x220F0001), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_MULTICAST_GROUP_1                             ,
+       RULL(0x230F0001), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_MULTICAST_GROUP_1                             ,
+       RULL(0x240F0001), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_MULTICAST_GROUP_1                             ,
+       RULL(0x250F0001), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_MULTICAST_GROUP_1                             ,
+       RULL(0x260F0001), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_MULTICAST_GROUP_1                             ,
+       RULL(0x270F0001), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_MULTICAST_GROUP_1                             ,
+       RULL(0x280F0001), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_MULTICAST_GROUP_1                             ,
+       RULL(0x290F0001), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_MULTICAST_GROUP_1                             ,
+       RULL(0x2A0F0001), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_MULTICAST_GROUP_1                             ,
+       RULL(0x2B0F0001), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_MULTICAST_GROUP_1                             ,
+       RULL(0x2C0F0001), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_MULTICAST_GROUP_1                             ,
+       RULL(0x2D0F0001), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_MULTICAST_GROUP_1                             ,
+       RULL(0x2E0F0001), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_MULTICAST_GROUP_1                             ,
+       RULL(0x2F0F0001), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_MULTICAST_GROUP_1                             ,
+       RULL(0x300F0001), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_MULTICAST_GROUP_1                             ,
+       RULL(0x310F0001), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_MULTICAST_GROUP_1                             ,
+       RULL(0x320F0001), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_MULTICAST_GROUP_1                             ,
+       RULL(0x330F0001), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_MULTICAST_GROUP_1                             ,
+       RULL(0x340F0001), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_MULTICAST_GROUP_1                             ,
+       RULL(0x350F0001), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_MULTICAST_GROUP_1                             ,
+       RULL(0x360F0001), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_MULTICAST_GROUP_1                             ,
+       RULL(0x370F0001), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_MULTICAST_GROUP_2                                  ,
+       RULL(0x000F0002), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_MULTICAST_GROUP_2                               ,
+       RULL(0x010F0002), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_MULTICAST_GROUP_2                               ,
+       RULL(0x020F0002), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_MULTICAST_GROUP_2                               ,
+       RULL(0x030F0002), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_MULTICAST_GROUP_2                               ,
+       RULL(0x040F0002), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_MULTICAST_GROUP_2                               ,
+       RULL(0x050F0002), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_MULTICAST_GROUP_2                               ,
+       RULL(0x060F0002), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_MULTICAST_GROUP_2                             ,
+       RULL(0x070F0002), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_MULTICAST_GROUP_2                             ,
+       RULL(0x080F0002), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_MULTICAST_GROUP_2                              ,
+       RULL(0x090F0002), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_MULTICAST_GROUP_2                              ,
+       RULL(0x0C0F0002), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_MULTICAST_GROUP_2                             ,
+       RULL(0x0D0F0002), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_MULTICAST_GROUP_2                             ,
+       RULL(0x0E0F0002), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_MULTICAST_GROUP_2                             ,
+       RULL(0x0F0F0002), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_MULTICAST_GROUP_2                             ,
+       RULL(0x100F0002), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_MULTICAST_GROUP_2                             ,
+       RULL(0x110F0002), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_MULTICAST_GROUP_2                             ,
+       RULL(0x120F0002), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_MULTICAST_GROUP_2                             ,
+       RULL(0x130F0002), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_MULTICAST_GROUP_2                             ,
+       RULL(0x140F0002), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_MULTICAST_GROUP_2                             ,
+       RULL(0x150F0002), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_MULTICAST_GROUP_2                             ,
+       RULL(0x200F0002), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_MULTICAST_GROUP_2                             ,
+       RULL(0x210F0002), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_MULTICAST_GROUP_2                             ,
+       RULL(0x220F0002), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_MULTICAST_GROUP_2                             ,
+       RULL(0x230F0002), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_MULTICAST_GROUP_2                             ,
+       RULL(0x240F0002), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_MULTICAST_GROUP_2                             ,
+       RULL(0x250F0002), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_MULTICAST_GROUP_2                             ,
+       RULL(0x260F0002), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_MULTICAST_GROUP_2                             ,
+       RULL(0x270F0002), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_MULTICAST_GROUP_2                             ,
+       RULL(0x280F0002), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_MULTICAST_GROUP_2                             ,
+       RULL(0x290F0002), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_MULTICAST_GROUP_2                             ,
+       RULL(0x2A0F0002), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_MULTICAST_GROUP_2                             ,
+       RULL(0x2B0F0002), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_MULTICAST_GROUP_2                             ,
+       RULL(0x2C0F0002), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_MULTICAST_GROUP_2                             ,
+       RULL(0x2D0F0002), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_MULTICAST_GROUP_2                             ,
+       RULL(0x2E0F0002), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_MULTICAST_GROUP_2                             ,
+       RULL(0x2F0F0002), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_MULTICAST_GROUP_2                             ,
+       RULL(0x300F0002), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_MULTICAST_GROUP_2                             ,
+       RULL(0x310F0002), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_MULTICAST_GROUP_2                             ,
+       RULL(0x320F0002), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_MULTICAST_GROUP_2                             ,
+       RULL(0x330F0002), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_MULTICAST_GROUP_2                             ,
+       RULL(0x340F0002), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_MULTICAST_GROUP_2                             ,
+       RULL(0x350F0002), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_MULTICAST_GROUP_2                             ,
+       RULL(0x360F0002), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_MULTICAST_GROUP_2                             ,
+       RULL(0x370F0002), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_MULTICAST_GROUP_3                                  ,
+       RULL(0x000F0003), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_MULTICAST_GROUP_3                               ,
+       RULL(0x010F0003), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_MULTICAST_GROUP_3                               ,
+       RULL(0x020F0003), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_MULTICAST_GROUP_3                               ,
+       RULL(0x030F0003), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_MULTICAST_GROUP_3                               ,
+       RULL(0x040F0003), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_MULTICAST_GROUP_3                               ,
+       RULL(0x050F0003), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_MULTICAST_GROUP_3                               ,
+       RULL(0x060F0003), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_MULTICAST_GROUP_3                             ,
+       RULL(0x070F0003), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_MULTICAST_GROUP_3                             ,
+       RULL(0x080F0003), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_MULTICAST_GROUP_3                              ,
+       RULL(0x090F0003), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_MULTICAST_GROUP_3                              ,
+       RULL(0x0C0F0003), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_MULTICAST_GROUP_3                             ,
+       RULL(0x0D0F0003), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_MULTICAST_GROUP_3                             ,
+       RULL(0x0E0F0003), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_MULTICAST_GROUP_3                             ,
+       RULL(0x0F0F0003), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_MULTICAST_GROUP_3                             ,
+       RULL(0x100F0003), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_MULTICAST_GROUP_3                             ,
+       RULL(0x110F0003), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_MULTICAST_GROUP_3                             ,
+       RULL(0x120F0003), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_MULTICAST_GROUP_3                             ,
+       RULL(0x130F0003), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_MULTICAST_GROUP_3                             ,
+       RULL(0x140F0003), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_MULTICAST_GROUP_3                             ,
+       RULL(0x150F0003), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_MULTICAST_GROUP_3                             ,
+       RULL(0x200F0003), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_MULTICAST_GROUP_3                             ,
+       RULL(0x210F0003), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_MULTICAST_GROUP_3                             ,
+       RULL(0x220F0003), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_MULTICAST_GROUP_3                             ,
+       RULL(0x230F0003), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_MULTICAST_GROUP_3                             ,
+       RULL(0x240F0003), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_MULTICAST_GROUP_3                             ,
+       RULL(0x250F0003), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_MULTICAST_GROUP_3                             ,
+       RULL(0x260F0003), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_MULTICAST_GROUP_3                             ,
+       RULL(0x270F0003), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_MULTICAST_GROUP_3                             ,
+       RULL(0x280F0003), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_MULTICAST_GROUP_3                             ,
+       RULL(0x290F0003), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_MULTICAST_GROUP_3                             ,
+       RULL(0x2A0F0003), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_MULTICAST_GROUP_3                             ,
+       RULL(0x2B0F0003), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_MULTICAST_GROUP_3                             ,
+       RULL(0x2C0F0003), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_MULTICAST_GROUP_3                             ,
+       RULL(0x2D0F0003), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_MULTICAST_GROUP_3                             ,
+       RULL(0x2E0F0003), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_MULTICAST_GROUP_3                             ,
+       RULL(0x2F0F0003), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_MULTICAST_GROUP_3                             ,
+       RULL(0x300F0003), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_MULTICAST_GROUP_3                             ,
+       RULL(0x310F0003), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_MULTICAST_GROUP_3                             ,
+       RULL(0x320F0003), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_MULTICAST_GROUP_3                             ,
+       RULL(0x330F0003), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_MULTICAST_GROUP_3                             ,
+       RULL(0x340F0003), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_MULTICAST_GROUP_3                             ,
+       RULL(0x350F0003), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_MULTICAST_GROUP_3                             ,
+       RULL(0x360F0003), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_MULTICAST_GROUP_3                             ,
+       RULL(0x370F0003), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_MULTICAST_GROUP_4                                  ,
+       RULL(0x000F0004), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_MULTICAST_GROUP_4                               ,
+       RULL(0x010F0004), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_MULTICAST_GROUP_4                               ,
+       RULL(0x020F0004), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_MULTICAST_GROUP_4                               ,
+       RULL(0x030F0004), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_MULTICAST_GROUP_4                               ,
+       RULL(0x040F0004), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_MULTICAST_GROUP_4                               ,
+       RULL(0x050F0004), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_MULTICAST_GROUP_4                               ,
+       RULL(0x060F0004), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_MULTICAST_GROUP_4                             ,
+       RULL(0x070F0004), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_MULTICAST_GROUP_4                             ,
+       RULL(0x080F0004), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_MULTICAST_GROUP_4                              ,
+       RULL(0x090F0004), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_MULTICAST_GROUP_4                              ,
+       RULL(0x0C0F0004), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_MULTICAST_GROUP_4                             ,
+       RULL(0x0D0F0004), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_MULTICAST_GROUP_4                             ,
+       RULL(0x0E0F0004), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_MULTICAST_GROUP_4                             ,
+       RULL(0x0F0F0004), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_MULTICAST_GROUP_4                             ,
+       RULL(0x100F0004), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_MULTICAST_GROUP_4                             ,
+       RULL(0x110F0004), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_MULTICAST_GROUP_4                             ,
+       RULL(0x120F0004), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_MULTICAST_GROUP_4                             ,
+       RULL(0x130F0004), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_MULTICAST_GROUP_4                             ,
+       RULL(0x140F0004), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_MULTICAST_GROUP_4                             ,
+       RULL(0x150F0004), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_MULTICAST_GROUP_4                             ,
+       RULL(0x200F0004), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_MULTICAST_GROUP_4                             ,
+       RULL(0x210F0004), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_MULTICAST_GROUP_4                             ,
+       RULL(0x220F0004), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_MULTICAST_GROUP_4                             ,
+       RULL(0x230F0004), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_MULTICAST_GROUP_4                             ,
+       RULL(0x240F0004), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_MULTICAST_GROUP_4                             ,
+       RULL(0x250F0004), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_MULTICAST_GROUP_4                             ,
+       RULL(0x260F0004), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_MULTICAST_GROUP_4                             ,
+       RULL(0x270F0004), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_MULTICAST_GROUP_4                             ,
+       RULL(0x280F0004), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_MULTICAST_GROUP_4                             ,
+       RULL(0x290F0004), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_MULTICAST_GROUP_4                             ,
+       RULL(0x2A0F0004), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_MULTICAST_GROUP_4                             ,
+       RULL(0x2B0F0004), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_MULTICAST_GROUP_4                             ,
+       RULL(0x2C0F0004), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_MULTICAST_GROUP_4                             ,
+       RULL(0x2D0F0004), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_MULTICAST_GROUP_4                             ,
+       RULL(0x2E0F0004), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_MULTICAST_GROUP_4                             ,
+       RULL(0x2F0F0004), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_MULTICAST_GROUP_4                             ,
+       RULL(0x300F0004), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_MULTICAST_GROUP_4                             ,
+       RULL(0x310F0004), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_MULTICAST_GROUP_4                             ,
+       RULL(0x320F0004), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_MULTICAST_GROUP_4                             ,
+       RULL(0x330F0004), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_MULTICAST_GROUP_4                             ,
+       RULL(0x340F0004), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_MULTICAST_GROUP_4                             ,
+       RULL(0x350F0004), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_MULTICAST_GROUP_4                             ,
+       RULL(0x360F0004), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_MULTICAST_GROUP_4                             ,
+       RULL(0x370F0004), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_NET_CTRL0                                          ,
+       RULL(0x000F0040), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_NET_CTRL0                                       ,
+       RULL(0x010F0040), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_NET_CTRL0_WAND                                     ,
+       RULL(0x000F0041), SH_UNT_PERV_1   , SH_ACS_SCOM1_WAND );
+REG64( PERV_TP_NET_CTRL0_WAND                                  ,
+       RULL(0x010F0041), SH_UNT_PERV_1   , SH_ACS_SCOM1_WAND );
+REG64( PERV_NET_CTRL0_WOR                                      ,
+       RULL(0x000F0042), SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR );
+REG64( PERV_TP_NET_CTRL0_WOR                                   ,
+       RULL(0x010F0042), SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR );
+REG64( PERV_N0_NET_CTRL0                                       ,
+       RULL(0x020F0040), SH_UNT_PERV_2   , SH_ACS_SCOM_RW   );
+REG64( PERV_N0_NET_CTRL0_WAND                                  ,
+       RULL(0x020F0041), SH_UNT_PERV_2   , SH_ACS_SCOM1_WAND );
+REG64( PERV_N0_NET_CTRL0_WOR                                   ,
+       RULL(0x020F0042), SH_UNT_PERV_2   , SH_ACS_SCOM2_WOR );
+REG64( PERV_N1_NET_CTRL0                                       ,
+       RULL(0x030F0040), SH_UNT_PERV_3   , SH_ACS_SCOM_RW   );
+REG64( PERV_N1_NET_CTRL0_WAND                                  ,
+       RULL(0x030F0041), SH_UNT_PERV_3   , SH_ACS_SCOM1_WAND );
+REG64( PERV_N1_NET_CTRL0_WOR                                   ,
+       RULL(0x030F0042), SH_UNT_PERV_3   , SH_ACS_SCOM2_WOR );
+REG64( PERV_N2_NET_CTRL0                                       ,
+       RULL(0x040F0040), SH_UNT_PERV_4   , SH_ACS_SCOM_RW   );
+REG64( PERV_N2_NET_CTRL0_WAND                                  ,
+       RULL(0x040F0041), SH_UNT_PERV_4   , SH_ACS_SCOM1_WAND );
+REG64( PERV_N2_NET_CTRL0_WOR                                   ,
+       RULL(0x040F0042), SH_UNT_PERV_4   , SH_ACS_SCOM2_WOR );
+REG64( PERV_N3_NET_CTRL0                                       ,
+       RULL(0x050F0040), SH_UNT_PERV_5   , SH_ACS_SCOM_RW   );
+REG64( PERV_N3_NET_CTRL0_WAND                                  ,
+       RULL(0x050F0041), SH_UNT_PERV_5   , SH_ACS_SCOM1_WAND );
+REG64( PERV_N3_NET_CTRL0_WOR                                   ,
+       RULL(0x050F0042), SH_UNT_PERV_5   , SH_ACS_SCOM2_WOR );
+REG64( PERV_XB_NET_CTRL0                                       ,
+       RULL(0x060F0040), SH_UNT_PERV_6   , SH_ACS_SCOM_RW   );
+REG64( PERV_XB_NET_CTRL0_WAND                                  ,
+       RULL(0x060F0041), SH_UNT_PERV_6   , SH_ACS_SCOM1_WAND );
+REG64( PERV_XB_NET_CTRL0_WOR                                   ,
+       RULL(0x060F0042), SH_UNT_PERV_6   , SH_ACS_SCOM2_WOR );
+REG64( PERV_MC01_NET_CTRL0                                     ,
+       RULL(0x070F0040), SH_UNT_PERV_7   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC01_NET_CTRL0_WAND                                ,
+       RULL(0x070F0041), SH_UNT_PERV_7   , SH_ACS_SCOM1_WAND );
+REG64( PERV_MC01_NET_CTRL0_WOR                                 ,
+       RULL(0x070F0042), SH_UNT_PERV_7   , SH_ACS_SCOM2_WOR );
+REG64( PERV_MC23_NET_CTRL0                                     ,
+       RULL(0x080F0040), SH_UNT_PERV_8   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC23_NET_CTRL0_WAND                                ,
+       RULL(0x080F0041), SH_UNT_PERV_8   , SH_ACS_SCOM1_WAND );
+REG64( PERV_MC23_NET_CTRL0_WOR                                 ,
+       RULL(0x080F0042), SH_UNT_PERV_8   , SH_ACS_SCOM2_WOR );
+REG64( PERV_OB0_NET_CTRL0                                      ,
+       RULL(0x090F0040), SH_UNT_PERV_9   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB0_NET_CTRL0_WAND                                 ,
+       RULL(0x090F0041), SH_UNT_PERV_9   , SH_ACS_SCOM1_WAND );
+REG64( PERV_OB0_NET_CTRL0_WOR                                  ,
+       RULL(0x090F0042), SH_UNT_PERV_9   , SH_ACS_SCOM2_WOR );
+REG64( PERV_OB3_NET_CTRL0                                      ,
+       RULL(0x0C0F0040), SH_UNT_PERV_12  , SH_ACS_SCOM_RW   );
+REG64( PERV_OB3_NET_CTRL0_WAND                                 ,
+       RULL(0x0C0F0041), SH_UNT_PERV_12  , SH_ACS_SCOM1_WAND );
+REG64( PERV_OB3_NET_CTRL0_WOR                                  ,
+       RULL(0x0C0F0042), SH_UNT_PERV_12  , SH_ACS_SCOM2_WOR );
+REG64( PERV_PCI0_NET_CTRL0                                     ,
+       RULL(0x0D0F0040), SH_UNT_PERV_13  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI0_NET_CTRL0_WAND                                ,
+       RULL(0x0D0F0041), SH_UNT_PERV_13  , SH_ACS_SCOM1_WAND );
+REG64( PERV_PCI0_NET_CTRL0_WOR                                 ,
+       RULL(0x0D0F0042), SH_UNT_PERV_13  , SH_ACS_SCOM2_WOR );
+REG64( PERV_PCI1_NET_CTRL0                                     ,
+       RULL(0x0E0F0040), SH_UNT_PERV_14  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI1_NET_CTRL0_WAND                                ,
+       RULL(0x0E0F0041), SH_UNT_PERV_14  , SH_ACS_SCOM1_WAND );
+REG64( PERV_PCI1_NET_CTRL0_WOR                                 ,
+       RULL(0x0E0F0042), SH_UNT_PERV_14  , SH_ACS_SCOM2_WOR );
+REG64( PERV_PCI2_NET_CTRL0                                     ,
+       RULL(0x0F0F0040), SH_UNT_PERV_15  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI2_NET_CTRL0_WAND                                ,
+       RULL(0x0F0F0041), SH_UNT_PERV_15  , SH_ACS_SCOM1_WAND );
+REG64( PERV_PCI2_NET_CTRL0_WOR                                 ,
+       RULL(0x0F0F0042), SH_UNT_PERV_15  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP00_NET_CTRL0                                     ,
+       RULL(0x100F0040), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_NET_CTRL0_WAND                                ,
+       RULL(0x100F0041), SH_UNT_PERV_16  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EP00_NET_CTRL0_WOR                                 ,
+       RULL(0x100F0042), SH_UNT_PERV_16  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP01_NET_CTRL0                                     ,
+       RULL(0x110F0040), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_NET_CTRL0_WAND                                ,
+       RULL(0x110F0041), SH_UNT_PERV_17  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EP01_NET_CTRL0_WOR                                 ,
+       RULL(0x110F0042), SH_UNT_PERV_17  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP02_NET_CTRL0                                     ,
+       RULL(0x120F0040), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_NET_CTRL0_WAND                                ,
+       RULL(0x120F0041), SH_UNT_PERV_18  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EP02_NET_CTRL0_WOR                                 ,
+       RULL(0x120F0042), SH_UNT_PERV_18  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP03_NET_CTRL0                                     ,
+       RULL(0x130F0040), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_NET_CTRL0_WAND                                ,
+       RULL(0x130F0041), SH_UNT_PERV_19  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EP03_NET_CTRL0_WOR                                 ,
+       RULL(0x130F0042), SH_UNT_PERV_19  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP04_NET_CTRL0                                     ,
+       RULL(0x140F0040), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_NET_CTRL0_WAND                                ,
+       RULL(0x140F0041), SH_UNT_PERV_20  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EP04_NET_CTRL0_WOR                                 ,
+       RULL(0x140F0042), SH_UNT_PERV_20  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP05_NET_CTRL0                                     ,
+       RULL(0x150F0040), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_NET_CTRL0_WAND                                ,
+       RULL(0x150F0041), SH_UNT_PERV_21  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EP05_NET_CTRL0_WOR                                 ,
+       RULL(0x150F0042), SH_UNT_PERV_21  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC00_NET_CTRL0                                     ,
+       RULL(0x200F0040), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_NET_CTRL0_WAND                                ,
+       RULL(0x200F0041), SH_UNT_PERV_32  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC00_NET_CTRL0_WOR                                 ,
+       RULL(0x200F0042), SH_UNT_PERV_32  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC01_NET_CTRL0                                     ,
+       RULL(0x210F0040), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_NET_CTRL0_WAND                                ,
+       RULL(0x210F0041), SH_UNT_PERV_33  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC01_NET_CTRL0_WOR                                 ,
+       RULL(0x210F0042), SH_UNT_PERV_33  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC02_NET_CTRL0                                     ,
+       RULL(0x220F0040), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_NET_CTRL0_WAND                                ,
+       RULL(0x220F0041), SH_UNT_PERV_34  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC02_NET_CTRL0_WOR                                 ,
+       RULL(0x220F0042), SH_UNT_PERV_34  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC03_NET_CTRL0                                     ,
+       RULL(0x230F0040), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_NET_CTRL0_WAND                                ,
+       RULL(0x230F0041), SH_UNT_PERV_35  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC03_NET_CTRL0_WOR                                 ,
+       RULL(0x230F0042), SH_UNT_PERV_35  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC04_NET_CTRL0                                     ,
+       RULL(0x240F0040), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_NET_CTRL0_WAND                                ,
+       RULL(0x240F0041), SH_UNT_PERV_36  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC04_NET_CTRL0_WOR                                 ,
+       RULL(0x240F0042), SH_UNT_PERV_36  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC05_NET_CTRL0                                     ,
+       RULL(0x250F0040), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_NET_CTRL0_WAND                                ,
+       RULL(0x250F0041), SH_UNT_PERV_37  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC05_NET_CTRL0_WOR                                 ,
+       RULL(0x250F0042), SH_UNT_PERV_37  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC06_NET_CTRL0                                     ,
+       RULL(0x260F0040), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_NET_CTRL0_WAND                                ,
+       RULL(0x260F0041), SH_UNT_PERV_38  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC06_NET_CTRL0_WOR                                 ,
+       RULL(0x260F0042), SH_UNT_PERV_38  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC07_NET_CTRL0                                     ,
+       RULL(0x270F0040), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_NET_CTRL0_WAND                                ,
+       RULL(0x270F0041), SH_UNT_PERV_39  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC07_NET_CTRL0_WOR                                 ,
+       RULL(0x270F0042), SH_UNT_PERV_39  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC08_NET_CTRL0                                     ,
+       RULL(0x280F0040), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_NET_CTRL0_WAND                                ,
+       RULL(0x280F0041), SH_UNT_PERV_40  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC08_NET_CTRL0_WOR                                 ,
+       RULL(0x280F0042), SH_UNT_PERV_40  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC09_NET_CTRL0                                     ,
+       RULL(0x290F0040), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_NET_CTRL0_WAND                                ,
+       RULL(0x290F0041), SH_UNT_PERV_41  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC09_NET_CTRL0_WOR                                 ,
+       RULL(0x290F0042), SH_UNT_PERV_41  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC10_NET_CTRL0                                     ,
+       RULL(0x2A0F0040), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_NET_CTRL0_WAND                                ,
+       RULL(0x2A0F0041), SH_UNT_PERV_42  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC10_NET_CTRL0_WOR                                 ,
+       RULL(0x2A0F0042), SH_UNT_PERV_42  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC11_NET_CTRL0                                     ,
+       RULL(0x2B0F0040), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_NET_CTRL0_WAND                                ,
+       RULL(0x2B0F0041), SH_UNT_PERV_43  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC11_NET_CTRL0_WOR                                 ,
+       RULL(0x2B0F0042), SH_UNT_PERV_43  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC12_NET_CTRL0                                     ,
+       RULL(0x2C0F0040), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_NET_CTRL0_WAND                                ,
+       RULL(0x2C0F0041), SH_UNT_PERV_44  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC12_NET_CTRL0_WOR                                 ,
+       RULL(0x2C0F0042), SH_UNT_PERV_44  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC13_NET_CTRL0                                     ,
+       RULL(0x2D0F0040), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_NET_CTRL0_WAND                                ,
+       RULL(0x2D0F0041), SH_UNT_PERV_45  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC13_NET_CTRL0_WOR                                 ,
+       RULL(0x2D0F0042), SH_UNT_PERV_45  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC14_NET_CTRL0                                     ,
+       RULL(0x2E0F0040), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_NET_CTRL0_WAND                                ,
+       RULL(0x2E0F0041), SH_UNT_PERV_46  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC14_NET_CTRL0_WOR                                 ,
+       RULL(0x2E0F0042), SH_UNT_PERV_46  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC15_NET_CTRL0                                     ,
+       RULL(0x2F0F0040), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_NET_CTRL0_WAND                                ,
+       RULL(0x2F0F0041), SH_UNT_PERV_47  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC15_NET_CTRL0_WOR                                 ,
+       RULL(0x2F0F0042), SH_UNT_PERV_47  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC16_NET_CTRL0                                     ,
+       RULL(0x300F0040), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_NET_CTRL0_WAND                                ,
+       RULL(0x300F0041), SH_UNT_PERV_48  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC16_NET_CTRL0_WOR                                 ,
+       RULL(0x300F0042), SH_UNT_PERV_48  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC17_NET_CTRL0                                     ,
+       RULL(0x310F0040), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_NET_CTRL0_WAND                                ,
+       RULL(0x310F0041), SH_UNT_PERV_49  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC17_NET_CTRL0_WOR                                 ,
+       RULL(0x310F0042), SH_UNT_PERV_49  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC18_NET_CTRL0                                     ,
+       RULL(0x320F0040), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_NET_CTRL0_WAND                                ,
+       RULL(0x320F0041), SH_UNT_PERV_50  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC18_NET_CTRL0_WOR                                 ,
+       RULL(0x320F0042), SH_UNT_PERV_50  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC19_NET_CTRL0                                     ,
+       RULL(0x330F0040), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_NET_CTRL0_WAND                                ,
+       RULL(0x330F0041), SH_UNT_PERV_51  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC19_NET_CTRL0_WOR                                 ,
+       RULL(0x330F0042), SH_UNT_PERV_51  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC20_NET_CTRL0                                     ,
+       RULL(0x340F0040), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_NET_CTRL0_WAND                                ,
+       RULL(0x340F0041), SH_UNT_PERV_52  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC20_NET_CTRL0_WOR                                 ,
+       RULL(0x340F0042), SH_UNT_PERV_52  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC21_NET_CTRL0                                     ,
+       RULL(0x350F0040), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_NET_CTRL0_WAND                                ,
+       RULL(0x350F0041), SH_UNT_PERV_53  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC21_NET_CTRL0_WOR                                 ,
+       RULL(0x350F0042), SH_UNT_PERV_53  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC22_NET_CTRL0                                     ,
+       RULL(0x360F0040), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_NET_CTRL0_WAND                                ,
+       RULL(0x360F0041), SH_UNT_PERV_54  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC22_NET_CTRL0_WOR                                 ,
+       RULL(0x360F0042), SH_UNT_PERV_54  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC23_NET_CTRL0                                     ,
+       RULL(0x370F0040), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_NET_CTRL0_WAND                                ,
+       RULL(0x370F0041), SH_UNT_PERV_55  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC23_NET_CTRL0_WOR                                 ,
+       RULL(0x370F0042), SH_UNT_PERV_55  , SH_ACS_SCOM2_WOR );
+
+REG64( PERV_NET_CTRL1                                          ,
+       RULL(0x000F0044), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_NET_CTRL1                                       ,
+       RULL(0x010F0044), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_NET_CTRL1_WAND                                     ,
+       RULL(0x000F0045), SH_UNT_PERV_1   , SH_ACS_SCOM1_WAND );
+REG64( PERV_TP_NET_CTRL1_WAND                                  ,
+       RULL(0x010F0045), SH_UNT_PERV_1   , SH_ACS_SCOM1_WAND );
+REG64( PERV_NET_CTRL1_WOR                                      ,
+       RULL(0x000F0046), SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR );
+REG64( PERV_TP_NET_CTRL1_WOR                                   ,
+       RULL(0x010F0046), SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR );
+REG64( PERV_N0_NET_CTRL1                                       ,
+       RULL(0x020F0044), SH_UNT_PERV_2   , SH_ACS_SCOM_RW   );
+REG64( PERV_N0_NET_CTRL1_WAND                                  ,
+       RULL(0x020F0045), SH_UNT_PERV_2   , SH_ACS_SCOM1_WAND );
+REG64( PERV_N0_NET_CTRL1_WOR                                   ,
+       RULL(0x020F0046), SH_UNT_PERV_2   , SH_ACS_SCOM2_WOR );
+REG64( PERV_N1_NET_CTRL1                                       ,
+       RULL(0x030F0044), SH_UNT_PERV_3   , SH_ACS_SCOM_RW   );
+REG64( PERV_N1_NET_CTRL1_WAND                                  ,
+       RULL(0x030F0045), SH_UNT_PERV_3   , SH_ACS_SCOM1_WAND );
+REG64( PERV_N1_NET_CTRL1_WOR                                   ,
+       RULL(0x030F0046), SH_UNT_PERV_3   , SH_ACS_SCOM2_WOR );
+REG64( PERV_N2_NET_CTRL1                                       ,
+       RULL(0x040F0044), SH_UNT_PERV_4   , SH_ACS_SCOM_RW   );
+REG64( PERV_N2_NET_CTRL1_WAND                                  ,
+       RULL(0x040F0045), SH_UNT_PERV_4   , SH_ACS_SCOM1_WAND );
+REG64( PERV_N2_NET_CTRL1_WOR                                   ,
+       RULL(0x040F0046), SH_UNT_PERV_4   , SH_ACS_SCOM2_WOR );
+REG64( PERV_N3_NET_CTRL1                                       ,
+       RULL(0x050F0044), SH_UNT_PERV_5   , SH_ACS_SCOM_RW   );
+REG64( PERV_N3_NET_CTRL1_WAND                                  ,
+       RULL(0x050F0045), SH_UNT_PERV_5   , SH_ACS_SCOM1_WAND );
+REG64( PERV_N3_NET_CTRL1_WOR                                   ,
+       RULL(0x050F0046), SH_UNT_PERV_5   , SH_ACS_SCOM2_WOR );
+REG64( PERV_XB_NET_CTRL1                                       ,
+       RULL(0x060F0044), SH_UNT_PERV_6   , SH_ACS_SCOM_RW   );
+REG64( PERV_XB_NET_CTRL1_WAND                                  ,
+       RULL(0x060F0045), SH_UNT_PERV_6   , SH_ACS_SCOM1_WAND );
+REG64( PERV_XB_NET_CTRL1_WOR                                   ,
+       RULL(0x060F0046), SH_UNT_PERV_6   , SH_ACS_SCOM2_WOR );
+REG64( PERV_MC01_NET_CTRL1                                     ,
+       RULL(0x070F0044), SH_UNT_PERV_7   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC01_NET_CTRL1_WAND                                ,
+       RULL(0x070F0045), SH_UNT_PERV_7   , SH_ACS_SCOM1_WAND );
+REG64( PERV_MC01_NET_CTRL1_WOR                                 ,
+       RULL(0x070F0046), SH_UNT_PERV_7   , SH_ACS_SCOM2_WOR );
+REG64( PERV_MC23_NET_CTRL1                                     ,
+       RULL(0x080F0044), SH_UNT_PERV_8   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC23_NET_CTRL1_WAND                                ,
+       RULL(0x080F0045), SH_UNT_PERV_8   , SH_ACS_SCOM1_WAND );
+REG64( PERV_MC23_NET_CTRL1_WOR                                 ,
+       RULL(0x080F0046), SH_UNT_PERV_8   , SH_ACS_SCOM2_WOR );
+REG64( PERV_OB0_NET_CTRL1                                      ,
+       RULL(0x090F0044), SH_UNT_PERV_9   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB0_NET_CTRL1_WAND                                 ,
+       RULL(0x090F0045), SH_UNT_PERV_9   , SH_ACS_SCOM1_WAND );
+REG64( PERV_OB0_NET_CTRL1_WOR                                  ,
+       RULL(0x090F0046), SH_UNT_PERV_9   , SH_ACS_SCOM2_WOR );
+REG64( PERV_OB3_NET_CTRL1                                      ,
+       RULL(0x0C0F0044), SH_UNT_PERV_12  , SH_ACS_SCOM_RW   );
+REG64( PERV_OB3_NET_CTRL1_WAND                                 ,
+       RULL(0x0C0F0045), SH_UNT_PERV_12  , SH_ACS_SCOM1_WAND );
+REG64( PERV_OB3_NET_CTRL1_WOR                                  ,
+       RULL(0x0C0F0046), SH_UNT_PERV_12  , SH_ACS_SCOM2_WOR );
+REG64( PERV_PCI0_NET_CTRL1                                     ,
+       RULL(0x0D0F0044), SH_UNT_PERV_13  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI0_NET_CTRL1_WAND                                ,
+       RULL(0x0D0F0045), SH_UNT_PERV_13  , SH_ACS_SCOM1_WAND );
+REG64( PERV_PCI0_NET_CTRL1_WOR                                 ,
+       RULL(0x0D0F0046), SH_UNT_PERV_13  , SH_ACS_SCOM2_WOR );
+REG64( PERV_PCI1_NET_CTRL1                                     ,
+       RULL(0x0E0F0044), SH_UNT_PERV_14  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI1_NET_CTRL1_WAND                                ,
+       RULL(0x0E0F0045), SH_UNT_PERV_14  , SH_ACS_SCOM1_WAND );
+REG64( PERV_PCI1_NET_CTRL1_WOR                                 ,
+       RULL(0x0E0F0046), SH_UNT_PERV_14  , SH_ACS_SCOM2_WOR );
+REG64( PERV_PCI2_NET_CTRL1                                     ,
+       RULL(0x0F0F0044), SH_UNT_PERV_15  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI2_NET_CTRL1_WAND                                ,
+       RULL(0x0F0F0045), SH_UNT_PERV_15  , SH_ACS_SCOM1_WAND );
+REG64( PERV_PCI2_NET_CTRL1_WOR                                 ,
+       RULL(0x0F0F0046), SH_UNT_PERV_15  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP00_NET_CTRL1                                     ,
+       RULL(0x100F0044), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_NET_CTRL1_WAND                                ,
+       RULL(0x100F0045), SH_UNT_PERV_16  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EP00_NET_CTRL1_WOR                                 ,
+       RULL(0x100F0046), SH_UNT_PERV_16  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP01_NET_CTRL1                                     ,
+       RULL(0x110F0044), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_NET_CTRL1_WAND                                ,
+       RULL(0x110F0045), SH_UNT_PERV_17  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EP01_NET_CTRL1_WOR                                 ,
+       RULL(0x110F0046), SH_UNT_PERV_17  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP02_NET_CTRL1                                     ,
+       RULL(0x120F0044), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_NET_CTRL1_WAND                                ,
+       RULL(0x120F0045), SH_UNT_PERV_18  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EP02_NET_CTRL1_WOR                                 ,
+       RULL(0x120F0046), SH_UNT_PERV_18  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP03_NET_CTRL1                                     ,
+       RULL(0x130F0044), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_NET_CTRL1_WAND                                ,
+       RULL(0x130F0045), SH_UNT_PERV_19  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EP03_NET_CTRL1_WOR                                 ,
+       RULL(0x130F0046), SH_UNT_PERV_19  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP04_NET_CTRL1                                     ,
+       RULL(0x140F0044), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_NET_CTRL1_WAND                                ,
+       RULL(0x140F0045), SH_UNT_PERV_20  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EP04_NET_CTRL1_WOR                                 ,
+       RULL(0x140F0046), SH_UNT_PERV_20  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP05_NET_CTRL1                                     ,
+       RULL(0x150F0044), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_NET_CTRL1_WAND                                ,
+       RULL(0x150F0045), SH_UNT_PERV_21  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EP05_NET_CTRL1_WOR                                 ,
+       RULL(0x150F0046), SH_UNT_PERV_21  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC00_NET_CTRL1                                     ,
+       RULL(0x200F0044), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_NET_CTRL1_WAND                                ,
+       RULL(0x200F0045), SH_UNT_PERV_32  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC00_NET_CTRL1_WOR                                 ,
+       RULL(0x200F0046), SH_UNT_PERV_32  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC01_NET_CTRL1                                     ,
+       RULL(0x210F0044), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_NET_CTRL1_WAND                                ,
+       RULL(0x210F0045), SH_UNT_PERV_33  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC01_NET_CTRL1_WOR                                 ,
+       RULL(0x210F0046), SH_UNT_PERV_33  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC02_NET_CTRL1                                     ,
+       RULL(0x220F0044), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_NET_CTRL1_WAND                                ,
+       RULL(0x220F0045), SH_UNT_PERV_34  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC02_NET_CTRL1_WOR                                 ,
+       RULL(0x220F0046), SH_UNT_PERV_34  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC03_NET_CTRL1                                     ,
+       RULL(0x230F0044), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_NET_CTRL1_WAND                                ,
+       RULL(0x230F0045), SH_UNT_PERV_35  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC03_NET_CTRL1_WOR                                 ,
+       RULL(0x230F0046), SH_UNT_PERV_35  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC04_NET_CTRL1                                     ,
+       RULL(0x240F0044), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_NET_CTRL1_WAND                                ,
+       RULL(0x240F0045), SH_UNT_PERV_36  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC04_NET_CTRL1_WOR                                 ,
+       RULL(0x240F0046), SH_UNT_PERV_36  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC05_NET_CTRL1                                     ,
+       RULL(0x250F0044), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_NET_CTRL1_WAND                                ,
+       RULL(0x250F0045), SH_UNT_PERV_37  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC05_NET_CTRL1_WOR                                 ,
+       RULL(0x250F0046), SH_UNT_PERV_37  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC06_NET_CTRL1                                     ,
+       RULL(0x260F0044), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_NET_CTRL1_WAND                                ,
+       RULL(0x260F0045), SH_UNT_PERV_38  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC06_NET_CTRL1_WOR                                 ,
+       RULL(0x260F0046), SH_UNT_PERV_38  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC07_NET_CTRL1                                     ,
+       RULL(0x270F0044), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_NET_CTRL1_WAND                                ,
+       RULL(0x270F0045), SH_UNT_PERV_39  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC07_NET_CTRL1_WOR                                 ,
+       RULL(0x270F0046), SH_UNT_PERV_39  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC08_NET_CTRL1                                     ,
+       RULL(0x280F0044), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_NET_CTRL1_WAND                                ,
+       RULL(0x280F0045), SH_UNT_PERV_40  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC08_NET_CTRL1_WOR                                 ,
+       RULL(0x280F0046), SH_UNT_PERV_40  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC09_NET_CTRL1                                     ,
+       RULL(0x290F0044), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_NET_CTRL1_WAND                                ,
+       RULL(0x290F0045), SH_UNT_PERV_41  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC09_NET_CTRL1_WOR                                 ,
+       RULL(0x290F0046), SH_UNT_PERV_41  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC10_NET_CTRL1                                     ,
+       RULL(0x2A0F0044), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_NET_CTRL1_WAND                                ,
+       RULL(0x2A0F0045), SH_UNT_PERV_42  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC10_NET_CTRL1_WOR                                 ,
+       RULL(0x2A0F0046), SH_UNT_PERV_42  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC11_NET_CTRL1                                     ,
+       RULL(0x2B0F0044), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_NET_CTRL1_WAND                                ,
+       RULL(0x2B0F0045), SH_UNT_PERV_43  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC11_NET_CTRL1_WOR                                 ,
+       RULL(0x2B0F0046), SH_UNT_PERV_43  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC12_NET_CTRL1                                     ,
+       RULL(0x2C0F0044), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_NET_CTRL1_WAND                                ,
+       RULL(0x2C0F0045), SH_UNT_PERV_44  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC12_NET_CTRL1_WOR                                 ,
+       RULL(0x2C0F0046), SH_UNT_PERV_44  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC13_NET_CTRL1                                     ,
+       RULL(0x2D0F0044), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_NET_CTRL1_WAND                                ,
+       RULL(0x2D0F0045), SH_UNT_PERV_45  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC13_NET_CTRL1_WOR                                 ,
+       RULL(0x2D0F0046), SH_UNT_PERV_45  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC14_NET_CTRL1                                     ,
+       RULL(0x2E0F0044), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_NET_CTRL1_WAND                                ,
+       RULL(0x2E0F0045), SH_UNT_PERV_46  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC14_NET_CTRL1_WOR                                 ,
+       RULL(0x2E0F0046), SH_UNT_PERV_46  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC15_NET_CTRL1                                     ,
+       RULL(0x2F0F0044), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_NET_CTRL1_WAND                                ,
+       RULL(0x2F0F0045), SH_UNT_PERV_47  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC15_NET_CTRL1_WOR                                 ,
+       RULL(0x2F0F0046), SH_UNT_PERV_47  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC16_NET_CTRL1                                     ,
+       RULL(0x300F0044), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_NET_CTRL1_WAND                                ,
+       RULL(0x300F0045), SH_UNT_PERV_48  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC16_NET_CTRL1_WOR                                 ,
+       RULL(0x300F0046), SH_UNT_PERV_48  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC17_NET_CTRL1                                     ,
+       RULL(0x310F0044), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_NET_CTRL1_WAND                                ,
+       RULL(0x310F0045), SH_UNT_PERV_49  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC17_NET_CTRL1_WOR                                 ,
+       RULL(0x310F0046), SH_UNT_PERV_49  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC18_NET_CTRL1                                     ,
+       RULL(0x320F0044), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_NET_CTRL1_WAND                                ,
+       RULL(0x320F0045), SH_UNT_PERV_50  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC18_NET_CTRL1_WOR                                 ,
+       RULL(0x320F0046), SH_UNT_PERV_50  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC19_NET_CTRL1                                     ,
+       RULL(0x330F0044), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_NET_CTRL1_WAND                                ,
+       RULL(0x330F0045), SH_UNT_PERV_51  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC19_NET_CTRL1_WOR                                 ,
+       RULL(0x330F0046), SH_UNT_PERV_51  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC20_NET_CTRL1                                     ,
+       RULL(0x340F0044), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_NET_CTRL1_WAND                                ,
+       RULL(0x340F0045), SH_UNT_PERV_52  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC20_NET_CTRL1_WOR                                 ,
+       RULL(0x340F0046), SH_UNT_PERV_52  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC21_NET_CTRL1                                     ,
+       RULL(0x350F0044), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_NET_CTRL1_WAND                                ,
+       RULL(0x350F0045), SH_UNT_PERV_53  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC21_NET_CTRL1_WOR                                 ,
+       RULL(0x350F0046), SH_UNT_PERV_53  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC22_NET_CTRL1                                     ,
+       RULL(0x360F0044), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_NET_CTRL1_WAND                                ,
+       RULL(0x360F0045), SH_UNT_PERV_54  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC22_NET_CTRL1_WOR                                 ,
+       RULL(0x360F0046), SH_UNT_PERV_54  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC23_NET_CTRL1                                     ,
+       RULL(0x370F0044), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_NET_CTRL1_WAND                                ,
+       RULL(0x370F0045), SH_UNT_PERV_55  , SH_ACS_SCOM1_WAND );
+REG64( PERV_EC23_NET_CTRL1_WOR                                 ,
+       RULL(0x370F0046), SH_UNT_PERV_55  , SH_ACS_SCOM2_WOR );
+
+REG64( PERV_OPCG_ALIGN                                         ,
+       RULL(0x00030001), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_OPCG_ALIGN                                      ,
+       RULL(0x01030001), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_OPCG_ALIGN                                      ,
+       RULL(0x02030001), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_OPCG_ALIGN                                      ,
+       RULL(0x03030001), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_OPCG_ALIGN                                      ,
+       RULL(0x04030001), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_OPCG_ALIGN                                      ,
+       RULL(0x05030001), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_OPCG_ALIGN                                      ,
+       RULL(0x06030001), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_OPCG_ALIGN                                    ,
+       RULL(0x07030001), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_OPCG_ALIGN                                    ,
+       RULL(0x08030001), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_OPCG_ALIGN                                     ,
+       RULL(0x09030001), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_OPCG_ALIGN                                     ,
+       RULL(0x0C030001), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_OPCG_ALIGN                                    ,
+       RULL(0x0D030001), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_OPCG_ALIGN                                    ,
+       RULL(0x0E030001), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_OPCG_ALIGN                                    ,
+       RULL(0x0F030001), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_OPCG_ALIGN                                    ,
+       RULL(0x10030001), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_OPCG_ALIGN                                    ,
+       RULL(0x11030001), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_OPCG_ALIGN                                    ,
+       RULL(0x12030001), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_OPCG_ALIGN                                    ,
+       RULL(0x13030001), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_OPCG_ALIGN                                    ,
+       RULL(0x14030001), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_OPCG_ALIGN                                    ,
+       RULL(0x15030001), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_OPCG_ALIGN                                    ,
+       RULL(0x20030001), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_OPCG_ALIGN                                    ,
+       RULL(0x21030001), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_OPCG_ALIGN                                    ,
+       RULL(0x22030001), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_OPCG_ALIGN                                    ,
+       RULL(0x23030001), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_OPCG_ALIGN                                    ,
+       RULL(0x24030001), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_OPCG_ALIGN                                    ,
+       RULL(0x25030001), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_OPCG_ALIGN                                    ,
+       RULL(0x26030001), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_OPCG_ALIGN                                    ,
+       RULL(0x27030001), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_OPCG_ALIGN                                    ,
+       RULL(0x28030001), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_OPCG_ALIGN                                    ,
+       RULL(0x29030001), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_OPCG_ALIGN                                    ,
+       RULL(0x2A030001), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_OPCG_ALIGN                                    ,
+       RULL(0x2B030001), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_OPCG_ALIGN                                    ,
+       RULL(0x2C030001), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_OPCG_ALIGN                                    ,
+       RULL(0x2D030001), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_OPCG_ALIGN                                    ,
+       RULL(0x2E030001), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_OPCG_ALIGN                                    ,
+       RULL(0x2F030001), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_OPCG_ALIGN                                    ,
+       RULL(0x30030001), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_OPCG_ALIGN                                    ,
+       RULL(0x31030001), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_OPCG_ALIGN                                    ,
+       RULL(0x32030001), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_OPCG_ALIGN                                    ,
+       RULL(0x33030001), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_OPCG_ALIGN                                    ,
+       RULL(0x34030001), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_OPCG_ALIGN                                    ,
+       RULL(0x35030001), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_OPCG_ALIGN                                    ,
+       RULL(0x36030001), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_OPCG_ALIGN                                    ,
+       RULL(0x37030001), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_OPCG_CAPT1                                         ,
+       RULL(0x00030010), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_OPCG_CAPT1                                      ,
+       RULL(0x01030010), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_OPCG_CAPT1                                      ,
+       RULL(0x02030010), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_OPCG_CAPT1                                      ,
+       RULL(0x03030010), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_OPCG_CAPT1                                      ,
+       RULL(0x04030010), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_OPCG_CAPT1                                      ,
+       RULL(0x05030010), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_OPCG_CAPT1                                      ,
+       RULL(0x06030010), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_OPCG_CAPT1                                    ,
+       RULL(0x07030010), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_OPCG_CAPT1                                    ,
+       RULL(0x08030010), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_OPCG_CAPT1                                     ,
+       RULL(0x09030010), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_OPCG_CAPT1                                     ,
+       RULL(0x0C030010), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_OPCG_CAPT1                                    ,
+       RULL(0x0D030010), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_OPCG_CAPT1                                    ,
+       RULL(0x0E030010), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_OPCG_CAPT1                                    ,
+       RULL(0x0F030010), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_OPCG_CAPT1                                    ,
+       RULL(0x10030010), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_OPCG_CAPT1                                    ,
+       RULL(0x11030010), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_OPCG_CAPT1                                    ,
+       RULL(0x12030010), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_OPCG_CAPT1                                    ,
+       RULL(0x13030010), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_OPCG_CAPT1                                    ,
+       RULL(0x14030010), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_OPCG_CAPT1                                    ,
+       RULL(0x15030010), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_OPCG_CAPT1                                    ,
+       RULL(0x20030010), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_OPCG_CAPT1                                    ,
+       RULL(0x21030010), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_OPCG_CAPT1                                    ,
+       RULL(0x22030010), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_OPCG_CAPT1                                    ,
+       RULL(0x23030010), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_OPCG_CAPT1                                    ,
+       RULL(0x24030010), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_OPCG_CAPT1                                    ,
+       RULL(0x25030010), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_OPCG_CAPT1                                    ,
+       RULL(0x26030010), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_OPCG_CAPT1                                    ,
+       RULL(0x27030010), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_OPCG_CAPT1                                    ,
+       RULL(0x28030010), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_OPCG_CAPT1                                    ,
+       RULL(0x29030010), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_OPCG_CAPT1                                    ,
+       RULL(0x2A030010), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_OPCG_CAPT1                                    ,
+       RULL(0x2B030010), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_OPCG_CAPT1                                    ,
+       RULL(0x2C030010), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_OPCG_CAPT1                                    ,
+       RULL(0x2D030010), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_OPCG_CAPT1                                    ,
+       RULL(0x2E030010), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_OPCG_CAPT1                                    ,
+       RULL(0x2F030010), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_OPCG_CAPT1                                    ,
+       RULL(0x30030010), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_OPCG_CAPT1                                    ,
+       RULL(0x31030010), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_OPCG_CAPT1                                    ,
+       RULL(0x32030010), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_OPCG_CAPT1                                    ,
+       RULL(0x33030010), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_OPCG_CAPT1                                    ,
+       RULL(0x34030010), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_OPCG_CAPT1                                    ,
+       RULL(0x35030010), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_OPCG_CAPT1                                    ,
+       RULL(0x36030010), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_OPCG_CAPT1                                    ,
+       RULL(0x37030010), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_OPCG_CAPT2                                         ,
+       RULL(0x00030011), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_OPCG_CAPT2                                      ,
+       RULL(0x01030011), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_OPCG_CAPT2                                      ,
+       RULL(0x02030011), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_OPCG_CAPT2                                      ,
+       RULL(0x03030011), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_OPCG_CAPT2                                      ,
+       RULL(0x04030011), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_OPCG_CAPT2                                      ,
+       RULL(0x05030011), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_OPCG_CAPT2                                      ,
+       RULL(0x06030011), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_OPCG_CAPT2                                    ,
+       RULL(0x07030011), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_OPCG_CAPT2                                    ,
+       RULL(0x08030011), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_OPCG_CAPT2                                     ,
+       RULL(0x09030011), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_OPCG_CAPT2                                     ,
+       RULL(0x0C030011), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_OPCG_CAPT2                                    ,
+       RULL(0x0D030011), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_OPCG_CAPT2                                    ,
+       RULL(0x0E030011), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_OPCG_CAPT2                                    ,
+       RULL(0x0F030011), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_OPCG_CAPT2                                    ,
+       RULL(0x10030011), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_OPCG_CAPT2                                    ,
+       RULL(0x11030011), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_OPCG_CAPT2                                    ,
+       RULL(0x12030011), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_OPCG_CAPT2                                    ,
+       RULL(0x13030011), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_OPCG_CAPT2                                    ,
+       RULL(0x14030011), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_OPCG_CAPT2                                    ,
+       RULL(0x15030011), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_OPCG_CAPT2                                    ,
+       RULL(0x20030011), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_OPCG_CAPT2                                    ,
+       RULL(0x21030011), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_OPCG_CAPT2                                    ,
+       RULL(0x22030011), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_OPCG_CAPT2                                    ,
+       RULL(0x23030011), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_OPCG_CAPT2                                    ,
+       RULL(0x24030011), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_OPCG_CAPT2                                    ,
+       RULL(0x25030011), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_OPCG_CAPT2                                    ,
+       RULL(0x26030011), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_OPCG_CAPT2                                    ,
+       RULL(0x27030011), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_OPCG_CAPT2                                    ,
+       RULL(0x28030011), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_OPCG_CAPT2                                    ,
+       RULL(0x29030011), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_OPCG_CAPT2                                    ,
+       RULL(0x2A030011), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_OPCG_CAPT2                                    ,
+       RULL(0x2B030011), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_OPCG_CAPT2                                    ,
+       RULL(0x2C030011), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_OPCG_CAPT2                                    ,
+       RULL(0x2D030011), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_OPCG_CAPT2                                    ,
+       RULL(0x2E030011), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_OPCG_CAPT2                                    ,
+       RULL(0x2F030011), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_OPCG_CAPT2                                    ,
+       RULL(0x30030011), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_OPCG_CAPT2                                    ,
+       RULL(0x31030011), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_OPCG_CAPT2                                    ,
+       RULL(0x32030011), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_OPCG_CAPT2                                    ,
+       RULL(0x33030011), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_OPCG_CAPT2                                    ,
+       RULL(0x34030011), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_OPCG_CAPT2                                    ,
+       RULL(0x35030011), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_OPCG_CAPT2                                    ,
+       RULL(0x36030011), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_OPCG_CAPT2                                    ,
+       RULL(0x37030011), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_OPCG_CAPT3                                         ,
+       RULL(0x00030012), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_OPCG_CAPT3                                      ,
+       RULL(0x01030012), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_OPCG_CAPT3                                      ,
+       RULL(0x02030012), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_OPCG_CAPT3                                      ,
+       RULL(0x03030012), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_OPCG_CAPT3                                      ,
+       RULL(0x04030012), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_OPCG_CAPT3                                      ,
+       RULL(0x05030012), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_OPCG_CAPT3                                      ,
+       RULL(0x06030012), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_OPCG_CAPT3                                    ,
+       RULL(0x07030012), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_OPCG_CAPT3                                    ,
+       RULL(0x08030012), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_OPCG_CAPT3                                     ,
+       RULL(0x09030012), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_OPCG_CAPT3                                     ,
+       RULL(0x0C030012), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_OPCG_CAPT3                                    ,
+       RULL(0x0D030012), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_OPCG_CAPT3                                    ,
+       RULL(0x0E030012), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_OPCG_CAPT3                                    ,
+       RULL(0x0F030012), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_OPCG_CAPT3                                    ,
+       RULL(0x10030012), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_OPCG_CAPT3                                    ,
+       RULL(0x11030012), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_OPCG_CAPT3                                    ,
+       RULL(0x12030012), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_OPCG_CAPT3                                    ,
+       RULL(0x13030012), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_OPCG_CAPT3                                    ,
+       RULL(0x14030012), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_OPCG_CAPT3                                    ,
+       RULL(0x15030012), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_OPCG_CAPT3                                    ,
+       RULL(0x20030012), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_OPCG_CAPT3                                    ,
+       RULL(0x21030012), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_OPCG_CAPT3                                    ,
+       RULL(0x22030012), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_OPCG_CAPT3                                    ,
+       RULL(0x23030012), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_OPCG_CAPT3                                    ,
+       RULL(0x24030012), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_OPCG_CAPT3                                    ,
+       RULL(0x25030012), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_OPCG_CAPT3                                    ,
+       RULL(0x26030012), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_OPCG_CAPT3                                    ,
+       RULL(0x27030012), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_OPCG_CAPT3                                    ,
+       RULL(0x28030012), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_OPCG_CAPT3                                    ,
+       RULL(0x29030012), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_OPCG_CAPT3                                    ,
+       RULL(0x2A030012), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_OPCG_CAPT3                                    ,
+       RULL(0x2B030012), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_OPCG_CAPT3                                    ,
+       RULL(0x2C030012), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_OPCG_CAPT3                                    ,
+       RULL(0x2D030012), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_OPCG_CAPT3                                    ,
+       RULL(0x2E030012), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_OPCG_CAPT3                                    ,
+       RULL(0x2F030012), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_OPCG_CAPT3                                    ,
+       RULL(0x30030012), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_OPCG_CAPT3                                    ,
+       RULL(0x31030012), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_OPCG_CAPT3                                    ,
+       RULL(0x32030012), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_OPCG_CAPT3                                    ,
+       RULL(0x33030012), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_OPCG_CAPT3                                    ,
+       RULL(0x34030012), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_OPCG_CAPT3                                    ,
+       RULL(0x35030012), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_OPCG_CAPT3                                    ,
+       RULL(0x36030012), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_OPCG_CAPT3                                    ,
+       RULL(0x37030012), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_OPCG_REG0                                          ,
+       RULL(0x00030002), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_OPCG_REG0                                       ,
+       RULL(0x01030002), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_OPCG_REG0                                       ,
+       RULL(0x02030002), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_OPCG_REG0                                       ,
+       RULL(0x03030002), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_OPCG_REG0                                       ,
+       RULL(0x04030002), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_OPCG_REG0                                       ,
+       RULL(0x05030002), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_OPCG_REG0                                       ,
+       RULL(0x06030002), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_OPCG_REG0                                     ,
+       RULL(0x07030002), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_OPCG_REG0                                     ,
+       RULL(0x08030002), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_OPCG_REG0                                      ,
+       RULL(0x09030002), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_OPCG_REG0                                      ,
+       RULL(0x0C030002), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_OPCG_REG0                                     ,
+       RULL(0x0D030002), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_OPCG_REG0                                     ,
+       RULL(0x0E030002), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_OPCG_REG0                                     ,
+       RULL(0x0F030002), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_OPCG_REG0                                     ,
+       RULL(0x10030002), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_OPCG_REG0                                     ,
+       RULL(0x11030002), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_OPCG_REG0                                     ,
+       RULL(0x12030002), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_OPCG_REG0                                     ,
+       RULL(0x13030002), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_OPCG_REG0                                     ,
+       RULL(0x14030002), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_OPCG_REG0                                     ,
+       RULL(0x15030002), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_OPCG_REG0                                     ,
+       RULL(0x20030002), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_OPCG_REG0                                     ,
+       RULL(0x21030002), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_OPCG_REG0                                     ,
+       RULL(0x22030002), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_OPCG_REG0                                     ,
+       RULL(0x23030002), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_OPCG_REG0                                     ,
+       RULL(0x24030002), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_OPCG_REG0                                     ,
+       RULL(0x25030002), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_OPCG_REG0                                     ,
+       RULL(0x26030002), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_OPCG_REG0                                     ,
+       RULL(0x27030002), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_OPCG_REG0                                     ,
+       RULL(0x28030002), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_OPCG_REG0                                     ,
+       RULL(0x29030002), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_OPCG_REG0                                     ,
+       RULL(0x2A030002), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_OPCG_REG0                                     ,
+       RULL(0x2B030002), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_OPCG_REG0                                     ,
+       RULL(0x2C030002), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_OPCG_REG0                                     ,
+       RULL(0x2D030002), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_OPCG_REG0                                     ,
+       RULL(0x2E030002), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_OPCG_REG0                                     ,
+       RULL(0x2F030002), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_OPCG_REG0                                     ,
+       RULL(0x30030002), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_OPCG_REG0                                     ,
+       RULL(0x31030002), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_OPCG_REG0                                     ,
+       RULL(0x32030002), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_OPCG_REG0                                     ,
+       RULL(0x33030002), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_OPCG_REG0                                     ,
+       RULL(0x34030002), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_OPCG_REG0                                     ,
+       RULL(0x35030002), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_OPCG_REG0                                     ,
+       RULL(0x36030002), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_OPCG_REG0                                     ,
+       RULL(0x37030002), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_OPCG_REG1                                          ,
+       RULL(0x00030003), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_OPCG_REG1                                       ,
+       RULL(0x01030003), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_OPCG_REG1                                       ,
+       RULL(0x02030003), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_OPCG_REG1                                       ,
+       RULL(0x03030003), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_OPCG_REG1                                       ,
+       RULL(0x04030003), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_OPCG_REG1                                       ,
+       RULL(0x05030003), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_OPCG_REG1                                       ,
+       RULL(0x06030003), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_OPCG_REG1                                     ,
+       RULL(0x07030003), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_OPCG_REG1                                     ,
+       RULL(0x08030003), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_OPCG_REG1                                      ,
+       RULL(0x09030003), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_OPCG_REG1                                      ,
+       RULL(0x0C030003), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_OPCG_REG1                                     ,
+       RULL(0x0D030003), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_OPCG_REG1                                     ,
+       RULL(0x0E030003), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_OPCG_REG1                                     ,
+       RULL(0x0F030003), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_OPCG_REG1                                     ,
+       RULL(0x10030003), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_OPCG_REG1                                     ,
+       RULL(0x11030003), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_OPCG_REG1                                     ,
+       RULL(0x12030003), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_OPCG_REG1                                     ,
+       RULL(0x13030003), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_OPCG_REG1                                     ,
+       RULL(0x14030003), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_OPCG_REG1                                     ,
+       RULL(0x15030003), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_OPCG_REG1                                     ,
+       RULL(0x20030003), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_OPCG_REG1                                     ,
+       RULL(0x21030003), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_OPCG_REG1                                     ,
+       RULL(0x22030003), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_OPCG_REG1                                     ,
+       RULL(0x23030003), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_OPCG_REG1                                     ,
+       RULL(0x24030003), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_OPCG_REG1                                     ,
+       RULL(0x25030003), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_OPCG_REG1                                     ,
+       RULL(0x26030003), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_OPCG_REG1                                     ,
+       RULL(0x27030003), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_OPCG_REG1                                     ,
+       RULL(0x28030003), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_OPCG_REG1                                     ,
+       RULL(0x29030003), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_OPCG_REG1                                     ,
+       RULL(0x2A030003), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_OPCG_REG1                                     ,
+       RULL(0x2B030003), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_OPCG_REG1                                     ,
+       RULL(0x2C030003), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_OPCG_REG1                                     ,
+       RULL(0x2D030003), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_OPCG_REG1                                     ,
+       RULL(0x2E030003), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_OPCG_REG1                                     ,
+       RULL(0x2F030003), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_OPCG_REG1                                     ,
+       RULL(0x30030003), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_OPCG_REG1                                     ,
+       RULL(0x31030003), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_OPCG_REG1                                     ,
+       RULL(0x32030003), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_OPCG_REG1                                     ,
+       RULL(0x33030003), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_OPCG_REG1                                     ,
+       RULL(0x34030003), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_OPCG_REG1                                     ,
+       RULL(0x35030003), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_OPCG_REG1                                     ,
+       RULL(0x36030003), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_OPCG_REG1                                     ,
+       RULL(0x37030003), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_OPCG_REG2                                          ,
+       RULL(0x00030004), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_OPCG_REG2                                       ,
+       RULL(0x01030004), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_OPCG_REG2                                       ,
+       RULL(0x02030004), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_OPCG_REG2                                       ,
+       RULL(0x03030004), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_OPCG_REG2                                       ,
+       RULL(0x04030004), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_OPCG_REG2                                       ,
+       RULL(0x05030004), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_OPCG_REG2                                       ,
+       RULL(0x06030004), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_OPCG_REG2                                     ,
+       RULL(0x07030004), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_OPCG_REG2                                     ,
+       RULL(0x08030004), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_OPCG_REG2                                      ,
+       RULL(0x09030004), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_OPCG_REG2                                      ,
+       RULL(0x0C030004), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_OPCG_REG2                                     ,
+       RULL(0x0D030004), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_OPCG_REG2                                     ,
+       RULL(0x0E030004), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_OPCG_REG2                                     ,
+       RULL(0x0F030004), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_OPCG_REG2                                     ,
+       RULL(0x10030004), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_OPCG_REG2                                     ,
+       RULL(0x11030004), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_OPCG_REG2                                     ,
+       RULL(0x12030004), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_OPCG_REG2                                     ,
+       RULL(0x13030004), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_OPCG_REG2                                     ,
+       RULL(0x14030004), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_OPCG_REG2                                     ,
+       RULL(0x15030004), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_OPCG_REG2                                     ,
+       RULL(0x20030004), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_OPCG_REG2                                     ,
+       RULL(0x21030004), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_OPCG_REG2                                     ,
+       RULL(0x22030004), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_OPCG_REG2                                     ,
+       RULL(0x23030004), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_OPCG_REG2                                     ,
+       RULL(0x24030004), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_OPCG_REG2                                     ,
+       RULL(0x25030004), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_OPCG_REG2                                     ,
+       RULL(0x26030004), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_OPCG_REG2                                     ,
+       RULL(0x27030004), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_OPCG_REG2                                     ,
+       RULL(0x28030004), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_OPCG_REG2                                     ,
+       RULL(0x29030004), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_OPCG_REG2                                     ,
+       RULL(0x2A030004), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_OPCG_REG2                                     ,
+       RULL(0x2B030004), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_OPCG_REG2                                     ,
+       RULL(0x2C030004), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_OPCG_REG2                                     ,
+       RULL(0x2D030004), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_OPCG_REG2                                     ,
+       RULL(0x2E030004), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_OPCG_REG2                                     ,
+       RULL(0x2F030004), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_OPCG_REG2                                     ,
+       RULL(0x30030004), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_OPCG_REG2                                     ,
+       RULL(0x31030004), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_OPCG_REG2                                     ,
+       RULL(0x32030004), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_OPCG_REG2                                     ,
+       RULL(0x33030004), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_OPCG_REG2                                     ,
+       RULL(0x34030004), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_OPCG_REG2                                     ,
+       RULL(0x35030004), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_OPCG_REG2                                     ,
+       RULL(0x36030004), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_OPCG_REG2                                     ,
+       RULL(0x37030004), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG32( PERV_PEEK4A0_FSI                                        ,
+       RULL(0x000004A0), SH_UNT_PERV     , SH_ACS_FSI       );
+
+REG32( PERV_PEEK4A4_FSI                                        ,
+       RULL(0x000004A4), SH_UNT_PERV     , SH_ACS_FSI       );
+
+REG32( PERV_PEEK4A8_FSI                                        ,
+       RULL(0x000004A8), SH_UNT_PERV     , SH_ACS_FSI       );
+
+REG32( PERV_PEEK4AC_FSI                                        ,
+       RULL(0x000004AC), SH_UNT_PERV     , SH_ACS_FSI       );
+
+REG32( PERV_PEEK4B0_FSI                                        ,
+       RULL(0x000004B0), SH_UNT_PERV     , SH_ACS_FSI       );
+
+REG32( PERV_PEEK4B4_FSI                                        ,
+       RULL(0x000004B4), SH_UNT_PERV     , SH_ACS_FSI       );
+
+REG32( PERV_PEEK4B8_FSI                                        ,
+       RULL(0x000004B8), SH_UNT_PERV     , SH_ACS_FSI       );
+
+REG32( PERV_PERV_CTRL0_FSI                                     ,
+       RULL(0x0000281A), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_PERV_CTRL0_FSI_BYTE                                ,
+       RULL(0x00002868), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_PERV_CTRL0_SCOM                                    ,
+       RULL(0x0005001A), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_PERV_CTRL0                                     ,
+       RULL(0x0005001A), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_PERV_CTRL0_COPY_FSI                                ,
+       RULL(0x0000291A), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_PERV_CTRL0_COPY_FSI_BYTE                           ,
+       RULL(0x00002968), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_PERV_CTRL0_COPY_SCOM                               ,
+       RULL(0x0005011A), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_PERV_CTRL0_COPY                                ,
+       RULL(0x0005011A), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_PERV_CTRL1_FSI                                     ,
+       RULL(0x0000281B), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_PERV_CTRL1_FSI_BYTE                                ,
+       RULL(0x0000286C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_PERV_CTRL1_SCOM                                    ,
+       RULL(0x0005001B), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_PERV_CTRL1                                     ,
+       RULL(0x0005001B), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_PERV_CTRL1_COPY_FSI                                ,
+       RULL(0x0000291B), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_PERV_CTRL1_COPY_FSI_BYTE                           ,
+       RULL(0x0000296C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_PERV_CTRL1_COPY_SCOM                               ,
+       RULL(0x0005011B), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_PERV_CTRL1_COPY                                ,
+       RULL(0x0005011B), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_PLL_LOCK_REG                                       ,
+       RULL(0x000F0019), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_PLL_LOCK_REG                                    ,
+       RULL(0x010F0019), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_PLL_LOCK_REG                                    ,
+       RULL(0x020F0019), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_PLL_LOCK_REG                                    ,
+       RULL(0x030F0019), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_PLL_LOCK_REG                                    ,
+       RULL(0x040F0019), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_PLL_LOCK_REG                                    ,
+       RULL(0x050F0019), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_PLL_LOCK_REG                                    ,
+       RULL(0x060F0019), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_PLL_LOCK_REG                                  ,
+       RULL(0x070F0019), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_PLL_LOCK_REG                                  ,
+       RULL(0x080F0019), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_PLL_LOCK_REG                                   ,
+       RULL(0x090F0019), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_PLL_LOCK_REG                                   ,
+       RULL(0x0C0F0019), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_PLL_LOCK_REG                                  ,
+       RULL(0x0D0F0019), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_PLL_LOCK_REG                                  ,
+       RULL(0x0E0F0019), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_PLL_LOCK_REG                                  ,
+       RULL(0x0F0F0019), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_PLL_LOCK_REG                                  ,
+       RULL(0x100F0019), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PLL_LOCK_REG                                  ,
+       RULL(0x110F0019), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PLL_LOCK_REG                                  ,
+       RULL(0x120F0019), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PLL_LOCK_REG                                  ,
+       RULL(0x130F0019), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PLL_LOCK_REG                                  ,
+       RULL(0x140F0019), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PLL_LOCK_REG                                  ,
+       RULL(0x150F0019), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PLL_LOCK_REG                                  ,
+       RULL(0x200F0019), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PLL_LOCK_REG                                  ,
+       RULL(0x210F0019), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PLL_LOCK_REG                                  ,
+       RULL(0x220F0019), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PLL_LOCK_REG                                  ,
+       RULL(0x230F0019), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PLL_LOCK_REG                                  ,
+       RULL(0x240F0019), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PLL_LOCK_REG                                  ,
+       RULL(0x250F0019), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PLL_LOCK_REG                                  ,
+       RULL(0x260F0019), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PLL_LOCK_REG                                  ,
+       RULL(0x270F0019), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PLL_LOCK_REG                                  ,
+       RULL(0x280F0019), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PLL_LOCK_REG                                  ,
+       RULL(0x290F0019), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PLL_LOCK_REG                                  ,
+       RULL(0x2A0F0019), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PLL_LOCK_REG                                  ,
+       RULL(0x2B0F0019), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PLL_LOCK_REG                                  ,
+       RULL(0x2C0F0019), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PLL_LOCK_REG                                  ,
+       RULL(0x2D0F0019), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PLL_LOCK_REG                                  ,
+       RULL(0x2E0F0019), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PLL_LOCK_REG                                  ,
+       RULL(0x2F0F0019), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PLL_LOCK_REG                                  ,
+       RULL(0x300F0019), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PLL_LOCK_REG                                  ,
+       RULL(0x310F0019), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PLL_LOCK_REG                                  ,
+       RULL(0x320F0019), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PLL_LOCK_REG                                  ,
+       RULL(0x330F0019), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PLL_LOCK_REG                                  ,
+       RULL(0x340F0019), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PLL_LOCK_REG                                  ,
+       RULL(0x350F0019), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PLL_LOCK_REG                                  ,
+       RULL(0x360F0019), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PLL_LOCK_REG                                  ,
+       RULL(0x370F0019), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_PPE_XIDBGPRO                                       ,
+       RULL(0x00000415), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_PPE_XIDBGPRO                                   ,
+       RULL(0x00000415), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_PPE_XIRAMDBG                                       ,
+       RULL(0x00000413), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_PPE_XIRAMDBG                                   ,
+       RULL(0x00000413), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_PPE_XIRAMEDR                                       ,
+       RULL(0x00000414), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_PPE_XIRAMEDR                                   ,
+       RULL(0x00000414), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_PPE_XIRAMGA                                        ,
+       RULL(0x00000412), SH_UNT_PERV     , SH_ACS_SCOM_WO   );
+REG64( PERV_PIB_PPE_XIRAMGA                                    ,
+       RULL(0x00000412), SH_UNT_PERV_0   , SH_ACS_SCOM_WO   );
+
+REG64( PERV_PPE_XIRAMRA                                        ,
+       RULL(0x00000411), SH_UNT_PERV     , SH_ACS_SCOM_WO   );
+REG64( PERV_PIB_PPE_XIRAMRA                                    ,
+       RULL(0x00000411), SH_UNT_PERV_0   , SH_ACS_SCOM_WO   );
+
+REG64( PERV_PPE_XIXCR                                          ,
+       RULL(0x00000410), SH_UNT_PERV     , SH_ACS_SCOM_WO   );
+REG64( PERV_PIB_PPE_XIXCR                                      ,
+       RULL(0x00000410), SH_UNT_PERV_0   , SH_ACS_SCOM_WO   );
+
+REG64( PERV_EP00_PPM_CGCR                                      ,
+       RULL(0x100F0165), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_PPM_CGCR_CLEAR                                ,
+       RULL(0x100F0167), SH_UNT_PERV_16  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP00_PPM_CGCR_OR                                   ,
+       RULL(0x100F0166), SH_UNT_PERV_16  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP01_PPM_CGCR                                      ,
+       RULL(0x110F0165), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_CGCR_CLEAR                                ,
+       RULL(0x110F0167), SH_UNT_PERV_17  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP01_PPM_CGCR_OR                                   ,
+       RULL(0x110F0166), SH_UNT_PERV_17  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP02_PPM_CGCR                                      ,
+       RULL(0x120F0165), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_CGCR_CLEAR                                ,
+       RULL(0x120F0167), SH_UNT_PERV_18  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP02_PPM_CGCR_OR                                   ,
+       RULL(0x120F0166), SH_UNT_PERV_18  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP03_PPM_CGCR                                      ,
+       RULL(0x130F0165), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_CGCR_CLEAR                                ,
+       RULL(0x130F0167), SH_UNT_PERV_19  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP03_PPM_CGCR_OR                                   ,
+       RULL(0x130F0166), SH_UNT_PERV_19  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP04_PPM_CGCR                                      ,
+       RULL(0x140F0165), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_CGCR_CLEAR                                ,
+       RULL(0x140F0167), SH_UNT_PERV_20  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP04_PPM_CGCR_OR                                   ,
+       RULL(0x140F0166), SH_UNT_PERV_20  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP05_PPM_CGCR                                      ,
+       RULL(0x150F0165), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_CGCR_CLEAR                                ,
+       RULL(0x150F0167), SH_UNT_PERV_21  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP05_PPM_CGCR_OR                                   ,
+       RULL(0x150F0166), SH_UNT_PERV_21  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC00_PPM_CGCR                                      ,
+       RULL(0x200F0165), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_CGCR_CLEAR                                ,
+       RULL(0x200F0167), SH_UNT_PERV_32  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC00_PPM_CGCR_OR                                   ,
+       RULL(0x200F0166), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_PPM_CGCR                                      ,
+       RULL(0x210F0165), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_CGCR_CLEAR                                ,
+       RULL(0x210F0167), SH_UNT_PERV_33  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC01_PPM_CGCR_OR                                   ,
+       RULL(0x210F0166), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_PPM_CGCR                                      ,
+       RULL(0x220F0165), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_CGCR_CLEAR                                ,
+       RULL(0x220F0167), SH_UNT_PERV_34  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC02_PPM_CGCR_OR                                   ,
+       RULL(0x220F0166), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_PPM_CGCR                                      ,
+       RULL(0x230F0165), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_CGCR_CLEAR                                ,
+       RULL(0x230F0167), SH_UNT_PERV_35  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC03_PPM_CGCR_OR                                   ,
+       RULL(0x230F0166), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_PPM_CGCR                                      ,
+       RULL(0x240F0165), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_CGCR_CLEAR                                ,
+       RULL(0x240F0167), SH_UNT_PERV_36  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC04_PPM_CGCR_OR                                   ,
+       RULL(0x240F0166), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_PPM_CGCR                                      ,
+       RULL(0x250F0165), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_CGCR_CLEAR                                ,
+       RULL(0x250F0167), SH_UNT_PERV_37  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC05_PPM_CGCR_OR                                   ,
+       RULL(0x250F0166), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_PPM_CGCR                                      ,
+       RULL(0x260F0165), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_CGCR_CLEAR                                ,
+       RULL(0x260F0167), SH_UNT_PERV_38  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC06_PPM_CGCR_OR                                   ,
+       RULL(0x260F0166), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_PPM_CGCR                                      ,
+       RULL(0x270F0165), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_CGCR_CLEAR                                ,
+       RULL(0x270F0167), SH_UNT_PERV_39  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC07_PPM_CGCR_OR                                   ,
+       RULL(0x270F0166), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_PPM_CGCR                                      ,
+       RULL(0x280F0165), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_CGCR_CLEAR                                ,
+       RULL(0x280F0167), SH_UNT_PERV_40  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC08_PPM_CGCR_OR                                   ,
+       RULL(0x280F0166), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_PPM_CGCR                                      ,
+       RULL(0x290F0165), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_CGCR_CLEAR                                ,
+       RULL(0x290F0167), SH_UNT_PERV_41  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC09_PPM_CGCR_OR                                   ,
+       RULL(0x290F0166), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_PPM_CGCR                                      ,
+       RULL(0x2A0F0165), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_CGCR_CLEAR                                ,
+       RULL(0x2A0F0167), SH_UNT_PERV_42  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC10_PPM_CGCR_OR                                   ,
+       RULL(0x2A0F0166), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_PPM_CGCR                                      ,
+       RULL(0x2B0F0165), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_CGCR_CLEAR                                ,
+       RULL(0x2B0F0167), SH_UNT_PERV_43  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC11_PPM_CGCR_OR                                   ,
+       RULL(0x2B0F0166), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_PPM_CGCR                                      ,
+       RULL(0x2C0F0165), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_CGCR_CLEAR                                ,
+       RULL(0x2C0F0167), SH_UNT_PERV_44  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC12_PPM_CGCR_OR                                   ,
+       RULL(0x2C0F0166), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_PPM_CGCR                                      ,
+       RULL(0x2D0F0165), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_CGCR_CLEAR                                ,
+       RULL(0x2D0F0167), SH_UNT_PERV_45  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC13_PPM_CGCR_OR                                   ,
+       RULL(0x2D0F0166), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_PPM_CGCR                                      ,
+       RULL(0x2E0F0165), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_CGCR_CLEAR                                ,
+       RULL(0x2E0F0167), SH_UNT_PERV_46  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC14_PPM_CGCR_OR                                   ,
+       RULL(0x2E0F0166), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_PPM_CGCR                                      ,
+       RULL(0x2F0F0165), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_CGCR_CLEAR                                ,
+       RULL(0x2F0F0167), SH_UNT_PERV_47  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC15_PPM_CGCR_OR                                   ,
+       RULL(0x2F0F0166), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_PPM_CGCR                                      ,
+       RULL(0x300F0165), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_CGCR_CLEAR                                ,
+       RULL(0x300F0167), SH_UNT_PERV_48  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC16_PPM_CGCR_OR                                   ,
+       RULL(0x300F0166), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_PPM_CGCR                                      ,
+       RULL(0x310F0165), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_CGCR_CLEAR                                ,
+       RULL(0x310F0167), SH_UNT_PERV_49  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC17_PPM_CGCR_OR                                   ,
+       RULL(0x310F0166), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_PPM_CGCR                                      ,
+       RULL(0x320F0165), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_CGCR_CLEAR                                ,
+       RULL(0x320F0167), SH_UNT_PERV_50  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC18_PPM_CGCR_OR                                   ,
+       RULL(0x320F0166), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_PPM_CGCR                                      ,
+       RULL(0x330F0165), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_CGCR_CLEAR                                ,
+       RULL(0x330F0167), SH_UNT_PERV_51  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC19_PPM_CGCR_OR                                   ,
+       RULL(0x330F0166), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_PPM_CGCR                                      ,
+       RULL(0x340F0165), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_CGCR_CLEAR                                ,
+       RULL(0x340F0167), SH_UNT_PERV_52  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC20_PPM_CGCR_OR                                   ,
+       RULL(0x340F0166), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_PPM_CGCR                                      ,
+       RULL(0x350F0165), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_CGCR_CLEAR                                ,
+       RULL(0x350F0167), SH_UNT_PERV_53  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC21_PPM_CGCR_OR                                   ,
+       RULL(0x350F0166), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_PPM_CGCR                                      ,
+       RULL(0x360F0165), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_CGCR_CLEAR                                ,
+       RULL(0x360F0167), SH_UNT_PERV_54  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC22_PPM_CGCR_OR                                   ,
+       RULL(0x360F0166), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_PPM_CGCR                                      ,
+       RULL(0x370F0165), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_CGCR_CLEAR                                ,
+       RULL(0x370F0167), SH_UNT_PERV_55  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC23_PPM_CGCR_OR                                   ,
+       RULL(0x370F0166), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EP00_PPM_GPMMR_SCOM                                ,
+       RULL(0x100F0100), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP00_PPM_GPMMR_SCOM1                               ,
+       RULL(0x100F0101), SH_UNT_PERV_16  , SH_ACS_SCOM1     );
+REG64( PERV_EP00_PPM_GPMMR_SCOM2                               ,
+       RULL(0x100F0102), SH_UNT_PERV_16  , SH_ACS_SCOM2     );
+REG64( PERV_EP01_PPM_GPMMR_SCOM                                ,
+       RULL(0x110F0100), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PPM_GPMMR_SCOM1                               ,
+       RULL(0x110F0101), SH_UNT_PERV_17  , SH_ACS_SCOM1     );
+REG64( PERV_EP01_PPM_GPMMR_SCOM2                               ,
+       RULL(0x110F0102), SH_UNT_PERV_17  , SH_ACS_SCOM2     );
+REG64( PERV_EP02_PPM_GPMMR_SCOM                                ,
+       RULL(0x120F0100), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PPM_GPMMR_SCOM1                               ,
+       RULL(0x120F0101), SH_UNT_PERV_18  , SH_ACS_SCOM1     );
+REG64( PERV_EP02_PPM_GPMMR_SCOM2                               ,
+       RULL(0x120F0102), SH_UNT_PERV_18  , SH_ACS_SCOM2     );
+REG64( PERV_EP03_PPM_GPMMR_SCOM                                ,
+       RULL(0x130F0100), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PPM_GPMMR_SCOM1                               ,
+       RULL(0x130F0101), SH_UNT_PERV_19  , SH_ACS_SCOM1     );
+REG64( PERV_EP03_PPM_GPMMR_SCOM2                               ,
+       RULL(0x130F0102), SH_UNT_PERV_19  , SH_ACS_SCOM2     );
+REG64( PERV_EP04_PPM_GPMMR_SCOM                                ,
+       RULL(0x140F0100), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PPM_GPMMR_SCOM1                               ,
+       RULL(0x140F0101), SH_UNT_PERV_20  , SH_ACS_SCOM1     );
+REG64( PERV_EP04_PPM_GPMMR_SCOM2                               ,
+       RULL(0x140F0102), SH_UNT_PERV_20  , SH_ACS_SCOM2     );
+REG64( PERV_EP05_PPM_GPMMR_SCOM                                ,
+       RULL(0x150F0100), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PPM_GPMMR_SCOM1                               ,
+       RULL(0x150F0101), SH_UNT_PERV_21  , SH_ACS_SCOM1     );
+REG64( PERV_EP05_PPM_GPMMR_SCOM2                               ,
+       RULL(0x150F0102), SH_UNT_PERV_21  , SH_ACS_SCOM2     );
+REG64( PERV_EC00_PPM_GPMMR_SCOM                                ,
+       RULL(0x200F0100), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PPM_GPMMR_SCOM1                               ,
+       RULL(0x200F0101), SH_UNT_PERV_32  , SH_ACS_SCOM1     );
+REG64( PERV_EC00_PPM_GPMMR_SCOM2                               ,
+       RULL(0x200F0102), SH_UNT_PERV_32  , SH_ACS_SCOM2     );
+REG64( PERV_EC01_PPM_GPMMR_SCOM                                ,
+       RULL(0x210F0100), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PPM_GPMMR_SCOM1                               ,
+       RULL(0x210F0101), SH_UNT_PERV_33  , SH_ACS_SCOM1     );
+REG64( PERV_EC01_PPM_GPMMR_SCOM2                               ,
+       RULL(0x210F0102), SH_UNT_PERV_33  , SH_ACS_SCOM2     );
+REG64( PERV_EC02_PPM_GPMMR_SCOM                                ,
+       RULL(0x220F0100), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PPM_GPMMR_SCOM1                               ,
+       RULL(0x220F0101), SH_UNT_PERV_34  , SH_ACS_SCOM1     );
+REG64( PERV_EC02_PPM_GPMMR_SCOM2                               ,
+       RULL(0x220F0102), SH_UNT_PERV_34  , SH_ACS_SCOM2     );
+REG64( PERV_EC03_PPM_GPMMR_SCOM                                ,
+       RULL(0x230F0100), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PPM_GPMMR_SCOM1                               ,
+       RULL(0x230F0101), SH_UNT_PERV_35  , SH_ACS_SCOM1     );
+REG64( PERV_EC03_PPM_GPMMR_SCOM2                               ,
+       RULL(0x230F0102), SH_UNT_PERV_35  , SH_ACS_SCOM2     );
+REG64( PERV_EC04_PPM_GPMMR_SCOM                                ,
+       RULL(0x240F0100), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PPM_GPMMR_SCOM1                               ,
+       RULL(0x240F0101), SH_UNT_PERV_36  , SH_ACS_SCOM1     );
+REG64( PERV_EC04_PPM_GPMMR_SCOM2                               ,
+       RULL(0x240F0102), SH_UNT_PERV_36  , SH_ACS_SCOM2     );
+REG64( PERV_EC05_PPM_GPMMR_SCOM                                ,
+       RULL(0x250F0100), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PPM_GPMMR_SCOM1                               ,
+       RULL(0x250F0101), SH_UNT_PERV_37  , SH_ACS_SCOM1     );
+REG64( PERV_EC05_PPM_GPMMR_SCOM2                               ,
+       RULL(0x250F0102), SH_UNT_PERV_37  , SH_ACS_SCOM2     );
+REG64( PERV_EC06_PPM_GPMMR_SCOM                                ,
+       RULL(0x260F0100), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PPM_GPMMR_SCOM1                               ,
+       RULL(0x260F0101), SH_UNT_PERV_38  , SH_ACS_SCOM1     );
+REG64( PERV_EC06_PPM_GPMMR_SCOM2                               ,
+       RULL(0x260F0102), SH_UNT_PERV_38  , SH_ACS_SCOM2     );
+REG64( PERV_EC07_PPM_GPMMR_SCOM                                ,
+       RULL(0x270F0100), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PPM_GPMMR_SCOM1                               ,
+       RULL(0x270F0101), SH_UNT_PERV_39  , SH_ACS_SCOM1     );
+REG64( PERV_EC07_PPM_GPMMR_SCOM2                               ,
+       RULL(0x270F0102), SH_UNT_PERV_39  , SH_ACS_SCOM2     );
+REG64( PERV_EC08_PPM_GPMMR_SCOM                                ,
+       RULL(0x280F0100), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PPM_GPMMR_SCOM1                               ,
+       RULL(0x280F0101), SH_UNT_PERV_40  , SH_ACS_SCOM1     );
+REG64( PERV_EC08_PPM_GPMMR_SCOM2                               ,
+       RULL(0x280F0102), SH_UNT_PERV_40  , SH_ACS_SCOM2     );
+REG64( PERV_EC09_PPM_GPMMR_SCOM                                ,
+       RULL(0x290F0100), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PPM_GPMMR_SCOM1                               ,
+       RULL(0x290F0101), SH_UNT_PERV_41  , SH_ACS_SCOM1     );
+REG64( PERV_EC09_PPM_GPMMR_SCOM2                               ,
+       RULL(0x290F0102), SH_UNT_PERV_41  , SH_ACS_SCOM2     );
+REG64( PERV_EC10_PPM_GPMMR_SCOM                                ,
+       RULL(0x2A0F0100), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PPM_GPMMR_SCOM1                               ,
+       RULL(0x2A0F0101), SH_UNT_PERV_42  , SH_ACS_SCOM1     );
+REG64( PERV_EC10_PPM_GPMMR_SCOM2                               ,
+       RULL(0x2A0F0102), SH_UNT_PERV_42  , SH_ACS_SCOM2     );
+REG64( PERV_EC11_PPM_GPMMR_SCOM                                ,
+       RULL(0x2B0F0100), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PPM_GPMMR_SCOM1                               ,
+       RULL(0x2B0F0101), SH_UNT_PERV_43  , SH_ACS_SCOM1     );
+REG64( PERV_EC11_PPM_GPMMR_SCOM2                               ,
+       RULL(0x2B0F0102), SH_UNT_PERV_43  , SH_ACS_SCOM2     );
+REG64( PERV_EC12_PPM_GPMMR_SCOM                                ,
+       RULL(0x2C0F0100), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PPM_GPMMR_SCOM1                               ,
+       RULL(0x2C0F0101), SH_UNT_PERV_44  , SH_ACS_SCOM1     );
+REG64( PERV_EC12_PPM_GPMMR_SCOM2                               ,
+       RULL(0x2C0F0102), SH_UNT_PERV_44  , SH_ACS_SCOM2     );
+REG64( PERV_EC13_PPM_GPMMR_SCOM                                ,
+       RULL(0x2D0F0100), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PPM_GPMMR_SCOM1                               ,
+       RULL(0x2D0F0101), SH_UNT_PERV_45  , SH_ACS_SCOM1     );
+REG64( PERV_EC13_PPM_GPMMR_SCOM2                               ,
+       RULL(0x2D0F0102), SH_UNT_PERV_45  , SH_ACS_SCOM2     );
+REG64( PERV_EC14_PPM_GPMMR_SCOM                                ,
+       RULL(0x2E0F0100), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PPM_GPMMR_SCOM1                               ,
+       RULL(0x2E0F0101), SH_UNT_PERV_46  , SH_ACS_SCOM1     );
+REG64( PERV_EC14_PPM_GPMMR_SCOM2                               ,
+       RULL(0x2E0F0102), SH_UNT_PERV_46  , SH_ACS_SCOM2     );
+REG64( PERV_EC15_PPM_GPMMR_SCOM                                ,
+       RULL(0x2F0F0100), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PPM_GPMMR_SCOM1                               ,
+       RULL(0x2F0F0101), SH_UNT_PERV_47  , SH_ACS_SCOM1     );
+REG64( PERV_EC15_PPM_GPMMR_SCOM2                               ,
+       RULL(0x2F0F0102), SH_UNT_PERV_47  , SH_ACS_SCOM2     );
+REG64( PERV_EC16_PPM_GPMMR_SCOM                                ,
+       RULL(0x300F0100), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PPM_GPMMR_SCOM1                               ,
+       RULL(0x300F0101), SH_UNT_PERV_48  , SH_ACS_SCOM1     );
+REG64( PERV_EC16_PPM_GPMMR_SCOM2                               ,
+       RULL(0x300F0102), SH_UNT_PERV_48  , SH_ACS_SCOM2     );
+REG64( PERV_EC17_PPM_GPMMR_SCOM                                ,
+       RULL(0x310F0100), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PPM_GPMMR_SCOM1                               ,
+       RULL(0x310F0101), SH_UNT_PERV_49  , SH_ACS_SCOM1     );
+REG64( PERV_EC17_PPM_GPMMR_SCOM2                               ,
+       RULL(0x310F0102), SH_UNT_PERV_49  , SH_ACS_SCOM2     );
+REG64( PERV_EC18_PPM_GPMMR_SCOM                                ,
+       RULL(0x320F0100), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PPM_GPMMR_SCOM1                               ,
+       RULL(0x320F0101), SH_UNT_PERV_50  , SH_ACS_SCOM1     );
+REG64( PERV_EC18_PPM_GPMMR_SCOM2                               ,
+       RULL(0x320F0102), SH_UNT_PERV_50  , SH_ACS_SCOM2     );
+REG64( PERV_EC19_PPM_GPMMR_SCOM                                ,
+       RULL(0x330F0100), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PPM_GPMMR_SCOM1                               ,
+       RULL(0x330F0101), SH_UNT_PERV_51  , SH_ACS_SCOM1     );
+REG64( PERV_EC19_PPM_GPMMR_SCOM2                               ,
+       RULL(0x330F0102), SH_UNT_PERV_51  , SH_ACS_SCOM2     );
+REG64( PERV_EC20_PPM_GPMMR_SCOM                                ,
+       RULL(0x340F0100), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PPM_GPMMR_SCOM1                               ,
+       RULL(0x340F0101), SH_UNT_PERV_52  , SH_ACS_SCOM1     );
+REG64( PERV_EC20_PPM_GPMMR_SCOM2                               ,
+       RULL(0x340F0102), SH_UNT_PERV_52  , SH_ACS_SCOM2     );
+REG64( PERV_EC21_PPM_GPMMR_SCOM                                ,
+       RULL(0x350F0100), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PPM_GPMMR_SCOM1                               ,
+       RULL(0x350F0101), SH_UNT_PERV_53  , SH_ACS_SCOM1     );
+REG64( PERV_EC21_PPM_GPMMR_SCOM2                               ,
+       RULL(0x350F0102), SH_UNT_PERV_53  , SH_ACS_SCOM2     );
+REG64( PERV_EC22_PPM_GPMMR_SCOM                                ,
+       RULL(0x360F0100), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PPM_GPMMR_SCOM1                               ,
+       RULL(0x360F0101), SH_UNT_PERV_54  , SH_ACS_SCOM1     );
+REG64( PERV_EC22_PPM_GPMMR_SCOM2                               ,
+       RULL(0x360F0102), SH_UNT_PERV_54  , SH_ACS_SCOM2     );
+REG64( PERV_EC23_PPM_GPMMR_SCOM                                ,
+       RULL(0x370F0100), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PPM_GPMMR_SCOM1                               ,
+       RULL(0x370F0101), SH_UNT_PERV_55  , SH_ACS_SCOM1     );
+REG64( PERV_EC23_PPM_GPMMR_SCOM2                               ,
+       RULL(0x370F0102), SH_UNT_PERV_55  , SH_ACS_SCOM2     );
+
+REG64( PERV_EP00_PPM_IVRMAVR                                   ,
+       RULL(0x100F01B5), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_PPM_IVRMAVR                                   ,
+       RULL(0x110F01B5), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_PPM_IVRMAVR                                   ,
+       RULL(0x120F01B5), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_PPM_IVRMAVR                                   ,
+       RULL(0x130F01B5), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_PPM_IVRMAVR                                   ,
+       RULL(0x140F01B5), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_PPM_IVRMAVR                                   ,
+       RULL(0x150F01B5), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_PPM_IVRMAVR                                   ,
+       RULL(0x200F01B5), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_PPM_IVRMAVR                                   ,
+       RULL(0x210F01B5), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_PPM_IVRMAVR                                   ,
+       RULL(0x220F01B5), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_PPM_IVRMAVR                                   ,
+       RULL(0x230F01B5), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_PPM_IVRMAVR                                   ,
+       RULL(0x240F01B5), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_PPM_IVRMAVR                                   ,
+       RULL(0x250F01B5), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_PPM_IVRMAVR                                   ,
+       RULL(0x260F01B5), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_PPM_IVRMAVR                                   ,
+       RULL(0x270F01B5), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_PPM_IVRMAVR                                   ,
+       RULL(0x280F01B5), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_PPM_IVRMAVR                                   ,
+       RULL(0x290F01B5), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_PPM_IVRMAVR                                   ,
+       RULL(0x2A0F01B5), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_PPM_IVRMAVR                                   ,
+       RULL(0x2B0F01B5), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_PPM_IVRMAVR                                   ,
+       RULL(0x2C0F01B5), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_PPM_IVRMAVR                                   ,
+       RULL(0x2D0F01B5), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_PPM_IVRMAVR                                   ,
+       RULL(0x2E0F01B5), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_PPM_IVRMAVR                                   ,
+       RULL(0x2F0F01B5), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_PPM_IVRMAVR                                   ,
+       RULL(0x300F01B5), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_PPM_IVRMAVR                                   ,
+       RULL(0x310F01B5), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_PPM_IVRMAVR                                   ,
+       RULL(0x320F01B5), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_PPM_IVRMAVR                                   ,
+       RULL(0x330F01B5), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_PPM_IVRMAVR                                   ,
+       RULL(0x340F01B5), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_PPM_IVRMAVR                                   ,
+       RULL(0x350F01B5), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_PPM_IVRMAVR                                   ,
+       RULL(0x360F01B5), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_PPM_IVRMAVR                                   ,
+       RULL(0x370F01B5), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_EP00_PPM_IVRMCR                                    ,
+       RULL(0x100F01B0), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x100F01B1), SH_UNT_PERV_16  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP00_PPM_IVRMCR_OR                                 ,
+       RULL(0x100F01B2), SH_UNT_PERV_16  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP01_PPM_IVRMCR                                    ,
+       RULL(0x110F01B0), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x110F01B1), SH_UNT_PERV_17  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP01_PPM_IVRMCR_OR                                 ,
+       RULL(0x110F01B2), SH_UNT_PERV_17  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP02_PPM_IVRMCR                                    ,
+       RULL(0x120F01B0), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x120F01B1), SH_UNT_PERV_18  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP02_PPM_IVRMCR_OR                                 ,
+       RULL(0x120F01B2), SH_UNT_PERV_18  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP03_PPM_IVRMCR                                    ,
+       RULL(0x130F01B0), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x130F01B1), SH_UNT_PERV_19  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP03_PPM_IVRMCR_OR                                 ,
+       RULL(0x130F01B2), SH_UNT_PERV_19  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP04_PPM_IVRMCR                                    ,
+       RULL(0x140F01B0), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x140F01B1), SH_UNT_PERV_20  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP04_PPM_IVRMCR_OR                                 ,
+       RULL(0x140F01B2), SH_UNT_PERV_20  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP05_PPM_IVRMCR                                    ,
+       RULL(0x150F01B0), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x150F01B1), SH_UNT_PERV_21  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP05_PPM_IVRMCR_OR                                 ,
+       RULL(0x150F01B2), SH_UNT_PERV_21  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC00_PPM_IVRMCR                                    ,
+       RULL(0x200F01B0), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x200F01B1), SH_UNT_PERV_32  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC00_PPM_IVRMCR_OR                                 ,
+       RULL(0x200F01B2), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_PPM_IVRMCR                                    ,
+       RULL(0x210F01B0), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x210F01B1), SH_UNT_PERV_33  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC01_PPM_IVRMCR_OR                                 ,
+       RULL(0x210F01B2), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_PPM_IVRMCR                                    ,
+       RULL(0x220F01B0), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x220F01B1), SH_UNT_PERV_34  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC02_PPM_IVRMCR_OR                                 ,
+       RULL(0x220F01B2), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_PPM_IVRMCR                                    ,
+       RULL(0x230F01B0), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x230F01B1), SH_UNT_PERV_35  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC03_PPM_IVRMCR_OR                                 ,
+       RULL(0x230F01B2), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_PPM_IVRMCR                                    ,
+       RULL(0x240F01B0), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x240F01B1), SH_UNT_PERV_36  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC04_PPM_IVRMCR_OR                                 ,
+       RULL(0x240F01B2), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_PPM_IVRMCR                                    ,
+       RULL(0x250F01B0), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x250F01B1), SH_UNT_PERV_37  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC05_PPM_IVRMCR_OR                                 ,
+       RULL(0x250F01B2), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_PPM_IVRMCR                                    ,
+       RULL(0x260F01B0), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x260F01B1), SH_UNT_PERV_38  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC06_PPM_IVRMCR_OR                                 ,
+       RULL(0x260F01B2), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_PPM_IVRMCR                                    ,
+       RULL(0x270F01B0), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x270F01B1), SH_UNT_PERV_39  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC07_PPM_IVRMCR_OR                                 ,
+       RULL(0x270F01B2), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_PPM_IVRMCR                                    ,
+       RULL(0x280F01B0), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x280F01B1), SH_UNT_PERV_40  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC08_PPM_IVRMCR_OR                                 ,
+       RULL(0x280F01B2), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_PPM_IVRMCR                                    ,
+       RULL(0x290F01B0), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x290F01B1), SH_UNT_PERV_41  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC09_PPM_IVRMCR_OR                                 ,
+       RULL(0x290F01B2), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_PPM_IVRMCR                                    ,
+       RULL(0x2A0F01B0), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x2A0F01B1), SH_UNT_PERV_42  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC10_PPM_IVRMCR_OR                                 ,
+       RULL(0x2A0F01B2), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_PPM_IVRMCR                                    ,
+       RULL(0x2B0F01B0), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x2B0F01B1), SH_UNT_PERV_43  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC11_PPM_IVRMCR_OR                                 ,
+       RULL(0x2B0F01B2), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_PPM_IVRMCR                                    ,
+       RULL(0x2C0F01B0), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x2C0F01B1), SH_UNT_PERV_44  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC12_PPM_IVRMCR_OR                                 ,
+       RULL(0x2C0F01B2), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_PPM_IVRMCR                                    ,
+       RULL(0x2D0F01B0), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x2D0F01B1), SH_UNT_PERV_45  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC13_PPM_IVRMCR_OR                                 ,
+       RULL(0x2D0F01B2), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_PPM_IVRMCR                                    ,
+       RULL(0x2E0F01B0), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x2E0F01B1), SH_UNT_PERV_46  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC14_PPM_IVRMCR_OR                                 ,
+       RULL(0x2E0F01B2), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_PPM_IVRMCR                                    ,
+       RULL(0x2F0F01B0), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x2F0F01B1), SH_UNT_PERV_47  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC15_PPM_IVRMCR_OR                                 ,
+       RULL(0x2F0F01B2), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_PPM_IVRMCR                                    ,
+       RULL(0x300F01B0), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x300F01B1), SH_UNT_PERV_48  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC16_PPM_IVRMCR_OR                                 ,
+       RULL(0x300F01B2), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_PPM_IVRMCR                                    ,
+       RULL(0x310F01B0), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x310F01B1), SH_UNT_PERV_49  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC17_PPM_IVRMCR_OR                                 ,
+       RULL(0x310F01B2), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_PPM_IVRMCR                                    ,
+       RULL(0x320F01B0), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x320F01B1), SH_UNT_PERV_50  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC18_PPM_IVRMCR_OR                                 ,
+       RULL(0x320F01B2), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_PPM_IVRMCR                                    ,
+       RULL(0x330F01B0), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x330F01B1), SH_UNT_PERV_51  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC19_PPM_IVRMCR_OR                                 ,
+       RULL(0x330F01B2), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_PPM_IVRMCR                                    ,
+       RULL(0x340F01B0), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x340F01B1), SH_UNT_PERV_52  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC20_PPM_IVRMCR_OR                                 ,
+       RULL(0x340F01B2), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_PPM_IVRMCR                                    ,
+       RULL(0x350F01B0), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x350F01B1), SH_UNT_PERV_53  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC21_PPM_IVRMCR_OR                                 ,
+       RULL(0x350F01B2), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_PPM_IVRMCR                                    ,
+       RULL(0x360F01B0), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x360F01B1), SH_UNT_PERV_54  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC22_PPM_IVRMCR_OR                                 ,
+       RULL(0x360F01B2), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_PPM_IVRMCR                                    ,
+       RULL(0x370F01B0), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_IVRMCR_CLEAR                              ,
+       RULL(0x370F01B1), SH_UNT_PERV_55  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC23_PPM_IVRMCR_OR                                 ,
+       RULL(0x370F01B2), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EP00_PPM_IVRMDVR                                   ,
+       RULL(0x100F01B4), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_IVRMDVR                                   ,
+       RULL(0x110F01B4), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_IVRMDVR                                   ,
+       RULL(0x120F01B4), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_IVRMDVR                                   ,
+       RULL(0x130F01B4), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_IVRMDVR                                   ,
+       RULL(0x140F01B4), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_IVRMDVR                                   ,
+       RULL(0x150F01B4), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_IVRMDVR                                   ,
+       RULL(0x200F01B4), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_IVRMDVR                                   ,
+       RULL(0x210F01B4), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_IVRMDVR                                   ,
+       RULL(0x220F01B4), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_IVRMDVR                                   ,
+       RULL(0x230F01B4), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_IVRMDVR                                   ,
+       RULL(0x240F01B4), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_IVRMDVR                                   ,
+       RULL(0x250F01B4), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_IVRMDVR                                   ,
+       RULL(0x260F01B4), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_IVRMDVR                                   ,
+       RULL(0x270F01B4), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_IVRMDVR                                   ,
+       RULL(0x280F01B4), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_IVRMDVR                                   ,
+       RULL(0x290F01B4), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_IVRMDVR                                   ,
+       RULL(0x2A0F01B4), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_IVRMDVR                                   ,
+       RULL(0x2B0F01B4), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_IVRMDVR                                   ,
+       RULL(0x2C0F01B4), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_IVRMDVR                                   ,
+       RULL(0x2D0F01B4), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_IVRMDVR                                   ,
+       RULL(0x2E0F01B4), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_IVRMDVR                                   ,
+       RULL(0x2F0F01B4), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_IVRMDVR                                   ,
+       RULL(0x300F01B4), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_IVRMDVR                                   ,
+       RULL(0x310F01B4), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_IVRMDVR                                   ,
+       RULL(0x320F01B4), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_IVRMDVR                                   ,
+       RULL(0x330F01B4), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_IVRMDVR                                   ,
+       RULL(0x340F01B4), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_IVRMDVR                                   ,
+       RULL(0x350F01B4), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_IVRMDVR                                   ,
+       RULL(0x360F01B4), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_IVRMDVR                                   ,
+       RULL(0x370F01B4), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_PPM_IVRMST                                    ,
+       RULL(0x100F01B3), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_PPM_IVRMST                                    ,
+       RULL(0x110F01B3), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_PPM_IVRMST                                    ,
+       RULL(0x120F01B3), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_PPM_IVRMST                                    ,
+       RULL(0x130F01B3), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_PPM_IVRMST                                    ,
+       RULL(0x140F01B3), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_PPM_IVRMST                                    ,
+       RULL(0x150F01B3), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_PPM_IVRMST                                    ,
+       RULL(0x200F01B3), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_PPM_IVRMST                                    ,
+       RULL(0x210F01B3), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_PPM_IVRMST                                    ,
+       RULL(0x220F01B3), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_PPM_IVRMST                                    ,
+       RULL(0x230F01B3), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_PPM_IVRMST                                    ,
+       RULL(0x240F01B3), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_PPM_IVRMST                                    ,
+       RULL(0x250F01B3), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_PPM_IVRMST                                    ,
+       RULL(0x260F01B3), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_PPM_IVRMST                                    ,
+       RULL(0x270F01B3), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_PPM_IVRMST                                    ,
+       RULL(0x280F01B3), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_PPM_IVRMST                                    ,
+       RULL(0x290F01B3), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_PPM_IVRMST                                    ,
+       RULL(0x2A0F01B3), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_PPM_IVRMST                                    ,
+       RULL(0x2B0F01B3), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_PPM_IVRMST                                    ,
+       RULL(0x2C0F01B3), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_PPM_IVRMST                                    ,
+       RULL(0x2D0F01B3), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_PPM_IVRMST                                    ,
+       RULL(0x2E0F01B3), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_PPM_IVRMST                                    ,
+       RULL(0x2F0F01B3), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_PPM_IVRMST                                    ,
+       RULL(0x300F01B3), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_PPM_IVRMST                                    ,
+       RULL(0x310F01B3), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_PPM_IVRMST                                    ,
+       RULL(0x320F01B3), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_PPM_IVRMST                                    ,
+       RULL(0x330F01B3), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_PPM_IVRMST                                    ,
+       RULL(0x340F01B3), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_PPM_IVRMST                                    ,
+       RULL(0x350F01B3), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_PPM_IVRMST                                    ,
+       RULL(0x360F01B3), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_PPM_IVRMST                                    ,
+       RULL(0x370F01B3), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_EP00_PPM_PFCS_SCOM                                 ,
+       RULL(0x100F0118), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP00_PPM_PFCS_SCOM1                                ,
+       RULL(0x100F0119), SH_UNT_PERV_16  , SH_ACS_SCOM1     );
+REG64( PERV_EP00_PPM_PFCS_SCOM2                                ,
+       RULL(0x100F011A), SH_UNT_PERV_16  , SH_ACS_SCOM2     );
+REG64( PERV_EP01_PPM_PFCS_SCOM                                 ,
+       RULL(0x110F0118), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PPM_PFCS_SCOM1                                ,
+       RULL(0x110F0119), SH_UNT_PERV_17  , SH_ACS_SCOM1     );
+REG64( PERV_EP01_PPM_PFCS_SCOM2                                ,
+       RULL(0x110F011A), SH_UNT_PERV_17  , SH_ACS_SCOM2     );
+REG64( PERV_EP02_PPM_PFCS_SCOM                                 ,
+       RULL(0x120F0118), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PPM_PFCS_SCOM1                                ,
+       RULL(0x120F0119), SH_UNT_PERV_18  , SH_ACS_SCOM1     );
+REG64( PERV_EP02_PPM_PFCS_SCOM2                                ,
+       RULL(0x120F011A), SH_UNT_PERV_18  , SH_ACS_SCOM2     );
+REG64( PERV_EP03_PPM_PFCS_SCOM                                 ,
+       RULL(0x130F0118), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PPM_PFCS_SCOM1                                ,
+       RULL(0x130F0119), SH_UNT_PERV_19  , SH_ACS_SCOM1     );
+REG64( PERV_EP03_PPM_PFCS_SCOM2                                ,
+       RULL(0x130F011A), SH_UNT_PERV_19  , SH_ACS_SCOM2     );
+REG64( PERV_EP04_PPM_PFCS_SCOM                                 ,
+       RULL(0x140F0118), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PPM_PFCS_SCOM1                                ,
+       RULL(0x140F0119), SH_UNT_PERV_20  , SH_ACS_SCOM1     );
+REG64( PERV_EP04_PPM_PFCS_SCOM2                                ,
+       RULL(0x140F011A), SH_UNT_PERV_20  , SH_ACS_SCOM2     );
+REG64( PERV_EP05_PPM_PFCS_SCOM                                 ,
+       RULL(0x150F0118), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PPM_PFCS_SCOM1                                ,
+       RULL(0x150F0119), SH_UNT_PERV_21  , SH_ACS_SCOM1     );
+REG64( PERV_EP05_PPM_PFCS_SCOM2                                ,
+       RULL(0x150F011A), SH_UNT_PERV_21  , SH_ACS_SCOM2     );
+REG64( PERV_EC00_PPM_PFCS_SCOM                                 ,
+       RULL(0x200F0118), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PPM_PFCS_SCOM1                                ,
+       RULL(0x200F0119), SH_UNT_PERV_32  , SH_ACS_SCOM1     );
+REG64( PERV_EC00_PPM_PFCS_SCOM2                                ,
+       RULL(0x200F011A), SH_UNT_PERV_32  , SH_ACS_SCOM2     );
+REG64( PERV_EC01_PPM_PFCS_SCOM                                 ,
+       RULL(0x210F0118), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PPM_PFCS_SCOM1                                ,
+       RULL(0x210F0119), SH_UNT_PERV_33  , SH_ACS_SCOM1     );
+REG64( PERV_EC01_PPM_PFCS_SCOM2                                ,
+       RULL(0x210F011A), SH_UNT_PERV_33  , SH_ACS_SCOM2     );
+REG64( PERV_EC02_PPM_PFCS_SCOM                                 ,
+       RULL(0x220F0118), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PPM_PFCS_SCOM1                                ,
+       RULL(0x220F0119), SH_UNT_PERV_34  , SH_ACS_SCOM1     );
+REG64( PERV_EC02_PPM_PFCS_SCOM2                                ,
+       RULL(0x220F011A), SH_UNT_PERV_34  , SH_ACS_SCOM2     );
+REG64( PERV_EC03_PPM_PFCS_SCOM                                 ,
+       RULL(0x230F0118), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PPM_PFCS_SCOM1                                ,
+       RULL(0x230F0119), SH_UNT_PERV_35  , SH_ACS_SCOM1     );
+REG64( PERV_EC03_PPM_PFCS_SCOM2                                ,
+       RULL(0x230F011A), SH_UNT_PERV_35  , SH_ACS_SCOM2     );
+REG64( PERV_EC04_PPM_PFCS_SCOM                                 ,
+       RULL(0x240F0118), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PPM_PFCS_SCOM1                                ,
+       RULL(0x240F0119), SH_UNT_PERV_36  , SH_ACS_SCOM1     );
+REG64( PERV_EC04_PPM_PFCS_SCOM2                                ,
+       RULL(0x240F011A), SH_UNT_PERV_36  , SH_ACS_SCOM2     );
+REG64( PERV_EC05_PPM_PFCS_SCOM                                 ,
+       RULL(0x250F0118), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PPM_PFCS_SCOM1                                ,
+       RULL(0x250F0119), SH_UNT_PERV_37  , SH_ACS_SCOM1     );
+REG64( PERV_EC05_PPM_PFCS_SCOM2                                ,
+       RULL(0x250F011A), SH_UNT_PERV_37  , SH_ACS_SCOM2     );
+REG64( PERV_EC06_PPM_PFCS_SCOM                                 ,
+       RULL(0x260F0118), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PPM_PFCS_SCOM1                                ,
+       RULL(0x260F0119), SH_UNT_PERV_38  , SH_ACS_SCOM1     );
+REG64( PERV_EC06_PPM_PFCS_SCOM2                                ,
+       RULL(0x260F011A), SH_UNT_PERV_38  , SH_ACS_SCOM2     );
+REG64( PERV_EC07_PPM_PFCS_SCOM                                 ,
+       RULL(0x270F0118), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PPM_PFCS_SCOM1                                ,
+       RULL(0x270F0119), SH_UNT_PERV_39  , SH_ACS_SCOM1     );
+REG64( PERV_EC07_PPM_PFCS_SCOM2                                ,
+       RULL(0x270F011A), SH_UNT_PERV_39  , SH_ACS_SCOM2     );
+REG64( PERV_EC08_PPM_PFCS_SCOM                                 ,
+       RULL(0x280F0118), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PPM_PFCS_SCOM1                                ,
+       RULL(0x280F0119), SH_UNT_PERV_40  , SH_ACS_SCOM1     );
+REG64( PERV_EC08_PPM_PFCS_SCOM2                                ,
+       RULL(0x280F011A), SH_UNT_PERV_40  , SH_ACS_SCOM2     );
+REG64( PERV_EC09_PPM_PFCS_SCOM                                 ,
+       RULL(0x290F0118), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PPM_PFCS_SCOM1                                ,
+       RULL(0x290F0119), SH_UNT_PERV_41  , SH_ACS_SCOM1     );
+REG64( PERV_EC09_PPM_PFCS_SCOM2                                ,
+       RULL(0x290F011A), SH_UNT_PERV_41  , SH_ACS_SCOM2     );
+REG64( PERV_EC10_PPM_PFCS_SCOM                                 ,
+       RULL(0x2A0F0118), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PPM_PFCS_SCOM1                                ,
+       RULL(0x2A0F0119), SH_UNT_PERV_42  , SH_ACS_SCOM1     );
+REG64( PERV_EC10_PPM_PFCS_SCOM2                                ,
+       RULL(0x2A0F011A), SH_UNT_PERV_42  , SH_ACS_SCOM2     );
+REG64( PERV_EC11_PPM_PFCS_SCOM                                 ,
+       RULL(0x2B0F0118), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PPM_PFCS_SCOM1                                ,
+       RULL(0x2B0F0119), SH_UNT_PERV_43  , SH_ACS_SCOM1     );
+REG64( PERV_EC11_PPM_PFCS_SCOM2                                ,
+       RULL(0x2B0F011A), SH_UNT_PERV_43  , SH_ACS_SCOM2     );
+REG64( PERV_EC12_PPM_PFCS_SCOM                                 ,
+       RULL(0x2C0F0118), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PPM_PFCS_SCOM1                                ,
+       RULL(0x2C0F0119), SH_UNT_PERV_44  , SH_ACS_SCOM1     );
+REG64( PERV_EC12_PPM_PFCS_SCOM2                                ,
+       RULL(0x2C0F011A), SH_UNT_PERV_44  , SH_ACS_SCOM2     );
+REG64( PERV_EC13_PPM_PFCS_SCOM                                 ,
+       RULL(0x2D0F0118), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PPM_PFCS_SCOM1                                ,
+       RULL(0x2D0F0119), SH_UNT_PERV_45  , SH_ACS_SCOM1     );
+REG64( PERV_EC13_PPM_PFCS_SCOM2                                ,
+       RULL(0x2D0F011A), SH_UNT_PERV_45  , SH_ACS_SCOM2     );
+REG64( PERV_EC14_PPM_PFCS_SCOM                                 ,
+       RULL(0x2E0F0118), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PPM_PFCS_SCOM1                                ,
+       RULL(0x2E0F0119), SH_UNT_PERV_46  , SH_ACS_SCOM1     );
+REG64( PERV_EC14_PPM_PFCS_SCOM2                                ,
+       RULL(0x2E0F011A), SH_UNT_PERV_46  , SH_ACS_SCOM2     );
+REG64( PERV_EC15_PPM_PFCS_SCOM                                 ,
+       RULL(0x2F0F0118), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PPM_PFCS_SCOM1                                ,
+       RULL(0x2F0F0119), SH_UNT_PERV_47  , SH_ACS_SCOM1     );
+REG64( PERV_EC15_PPM_PFCS_SCOM2                                ,
+       RULL(0x2F0F011A), SH_UNT_PERV_47  , SH_ACS_SCOM2     );
+REG64( PERV_EC16_PPM_PFCS_SCOM                                 ,
+       RULL(0x300F0118), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PPM_PFCS_SCOM1                                ,
+       RULL(0x300F0119), SH_UNT_PERV_48  , SH_ACS_SCOM1     );
+REG64( PERV_EC16_PPM_PFCS_SCOM2                                ,
+       RULL(0x300F011A), SH_UNT_PERV_48  , SH_ACS_SCOM2     );
+REG64( PERV_EC17_PPM_PFCS_SCOM                                 ,
+       RULL(0x310F0118), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PPM_PFCS_SCOM1                                ,
+       RULL(0x310F0119), SH_UNT_PERV_49  , SH_ACS_SCOM1     );
+REG64( PERV_EC17_PPM_PFCS_SCOM2                                ,
+       RULL(0x310F011A), SH_UNT_PERV_49  , SH_ACS_SCOM2     );
+REG64( PERV_EC18_PPM_PFCS_SCOM                                 ,
+       RULL(0x320F0118), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PPM_PFCS_SCOM1                                ,
+       RULL(0x320F0119), SH_UNT_PERV_50  , SH_ACS_SCOM1     );
+REG64( PERV_EC18_PPM_PFCS_SCOM2                                ,
+       RULL(0x320F011A), SH_UNT_PERV_50  , SH_ACS_SCOM2     );
+REG64( PERV_EC19_PPM_PFCS_SCOM                                 ,
+       RULL(0x330F0118), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PPM_PFCS_SCOM1                                ,
+       RULL(0x330F0119), SH_UNT_PERV_51  , SH_ACS_SCOM1     );
+REG64( PERV_EC19_PPM_PFCS_SCOM2                                ,
+       RULL(0x330F011A), SH_UNT_PERV_51  , SH_ACS_SCOM2     );
+REG64( PERV_EC20_PPM_PFCS_SCOM                                 ,
+       RULL(0x340F0118), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PPM_PFCS_SCOM1                                ,
+       RULL(0x340F0119), SH_UNT_PERV_52  , SH_ACS_SCOM1     );
+REG64( PERV_EC20_PPM_PFCS_SCOM2                                ,
+       RULL(0x340F011A), SH_UNT_PERV_52  , SH_ACS_SCOM2     );
+REG64( PERV_EC21_PPM_PFCS_SCOM                                 ,
+       RULL(0x350F0118), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PPM_PFCS_SCOM1                                ,
+       RULL(0x350F0119), SH_UNT_PERV_53  , SH_ACS_SCOM1     );
+REG64( PERV_EC21_PPM_PFCS_SCOM2                                ,
+       RULL(0x350F011A), SH_UNT_PERV_53  , SH_ACS_SCOM2     );
+REG64( PERV_EC22_PPM_PFCS_SCOM                                 ,
+       RULL(0x360F0118), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PPM_PFCS_SCOM1                                ,
+       RULL(0x360F0119), SH_UNT_PERV_54  , SH_ACS_SCOM1     );
+REG64( PERV_EC22_PPM_PFCS_SCOM2                                ,
+       RULL(0x360F011A), SH_UNT_PERV_54  , SH_ACS_SCOM2     );
+REG64( PERV_EC23_PPM_PFCS_SCOM                                 ,
+       RULL(0x370F0118), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PPM_PFCS_SCOM1                                ,
+       RULL(0x370F0119), SH_UNT_PERV_55  , SH_ACS_SCOM1     );
+REG64( PERV_EC23_PPM_PFCS_SCOM2                                ,
+       RULL(0x370F011A), SH_UNT_PERV_55  , SH_ACS_SCOM2     );
+
+REG64( PERV_EP00_PPM_PFDLY                                     ,
+       RULL(0x100F011B), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_PFDLY                                     ,
+       RULL(0x110F011B), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_PFDLY                                     ,
+       RULL(0x120F011B), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_PFDLY                                     ,
+       RULL(0x130F011B), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_PFDLY                                     ,
+       RULL(0x140F011B), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_PFDLY                                     ,
+       RULL(0x150F011B), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_PFDLY                                     ,
+       RULL(0x200F011B), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_PFDLY                                     ,
+       RULL(0x210F011B), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_PFDLY                                     ,
+       RULL(0x220F011B), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_PFDLY                                     ,
+       RULL(0x230F011B), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_PFDLY                                     ,
+       RULL(0x240F011B), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_PFDLY                                     ,
+       RULL(0x250F011B), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_PFDLY                                     ,
+       RULL(0x260F011B), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_PFDLY                                     ,
+       RULL(0x270F011B), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_PFDLY                                     ,
+       RULL(0x280F011B), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_PFDLY                                     ,
+       RULL(0x290F011B), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_PFDLY                                     ,
+       RULL(0x2A0F011B), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_PFDLY                                     ,
+       RULL(0x2B0F011B), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_PFDLY                                     ,
+       RULL(0x2C0F011B), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_PFDLY                                     ,
+       RULL(0x2D0F011B), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_PFDLY                                     ,
+       RULL(0x2E0F011B), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_PFDLY                                     ,
+       RULL(0x2F0F011B), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_PFDLY                                     ,
+       RULL(0x300F011B), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_PFDLY                                     ,
+       RULL(0x310F011B), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_PFDLY                                     ,
+       RULL(0x320F011B), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_PFDLY                                     ,
+       RULL(0x330F011B), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_PFDLY                                     ,
+       RULL(0x340F011B), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_PFDLY                                     ,
+       RULL(0x350F011B), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_PFDLY                                     ,
+       RULL(0x360F011B), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_PFDLY                                     ,
+       RULL(0x370F011B), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_PPM_PFOFF                                     ,
+       RULL(0x100F011D), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_PFOFF                                     ,
+       RULL(0x110F011D), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_PFOFF                                     ,
+       RULL(0x120F011D), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_PFOFF                                     ,
+       RULL(0x130F011D), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_PFOFF                                     ,
+       RULL(0x140F011D), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_PFOFF                                     ,
+       RULL(0x150F011D), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_PFOFF                                     ,
+       RULL(0x200F011D), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_PFOFF                                     ,
+       RULL(0x210F011D), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_PFOFF                                     ,
+       RULL(0x220F011D), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_PFOFF                                     ,
+       RULL(0x230F011D), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_PFOFF                                     ,
+       RULL(0x240F011D), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_PFOFF                                     ,
+       RULL(0x250F011D), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_PFOFF                                     ,
+       RULL(0x260F011D), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_PFOFF                                     ,
+       RULL(0x270F011D), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_PFOFF                                     ,
+       RULL(0x280F011D), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_PFOFF                                     ,
+       RULL(0x290F011D), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_PFOFF                                     ,
+       RULL(0x2A0F011D), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_PFOFF                                     ,
+       RULL(0x2B0F011D), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_PFOFF                                     ,
+       RULL(0x2C0F011D), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_PFOFF                                     ,
+       RULL(0x2D0F011D), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_PFOFF                                     ,
+       RULL(0x2E0F011D), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_PFOFF                                     ,
+       RULL(0x2F0F011D), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_PFOFF                                     ,
+       RULL(0x300F011D), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_PFOFF                                     ,
+       RULL(0x310F011D), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_PFOFF                                     ,
+       RULL(0x320F011D), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_PFOFF                                     ,
+       RULL(0x330F011D), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_PFOFF                                     ,
+       RULL(0x340F011D), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_PFOFF                                     ,
+       RULL(0x350F011D), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_PFOFF                                     ,
+       RULL(0x360F011D), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_PFOFF                                     ,
+       RULL(0x370F011D), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_PPM_PFSNS                                     ,
+       RULL(0x100F011C), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_PPM_PFSNS                                     ,
+       RULL(0x110F011C), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_PPM_PFSNS                                     ,
+       RULL(0x120F011C), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_PPM_PFSNS                                     ,
+       RULL(0x130F011C), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_PPM_PFSNS                                     ,
+       RULL(0x140F011C), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_PPM_PFSNS                                     ,
+       RULL(0x150F011C), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_PPM_PFSNS                                     ,
+       RULL(0x200F011C), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_PPM_PFSNS                                     ,
+       RULL(0x210F011C), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_PPM_PFSNS                                     ,
+       RULL(0x220F011C), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_PPM_PFSNS                                     ,
+       RULL(0x230F011C), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_PPM_PFSNS                                     ,
+       RULL(0x240F011C), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_PPM_PFSNS                                     ,
+       RULL(0x250F011C), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_PPM_PFSNS                                     ,
+       RULL(0x260F011C), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_PPM_PFSNS                                     ,
+       RULL(0x270F011C), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_PPM_PFSNS                                     ,
+       RULL(0x280F011C), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_PPM_PFSNS                                     ,
+       RULL(0x290F011C), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_PPM_PFSNS                                     ,
+       RULL(0x2A0F011C), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_PPM_PFSNS                                     ,
+       RULL(0x2B0F011C), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_PPM_PFSNS                                     ,
+       RULL(0x2C0F011C), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_PPM_PFSNS                                     ,
+       RULL(0x2D0F011C), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_PPM_PFSNS                                     ,
+       RULL(0x2E0F011C), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_PPM_PFSNS                                     ,
+       RULL(0x2F0F011C), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_PPM_PFSNS                                     ,
+       RULL(0x300F011C), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_PPM_PFSNS                                     ,
+       RULL(0x310F011C), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_PPM_PFSNS                                     ,
+       RULL(0x320F011C), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_PPM_PFSNS                                     ,
+       RULL(0x330F011C), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_PPM_PFSNS                                     ,
+       RULL(0x340F011C), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_PPM_PFSNS                                     ,
+       RULL(0x350F011C), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_PPM_PFSNS                                     ,
+       RULL(0x360F011C), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_PPM_PFSNS                                     ,
+       RULL(0x370F011C), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_EP00_PPM_PIG                                       ,
+       RULL(0x100F0180), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PPM_PIG                                       ,
+       RULL(0x110F0180), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PPM_PIG                                       ,
+       RULL(0x120F0180), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PPM_PIG                                       ,
+       RULL(0x130F0180), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PPM_PIG                                       ,
+       RULL(0x140F0180), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PPM_PIG                                       ,
+       RULL(0x150F0180), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PPM_PIG                                       ,
+       RULL(0x200F0180), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PPM_PIG                                       ,
+       RULL(0x210F0180), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PPM_PIG                                       ,
+       RULL(0x220F0180), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PPM_PIG                                       ,
+       RULL(0x230F0180), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PPM_PIG                                       ,
+       RULL(0x240F0180), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PPM_PIG                                       ,
+       RULL(0x250F0180), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PPM_PIG                                       ,
+       RULL(0x260F0180), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PPM_PIG                                       ,
+       RULL(0x270F0180), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PPM_PIG                                       ,
+       RULL(0x280F0180), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PPM_PIG                                       ,
+       RULL(0x290F0180), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PPM_PIG                                       ,
+       RULL(0x2A0F0180), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PPM_PIG                                       ,
+       RULL(0x2B0F0180), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PPM_PIG                                       ,
+       RULL(0x2C0F0180), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PPM_PIG                                       ,
+       RULL(0x2D0F0180), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PPM_PIG                                       ,
+       RULL(0x2E0F0180), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PPM_PIG                                       ,
+       RULL(0x2F0F0180), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PPM_PIG                                       ,
+       RULL(0x300F0180), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PPM_PIG                                       ,
+       RULL(0x310F0180), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PPM_PIG                                       ,
+       RULL(0x320F0180), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PPM_PIG                                       ,
+       RULL(0x330F0180), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PPM_PIG                                       ,
+       RULL(0x340F0180), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PPM_PIG                                       ,
+       RULL(0x350F0180), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PPM_PIG                                       ,
+       RULL(0x360F0180), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PPM_PIG                                       ,
+       RULL(0x370F0180), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_EP00_PPM_SCRATCH0                                  ,
+       RULL(0x100F011E), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_SCRATCH0                                  ,
+       RULL(0x110F011E), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_SCRATCH0                                  ,
+       RULL(0x120F011E), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_SCRATCH0                                  ,
+       RULL(0x130F011E), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_SCRATCH0                                  ,
+       RULL(0x140F011E), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_SCRATCH0                                  ,
+       RULL(0x150F011E), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_SCRATCH0                                  ,
+       RULL(0x200F011E), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_SCRATCH0                                  ,
+       RULL(0x210F011E), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_SCRATCH0                                  ,
+       RULL(0x220F011E), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_SCRATCH0                                  ,
+       RULL(0x230F011E), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_SCRATCH0                                  ,
+       RULL(0x240F011E), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_SCRATCH0                                  ,
+       RULL(0x250F011E), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_SCRATCH0                                  ,
+       RULL(0x260F011E), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_SCRATCH0                                  ,
+       RULL(0x270F011E), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_SCRATCH0                                  ,
+       RULL(0x280F011E), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_SCRATCH0                                  ,
+       RULL(0x290F011E), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_SCRATCH0                                  ,
+       RULL(0x2A0F011E), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_SCRATCH0                                  ,
+       RULL(0x2B0F011E), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_SCRATCH0                                  ,
+       RULL(0x2C0F011E), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_SCRATCH0                                  ,
+       RULL(0x2D0F011E), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_SCRATCH0                                  ,
+       RULL(0x2E0F011E), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_SCRATCH0                                  ,
+       RULL(0x2F0F011E), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_SCRATCH0                                  ,
+       RULL(0x300F011E), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_SCRATCH0                                  ,
+       RULL(0x310F011E), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_SCRATCH0                                  ,
+       RULL(0x320F011E), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_SCRATCH0                                  ,
+       RULL(0x330F011E), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_SCRATCH0                                  ,
+       RULL(0x340F011E), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_SCRATCH0                                  ,
+       RULL(0x350F011E), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_SCRATCH0                                  ,
+       RULL(0x360F011E), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_SCRATCH0                                  ,
+       RULL(0x370F011E), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_PPM_SCRATCH1                                  ,
+       RULL(0x100F011F), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_SCRATCH1                                  ,
+       RULL(0x110F011F), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_SCRATCH1                                  ,
+       RULL(0x120F011F), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_SCRATCH1                                  ,
+       RULL(0x130F011F), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_SCRATCH1                                  ,
+       RULL(0x140F011F), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_SCRATCH1                                  ,
+       RULL(0x150F011F), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_SCRATCH1                                  ,
+       RULL(0x200F011F), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_SCRATCH1                                  ,
+       RULL(0x210F011F), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_SCRATCH1                                  ,
+       RULL(0x220F011F), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_SCRATCH1                                  ,
+       RULL(0x230F011F), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_SCRATCH1                                  ,
+       RULL(0x240F011F), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_SCRATCH1                                  ,
+       RULL(0x250F011F), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_SCRATCH1                                  ,
+       RULL(0x260F011F), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_SCRATCH1                                  ,
+       RULL(0x270F011F), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_SCRATCH1                                  ,
+       RULL(0x280F011F), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_SCRATCH1                                  ,
+       RULL(0x290F011F), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_SCRATCH1                                  ,
+       RULL(0x2A0F011F), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_SCRATCH1                                  ,
+       RULL(0x2B0F011F), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_SCRATCH1                                  ,
+       RULL(0x2C0F011F), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_SCRATCH1                                  ,
+       RULL(0x2D0F011F), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_SCRATCH1                                  ,
+       RULL(0x2E0F011F), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_SCRATCH1                                  ,
+       RULL(0x2F0F011F), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_SCRATCH1                                  ,
+       RULL(0x300F011F), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_SCRATCH1                                  ,
+       RULL(0x310F011F), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_SCRATCH1                                  ,
+       RULL(0x320F011F), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_SCRATCH1                                  ,
+       RULL(0x330F011F), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_SCRATCH1                                  ,
+       RULL(0x340F011F), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_SCRATCH1                                  ,
+       RULL(0x350F011F), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_SCRATCH1                                  ,
+       RULL(0x360F011F), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_SCRATCH1                                  ,
+       RULL(0x370F011F), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_PPM_SPWKUP_FSP                                ,
+       RULL(0x100F010B), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_SPWKUP_FSP                                ,
+       RULL(0x110F010B), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_SPWKUP_FSP                                ,
+       RULL(0x120F010B), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_SPWKUP_FSP                                ,
+       RULL(0x130F010B), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_SPWKUP_FSP                                ,
+       RULL(0x140F010B), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_SPWKUP_FSP                                ,
+       RULL(0x150F010B), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_SPWKUP_FSP                                ,
+       RULL(0x200F010B), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_SPWKUP_FSP                                ,
+       RULL(0x210F010B), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_SPWKUP_FSP                                ,
+       RULL(0x220F010B), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_SPWKUP_FSP                                ,
+       RULL(0x230F010B), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_SPWKUP_FSP                                ,
+       RULL(0x240F010B), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_SPWKUP_FSP                                ,
+       RULL(0x250F010B), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_SPWKUP_FSP                                ,
+       RULL(0x260F010B), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_SPWKUP_FSP                                ,
+       RULL(0x270F010B), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_SPWKUP_FSP                                ,
+       RULL(0x280F010B), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_SPWKUP_FSP                                ,
+       RULL(0x290F010B), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_SPWKUP_FSP                                ,
+       RULL(0x2A0F010B), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_SPWKUP_FSP                                ,
+       RULL(0x2B0F010B), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_SPWKUP_FSP                                ,
+       RULL(0x2C0F010B), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_SPWKUP_FSP                                ,
+       RULL(0x2D0F010B), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_SPWKUP_FSP                                ,
+       RULL(0x2E0F010B), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_SPWKUP_FSP                                ,
+       RULL(0x2F0F010B), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_SPWKUP_FSP                                ,
+       RULL(0x300F010B), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_SPWKUP_FSP                                ,
+       RULL(0x310F010B), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_SPWKUP_FSP                                ,
+       RULL(0x320F010B), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_SPWKUP_FSP                                ,
+       RULL(0x330F010B), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_SPWKUP_FSP                                ,
+       RULL(0x340F010B), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_SPWKUP_FSP                                ,
+       RULL(0x350F010B), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_SPWKUP_FSP                                ,
+       RULL(0x360F010B), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_SPWKUP_FSP                                ,
+       RULL(0x370F010B), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_PPM_SPWKUP_HYP                                ,
+       RULL(0x100F010D), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_SPWKUP_HYP                                ,
+       RULL(0x110F010D), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_SPWKUP_HYP                                ,
+       RULL(0x120F010D), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_SPWKUP_HYP                                ,
+       RULL(0x130F010D), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_SPWKUP_HYP                                ,
+       RULL(0x140F010D), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_SPWKUP_HYP                                ,
+       RULL(0x150F010D), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_SPWKUP_HYP                                ,
+       RULL(0x200F010D), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_SPWKUP_HYP                                ,
+       RULL(0x210F010D), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_SPWKUP_HYP                                ,
+       RULL(0x220F010D), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_SPWKUP_HYP                                ,
+       RULL(0x230F010D), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_SPWKUP_HYP                                ,
+       RULL(0x240F010D), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_SPWKUP_HYP                                ,
+       RULL(0x250F010D), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_SPWKUP_HYP                                ,
+       RULL(0x260F010D), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_SPWKUP_HYP                                ,
+       RULL(0x270F010D), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_SPWKUP_HYP                                ,
+       RULL(0x280F010D), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_SPWKUP_HYP                                ,
+       RULL(0x290F010D), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_SPWKUP_HYP                                ,
+       RULL(0x2A0F010D), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_SPWKUP_HYP                                ,
+       RULL(0x2B0F010D), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_SPWKUP_HYP                                ,
+       RULL(0x2C0F010D), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_SPWKUP_HYP                                ,
+       RULL(0x2D0F010D), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_SPWKUP_HYP                                ,
+       RULL(0x2E0F010D), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_SPWKUP_HYP                                ,
+       RULL(0x2F0F010D), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_SPWKUP_HYP                                ,
+       RULL(0x300F010D), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_SPWKUP_HYP                                ,
+       RULL(0x310F010D), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_SPWKUP_HYP                                ,
+       RULL(0x320F010D), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_SPWKUP_HYP                                ,
+       RULL(0x330F010D), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_SPWKUP_HYP                                ,
+       RULL(0x340F010D), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_SPWKUP_HYP                                ,
+       RULL(0x350F010D), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_SPWKUP_HYP                                ,
+       RULL(0x360F010D), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_SPWKUP_HYP                                ,
+       RULL(0x370F010D), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_PPM_SPWKUP_OCC                                ,
+       RULL(0x100F010C), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_SPWKUP_OCC                                ,
+       RULL(0x110F010C), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_SPWKUP_OCC                                ,
+       RULL(0x120F010C), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_SPWKUP_OCC                                ,
+       RULL(0x130F010C), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_SPWKUP_OCC                                ,
+       RULL(0x140F010C), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_SPWKUP_OCC                                ,
+       RULL(0x150F010C), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_SPWKUP_OCC                                ,
+       RULL(0x200F010C), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_SPWKUP_OCC                                ,
+       RULL(0x210F010C), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_SPWKUP_OCC                                ,
+       RULL(0x220F010C), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_SPWKUP_OCC                                ,
+       RULL(0x230F010C), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_SPWKUP_OCC                                ,
+       RULL(0x240F010C), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_SPWKUP_OCC                                ,
+       RULL(0x250F010C), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_SPWKUP_OCC                                ,
+       RULL(0x260F010C), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_SPWKUP_OCC                                ,
+       RULL(0x270F010C), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_SPWKUP_OCC                                ,
+       RULL(0x280F010C), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_SPWKUP_OCC                                ,
+       RULL(0x290F010C), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_SPWKUP_OCC                                ,
+       RULL(0x2A0F010C), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_SPWKUP_OCC                                ,
+       RULL(0x2B0F010C), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_SPWKUP_OCC                                ,
+       RULL(0x2C0F010C), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_SPWKUP_OCC                                ,
+       RULL(0x2D0F010C), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_SPWKUP_OCC                                ,
+       RULL(0x2E0F010C), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_SPWKUP_OCC                                ,
+       RULL(0x2F0F010C), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_SPWKUP_OCC                                ,
+       RULL(0x300F010C), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_SPWKUP_OCC                                ,
+       RULL(0x310F010C), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_SPWKUP_OCC                                ,
+       RULL(0x320F010C), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_SPWKUP_OCC                                ,
+       RULL(0x330F010C), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_SPWKUP_OCC                                ,
+       RULL(0x340F010C), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_SPWKUP_OCC                                ,
+       RULL(0x350F010C), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_SPWKUP_OCC                                ,
+       RULL(0x360F010C), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_SPWKUP_OCC                                ,
+       RULL(0x370F010C), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_PPM_SPWKUP_OTR                                ,
+       RULL(0x100F010A), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_SPWKUP_OTR                                ,
+       RULL(0x110F010A), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_SPWKUP_OTR                                ,
+       RULL(0x120F010A), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_SPWKUP_OTR                                ,
+       RULL(0x130F010A), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_SPWKUP_OTR                                ,
+       RULL(0x140F010A), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_SPWKUP_OTR                                ,
+       RULL(0x150F010A), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_SPWKUP_OTR                                ,
+       RULL(0x200F010A), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_SPWKUP_OTR                                ,
+       RULL(0x210F010A), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_SPWKUP_OTR                                ,
+       RULL(0x220F010A), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_SPWKUP_OTR                                ,
+       RULL(0x230F010A), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_SPWKUP_OTR                                ,
+       RULL(0x240F010A), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_SPWKUP_OTR                                ,
+       RULL(0x250F010A), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_SPWKUP_OTR                                ,
+       RULL(0x260F010A), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_SPWKUP_OTR                                ,
+       RULL(0x270F010A), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_SPWKUP_OTR                                ,
+       RULL(0x280F010A), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_SPWKUP_OTR                                ,
+       RULL(0x290F010A), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_SPWKUP_OTR                                ,
+       RULL(0x2A0F010A), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_SPWKUP_OTR                                ,
+       RULL(0x2B0F010A), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_SPWKUP_OTR                                ,
+       RULL(0x2C0F010A), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_SPWKUP_OTR                                ,
+       RULL(0x2D0F010A), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_SPWKUP_OTR                                ,
+       RULL(0x2E0F010A), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_SPWKUP_OTR                                ,
+       RULL(0x2F0F010A), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_SPWKUP_OTR                                ,
+       RULL(0x300F010A), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_SPWKUP_OTR                                ,
+       RULL(0x310F010A), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_SPWKUP_OTR                                ,
+       RULL(0x320F010A), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_SPWKUP_OTR                                ,
+       RULL(0x330F010A), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_SPWKUP_OTR                                ,
+       RULL(0x340F010A), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_SPWKUP_OTR                                ,
+       RULL(0x350F010A), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_SPWKUP_OTR                                ,
+       RULL(0x360F010A), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_SPWKUP_OTR                                ,
+       RULL(0x370F010A), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_PPM_SSHFSP                                    ,
+       RULL(0x100F0111), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PPM_SSHFSP                                    ,
+       RULL(0x110F0111), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PPM_SSHFSP                                    ,
+       RULL(0x120F0111), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PPM_SSHFSP                                    ,
+       RULL(0x130F0111), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PPM_SSHFSP                                    ,
+       RULL(0x140F0111), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PPM_SSHFSP                                    ,
+       RULL(0x150F0111), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PPM_SSHFSP                                    ,
+       RULL(0x200F0111), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PPM_SSHFSP                                    ,
+       RULL(0x210F0111), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PPM_SSHFSP                                    ,
+       RULL(0x220F0111), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PPM_SSHFSP                                    ,
+       RULL(0x230F0111), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PPM_SSHFSP                                    ,
+       RULL(0x240F0111), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PPM_SSHFSP                                    ,
+       RULL(0x250F0111), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PPM_SSHFSP                                    ,
+       RULL(0x260F0111), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PPM_SSHFSP                                    ,
+       RULL(0x270F0111), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PPM_SSHFSP                                    ,
+       RULL(0x280F0111), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PPM_SSHFSP                                    ,
+       RULL(0x290F0111), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PPM_SSHFSP                                    ,
+       RULL(0x2A0F0111), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PPM_SSHFSP                                    ,
+       RULL(0x2B0F0111), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PPM_SSHFSP                                    ,
+       RULL(0x2C0F0111), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PPM_SSHFSP                                    ,
+       RULL(0x2D0F0111), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PPM_SSHFSP                                    ,
+       RULL(0x2E0F0111), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PPM_SSHFSP                                    ,
+       RULL(0x2F0F0111), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PPM_SSHFSP                                    ,
+       RULL(0x300F0111), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PPM_SSHFSP                                    ,
+       RULL(0x310F0111), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PPM_SSHFSP                                    ,
+       RULL(0x320F0111), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PPM_SSHFSP                                    ,
+       RULL(0x330F0111), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PPM_SSHFSP                                    ,
+       RULL(0x340F0111), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PPM_SSHFSP                                    ,
+       RULL(0x350F0111), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PPM_SSHFSP                                    ,
+       RULL(0x360F0111), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PPM_SSHFSP                                    ,
+       RULL(0x370F0111), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_EP00_PPM_SSHHYP                                    ,
+       RULL(0x100F0114), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PPM_SSHHYP                                    ,
+       RULL(0x110F0114), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PPM_SSHHYP                                    ,
+       RULL(0x120F0114), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PPM_SSHHYP                                    ,
+       RULL(0x130F0114), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PPM_SSHHYP                                    ,
+       RULL(0x140F0114), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PPM_SSHHYP                                    ,
+       RULL(0x150F0114), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PPM_SSHHYP                                    ,
+       RULL(0x200F0114), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PPM_SSHHYP                                    ,
+       RULL(0x210F0114), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PPM_SSHHYP                                    ,
+       RULL(0x220F0114), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PPM_SSHHYP                                    ,
+       RULL(0x230F0114), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PPM_SSHHYP                                    ,
+       RULL(0x240F0114), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PPM_SSHHYP                                    ,
+       RULL(0x250F0114), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PPM_SSHHYP                                    ,
+       RULL(0x260F0114), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PPM_SSHHYP                                    ,
+       RULL(0x270F0114), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PPM_SSHHYP                                    ,
+       RULL(0x280F0114), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PPM_SSHHYP                                    ,
+       RULL(0x290F0114), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PPM_SSHHYP                                    ,
+       RULL(0x2A0F0114), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PPM_SSHHYP                                    ,
+       RULL(0x2B0F0114), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PPM_SSHHYP                                    ,
+       RULL(0x2C0F0114), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PPM_SSHHYP                                    ,
+       RULL(0x2D0F0114), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PPM_SSHHYP                                    ,
+       RULL(0x2E0F0114), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PPM_SSHHYP                                    ,
+       RULL(0x2F0F0114), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PPM_SSHHYP                                    ,
+       RULL(0x300F0114), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PPM_SSHHYP                                    ,
+       RULL(0x310F0114), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PPM_SSHHYP                                    ,
+       RULL(0x320F0114), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PPM_SSHHYP                                    ,
+       RULL(0x330F0114), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PPM_SSHHYP                                    ,
+       RULL(0x340F0114), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PPM_SSHHYP                                    ,
+       RULL(0x350F0114), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PPM_SSHHYP                                    ,
+       RULL(0x360F0114), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PPM_SSHHYP                                    ,
+       RULL(0x370F0114), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_EP00_PPM_SSHOCC                                    ,
+       RULL(0x100F0112), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PPM_SSHOCC                                    ,
+       RULL(0x110F0112), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PPM_SSHOCC                                    ,
+       RULL(0x120F0112), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PPM_SSHOCC                                    ,
+       RULL(0x130F0112), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PPM_SSHOCC                                    ,
+       RULL(0x140F0112), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PPM_SSHOCC                                    ,
+       RULL(0x150F0112), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PPM_SSHOCC                                    ,
+       RULL(0x200F0112), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PPM_SSHOCC                                    ,
+       RULL(0x210F0112), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PPM_SSHOCC                                    ,
+       RULL(0x220F0112), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PPM_SSHOCC                                    ,
+       RULL(0x230F0112), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PPM_SSHOCC                                    ,
+       RULL(0x240F0112), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PPM_SSHOCC                                    ,
+       RULL(0x250F0112), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PPM_SSHOCC                                    ,
+       RULL(0x260F0112), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PPM_SSHOCC                                    ,
+       RULL(0x270F0112), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PPM_SSHOCC                                    ,
+       RULL(0x280F0112), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PPM_SSHOCC                                    ,
+       RULL(0x290F0112), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PPM_SSHOCC                                    ,
+       RULL(0x2A0F0112), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PPM_SSHOCC                                    ,
+       RULL(0x2B0F0112), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PPM_SSHOCC                                    ,
+       RULL(0x2C0F0112), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PPM_SSHOCC                                    ,
+       RULL(0x2D0F0112), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PPM_SSHOCC                                    ,
+       RULL(0x2E0F0112), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PPM_SSHOCC                                    ,
+       RULL(0x2F0F0112), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PPM_SSHOCC                                    ,
+       RULL(0x300F0112), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PPM_SSHOCC                                    ,
+       RULL(0x310F0112), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PPM_SSHOCC                                    ,
+       RULL(0x320F0112), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PPM_SSHOCC                                    ,
+       RULL(0x330F0112), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PPM_SSHOCC                                    ,
+       RULL(0x340F0112), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PPM_SSHOCC                                    ,
+       RULL(0x350F0112), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PPM_SSHOCC                                    ,
+       RULL(0x360F0112), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PPM_SSHOCC                                    ,
+       RULL(0x370F0112), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_EP00_PPM_SSHOTR                                    ,
+       RULL(0x100F0113), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PPM_SSHOTR                                    ,
+       RULL(0x110F0113), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PPM_SSHOTR                                    ,
+       RULL(0x120F0113), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PPM_SSHOTR                                    ,
+       RULL(0x130F0113), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PPM_SSHOTR                                    ,
+       RULL(0x140F0113), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PPM_SSHOTR                                    ,
+       RULL(0x150F0113), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PPM_SSHOTR                                    ,
+       RULL(0x200F0113), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PPM_SSHOTR                                    ,
+       RULL(0x210F0113), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PPM_SSHOTR                                    ,
+       RULL(0x220F0113), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PPM_SSHOTR                                    ,
+       RULL(0x230F0113), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PPM_SSHOTR                                    ,
+       RULL(0x240F0113), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PPM_SSHOTR                                    ,
+       RULL(0x250F0113), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PPM_SSHOTR                                    ,
+       RULL(0x260F0113), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PPM_SSHOTR                                    ,
+       RULL(0x270F0113), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PPM_SSHOTR                                    ,
+       RULL(0x280F0113), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PPM_SSHOTR                                    ,
+       RULL(0x290F0113), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PPM_SSHOTR                                    ,
+       RULL(0x2A0F0113), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PPM_SSHOTR                                    ,
+       RULL(0x2B0F0113), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PPM_SSHOTR                                    ,
+       RULL(0x2C0F0113), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PPM_SSHOTR                                    ,
+       RULL(0x2D0F0113), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PPM_SSHOTR                                    ,
+       RULL(0x2E0F0113), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PPM_SSHOTR                                    ,
+       RULL(0x2F0F0113), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PPM_SSHOTR                                    ,
+       RULL(0x300F0113), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PPM_SSHOTR                                    ,
+       RULL(0x310F0113), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PPM_SSHOTR                                    ,
+       RULL(0x320F0113), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PPM_SSHOTR                                    ,
+       RULL(0x330F0113), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PPM_SSHOTR                                    ,
+       RULL(0x340F0113), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PPM_SSHOTR                                    ,
+       RULL(0x350F0113), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PPM_SSHOTR                                    ,
+       RULL(0x360F0113), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PPM_SSHOTR                                    ,
+       RULL(0x370F0113), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_EP00_PPM_SSHSRC                                    ,
+       RULL(0x100F0110), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PPM_SSHSRC                                    ,
+       RULL(0x110F0110), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PPM_SSHSRC                                    ,
+       RULL(0x120F0110), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PPM_SSHSRC                                    ,
+       RULL(0x130F0110), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PPM_SSHSRC                                    ,
+       RULL(0x140F0110), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PPM_SSHSRC                                    ,
+       RULL(0x150F0110), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PPM_SSHSRC                                    ,
+       RULL(0x200F0110), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PPM_SSHSRC                                    ,
+       RULL(0x210F0110), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PPM_SSHSRC                                    ,
+       RULL(0x220F0110), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PPM_SSHSRC                                    ,
+       RULL(0x230F0110), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PPM_SSHSRC                                    ,
+       RULL(0x240F0110), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PPM_SSHSRC                                    ,
+       RULL(0x250F0110), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PPM_SSHSRC                                    ,
+       RULL(0x260F0110), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PPM_SSHSRC                                    ,
+       RULL(0x270F0110), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PPM_SSHSRC                                    ,
+       RULL(0x280F0110), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PPM_SSHSRC                                    ,
+       RULL(0x290F0110), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PPM_SSHSRC                                    ,
+       RULL(0x2A0F0110), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PPM_SSHSRC                                    ,
+       RULL(0x2B0F0110), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PPM_SSHSRC                                    ,
+       RULL(0x2C0F0110), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PPM_SSHSRC                                    ,
+       RULL(0x2D0F0110), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PPM_SSHSRC                                    ,
+       RULL(0x2E0F0110), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PPM_SSHSRC                                    ,
+       RULL(0x2F0F0110), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PPM_SSHSRC                                    ,
+       RULL(0x300F0110), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PPM_SSHSRC                                    ,
+       RULL(0x310F0110), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PPM_SSHSRC                                    ,
+       RULL(0x320F0110), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PPM_SSHSRC                                    ,
+       RULL(0x330F0110), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PPM_SSHSRC                                    ,
+       RULL(0x340F0110), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PPM_SSHSRC                                    ,
+       RULL(0x350F0110), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PPM_SSHSRC                                    ,
+       RULL(0x360F0110), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PPM_SSHSRC                                    ,
+       RULL(0x370F0110), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_EP00_PPM_VDMCR                                     ,
+       RULL(0x100F01B8), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_PPM_VDMCR_CLEAR                               ,
+       RULL(0x100F01BA), SH_UNT_PERV_16  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP00_PPM_VDMCR_OR                                  ,
+       RULL(0x100F01B9), SH_UNT_PERV_16  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP01_PPM_VDMCR                                     ,
+       RULL(0x110F01B8), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_VDMCR_CLEAR                               ,
+       RULL(0x110F01BA), SH_UNT_PERV_17  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP01_PPM_VDMCR_OR                                  ,
+       RULL(0x110F01B9), SH_UNT_PERV_17  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP02_PPM_VDMCR                                     ,
+       RULL(0x120F01B8), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_VDMCR_CLEAR                               ,
+       RULL(0x120F01BA), SH_UNT_PERV_18  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP02_PPM_VDMCR_OR                                  ,
+       RULL(0x120F01B9), SH_UNT_PERV_18  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP03_PPM_VDMCR                                     ,
+       RULL(0x130F01B8), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_VDMCR_CLEAR                               ,
+       RULL(0x130F01BA), SH_UNT_PERV_19  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP03_PPM_VDMCR_OR                                  ,
+       RULL(0x130F01B9), SH_UNT_PERV_19  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP04_PPM_VDMCR                                     ,
+       RULL(0x140F01B8), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_VDMCR_CLEAR                               ,
+       RULL(0x140F01BA), SH_UNT_PERV_20  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP04_PPM_VDMCR_OR                                  ,
+       RULL(0x140F01B9), SH_UNT_PERV_20  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP05_PPM_VDMCR                                     ,
+       RULL(0x150F01B8), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_VDMCR_CLEAR                               ,
+       RULL(0x150F01BA), SH_UNT_PERV_21  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP05_PPM_VDMCR_OR                                  ,
+       RULL(0x150F01B9), SH_UNT_PERV_21  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC00_PPM_VDMCR                                     ,
+       RULL(0x200F01B8), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_VDMCR_CLEAR                               ,
+       RULL(0x200F01BA), SH_UNT_PERV_32  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC00_PPM_VDMCR_OR                                  ,
+       RULL(0x200F01B9), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_PPM_VDMCR                                     ,
+       RULL(0x210F01B8), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_VDMCR_CLEAR                               ,
+       RULL(0x210F01BA), SH_UNT_PERV_33  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC01_PPM_VDMCR_OR                                  ,
+       RULL(0x210F01B9), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_PPM_VDMCR                                     ,
+       RULL(0x220F01B8), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_VDMCR_CLEAR                               ,
+       RULL(0x220F01BA), SH_UNT_PERV_34  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC02_PPM_VDMCR_OR                                  ,
+       RULL(0x220F01B9), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_PPM_VDMCR                                     ,
+       RULL(0x230F01B8), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_VDMCR_CLEAR                               ,
+       RULL(0x230F01BA), SH_UNT_PERV_35  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC03_PPM_VDMCR_OR                                  ,
+       RULL(0x230F01B9), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_PPM_VDMCR                                     ,
+       RULL(0x240F01B8), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_VDMCR_CLEAR                               ,
+       RULL(0x240F01BA), SH_UNT_PERV_36  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC04_PPM_VDMCR_OR                                  ,
+       RULL(0x240F01B9), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_PPM_VDMCR                                     ,
+       RULL(0x250F01B8), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_VDMCR_CLEAR                               ,
+       RULL(0x250F01BA), SH_UNT_PERV_37  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC05_PPM_VDMCR_OR                                  ,
+       RULL(0x250F01B9), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_PPM_VDMCR                                     ,
+       RULL(0x260F01B8), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_VDMCR_CLEAR                               ,
+       RULL(0x260F01BA), SH_UNT_PERV_38  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC06_PPM_VDMCR_OR                                  ,
+       RULL(0x260F01B9), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_PPM_VDMCR                                     ,
+       RULL(0x270F01B8), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_VDMCR_CLEAR                               ,
+       RULL(0x270F01BA), SH_UNT_PERV_39  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC07_PPM_VDMCR_OR                                  ,
+       RULL(0x270F01B9), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_PPM_VDMCR                                     ,
+       RULL(0x280F01B8), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_VDMCR_CLEAR                               ,
+       RULL(0x280F01BA), SH_UNT_PERV_40  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC08_PPM_VDMCR_OR                                  ,
+       RULL(0x280F01B9), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_PPM_VDMCR                                     ,
+       RULL(0x290F01B8), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_VDMCR_CLEAR                               ,
+       RULL(0x290F01BA), SH_UNT_PERV_41  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC09_PPM_VDMCR_OR                                  ,
+       RULL(0x290F01B9), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_PPM_VDMCR                                     ,
+       RULL(0x2A0F01B8), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_VDMCR_CLEAR                               ,
+       RULL(0x2A0F01BA), SH_UNT_PERV_42  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC10_PPM_VDMCR_OR                                  ,
+       RULL(0x2A0F01B9), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_PPM_VDMCR                                     ,
+       RULL(0x2B0F01B8), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_VDMCR_CLEAR                               ,
+       RULL(0x2B0F01BA), SH_UNT_PERV_43  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC11_PPM_VDMCR_OR                                  ,
+       RULL(0x2B0F01B9), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_PPM_VDMCR                                     ,
+       RULL(0x2C0F01B8), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_VDMCR_CLEAR                               ,
+       RULL(0x2C0F01BA), SH_UNT_PERV_44  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC12_PPM_VDMCR_OR                                  ,
+       RULL(0x2C0F01B9), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_PPM_VDMCR                                     ,
+       RULL(0x2D0F01B8), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_VDMCR_CLEAR                               ,
+       RULL(0x2D0F01BA), SH_UNT_PERV_45  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC13_PPM_VDMCR_OR                                  ,
+       RULL(0x2D0F01B9), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_PPM_VDMCR                                     ,
+       RULL(0x2E0F01B8), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_VDMCR_CLEAR                               ,
+       RULL(0x2E0F01BA), SH_UNT_PERV_46  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC14_PPM_VDMCR_OR                                  ,
+       RULL(0x2E0F01B9), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_PPM_VDMCR                                     ,
+       RULL(0x2F0F01B8), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_VDMCR_CLEAR                               ,
+       RULL(0x2F0F01BA), SH_UNT_PERV_47  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC15_PPM_VDMCR_OR                                  ,
+       RULL(0x2F0F01B9), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_PPM_VDMCR                                     ,
+       RULL(0x300F01B8), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_VDMCR_CLEAR                               ,
+       RULL(0x300F01BA), SH_UNT_PERV_48  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC16_PPM_VDMCR_OR                                  ,
+       RULL(0x300F01B9), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_PPM_VDMCR                                     ,
+       RULL(0x310F01B8), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_VDMCR_CLEAR                               ,
+       RULL(0x310F01BA), SH_UNT_PERV_49  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC17_PPM_VDMCR_OR                                  ,
+       RULL(0x310F01B9), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_PPM_VDMCR                                     ,
+       RULL(0x320F01B8), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_VDMCR_CLEAR                               ,
+       RULL(0x320F01BA), SH_UNT_PERV_50  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC18_PPM_VDMCR_OR                                  ,
+       RULL(0x320F01B9), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_PPM_VDMCR                                     ,
+       RULL(0x330F01B8), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_VDMCR_CLEAR                               ,
+       RULL(0x330F01BA), SH_UNT_PERV_51  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC19_PPM_VDMCR_OR                                  ,
+       RULL(0x330F01B9), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_PPM_VDMCR                                     ,
+       RULL(0x340F01B8), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_VDMCR_CLEAR                               ,
+       RULL(0x340F01BA), SH_UNT_PERV_52  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC20_PPM_VDMCR_OR                                  ,
+       RULL(0x340F01B9), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_PPM_VDMCR                                     ,
+       RULL(0x350F01B8), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_VDMCR_CLEAR                               ,
+       RULL(0x350F01BA), SH_UNT_PERV_53  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC21_PPM_VDMCR_OR                                  ,
+       RULL(0x350F01B9), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_PPM_VDMCR                                     ,
+       RULL(0x360F01B8), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_VDMCR_CLEAR                               ,
+       RULL(0x360F01BA), SH_UNT_PERV_54  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC22_PPM_VDMCR_OR                                  ,
+       RULL(0x360F01B9), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_PPM_VDMCR                                     ,
+       RULL(0x370F01B8), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_VDMCR_CLEAR                               ,
+       RULL(0x370F01BA), SH_UNT_PERV_55  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC23_PPM_VDMCR_OR                                  ,
+       RULL(0x370F01B9), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_PRE_COUNTER_REG                                    ,
+       RULL(0x000F0028), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_PRE_COUNTER_REG                                 ,
+       RULL(0x010F0028), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_PRE_COUNTER_REG                                 ,
+       RULL(0x020F0028), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_PRE_COUNTER_REG                                 ,
+       RULL(0x030F0028), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_PRE_COUNTER_REG                                 ,
+       RULL(0x040F0028), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_PRE_COUNTER_REG                                 ,
+       RULL(0x050F0028), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_PRE_COUNTER_REG                                 ,
+       RULL(0x060F0028), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_PRE_COUNTER_REG                               ,
+       RULL(0x070F0028), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_PRE_COUNTER_REG                               ,
+       RULL(0x080F0028), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_PRE_COUNTER_REG                                ,
+       RULL(0x090F0028), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_PRE_COUNTER_REG                                ,
+       RULL(0x0C0F0028), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_PRE_COUNTER_REG                               ,
+       RULL(0x0D0F0028), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_PRE_COUNTER_REG                               ,
+       RULL(0x0E0F0028), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_PRE_COUNTER_REG                               ,
+       RULL(0x0F0F0028), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_PRE_COUNTER_REG                               ,
+       RULL(0x100F0028), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PRE_COUNTER_REG                               ,
+       RULL(0x110F0028), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PRE_COUNTER_REG                               ,
+       RULL(0x120F0028), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PRE_COUNTER_REG                               ,
+       RULL(0x130F0028), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PRE_COUNTER_REG                               ,
+       RULL(0x140F0028), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PRE_COUNTER_REG                               ,
+       RULL(0x150F0028), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PRE_COUNTER_REG                               ,
+       RULL(0x200F0028), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PRE_COUNTER_REG                               ,
+       RULL(0x210F0028), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PRE_COUNTER_REG                               ,
+       RULL(0x220F0028), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PRE_COUNTER_REG                               ,
+       RULL(0x230F0028), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PRE_COUNTER_REG                               ,
+       RULL(0x240F0028), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PRE_COUNTER_REG                               ,
+       RULL(0x250F0028), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PRE_COUNTER_REG                               ,
+       RULL(0x260F0028), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PRE_COUNTER_REG                               ,
+       RULL(0x270F0028), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PRE_COUNTER_REG                               ,
+       RULL(0x280F0028), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PRE_COUNTER_REG                               ,
+       RULL(0x290F0028), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PRE_COUNTER_REG                               ,
+       RULL(0x2A0F0028), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PRE_COUNTER_REG                               ,
+       RULL(0x2B0F0028), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PRE_COUNTER_REG                               ,
+       RULL(0x2C0F0028), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PRE_COUNTER_REG                               ,
+       RULL(0x2D0F0028), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PRE_COUNTER_REG                               ,
+       RULL(0x2E0F0028), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PRE_COUNTER_REG                               ,
+       RULL(0x2F0F0028), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PRE_COUNTER_REG                               ,
+       RULL(0x300F0028), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PRE_COUNTER_REG                               ,
+       RULL(0x310F0028), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PRE_COUNTER_REG                               ,
+       RULL(0x320F0028), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PRE_COUNTER_REG                               ,
+       RULL(0x330F0028), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PRE_COUNTER_REG                               ,
+       RULL(0x340F0028), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PRE_COUNTER_REG                               ,
+       RULL(0x350F0028), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PRE_COUNTER_REG                               ,
+       RULL(0x360F0028), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PRE_COUNTER_REG                               ,
+       RULL(0x370F0028), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_PRIMARY_ADDRESS_REG                                ,
+       RULL(0x000F0000), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_PRIMARY_ADDRESS_REG                             ,
+       RULL(0x010F0000), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_PRIMARY_ADDRESS_REG                             ,
+       RULL(0x020F0000), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_PRIMARY_ADDRESS_REG                             ,
+       RULL(0x030F0000), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_PRIMARY_ADDRESS_REG                             ,
+       RULL(0x040F0000), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_PRIMARY_ADDRESS_REG                             ,
+       RULL(0x050F0000), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_PRIMARY_ADDRESS_REG                             ,
+       RULL(0x060F0000), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x070F0000), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x080F0000), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_PRIMARY_ADDRESS_REG                            ,
+       RULL(0x090F0000), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_PRIMARY_ADDRESS_REG                            ,
+       RULL(0x0C0F0000), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x0D0F0000), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x0E0F0000), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x0F0F0000), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x100F0000), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x110F0000), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x120F0000), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x130F0000), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x140F0000), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x150F0000), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x200F0000), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x210F0000), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x220F0000), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x230F0000), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x240F0000), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x250F0000), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x260F0000), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x270F0000), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x280F0000), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x290F0000), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x2A0F0000), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x2B0F0000), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x2C0F0000), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x2D0F0000), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x2E0F0000), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x2F0F0000), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x300F0000), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x310F0000), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x320F0000), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x330F0000), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x340F0000), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x350F0000), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x360F0000), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PRIMARY_ADDRESS_REG                           ,
+       RULL(0x370F0000), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_PROTECT_MODE_REG                                   ,
+       RULL(0x000F03FE), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_PROTECT_MODE_REG                                ,
+       RULL(0x010F03FE), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_PROTECT_MODE_REG                                ,
+       RULL(0x020F03FE), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_PROTECT_MODE_REG                                ,
+       RULL(0x030F03FE), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_PROTECT_MODE_REG                                ,
+       RULL(0x040F03FE), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_PROTECT_MODE_REG                                ,
+       RULL(0x050F03FE), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_PROTECT_MODE_REG                                ,
+       RULL(0x060F03FE), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_PROTECT_MODE_REG                              ,
+       RULL(0x070F03FE), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_PROTECT_MODE_REG                              ,
+       RULL(0x080F03FE), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_PROTECT_MODE_REG                               ,
+       RULL(0x090F03FE), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_PROTECT_MODE_REG                               ,
+       RULL(0x0C0F03FE), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_PROTECT_MODE_REG                              ,
+       RULL(0x0D0F03FE), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_PROTECT_MODE_REG                              ,
+       RULL(0x0E0F03FE), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_PROTECT_MODE_REG                              ,
+       RULL(0x0F0F03FE), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_PROTECT_MODE_REG                              ,
+       RULL(0x100F03FE), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PROTECT_MODE_REG                              ,
+       RULL(0x110F03FE), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PROTECT_MODE_REG                              ,
+       RULL(0x120F03FE), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PROTECT_MODE_REG                              ,
+       RULL(0x130F03FE), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PROTECT_MODE_REG                              ,
+       RULL(0x140F03FE), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PROTECT_MODE_REG                              ,
+       RULL(0x150F03FE), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PROTECT_MODE_REG                              ,
+       RULL(0x200F03FE), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PROTECT_MODE_REG                              ,
+       RULL(0x210F03FE), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PROTECT_MODE_REG                              ,
+       RULL(0x220F03FE), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PROTECT_MODE_REG                              ,
+       RULL(0x230F03FE), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PROTECT_MODE_REG                              ,
+       RULL(0x240F03FE), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PROTECT_MODE_REG                              ,
+       RULL(0x250F03FE), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PROTECT_MODE_REG                              ,
+       RULL(0x260F03FE), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PROTECT_MODE_REG                              ,
+       RULL(0x270F03FE), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PROTECT_MODE_REG                              ,
+       RULL(0x280F03FE), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PROTECT_MODE_REG                              ,
+       RULL(0x290F03FE), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PROTECT_MODE_REG                              ,
+       RULL(0x2A0F03FE), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PROTECT_MODE_REG                              ,
+       RULL(0x2B0F03FE), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PROTECT_MODE_REG                              ,
+       RULL(0x2C0F03FE), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PROTECT_MODE_REG                              ,
+       RULL(0x2D0F03FE), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PROTECT_MODE_REG                              ,
+       RULL(0x2E0F03FE), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PROTECT_MODE_REG                              ,
+       RULL(0x2F0F03FE), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PROTECT_MODE_REG                              ,
+       RULL(0x300F03FE), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PROTECT_MODE_REG                              ,
+       RULL(0x310F03FE), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PROTECT_MODE_REG                              ,
+       RULL(0x320F03FE), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PROTECT_MODE_REG                              ,
+       RULL(0x330F03FE), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PROTECT_MODE_REG                              ,
+       RULL(0x340F03FE), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PROTECT_MODE_REG                              ,
+       RULL(0x350F03FE), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PROTECT_MODE_REG                              ,
+       RULL(0x360F03FE), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PROTECT_MODE_REG                              ,
+       RULL(0x370F03FE), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_PRV_DBG_PPE                                        ,
+       RULL(0x00002000), SH_UNT_PERV     , SH_ACS_PPE       );
+REG64( PERV_PRV_DBG_PPE1                                       ,
+       RULL(0x00002010), SH_UNT_PERV     , SH_ACS_PPE1      );
+REG64( PERV_PRV_DBG_PPE2                                       ,
+       RULL(0x00002018), SH_UNT_PERV     , SH_ACS_PPE2      );
+
+REG64( PERV_EP00_QPPM_DPLL_CHAR                                ,
+       RULL(0x100F0156), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_QPPM_DPLL_CHAR                                ,
+       RULL(0x110F0156), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_QPPM_DPLL_CHAR                                ,
+       RULL(0x120F0156), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_QPPM_DPLL_CHAR                                ,
+       RULL(0x130F0156), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_QPPM_DPLL_CHAR                                ,
+       RULL(0x140F0156), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_QPPM_DPLL_CHAR                                ,
+       RULL(0x150F0156), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_EP00_QPPM_DPLL_CTRL                                ,
+       RULL(0x100F0152), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_QPPM_DPLL_CTRL_CLEAR                          ,
+       RULL(0x100F0153), SH_UNT_PERV_16  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP00_QPPM_DPLL_CTRL_OR                             ,
+       RULL(0x100F0154), SH_UNT_PERV_16  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP01_QPPM_DPLL_CTRL                                ,
+       RULL(0x110F0152), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_QPPM_DPLL_CTRL_CLEAR                          ,
+       RULL(0x110F0153), SH_UNT_PERV_17  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP01_QPPM_DPLL_CTRL_OR                             ,
+       RULL(0x110F0154), SH_UNT_PERV_17  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP02_QPPM_DPLL_CTRL                                ,
+       RULL(0x120F0152), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_QPPM_DPLL_CTRL_CLEAR                          ,
+       RULL(0x120F0153), SH_UNT_PERV_18  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP02_QPPM_DPLL_CTRL_OR                             ,
+       RULL(0x120F0154), SH_UNT_PERV_18  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP03_QPPM_DPLL_CTRL                                ,
+       RULL(0x130F0152), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_QPPM_DPLL_CTRL_CLEAR                          ,
+       RULL(0x130F0153), SH_UNT_PERV_19  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP03_QPPM_DPLL_CTRL_OR                             ,
+       RULL(0x130F0154), SH_UNT_PERV_19  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP04_QPPM_DPLL_CTRL                                ,
+       RULL(0x140F0152), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_QPPM_DPLL_CTRL_CLEAR                          ,
+       RULL(0x140F0153), SH_UNT_PERV_20  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP04_QPPM_DPLL_CTRL_OR                             ,
+       RULL(0x140F0154), SH_UNT_PERV_20  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP05_QPPM_DPLL_CTRL                                ,
+       RULL(0x150F0152), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_QPPM_DPLL_CTRL_CLEAR                          ,
+       RULL(0x150F0153), SH_UNT_PERV_21  , SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP05_QPPM_DPLL_CTRL_OR                             ,
+       RULL(0x150F0154), SH_UNT_PERV_21  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EP00_QPPM_DPLL_FREQ                                ,
+       RULL(0x100F0151), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_QPPM_DPLL_FREQ                                ,
+       RULL(0x110F0151), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_QPPM_DPLL_FREQ                                ,
+       RULL(0x120F0151), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_QPPM_DPLL_FREQ                                ,
+       RULL(0x130F0151), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_QPPM_DPLL_FREQ                                ,
+       RULL(0x140F0151), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_QPPM_DPLL_FREQ                                ,
+       RULL(0x150F0151), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_QPPM_DPLL_STAT                                ,
+       RULL(0x100F0155), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_QPPM_DPLL_STAT                                ,
+       RULL(0x110F0155), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_QPPM_DPLL_STAT                                ,
+       RULL(0x120F0155), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_QPPM_DPLL_STAT                                ,
+       RULL(0x130F0155), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_QPPM_DPLL_STAT                                ,
+       RULL(0x140F0155), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_QPPM_DPLL_STAT                                ,
+       RULL(0x150F0155), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_EP00_QPPM_ERR                                      ,
+       RULL(0x100F0121), SH_UNT_PERV_16  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EP01_QPPM_ERR                                      ,
+       RULL(0x110F0121), SH_UNT_PERV_17  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EP02_QPPM_ERR                                      ,
+       RULL(0x120F0121), SH_UNT_PERV_18  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EP03_QPPM_ERR                                      ,
+       RULL(0x130F0121), SH_UNT_PERV_19  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EP04_QPPM_ERR                                      ,
+       RULL(0x140F0121), SH_UNT_PERV_20  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EP05_QPPM_ERR                                      ,
+       RULL(0x150F0121), SH_UNT_PERV_21  , SH_ACS_SCOM_WCLRPART );
+
+REG64( PERV_EP00_QPPM_ERRMSK                                   ,
+       RULL(0x100F0122), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_QPPM_ERRMSK                                   ,
+       RULL(0x110F0122), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_QPPM_ERRMSK                                   ,
+       RULL(0x120F0122), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_QPPM_ERRMSK                                   ,
+       RULL(0x130F0122), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_QPPM_ERRMSK                                   ,
+       RULL(0x140F0122), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_QPPM_ERRMSK                                   ,
+       RULL(0x150F0122), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_QPPM_ERRSUM                                   ,
+       RULL(0x100F0120), SH_UNT_PERV_16  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EP01_QPPM_ERRSUM                                   ,
+       RULL(0x110F0120), SH_UNT_PERV_17  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EP02_QPPM_ERRSUM                                   ,
+       RULL(0x120F0120), SH_UNT_PERV_18  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EP03_QPPM_ERRSUM                                   ,
+       RULL(0x130F0120), SH_UNT_PERV_19  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EP04_QPPM_ERRSUM                                   ,
+       RULL(0x140F0120), SH_UNT_PERV_20  , SH_ACS_SCOM_WCLRPART );
+REG64( PERV_EP05_QPPM_ERRSUM                                   ,
+       RULL(0x150F0120), SH_UNT_PERV_21  , SH_ACS_SCOM_WCLRPART );
+
+REG64( PERV_EP00_QPPM_OCCHB                                    ,
+       RULL(0x100F015F), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_QPPM_OCCHB                                    ,
+       RULL(0x110F015F), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_QPPM_OCCHB                                    ,
+       RULL(0x120F015F), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_QPPM_OCCHB                                    ,
+       RULL(0x130F015F), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_QPPM_OCCHB                                    ,
+       RULL(0x140F015F), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_QPPM_OCCHB                                    ,
+       RULL(0x150F015F), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_QPPM_QACCR_SCOM                               ,
+       RULL(0x100F0160), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP00_QPPM_QACCR_SCOM1                              ,
+       RULL(0x100F0161), SH_UNT_PERV_16  , SH_ACS_SCOM1     );
+REG64( PERV_EP00_QPPM_QACCR_SCOM2                              ,
+       RULL(0x100F0162), SH_UNT_PERV_16  , SH_ACS_SCOM2     );
+REG64( PERV_EP01_QPPM_QACCR_SCOM                               ,
+       RULL(0x110F0160), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP01_QPPM_QACCR_SCOM1                              ,
+       RULL(0x110F0161), SH_UNT_PERV_17  , SH_ACS_SCOM1     );
+REG64( PERV_EP01_QPPM_QACCR_SCOM2                              ,
+       RULL(0x110F0162), SH_UNT_PERV_17  , SH_ACS_SCOM2     );
+REG64( PERV_EP02_QPPM_QACCR_SCOM                               ,
+       RULL(0x120F0160), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP02_QPPM_QACCR_SCOM1                              ,
+       RULL(0x120F0161), SH_UNT_PERV_18  , SH_ACS_SCOM1     );
+REG64( PERV_EP02_QPPM_QACCR_SCOM2                              ,
+       RULL(0x120F0162), SH_UNT_PERV_18  , SH_ACS_SCOM2     );
+REG64( PERV_EP03_QPPM_QACCR_SCOM                               ,
+       RULL(0x130F0160), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP03_QPPM_QACCR_SCOM1                              ,
+       RULL(0x130F0161), SH_UNT_PERV_19  , SH_ACS_SCOM1     );
+REG64( PERV_EP03_QPPM_QACCR_SCOM2                              ,
+       RULL(0x130F0162), SH_UNT_PERV_19  , SH_ACS_SCOM2     );
+REG64( PERV_EP04_QPPM_QACCR_SCOM                               ,
+       RULL(0x140F0160), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP04_QPPM_QACCR_SCOM1                              ,
+       RULL(0x140F0161), SH_UNT_PERV_20  , SH_ACS_SCOM1     );
+REG64( PERV_EP04_QPPM_QACCR_SCOM2                              ,
+       RULL(0x140F0162), SH_UNT_PERV_20  , SH_ACS_SCOM2     );
+REG64( PERV_EP05_QPPM_QACCR_SCOM                               ,
+       RULL(0x150F0160), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EP05_QPPM_QACCR_SCOM1                              ,
+       RULL(0x150F0161), SH_UNT_PERV_21  , SH_ACS_SCOM1     );
+REG64( PERV_EP05_QPPM_QACCR_SCOM2                              ,
+       RULL(0x150F0162), SH_UNT_PERV_21  , SH_ACS_SCOM2     );
+
+REG64( PERV_EP00_QPPM_QACSR                                    ,
+       RULL(0x100F0163), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_QPPM_QACSR                                    ,
+       RULL(0x110F0163), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_QPPM_QACSR                                    ,
+       RULL(0x120F0163), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_QPPM_QACSR                                    ,
+       RULL(0x130F0163), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_QPPM_QACSR                                    ,
+       RULL(0x140F0163), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_QPPM_QACSR                                    ,
+       RULL(0x150F0163), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_EP00_QPPM_QPMMR_SCOM                               ,
+       RULL(0x100F0103), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP00_QPPM_QPMMR_SCOM1                              ,
+       RULL(0x100F0104), SH_UNT_PERV_16  , SH_ACS_SCOM1     );
+REG64( PERV_EP00_QPPM_QPMMR_SCOM2                              ,
+       RULL(0x100F0105), SH_UNT_PERV_16  , SH_ACS_SCOM2     );
+REG64( PERV_EP01_QPPM_QPMMR_SCOM                               ,
+       RULL(0x110F0103), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP01_QPPM_QPMMR_SCOM1                              ,
+       RULL(0x110F0104), SH_UNT_PERV_17  , SH_ACS_SCOM1     );
+REG64( PERV_EP01_QPPM_QPMMR_SCOM2                              ,
+       RULL(0x110F0105), SH_UNT_PERV_17  , SH_ACS_SCOM2     );
+REG64( PERV_EP02_QPPM_QPMMR_SCOM                               ,
+       RULL(0x120F0103), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP02_QPPM_QPMMR_SCOM1                              ,
+       RULL(0x120F0104), SH_UNT_PERV_18  , SH_ACS_SCOM1     );
+REG64( PERV_EP02_QPPM_QPMMR_SCOM2                              ,
+       RULL(0x120F0105), SH_UNT_PERV_18  , SH_ACS_SCOM2     );
+REG64( PERV_EP03_QPPM_QPMMR_SCOM                               ,
+       RULL(0x130F0103), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP03_QPPM_QPMMR_SCOM1                              ,
+       RULL(0x130F0104), SH_UNT_PERV_19  , SH_ACS_SCOM1     );
+REG64( PERV_EP03_QPPM_QPMMR_SCOM2                              ,
+       RULL(0x130F0105), SH_UNT_PERV_19  , SH_ACS_SCOM2     );
+REG64( PERV_EP04_QPPM_QPMMR_SCOM                               ,
+       RULL(0x140F0103), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP04_QPPM_QPMMR_SCOM1                              ,
+       RULL(0x140F0104), SH_UNT_PERV_20  , SH_ACS_SCOM1     );
+REG64( PERV_EP04_QPPM_QPMMR_SCOM2                              ,
+       RULL(0x140F0105), SH_UNT_PERV_20  , SH_ACS_SCOM2     );
+REG64( PERV_EP05_QPPM_QPMMR_SCOM                               ,
+       RULL(0x150F0103), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EP05_QPPM_QPMMR_SCOM1                              ,
+       RULL(0x150F0104), SH_UNT_PERV_21  , SH_ACS_SCOM1     );
+REG64( PERV_EP05_QPPM_QPMMR_SCOM2                              ,
+       RULL(0x150F0105), SH_UNT_PERV_21  , SH_ACS_SCOM2     );
+
+REG64( PERV_EP00_QPPM_VDMCFGR                                  ,
+       RULL(0x100F01B6), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_QPPM_VDMCFGR                                  ,
+       RULL(0x110F01B6), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_QPPM_VDMCFGR                                  ,
+       RULL(0x120F01B6), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_QPPM_VDMCFGR                                  ,
+       RULL(0x130F01B6), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_QPPM_VDMCFGR                                  ,
+       RULL(0x140F01B6), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_QPPM_VDMCFGR                                  ,
+       RULL(0x150F01B6), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+
+REG32( PERV_FSISHIFT_READ_BUFFER_FSI                           ,
+       RULL(0x00000C03), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_READ_BUFFER_FSI_BYTE                      ,
+       RULL(0x00000C0C), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE  );
+
+REG64( PERV_RECOV_INTERRUPT_REG                                ,
+       RULL(0x000F001B), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_RECOV_INTERRUPT_REG                             ,
+       RULL(0x010F001B), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_RECOV_INTERRUPT_REG                             ,
+       RULL(0x020F001B), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_RECOV_INTERRUPT_REG                             ,
+       RULL(0x030F001B), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_RECOV_INTERRUPT_REG                             ,
+       RULL(0x040F001B), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_RECOV_INTERRUPT_REG                             ,
+       RULL(0x050F001B), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_RECOV_INTERRUPT_REG                             ,
+       RULL(0x060F001B), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_RECOV_INTERRUPT_REG                           ,
+       RULL(0x070F001B), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_RECOV_INTERRUPT_REG                           ,
+       RULL(0x080F001B), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_RECOV_INTERRUPT_REG                            ,
+       RULL(0x090F001B), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_RECOV_INTERRUPT_REG                            ,
+       RULL(0x0C0F001B), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_RECOV_INTERRUPT_REG                           ,
+       RULL(0x0D0F001B), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_RECOV_INTERRUPT_REG                           ,
+       RULL(0x0E0F001B), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_RECOV_INTERRUPT_REG                           ,
+       RULL(0x0F0F001B), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_RECOV_INTERRUPT_REG                           ,
+       RULL(0x100F001B), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_RECOV_INTERRUPT_REG                           ,
+       RULL(0x110F001B), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_RECOV_INTERRUPT_REG                           ,
+       RULL(0x120F001B), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_RECOV_INTERRUPT_REG                           ,
+       RULL(0x130F001B), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_RECOV_INTERRUPT_REG                           ,
+       RULL(0x140F001B), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_RECOV_INTERRUPT_REG                           ,
+       RULL(0x150F001B), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_RECOV_INTERRUPT_REG                           ,
+       RULL(0x200F001B), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_RECOV_INTERRUPT_REG                           ,
+       RULL(0x210F001B), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_RECOV_INTERRUPT_REG                           ,
+       RULL(0x220F001B), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_RECOV_INTERRUPT_REG                           ,
+       RULL(0x230F001B), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_RECOV_INTERRUPT_REG                           ,
+       RULL(0x240F001B), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_RECOV_INTERRUPT_REG                           ,
+       RULL(0x250F001B), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_RECOV_INTERRUPT_REG                           ,
+       RULL(0x260F001B), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_RECOV_INTERRUPT_REG                           ,
+       RULL(0x270F001B), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_RECOV_INTERRUPT_REG                           ,
+       RULL(0x280F001B), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_RECOV_INTERRUPT_REG                           ,
+       RULL(0x290F001B), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_RECOV_INTERRUPT_REG                           ,
+       RULL(0x2A0F001B), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_RECOV_INTERRUPT_REG                           ,
+       RULL(0x2B0F001B), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_RECOV_INTERRUPT_REG                           ,
+       RULL(0x2C0F001B), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_RECOV_INTERRUPT_REG                           ,
+       RULL(0x2D0F001B), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_RECOV_INTERRUPT_REG                           ,
+       RULL(0x2E0F001B), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_RECOV_INTERRUPT_REG                           ,
+       RULL(0x2F0F001B), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_RECOV_INTERRUPT_REG                           ,
+       RULL(0x300F001B), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_RECOV_INTERRUPT_REG                           ,
+       RULL(0x310F001B), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_RECOV_INTERRUPT_REG                           ,
+       RULL(0x320F001B), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_RECOV_INTERRUPT_REG                           ,
+       RULL(0x330F001B), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_RECOV_INTERRUPT_REG                           ,
+       RULL(0x340F001B), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_RECOV_INTERRUPT_REG                           ,
+       RULL(0x350F001B), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_RECOV_INTERRUPT_REG                           ,
+       RULL(0x360F001B), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_RECOV_INTERRUPT_REG                           ,
+       RULL(0x370F001B), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_REC_ACK_REG                                        ,
+       RULL(0x000F0010), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_REC_ACK_REG                                    ,
+       RULL(0x000F0010), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_REC_ERR_REG0                                       ,
+       RULL(0x000F0011), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_REC_ERR_REG0                                   ,
+       RULL(0x000F0011), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_REC_ERR_REG1                                       ,
+       RULL(0x000F0012), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_REC_ERR_REG1                                   ,
+       RULL(0x000F0012), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_REC_ERR_REG2                                       ,
+       RULL(0x000F0013), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_REC_ERR_REG2                                   ,
+       RULL(0x000F0013), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_REC_ERR_REG3                                       ,
+       RULL(0x000F0014), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_REC_ERR_REG3                                   ,
+       RULL(0x000F0014), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_RESET                                              ,
+       RULL(0x00030004), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_RESET                                          ,
+       RULL(0x00030004), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+REG32( PERV_FSI2PIB_RESET_FSI                                  ,
+       RULL(0x00001006), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI       );
+REG32( PERV_FSI2PIB_RESET_FSI_BYTE                             ,
+       RULL(0x00001018), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE  );
+REG32( PERV_FSISHIFT_RESET_FSI                                 ,
+       RULL(0x00000C06), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_RESET_FSI_BYTE                            ,
+       RULL(0x00000C18), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_RESET_ERRORS_FSI                          ,
+       RULL(0x00000C07), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_RESET_ERRORS_FSI_BYTE                     ,
+       RULL(0x00000C1C), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE  );
+
+REG64( PERV_RESET_REG                                          ,
+       RULL(0x000F001D), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_RESET_REG                                      ,
+       RULL(0x000F001D), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_0_FSII2C_RESIDUAL_FRONT_END_BACK_END_LENGTH        ,
+       RULL(0x00001809), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSII2C_RESIDUAL_FRONT_END_BACK_END_LENGTH          ,
+       RULL(0x00001809), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_ROOT_CTRL0_FSI                                     ,
+       RULL(0x00002810), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL0_FSI_BYTE                                ,
+       RULL(0x00002840), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL0_SCOM                                    ,
+       RULL(0x00050010), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL0                                     ,
+       RULL(0x00050010), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL0_COPY_FSI                                ,
+       RULL(0x00002910), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL0_COPY_FSI_BYTE                           ,
+       RULL(0x00002940), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL0_COPY_SCOM                               ,
+       RULL(0x00050110), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL0_COPY                                ,
+       RULL(0x00050110), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL1_FSI                                     ,
+       RULL(0x00002811), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL1_FSI_BYTE                                ,
+       RULL(0x00002844), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL1_SCOM                                    ,
+       RULL(0x00050011), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL1                                     ,
+       RULL(0x00050011), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL1_COPY_FSI                                ,
+       RULL(0x00002911), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL1_COPY_FSI_BYTE                           ,
+       RULL(0x00002944), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL1_COPY_SCOM                               ,
+       RULL(0x00050111), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL1_COPY                                ,
+       RULL(0x00050111), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL2_FSI                                     ,
+       RULL(0x00002812), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL2_FSI_BYTE                                ,
+       RULL(0x00002848), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL2_SCOM                                    ,
+       RULL(0x00050012), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL2                                     ,
+       RULL(0x00050012), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL2_COPY_FSI                                ,
+       RULL(0x00002912), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL2_COPY_FSI_BYTE                           ,
+       RULL(0x00002948), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL2_COPY_SCOM                               ,
+       RULL(0x00050112), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL2_COPY                                ,
+       RULL(0x00050112), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL3_FSI                                     ,
+       RULL(0x00002813), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL3_FSI_BYTE                                ,
+       RULL(0x0000284C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL3_SCOM                                    ,
+       RULL(0x00050013), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL3                                     ,
+       RULL(0x00050013), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL3_COPY_FSI                                ,
+       RULL(0x00002913), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL3_COPY_FSI_BYTE                           ,
+       RULL(0x0000294C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL3_COPY_SCOM                               ,
+       RULL(0x00050113), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL3_COPY                                ,
+       RULL(0x00050113), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL4_FSI                                     ,
+       RULL(0x00002814), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL4_FSI_BYTE                                ,
+       RULL(0x00002850), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL4_SCOM                                    ,
+       RULL(0x00050014), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL4                                     ,
+       RULL(0x00050014), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL4_COPY_FSI                                ,
+       RULL(0x00002914), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL4_COPY_FSI_BYTE                           ,
+       RULL(0x00002950), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL4_COPY_SCOM                               ,
+       RULL(0x00050114), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL4_COPY                                ,
+       RULL(0x00050114), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL5_FSI                                     ,
+       RULL(0x00002815), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL5_FSI_BYTE                                ,
+       RULL(0x00002854), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL5_SCOM                                    ,
+       RULL(0x00050015), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL5                                     ,
+       RULL(0x00050015), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL5_COPY_FSI                                ,
+       RULL(0x00002915), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL5_COPY_FSI_BYTE                           ,
+       RULL(0x00002954), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL5_COPY_SCOM                               ,
+       RULL(0x00050115), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL5_COPY                                ,
+       RULL(0x00050115), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL6_FSI                                     ,
+       RULL(0x00002816), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL6_FSI_BYTE                                ,
+       RULL(0x00002858), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL6_SCOM                                    ,
+       RULL(0x00050016), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL6                                     ,
+       RULL(0x00050016), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL6_COPY_FSI                                ,
+       RULL(0x00002916), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL6_COPY_FSI_BYTE                           ,
+       RULL(0x00002958), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL6_COPY_SCOM                               ,
+       RULL(0x00050116), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL6_COPY                                ,
+       RULL(0x00050116), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL7_FSI                                     ,
+       RULL(0x00002817), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL7_FSI_BYTE                                ,
+       RULL(0x0000285C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL7_SCOM                                    ,
+       RULL(0x00050017), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL7                                     ,
+       RULL(0x00050017), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL7_COPY_FSI                                ,
+       RULL(0x00002917), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL7_COPY_FSI_BYTE                           ,
+       RULL(0x0000295C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL7_COPY_SCOM                               ,
+       RULL(0x00050117), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL7_COPY                                ,
+       RULL(0x00050117), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL8_FSI                                     ,
+       RULL(0x00002818), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL8_FSI_BYTE                                ,
+       RULL(0x00002860), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL8_SCOM                                    ,
+       RULL(0x00050018), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL8                                     ,
+       RULL(0x00050018), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL8_COPY_FSI                                ,
+       RULL(0x00002918), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL8_COPY_FSI_BYTE                           ,
+       RULL(0x00002960), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL8_COPY_SCOM                               ,
+       RULL(0x00050118), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL8_COPY                                ,
+       RULL(0x00050118), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_RSIC                                               ,
+       RULL(0x00030008), SH_UNT_PERV     , SH_ACS_SCOM_WCLEAR );
+REG64( PERV_PIB_RSIC                                           ,
+       RULL(0x00030008), SH_UNT_PERV_0   , SH_ACS_SCOM_WCLEAR );
+
+REG64( PERV_RSIM                                               ,
+       RULL(0x00030009), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_RSIM                                           ,
+       RULL(0x00030009), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_RSIS                                               ,
+       RULL(0x0003000A), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_RSIS                                           ,
+       RULL(0x0003000A), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+
+REG64( PERV_SBE_LCL_DBG_PPE                                    ,
+       RULL(0x00000120), SH_UNT_PERV     , SH_ACS_PPE       );
+
+REG64( PERV_SBE_LCL_EIMR_PPE                                   ,
+       RULL(0x00000020), SH_UNT_PERV     , SH_ACS_PPE       );
+REG64( PERV_SBE_LCL_EIMR_PPE1                                  ,
+       RULL(0x00000030), SH_UNT_PERV     , SH_ACS_PPE1      );
+REG64( PERV_SBE_LCL_EIMR_PPE2                                  ,
+       RULL(0x00000038), SH_UNT_PERV     , SH_ACS_PPE2      );
+
+REG64( PERV_SBE_LCL_EINR_PPE                                   ,
+       RULL(0x000000A0), SH_UNT_PERV     , SH_ACS_PPE       );
+
+REG64( PERV_SBE_LCL_EIPR_PPE                                   ,
+       RULL(0x00000040), SH_UNT_PERV     , SH_ACS_PPE       );
+REG64( PERV_SBE_LCL_EIPR_PPE1                                  ,
+       RULL(0x00000050), SH_UNT_PERV     , SH_ACS_PPE1      );
+REG64( PERV_SBE_LCL_EIPR_PPE2                                  ,
+       RULL(0x00000058), SH_UNT_PERV     , SH_ACS_PPE2      );
+
+REG64( PERV_SBE_LCL_EISR_PPE                                   ,
+       RULL(0x00000000), SH_UNT_PERV     , SH_ACS_PPE       );
+REG64( PERV_SBE_LCL_EISR_PPE1                                  ,
+       RULL(0x00000010), SH_UNT_PERV     , SH_ACS_PPE1      );
+REG64( PERV_SBE_LCL_EISR_PPE2                                  ,
+       RULL(0x00000018), SH_UNT_PERV     , SH_ACS_PPE2      );
+
+REG64( PERV_SBE_LCL_EISTR_PPE                                  ,
+       RULL(0x00000080), SH_UNT_PERV     , SH_ACS_PPE       );
+
+REG64( PERV_SBE_LCL_EITR_PPE                                   ,
+       RULL(0x00000060), SH_UNT_PERV     , SH_ACS_PPE       );
+REG64( PERV_SBE_LCL_EITR_PPE1                                  ,
+       RULL(0x00000070), SH_UNT_PERV     , SH_ACS_PPE1      );
+REG64( PERV_SBE_LCL_EITR_PPE2                                  ,
+       RULL(0x00000078), SH_UNT_PERV     , SH_ACS_PPE2      );
+
+REG64( PERV_SBE_LCL_IVPR_PPE                                   ,
+       RULL(0x00000160), SH_UNT_PERV     , SH_ACS_PPE       );
+
+REG64( PERV_SBE_LCL_TBR_PPE                                    ,
+       RULL(0x00000140), SH_UNT_PERV     , SH_ACS_PPE       );
+
+REG64( PERV_SBE_LCL_TSEL_PPE                                   ,
+       RULL(0x00000100), SH_UNT_PERV     , SH_ACS_PPE       );
+
+REG32( PERV_SB_CS_FSI                                          ,
+       RULL(0x00002808), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SB_CS_FSI_BYTE                                     ,
+       RULL(0x00002820), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SB_CS_SCOM                                         ,
+       RULL(0x00050008), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SB_CS                                          ,
+       RULL(0x00050008), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_SB_MSG_FSI                                         ,
+       RULL(0x00002809), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SB_MSG_FSI_BYTE                                    ,
+       RULL(0x00002824), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SB_MSG_SCOM                                        ,
+       RULL(0x00050009), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SB_MSG                                         ,
+       RULL(0x00050009), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_SCAN_REGION_TYPE                                   ,
+       RULL(0x00030005), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_SCAN_REGION_TYPE                                ,
+       RULL(0x01030005), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_SCAN_REGION_TYPE                                ,
+       RULL(0x02030005), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_SCAN_REGION_TYPE                                ,
+       RULL(0x03030005), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_SCAN_REGION_TYPE                                ,
+       RULL(0x04030005), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_SCAN_REGION_TYPE                                ,
+       RULL(0x05030005), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_SCAN_REGION_TYPE                                ,
+       RULL(0x06030005), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_SCAN_REGION_TYPE                              ,
+       RULL(0x07030005), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_SCAN_REGION_TYPE                              ,
+       RULL(0x08030005), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_SCAN_REGION_TYPE                               ,
+       RULL(0x09030005), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_SCAN_REGION_TYPE                               ,
+       RULL(0x0C030005), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_SCAN_REGION_TYPE                              ,
+       RULL(0x0D030005), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_SCAN_REGION_TYPE                              ,
+       RULL(0x0E030005), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_SCAN_REGION_TYPE                              ,
+       RULL(0x0F030005), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_SCAN_REGION_TYPE                              ,
+       RULL(0x10030005), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_SCAN_REGION_TYPE                              ,
+       RULL(0x11030005), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_SCAN_REGION_TYPE                              ,
+       RULL(0x12030005), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_SCAN_REGION_TYPE                              ,
+       RULL(0x13030005), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_SCAN_REGION_TYPE                              ,
+       RULL(0x14030005), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_SCAN_REGION_TYPE                              ,
+       RULL(0x15030005), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_SCAN_REGION_TYPE                              ,
+       RULL(0x20030005), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_SCAN_REGION_TYPE                              ,
+       RULL(0x21030005), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_SCAN_REGION_TYPE                              ,
+       RULL(0x22030005), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_SCAN_REGION_TYPE                              ,
+       RULL(0x23030005), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_SCAN_REGION_TYPE                              ,
+       RULL(0x24030005), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_SCAN_REGION_TYPE                              ,
+       RULL(0x25030005), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_SCAN_REGION_TYPE                              ,
+       RULL(0x26030005), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_SCAN_REGION_TYPE                              ,
+       RULL(0x27030005), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_SCAN_REGION_TYPE                              ,
+       RULL(0x28030005), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_SCAN_REGION_TYPE                              ,
+       RULL(0x29030005), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_SCAN_REGION_TYPE                              ,
+       RULL(0x2A030005), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_SCAN_REGION_TYPE                              ,
+       RULL(0x2B030005), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_SCAN_REGION_TYPE                              ,
+       RULL(0x2C030005), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_SCAN_REGION_TYPE                              ,
+       RULL(0x2D030005), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_SCAN_REGION_TYPE                              ,
+       RULL(0x2E030005), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_SCAN_REGION_TYPE                              ,
+       RULL(0x2F030005), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_SCAN_REGION_TYPE                              ,
+       RULL(0x30030005), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_SCAN_REGION_TYPE                              ,
+       RULL(0x31030005), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_SCAN_REGION_TYPE                              ,
+       RULL(0x32030005), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_SCAN_REGION_TYPE                              ,
+       RULL(0x33030005), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_SCAN_REGION_TYPE                              ,
+       RULL(0x34030005), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_SCAN_REGION_TYPE                              ,
+       RULL(0x35030005), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_SCAN_REGION_TYPE                              ,
+       RULL(0x36030005), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_SCAN_REGION_TYPE                              ,
+       RULL(0x37030005), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG32( PERV_SCPSIZE_FSI                                        ,
+       RULL(0x00001400), SH_UNT_PERV     , SH_ACS_FSI       );
+
+REG32( PERV_FSI2PIB_SCRATCH0_PPE                               ,
+       RULL(0x00001000), SH_UNT_PERV_FSI2PIB, SH_ACS_PPE       );
+REG32( PERV_FSI2PIB_SCRATCH0_PPE1                              ,
+       RULL(0x00001010), SH_UNT_PERV_FSI2PIB, SH_ACS_PPE1      );
+REG32( PERV_FSI2PIB_SCRATCH0_PPE2                              ,
+       RULL(0x00001018), SH_UNT_PERV_FSI2PIB, SH_ACS_PPE2      );
+
+REG32( PERV_FSI2PIB_SCRATCH1_PPE                               ,
+       RULL(0x00001020), SH_UNT_PERV_FSI2PIB, SH_ACS_PPE       );
+REG32( PERV_FSI2PIB_SCRATCH1_PPE1                              ,
+       RULL(0x00001030), SH_UNT_PERV_FSI2PIB, SH_ACS_PPE1      );
+REG32( PERV_FSI2PIB_SCRATCH1_PPE2                              ,
+       RULL(0x00001038), SH_UNT_PERV_FSI2PIB, SH_ACS_PPE2      );
+
+REG32( PERV_FSI2PIB_SCRATCH2_PPE                               ,
+       RULL(0x00001040), SH_UNT_PERV_FSI2PIB, SH_ACS_PPE       );
+REG32( PERV_FSI2PIB_SCRATCH2_PPE1                              ,
+       RULL(0x00001050), SH_UNT_PERV_FSI2PIB, SH_ACS_PPE1      );
+REG32( PERV_FSI2PIB_SCRATCH2_PPE2                              ,
+       RULL(0x00001058), SH_UNT_PERV_FSI2PIB, SH_ACS_PPE2      );
+
+REG32( PERV_FSI2PIB_SCRATCH3_PPE                               ,
+       RULL(0x00001060), SH_UNT_PERV_FSI2PIB, SH_ACS_PPE       );
+REG32( PERV_FSI2PIB_SCRATCH3_PPE1                              ,
+       RULL(0x00001070), SH_UNT_PERV_FSI2PIB, SH_ACS_PPE1      );
+REG32( PERV_FSI2PIB_SCRATCH3_PPE2                              ,
+       RULL(0x00001078), SH_UNT_PERV_FSI2PIB, SH_ACS_PPE2      );
+
+REG32( PERV_SCRATCH_REGISTER_1_FSI                             ,
+       RULL(0x00002838), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SCRATCH_REGISTER_1_FSI_BYTE                        ,
+       RULL(0x000028E0), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SCRATCH_REGISTER_1_SCOM                            ,
+       RULL(0x00050038), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SCRATCH_REGISTER_1                             ,
+       RULL(0x00050038), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_SCRATCH_REGISTER_2_FSI                             ,
+       RULL(0x00002839), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SCRATCH_REGISTER_2_FSI_BYTE                        ,
+       RULL(0x000028E4), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SCRATCH_REGISTER_2_SCOM                            ,
+       RULL(0x00050039), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SCRATCH_REGISTER_2                             ,
+       RULL(0x00050039), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_SCRATCH_REGISTER_3_FSI                             ,
+       RULL(0x0000283A), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SCRATCH_REGISTER_3_FSI_BYTE                        ,
+       RULL(0x000028E8), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SCRATCH_REGISTER_3_SCOM                            ,
+       RULL(0x0005003A), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SCRATCH_REGISTER_3                             ,
+       RULL(0x0005003A), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_SCRATCH_REGISTER_4_FSI                             ,
+       RULL(0x0000283B), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SCRATCH_REGISTER_4_FSI_BYTE                        ,
+       RULL(0x000028EC), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SCRATCH_REGISTER_4_SCOM                            ,
+       RULL(0x0005003B), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SCRATCH_REGISTER_4                             ,
+       RULL(0x0005003B), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_SCRATCH_REGISTER_5_FSI                             ,
+       RULL(0x0000283C), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SCRATCH_REGISTER_5_FSI_BYTE                        ,
+       RULL(0x000028F0), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SCRATCH_REGISTER_5_SCOM                            ,
+       RULL(0x0005003C), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SCRATCH_REGISTER_5                             ,
+       RULL(0x0005003C), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_SCRATCH_REGISTER_6_FSI                             ,
+       RULL(0x0000283D), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SCRATCH_REGISTER_6_FSI_BYTE                        ,
+       RULL(0x000028F4), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SCRATCH_REGISTER_6_SCOM                            ,
+       RULL(0x0005003D), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SCRATCH_REGISTER_6                             ,
+       RULL(0x0005003D), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_SCRATCH_REGISTER_7_FSI                             ,
+       RULL(0x0000283E), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SCRATCH_REGISTER_7_FSI_BYTE                        ,
+       RULL(0x000028F8), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SCRATCH_REGISTER_7_SCOM                            ,
+       RULL(0x0005003E), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SCRATCH_REGISTER_7                             ,
+       RULL(0x0005003E), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_SCRATCH_REGISTER_8_FSI                             ,
+       RULL(0x0000283F), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SCRATCH_REGISTER_8_FSI_BYTE                        ,
+       RULL(0x000028FC), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SCRATCH_REGISTER_8_SCOM                            ,
+       RULL(0x0005003F), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SCRATCH_REGISTER_8                             ,
+       RULL(0x0005003F), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_FSI2PIB_SET_PIB_RESET_FSI                          ,
+       RULL(0x00001007), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI       );
+REG32( PERV_FSI2PIB_SET_PIB_RESET_FSI_BYTE                     ,
+       RULL(0x0000101C), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_SHIFT_CONTROL_REGISTER_2_FSI              ,
+       RULL(0x00000C10), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_SHIFT_CONTROL_REGISTER_2_FSI_BYTE         ,
+       RULL(0x00000C40), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE  );
+
+REG64( PERV_SKITTER_CLKSRC_REG                                 ,
+       RULL(0x00050016), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_SKITTER_CLKSRC_REG                              ,
+       RULL(0x01050016), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_SKITTER_CLKSRC_REG                              ,
+       RULL(0x02050016), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_SKITTER_CLKSRC_REG                              ,
+       RULL(0x03050016), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_SKITTER_CLKSRC_REG                              ,
+       RULL(0x04050016), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_SKITTER_CLKSRC_REG                              ,
+       RULL(0x05050016), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_SKITTER_CLKSRC_REG                              ,
+       RULL(0x06050016), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_SKITTER_CLKSRC_REG                            ,
+       RULL(0x07050016), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_SKITTER_CLKSRC_REG                            ,
+       RULL(0x08050016), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_SKITTER_CLKSRC_REG                             ,
+       RULL(0x09050016), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_SKITTER_CLKSRC_REG                             ,
+       RULL(0x0C050016), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_SKITTER_CLKSRC_REG                            ,
+       RULL(0x0D050016), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_SKITTER_CLKSRC_REG                            ,
+       RULL(0x0E050016), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_SKITTER_CLKSRC_REG                            ,
+       RULL(0x0F050016), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_SKITTER_CLKSRC_REG                            ,
+       RULL(0x10050016), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_SKITTER_CLKSRC_REG                            ,
+       RULL(0x11050016), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_SKITTER_CLKSRC_REG                            ,
+       RULL(0x12050016), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_SKITTER_CLKSRC_REG                            ,
+       RULL(0x13050016), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_SKITTER_CLKSRC_REG                            ,
+       RULL(0x14050016), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_SKITTER_CLKSRC_REG                            ,
+       RULL(0x15050016), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_SKITTER_CLKSRC_REG                            ,
+       RULL(0x20050016), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_SKITTER_CLKSRC_REG                            ,
+       RULL(0x21050016), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_SKITTER_CLKSRC_REG                            ,
+       RULL(0x22050016), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_SKITTER_CLKSRC_REG                            ,
+       RULL(0x23050016), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_SKITTER_CLKSRC_REG                            ,
+       RULL(0x24050016), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_SKITTER_CLKSRC_REG                            ,
+       RULL(0x25050016), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_SKITTER_CLKSRC_REG                            ,
+       RULL(0x26050016), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_SKITTER_CLKSRC_REG                            ,
+       RULL(0x27050016), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_SKITTER_CLKSRC_REG                            ,
+       RULL(0x28050016), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_SKITTER_CLKSRC_REG                            ,
+       RULL(0x29050016), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_SKITTER_CLKSRC_REG                            ,
+       RULL(0x2A050016), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_SKITTER_CLKSRC_REG                            ,
+       RULL(0x2B050016), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_SKITTER_CLKSRC_REG                            ,
+       RULL(0x2C050016), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_SKITTER_CLKSRC_REG                            ,
+       RULL(0x2D050016), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_SKITTER_CLKSRC_REG                            ,
+       RULL(0x2E050016), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_SKITTER_CLKSRC_REG                            ,
+       RULL(0x2F050016), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_SKITTER_CLKSRC_REG                            ,
+       RULL(0x30050016), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_SKITTER_CLKSRC_REG                            ,
+       RULL(0x31050016), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_SKITTER_CLKSRC_REG                            ,
+       RULL(0x32050016), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_SKITTER_CLKSRC_REG                            ,
+       RULL(0x33050016), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_SKITTER_CLKSRC_REG                            ,
+       RULL(0x34050016), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_SKITTER_CLKSRC_REG                            ,
+       RULL(0x35050016), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_SKITTER_CLKSRC_REG                            ,
+       RULL(0x36050016), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_SKITTER_CLKSRC_REG                            ,
+       RULL(0x37050016), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_SKITTER_DATA0                                      ,
+       RULL(0x00050019), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_SKITTER_DATA0                                   ,
+       RULL(0x01050019), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_N0_SKITTER_DATA0                                   ,
+       RULL(0x02050019), SH_UNT_PERV_2   , SH_ACS_SCOM_RO   );
+REG64( PERV_N1_SKITTER_DATA0                                   ,
+       RULL(0x03050019), SH_UNT_PERV_3   , SH_ACS_SCOM_RO   );
+REG64( PERV_N2_SKITTER_DATA0                                   ,
+       RULL(0x04050019), SH_UNT_PERV_4   , SH_ACS_SCOM_RO   );
+REG64( PERV_N3_SKITTER_DATA0                                   ,
+       RULL(0x05050019), SH_UNT_PERV_5   , SH_ACS_SCOM_RO   );
+REG64( PERV_XB_SKITTER_DATA0                                   ,
+       RULL(0x06050019), SH_UNT_PERV_6   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC01_SKITTER_DATA0                                 ,
+       RULL(0x07050019), SH_UNT_PERV_7   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC23_SKITTER_DATA0                                 ,
+       RULL(0x08050019), SH_UNT_PERV_8   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB0_SKITTER_DATA0                                  ,
+       RULL(0x09050019), SH_UNT_PERV_9   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB3_SKITTER_DATA0                                  ,
+       RULL(0x0C050019), SH_UNT_PERV_12  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI0_SKITTER_DATA0                                 ,
+       RULL(0x0D050019), SH_UNT_PERV_13  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI1_SKITTER_DATA0                                 ,
+       RULL(0x0E050019), SH_UNT_PERV_14  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI2_SKITTER_DATA0                                 ,
+       RULL(0x0F050019), SH_UNT_PERV_15  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP00_SKITTER_DATA0                                 ,
+       RULL(0x10050019), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_SKITTER_DATA0                                 ,
+       RULL(0x11050019), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_SKITTER_DATA0                                 ,
+       RULL(0x12050019), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_SKITTER_DATA0                                 ,
+       RULL(0x13050019), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_SKITTER_DATA0                                 ,
+       RULL(0x14050019), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_SKITTER_DATA0                                 ,
+       RULL(0x15050019), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_SKITTER_DATA0                                 ,
+       RULL(0x20050019), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_SKITTER_DATA0                                 ,
+       RULL(0x21050019), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_SKITTER_DATA0                                 ,
+       RULL(0x22050019), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_SKITTER_DATA0                                 ,
+       RULL(0x23050019), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_SKITTER_DATA0                                 ,
+       RULL(0x24050019), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_SKITTER_DATA0                                 ,
+       RULL(0x25050019), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_SKITTER_DATA0                                 ,
+       RULL(0x26050019), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_SKITTER_DATA0                                 ,
+       RULL(0x27050019), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_SKITTER_DATA0                                 ,
+       RULL(0x28050019), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_SKITTER_DATA0                                 ,
+       RULL(0x29050019), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_SKITTER_DATA0                                 ,
+       RULL(0x2A050019), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_SKITTER_DATA0                                 ,
+       RULL(0x2B050019), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_SKITTER_DATA0                                 ,
+       RULL(0x2C050019), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_SKITTER_DATA0                                 ,
+       RULL(0x2D050019), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_SKITTER_DATA0                                 ,
+       RULL(0x2E050019), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_SKITTER_DATA0                                 ,
+       RULL(0x2F050019), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_SKITTER_DATA0                                 ,
+       RULL(0x30050019), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_SKITTER_DATA0                                 ,
+       RULL(0x31050019), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_SKITTER_DATA0                                 ,
+       RULL(0x32050019), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_SKITTER_DATA0                                 ,
+       RULL(0x33050019), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_SKITTER_DATA0                                 ,
+       RULL(0x34050019), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_SKITTER_DATA0                                 ,
+       RULL(0x35050019), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_SKITTER_DATA0                                 ,
+       RULL(0x36050019), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_SKITTER_DATA0                                 ,
+       RULL(0x37050019), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_SKITTER_DATA1                                      ,
+       RULL(0x0005001A), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_SKITTER_DATA1                                   ,
+       RULL(0x0105001A), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_N0_SKITTER_DATA1                                   ,
+       RULL(0x0205001A), SH_UNT_PERV_2   , SH_ACS_SCOM_RO   );
+REG64( PERV_N1_SKITTER_DATA1                                   ,
+       RULL(0x0305001A), SH_UNT_PERV_3   , SH_ACS_SCOM_RO   );
+REG64( PERV_N2_SKITTER_DATA1                                   ,
+       RULL(0x0405001A), SH_UNT_PERV_4   , SH_ACS_SCOM_RO   );
+REG64( PERV_N3_SKITTER_DATA1                                   ,
+       RULL(0x0505001A), SH_UNT_PERV_5   , SH_ACS_SCOM_RO   );
+REG64( PERV_XB_SKITTER_DATA1                                   ,
+       RULL(0x0605001A), SH_UNT_PERV_6   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC01_SKITTER_DATA1                                 ,
+       RULL(0x0705001A), SH_UNT_PERV_7   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC23_SKITTER_DATA1                                 ,
+       RULL(0x0805001A), SH_UNT_PERV_8   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB0_SKITTER_DATA1                                  ,
+       RULL(0x0905001A), SH_UNT_PERV_9   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB3_SKITTER_DATA1                                  ,
+       RULL(0x0C05001A), SH_UNT_PERV_12  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI0_SKITTER_DATA1                                 ,
+       RULL(0x0D05001A), SH_UNT_PERV_13  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI1_SKITTER_DATA1                                 ,
+       RULL(0x0E05001A), SH_UNT_PERV_14  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI2_SKITTER_DATA1                                 ,
+       RULL(0x0F05001A), SH_UNT_PERV_15  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP00_SKITTER_DATA1                                 ,
+       RULL(0x1005001A), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_SKITTER_DATA1                                 ,
+       RULL(0x1105001A), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_SKITTER_DATA1                                 ,
+       RULL(0x1205001A), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_SKITTER_DATA1                                 ,
+       RULL(0x1305001A), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_SKITTER_DATA1                                 ,
+       RULL(0x1405001A), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_SKITTER_DATA1                                 ,
+       RULL(0x1505001A), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_SKITTER_DATA1                                 ,
+       RULL(0x2005001A), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_SKITTER_DATA1                                 ,
+       RULL(0x2105001A), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_SKITTER_DATA1                                 ,
+       RULL(0x2205001A), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_SKITTER_DATA1                                 ,
+       RULL(0x2305001A), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_SKITTER_DATA1                                 ,
+       RULL(0x2405001A), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_SKITTER_DATA1                                 ,
+       RULL(0x2505001A), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_SKITTER_DATA1                                 ,
+       RULL(0x2605001A), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_SKITTER_DATA1                                 ,
+       RULL(0x2705001A), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_SKITTER_DATA1                                 ,
+       RULL(0x2805001A), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_SKITTER_DATA1                                 ,
+       RULL(0x2905001A), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_SKITTER_DATA1                                 ,
+       RULL(0x2A05001A), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_SKITTER_DATA1                                 ,
+       RULL(0x2B05001A), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_SKITTER_DATA1                                 ,
+       RULL(0x2C05001A), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_SKITTER_DATA1                                 ,
+       RULL(0x2D05001A), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_SKITTER_DATA1                                 ,
+       RULL(0x2E05001A), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_SKITTER_DATA1                                 ,
+       RULL(0x2F05001A), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_SKITTER_DATA1                                 ,
+       RULL(0x3005001A), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_SKITTER_DATA1                                 ,
+       RULL(0x3105001A), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_SKITTER_DATA1                                 ,
+       RULL(0x3205001A), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_SKITTER_DATA1                                 ,
+       RULL(0x3305001A), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_SKITTER_DATA1                                 ,
+       RULL(0x3405001A), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_SKITTER_DATA1                                 ,
+       RULL(0x3505001A), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_SKITTER_DATA1                                 ,
+       RULL(0x3605001A), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_SKITTER_DATA1                                 ,
+       RULL(0x3705001A), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_SKITTER_DATA2                                      ,
+       RULL(0x0005001B), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_SKITTER_DATA2                                   ,
+       RULL(0x0105001B), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_N0_SKITTER_DATA2                                   ,
+       RULL(0x0205001B), SH_UNT_PERV_2   , SH_ACS_SCOM_RO   );
+REG64( PERV_N1_SKITTER_DATA2                                   ,
+       RULL(0x0305001B), SH_UNT_PERV_3   , SH_ACS_SCOM_RO   );
+REG64( PERV_N2_SKITTER_DATA2                                   ,
+       RULL(0x0405001B), SH_UNT_PERV_4   , SH_ACS_SCOM_RO   );
+REG64( PERV_N3_SKITTER_DATA2                                   ,
+       RULL(0x0505001B), SH_UNT_PERV_5   , SH_ACS_SCOM_RO   );
+REG64( PERV_XB_SKITTER_DATA2                                   ,
+       RULL(0x0605001B), SH_UNT_PERV_6   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC01_SKITTER_DATA2                                 ,
+       RULL(0x0705001B), SH_UNT_PERV_7   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC23_SKITTER_DATA2                                 ,
+       RULL(0x0805001B), SH_UNT_PERV_8   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB0_SKITTER_DATA2                                  ,
+       RULL(0x0905001B), SH_UNT_PERV_9   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB3_SKITTER_DATA2                                  ,
+       RULL(0x0C05001B), SH_UNT_PERV_12  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI0_SKITTER_DATA2                                 ,
+       RULL(0x0D05001B), SH_UNT_PERV_13  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI1_SKITTER_DATA2                                 ,
+       RULL(0x0E05001B), SH_UNT_PERV_14  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI2_SKITTER_DATA2                                 ,
+       RULL(0x0F05001B), SH_UNT_PERV_15  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP00_SKITTER_DATA2                                 ,
+       RULL(0x1005001B), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_SKITTER_DATA2                                 ,
+       RULL(0x1105001B), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_SKITTER_DATA2                                 ,
+       RULL(0x1205001B), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_SKITTER_DATA2                                 ,
+       RULL(0x1305001B), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_SKITTER_DATA2                                 ,
+       RULL(0x1405001B), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_SKITTER_DATA2                                 ,
+       RULL(0x1505001B), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_SKITTER_DATA2                                 ,
+       RULL(0x2005001B), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_SKITTER_DATA2                                 ,
+       RULL(0x2105001B), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_SKITTER_DATA2                                 ,
+       RULL(0x2205001B), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_SKITTER_DATA2                                 ,
+       RULL(0x2305001B), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_SKITTER_DATA2                                 ,
+       RULL(0x2405001B), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_SKITTER_DATA2                                 ,
+       RULL(0x2505001B), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_SKITTER_DATA2                                 ,
+       RULL(0x2605001B), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_SKITTER_DATA2                                 ,
+       RULL(0x2705001B), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_SKITTER_DATA2                                 ,
+       RULL(0x2805001B), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_SKITTER_DATA2                                 ,
+       RULL(0x2905001B), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_SKITTER_DATA2                                 ,
+       RULL(0x2A05001B), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_SKITTER_DATA2                                 ,
+       RULL(0x2B05001B), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_SKITTER_DATA2                                 ,
+       RULL(0x2C05001B), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_SKITTER_DATA2                                 ,
+       RULL(0x2D05001B), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_SKITTER_DATA2                                 ,
+       RULL(0x2E05001B), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_SKITTER_DATA2                                 ,
+       RULL(0x2F05001B), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_SKITTER_DATA2                                 ,
+       RULL(0x3005001B), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_SKITTER_DATA2                                 ,
+       RULL(0x3105001B), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_SKITTER_DATA2                                 ,
+       RULL(0x3205001B), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_SKITTER_DATA2                                 ,
+       RULL(0x3305001B), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_SKITTER_DATA2                                 ,
+       RULL(0x3405001B), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_SKITTER_DATA2                                 ,
+       RULL(0x3505001B), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_SKITTER_DATA2                                 ,
+       RULL(0x3605001B), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_SKITTER_DATA2                                 ,
+       RULL(0x3705001B), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_SKITTER_FORCE_REG                                  ,
+       RULL(0x00050014), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_SKITTER_FORCE_REG                               ,
+       RULL(0x01050014), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_SKITTER_FORCE_REG                               ,
+       RULL(0x02050014), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_SKITTER_FORCE_REG                               ,
+       RULL(0x03050014), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_SKITTER_FORCE_REG                               ,
+       RULL(0x04050014), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_SKITTER_FORCE_REG                               ,
+       RULL(0x05050014), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_SKITTER_FORCE_REG                               ,
+       RULL(0x06050014), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_SKITTER_FORCE_REG                             ,
+       RULL(0x07050014), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_SKITTER_FORCE_REG                             ,
+       RULL(0x08050014), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_SKITTER_FORCE_REG                              ,
+       RULL(0x09050014), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_SKITTER_FORCE_REG                              ,
+       RULL(0x0C050014), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_SKITTER_FORCE_REG                             ,
+       RULL(0x0D050014), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_SKITTER_FORCE_REG                             ,
+       RULL(0x0E050014), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_SKITTER_FORCE_REG                             ,
+       RULL(0x0F050014), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_SKITTER_FORCE_REG                             ,
+       RULL(0x10050014), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_SKITTER_FORCE_REG                             ,
+       RULL(0x11050014), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_SKITTER_FORCE_REG                             ,
+       RULL(0x12050014), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_SKITTER_FORCE_REG                             ,
+       RULL(0x13050014), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_SKITTER_FORCE_REG                             ,
+       RULL(0x14050014), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_SKITTER_FORCE_REG                             ,
+       RULL(0x15050014), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_SKITTER_FORCE_REG                             ,
+       RULL(0x20050014), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_SKITTER_FORCE_REG                             ,
+       RULL(0x21050014), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_SKITTER_FORCE_REG                             ,
+       RULL(0x22050014), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_SKITTER_FORCE_REG                             ,
+       RULL(0x23050014), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_SKITTER_FORCE_REG                             ,
+       RULL(0x24050014), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_SKITTER_FORCE_REG                             ,
+       RULL(0x25050014), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_SKITTER_FORCE_REG                             ,
+       RULL(0x26050014), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_SKITTER_FORCE_REG                             ,
+       RULL(0x27050014), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_SKITTER_FORCE_REG                             ,
+       RULL(0x28050014), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_SKITTER_FORCE_REG                             ,
+       RULL(0x29050014), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_SKITTER_FORCE_REG                             ,
+       RULL(0x2A050014), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_SKITTER_FORCE_REG                             ,
+       RULL(0x2B050014), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_SKITTER_FORCE_REG                             ,
+       RULL(0x2C050014), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_SKITTER_FORCE_REG                             ,
+       RULL(0x2D050014), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_SKITTER_FORCE_REG                             ,
+       RULL(0x2E050014), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_SKITTER_FORCE_REG                             ,
+       RULL(0x2F050014), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_SKITTER_FORCE_REG                             ,
+       RULL(0x30050014), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_SKITTER_FORCE_REG                             ,
+       RULL(0x31050014), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_SKITTER_FORCE_REG                             ,
+       RULL(0x32050014), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_SKITTER_FORCE_REG                             ,
+       RULL(0x33050014), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_SKITTER_FORCE_REG                             ,
+       RULL(0x34050014), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_SKITTER_FORCE_REG                             ,
+       RULL(0x35050014), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_SKITTER_FORCE_REG                             ,
+       RULL(0x36050014), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_SKITTER_FORCE_REG                             ,
+       RULL(0x37050014), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_SKITTER_MODE_REG                                   ,
+       RULL(0x00050010), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_SKITTER_MODE_REG                                ,
+       RULL(0x01050010), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_SKITTER_MODE_REG                                ,
+       RULL(0x02050010), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_SKITTER_MODE_REG                                ,
+       RULL(0x03050010), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_SKITTER_MODE_REG                                ,
+       RULL(0x04050010), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_SKITTER_MODE_REG                                ,
+       RULL(0x05050010), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_SKITTER_MODE_REG                                ,
+       RULL(0x06050010), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_SKITTER_MODE_REG                              ,
+       RULL(0x07050010), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_SKITTER_MODE_REG                              ,
+       RULL(0x08050010), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_SKITTER_MODE_REG                               ,
+       RULL(0x09050010), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_SKITTER_MODE_REG                               ,
+       RULL(0x0C050010), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_SKITTER_MODE_REG                              ,
+       RULL(0x0D050010), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_SKITTER_MODE_REG                              ,
+       RULL(0x0E050010), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_SKITTER_MODE_REG                              ,
+       RULL(0x0F050010), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_SKITTER_MODE_REG                              ,
+       RULL(0x10050010), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_SKITTER_MODE_REG                              ,
+       RULL(0x11050010), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_SKITTER_MODE_REG                              ,
+       RULL(0x12050010), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_SKITTER_MODE_REG                              ,
+       RULL(0x13050010), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_SKITTER_MODE_REG                              ,
+       RULL(0x14050010), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_SKITTER_MODE_REG                              ,
+       RULL(0x15050010), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_SKITTER_MODE_REG                              ,
+       RULL(0x20050010), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_SKITTER_MODE_REG                              ,
+       RULL(0x21050010), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_SKITTER_MODE_REG                              ,
+       RULL(0x22050010), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_SKITTER_MODE_REG                              ,
+       RULL(0x23050010), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_SKITTER_MODE_REG                              ,
+       RULL(0x24050010), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_SKITTER_MODE_REG                              ,
+       RULL(0x25050010), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_SKITTER_MODE_REG                              ,
+       RULL(0x26050010), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_SKITTER_MODE_REG                              ,
+       RULL(0x27050010), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_SKITTER_MODE_REG                              ,
+       RULL(0x28050010), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_SKITTER_MODE_REG                              ,
+       RULL(0x29050010), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_SKITTER_MODE_REG                              ,
+       RULL(0x2A050010), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_SKITTER_MODE_REG                              ,
+       RULL(0x2B050010), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_SKITTER_MODE_REG                              ,
+       RULL(0x2C050010), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_SKITTER_MODE_REG                              ,
+       RULL(0x2D050010), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_SKITTER_MODE_REG                              ,
+       RULL(0x2E050010), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_SKITTER_MODE_REG                              ,
+       RULL(0x2F050010), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_SKITTER_MODE_REG                              ,
+       RULL(0x30050010), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_SKITTER_MODE_REG                              ,
+       RULL(0x31050010), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_SKITTER_MODE_REG                              ,
+       RULL(0x32050010), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_SKITTER_MODE_REG                              ,
+       RULL(0x33050010), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_SKITTER_MODE_REG                              ,
+       RULL(0x34050010), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_SKITTER_MODE_REG                              ,
+       RULL(0x35050010), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_SKITTER_MODE_REG                              ,
+       RULL(0x36050010), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_SKITTER_MODE_REG                              ,
+       RULL(0x37050010), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_SLAVE_CONFIG_REG                                   ,
+       RULL(0x000F001E), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_SLAVE_CONFIG_REG                                ,
+       RULL(0x010F001E), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_SLAVE_CONFIG_REG                                ,
+       RULL(0x020F001E), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_SLAVE_CONFIG_REG                                ,
+       RULL(0x030F001E), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_SLAVE_CONFIG_REG                                ,
+       RULL(0x040F001E), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_SLAVE_CONFIG_REG                                ,
+       RULL(0x050F001E), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_SLAVE_CONFIG_REG                                ,
+       RULL(0x060F001E), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_SLAVE_CONFIG_REG                              ,
+       RULL(0x070F001E), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_SLAVE_CONFIG_REG                              ,
+       RULL(0x080F001E), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_SLAVE_CONFIG_REG                               ,
+       RULL(0x090F001E), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_SLAVE_CONFIG_REG                               ,
+       RULL(0x0C0F001E), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_SLAVE_CONFIG_REG                              ,
+       RULL(0x0D0F001E), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_SLAVE_CONFIG_REG                              ,
+       RULL(0x0E0F001E), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_SLAVE_CONFIG_REG                              ,
+       RULL(0x0F0F001E), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_SLAVE_CONFIG_REG                              ,
+       RULL(0x100F001E), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_SLAVE_CONFIG_REG                              ,
+       RULL(0x110F001E), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_SLAVE_CONFIG_REG                              ,
+       RULL(0x120F001E), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_SLAVE_CONFIG_REG                              ,
+       RULL(0x130F001E), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_SLAVE_CONFIG_REG                              ,
+       RULL(0x140F001E), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_SLAVE_CONFIG_REG                              ,
+       RULL(0x150F001E), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_SLAVE_CONFIG_REG                              ,
+       RULL(0x200F001E), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_SLAVE_CONFIG_REG                              ,
+       RULL(0x210F001E), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_SLAVE_CONFIG_REG                              ,
+       RULL(0x220F001E), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_SLAVE_CONFIG_REG                              ,
+       RULL(0x230F001E), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_SLAVE_CONFIG_REG                              ,
+       RULL(0x240F001E), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_SLAVE_CONFIG_REG                              ,
+       RULL(0x250F001E), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_SLAVE_CONFIG_REG                              ,
+       RULL(0x260F001E), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_SLAVE_CONFIG_REG                              ,
+       RULL(0x270F001E), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_SLAVE_CONFIG_REG                              ,
+       RULL(0x280F001E), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_SLAVE_CONFIG_REG                              ,
+       RULL(0x290F001E), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_SLAVE_CONFIG_REG                              ,
+       RULL(0x2A0F001E), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_SLAVE_CONFIG_REG                              ,
+       RULL(0x2B0F001E), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_SLAVE_CONFIG_REG                              ,
+       RULL(0x2C0F001E), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_SLAVE_CONFIG_REG                              ,
+       RULL(0x2D0F001E), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_SLAVE_CONFIG_REG                              ,
+       RULL(0x2E0F001E), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_SLAVE_CONFIG_REG                              ,
+       RULL(0x2F0F001E), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_SLAVE_CONFIG_REG                              ,
+       RULL(0x300F001E), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_SLAVE_CONFIG_REG                              ,
+       RULL(0x310F001E), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_SLAVE_CONFIG_REG                              ,
+       RULL(0x320F001E), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_SLAVE_CONFIG_REG                              ,
+       RULL(0x330F001E), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_SLAVE_CONFIG_REG                              ,
+       RULL(0x340F001E), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_SLAVE_CONFIG_REG                              ,
+       RULL(0x350F001E), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_SLAVE_CONFIG_REG                              ,
+       RULL(0x360F001E), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_SLAVE_CONFIG_REG                              ,
+       RULL(0x370F001E), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG32( PERV_SNS1LTH_FSI                                        ,
+       RULL(0x0000281D), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SNS1LTH_FSI_BYTE                                   ,
+       RULL(0x00002874), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SNS1LTH_SCOM                                       ,
+       RULL(0x0005001D), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SNS1LTH                                        ,
+       RULL(0x0005001D), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_SNS2LTH_FSI                                        ,
+       RULL(0x0000281E), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SNS2LTH_FSI_BYTE                                   ,
+       RULL(0x00002878), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SNS2LTH_SCOM                                       ,
+       RULL(0x0005001E), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SNS2LTH                                        ,
+       RULL(0x0005001E), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_FSI2PIB_STATUS_FSI                                 ,
+       RULL(0x00001007), SH_UNT_PERV_FSI2PIB,
+       SH_ACS_FSI       ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI2PIB_STATUS_FSI_BYTE                            ,
+       RULL(0x0000101C), SH_UNT_PERV_FSI2PIB,
+       SH_ACS_FSI_BYTE  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_STATUS_FSI                                ,
+       RULL(0x00000C07), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI       ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_STATUS_FSI_BYTE                           ,
+       RULL(0x00000C1C), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI_BYTE  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PERV_0_FSII2C_STATUS_REGISTER                           ,
+       RULL(0x00001807), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSII2C_STATUS_REGISTER                             ,
+       RULL(0x00001807), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PERV_STAT_RDDAT_ERRES                                   ,
+       RULL(0x00030001), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_STAT_RDDAT_ERRES                               ,
+       RULL(0x00030001), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+
+REG64( PERV_SYNC_CONFIG                                        ,
+       RULL(0x00030000), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_SYNC_CONFIG                                     ,
+       RULL(0x01030000), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_SYNC_CONFIG                                     ,
+       RULL(0x02030000), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_SYNC_CONFIG                                     ,
+       RULL(0x03030000), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_SYNC_CONFIG                                     ,
+       RULL(0x04030000), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_SYNC_CONFIG                                     ,
+       RULL(0x05030000), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_SYNC_CONFIG                                     ,
+       RULL(0x06030000), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_SYNC_CONFIG                                   ,
+       RULL(0x07030000), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_SYNC_CONFIG                                   ,
+       RULL(0x08030000), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_SYNC_CONFIG                                    ,
+       RULL(0x09030000), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_SYNC_CONFIG                                    ,
+       RULL(0x0C030000), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_SYNC_CONFIG                                   ,
+       RULL(0x0D030000), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_SYNC_CONFIG                                   ,
+       RULL(0x0E030000), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_SYNC_CONFIG                                   ,
+       RULL(0x0F030000), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_SYNC_CONFIG                                   ,
+       RULL(0x10030000), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_SYNC_CONFIG                                   ,
+       RULL(0x11030000), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_SYNC_CONFIG                                   ,
+       RULL(0x12030000), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_SYNC_CONFIG                                   ,
+       RULL(0x13030000), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_SYNC_CONFIG                                   ,
+       RULL(0x14030000), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_SYNC_CONFIG                                   ,
+       RULL(0x15030000), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_SYNC_CONFIG                                   ,
+       RULL(0x20030000), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_SYNC_CONFIG                                   ,
+       RULL(0x21030000), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_SYNC_CONFIG                                   ,
+       RULL(0x22030000), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_SYNC_CONFIG                                   ,
+       RULL(0x23030000), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_SYNC_CONFIG                                   ,
+       RULL(0x24030000), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_SYNC_CONFIG                                   ,
+       RULL(0x25030000), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_SYNC_CONFIG                                   ,
+       RULL(0x26030000), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_SYNC_CONFIG                                   ,
+       RULL(0x27030000), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_SYNC_CONFIG                                   ,
+       RULL(0x28030000), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_SYNC_CONFIG                                   ,
+       RULL(0x29030000), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_SYNC_CONFIG                                   ,
+       RULL(0x2A030000), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_SYNC_CONFIG                                   ,
+       RULL(0x2B030000), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_SYNC_CONFIG                                   ,
+       RULL(0x2C030000), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_SYNC_CONFIG                                   ,
+       RULL(0x2D030000), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_SYNC_CONFIG                                   ,
+       RULL(0x2E030000), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_SYNC_CONFIG                                   ,
+       RULL(0x2F030000), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_SYNC_CONFIG                                   ,
+       RULL(0x30030000), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_SYNC_CONFIG                                   ,
+       RULL(0x31030000), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_SYNC_CONFIG                                   ,
+       RULL(0x32030000), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_SYNC_CONFIG                                   ,
+       RULL(0x33030000), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_SYNC_CONFIG                                   ,
+       RULL(0x34030000), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_SYNC_CONFIG                                   ,
+       RULL(0x35030000), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_SYNC_CONFIG                                   ,
+       RULL(0x36030000), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_SYNC_CONFIG                                   ,
+       RULL(0x37030000), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_THERM_MODE_REG                                     ,
+       RULL(0x0005000F), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_THERM_MODE_REG                                  ,
+       RULL(0x0105000F), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_THERM_MODE_REG                                  ,
+       RULL(0x0205000F), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_THERM_MODE_REG                                  ,
+       RULL(0x0305000F), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_THERM_MODE_REG                                  ,
+       RULL(0x0405000F), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_THERM_MODE_REG                                  ,
+       RULL(0x0505000F), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_THERM_MODE_REG                                  ,
+       RULL(0x0605000F), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_THERM_MODE_REG                                ,
+       RULL(0x0705000F), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_THERM_MODE_REG                                ,
+       RULL(0x0805000F), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_THERM_MODE_REG                                 ,
+       RULL(0x0905000F), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_THERM_MODE_REG                                 ,
+       RULL(0x0C05000F), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_THERM_MODE_REG                                ,
+       RULL(0x0D05000F), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_THERM_MODE_REG                                ,
+       RULL(0x0E05000F), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_THERM_MODE_REG                                ,
+       RULL(0x0F05000F), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_THERM_MODE_REG                                ,
+       RULL(0x1005000F), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_THERM_MODE_REG                                ,
+       RULL(0x1105000F), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_THERM_MODE_REG                                ,
+       RULL(0x1205000F), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_THERM_MODE_REG                                ,
+       RULL(0x1305000F), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_THERM_MODE_REG                                ,
+       RULL(0x1405000F), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_THERM_MODE_REG                                ,
+       RULL(0x1505000F), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_THERM_MODE_REG                                ,
+       RULL(0x2005000F), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_THERM_MODE_REG                                ,
+       RULL(0x2105000F), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_THERM_MODE_REG                                ,
+       RULL(0x2205000F), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_THERM_MODE_REG                                ,
+       RULL(0x2305000F), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_THERM_MODE_REG                                ,
+       RULL(0x2405000F), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_THERM_MODE_REG                                ,
+       RULL(0x2505000F), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_THERM_MODE_REG                                ,
+       RULL(0x2605000F), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_THERM_MODE_REG                                ,
+       RULL(0x2705000F), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_THERM_MODE_REG                                ,
+       RULL(0x2805000F), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_THERM_MODE_REG                                ,
+       RULL(0x2905000F), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_THERM_MODE_REG                                ,
+       RULL(0x2A05000F), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_THERM_MODE_REG                                ,
+       RULL(0x2B05000F), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_THERM_MODE_REG                                ,
+       RULL(0x2C05000F), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_THERM_MODE_REG                                ,
+       RULL(0x2D05000F), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_THERM_MODE_REG                                ,
+       RULL(0x2E05000F), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_THERM_MODE_REG                                ,
+       RULL(0x2F05000F), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_THERM_MODE_REG                                ,
+       RULL(0x3005000F), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_THERM_MODE_REG                                ,
+       RULL(0x3105000F), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_THERM_MODE_REG                                ,
+       RULL(0x3205000F), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_THERM_MODE_REG                                ,
+       RULL(0x3305000F), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_THERM_MODE_REG                                ,
+       RULL(0x3405000F), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_THERM_MODE_REG                                ,
+       RULL(0x3505000F), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_THERM_MODE_REG                                ,
+       RULL(0x3605000F), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_THERM_MODE_REG                                ,
+       RULL(0x3705000F), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_TIMEOUT_REG                                        ,
+       RULL(0x000F0019), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_TIMEOUT_REG                                    ,
+       RULL(0x000F0019), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+REG64( PERV_TP_TIMEOUT_REG                                     ,
+       RULL(0x010F0010), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_TIMEOUT_REG                                     ,
+       RULL(0x020F0010), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_TIMEOUT_REG                                     ,
+       RULL(0x030F0010), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_TIMEOUT_REG                                     ,
+       RULL(0x040F0010), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_TIMEOUT_REG                                     ,
+       RULL(0x050F0010), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_TIMEOUT_REG                                     ,
+       RULL(0x060F0010), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_TIMEOUT_REG                                   ,
+       RULL(0x070F0010), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_TIMEOUT_REG                                   ,
+       RULL(0x080F0010), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_TIMEOUT_REG                                    ,
+       RULL(0x090F0010), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_TIMEOUT_REG                                    ,
+       RULL(0x0C0F0010), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_TIMEOUT_REG                                   ,
+       RULL(0x0D0F0010), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_TIMEOUT_REG                                   ,
+       RULL(0x0E0F0010), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_TIMEOUT_REG                                   ,
+       RULL(0x0F0F0010), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_TIMEOUT_REG                                   ,
+       RULL(0x100F0010), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_TIMEOUT_REG                                   ,
+       RULL(0x110F0010), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_TIMEOUT_REG                                   ,
+       RULL(0x120F0010), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_TIMEOUT_REG                                   ,
+       RULL(0x130F0010), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_TIMEOUT_REG                                   ,
+       RULL(0x140F0010), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_TIMEOUT_REG                                   ,
+       RULL(0x150F0010), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_TIMEOUT_REG                                   ,
+       RULL(0x200F0010), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_TIMEOUT_REG                                   ,
+       RULL(0x210F0010), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_TIMEOUT_REG                                   ,
+       RULL(0x220F0010), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_TIMEOUT_REG                                   ,
+       RULL(0x230F0010), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_TIMEOUT_REG                                   ,
+       RULL(0x240F0010), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_TIMEOUT_REG                                   ,
+       RULL(0x250F0010), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_TIMEOUT_REG                                   ,
+       RULL(0x260F0010), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_TIMEOUT_REG                                   ,
+       RULL(0x270F0010), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_TIMEOUT_REG                                   ,
+       RULL(0x280F0010), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_TIMEOUT_REG                                   ,
+       RULL(0x290F0010), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_TIMEOUT_REG                                   ,
+       RULL(0x2A0F0010), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_TIMEOUT_REG                                   ,
+       RULL(0x2B0F0010), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_TIMEOUT_REG                                   ,
+       RULL(0x2C0F0010), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_TIMEOUT_REG                                   ,
+       RULL(0x2D0F0010), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_TIMEOUT_REG                                   ,
+       RULL(0x2E0F0010), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_TIMEOUT_REG                                   ,
+       RULL(0x2F0F0010), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_TIMEOUT_REG                                   ,
+       RULL(0x300F0010), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_TIMEOUT_REG                                   ,
+       RULL(0x310F0010), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_TIMEOUT_REG                                   ,
+       RULL(0x320F0010), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_TIMEOUT_REG                                   ,
+       RULL(0x330F0010), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_TIMEOUT_REG                                   ,
+       RULL(0x340F0010), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_TIMEOUT_REG                                   ,
+       RULL(0x350F0010), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_TIMEOUT_REG                                   ,
+       RULL(0x360F0010), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_TIMEOUT_REG                                   ,
+       RULL(0x370F0010), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_TIMESTAMP_COUNTER_READ                             ,
+       RULL(0x0005001C), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_TIMESTAMP_COUNTER_READ                          ,
+       RULL(0x0105001C), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_N0_TIMESTAMP_COUNTER_READ                          ,
+       RULL(0x0205001C), SH_UNT_PERV_2   , SH_ACS_SCOM_RO   );
+REG64( PERV_N1_TIMESTAMP_COUNTER_READ                          ,
+       RULL(0x0305001C), SH_UNT_PERV_3   , SH_ACS_SCOM_RO   );
+REG64( PERV_N2_TIMESTAMP_COUNTER_READ                          ,
+       RULL(0x0405001C), SH_UNT_PERV_4   , SH_ACS_SCOM_RO   );
+REG64( PERV_N3_TIMESTAMP_COUNTER_READ                          ,
+       RULL(0x0505001C), SH_UNT_PERV_5   , SH_ACS_SCOM_RO   );
+REG64( PERV_XB_TIMESTAMP_COUNTER_READ                          ,
+       RULL(0x0605001C), SH_UNT_PERV_6   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC01_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x0705001C), SH_UNT_PERV_7   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC23_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x0805001C), SH_UNT_PERV_8   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB0_TIMESTAMP_COUNTER_READ                         ,
+       RULL(0x0905001C), SH_UNT_PERV_9   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB3_TIMESTAMP_COUNTER_READ                         ,
+       RULL(0x0C05001C), SH_UNT_PERV_12  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI0_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x0D05001C), SH_UNT_PERV_13  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI1_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x0E05001C), SH_UNT_PERV_14  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI2_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x0F05001C), SH_UNT_PERV_15  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP00_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x1005001C), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x1105001C), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x1205001C), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x1305001C), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x1405001C), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x1505001C), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x2005001C), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x2105001C), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x2205001C), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x2305001C), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x2405001C), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x2505001C), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x2605001C), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x2705001C), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x2805001C), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x2905001C), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x2A05001C), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x2B05001C), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x2C05001C), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x2D05001C), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x2E05001C), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x2F05001C), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x3005001C), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x3105001C), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x3205001C), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x3305001C), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x3405001C), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x3505001C), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x3605001C), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_TIMESTAMP_COUNTER_READ                        ,
+       RULL(0x3705001C), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_TOD_CHIP_CTRL_REG                                  ,
+       RULL(0x00040010), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_TOD_CHIP_CTRL_REG                              ,
+       RULL(0x00040010), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_TOD_ERROR_INJECT_REG                               ,
+       RULL(0x00040031), SH_UNT_PERV     , SH_ACS_SCOM_WO   );
+REG64( PERV_PIB_TOD_ERROR_INJECT_REG                           ,
+       RULL(0x00040031), SH_UNT_PERV_0   , SH_ACS_SCOM_WO   );
+
+REG64( PERV_TOD_ERROR_MASK_REG                                 ,
+       RULL(0x00040032), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_ERROR_MASK_REG                             ,
+       RULL(0x00040032), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_ERROR_REG                                      ,
+       RULL(0x00040030), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_ERROR_REG                                  ,
+       RULL(0x00040030), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_ERROR_ROUTING_REG                              ,
+       RULL(0x00040033), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_ERROR_ROUTING_REG                          ,
+       RULL(0x00040033), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_FSM_REG                                        ,
+       RULL(0x00040024), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_TOD_FSM_REG                                    ,
+       RULL(0x00040024), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_TOD_I_PATH_CTRL_REG                                ,
+       RULL(0x00040006), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_TOD_I_PATH_CTRL_REG                            ,
+       RULL(0x00040006), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_TOD_LOAD_TOD_MOD_REG                               ,
+       RULL(0x00040018), SH_UNT_PERV     , SH_ACS_SCOM_WO   );
+REG64( PERV_PIB_TOD_LOAD_TOD_MOD_REG                           ,
+       RULL(0x00040018), SH_UNT_PERV_0   , SH_ACS_SCOM_WO   );
+
+REG64( PERV_TOD_LOAD_TOD_REG                                   ,
+       RULL(0x00040021), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_LOAD_TOD_REG                               ,
+       RULL(0x00040021), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_LOW_ORDER_STEP_REG                             ,
+       RULL(0x00040023), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_LOW_ORDER_STEP_REG                         ,
+       RULL(0x00040023), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_MISC_RESET_REG                                 ,
+       RULL(0x0004000B), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_MISC_RESET_REG                             ,
+       RULL(0x0004000B), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_MOVE_TOD_TO_TB_REG                             ,
+       RULL(0x00040017), SH_UNT_PERV     , SH_ACS_SCOM_WO   );
+REG64( PERV_PIB_TOD_MOVE_TOD_TO_TB_REG                         ,
+       RULL(0x00040017), SH_UNT_PERV_0   , SH_ACS_SCOM_WO   );
+
+REG64( PERV_TOD_M_PATH_0_STEP_STEER_REG                        ,
+       RULL(0x0004000E), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_M_PATH_0_STEP_STEER_REG                    ,
+       RULL(0x0004000E), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_M_PATH_1_STEP_STEER_REG                        ,
+       RULL(0x0004000F), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_M_PATH_1_STEP_STEER_REG                    ,
+       RULL(0x0004000F), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_M_PATH_CTRL_REG                                ,
+       RULL(0x00040000), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_M_PATH_CTRL_REG                            ,
+       RULL(0x00040000), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_M_PATH_STATUS_REG                              ,
+       RULL(0x00040009), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_M_PATH_STATUS_REG                          ,
+       RULL(0x00040009), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_PRI_PORT_0_CTRL_REG                            ,
+       RULL(0x00040001), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_PRI_PORT_0_CTRL_REG                        ,
+       RULL(0x00040001), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_PRI_PORT_1_CTRL_REG                            ,
+       RULL(0x00040002), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_PRI_PORT_1_CTRL_REG                        ,
+       RULL(0x00040002), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_PROBE_SELECT_REG                               ,
+       RULL(0x0004000C), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_PROBE_SELECT_REG                           ,
+       RULL(0x0004000C), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_PSS_MSS_CTRL_REG                               ,
+       RULL(0x00040007), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_PSS_MSS_CTRL_REG                           ,
+       RULL(0x00040007), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_PSS_MSS_STATUS_REG                             ,
+       RULL(0x00040008), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_TOD_PSS_MSS_STATUS_REG                         ,
+       RULL(0x00040008), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_TOD_RX_TTYPE_CTRL_REG                              ,
+       RULL(0x00040029), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_RX_TTYPE_CTRL_REG                          ,
+       RULL(0x00040029), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_SEC_PORT_0_CTRL_REG                            ,
+       RULL(0x00040003), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_SEC_PORT_0_CTRL_REG                        ,
+       RULL(0x00040003), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_SEC_PORT_1_CTRL_REG                            ,
+       RULL(0x00040004), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_SEC_PORT_1_CTRL_REG                        ,
+       RULL(0x00040004), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_START_TOD_REG                                  ,
+       RULL(0x00040022), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_TOD_START_TOD_REG                              ,
+       RULL(0x00040022), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_TOD_S_PATH_CTRL_REG                                ,
+       RULL(0x00040005), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_S_PATH_CTRL_REG                            ,
+       RULL(0x00040005), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_S_PATH_STATUS_REG                              ,
+       RULL(0x0004000A), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_S_PATH_STATUS_REG                          ,
+       RULL(0x0004000A), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_TIMER_REG                                      ,
+       RULL(0x0004000D), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_TOD_TIMER_REG                                  ,
+       RULL(0x0004000D), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_TOD_TRACE_DATA_1_REG                               ,
+       RULL(0x0004001D), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_TRACE_DATA_1_REG                           ,
+       RULL(0x0004001D), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_TRACE_DATA_2_REG                               ,
+       RULL(0x0004001E), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_TRACE_DATA_2_REG                           ,
+       RULL(0x0004001E), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_TRACE_DATA_3_REG                               ,
+       RULL(0x0004001F), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_TRACE_DATA_3_REG                           ,
+       RULL(0x0004001F), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_TX_TTYPE_0_REG                                 ,
+       RULL(0x00040011), SH_UNT_PERV     , SH_ACS_SCOM_WO   );
+REG64( PERV_PIB_TOD_TX_TTYPE_0_REG                             ,
+       RULL(0x00040011), SH_UNT_PERV_0   , SH_ACS_SCOM_WO   );
+
+REG64( PERV_TOD_TX_TTYPE_1_REG                                 ,
+       RULL(0x00040012), SH_UNT_PERV     , SH_ACS_SCOM_WO   );
+REG64( PERV_PIB_TOD_TX_TTYPE_1_REG                             ,
+       RULL(0x00040012), SH_UNT_PERV_0   , SH_ACS_SCOM_WO   );
+
+REG64( PERV_TOD_TX_TTYPE_2_REG                                 ,
+       RULL(0x00040013), SH_UNT_PERV     , SH_ACS_SCOM_WO   );
+REG64( PERV_PIB_TOD_TX_TTYPE_2_REG                             ,
+       RULL(0x00040013), SH_UNT_PERV_0   , SH_ACS_SCOM_WO   );
+
+REG64( PERV_TOD_TX_TTYPE_3_REG                                 ,
+       RULL(0x00040014), SH_UNT_PERV     , SH_ACS_SCOM_WO   );
+REG64( PERV_PIB_TOD_TX_TTYPE_3_REG                             ,
+       RULL(0x00040014), SH_UNT_PERV_0   , SH_ACS_SCOM_WO   );
+
+REG64( PERV_TOD_TX_TTYPE_4_REG                                 ,
+       RULL(0x00040015), SH_UNT_PERV     , SH_ACS_SCOM_WO   );
+REG64( PERV_PIB_TOD_TX_TTYPE_4_REG                             ,
+       RULL(0x00040015), SH_UNT_PERV_0   , SH_ACS_SCOM_WO   );
+
+REG64( PERV_TOD_TX_TTYPE_5_REG                                 ,
+       RULL(0x00040016), SH_UNT_PERV     , SH_ACS_SCOM_WO   );
+REG64( PERV_PIB_TOD_TX_TTYPE_5_REG                             ,
+       RULL(0x00040016), SH_UNT_PERV_0   , SH_ACS_SCOM_WO   );
+
+REG64( PERV_TOD_TX_TTYPE_CTRL_REG                              ,
+       RULL(0x00040027), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_TOD_TX_TTYPE_CTRL_REG                          ,
+       RULL(0x00040027), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_TOD_VALUE_REG                                      ,
+       RULL(0x00040020), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_TOD_VALUE_REG                                  ,
+       RULL(0x00040020), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_FSI2PIB_TRUE_MASK_FSI                              ,
+       RULL(0x0000100D), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI       );
+REG32( PERV_FSI2PIB_TRUE_MASK_FSI_BYTE                         ,
+       RULL(0x00001034), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE  );
+REG32( PERV_FSISHIFT_TRUE_MASK_FSI                             ,
+       RULL(0x00000C0D), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_TRUE_MASK_FSI_BYTE                        ,
+       RULL(0x00000C34), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE  );
+
+REG64( PERV_VITAL_SCAN_OUT                                     ,
+       RULL(0x000F0017), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_VITAL_SCAN_OUT                                  ,
+       RULL(0x010F0017), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_N0_VITAL_SCAN_OUT                                  ,
+       RULL(0x020F0017), SH_UNT_PERV_2   , SH_ACS_SCOM_RO   );
+REG64( PERV_N1_VITAL_SCAN_OUT                                  ,
+       RULL(0x030F0017), SH_UNT_PERV_3   , SH_ACS_SCOM_RO   );
+REG64( PERV_N2_VITAL_SCAN_OUT                                  ,
+       RULL(0x040F0017), SH_UNT_PERV_4   , SH_ACS_SCOM_RO   );
+REG64( PERV_N3_VITAL_SCAN_OUT                                  ,
+       RULL(0x050F0017), SH_UNT_PERV_5   , SH_ACS_SCOM_RO   );
+REG64( PERV_XB_VITAL_SCAN_OUT                                  ,
+       RULL(0x060F0017), SH_UNT_PERV_6   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC01_VITAL_SCAN_OUT                                ,
+       RULL(0x070F0017), SH_UNT_PERV_7   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC23_VITAL_SCAN_OUT                                ,
+       RULL(0x080F0017), SH_UNT_PERV_8   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB0_VITAL_SCAN_OUT                                 ,
+       RULL(0x090F0017), SH_UNT_PERV_9   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB3_VITAL_SCAN_OUT                                 ,
+       RULL(0x0C0F0017), SH_UNT_PERV_12  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI0_VITAL_SCAN_OUT                                ,
+       RULL(0x0D0F0017), SH_UNT_PERV_13  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI1_VITAL_SCAN_OUT                                ,
+       RULL(0x0E0F0017), SH_UNT_PERV_14  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI2_VITAL_SCAN_OUT                                ,
+       RULL(0x0F0F0017), SH_UNT_PERV_15  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP00_VITAL_SCAN_OUT                                ,
+       RULL(0x100F0017), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_VITAL_SCAN_OUT                                ,
+       RULL(0x110F0017), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_VITAL_SCAN_OUT                                ,
+       RULL(0x120F0017), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_VITAL_SCAN_OUT                                ,
+       RULL(0x130F0017), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_VITAL_SCAN_OUT                                ,
+       RULL(0x140F0017), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_VITAL_SCAN_OUT                                ,
+       RULL(0x150F0017), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_VITAL_SCAN_OUT                                ,
+       RULL(0x200F0017), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_VITAL_SCAN_OUT                                ,
+       RULL(0x210F0017), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_VITAL_SCAN_OUT                                ,
+       RULL(0x220F0017), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_VITAL_SCAN_OUT                                ,
+       RULL(0x230F0017), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_VITAL_SCAN_OUT                                ,
+       RULL(0x240F0017), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_VITAL_SCAN_OUT                                ,
+       RULL(0x250F0017), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_VITAL_SCAN_OUT                                ,
+       RULL(0x260F0017), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_VITAL_SCAN_OUT                                ,
+       RULL(0x270F0017), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_VITAL_SCAN_OUT                                ,
+       RULL(0x280F0017), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_VITAL_SCAN_OUT                                ,
+       RULL(0x290F0017), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_VITAL_SCAN_OUT                                ,
+       RULL(0x2A0F0017), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_VITAL_SCAN_OUT                                ,
+       RULL(0x2B0F0017), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_VITAL_SCAN_OUT                                ,
+       RULL(0x2C0F0017), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_VITAL_SCAN_OUT                                ,
+       RULL(0x2D0F0017), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_VITAL_SCAN_OUT                                ,
+       RULL(0x2E0F0017), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_VITAL_SCAN_OUT                                ,
+       RULL(0x2F0F0017), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_VITAL_SCAN_OUT                                ,
+       RULL(0x300F0017), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_VITAL_SCAN_OUT                                ,
+       RULL(0x310F0017), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_VITAL_SCAN_OUT                                ,
+       RULL(0x320F0017), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_VITAL_SCAN_OUT                                ,
+       RULL(0x330F0017), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_VITAL_SCAN_OUT                                ,
+       RULL(0x340F0017), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_VITAL_SCAN_OUT                                ,
+       RULL(0x350F0017), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_VITAL_SCAN_OUT                                ,
+       RULL(0x360F0017), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_VITAL_SCAN_OUT                                ,
+       RULL(0x370F0017), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_0_FSII2C_WATER_MARK_REGISTER                       ,
+       RULL(0x00001803), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM      );
+REG32( PERV_FSII2C_WATER_MARK_REGISTER                         ,
+       RULL(0x00001803), SH_UNT_PERV_FSII2C, SH_ACS_SCOM      );
+
+REG64( PERV_XSTOP1                                             ,
+       RULL(0x0003000C), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_XSTOP1                                          ,
+       RULL(0x0103000C), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_XSTOP1                                          ,
+       RULL(0x0203000C), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_XSTOP1                                          ,
+       RULL(0x0303000C), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_XSTOP1                                          ,
+       RULL(0x0403000C), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_XSTOP1                                          ,
+       RULL(0x0503000C), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_XSTOP1                                          ,
+       RULL(0x0603000C), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_XSTOP1                                        ,
+       RULL(0x0703000C), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_XSTOP1                                        ,
+       RULL(0x0803000C), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_XSTOP1                                         ,
+       RULL(0x0903000C), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_XSTOP1                                         ,
+       RULL(0x0C03000C), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_XSTOP1                                        ,
+       RULL(0x0D03000C), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_XSTOP1                                        ,
+       RULL(0x0E03000C), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_XSTOP1                                        ,
+       RULL(0x0F03000C), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_XSTOP1                                        ,
+       RULL(0x1003000C), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_XSTOP1                                        ,
+       RULL(0x1103000C), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_XSTOP1                                        ,
+       RULL(0x1203000C), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_XSTOP1                                        ,
+       RULL(0x1303000C), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_XSTOP1                                        ,
+       RULL(0x1403000C), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_XSTOP1                                        ,
+       RULL(0x1503000C), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_XSTOP1                                        ,
+       RULL(0x2003000C), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_XSTOP1                                        ,
+       RULL(0x2103000C), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_XSTOP1                                        ,
+       RULL(0x2203000C), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_XSTOP1                                        ,
+       RULL(0x2303000C), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_XSTOP1                                        ,
+       RULL(0x2403000C), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_XSTOP1                                        ,
+       RULL(0x2503000C), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_XSTOP1                                        ,
+       RULL(0x2603000C), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_XSTOP1                                        ,
+       RULL(0x2703000C), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_XSTOP1                                        ,
+       RULL(0x2803000C), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_XSTOP1                                        ,
+       RULL(0x2903000C), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_XSTOP1                                        ,
+       RULL(0x2A03000C), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_XSTOP1                                        ,
+       RULL(0x2B03000C), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_XSTOP1                                        ,
+       RULL(0x2C03000C), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_XSTOP1                                        ,
+       RULL(0x2D03000C), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_XSTOP1                                        ,
+       RULL(0x2E03000C), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_XSTOP1                                        ,
+       RULL(0x2F03000C), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_XSTOP1                                        ,
+       RULL(0x3003000C), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_XSTOP1                                        ,
+       RULL(0x3103000C), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_XSTOP1                                        ,
+       RULL(0x3203000C), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_XSTOP1                                        ,
+       RULL(0x3303000C), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_XSTOP1                                        ,
+       RULL(0x3403000C), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_XSTOP1                                        ,
+       RULL(0x3503000C), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_XSTOP1                                        ,
+       RULL(0x3603000C), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_XSTOP1                                        ,
+       RULL(0x3703000C), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_XSTOP2                                             ,
+       RULL(0x0003000D), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_XSTOP2                                          ,
+       RULL(0x0103000D), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_XSTOP2                                          ,
+       RULL(0x0203000D), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_XSTOP2                                          ,
+       RULL(0x0303000D), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_XSTOP2                                          ,
+       RULL(0x0403000D), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_XSTOP2                                          ,
+       RULL(0x0503000D), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_XSTOP2                                          ,
+       RULL(0x0603000D), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_XSTOP2                                        ,
+       RULL(0x0703000D), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_XSTOP2                                        ,
+       RULL(0x0803000D), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_XSTOP2                                         ,
+       RULL(0x0903000D), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_XSTOP2                                         ,
+       RULL(0x0C03000D), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_XSTOP2                                        ,
+       RULL(0x0D03000D), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_XSTOP2                                        ,
+       RULL(0x0E03000D), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_XSTOP2                                        ,
+       RULL(0x0F03000D), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_XSTOP2                                        ,
+       RULL(0x1003000D), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_XSTOP2                                        ,
+       RULL(0x1103000D), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_XSTOP2                                        ,
+       RULL(0x1203000D), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_XSTOP2                                        ,
+       RULL(0x1303000D), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_XSTOP2                                        ,
+       RULL(0x1403000D), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_XSTOP2                                        ,
+       RULL(0x1503000D), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_XSTOP2                                        ,
+       RULL(0x2003000D), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_XSTOP2                                        ,
+       RULL(0x2103000D), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_XSTOP2                                        ,
+       RULL(0x2203000D), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_XSTOP2                                        ,
+       RULL(0x2303000D), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_XSTOP2                                        ,
+       RULL(0x2403000D), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_XSTOP2                                        ,
+       RULL(0x2503000D), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_XSTOP2                                        ,
+       RULL(0x2603000D), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_XSTOP2                                        ,
+       RULL(0x2703000D), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_XSTOP2                                        ,
+       RULL(0x2803000D), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_XSTOP2                                        ,
+       RULL(0x2903000D), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_XSTOP2                                        ,
+       RULL(0x2A03000D), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_XSTOP2                                        ,
+       RULL(0x2B03000D), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_XSTOP2                                        ,
+       RULL(0x2C03000D), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_XSTOP2                                        ,
+       RULL(0x2D03000D), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_XSTOP2                                        ,
+       RULL(0x2E03000D), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_XSTOP2                                        ,
+       RULL(0x2F03000D), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_XSTOP2                                        ,
+       RULL(0x3003000D), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_XSTOP2                                        ,
+       RULL(0x3103000D), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_XSTOP2                                        ,
+       RULL(0x3203000D), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_XSTOP2                                        ,
+       RULL(0x3303000D), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_XSTOP2                                        ,
+       RULL(0x3403000D), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_XSTOP2                                        ,
+       RULL(0x3503000D), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_XSTOP2                                        ,
+       RULL(0x3603000D), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_XSTOP2                                        ,
+       RULL(0x3703000D), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_XSTOP3                                             ,
+       RULL(0x0003000E), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_XSTOP3                                          ,
+       RULL(0x0103000E), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_XSTOP3                                          ,
+       RULL(0x0203000E), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_XSTOP3                                          ,
+       RULL(0x0303000E), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_XSTOP3                                          ,
+       RULL(0x0403000E), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_XSTOP3                                          ,
+       RULL(0x0503000E), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_XSTOP3                                          ,
+       RULL(0x0603000E), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_XSTOP3                                        ,
+       RULL(0x0703000E), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_XSTOP3                                        ,
+       RULL(0x0803000E), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_XSTOP3                                         ,
+       RULL(0x0903000E), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_XSTOP3                                         ,
+       RULL(0x0C03000E), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_XSTOP3                                        ,
+       RULL(0x0D03000E), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_XSTOP3                                        ,
+       RULL(0x0E03000E), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_XSTOP3                                        ,
+       RULL(0x0F03000E), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_XSTOP3                                        ,
+       RULL(0x1003000E), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_XSTOP3                                        ,
+       RULL(0x1103000E), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_XSTOP3                                        ,
+       RULL(0x1203000E), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_XSTOP3                                        ,
+       RULL(0x1303000E), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_XSTOP3                                        ,
+       RULL(0x1403000E), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_XSTOP3                                        ,
+       RULL(0x1503000E), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_XSTOP3                                        ,
+       RULL(0x2003000E), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_XSTOP3                                        ,
+       RULL(0x2103000E), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_XSTOP3                                        ,
+       RULL(0x2203000E), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_XSTOP3                                        ,
+       RULL(0x2303000E), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_XSTOP3                                        ,
+       RULL(0x2403000E), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_XSTOP3                                        ,
+       RULL(0x2503000E), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_XSTOP3                                        ,
+       RULL(0x2603000E), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_XSTOP3                                        ,
+       RULL(0x2703000E), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_XSTOP3                                        ,
+       RULL(0x2803000E), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_XSTOP3                                        ,
+       RULL(0x2903000E), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_XSTOP3                                        ,
+       RULL(0x2A03000E), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_XSTOP3                                        ,
+       RULL(0x2B03000E), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_XSTOP3                                        ,
+       RULL(0x2C03000E), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_XSTOP3                                        ,
+       RULL(0x2D03000E), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_XSTOP3                                        ,
+       RULL(0x2E03000E), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_XSTOP3                                        ,
+       RULL(0x2F03000E), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_XSTOP3                                        ,
+       RULL(0x3003000E), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_XSTOP3                                        ,
+       RULL(0x3103000E), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_XSTOP3                                        ,
+       RULL(0x3203000E), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_XSTOP3                                        ,
+       RULL(0x3303000E), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_XSTOP3                                        ,
+       RULL(0x3403000E), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_XSTOP3                                        ,
+       RULL(0x3503000E), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_XSTOP3                                        ,
+       RULL(0x3603000E), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_XSTOP3                                        ,
+       RULL(0x3703000E), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_XSTOP_INTERRUPT_REG                                ,
+       RULL(0x000F001C), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_TP_XSTOP_INTERRUPT_REG                             ,
+       RULL(0x010F001C), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_XSTOP_INTERRUPT_REG                             ,
+       RULL(0x020F001C), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_XSTOP_INTERRUPT_REG                             ,
+       RULL(0x030F001C), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_XSTOP_INTERRUPT_REG                             ,
+       RULL(0x040F001C), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_XSTOP_INTERRUPT_REG                             ,
+       RULL(0x050F001C), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_XSTOP_INTERRUPT_REG                             ,
+       RULL(0x060F001C), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x070F001C), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x080F001C), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_XSTOP_INTERRUPT_REG                            ,
+       RULL(0x090F001C), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_XSTOP_INTERRUPT_REG                            ,
+       RULL(0x0C0F001C), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x0D0F001C), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x0E0F001C), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x0F0F001C), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x100F001C), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x110F001C), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x120F001C), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x130F001C), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x140F001C), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x150F001C), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x200F001C), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x210F001C), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x220F001C), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x230F001C), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x240F001C), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x250F001C), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x260F001C), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x270F001C), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x280F001C), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x290F001C), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x2A0F001C), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x2B0F001C), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x2C0F001C), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x2D0F001C), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x2E0F001C), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x2F0F001C), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x300F001C), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x310F001C), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x320F001C), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x330F001C), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x340F001C), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x350F001C), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x360F001C), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_XSTOP_INTERRUPT_REG                           ,
+       RULL(0x370F001C), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+#endif
+
diff --git a/src/ppe/importtemp/common/include/perv_scom_addresses_fixes.H b/src/ppe/importtemp/common/include/perv_scom_addresses_fixes.H
new file mode 100644
index 0000000..97c73fc
--- /dev/null
+++ b/src/ppe/importtemp/common/include/perv_scom_addresses_fixes.H
@@ -0,0 +1,50 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/common/include/perv_scom_addresses_fixes.H $ */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file perv_scom_addresses_fixes.H
+/// @brief The *scom_addresses.H files are  generated form figtree, but
+///        the figree can be wrong.  This file is included at the end
+///        of scom_addresses.H and allows incorrect constants to be
+///        fixed manually.
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: ? <?>
+// *HWP Team: SAO
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#ifndef __PERV_SCOM_ADDRESSES_FIXES_H
+#define __PERV_SCOM_ADDRESSES_FIXES_H
+
+//Example,
+//Copy the whole line from the *scom_addresses.H file.  Then add
+//FIX in front of REG, and add another paramter that is the new
+//corrected value.
+//FIXREG64( PU_ALTD_ADDR_REG,
+//          RULL(0x05022800), SH_UNT, SH_ACS_SCOM,
+//          RULL(0x00090000)
+//        );
+
+#endif
diff --git a/src/ppe/importtemp/common/include/perv_scom_addresses_fld.H b/src/ppe/importtemp/common/include/perv_scom_addresses_fld.H
new file mode 100644
index 0000000..8460e8c
--- /dev/null
+++ b/src/ppe/importtemp/common/include/perv_scom_addresses_fld.H
@@ -0,0 +1,6301 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/common/include/perv_scom_addresses_fld.H $ */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file perv_scom_addresses_fld.H
+/// @brief  Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+#ifndef __PERV_SCOM_ADDRESSES_FLD_H
+#define __PERV_SCOM_ADDRESSES_FLD_H
+
+
+#include <scom_template_consts.H>
+#include <perv_scom_addresses_fld_fixes.H>
+
+REG64_FLD( PERV_1_ATOMIC_LOCK_REG_ENABLE                           , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PERV_1_ATOMIC_LOCK_REG_ID                               , 1   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ID         );
+REG64_FLD( PERV_1_ATOMIC_LOCK_REG_ID_LEN                           , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ID_LEN     );
+REG64_FLD( PERV_1_ATOMIC_LOCK_REG_ACTIVITY                         , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ACTIVITY   );
+REG64_FLD( PERV_1_ATOMIC_LOCK_REG_ACTIVITY_LEN                     , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ACTIVITY_LEN );
+
+REG64_FLD( PERV_1_BIST_TC_START_TEST_DC                            , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_TC_START_TEST_DC );
+REG64_FLD( PERV_1_BIST_TC_SRAM_ABIST_MODE_DC                       , 1   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_TC_SRAM_ABIST_MODE_DC );
+REG64_FLD( PERV_1_BIST_TC_EDRAM_ABIST_MODE_DC                      , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_TC_EDRAM_ABIST_MODE_DC );
+REG64_FLD( PERV_1_BIST_TC_IOBIST_MODE_DC                           , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_TC_IOBIST_MODE_DC );
+REG64_FLD( PERV_1_BIST_PERV                                        , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PERV       );
+REG64_FLD( PERV_1_BIST_UNIT1                                       , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT1      );
+REG64_FLD( PERV_1_BIST_UNIT2                                       , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT2      );
+REG64_FLD( PERV_1_BIST_UNIT3                                       , 7   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT3      );
+REG64_FLD( PERV_1_BIST_UNIT4                                       , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT4      );
+REG64_FLD( PERV_1_BIST_UNIT5                                       , 9   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT5      );
+REG64_FLD( PERV_1_BIST_UNIT6                                       , 10  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT6      );
+REG64_FLD( PERV_1_BIST_UNIT7                                       , 11  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT7      );
+REG64_FLD( PERV_1_BIST_UNIT8                                       , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT8      );
+REG64_FLD( PERV_1_BIST_UNIT9                                       , 13  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT9      );
+REG64_FLD( PERV_1_BIST_UNIT10                                      , 14  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT10     );
+
+REG64_FLD( PERV_BIT_SEL_REG_2_SELECT_REGISTER_FSP2PIB              , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SELECT_REGISTER_FSP2PIB );
+REG64_FLD( PERV_BIT_SEL_REG_2_SELECT_REGISTER_FSP2PIB_LEN          , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SELECT_REGISTER_FSP2PIB_LEN );
+
+REG64_FLD( PERV_CBS_CS_START_BOOT_SEQUENCER                        , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_START_BOOT_SEQUENCER );
+REG64_FLD( PERV_CBS_CS_OPTION_PIB_RESET                            , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_OPTION_PIB_RESET );
+REG64_FLD( PERV_CBS_CS_PREVENT_SBE_START                           , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_PREVENT_SBE_START );
+REG64_FLD( PERV_CBS_CS_SECURE_ACCESS_BIT                           , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SECURE_ACCESS_BIT );
+REG64_FLD( PERV_CBS_CS_SAMPLED_SMD_PIN                             , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SAMPLED_SMD_PIN );
+REG64_FLD( PERV_CBS_CS_STATE_MACHINE_TRANSITION_DELAY              , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_STATE_MACHINE_TRANSITION_DELAY );
+REG64_FLD( PERV_CBS_CS_STATE_MACHINE_TRANSITION_DELAY_LEN          , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_STATE_MACHINE_TRANSITION_DELAY_LEN );
+
+REG64_FLD( PERV_1_CC_ATOMIC_LOCK_REG_ENABLE                        , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PERV_1_CC_ATOMIC_LOCK_REG_ID                            , 1   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ID         );
+REG64_FLD( PERV_1_CC_ATOMIC_LOCK_REG_ID_LEN                        , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ID_LEN     );
+REG64_FLD( PERV_1_CC_ATOMIC_LOCK_REG_ACTIVITY                      , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ACTIVITY   );
+REG64_FLD( PERV_1_CC_ATOMIC_LOCK_REG_ACTIVITY_LEN                  , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ACTIVITY_LEN );
+
+REG64_FLD( PERV_1_CC_PROTECT_MODE_REG_READ_ENABLE                  , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_READ_ENABLE );
+REG64_FLD( PERV_1_CC_PROTECT_MODE_REG_WRITE_ENABLE                 , 1   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_WRITE_ENABLE );
+
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_CMD                             , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CLOCK_CMD  );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_CMD_LEN                         , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CLOCK_CMD_LEN );
+REG64_FLD( PERV_1_CLK_REGION_SLAVE_MODE                            , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SLAVE_MODE );
+REG64_FLD( PERV_1_CLK_REGION_MASTER_MODE                           , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_MASTER_MODE );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_PERV                            , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CLOCK_PERV );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_UNIT1                           , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CLOCK_UNIT1 );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_UNIT2                           , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CLOCK_UNIT2 );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_UNIT3                           , 7   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CLOCK_UNIT3 );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_UNIT4                           , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CLOCK_UNIT4 );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_UNIT5                           , 9   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CLOCK_UNIT5 );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_UNIT6                           , 10  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CLOCK_UNIT6 );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_UNIT7                           , 11  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CLOCK_UNIT7 );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_UNIT8                           , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CLOCK_UNIT8 );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_UNIT9                           , 13  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CLOCK_UNIT9 );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_UNIT10                          , 14  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CLOCK_UNIT10 );
+REG64_FLD( PERV_1_CLK_REGION_SEL_THOLD_SL                          , 48  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEL_THOLD_SL );
+REG64_FLD( PERV_1_CLK_REGION_SEL_THOLD_NSL                         , 49  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEL_THOLD_NSL );
+REG64_FLD( PERV_1_CLK_REGION_SEL_THOLD_ARY                         , 50  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEL_THOLD_ARY );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_PULSE_USE_EVEN                  , 52  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CLOCK_PULSE_USE_EVEN );
+
+REG64_FLD( PERV_1_CLOCK_STAT_ARY_STATUS_PERV                       , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_PERV );
+REG64_FLD( PERV_1_CLOCK_STAT_ARY_STATUS_UNIT1                      , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT1 );
+REG64_FLD( PERV_1_CLOCK_STAT_ARY_STATUS_UNIT2                      , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT2 );
+REG64_FLD( PERV_1_CLOCK_STAT_ARY_STATUS_UNIT3                      , 7   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT3 );
+REG64_FLD( PERV_1_CLOCK_STAT_ARY_STATUS_UNIT4                      , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT4 );
+REG64_FLD( PERV_1_CLOCK_STAT_ARY_STATUS_UNIT5                      , 9   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT5 );
+REG64_FLD( PERV_1_CLOCK_STAT_ARY_STATUS_UNIT6                      , 10  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT6 );
+REG64_FLD( PERV_1_CLOCK_STAT_ARY_STATUS_UNIT7                      , 11  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT7 );
+REG64_FLD( PERV_1_CLOCK_STAT_ARY_STATUS_UNIT8                      , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT8 );
+REG64_FLD( PERV_1_CLOCK_STAT_ARY_STATUS_UNIT9                      , 13  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT9 );
+REG64_FLD( PERV_1_CLOCK_STAT_ARY_STATUS_UNIT10                     , 14  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT10 );
+
+REG64_FLD( PERV_1_CLOCK_STAT_NSL_STATUS_PERV                       , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_PERV );
+REG64_FLD( PERV_1_CLOCK_STAT_NSL_STATUS_UNIT1                      , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT1 );
+REG64_FLD( PERV_1_CLOCK_STAT_NSL_STATUS_UNIT2                      , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT2 );
+REG64_FLD( PERV_1_CLOCK_STAT_NSL_STATUS_UNIT3                      , 7   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT3 );
+REG64_FLD( PERV_1_CLOCK_STAT_NSL_STATUS_UNIT4                      , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT4 );
+REG64_FLD( PERV_1_CLOCK_STAT_NSL_STATUS_UNIT5                      , 9   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT5 );
+REG64_FLD( PERV_1_CLOCK_STAT_NSL_STATUS_UNIT6                      , 10  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT6 );
+REG64_FLD( PERV_1_CLOCK_STAT_NSL_STATUS_UNIT7                      , 11  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT7 );
+REG64_FLD( PERV_1_CLOCK_STAT_NSL_STATUS_UNIT8                      , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT8 );
+REG64_FLD( PERV_1_CLOCK_STAT_NSL_STATUS_UNIT9                      , 13  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT9 );
+REG64_FLD( PERV_1_CLOCK_STAT_NSL_STATUS_UNIT10                     , 14  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT10 );
+
+REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_PERV                        , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_PERV );
+REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_UNIT1                       , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT1 );
+REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_UNIT2                       , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT2 );
+REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_UNIT3                       , 7   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT3 );
+REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_UNIT4                       , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT4 );
+REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_UNIT5                       , 9   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT5 );
+REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_UNIT6                       , 10  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT6 );
+REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_UNIT7                       , 11  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT7 );
+REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_UNIT8                       , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT8 );
+REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_UNIT9                       , 13  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT9 );
+REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_UNIT10                      , 14  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATUS_UNIT10 );
+
+REG64_FLD( PERV_CMD_WRDAT_WRITE_NOT_READ                           , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_WRITE_NOT_READ );
+
+REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_CMD_REG                    , 0   ,
+           SH_UNT_PERV_FSII2C, SH_ACS_SCOM     , SH_FLD_CMD_REG    );
+REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_CMD_REG_LEN                , 32  ,
+           SH_UNT_PERV_FSII2C, SH_ACS_SCOM     , SH_FLD_CMD_REG_LEN );
+
+REG32_FLD( PERV_FSI2PIB_COMMAND_REGISTER_CMD_REG                   , 0   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_CMD_REG    );
+REG32_FLD( PERV_FSI2PIB_COMMAND_REGISTER_CMD_REG_LEN               , 32  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_CMD_REG_LEN );
+
+REG32_FLD( PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_WRITE_FLAG        , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_CMDREG_WRITE_FLAG );
+REG32_FLD( PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_BROADCAST_FLAG    , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_CMDREG_BROADCAST_FLAG );
+REG32_FLD( PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_SCAN_ADDRESS      , 2   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_CMDREG_SCAN_ADDRESS );
+REG32_FLD( PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_SCAN_ADDRESS_LEN  , 14  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_CMDREG_SCAN_ADDRESS_LEN );
+REG32_FLD( PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_SCAN_REGION       , 16  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_CMDREG_SCAN_REGION );
+REG32_FLD( PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_SCAN_REGION_LEN   , 12  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_CMDREG_SCAN_REGION_LEN );
+REG32_FLD( PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_SCAN_TYPE         , 28  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_CMDREG_SCAN_TYPE );
+REG32_FLD( PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_SCAN_TYPE_LEN     , 4   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_CMDREG_SCAN_TYPE_LEN );
+
+REG32_FLD( PERV_FSI2PIB_COMPLEMENT_MASK_REG                        , 0   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_REG        );
+REG32_FLD( PERV_FSI2PIB_COMPLEMENT_MASK_REG_LEN                    , 32  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_REG_LEN    );
+
+REG32_FLD( PERV_FSISHIFT_COMPLEMENT_MASK_REG                       , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REG        );
+REG32_FLD( PERV_FSISHIFT_COMPLEMENT_MASK_REG_LEN                   , 32  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REG_LEN    );
+
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC               , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE0_SEL_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC_LEN           , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE0_SEL_DC_LEN );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_6C                           , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_6C );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_7C                           , 7   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_7C );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC               , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE1_SEL_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC_LEN           , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE1_SEL_DC_LEN );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_14C                          , 14  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_14C );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_15C                          , 15  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_15C );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC               , 16  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE2_SEL_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC_LEN           , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE2_SEL_DC_LEN );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_22C                          , 22  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_22C );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_23C                          , 23  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_23C );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC               , 24  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE3_SEL_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC_LEN           , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE3_SEL_DC_LEN );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_30C                          , 30  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_30C );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_31C                          , 31  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_31C );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_CC_OFLOW_FEH_SEL_DC              , 32  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_OFLOW_FEH_SEL_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_CC_SCAN_PROTECT_DC               , 33  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_SCAN_PROTECT_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_CC_SDIS_DC_N                     , 34  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_SDIS_DC_N );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_TEST_CONTROL_35C             , 35  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_35C );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_TEST_CONTROL_36C             , 36  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_36C );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_TEST_CONTROL_37C             , 37  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_37C );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_TEST_CONTROL_38C             , 38  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_38C );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_TEST_CONTROL_39C             , 39  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_39C );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_EPS_MASK_VITL_PCB_ERR_DC         , 40  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_EPS_MASK_VITL_PCB_ERR_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC    , 41  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_TP_PIB_TRACE_MODE_DATA_DC             , 42  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TP_PIB_TRACE_MODE_DATA_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_43C                          , 43  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_43C );
+REG64_FLD( PERV_1_CPLT_CONF0_FREE_USAGE_44C                        , 44  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_44C );
+REG64_FLD( PERV_1_CPLT_CONF0_FREE_USAGE_45C                        , 45  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_45C );
+REG64_FLD( PERV_1_CPLT_CONF0_FREE_USAGE_46C                        , 46  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_46C );
+REG64_FLD( PERV_1_CPLT_CONF0_FREE_USAGE_47C                        , 47  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_47C );
+REG64_FLD( PERV_1_CPLT_CONF0_TC_UNIT_GROUP_ID_DC                   , 48  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_GROUP_ID_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_TC_UNIT_GROUP_ID_DC_LEN               , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_GROUP_ID_DC_LEN );
+REG64_FLD( PERV_1_CPLT_CONF0_TC_UNIT_CHIP_ID_DC                    , 52  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_CHIP_ID_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_TC_UNIT_CHIP_ID_DC_LEN                , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_CHIP_ID_DC_LEN );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_ID_55C                       , 55  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_55C );
+REG64_FLD( PERV_1_CPLT_CONF0_TC_UNIT_SYS_ID_DC                     , 56  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_SYS_ID_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_TC_UNIT_SYS_ID_DC_LEN                 , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_SYS_ID_DC_LEN );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_ID_61C                       , 61  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_61C );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_ID_62C                       , 62  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_62C );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_ID_63C                       , 63  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_63C );
+
+REG64_FLD( PERV_1_CPLT_CONF1_TC_AMUX_CTRL_DC                       , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_AMUX_CTRL_DC );
+REG64_FLD( PERV_1_CPLT_CONF1_TC_AMUX_CTRL_DC_LEN                   , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_AMUX_CTRL_DC_LEN );
+REG64_FLD( PERV_1_CPLT_CONF1_IOVALID_4D                            , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_4D );
+REG64_FLD( PERV_1_CPLT_CONF1_IOVALID_5D                            , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_5D );
+REG64_FLD( PERV_1_CPLT_CONF1_IOVALID_6D                            , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_6D );
+REG64_FLD( PERV_1_CPLT_CONF1_IOVALID_7D                            , 7   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_7D );
+REG64_FLD( PERV_1_CPLT_CONF1_IOVALID_8D                            , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_8D );
+REG64_FLD( PERV_1_CPLT_CONF1_IOVALID_9D                            , 9   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_9D );
+REG64_FLD( PERV_1_CPLT_CONF1_IOVALID_10D                           , 10  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_10D );
+REG64_FLD( PERV_1_CPLT_CONF1_IOVALID_11D                           , 11  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_11D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_12D                        , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_12D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_13D                        , 13  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_13D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_14D                        , 14  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_14D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_15D                        , 15  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_15D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_16D                        , 16  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_16D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_17D                        , 17  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_17D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_18D                        , 18  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_18D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_19D                        , 19  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_19D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_20D                        , 20  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_20D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_21D                        , 21  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_21D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_22D                        , 22  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_22D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_23D                        , 23  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_23D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_24D                        , 24  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_24D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_25D                        , 25  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_25D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_26D                        , 26  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_26D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_27D                        , 27  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_27D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_28D                        , 28  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_28D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_29D                        , 29  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_29D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_30D                        , 30  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_30D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_31D                        , 31  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_31D );
+
+REG64_FLD( PERV_1_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC             , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_ABSTCLK_MUXSEL_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_UNIT_SYNCCLK_MUXSEL_DC             , 1   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_SYNCCLK_MUXSEL_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC              , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_FLUSHMODE_INH_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC                , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_FORCE_ALIGN_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_UNIT_ARY_WRT_THRU_DC               , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_ARY_WRT_THRU_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_UNIT_AVP_MODE                      , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_AVP_MODE );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_6A                         , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_6A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_7A                         , 7   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_7A );
+REG64_FLD( PERV_1_CPLT_CTRL0_CTRL_CC_ABIST_RECOV_DISABLE_DC        , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_ABIST_RECOV_DISABLE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_9A                         , 9   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_9A );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC      , 10  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_RESERVED_11A                          , 11  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_11A );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_SKIT_MODE_BIST_DC                  , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_SKIT_MODE_BIST_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC  , 13  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_UNIT_CONSTRAIN_SAFESCAN_DC         , 14  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_CONSTRAIN_SAFESCAN_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_UNIT_RRFA_TEST_ENABLE_DC           , 15  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_RRFA_TEST_ENABLE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_NBTI_HDR_ENABLE_OVR_DC             , 16  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_NBTI_HDR_ENABLE_OVR_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_NBTI_ACDC_STRESS_SELECT_DC         , 17  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_NBTI_ACDC_STRESS_SELECT_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_RESERVED_18A                          , 18  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_18A );
+REG64_FLD( PERV_1_CPLT_CTRL0_RESERVED_19A                          , 19  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_19A );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_PSRO_SEL_DC                        , 20  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PSRO_SEL_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_PSRO_SEL_DC_LEN                    , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PSRO_SEL_DC_LEN );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_BSC_WRAPSEL_DC                     , 28  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_BSC_WRAPSEL_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_BSC_INTMODE_DC                     , 29  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_BSC_INTMODE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_BSC_INV_DC                         , 30  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_BSC_INV_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_BSC_EXTMODE_DC                     , 31  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_BSC_EXTMODE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_REFCLK_DRVR_EN_DC                  , 32  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REFCLK_DRVR_EN_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_RESERVED_33A                          , 33  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_33A );
+REG64_FLD( PERV_1_CPLT_CTRL0_RESERVED_34A                          , 34  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_34A );
+REG64_FLD( PERV_1_CPLT_CTRL0_RESERVED_35A                          , 35  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_35A );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_OELCC_EDGE_DELAYED_DC              , 36  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_OELCC_EDGE_DELAYED_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_OELCC_ALIGN_FLUSH_DC               , 37  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_OELCC_ALIGN_FLUSH_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_RESERVED_38A                          , 38  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_38A );
+REG64_FLD( PERV_1_CPLT_CTRL0_RESERVED_39A                          , 39  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_39A );
+REG64_FLD( PERV_1_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC               , 40  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_CLKDIV_SEL_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC_LEN           , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_CLKDIV_SEL_DC_LEN );
+REG64_FLD( PERV_1_CPLT_CTRL0_RESERVED_42A                          , 42  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_42A );
+REG64_FLD( PERV_1_CPLT_CTRL0_RESERVED_43A                          , 43  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_43A );
+REG64_FLD( PERV_1_CPLT_CTRL0_CTRL_CC_DCTEST_DC                     , 44  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_DCTEST_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_CTRL_CC_OTP_PRGMODE_DC                , 45  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_OTP_PRGMODE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_CTRL_CC_SSS_CALIBRATE_DC              , 46  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_SSS_CALIBRATE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_CTRL_CC_PIN_LBIST_DC                  , 47  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_PIN_LBIST_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_48A                        , 48  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_48A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_49A                        , 49  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_49A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_50A                        , 50  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_50A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_51A                        , 51  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_51A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_52A                        , 52  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_52A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_53A                        , 53  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_53A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_54A                        , 54  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_54A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_55A                        , 55  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_55A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_56A                        , 56  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_56A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_57A                        , 57  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_57A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_58A                        , 58  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_58A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_59A                        , 59  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_59A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_60A                        , 60  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_60A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_61A                        , 61  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_61A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_62A                        , 62  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_62A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_63A                        , 63  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_63A );
+
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_FENCE0                             , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_FENCE0  );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_FENCE1                             , 1   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_FENCE1  );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_FENCE2                             , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_FENCE2  );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_VITL_FENCE_DC                      , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_VITL_FENCE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_PERV_FENCE_DC                      , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PERV_FENCE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_REGION1_FENCE_DC                   , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION1_FENCE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_REGION2_FENCE_DC                   , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION2_FENCE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_REGION3_FENCE_DC                   , 7   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION3_FENCE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_REGION4_FENCE_DC                   , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION4_FENCE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_REGION5_FENCE_DC                   , 9   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION5_FENCE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_REGION6_FENCE_DC                   , 10  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION6_FENCE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_REGION7_FENCE_DC                   , 11  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION7_FENCE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_REGION8_FENCE_DC                   , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION8_FENCE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_REGION9_FENCE_DC                   , 13  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION9_FENCE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_REGION10_FENCE_DC                  , 14  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION10_FENCE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL1_RESERVED                              , 15  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED   );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_UNIT_MULTICYCLE_TEST_FENCE_DC      , 16  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_MULTICYCLE_TEST_FENCE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL1_TCPERV_OCC_PIB_FENCE_DC               , 17  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TCPERV_OCC_PIB_FENCE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_FUNCTIONAL_FENCE_1                 , 18  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_FUNCTIONAL_FENCE_1 );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_FUNCTIONAL_FENCE_2                 , 19  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_FUNCTIONAL_FENCE_2 );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_FUNCTIONAL_FENCE_3                 , 20  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_FUNCTIONAL_FENCE_3 );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_FUNCTIONAL_FENCE_4                 , 21  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_FUNCTIONAL_FENCE_4 );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_FUNCTIONAL_FENCE_5                 , 22  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_FUNCTIONAL_FENCE_5 );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_FUNCTIONAL_FENCE_6                 , 23  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_FUNCTIONAL_FENCE_6 );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_FUNCTIONAL_FENCE_7                 , 24  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_FUNCTIONAL_FENCE_7 );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_FUNCTIONAL_FENCE_8                 , 25  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_FUNCTIONAL_FENCE_8 );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_FUNCTIONAL_FENCE_9                 , 26  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_FUNCTIONAL_FENCE_9 );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_FUNCTIONAL_FENCE_10                , 27  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_FUNCTIONAL_FENCE_10 );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_FUNCTIONAL_FENCE_11                , 28  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_FUNCTIONAL_FENCE_11 );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_FUNCTIONAL_FENCE_12                , 29  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_FUNCTIONAL_FENCE_12 );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_FUNCTIONAL_FENCE_13                , 30  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_FUNCTIONAL_FENCE_13 );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_FUNCTIONAL_FENCE_14                , 31  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_FUNCTIONAL_FENCE_14 );
+
+REG64_FLD( PERV_1_CPLT_MASK0_CPLTMASK0                             , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CPLTMASK0  );
+REG64_FLD( PERV_1_CPLT_MASK0_CPLTMASK0_LEN                         , 24  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CPLTMASK0_LEN );
+
+REG64_FLD( PERV_1_CPLT_STAT0_SRAM_ABIST_DONE_DC                    , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SRAM_ABIST_DONE_DC );
+REG64_FLD( PERV_1_CPLT_STAT0_DRAM_ABIST_DONE_DC                    , 1   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_DRAM_ABIST_DONE_DC );
+REG64_FLD( PERV_1_CPLT_STAT0_RESERVED_2E                           , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_RESERVED_2E );
+REG64_FLD( PERV_1_CPLT_STAT0_RESERVED_3E                           , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_RESERVED_3E );
+REG64_FLD( PERV_1_CPLT_STAT0_TC_DIAG_PORT0_OUT                     , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_TC_DIAG_PORT0_OUT );
+REG64_FLD( PERV_1_CPLT_STAT0_TC_DIAG_PORT1_OUT                     , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_TC_DIAG_PORT1_OUT );
+REG64_FLD( PERV_1_CPLT_STAT0_RESERVED_6E                           , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_RESERVED_6E );
+REG64_FLD( PERV_1_CPLT_STAT0_PLL_DESTOUT                           , 7   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PLL_DESTOUT );
+REG64_FLD( PERV_1_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC                  , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CC_CTRL_OPCG_DONE_DC );
+REG64_FLD( PERV_1_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC         , 9   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CC_CTRL_CHIPLET_IS_ALIGNED_DC );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_10E                        , 10  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_FREE_USAGE_10E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_11E                        , 11  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_FREE_USAGE_11E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_12E                        , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_FREE_USAGE_12E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_13E                        , 13  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_FREE_USAGE_13E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_14E                        , 14  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_FREE_USAGE_14E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_15E                        , 15  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_FREE_USAGE_15E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_16E                        , 16  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_FREE_USAGE_16E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_17E                        , 17  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_FREE_USAGE_17E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_18E                        , 18  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_FREE_USAGE_18E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_19E                        , 19  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_FREE_USAGE_19E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_20E                        , 20  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_FREE_USAGE_20E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_21E                        , 21  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_FREE_USAGE_21E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_22E                        , 22  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_FREE_USAGE_22E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_23E                        , 23  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_FREE_USAGE_23E );
+
+REG64_FLD( PERV_1_CTRL_ATOMIC_LOCK_REG_ENABLE                      , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ENABLE     );
+REG64_FLD( PERV_1_CTRL_ATOMIC_LOCK_REG_ID                          , 1   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ID         );
+REG64_FLD( PERV_1_CTRL_ATOMIC_LOCK_REG_ID_LEN                      , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ID_LEN     );
+REG64_FLD( PERV_1_CTRL_ATOMIC_LOCK_REG_ACTIVITY                    , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ACTIVITY   );
+REG64_FLD( PERV_1_CTRL_ATOMIC_LOCK_REG_ACTIVITY_LEN                , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ACTIVITY_LEN );
+
+REG64_FLD( PERV_1_CTRL_PROTECT_MODE_REG_READ_ENABLE                , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_READ_ENABLE );
+REG64_FLD( PERV_1_CTRL_PROTECT_MODE_REG_WRITE_ENABLE               , 1   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_WRITE_ENABLE );
+
+REG32_FLD( PERV_FSI2PIB_DATA_REGISTER_0_REG                        , 0   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI      , SH_FLD_REG        );
+REG32_FLD( PERV_FSI2PIB_DATA_REGISTER_0_REG_LEN                    , 32  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI      , SH_FLD_REG_LEN    );
+
+REG32_FLD( PERV_FSI2PIB_DATA_REGISTER_1_REG                        , 0   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_REG        );
+REG32_FLD( PERV_FSI2PIB_DATA_REGISTER_1_REG_LEN                    , 32  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_REG_LEN    );
+
+REG64_FLD( PERV_1_DBG_CBS_CC_RESET_EP                              , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_RESET_EP   );
+REG64_FLD( PERV_1_DBG_CBS_CC_OPCG_IP                               , 1   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_OPCG_IP    );
+REG64_FLD( PERV_1_DBG_CBS_CC_VITL_CLKOFF                           , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_VITL_CLKOFF );
+REG64_FLD( PERV_1_DBG_CBS_CC_TEST_ENABLE                           , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_TEST_ENABLE );
+REG64_FLD( PERV_1_DBG_CBS_CC_REQ                                   , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_REQ        );
+REG64_FLD( PERV_1_DBG_CBS_CC_CMD                                   , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CMD        );
+REG64_FLD( PERV_1_DBG_CBS_CC_CMD_LEN                               , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CMD_LEN    );
+REG64_FLD( PERV_1_DBG_CBS_CC_STATE                                 , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATE      );
+REG64_FLD( PERV_1_DBG_CBS_CC_STATE_LEN                             , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STATE_LEN  );
+REG64_FLD( PERV_1_DBG_CBS_CC_SECURITY_DEBUG_MODE                   , 13  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SECURITY_DEBUG_MODE );
+REG64_FLD( PERV_1_DBG_CBS_CC_PROTOCOL_ERROR                        , 14  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PROTOCOL_ERROR );
+REG64_FLD( PERV_1_DBG_CBS_CC_PCB_IDLE                              , 15  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PCB_IDLE   );
+REG64_FLD( PERV_1_DBG_CBS_CC_CURRENT_OPCG_MODE                     , 16  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CURRENT_OPCG_MODE );
+REG64_FLD( PERV_1_DBG_CBS_CC_CURRENT_OPCG_MODE_LEN                 , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CURRENT_OPCG_MODE_LEN );
+REG64_FLD( PERV_1_DBG_CBS_CC_LAST_OPCG_MODE                        , 20  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_LAST_OPCG_MODE );
+REG64_FLD( PERV_1_DBG_CBS_CC_LAST_OPCG_MODE_LEN                    , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_LAST_OPCG_MODE_LEN );
+REG64_FLD( PERV_1_DBG_CBS_CC_PCB_ERROR                             , 24  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PCB_ERROR  );
+REG64_FLD( PERV_1_DBG_CBS_CC_PARITY_ERROR                          , 25  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PARITY_ERROR );
+REG64_FLD( PERV_1_DBG_CBS_CC_ERROR                                 , 26  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ERROR      );
+REG64_FLD( PERV_1_DBG_CBS_CC_CHIPLET_IS_ALIGNED                    , 27  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CHIPLET_IS_ALIGNED );
+REG64_FLD( PERV_1_DBG_CBS_CC_PCB_REQUEST_SINCE_RESET               , 28  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PCB_REQUEST_SINCE_RESET );
+REG64_FLD( PERV_1_DBG_CBS_CC_PARANOIA_TEST_ENABLE_CHANGE           , 29  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PARANOIA_TEST_ENABLE_CHANGE );
+REG64_FLD( PERV_1_DBG_CBS_CC_PARANOIA_VITL_CLKOFF_CHANGE           , 30  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PARANOIA_VITL_CLKOFF_CHANGE );
+REG64_FLD( PERV_1_DBG_CBS_CC_TP_TPFSI_ACK                          , 31  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_TP_TPFSI_ACK );
+
+REG32_FLD( PERV_FSISHIFT_DMA_ERROR_PTR_REGISTER_REG                , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REG        );
+REG32_FLD( PERV_FSISHIFT_DMA_ERROR_PTR_REGISTER_REG_LEN            , 32  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REG_LEN    );
+
+REG32_FLD( PERV_FSISHIFT_DMA_MODE_REGISTER_REG_ENABLE              , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REG_ENABLE );
+REG32_FLD( PERV_FSISHIFT_DMA_MODE_REGISTER_REG_FIFO_SIZE_EQ_1      , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REG_FIFO_SIZE_EQ_1 );
+REG32_FLD( PERV_FSISHIFT_DMA_MODE_REGISTER_REG_UNUSED              , 2   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REG_UNUSED );
+REG32_FLD( PERV_FSISHIFT_DMA_MODE_REGISTER_REG_UNUSED_LEN          , 30  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REG_UNUSED_LEN );
+
+REG32_FLD( PERV_FSISHIFT_DMA_OP_BLOCKSIZE_REGISTER_OPCODE          , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_OPCODE     );
+REG32_FLD( PERV_FSISHIFT_DMA_OP_BLOCKSIZE_REGISTER_OPCODE_LEN      , 8   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_OPCODE_LEN );
+REG32_FLD( PERV_FSISHIFT_DMA_OP_BLOCKSIZE_REGISTER_SIZE            , 8   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_SIZE       );
+REG32_FLD( PERV_FSISHIFT_DMA_OP_BLOCKSIZE_REGISTER_SIZE_LEN        , 24  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_SIZE_LEN   );
+
+REG32_FLD( PERV_FSISHIFT_DMA_PIB_RCV_BUFFER0_REGISTER_BUF0_REG_DATA0 , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_BUF0_REG_DATA0 );
+REG32_FLD( PERV_FSISHIFT_DMA_PIB_RCV_BUFFER0_REGISTER_BUF0_REG_DATA0_LEN , 32  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_BUF0_REG_DATA0_LEN );
+
+REG32_FLD( PERV_FSISHIFT_DMA_PIB_RCV_BUFFER1_REGISTER_BUF1_REG_DATA1 , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_BUF1_REG_DATA1 );
+REG32_FLD( PERV_FSISHIFT_DMA_PIB_RCV_BUFFER1_REGISTER_BUF1_REG_DATA1_LEN , 32  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_BUF1_REG_DATA1_LEN );
+
+REG32_FLD( PERV_FSISHIFT_DMA_PIB_SND_BUFFER0_REGISTER_BUF0_REG_DATA0 , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_BUF0_REG_DATA0 );
+REG32_FLD( PERV_FSISHIFT_DMA_PIB_SND_BUFFER0_REGISTER_BUF0_REG_DATA0_LEN , 32  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_BUF0_REG_DATA0_LEN );
+
+REG32_FLD( PERV_FSISHIFT_DMA_PIB_SND_BUFFER1_REGISTER_BUF1_REG_DATA0 , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_BUF1_REG_DATA0 );
+REG32_FLD( PERV_FSISHIFT_DMA_PIB_SND_BUFFER1_REGISTER_BUF1_REG_DATA0_LEN , 32  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_BUF1_REG_DATA0_LEN );
+
+REG32_FLD( PERV_FSISHIFT_DMA_REM_SIZE_REGISTER_REMAINING_WORDS     , 8   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REMAINING_WORDS );
+REG32_FLD( PERV_FSISHIFT_DMA_REM_SIZE_REGISTER_REMAINING_WORDS_LEN , 24  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REMAINING_WORDS_LEN );
+
+REG32_FLD( PERV_FSISHIFT_DMA_SCOM_CMD_REGISTER_REG                 , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REG        );
+REG32_FLD( PERV_FSISHIFT_DMA_SCOM_CMD_REGISTER_REG_LEN             , 32  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REG_LEN    );
+
+REG32_FLD( PERV_FSISHIFT_DMA_STAT_COMP_MASK_REGISTER_REG           , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REG        );
+REG32_FLD( PERV_FSISHIFT_DMA_STAT_COMP_MASK_REGISTER_REG_LEN       , 32  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REG_LEN    );
+
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_PERMISSION_TO_SEND_1 , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC1_PERMISSION_TO_SEND_1 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_ABORT_1            , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC1_ABORT_1 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_LBUS_SLAVE_1B_PENDING , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC1_LBUS_SLAVE_1B_PENDING );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_PIB_SLAVE_PENDING  , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC1_PIB_SLAVE_PENDING );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_UNUSED_27          , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC1_UNUSED_27 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_XDN_1              , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC1_XDN_1 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_XUP_1              , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC1_XUP_1 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_UNUSED_24          , 7   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC1_UNUSED_24 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_HEADER_COUNT       , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC1_HEADER_COUNT );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_HEADER_COUNT_LEN   , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC1_HEADER_COUNT_LEN );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_DATA_COUNT         , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC1_DATA_COUNT );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_DATA_COUNT_LEN     , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC1_DATA_COUNT_LEN );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_HEADER_COUNT_1B    , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC1_HEADER_COUNT_1B );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_HEADER_COUNT_1B_LEN , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC1_HEADER_COUNT_1B_LEN );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_DATA_COUNT_1B      , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC1_DATA_COUNT_1B );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_DATA_COUNT_1B_LEN  , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC1_DATA_COUNT_1B_LEN );
+
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_PERMISSION_TO_SEND_2 , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC2_PERMISSION_TO_SEND_2 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_ABORT_2            , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC2_ABORT_2 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_LBUS_SLAVE_2B_PENDING , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC2_LBUS_SLAVE_2B_PENDING );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_PIB_SLAVE_PENDING  , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC2_PIB_SLAVE_PENDING );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_UNUSED_27          , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC2_UNUSED_27 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_XDN_2              , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC2_XDN_2 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_XUP_2              , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC2_XUP_2 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_UNUSED_24          , 7   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC2_UNUSED_24 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_HEADER_COUNT       , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC2_HEADER_COUNT );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_HEADER_COUNT_LEN   , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC2_HEADER_COUNT_LEN );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_DATA_COUNT         , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC2_DATA_COUNT );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_DATA_COUNT_LEN     , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC2_DATA_COUNT_LEN );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_HEADER_COUNT_2B    , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC2_HEADER_COUNT_2B );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_HEADER_COUNT_2B_LEN , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC2_HEADER_COUNT_2B_LEN );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_DATA_COUNT_2B      , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC2_DATA_COUNT_2B );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_DATA_COUNT_2B_LEN  , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DSC2_DATA_COUNT_2B_LEN );
+
+REG64_FLD( PERV_1_DTS_RESULT0_0_RESULT                             , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_0_RESULT   );
+REG64_FLD( PERV_1_DTS_RESULT0_0_RESULT_LEN                         , 16  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_0_RESULT_LEN );
+REG64_FLD( PERV_1_DTS_RESULT0_1_RESULT                             , 16  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_1_RESULT   );
+REG64_FLD( PERV_1_DTS_RESULT0_1_RESULT_LEN                         , 16  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_1_RESULT_LEN );
+
+REG64_FLD( PERV_1_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE           , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_TIMESTAMP_COUNTER_VALUE );
+REG64_FLD( PERV_1_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE_LEN       , 44  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_TIMESTAMP_COUNTER_VALUE_LEN );
+REG64_FLD( PERV_1_DTS_TRC_RESULT_TIMESTAMP_COUNTER_OVERFLOW_ERR    , 44  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_TIMESTAMP_COUNTER_OVERFLOW_ERR );
+REG64_FLD( PERV_1_DTS_TRC_RESULT_1                                 , 48  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_1          );
+REG64_FLD( PERV_1_DTS_TRC_RESULT_1_LEN                             , 16  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_1_LEN      );
+
+REG64_FLD( PERV_ERROR_REG_TIMEOUT_ACTIVE                           , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TIMEOUT_ACTIVE );
+REG64_FLD( PERV_ERROR_REG_PARITY_ERR                               , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_PARITY_ERR );
+REG64_FLD( PERV_ERROR_REG_BEAT_NUM_ERR                             , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_BEAT_NUM_ERR );
+REG64_FLD( PERV_ERROR_REG_BEAT_REC_ERR                             , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_BEAT_REC_ERR );
+REG64_FLD( PERV_ERROR_REG_RECEIVED                                 , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_RECEIVED   );
+REG64_FLD( PERV_ERROR_REG_RX_PCB_DATA_P_ERR                        , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_RX_PCB_DATA_P_ERR );
+REG64_FLD( PERV_ERROR_REG_PIB_ADDR_P_ERR                           , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_PIB_ADDR_P_ERR );
+REG64_FLD( PERV_ERROR_REG_PIB_DATA_P_ERR                           , 7   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_PIB_DATA_P_ERR );
+
+REG64_FLD( PERV_1_ERROR_STATUS_ERRORS                              , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ERRORS     );
+REG64_FLD( PERV_1_ERROR_STATUS_ERRORS_LEN                          , 32  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ERRORS_LEN );
+
+REG64_FLD( PERV_1_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK , 16  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK         , 17  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_THERM_MODEREG_PARITY_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_MASK       , 18  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_SKITTER_MODEREG_PARITY_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_MASK      , 19  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_SKITTER_FORCEREG_PARITY_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_SCAN_INIT_VERSION_PARITY_MASK     , 20  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_SCAN_INIT_VERSION_PARITY_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_VOLT_MODEREG_PARITY_MASK          , 21  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_VOLT_MODEREG_PARITY_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_COUNT_STATE_MASK                  , 23  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_COUNT_STATE_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_RUN_STATE_MASK                    , 24  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_RUN_STATE_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_THRES_STATE_MASK                  , 25  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_THRES_STATE_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_OVERFLOW_MASK                     , 26  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_OVERFLOW_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_SHIFTER_PARITY_MASK               , 27  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_SHIFTER_PARITY_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_SHIFTER_VALID_MASK                , 28  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_SHIFTER_VALID_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_TIMEOUT_MASK                      , 29  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_TIMEOUT_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_F_SKITTER_READ_MASK               , 30  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_F_SKITTER_READ_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_PCB_MASK                          , 31  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_PCB_MASK   );
+
+REG64_FLD( PERV_FI2C_CFG_PIBI2CM_PIB_SLAVE_ID                      , 0   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_PIBI2CM_PIB_SLAVE_ID );
+REG64_FLD( PERV_FI2C_CFG_PIBI2CM_PIB_SLAVE_ID_LEN                  , 16  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_PIBI2CM_PIB_SLAVE_ID_LEN );
+REG64_FLD( PERV_FI2C_CFG_ECC_ENABLE                                , 16  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_ECC_ENABLE );
+REG64_FLD( PERV_FI2C_CFG_DISABLE_ECC_CHK                           , 17  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_DISABLE_ECC_CHK );
+REG64_FLD( PERV_FI2C_CFG_I2C_SPEED_MUX                             , 18  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_I2C_SPEED_MUX );
+REG64_FLD( PERV_FI2C_CFG_I2C_SPEED_MUX_LEN                         , 2   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_I2C_SPEED_MUX_LEN );
+REG64_FLD( PERV_FI2C_CFG_BIT_RATE_DIVISOR_VALUE                    , 20  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_BIT_RATE_DIVISOR_VALUE );
+REG64_FLD( PERV_FI2C_CFG_BIT_RATE_DIVISOR_VALUE_LEN                , 16  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_BIT_RATE_DIVISOR_VALUE_LEN );
+REG64_FLD( PERV_FI2C_CFG_I2C_BUS_HELD_MODE_ENABLE                  , 36  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_I2C_BUS_HELD_MODE_ENABLE );
+REG64_FLD( PERV_FI2C_CFG_PIPELINE_ENABLE                           , 37  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_PIPELINE_ENABLE );
+REG64_FLD( PERV_FI2C_CFG_BACKUP_SEEPROM_SELECT                     , 38  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_BACKUP_SEEPROM_SELECT );
+REG64_FLD( PERV_FI2C_CFG_FORCE_RESET                               , 39  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_FORCE_RESET );
+REG64_FLD( PERV_FI2C_CFG_RESET_PIB                                 , 40  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESET_PIB  );
+REG64_FLD( PERV_FI2C_CFG_RESERVED_FOR_CONFIGS                      , 41  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_FOR_CONFIGS );
+REG64_FLD( PERV_FI2C_CFG_RESERVED_FOR_CONFIGS_LEN                  , 3   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_FOR_CONFIGS_LEN );
+REG64_FLD( PERV_FI2C_CFG_I2C_TIMEOUT                               , 44  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_I2C_TIMEOUT );
+REG64_FLD( PERV_FI2C_CFG_I2C_TIMEOUT_LEN                           , 16  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_I2C_TIMEOUT_LEN );
+
+REG64_FLD( PERV_FI2C_SCFG0_REGISTER_VALID                          , 0   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_REGISTER_VALID );
+REG64_FLD( PERV_FI2C_SCFG0_RESERVED_3                              , 1   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_3 );
+REG64_FLD( PERV_FI2C_SCFG0_RESERVED_4                              , 2   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_4 );
+REG64_FLD( PERV_FI2C_SCFG0_RESERVED_4_LEN                          , 2   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_4_LEN );
+REG64_FLD( PERV_FI2C_SCFG0_RESERVED_5                              , 4   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_5 );
+REG64_FLD( PERV_FI2C_SCFG0_RESERVED_5_LEN                          , 4   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_5_LEN );
+REG64_FLD( PERV_FI2C_SCFG0_DEVICE_ID                               , 8   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_DEVICE_ID  );
+REG64_FLD( PERV_FI2C_SCFG0_DEVICE_ID_LEN                           , 7   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_DEVICE_ID_LEN );
+REG64_FLD( PERV_FI2C_SCFG0_ECC_ENABLE                              , 15  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_ECC_ENABLE );
+REG64_FLD( PERV_FI2C_SCFG0_MEMORY_SIZE_IN_PPE_ADDR_MAP             , 16  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP );
+REG64_FLD( PERV_FI2C_SCFG0_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN         , 16  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN );
+REG64_FLD( PERV_FI2C_SCFG0_START_SEEPROM_ADDRESS                   , 32  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START_SEEPROM_ADDRESS );
+REG64_FLD( PERV_FI2C_SCFG0_START_SEEPROM_ADDRESS_LEN               , 16  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START_SEEPROM_ADDRESS_LEN );
+REG64_FLD( PERV_FI2C_SCFG0_START_PPE_ADDR                          , 48  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START_PPE_ADDR );
+REG64_FLD( PERV_FI2C_SCFG0_START_PPE_ADDR_LEN                      , 16  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START_PPE_ADDR_LEN );
+
+REG64_FLD( PERV_FI2C_SCFG1_REGISTER_VALID                          , 0   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_REGISTER_VALID );
+REG64_FLD( PERV_FI2C_SCFG1_RESERVED_6                              , 1   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_6 );
+REG64_FLD( PERV_FI2C_SCFG1_RESERVED_7                              , 2   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_7 );
+REG64_FLD( PERV_FI2C_SCFG1_RESERVED_7_LEN                          , 2   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_7_LEN );
+REG64_FLD( PERV_FI2C_SCFG1_RESERVED_8                              , 4   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_8 );
+REG64_FLD( PERV_FI2C_SCFG1_RESERVED_8_LEN                          , 4   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_8_LEN );
+REG64_FLD( PERV_FI2C_SCFG1_DEVICE_ID                               , 8   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_DEVICE_ID  );
+REG64_FLD( PERV_FI2C_SCFG1_DEVICE_ID_LEN                           , 7   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_DEVICE_ID_LEN );
+REG64_FLD( PERV_FI2C_SCFG1_ECC_ENABLE                              , 15  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_ECC_ENABLE );
+REG64_FLD( PERV_FI2C_SCFG1_MEMORY_SIZE_IN_PPE_ADDR_MAP             , 16  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP );
+REG64_FLD( PERV_FI2C_SCFG1_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN         , 16  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN );
+REG64_FLD( PERV_FI2C_SCFG1_START_SEEPROM_ADDRESS                   , 32  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START_SEEPROM_ADDRESS );
+REG64_FLD( PERV_FI2C_SCFG1_START_SEEPROM_ADDRESS_LEN               , 16  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START_SEEPROM_ADDRESS_LEN );
+REG64_FLD( PERV_FI2C_SCFG1_START_PPE_ADDR                          , 48  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START_PPE_ADDR );
+REG64_FLD( PERV_FI2C_SCFG1_START_PPE_ADDR_LEN                      , 16  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START_PPE_ADDR_LEN );
+
+REG64_FLD( PERV_FI2C_SCFG2_REGISTER_VALID                          , 0   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_REGISTER_VALID );
+REG64_FLD( PERV_FI2C_SCFG2_RESERVED_9                              , 1   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_9 );
+REG64_FLD( PERV_FI2C_SCFG2_RESERVED_10                             , 2   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_10 );
+REG64_FLD( PERV_FI2C_SCFG2_RESERVED_10_LEN                         , 2   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_10_LEN );
+REG64_FLD( PERV_FI2C_SCFG2_RESERVED_11                             , 4   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_11 );
+REG64_FLD( PERV_FI2C_SCFG2_RESERVED_11_LEN                         , 4   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_11_LEN );
+REG64_FLD( PERV_FI2C_SCFG2_DEVICE_ID                               , 8   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_DEVICE_ID  );
+REG64_FLD( PERV_FI2C_SCFG2_DEVICE_ID_LEN                           , 7   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_DEVICE_ID_LEN );
+REG64_FLD( PERV_FI2C_SCFG2_ECC_ENABLE                              , 15  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_ECC_ENABLE );
+REG64_FLD( PERV_FI2C_SCFG2_MEMORY_SIZE_IN_PPE_ADDR_MAP             , 16  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP );
+REG64_FLD( PERV_FI2C_SCFG2_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN         , 16  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN );
+REG64_FLD( PERV_FI2C_SCFG2_START_SEEPROM_ADDRESS                   , 32  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START_SEEPROM_ADDRESS );
+REG64_FLD( PERV_FI2C_SCFG2_START_SEEPROM_ADDRESS_LEN               , 16  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START_SEEPROM_ADDRESS_LEN );
+REG64_FLD( PERV_FI2C_SCFG2_START_PPE_ADDR                          , 48  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START_PPE_ADDR );
+REG64_FLD( PERV_FI2C_SCFG2_START_PPE_ADDR_LEN                      , 16  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START_PPE_ADDR_LEN );
+
+REG64_FLD( PERV_FI2C_SCFG3_REGISTER_VALID                          , 0   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_REGISTER_VALID );
+REG64_FLD( PERV_FI2C_SCFG3_RESERVED_12                             , 1   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_12 );
+REG64_FLD( PERV_FI2C_SCFG3_RESERVED_13                             , 2   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_13 );
+REG64_FLD( PERV_FI2C_SCFG3_RESERVED_13_LEN                         , 2   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_13_LEN );
+REG64_FLD( PERV_FI2C_SCFG3_RESERVED_14                             , 4   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_14 );
+REG64_FLD( PERV_FI2C_SCFG3_RESERVED_14_LEN                         , 4   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_14_LEN );
+REG64_FLD( PERV_FI2C_SCFG3_DEVICE_ID                               , 8   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_DEVICE_ID  );
+REG64_FLD( PERV_FI2C_SCFG3_DEVICE_ID_LEN                           , 7   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_DEVICE_ID_LEN );
+REG64_FLD( PERV_FI2C_SCFG3_ECC_ENABLE                              , 15  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_ECC_ENABLE );
+REG64_FLD( PERV_FI2C_SCFG3_MEMORY_SIZE_IN_PPE_ADDR_MAP             , 16  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP );
+REG64_FLD( PERV_FI2C_SCFG3_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN         , 16  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN );
+REG64_FLD( PERV_FI2C_SCFG3_START_SEEPROM_ADDRESS                   , 32  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START_SEEPROM_ADDRESS );
+REG64_FLD( PERV_FI2C_SCFG3_START_SEEPROM_ADDRESS_LEN               , 16  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START_SEEPROM_ADDRESS_LEN );
+REG64_FLD( PERV_FI2C_SCFG3_START_PPE_ADDR                          , 48  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START_PPE_ADDR );
+REG64_FLD( PERV_FI2C_SCFG3_START_PPE_ADDR_LEN                      , 16  ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START_PPE_ADDR_LEN );
+
+REG64_FLD( PERV_FI2C_STAT_PIB_RESPONSE_INFO                        , 0   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_PIB_RESPONSE_INFO );
+REG64_FLD( PERV_FI2C_STAT_PIB_RESPONSE_INFO_LEN                    , 3   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_PIB_RESPONSE_INFO_LEN );
+REG64_FLD( PERV_FI2C_STAT_I2CM_PIB_ERRORS                          , 3   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_I2CM_PIB_ERRORS );
+REG64_FLD( PERV_FI2C_STAT_I2CM_PIB_ERRORS_LEN                      , 6   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_I2CM_PIB_ERRORS_LEN );
+REG64_FLD( PERV_FI2C_STAT_I2CM_ECC_ERRORS                          , 9   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_I2CM_ECC_ERRORS );
+REG64_FLD( PERV_FI2C_STAT_I2CM_ECC_ERRORS_LEN                      , 3   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_I2CM_ECC_ERRORS_LEN );
+REG64_FLD( PERV_FI2C_STAT_I2CM_I2C_ERRORS                          , 12  ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_I2CM_I2C_ERRORS );
+REG64_FLD( PERV_FI2C_STAT_I2CM_I2C_ERRORS_LEN                      , 7   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_I2CM_I2C_ERRORS_LEN );
+REG64_FLD( PERV_FI2C_STAT_ERR_ADDR_BEYOND_RANGE                    , 19  ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_ERR_ADDR_BEYOND_RANGE );
+REG64_FLD( PERV_FI2C_STAT_ERR_ADDR_OVERLAP                         , 20  ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_ERR_ADDR_OVERLAP );
+REG64_FLD( PERV_FI2C_STAT_PIB_ABORT                                , 21  ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_PIB_ABORT  );
+REG64_FLD( PERV_FI2C_STAT_RESERVED_FOR_ERRS                        , 22  ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_RESERVED_FOR_ERRS );
+REG64_FLD( PERV_FI2C_STAT_RESERVED_FOR_ERRS_LEN                    , 10  ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_RESERVED_FOR_ERRS_LEN );
+REG64_FLD( PERV_FI2C_STAT_LOCKED_PIBM_ADDR                         , 32  ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_LOCKED_PIBM_ADDR );
+REG64_FLD( PERV_FI2C_STAT_LOCKED_PIBM_ADDR_LEN                     , 8   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_LOCKED_PIBM_ADDR_LEN );
+REG64_FLD( PERV_FI2C_STAT_RESERVED_FOR_ADDRESS                     , 40  ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_RESERVED_FOR_ADDRESS );
+REG64_FLD( PERV_FI2C_STAT_RESERVED_FOR_ADDRESS_LEN                 , 3   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_RESERVED_FOR_ADDRESS_LEN );
+REG64_FLD( PERV_FI2C_STAT_LOCKED_FSM_STATE                         , 43  ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_LOCKED_FSM_STATE );
+REG64_FLD( PERV_FI2C_STAT_LOCKED_FSM_STATE_LEN                     , 5   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_LOCKED_FSM_STATE_LEN );
+REG64_FLD( PERV_FI2C_STAT_LOCKED_SEEPROM_ADDRESS                   , 48  ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_LOCKED_SEEPROM_ADDRESS );
+REG64_FLD( PERV_FI2C_STAT_LOCKED_SEEPROM_ADDRESS_LEN               , 16  ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_LOCKED_SEEPROM_ADDRESS_LEN );
+
+REG64_FLD( PERV_FIRST_ERR_REG_TIMEOUT_ACTIVE                       , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TIMEOUT_ACTIVE );
+REG64_FLD( PERV_FIRST_ERR_REG_PARITY                               , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_PARITY     );
+REG64_FLD( PERV_FIRST_ERR_REG_BEAT_NUM                             , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_BEAT_NUM   );
+REG64_FLD( PERV_FIRST_ERR_REG_BEAT_REC                             , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_BEAT_REC   );
+REG64_FLD( PERV_FIRST_ERR_REG_RECEIVED_ERROR                       , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_RECEIVED_ERROR );
+REG64_FLD( PERV_FIRST_ERR_REG_RX_PCB_DATA_P                        , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_RX_PCB_DATA_P );
+REG64_FLD( PERV_FIRST_ERR_REG_PIB_ADDR_P                           , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_PIB_ADDR_P );
+REG64_FLD( PERV_FIRST_ERR_REG_PIB_DATA_P                           , 7   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_PIB_DATA_P );
+
+REG64_FLD( PERV_FIRST_REPLY_REG_REGISTER                           , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_REGISTER   );
+REG64_FLD( PERV_FIRST_REPLY_REG_REGISTER_LEN                       , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_REGISTER_LEN );
+
+REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SBE    , 6   ,
+           SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DNFIFO_REQ_RESET_FR_SBE );
+REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SP     , 7   ,
+           SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DNFIFO_REQ_RESET_FR_SP );
+REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_DEQUEUED_EOT_FLAG   , 8   ,
+           SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DNFIFO_DEQUEUED_EOT_FLAG );
+REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_FULL           , 10  ,
+           SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DNFIFO_FIFO_FULL );
+REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EMPTY          , 11  ,
+           SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DNFIFO_FIFO_EMPTY );
+REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT    , 12  ,
+           SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DNFIFO_FIFO_ENTRY_COUNT );
+REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT_LEN , 4   ,
+           SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DNFIFO_FIFO_ENTRY_COUNT_LEN );
+REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS    , 16  ,
+           SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DNFIFO_FIFO_VALID_FLAGS );
+REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS_LEN , 8   ,
+           SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DNFIFO_FIFO_VALID_FLAGS_LEN );
+REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS      , 24  ,
+           SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DNFIFO_FIFO_EOT_FLAGS );
+REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS_LEN  , 8   ,
+           SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DNFIFO_FIFO_EOT_FLAGS_LEN );
+
+REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_REQ_RESET_FR_SP              , 6   ,
+           SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_REQ_RESET_FR_SP );
+REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_REQ_RESET_FR_SBE             , 7   ,
+           SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_REQ_RESET_FR_SBE );
+REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_DEQUEUED_EOT_FLAG            , 8   ,
+           SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DEQUEUED_EOT_FLAG );
+REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_FULL                    , 10  ,
+           SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_FIFO_FULL  );
+REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_EMPTY                   , 11  ,
+           SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_FIFO_EMPTY );
+REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT             , 12  ,
+           SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_FIFO_ENTRY_COUNT );
+REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT_LEN         , 4   ,
+           SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_FIFO_ENTRY_COUNT_LEN );
+REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS             , 16  ,
+           SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_FIFO_VALID_FLAGS );
+REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS_LEN         , 8   ,
+           SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_FIFO_VALID_FLAGS_LEN );
+REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS               , 24  ,
+           SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_FIFO_EOT_FLAGS );
+REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS_LEN           , 8   ,
+           SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_FIFO_EOT_FLAGS_LEN );
+
+REG32_FLD( PERV_FSISCRPD_FSI_SCRATCH_PAD                           , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI_BYTE , SH_FLD_FSI_SCRATCH_PAD );
+REG32_FLD( PERV_FSISCRPD_FSI_SCRATCH_PAD_LEN                       , 32  ,
+           SH_UNT_PERV     , SH_ACS_FSI_BYTE , SH_FLD_FSI_SCRATCH_PAD_LEN );
+
+REG32_FLD( PERV_FSI_A_LLMOD_ASYNC_MODE                             , 31  ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_ASYNC_MODE );
+
+REG32_FLD( PERV_FSI_A_MST_0_MENP0_PORT_ENABLE                      , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_0_MENP0_PORT_1_ENABLE                    , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT_1_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_0_MENP0_PORT_2_ENABLE                    , 2   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT_2_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_0_MENP0_PORT_3_ENABLE                    , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT_3_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_0_MENP0_PORT_4_ENABLE                    , 4   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT_4_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_0_MENP0_PORT_5_ENABLE                    , 5   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT_5_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_0_MENP0_PORT_6_ENABLE                    , 6   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT_6_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_0_MENP0_PORT_7_ENABLE                    , 7   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT_7_ENABLE );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_ENABLE             , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_1_ENABLE           , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_1_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_2_ENABLE           , 2   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_2_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_3_ENABLE           , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_3_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_4_ENABLE           , 4   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_4_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_5_ENABLE           , 5   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_5_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_6_ENABLE           , 6   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_6_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_7_ENABLE           , 7   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_7_ENABLE );
+
+REG32_FLD( PERV_FSI_A_MST_0_MESRB0_FIRST_ERROR                     , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_FIRST_ERROR );
+REG32_FLD( PERV_FSI_A_MST_0_MESRB0_FIRST_ERROR_LEN                 , 4   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_FIRST_ERROR_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_FRST         , 17  ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_FAILING_OPB_MASTER_FRST );
+REG32_FLD( PERV_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_FRST_LEN     , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_FAILING_OPB_MASTER_FRST_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MESRB0_ACTUAL_ERROR                    , 20  ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_ACTUAL_ERROR );
+REG32_FLD( PERV_FSI_A_MST_0_MESRB0_ACTUAL_ERROR_LEN                , 4   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_ACTUAL_ERROR_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_ACT          , 29  ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_FAILING_OPB_MASTER_ACT );
+REG32_FLD( PERV_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_ACT_LEN      , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_FAILING_OPB_MASTER_ACT_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FIRST_ERROR            , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_FIRST_ERROR );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FIRST_ERROR_LEN        , 4   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_FIRST_ERROR_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_FRST , 17  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_FAILING_OPB_MASTER_FRST );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_FRST_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_FAILING_OPB_MASTER_FRST_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_ACTUAL_ERROR           , 20  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_ACTUAL_ERROR );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_ACTUAL_ERROR_LEN       , 4   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_ACTUAL_ERROR_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_ACT , 29  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_FAILING_OPB_MASTER_ACT );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_ACT_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_FAILING_OPB_MASTER_ACT_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_ENABLE_IPOLL_AND_DMA             , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_ENABLE_IPOLL_AND_DMA );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_ENABLE_HW_ERROR_RECOVERY         , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_ENABLE_HW_ERROR_RECOVERY );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_ENABLE_RELATIVE_ADDRESS_CMDS     , 2   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_ENABLE_RELATIVE_ADDRESS_CMDS );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_ENABLE_PARITY_CHECK              , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_ENABLE_PARITY_CHECK );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION             , 4   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_CLOCK_RATE_SELECTION );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION_LEN         , 10  ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_CLOCK_RATE_SELECTION_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION_1           , 14  ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_CLOCK_RATE_SELECTION_1 );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION_1_LEN       , 10  ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_CLOCK_RATE_SELECTION_1_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_CLOCK_DIV_4                      , 25  ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_CLOCK_DIV_4 );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_TIMEOUT_SEL                      , 26  ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_TIMEOUT_SEL );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_TIMEOUT_SEL_LEN                  , 2   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_TIMEOUT_SEL_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_RECEIVER_MODE                    , 29  ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_RECEIVER_MODE );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_RECEIVER_MODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_RECEIVER_MODE_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_ENABLE_IPOLL_AND_DMA    , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_ENABLE_IPOLL_AND_DMA );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_ENABLE_HW_ERROR_RECOVERY , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_ENABLE_HW_ERROR_RECOVERY );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_ENABLE_RELATIVE_ADDRESS_CMDS , 2   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_ENABLE_RELATIVE_ADDRESS_CMDS );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_ENABLE_PARITY_CHECK     , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_ENABLE_PARITY_CHECK );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION    , 4   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_CLOCK_RATE_SELECTION );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION_LEN , 10  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_CLOCK_RATE_SELECTION_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION_1  , 14  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_CLOCK_RATE_SELECTION_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION_1_LEN , 10  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_CLOCK_RATE_SELECTION_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_CLOCK_DIV_4             , 25  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_CLOCK_DIV_4 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_TIMEOUT_SEL             , 26  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_TIMEOUT_SEL );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_TIMEOUT_SEL_LEN         , 2   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_TIMEOUT_SEL_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_RECEIVER_MODE           , 29  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_RECEIVER_MODE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_RECEIVER_MODE_LEN       , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_RECEIVER_MODE_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_0_MRESP1_PORT_GENERAL_RESET_1            , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT_GENERAL_RESET_1 );
+REG32_FLD( PERV_FSI_A_MST_0_MRESP1_PORT_ERROR_RESET_1              , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT_ERROR_RESET_1 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP1_PORT_GENERAL_RESET_1   , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_GENERAL_RESET_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP1_PORT_ERROR_RESET_1     , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_ERROR_RESET_1 );
+
+REG32_FLD( PERV_FSI_A_MST_0_MRESP2_PORT_GENERAL_RESET_2            , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT_GENERAL_RESET_2 );
+REG32_FLD( PERV_FSI_A_MST_0_MRESP2_PORT_ERROR_RESET_2              , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT_ERROR_RESET_2 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP2_PORT_GENERAL_RESET_2   , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_GENERAL_RESET_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP2_PORT_ERROR_RESET_2     , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_ERROR_RESET_2 );
+
+REG32_FLD( PERV_FSI_A_MST_0_MRESP3_PORT_GENERAL_RESET_3            , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT_GENERAL_RESET_3 );
+REG32_FLD( PERV_FSI_A_MST_0_MRESP3_PORT_ERROR_RESET_3              , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT_ERROR_RESET_3 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP3_PORT_GENERAL_RESET_3   , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_GENERAL_RESET_3 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP3_PORT_ERROR_RESET_3     , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_ERROR_RESET_3 );
+
+REG32_FLD( PERV_FSI_A_MST_0_MRESP4_PORT_GENERAL_RESET_4            , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT_GENERAL_RESET_4 );
+REG32_FLD( PERV_FSI_A_MST_0_MRESP4_PORT_ERROR_RESET_4              , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT_ERROR_RESET_4 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP4_PORT_GENERAL_RESET_4   , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_GENERAL_RESET_4 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP4_PORT_ERROR_RESET_4     , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_ERROR_RESET_4 );
+
+REG32_FLD( PERV_FSI_A_MST_0_MRESP5_PORT_GENERAL_RESET_5            , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT_GENERAL_RESET_5 );
+REG32_FLD( PERV_FSI_A_MST_0_MRESP5_PORT_ERROR_RESET_5              , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT_ERROR_RESET_5 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP5_PORT_GENERAL_RESET_5   , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_GENERAL_RESET_5 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP5_PORT_ERROR_RESET_5     , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_ERROR_RESET_5 );
+
+REG32_FLD( PERV_FSI_A_MST_0_MRESP6_PORT_GENERAL_RESET_6            , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT_GENERAL_RESET_6 );
+REG32_FLD( PERV_FSI_A_MST_0_MRESP6_PORT_ERROR_RESET_6              , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT_ERROR_RESET_6 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP6_PORT_GENERAL_RESET_6   , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_GENERAL_RESET_6 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP6_PORT_ERROR_RESET_6     , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_ERROR_RESET_6 );
+
+REG32_FLD( PERV_FSI_A_MST_0_MRESP7_PORT_GENERAL_RESET_7            , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT_GENERAL_RESET_7 );
+REG32_FLD( PERV_FSI_A_MST_0_MRESP7_PORT_ERROR_RESET_7              , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT_ERROR_RESET_7 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP7_PORT_GENERAL_RESET_7   , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_GENERAL_RESET_7 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP7_PORT_ERROR_RESET_7     , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_ERROR_RESET_7 );
+
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE                , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT0_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT0_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_1              , 5   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT0_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_1_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT0_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT0_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT0_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE       , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT0_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_LEN   , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT0_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_1     , 5   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT0_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_1_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT0_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_2     , 9   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT0_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_2_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT0_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE                , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT1_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT1_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_1              , 5   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT1_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_1_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT1_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT1_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT1_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE       , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT1_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_LEN   , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT1_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_1     , 5   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT1_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_1_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT1_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_2     , 9   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT1_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_2_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT1_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE                , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT2_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT2_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_1              , 5   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT2_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_1_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT2_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT2_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT2_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE       , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT2_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_LEN   , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT2_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_1     , 5   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT2_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_1_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT2_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_2     , 9   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT2_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_2_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT2_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE                , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT3_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT3_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_1              , 5   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT3_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_1_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT3_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT3_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT3_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE       , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT3_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_LEN   , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT3_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_1     , 5   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT3_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_1_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT3_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_2     , 9   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT3_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_2_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT3_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE                , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT4_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT4_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_1              , 5   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT4_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_1_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT4_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT4_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT4_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE       , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT4_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_LEN   , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT4_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_1     , 5   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT4_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_1_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT4_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_2     , 9   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT4_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_2_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT4_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE                , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT5_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT5_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_1              , 5   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT5_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_1_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT5_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT5_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT5_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE       , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT5_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_LEN   , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT5_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_1     , 5   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT5_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_1_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT5_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_2     , 9   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT5_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_2_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT5_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE                , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT6_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT6_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_1              , 5   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT6_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_1_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT6_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT6_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT6_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE       , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT6_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_LEN   , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT6_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_1     , 5   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT6_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_1_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT6_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_2     , 9   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT6_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_2_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT6_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE                , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT7_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT7_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_1              , 5   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT7_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_1_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT7_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT7_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_PORT7_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE       , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT7_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_LEN   , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT7_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_1     , 5   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT7_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_1_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT7_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_2     , 9   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT7_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_2_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT7_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_1_MENP0_PORT_0_ENABLE                    , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT_0_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_1_MENP0_PORT_ENABLE                      , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_1_MENP0_PORT_2_ENABLE                    , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT_2_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_1_MENP0_PORT_3_ENABLE                    , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT_3_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_1_MENP0_PORT_4_ENABLE                    , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT_4_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_1_MENP0_PORT_5_ENABLE                    , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT_5_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_1_MENP0_PORT_6_ENABLE                    , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT_6_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_1_MENP0_PORT_7_ENABLE                    , 7   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT_7_ENABLE );
+
+REG32_FLD( PERV_FSI_A_MST_1_MESRB0_FIRST_ERROR                     , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_FIRST_ERROR );
+REG32_FLD( PERV_FSI_A_MST_1_MESRB0_FIRST_ERROR_LEN                 , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_FIRST_ERROR_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MESRB0_FAILING_OPB_MASTER_FRST         , 17  ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_FAILING_OPB_MASTER_FRST );
+REG32_FLD( PERV_FSI_A_MST_1_MESRB0_FAILING_OPB_MASTER_FRST_LEN     , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_FAILING_OPB_MASTER_FRST_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MESRB0_ACTUAL_ERROR                    , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_ACTUAL_ERROR );
+REG32_FLD( PERV_FSI_A_MST_1_MESRB0_ACTUAL_ERROR_LEN                , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_ACTUAL_ERROR_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MESRB0_FAILING_OPB_MASTER_ACT          , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_FAILING_OPB_MASTER_ACT );
+REG32_FLD( PERV_FSI_A_MST_1_MESRB0_FAILING_OPB_MASTER_ACT_LEN      , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_FAILING_OPB_MASTER_ACT_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_ENABLE_IPOLL_AND_DMA             , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_ENABLE_IPOLL_AND_DMA );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_ENABLE_HW_ERROR_RECOVERY         , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_ENABLE_HW_ERROR_RECOVERY );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_ENABLE_RELATIVE_ADDRESS_CMDS     , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_ENABLE_RELATIVE_ADDRESS_CMDS );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_ENABLE_PARITY_CHECK              , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_ENABLE_PARITY_CHECK );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_CLOCK_RATE_SELECTION_0           , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_CLOCK_RATE_SELECTION_0 );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_CLOCK_RATE_SELECTION_0_LEN       , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_CLOCK_RATE_SELECTION_0_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_CLOCK_RATE_SELECTION             , 14  ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_CLOCK_RATE_SELECTION );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_CLOCK_RATE_SELECTION_LEN         , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_CLOCK_RATE_SELECTION_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_CLOCK_DIV_4                      , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_CLOCK_DIV_4 );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_TIMEOUT_SEL                      , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_TIMEOUT_SEL );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_TIMEOUT_SEL_LEN                  , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_TIMEOUT_SEL_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_RECEIVER_MODE                    , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_RECEIVER_MODE );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_RECEIVER_MODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_RECEIVER_MODE_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_1_MRESP1_PORT_GENERAL_RESET              , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT_GENERAL_RESET );
+REG32_FLD( PERV_FSI_A_MST_1_MRESP1_PORT_ERROR_RESET                , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT_ERROR_RESET );
+
+REG32_FLD( PERV_FSI_A_MST_1_MRESP2_PORT_GENERAL_RESET_2            , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT_GENERAL_RESET_2 );
+REG32_FLD( PERV_FSI_A_MST_1_MRESP2_PORT_ERROR_RESET_2              , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT_ERROR_RESET_2 );
+
+REG32_FLD( PERV_FSI_A_MST_1_MRESP3_PORT_GENERAL_RESET_3            , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT_GENERAL_RESET_3 );
+REG32_FLD( PERV_FSI_A_MST_1_MRESP3_PORT_ERROR_RESET_3              , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT_ERROR_RESET_3 );
+
+REG32_FLD( PERV_FSI_A_MST_1_MRESP4_PORT_GENERAL_RESET_4            , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT_GENERAL_RESET_4 );
+REG32_FLD( PERV_FSI_A_MST_1_MRESP4_PORT_ERROR_RESET_4              , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT_ERROR_RESET_4 );
+
+REG32_FLD( PERV_FSI_A_MST_1_MRESP5_PORT_GENERAL_RESET_5            , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT_GENERAL_RESET_5 );
+REG32_FLD( PERV_FSI_A_MST_1_MRESP5_PORT_ERROR_RESET_5              , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT_ERROR_RESET_5 );
+
+REG32_FLD( PERV_FSI_A_MST_1_MRESP6_PORT_GENERAL_RESET_6            , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT_GENERAL_RESET_6 );
+REG32_FLD( PERV_FSI_A_MST_1_MRESP6_PORT_ERROR_RESET_6              , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT_ERROR_RESET_6 );
+
+REG32_FLD( PERV_FSI_A_MST_1_MRESP7_PORT_GENERAL_RESET_7            , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT_GENERAL_RESET_7 );
+REG32_FLD( PERV_FSI_A_MST_1_MRESP7_PORT_ERROR_RESET_7              , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT_ERROR_RESET_7 );
+
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP0_PORT0_ERROR_CODE_0              , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT0_ERROR_CODE_0 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP0_PORT0_ERROR_CODE_0_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT0_ERROR_CODE_0_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP0_PORT0_ERROR_CODE                , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT0_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP0_PORT0_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT0_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP0_PORT0_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT0_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP0_PORT0_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT0_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP1_PORT1_ERROR_CODE_0              , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT1_ERROR_CODE_0 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP1_PORT1_ERROR_CODE_0_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT1_ERROR_CODE_0_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP1_PORT1_ERROR_CODE                , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT1_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP1_PORT1_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT1_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP1_PORT1_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT1_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP1_PORT1_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT1_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP2_PORT2_ERROR_CODE_0              , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT2_ERROR_CODE_0 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP2_PORT2_ERROR_CODE_0_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT2_ERROR_CODE_0_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP2_PORT2_ERROR_CODE                , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT2_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP2_PORT2_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT2_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP2_PORT2_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT2_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP2_PORT2_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT2_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP3_PORT3_ERROR_CODE_0              , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT3_ERROR_CODE_0 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP3_PORT3_ERROR_CODE_0_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT3_ERROR_CODE_0_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP3_PORT3_ERROR_CODE                , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT3_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP3_PORT3_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT3_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP3_PORT3_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT3_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP3_PORT3_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT3_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP4_PORT4_ERROR_CODE_0              , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT4_ERROR_CODE_0 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP4_PORT4_ERROR_CODE_0_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT4_ERROR_CODE_0_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP4_PORT4_ERROR_CODE                , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT4_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP4_PORT4_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT4_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP4_PORT4_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT4_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP4_PORT4_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT4_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP5_PORT5_ERROR_CODE_0              , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT5_ERROR_CODE_0 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP5_PORT5_ERROR_CODE_0_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT5_ERROR_CODE_0_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP5_PORT5_ERROR_CODE                , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT5_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP5_PORT5_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT5_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP5_PORT5_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT5_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP5_PORT5_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT5_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP6_PORT6_ERROR_CODE_0              , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT6_ERROR_CODE_0 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP6_PORT6_ERROR_CODE_0_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT6_ERROR_CODE_0_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP6_PORT6_ERROR_CODE                , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT6_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP6_PORT6_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT6_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP6_PORT6_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT6_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP6_PORT6_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT6_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP7_PORT7_ERROR_CODE_0              , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT7_ERROR_CODE_0 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP7_PORT7_ERROR_CODE_0_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT7_ERROR_CODE_0_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP7_PORT7_ERROR_CODE                , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT7_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP7_PORT7_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT7_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP7_PORT7_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT7_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP7_PORT7_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOMFSI0 , SH_FLD_PORT7_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_SMODE_WARM_START_COMPLETED                   , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_WARM_START_COMPLETED );
+REG32_FLD( PERV_FSI_A_SMODE_ENABLE_AUX_PORT_UNUSED                 , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_ENABLE_AUX_PORT_UNUSED );
+REG32_FLD( PERV_FSI_A_SMODE_ENABLE_HW_ERROR_RECOVERY               , 2   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_ENABLE_HW_ERROR_RECOVERY );
+REG32_FLD( PERV_FSI_A_SMODE_OWN_ID_THIS_SLAVE                      , 6   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_OWN_ID_THIS_SLAVE );
+REG32_FLD( PERV_FSI_A_SMODE_OWN_ID_THIS_SLAVE_LEN                  , 2   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_OWN_ID_THIS_SLAVE_LEN );
+REG32_FLD( PERV_FSI_A_SMODE_ECHO_DELAY_CYCLES                      , 8   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_ECHO_DELAY_CYCLES );
+REG32_FLD( PERV_FSI_A_SMODE_ECHO_DELAY_CYCLES_LEN                  , 4   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_ECHO_DELAY_CYCLES_LEN );
+REG32_FLD( PERV_FSI_A_SMODE_SEND_DELAY_CYCLES                      , 12  ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_SEND_DELAY_CYCLES );
+REG32_FLD( PERV_FSI_A_SMODE_SEND_DELAY_CYCLES_LEN                  , 4   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_SEND_DELAY_CYCLES_LEN );
+REG32_FLD( PERV_FSI_A_SMODE_LBUS_CLOCK_DIVIDER                     , 20  ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_LBUS_CLOCK_DIVIDER );
+REG32_FLD( PERV_FSI_A_SMODE_LBUS_CLOCK_DIVIDER_LEN                 , 4   ,
+           SH_UNT_PERV     , SH_ACS_FSI0     , SH_FLD_LBUS_CLOCK_DIVIDER_LEN );
+
+REG32_FLD( PERV_FSI_B_LLMOD_ASYNC_MODE                             , 31  ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_ASYNC_MODE );
+
+REG32_FLD( PERV_FSI_B_MST_0_MENP0_PORT_ENABLE                      , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT_ENABLE );
+REG32_FLD( PERV_FSI_B_MST_0_MENP0_PORT_1_ENABLE                    , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT_1_ENABLE );
+REG32_FLD( PERV_FSI_B_MST_0_MENP0_PORT_2_ENABLE                    , 2   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT_2_ENABLE );
+REG32_FLD( PERV_FSI_B_MST_0_MENP0_PORT_3_ENABLE                    , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT_3_ENABLE );
+REG32_FLD( PERV_FSI_B_MST_0_MENP0_PORT_4_ENABLE                    , 4   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT_4_ENABLE );
+REG32_FLD( PERV_FSI_B_MST_0_MENP0_PORT_5_ENABLE                    , 5   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT_5_ENABLE );
+REG32_FLD( PERV_FSI_B_MST_0_MENP0_PORT_6_ENABLE                    , 6   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT_6_ENABLE );
+REG32_FLD( PERV_FSI_B_MST_0_MENP0_PORT_7_ENABLE                    , 7   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT_7_ENABLE );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_ENABLE             , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_1_ENABLE           , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_1_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_2_ENABLE           , 2   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_2_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_3_ENABLE           , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_3_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_4_ENABLE           , 4   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_4_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_5_ENABLE           , 5   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_5_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_6_ENABLE           , 6   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_6_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_7_ENABLE           , 7   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_7_ENABLE );
+
+REG32_FLD( PERV_FSI_B_MST_0_MESRB0_FIRST_ERROR                     , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_FIRST_ERROR );
+REG32_FLD( PERV_FSI_B_MST_0_MESRB0_FIRST_ERROR_LEN                 , 4   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_FIRST_ERROR_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_FRST         , 17  ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_FAILING_OPB_MASTER_FRST );
+REG32_FLD( PERV_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_FRST_LEN     , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_FAILING_OPB_MASTER_FRST_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MESRB0_ACTUAL_ERROR                    , 20  ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_ACTUAL_ERROR );
+REG32_FLD( PERV_FSI_B_MST_0_MESRB0_ACTUAL_ERROR_LEN                , 4   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_ACTUAL_ERROR_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_ACT          , 29  ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_FAILING_OPB_MASTER_ACT );
+REG32_FLD( PERV_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_ACT_LEN      , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_FAILING_OPB_MASTER_ACT_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FIRST_ERROR            , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_FIRST_ERROR );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FIRST_ERROR_LEN        , 4   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_FIRST_ERROR_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_FRST , 17  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_FAILING_OPB_MASTER_FRST );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_FRST_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_FAILING_OPB_MASTER_FRST_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_ACTUAL_ERROR           , 20  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_ACTUAL_ERROR );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_ACTUAL_ERROR_LEN       , 4   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_ACTUAL_ERROR_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_ACT , 29  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_FAILING_OPB_MASTER_ACT );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_ACT_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_FAILING_OPB_MASTER_ACT_LEN );
+
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_ENABLE_IPOLL_AND_DMA             , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_ENABLE_IPOLL_AND_DMA );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_ENABLE_HW_ERROR_RECOVERY         , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_ENABLE_HW_ERROR_RECOVERY );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_ENABLE_RELATIVE_ADDRESS_CMDS     , 2   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_ENABLE_RELATIVE_ADDRESS_CMDS );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_ENABLE_PARITY_CHECK              , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_ENABLE_PARITY_CHECK );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION             , 4   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_CLOCK_RATE_SELECTION );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION_LEN         , 10  ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_CLOCK_RATE_SELECTION_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION_1           , 14  ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_CLOCK_RATE_SELECTION_1 );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION_1_LEN       , 10  ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_CLOCK_RATE_SELECTION_1_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_CLOCK_DIV_4                      , 25  ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_CLOCK_DIV_4 );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_TIMEOUT_SEL                      , 26  ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_TIMEOUT_SEL );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_TIMEOUT_SEL_LEN                  , 2   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_TIMEOUT_SEL_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_RECEIVER_MODE                    , 29  ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_RECEIVER_MODE );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_RECEIVER_MODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_RECEIVER_MODE_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_ENABLE_IPOLL_AND_DMA    , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_ENABLE_IPOLL_AND_DMA );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_ENABLE_HW_ERROR_RECOVERY , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_ENABLE_HW_ERROR_RECOVERY );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_ENABLE_RELATIVE_ADDRESS_CMDS , 2   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_ENABLE_RELATIVE_ADDRESS_CMDS );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_ENABLE_PARITY_CHECK     , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_ENABLE_PARITY_CHECK );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION    , 4   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_CLOCK_RATE_SELECTION );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION_LEN , 10  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_CLOCK_RATE_SELECTION_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION_1  , 14  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_CLOCK_RATE_SELECTION_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION_1_LEN , 10  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_CLOCK_RATE_SELECTION_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_CLOCK_DIV_4             , 25  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_CLOCK_DIV_4 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_TIMEOUT_SEL             , 26  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_TIMEOUT_SEL );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_TIMEOUT_SEL_LEN         , 2   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_TIMEOUT_SEL_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_RECEIVER_MODE           , 29  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_RECEIVER_MODE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_RECEIVER_MODE_LEN       , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_RECEIVER_MODE_LEN );
+
+REG32_FLD( PERV_FSI_B_MST_0_MRESP1_PORT_GENERAL_RESET_1            , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT_GENERAL_RESET_1 );
+REG32_FLD( PERV_FSI_B_MST_0_MRESP1_PORT_ERROR_RESET_1              , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT_ERROR_RESET_1 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP1_PORT_GENERAL_RESET_1   , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_GENERAL_RESET_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP1_PORT_ERROR_RESET_1     , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_ERROR_RESET_1 );
+
+REG32_FLD( PERV_FSI_B_MST_0_MRESP2_PORT_GENERAL_RESET_2            , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT_GENERAL_RESET_2 );
+REG32_FLD( PERV_FSI_B_MST_0_MRESP2_PORT_ERROR_RESET_2              , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT_ERROR_RESET_2 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP2_PORT_GENERAL_RESET_2   , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_GENERAL_RESET_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP2_PORT_ERROR_RESET_2     , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_ERROR_RESET_2 );
+
+REG32_FLD( PERV_FSI_B_MST_0_MRESP3_PORT_GENERAL_RESET_3            , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT_GENERAL_RESET_3 );
+REG32_FLD( PERV_FSI_B_MST_0_MRESP3_PORT_ERROR_RESET_3              , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT_ERROR_RESET_3 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP3_PORT_GENERAL_RESET_3   , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_GENERAL_RESET_3 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP3_PORT_ERROR_RESET_3     , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_ERROR_RESET_3 );
+
+REG32_FLD( PERV_FSI_B_MST_0_MRESP4_PORT_GENERAL_RESET_4            , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT_GENERAL_RESET_4 );
+REG32_FLD( PERV_FSI_B_MST_0_MRESP4_PORT_ERROR_RESET_4              , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT_ERROR_RESET_4 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP4_PORT_GENERAL_RESET_4   , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_GENERAL_RESET_4 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP4_PORT_ERROR_RESET_4     , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_ERROR_RESET_4 );
+
+REG32_FLD( PERV_FSI_B_MST_0_MRESP5_PORT_GENERAL_RESET_5            , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT_GENERAL_RESET_5 );
+REG32_FLD( PERV_FSI_B_MST_0_MRESP5_PORT_ERROR_RESET_5              , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT_ERROR_RESET_5 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP5_PORT_GENERAL_RESET_5   , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_GENERAL_RESET_5 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP5_PORT_ERROR_RESET_5     , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_ERROR_RESET_5 );
+
+REG32_FLD( PERV_FSI_B_MST_0_MRESP6_PORT_GENERAL_RESET_6            , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT_GENERAL_RESET_6 );
+REG32_FLD( PERV_FSI_B_MST_0_MRESP6_PORT_ERROR_RESET_6              , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT_ERROR_RESET_6 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP6_PORT_GENERAL_RESET_6   , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_GENERAL_RESET_6 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP6_PORT_ERROR_RESET_6     , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_ERROR_RESET_6 );
+
+REG32_FLD( PERV_FSI_B_MST_0_MRESP7_PORT_GENERAL_RESET_7            , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT_GENERAL_RESET_7 );
+REG32_FLD( PERV_FSI_B_MST_0_MRESP7_PORT_ERROR_RESET_7              , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT_ERROR_RESET_7 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP7_PORT_GENERAL_RESET_7   , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_GENERAL_RESET_7 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP7_PORT_ERROR_RESET_7     , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_ERROR_RESET_7 );
+
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE                , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT0_ERROR_CODE );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT0_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_1              , 5   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT0_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_1_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT0_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT0_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT0_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE       , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT0_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_LEN   , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT0_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_1     , 5   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT0_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_1_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT0_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_2     , 9   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT0_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_2_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT0_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE                , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT1_ERROR_CODE );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT1_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_1              , 5   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT1_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_1_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT1_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT1_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT1_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE       , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT1_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_LEN   , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT1_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_1     , 5   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT1_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_1_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT1_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_2     , 9   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT1_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_2_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT1_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE                , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT2_ERROR_CODE );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT2_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_1              , 5   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT2_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_1_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT2_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT2_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT2_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE       , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT2_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_LEN   , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT2_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_1     , 5   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT2_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_1_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT2_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_2     , 9   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT2_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_2_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT2_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE                , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT3_ERROR_CODE );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT3_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_1              , 5   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT3_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_1_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT3_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT3_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT3_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE       , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT3_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_LEN   , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT3_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_1     , 5   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT3_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_1_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT3_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_2     , 9   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT3_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_2_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT3_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE                , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT4_ERROR_CODE );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT4_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_1              , 5   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT4_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_1_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT4_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT4_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT4_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE       , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT4_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_LEN   , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT4_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_1     , 5   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT4_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_1_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT4_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_2     , 9   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT4_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_2_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT4_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE                , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT5_ERROR_CODE );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT5_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_1              , 5   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT5_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_1_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT5_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT5_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT5_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE       , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT5_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_LEN   , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT5_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_1     , 5   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT5_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_1_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT5_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_2     , 9   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT5_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_2_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT5_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE                , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT6_ERROR_CODE );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT6_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_1              , 5   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT6_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_1_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT6_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT6_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT6_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE       , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT6_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_LEN   , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT6_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_1     , 5   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT6_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_1_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT6_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_2     , 9   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT6_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_2_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT6_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE                , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT7_ERROR_CODE );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT7_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_1              , 5   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT7_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_1_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT7_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_2              , 9   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT7_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_2_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_PORT7_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE       , 1   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT7_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_LEN   , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT7_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_1     , 5   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT7_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_1_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT7_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_2     , 9   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT7_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_2_LEN , 3   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT7_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_B_SMODE_WARM_START_COMPLETED                   , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_WARM_START_COMPLETED );
+REG32_FLD( PERV_FSI_B_SMODE_ENABLE_AUX_PORT_UNUSED                 , 1   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_ENABLE_AUX_PORT_UNUSED );
+REG32_FLD( PERV_FSI_B_SMODE_ENABLE_HW_ERROR_RECOVERY               , 2   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_ENABLE_HW_ERROR_RECOVERY );
+REG32_FLD( PERV_FSI_B_SMODE_OWN_ID_THIS_SLAVE                      , 6   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_OWN_ID_THIS_SLAVE );
+REG32_FLD( PERV_FSI_B_SMODE_OWN_ID_THIS_SLAVE_LEN                  , 2   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_OWN_ID_THIS_SLAVE_LEN );
+REG32_FLD( PERV_FSI_B_SMODE_ECHO_DELAY_CYCLES                      , 8   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_ECHO_DELAY_CYCLES );
+REG32_FLD( PERV_FSI_B_SMODE_ECHO_DELAY_CYCLES_LEN                  , 4   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_ECHO_DELAY_CYCLES_LEN );
+REG32_FLD( PERV_FSI_B_SMODE_SEND_DELAY_CYCLES                      , 12  ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_SEND_DELAY_CYCLES );
+REG32_FLD( PERV_FSI_B_SMODE_SEND_DELAY_CYCLES_LEN                  , 4   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_SEND_DELAY_CYCLES_LEN );
+REG32_FLD( PERV_FSI_B_SMODE_LBUS_CLOCK_DIVIDER                     , 20  ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_LBUS_CLOCK_DIVIDER );
+REG32_FLD( PERV_FSI_B_SMODE_LBUS_CLOCK_DIVIDER_LEN                 , 4   ,
+           SH_UNT_PERV     , SH_ACS_FSI1     , SH_FLD_LBUS_CLOCK_DIVIDER_LEN );
+
+REG64_FLD( PERV_GPWRP_MAGIC_COOKIE                                 , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MAGIC_COOKIE );
+REG64_FLD( PERV_GPWRP_MAGIC_COOKIE_LEN                             , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MAGIC_COOKIE_LEN );
+REG64_FLD( PERV_GPWRP_EN_OR_DIS_WRITE_PROTECTION                   , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_EN_OR_DIS_WRITE_PROTECTION );
+REG64_FLD( PERV_GPWRP_EN_OR_DIS_WRITE_PROTECTION_LEN               , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_EN_OR_DIS_WRITE_PROTECTION_LEN );
+
+REG64_FLD( PERV_1_HANG_PULSE_0_REG_0                               , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_0          );
+REG64_FLD( PERV_1_HANG_PULSE_0_REG_0_LEN                           , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_0_LEN      );
+REG64_FLD( PERV_1_HANG_PULSE_0_REG_SUPPRESS                        , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SUPPRESS   );
+
+REG64_FLD( PERV_1_HANG_PULSE_1_REG_1                               , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_1          );
+REG64_FLD( PERV_1_HANG_PULSE_1_REG_1_LEN                           , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_1_LEN      );
+REG64_FLD( PERV_1_HANG_PULSE_1_REG_SUPPRESS                        , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SUPPRESS   );
+
+REG64_FLD( PERV_1_HANG_PULSE_2_REG_2                               , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_2          );
+REG64_FLD( PERV_1_HANG_PULSE_2_REG_2_LEN                           , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_2_LEN      );
+REG64_FLD( PERV_1_HANG_PULSE_2_REG_SUPPRESS                        , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SUPPRESS   );
+
+REG64_FLD( PERV_1_HANG_PULSE_3_REG_3                               , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_3          );
+REG64_FLD( PERV_1_HANG_PULSE_3_REG_3_LEN                           , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_3_LEN      );
+REG64_FLD( PERV_1_HANG_PULSE_3_REG_SUPPRESS                        , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SUPPRESS   );
+
+REG64_FLD( PERV_1_HANG_PULSE_4_REG_4                               , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_4          );
+REG64_FLD( PERV_1_HANG_PULSE_4_REG_4_LEN                           , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_4_LEN      );
+REG64_FLD( PERV_1_HANG_PULSE_4_REG_SUPPRESS                        , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SUPPRESS   );
+
+REG64_FLD( PERV_1_HANG_PULSE_5_REG_5                               , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_5          );
+REG64_FLD( PERV_1_HANG_PULSE_5_REG_5_LEN                           , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_5_LEN      );
+REG64_FLD( PERV_1_HANG_PULSE_5_REG_SUPPRESS                        , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SUPPRESS   );
+
+REG64_FLD( PERV_1_HANG_PULSE_6_REG_6                               , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_6          );
+REG64_FLD( PERV_1_HANG_PULSE_6_REG_6_LEN                           , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_6_LEN      );
+REG64_FLD( PERV_1_HANG_PULSE_6_REG_SUPPRESS                        , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SUPPRESS   );
+
+REG64_FLD( PERV_1_HEARTBEAT_REG_DEAD                               , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_DEAD       );
+
+REG64_FLD( PERV_HOST_MASK_REG_IPOLL_0                              , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_IPOLL_0    );
+REG64_FLD( PERV_HOST_MASK_REG_IPOLL_1                              , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_IPOLL_1    );
+REG64_FLD( PERV_HOST_MASK_REG_IPOLL_2                              , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_IPOLL_2    );
+REG64_FLD( PERV_HOST_MASK_REG_IPOLL_3                              , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_IPOLL_3    );
+REG64_FLD( PERV_HOST_MASK_REG_IPOLL_4                              , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_IPOLL_4    );
+REG64_FLD( PERV_HOST_MASK_REG_IPOLL_5                              , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_IPOLL_5    );
+REG64_FLD( PERV_HOST_MASK_REG_ERROR_0                              , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_ERROR_0    );
+REG64_FLD( PERV_HOST_MASK_REG_ERROR_1                              , 7   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_ERROR_1    );
+REG64_FLD( PERV_HOST_MASK_REG_ERROR_2                              , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_ERROR_2    );
+REG64_FLD( PERV_HOST_MASK_REG_ERROR_3                              , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_ERROR_3    );
+REG64_FLD( PERV_HOST_MASK_REG_ERROR_4                              , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_ERROR_4    );
+REG64_FLD( PERV_HOST_MASK_REG_ERROR_5                              , 11  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_ERROR_5    );
+
+REG64_FLD( PERV_IGNORE_PAR_REG_PARITY                              , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_PARITY     );
+REG64_FLD( PERV_IGNORE_PAR_REG_DISABLE_ECC_CORRECTION              , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DISABLE_ECC_CORRECTION );
+REG64_FLD( PERV_IGNORE_PAR_REG_ECC_S_BIT_ERROR                     , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_ECC_S_BIT_ERROR );
+
+REG64_FLD( PERV_1_INJECT_REG_THERM_TRIP                            , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_THERM_TRIP );
+REG64_FLD( PERV_1_INJECT_REG_THERM_TRIP_LEN                        , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_THERM_TRIP_LEN );
+REG64_FLD( PERV_1_INJECT_REG_THERM_MODE                            , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_THERM_MODE );
+REG64_FLD( PERV_1_INJECT_REG_THERM_MODE_LEN                        , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_THERM_MODE_LEN );
+
+REG32_FLD( PERV_FSI2PIB_INTERRUPT_STATUS_REG                       , 0   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_STATUS_REG );
+REG32_FLD( PERV_FSI2PIB_INTERRUPT_STATUS_REG_LEN                   , 32  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_STATUS_REG_LEN );
+
+REG64_FLD( PERV_INTERRUPT1_REG_INTERRUPT1                          , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM2_AND, SH_FLD_INTERRUPT1 );
+REG64_FLD( PERV_INTERRUPT1_REG_INTERRUPT1_LEN                      , 56  ,
+           SH_UNT_PERV     , SH_ACS_SCOM2_AND, SH_FLD_INTERRUPT1_LEN );
+
+REG64_FLD( PERV_INTERRUPT2_REG_INTERRUPT2                          , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM2_AND, SH_FLD_INTERRUPT2 );
+REG64_FLD( PERV_INTERRUPT2_REG_INTERRUPT2_LEN                      , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM2_AND, SH_FLD_INTERRUPT2_LEN );
+
+REG64_FLD( PERV_INTERRUPT3_REG_INTERRUPT3                          , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM2_AND, SH_FLD_INTERRUPT3 );
+REG64_FLD( PERV_INTERRUPT3_REG_INTERRUPT3_LEN                      , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM2_AND, SH_FLD_INTERRUPT3_LEN );
+
+REG64_FLD( PERV_INTERRUPT4_REG_INTERRUPT4                          , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM2_AND, SH_FLD_INTERRUPT4 );
+REG64_FLD( PERV_INTERRUPT4_REG_INTERRUPT4_LEN                      , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM2_AND, SH_FLD_INTERRUPT4_LEN );
+
+REG64_FLD( PERV_INTERRUPT_CONF_REG_UNUSED0                         , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM2_WAND, SH_FLD_UNUSED0    );
+REG64_FLD( PERV_INTERRUPT_CONF_REG_CC                              , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM2_WAND, SH_FLD_CC         );
+REG64_FLD( PERV_INTERRUPT_CONF_REG_UNUSED2                         , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM2_WAND, SH_FLD_UNUSED2    );
+REG64_FLD( PERV_INTERRUPT_CONF_REG_UNUSED3                         , 11  ,
+           SH_UNT_PERV     , SH_ACS_SCOM2_WAND, SH_FLD_UNUSED3    );
+
+REG64_FLD( PERV_INTERRUPT_HOLD_REG_HOLD                            , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_HOLD       );
+REG64_FLD( PERV_INTERRUPT_HOLD_REG_HOLD_LEN                        , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_HOLD_LEN   );
+
+REG32_FLD( PERV_FSII2C_INTERRUPT_MASK_REGISTER_INT                 , 16  ,
+           SH_UNT_PERV_FSII2C, SH_ACS_SCOM2_AND, SH_FLD_INT        );
+REG32_FLD( PERV_FSII2C_INTERRUPT_MASK_REGISTER_INT_LEN             , 16  ,
+           SH_UNT_PERV_FSII2C, SH_ACS_SCOM2_AND, SH_FLD_INT_LEN    );
+
+REG64_FLD( PERV_INTERRUPT_TYPE_MASK_REG_GP                         , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM2_WAND, SH_FLD_GP         );
+REG64_FLD( PERV_INTERRUPT_TYPE_MASK_REG_CC                         , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM2_WAND, SH_FLD_CC         );
+REG64_FLD( PERV_INTERRUPT_TYPE_MASK_REG_UNUSED2                    , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM2_WAND, SH_FLD_UNUSED2    );
+REG64_FLD( PERV_INTERRUPT_TYPE_MASK_REG_UNUSED3                    , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM2_WAND, SH_FLD_UNUSED3    );
+
+REG64_FLD( PERV_INTERRUPT_TYPE_REG_ATTENTION                       , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_ATTENTION  );
+REG64_FLD( PERV_INTERRUPT_TYPE_REG_RECOVERABLE_ERROR               , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_RECOVERABLE_ERROR );
+REG64_FLD( PERV_INTERRUPT_TYPE_REG_CHECKSTOP                       , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_CHECKSTOP  );
+
+REG64_FLD( PERV_1_LOCAL_FIR_ACTION0_IN                             , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_IN         );
+REG64_FLD( PERV_1_LOCAL_FIR_ACTION0_IN_LEN                         , 41  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_IN_LEN     );
+
+REG64_FLD( PERV_1_LOCAL_FIR_ACTION1_IN                             , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_IN         );
+REG64_FLD( PERV_1_LOCAL_FIR_ACTION1_IN_LEN                         , 41  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_IN_LEN     );
+
+REG64_FLD( PERV_1_LOCAL_FIR_MASK_LFIR_IN                           , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_OR , SH_FLD_LFIR_IN    );
+REG64_FLD( PERV_1_LOCAL_FIR_MASK_LFIR_IN_LEN                       , 41  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_OR , SH_FLD_LFIR_IN_LEN );
+
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_0_A_M1HC0A                , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M1HC0A     );
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_0_A_M1HC0A_LEN            , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M1HC0A_LEN );
+
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_0_B_M1HC0B                , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_M1HC0B     );
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_0_B_M1HC0B_LEN            , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_M1HC0B_LEN );
+
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_1_A_M1HC1A                , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M1HC1A     );
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_1_A_M1HC1A_LEN            , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M1HC1A_LEN );
+
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_1_B_M1HC1B                , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_M1HC1B     );
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_1_B_M1HC1B_LEN            , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_M1HC1B_LEN );
+
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_2_A_M1HC2A                , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M1HC2A     );
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_2_A_M1HC2A_LEN            , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M1HC2A_LEN );
+
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_2_B_M1HC2B                , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_M1HC2B     );
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_2_B_M1HC2B_LEN            , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_M1HC2B_LEN );
+
+REG64_FLD(
+    PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_M1SASIM1_ENABLE_PIB_PENDING ,
+    29  , SH_UNT_PERV     , SH_ACS_SCOM1_CLEAR,
+    SH_FLD_M1SASIM1_ENABLE_PIB_PENDING );
+REG64_FLD( PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_M1SASIM1_ENABLE_XUP
+           , 30  , SH_UNT_PERV     , SH_ACS_SCOM1_CLEAR, SH_FLD_M1SASIM1_ENABLE_XUP );
+REG64_FLD(
+    PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_M1SASIM1_ENABLE_PIB_ERROR ,
+    31  , SH_UNT_PERV     , SH_ACS_SCOM1_CLEAR, SH_FLD_M1SASIM1_ENABLE_PIB_ERROR );
+
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_0_A_M2HC0A                , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M2HC0A     );
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_0_A_M2HC0A_LEN            , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M2HC0A_LEN );
+
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_0_B_M2HC0B                , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_M2HC0B     );
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_0_B_M2HC0B_LEN            , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_M2HC0B_LEN );
+
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_1_A_M2HC1A                , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M2HC1A     );
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_1_A_M2HC1A_LEN            , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M2HC1A_LEN );
+
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_1_B_M2HC1B                , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_M2HC1B     );
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_1_B_M2HC1B_LEN            , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_M2HC1B_LEN );
+
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_2_A_M2HC2A                , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M2HC2A     );
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_2_A_M2HC2A_LEN            , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M2HC2A_LEN );
+
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_2_B_M2HC2B                , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_M2HC2B     );
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_2_B_M2HC2B_LEN            , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_M2HC2B_LEN );
+
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_UNUSED_31_28 ,
+           0   , SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSADES_UNUSED_31_28 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_UNUSED_31_28_LEN ,
+           4   , SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSADES_UNUSED_31_28_LEN );
+REG64_FLD(
+    PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ILLEGAL_OPERATION_ATTEMPTED_1
+    , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+    SH_FLD_MSADES_ILLEGAL_OPERATION_ATTEMPTED_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_WRITE_FULL_PIB_1 ,
+           5   , SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSADES_WRITE_FULL_PIB_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_READ_EMPTY_PIB_1 ,
+           6   , SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSADES_READ_EMPTY_PIB_1 );
+REG64_FLD(
+    PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_LBUS_B_RAM_PARITY_DETECTED_1 ,
+    7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+    SH_FLD_MSADES_LBUS_B_RAM_PARITY_DETECTED_1 );
+REG64_FLD(
+    PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ADDRESS_OF_LBUS_PARITY_1 ,
+    8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+    SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_1 );
+REG64_FLD(
+    PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ADDRESS_OF_LBUS_PARITY_1_LEN ,
+    6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+    SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_1_LEN );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_UNUSED_15_12 ,
+           14  , SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSADES_UNUSED_15_12 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_UNUSED_15_12_LEN ,
+           6   , SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSADES_UNUSED_15_12_LEN );
+REG64_FLD(
+    PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ILLEGAL_OPERATION_ATTEMPTED_2
+    , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+    SH_FLD_MSADES_ILLEGAL_OPERATION_ATTEMPTED_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_WRITE_FULL_PIB_2 ,
+           21  , SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSADES_WRITE_FULL_PIB_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_READ_EMPTY_PIB_2 ,
+           22  , SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSADES_READ_EMPTY_PIB_2 );
+REG64_FLD(
+    PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_LBUS_B_RAM_PARITY_DETECTED_2 ,
+    23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+    SH_FLD_MSADES_LBUS_B_RAM_PARITY_DETECTED_2 );
+REG64_FLD(
+    PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ADDRESS_OF_LBUS_PARITY_2 ,
+    24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+    SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_2 );
+REG64_FLD(
+    PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ADDRESS_OF_LBUS_PARITY_2_LEN ,
+    6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+    SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_2_LEN );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_1_0 , 30  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSBDES_UNUSED_1_0 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_1_0_LEN ,
+           2   , SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSBDES_UNUSED_1_0_LEN );
+
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_UNUSED_31_11 , 11  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSADI_UNUSED_31_11 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_UNUSED_31_11_LEN ,
+           10  , SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSADI_UNUSED_31_11_LEN );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_PIB_ERROR_2 , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSADI_PIB_ERROR_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_XUP_2     , 22  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSADI_XUP_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_PIB_PENDING_2 , 23  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSADI_PIB_PENDING_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_UNUSED_7_3 , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSADI_UNUSED_7_3 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_UNUSED_7_3_LEN , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSADI_UNUSED_7_3_LEN );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_PIB_ERROR_1 , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSADI_PIB_ERROR_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_XUP_1     , 30  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSADI_XUP_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_PIB_PENDING_1 , 31  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSADI_PIB_PENDING_1 );
+
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_31_28 ,
+           0   , SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSBDES_UNUSED_31_28 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_31_28_LEN ,
+           4   , SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSBDES_UNUSED_31_28_LEN );
+REG64_FLD(
+    PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_1
+    , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+    SH_FLD_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_WRITE_FULL_PIB_A_1
+           , 5   , SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSBDES_WRITE_FULL_PIB_A_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_READ_EMPTY_PIB_A_1
+           , 6   , SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSBDES_READ_EMPTY_PIB_A_1 );
+REG64_FLD(
+    PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_PIB_A_RAM_PARITY_DETECTED_1 ,
+    7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+    SH_FLD_MSBDES_PIB_A_RAM_PARITY_DETECTED_1 );
+REG64_FLD(
+    PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ADDRESS_OF_PIB_PARITY_1 ,
+    8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+    SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_1 );
+REG64_FLD(
+    PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ADDRESS_OF_PIB_PARITY_1_LEN ,
+    6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+    SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_1_LEN );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_17_12 ,
+           14  , SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSBDES_UNUSED_17_12 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_17_12_LEN ,
+           6   , SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSBDES_UNUSED_17_12_LEN );
+REG64_FLD(
+    PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_2
+    , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+    SH_FLD_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_WRITE_FULL_PIB_A_2
+           , 21  , SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSBDES_WRITE_FULL_PIB_A_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_READ_EMPTY_PIB_A_2
+           , 22  , SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSBDES_READ_EMPTY_PIB_A_2 );
+REG64_FLD(
+    PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_PIB_A_RAM_PARITY_DETECTED_2 ,
+    23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+    SH_FLD_MSBDES_PIB_A_RAM_PARITY_DETECTED_2 );
+REG64_FLD(
+    PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ADDRESS_OF_PIB_PARITY_2 ,
+    24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+    SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_2 );
+REG64_FLD(
+    PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ADDRESS_OF_PIB_PARITY_2_LEN ,
+    6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+    SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_2_LEN );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_1_0 , 30  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSBDES_UNUSED_1_0 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_1_0_LEN ,
+           2   , SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSBDES_UNUSED_1_0_LEN );
+
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_LBUS_PENDING_1 , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSBDI_LBUS_PENDING_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_LBUS_PENDING_2 , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSBDI_LBUS_PENDING_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_XDN_1     , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSBDI_XDN_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_XDN_2     , 27  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSBDI_XDN_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_LBUS_ERROR_1 , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSBDI_LBUS_ERROR_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_LBUS_ERROR_2 , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MSBDI_LBUS_ERROR_2 );
+
+REG64_FLD(
+    PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_LBUS_PENDING ,
+    24  , SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_MSBDIM1_ENABLE_LBUS_PENDING );
+REG64_FLD(
+    PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_LBUS_PENDING_2 ,
+    25  , SH_UNT_PERV     , SH_ACS_SCOM_RO  ,
+    SH_FLD_MSBDIM1_ENABLE_LBUS_PENDING_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_XDN ,
+           26  , SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_MSBDIM1_ENABLE_XDN );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_XDN_2 ,
+           27  , SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_MSBDIM1_ENABLE_XDN_2 );
+REG64_FLD(
+    PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_LBUS_ERROR , 28  ,
+    SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_MSBDIM1_ENABLE_LBUS_ERROR );
+REG64_FLD(
+    PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_LBUS_ERROR_2 ,
+    29  , SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_MSBDIM1_ENABLE_LBUS_ERROR_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_ABORT ,
+           30  , SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_MSBDIM1_ENABLE_ABORT );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_ABORT_2
+           , 31  , SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_MSBDIM1_ENABLE_ABORT_2 );
+
+REG64_FLD( PERV_MCAST_COMP_MASK_REG_MULTICAST_COMPARE_REGISTER     , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MULTICAST_COMPARE_REGISTER );
+REG64_FLD( PERV_MCAST_COMP_MASK_REG_MULTICAST_COMPARE_REGISTER_LEN , 64  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MULTICAST_COMPARE_REGISTER_LEN );
+
+REG64_FLD( PERV_MCAST_COMP_REG_MULTICAST_COMPARE_REGISTER          , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MULTICAST_COMPARE_REGISTER );
+REG64_FLD( PERV_MCAST_COMP_REG_MULTICAST_COMPARE_REGISTER_LEN      , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MULTICAST_COMPARE_REGISTER_LEN );
+
+REG64_FLD( PERV_MCAST_COMP_VAL_REG_MULTICAST_COMPARE_VALUE_REGISTER , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MULTICAST_COMPARE_VALUE_REGISTER );
+REG64_FLD( PERV_MCAST_COMP_VAL_REG_MULTICAST_COMPARE_VALUE_REGISTER_LEN , 64  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST_COMPARE_VALUE_REGISTER_LEN );
+
+REG64_FLD( PERV_MCAST_GRP_0_SLAVES_REG_GROUP                       , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_GROUP      );
+REG64_FLD( PERV_MCAST_GRP_0_SLAVES_REG_GROUP_LEN                   , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_GROUP_LEN  );
+
+REG64_FLD( PERV_MCAST_GRP_1_SLAVES_REG_GROUP                       , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_GROUP      );
+REG64_FLD( PERV_MCAST_GRP_1_SLAVES_REG_GROUP_LEN                   , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_GROUP_LEN  );
+
+REG64_FLD( PERV_MCAST_GRP_2_SLAVES_REG_GROUP                       , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_GROUP      );
+REG64_FLD( PERV_MCAST_GRP_2_SLAVES_REG_GROUP_LEN                   , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_GROUP_LEN  );
+
+REG64_FLD( PERV_MCAST_GRP_3_SLAVES_REG_GROUP                       , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_GROUP      );
+REG64_FLD( PERV_MCAST_GRP_3_SLAVES_REG_GROUP_LEN                   , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_GROUP_LEN  );
+
+REG64_FLD( PERV_MCAST_GRP_4_SLAVES_REG_GROUP                       , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_GROUP      );
+REG64_FLD( PERV_MCAST_GRP_4_SLAVES_REG_GROUP_LEN                   , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_GROUP_LEN  );
+
+REG64_FLD( PERV_MCAST_GRP_5_SLAVES_REG_GROUP                       , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_GROUP      );
+REG64_FLD( PERV_MCAST_GRP_5_SLAVES_REG_GROUP_LEN                   , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_GROUP_LEN  );
+
+REG64_FLD( PERV_MCAST_GRP_6_SLAVES_REG_GROUP                       , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_GROUP      );
+REG64_FLD( PERV_MCAST_GRP_6_SLAVES_REG_GROUP_LEN                   , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_GROUP_LEN  );
+
+REG64_FLD( PERV_MIB_XIICAC_ICACHE_TAG_ADDR                         , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_TAG_ADDR );
+REG64_FLD( PERV_MIB_XIICAC_ICACHE_TAG_ADDR_LEN                     , 27  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_TAG_ADDR_LEN );
+REG64_FLD( PERV_MIB_XIICAC_ICACHE_ERR                              , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_ERR );
+REG64_FLD( PERV_MIB_XIICAC_XISIB_PIB_IFETCH_PENDING                , 34  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_XISIB_PIB_IFETCH_PENDING );
+REG64_FLD( PERV_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING                , 35  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_XIMEM_MEM_IFETCH_PENDING );
+REG64_FLD( PERV_MIB_XIICAC_ICACHE_VALID                            , 36  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_VALID );
+REG64_FLD( PERV_MIB_XIICAC_ICACHE_VALID_LEN                        , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_ICACHE_VALID_LEN );
+
+REG64_FLD( PERV_MIB_XIMEM_MEM_ADDR                                 , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_MEM_ADDR   );
+REG64_FLD( PERV_MIB_XIMEM_MEM_ADDR_LEN                             , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_MEM_ADDR_LEN );
+REG64_FLD( PERV_MIB_XIMEM_MEM_R_NW                                 , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_MEM_R_NW   );
+REG64_FLD( PERV_MIB_XIMEM_MEM_BUSY                                 , 33  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_MEM_BUSY   );
+REG64_FLD( PERV_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING              , 34  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PERV_MIB_XIMEM_MEM_BYTE_ENABLE                          , 35  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_MEM_BYTE_ENABLE );
+REG64_FLD( PERV_MIB_XIMEM_MEM_BYTE_ENABLE_LEN                      , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_MEM_BYTE_ENABLE_LEN );
+REG64_FLD( PERV_MIB_XIMEM_MEM_LINE_MODE                            , 43  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_MEM_LINE_MODE );
+REG64_FLD( PERV_MIB_XIMEM_MEM_ERROR                                , 49  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_MEM_ERROR  );
+REG64_FLD( PERV_MIB_XIMEM_MEM_ERROR_LEN                            , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_MEM_ERROR_LEN );
+REG64_FLD( PERV_MIB_XIMEM_MEM_IFETCH_PENDING                       , 62  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_MEM_IFETCH_PENDING );
+REG64_FLD( PERV_MIB_XIMEM_MEM_DATAOP_PENDING                       , 63  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_MEM_DATAOP_PENDING );
+
+REG64_FLD( PERV_MIB_XISGB_STORE_ADDRESS                            , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_STORE_ADDRESS );
+REG64_FLD( PERV_MIB_XISGB_STORE_ADDRESS_LEN                        , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_STORE_ADDRESS_LEN );
+REG64_FLD( PERV_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING        , 35  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PERV_MIB_XISGB_SGB_BYTE_VALID                           , 36  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_SGB_BYTE_VALID );
+REG64_FLD( PERV_MIB_XISGB_SGB_BYTE_VALID_LEN                       , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_SGB_BYTE_VALID_LEN );
+REG64_FLD( PERV_MIB_XISGB_SGB_FLUSH_PENDING                        , 63  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_SGB_FLUSH_PENDING );
+
+REG64_FLD( PERV_MIB_XISIB_PIB_ADDR                                 , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_PIB_ADDR   );
+REG64_FLD( PERV_MIB_XISIB_PIB_ADDR_LEN                             , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_PIB_ADDR_LEN );
+REG64_FLD( PERV_MIB_XISIB_PIB_R_NW                                 , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_PIB_R_NW   );
+REG64_FLD( PERV_MIB_XISIB_PIB_BUSY                                 , 33  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_PIB_BUSY   );
+REG64_FLD( PERV_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING              , 34  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_PIB_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PERV_MIB_XISIB_PIB_RSP_INFO                             , 49  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_PIB_RSP_INFO );
+REG64_FLD( PERV_MIB_XISIB_PIB_RSP_INFO_LEN                         , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_PIB_RSP_INFO_LEN );
+REG64_FLD( PERV_MIB_XISIB_PIB_IFETCH_PENDING                       , 62  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_PIB_IFETCH_PENDING );
+REG64_FLD( PERV_MIB_XISIB_PIB_DATAOP_PENDING                       , 63  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_PIB_DATAOP_PENDING );
+
+REG64_FLD( PERV_1_MODE_REG_IN0                                     , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_IN0        );
+REG64_FLD( PERV_1_MODE_REG_IN1                                     , 1   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_IN1        );
+REG64_FLD( PERV_1_MODE_REG_IN2                                     , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_IN2        );
+REG64_FLD( PERV_1_MODE_REG_IN3                                     , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_IN3        );
+REG64_FLD( PERV_1_MODE_REG_IN4                                     , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_IN4        );
+REG64_FLD( PERV_1_MODE_REG_IN5                                     , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_IN5        );
+REG64_FLD( PERV_1_MODE_REG_IN6                                     , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_IN6        );
+REG64_FLD( PERV_1_MODE_REG_IN7                                     , 7   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_IN7        );
+REG64_FLD( PERV_1_MODE_REG_IN8                                     , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_IN8        );
+REG64_FLD( PERV_1_MODE_REG_IN9                                     , 9   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_IN9        );
+REG64_FLD( PERV_1_MODE_REG_IN10                                    , 10  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_IN10       );
+REG64_FLD( PERV_1_MODE_REG_IN11                                    , 11  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_IN11       );
+REG64_FLD( PERV_1_MODE_REG_IN                                      , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_IN         );
+REG64_FLD( PERV_1_MODE_REG_IN_LEN                                  , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_IN_LEN     );
+
+REG32_FLD( PERV_FSII2C_MODE_REGISTER_BIT_RATE_DIVISOR              , 0   ,
+           SH_UNT_PERV_FSII2C, SH_ACS_SCOM     , SH_FLD_BIT_RATE_DIVISOR );
+REG32_FLD( PERV_FSII2C_MODE_REGISTER_BIT_RATE_DIVISOR_LEN          , 16  ,
+           SH_UNT_PERV_FSII2C, SH_ACS_SCOM     , SH_FLD_BIT_RATE_DIVISOR_LEN );
+REG32_FLD( PERV_FSII2C_MODE_REGISTER_PORT_NUMBER                   , 16  ,
+           SH_UNT_PERV_FSII2C, SH_ACS_SCOM     , SH_FLD_PORT_NUMBER );
+REG32_FLD( PERV_FSII2C_MODE_REGISTER_PORT_NUMBER_LEN               , 6   ,
+           SH_UNT_PERV_FSII2C, SH_ACS_SCOM     , SH_FLD_PORT_NUMBER_LEN );
+REG32_FLD( PERV_FSII2C_MODE_REGISTER_CHKSW_I2C_BUSY                , 27  ,
+           SH_UNT_PERV_FSII2C, SH_ACS_SCOM     , SH_FLD_CHKSW_I2C_BUSY );
+REG32_FLD( PERV_FSII2C_MODE_REGISTER_FGAT                          , 28  ,
+           SH_UNT_PERV_FSII2C, SH_ACS_SCOM     , SH_FLD_FGAT       );
+REG32_FLD( PERV_FSII2C_MODE_REGISTER_DIAG                          , 29  ,
+           SH_UNT_PERV_FSII2C, SH_ACS_SCOM     , SH_FLD_DIAG       );
+REG32_FLD( PERV_FSII2C_MODE_REGISTER_PACING_ALLOW                  , 30  ,
+           SH_UNT_PERV_FSII2C, SH_ACS_SCOM     , SH_FLD_PACING_ALLOW );
+REG32_FLD( PERV_FSII2C_MODE_REGISTER_WRAP                          , 31  ,
+           SH_UNT_PERV_FSII2C, SH_ACS_SCOM     , SH_FLD_WRAP       );
+
+REG64_FLD( PERV_1_MULTICAST_GROUP_1_MULTICAST1                     , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_MULTICAST1 );
+REG64_FLD( PERV_1_MULTICAST_GROUP_1_MULTICAST1_LEN                 , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_MULTICAST1_LEN );
+
+REG64_FLD( PERV_1_MULTICAST_GROUP_2_MULTICAST2                     , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_MULTICAST2 );
+REG64_FLD( PERV_1_MULTICAST_GROUP_2_MULTICAST2_LEN                 , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_MULTICAST2_LEN );
+
+REG64_FLD( PERV_1_MULTICAST_GROUP_3_MULTICAST3                     , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_MULTICAST3 );
+REG64_FLD( PERV_1_MULTICAST_GROUP_3_MULTICAST3_LEN                 , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_MULTICAST3_LEN );
+
+REG64_FLD( PERV_1_MULTICAST_GROUP_4_MULTICAST4                     , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_MULTICAST4 );
+REG64_FLD( PERV_1_MULTICAST_GROUP_4_MULTICAST4_LEN                 , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_MULTICAST4_LEN );
+
+REG64_FLD( PERV_1_NET_CTRL0_CHIPLET_ENABLE                         , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_CHIPLET_ENABLE );
+REG64_FLD( PERV_1_NET_CTRL0_PCB_EP_RESET                           , 1   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_PCB_EP_RESET );
+REG64_FLD( PERV_1_NET_CTRL0_CLK_ASYNC_RESET                        , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_CLK_ASYNC_RESET );
+REG64_FLD( PERV_1_NET_CTRL0_PLL_TEST_EN                            , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_PLL_TEST_EN );
+REG64_FLD( PERV_1_NET_CTRL0_PLL_RESET                              , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_PLL_RESET  );
+REG64_FLD( PERV_1_NET_CTRL0_PLL_BYPASS                             , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_PLL_BYPASS );
+REG64_FLD( PERV_1_NET_CTRL0_VITAL_SCAN                             , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_VITAL_SCAN );
+REG64_FLD( PERV_1_NET_CTRL0_VITAL_SCAN_IN                          , 7   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_VITAL_SCAN_IN );
+REG64_FLD( PERV_1_NET_CTRL0_FLUSH_ALIGN_OVR                        , 9   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_FLUSH_ALIGN_OVR );
+REG64_FLD( PERV_1_NET_CTRL0_ARRAY_WRITE_ASSIST_EN                  , 10  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_ARRAY_WRITE_ASSIST_EN );
+REG64_FLD( PERV_1_NET_CTRL0_ACT_DIS                                , 11  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_ACT_DIS    );
+REG64_FLD( PERV_1_NET_CTRL0_MPW1                                   , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_MPW1       );
+REG64_FLD( PERV_1_NET_CTRL0_MPW2                                   , 13  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_MPW2       );
+REG64_FLD( PERV_1_NET_CTRL0_MPW3                                   , 14  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_MPW3       );
+REG64_FLD( PERV_1_NET_CTRL0_DELAY_LCLKR                            , 15  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_DELAY_LCLKR );
+REG64_FLD( PERV_1_NET_CTRL0_VITAL_THOLD                            , 16  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_VITAL_THOLD );
+REG64_FLD( PERV_1_NET_CTRL0_FLUSH_SCAN_N                           , 17  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_FLUSH_SCAN_N );
+REG64_FLD( PERV_1_NET_CTRL0_FENCE_EN                               , 18  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_FENCE_EN   );
+REG64_FLD( PERV_1_NET_CTRL0_RI_N                                   , 19  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_RI_N       );
+REG64_FLD( PERV_1_NET_CTRL0_DI1_N                                  , 20  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_DI1_N      );
+REG64_FLD( PERV_1_NET_CTRL0_DI2_N                                  , 21  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_DI2_N      );
+REG64_FLD( PERV_1_NET_CTRL0_TP_FENCE_PCB                           , 25  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_TP_FENCE_PCB );
+REG64_FLD( PERV_1_NET_CTRL0_LVLTRANS_FENCE                         , 26  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_LVLTRANS_FENCE );
+REG64_FLD( PERV_1_NET_CTRL0_L3_EDRAM_ENABLE                        , 27  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_L3_EDRAM_ENABLE );
+REG64_FLD( PERV_1_NET_CTRL0_HTB_INTEST                             , 28  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_HTB_INTEST );
+REG64_FLD( PERV_1_NET_CTRL0_HTB_EXTEST                             , 29  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_HTB_EXTEST );
+
+REG64_FLD( PERV_1_NET_CTRL1_PLL_CLKIN_SEL                          , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_PLL_CLKIN_SEL );
+REG64_FLD( PERV_1_NET_CTRL1_CLK_DIV_BYPASS_EN                      , 1   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_CLK_DIV_BYPASS_EN );
+REG64_FLD( PERV_1_NET_CTRL1_CLK_PDLY_BYPASS_EN                     , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PDLY_BYPASS_EN );
+REG64_FLD( PERV_1_NET_CTRL1_SB_STRENGTH                            , 16  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_SB_STRENGTH );
+REG64_FLD( PERV_1_NET_CTRL1_SB_STRENGTH_LEN                        , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_SB_STRENGTH_LEN );
+REG64_FLD( PERV_1_NET_CTRL1_CLK_PULSE_EN                           , 25  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_EN );
+REG64_FLD( PERV_1_NET_CTRL1_CLK_PULSE_MODE                         , 26  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_MODE );
+REG64_FLD( PERV_1_NET_CTRL1_CLK_PULSE_MODE_LEN                     , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_MODE_LEN );
+REG64_FLD( PERV_1_NET_CTRL1_RESCLK_DIS                             , 28  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_RESCLK_DIS );
+REG64_FLD( PERV_1_NET_CTRL1_CPM_CAL_SET                            , 29  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR, SH_FLD_CPM_CAL_SET );
+
+REG64_FLD( PERV_1_OPCG_ALIGN_INOP                                  , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_INOP       );
+REG64_FLD( PERV_1_OPCG_ALIGN_INOP_LEN                              , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_INOP_LEN   );
+REG64_FLD( PERV_1_OPCG_ALIGN_SNOP                                  , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SNOP       );
+REG64_FLD( PERV_1_OPCG_ALIGN_SNOP_LEN                              , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SNOP_LEN   );
+REG64_FLD( PERV_1_OPCG_ALIGN_ENOP                                  , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ENOP       );
+REG64_FLD( PERV_1_OPCG_ALIGN_ENOP_LEN                              , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ENOP_LEN   );
+REG64_FLD( PERV_1_OPCG_ALIGN_INOP_WAIT                             , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_INOP_WAIT  );
+REG64_FLD( PERV_1_OPCG_ALIGN_INOP_WAIT_LEN                         , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_INOP_WAIT_LEN );
+REG64_FLD( PERV_1_OPCG_ALIGN_SNOP_WAIT                             , 20  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SNOP_WAIT  );
+REG64_FLD( PERV_1_OPCG_ALIGN_SNOP_WAIT_LEN                         , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SNOP_WAIT_LEN );
+REG64_FLD( PERV_1_OPCG_ALIGN_ENOP_WAIT                             , 32  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ENOP_WAIT  );
+REG64_FLD( PERV_1_OPCG_ALIGN_ENOP_WAIT_LEN                         , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ENOP_WAIT_LEN );
+REG64_FLD( PERV_1_OPCG_ALIGN_INOP_FORCE_SG                         , 40  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_INOP_FORCE_SG );
+REG64_FLD( PERV_1_OPCG_ALIGN_SNOP_FORCE_SG                         , 41  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SNOP_FORCE_SG );
+REG64_FLD( PERV_1_OPCG_ALIGN_ENOP_FORCE_SG                         , 42  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ENOP_FORCE_SG );
+REG64_FLD( PERV_1_OPCG_ALIGN_NO_WAIT_ON_CLK_CMD                    , 43  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_NO_WAIT_ON_CLK_CMD );
+REG64_FLD( PERV_1_OPCG_ALIGN_SOURCE_SELECT                         , 44  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SOURCE_SELECT );
+REG64_FLD( PERV_1_OPCG_ALIGN_SOURCE_SELECT_LEN                     , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SOURCE_SELECT_LEN );
+REG64_FLD( PERV_1_OPCG_ALIGN_UNUSED46                              , 46  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNUSED46   );
+REG64_FLD( PERV_1_OPCG_ALIGN_SCAN_RATIO                            , 47  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SCAN_RATIO );
+REG64_FLD( PERV_1_OPCG_ALIGN_SCAN_RATIO_LEN                        , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SCAN_RATIO_LEN );
+REG64_FLD( PERV_1_OPCG_ALIGN_WAIT_CYCLES                           , 52  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_WAIT_CYCLES );
+REG64_FLD( PERV_1_OPCG_ALIGN_WAIT_CYCLES_LEN                       , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( PERV_1_OPCG_CAPT1_COUNT                                 , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_COUNT      );
+REG64_FLD( PERV_1_OPCG_CAPT1_COUNT_LEN                             , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_COUNT_LEN  );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_01                                , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_01     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_01_LEN                            , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_01_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_02                                , 9   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_02     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_02_LEN                            , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_02_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_03                                , 14  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_03     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_03_LEN                            , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_03_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_04                                , 19  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_04     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_04_LEN                            , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_04_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_05                                , 24  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_05     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_05_LEN                            , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_05_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_06                                , 29  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_06     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_06_LEN                            , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_06_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_07                                , 34  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_07     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_07_LEN                            , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_07_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_08                                , 39  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_08     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_08_LEN                            , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_08_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_09                                , 44  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_09     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_09_LEN                            , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_09_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_10                                , 49  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_10     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_10_LEN                            , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_10_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_11                                , 54  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_11     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_11_LEN                            , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_11_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_12                                , 59  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_12     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_12_LEN                            , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_12_LEN );
+
+REG64_FLD( PERV_1_OPCG_CAPT2_UNUSED                                , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNUSED     );
+REG64_FLD( PERV_1_OPCG_CAPT2_UNUSED_LEN                            , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNUSED_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_13_01EVEN                         , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_13_01EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_13_01EVEN_LEN                     , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_13_01EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_14_01ODD                          , 9   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_14_01ODD );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_14_01ODD_LEN                      , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_14_01ODD_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_15_02EVEN                         , 14  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_15_02EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_15_02EVEN_LEN                     , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_15_02EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_16_02ODD                          , 19  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_16_02ODD );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_16_02ODD_LEN                      , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_16_02ODD_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_17_03EVEN                         , 24  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_17_03EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_17_03EVEN_LEN                     , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_17_03EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_18_03ODD                          , 29  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_18_03ODD );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_18_03ODD_LEN                      , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_18_03ODD_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_19_04EVEN                         , 34  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_19_04EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_19_04EVEN_LEN                     , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_19_04EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_20_04ODD                          , 39  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_20_04ODD );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_20_04ODD_LEN                      , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_20_04ODD_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_21_05EVEN                         , 44  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_21_05EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_21_05EVEN_LEN                     , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_21_05EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_22_05ODD                          , 49  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_22_05ODD );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_22_05ODD_LEN                      , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_22_05ODD_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_23_06EVEN                         , 54  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_23_06EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_23_06EVEN_LEN                     , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_23_06EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_24_06ODD                          , 59  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_24_06ODD );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_24_06ODD_LEN                      , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_24_06ODD_LEN );
+
+REG64_FLD( PERV_1_OPCG_CAPT3_UNUSED                                , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNUSED     );
+REG64_FLD( PERV_1_OPCG_CAPT3_UNUSED_LEN                            , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNUSED_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_07EVEN                            , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_07EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_07EVEN_LEN                        , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_07EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_07ODD                             , 9   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_07ODD  );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_07ODD_LEN                         , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_07ODD_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_08EVEN                            , 14  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_08EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_08EVEN_LEN                        , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_08EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_08ODD                             , 19  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_08ODD  );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_08ODD_LEN                         , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_08ODD_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_09EVEN                            , 24  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_09EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_09EVEN_LEN                        , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_09EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_09ODD                             , 29  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_09ODD  );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_09ODD_LEN                         , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_09ODD_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_10EVEN                            , 34  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_10EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_10EVEN_LEN                        , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_10EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_10ODD                             , 39  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_10ODD  );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_10ODD_LEN                         , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_10ODD_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_11EVEN                            , 44  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_11EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_11EVEN_LEN                        , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_11EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_11ODD                             , 49  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_11ODD  );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_11ODD_LEN                         , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_11ODD_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_12EVEN                            , 54  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_12EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_12EVEN_LEN                        , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_12EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_12ODD                             , 59  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_12ODD  );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_12ODD_LEN                         , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SEQ_12ODD_LEN );
+
+REG64_FLD( PERV_1_OPCG_REG0_RUNN_MODE                              , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_RUNN_MODE  );
+REG64_FLD( PERV_1_OPCG_REG0_GO                                     , 1   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_GO         );
+REG64_FLD( PERV_1_OPCG_REG0_RUN_SCAN0                              , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_RUN_SCAN0  );
+REG64_FLD( PERV_1_OPCG_REG0_SCAN0_MODE                             , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SCAN0_MODE );
+REG64_FLD( PERV_1_OPCG_REG0_IN_SLAVE_MODE                          , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_IN_SLAVE_MODE );
+REG64_FLD( PERV_1_OPCG_REG0_IN_MASTER_MODE                         , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_IN_MASTER_MODE );
+REG64_FLD( PERV_1_OPCG_REG0_KEEP_MS_MODE                           , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_KEEP_MS_MODE );
+REG64_FLD( PERV_1_OPCG_REG0_UNUSED78                               , 7   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNUSED78   );
+REG64_FLD( PERV_1_OPCG_REG0_UNUSED78_LEN                           , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNUSED78_LEN );
+REG64_FLD( PERV_1_OPCG_REG0_RUN_CHIPLET_SCAN0                      , 9   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_RUN_CHIPLET_SCAN0 );
+REG64_FLD( PERV_1_OPCG_REG0_RUN_CHIPLET_SCAN0_NO_PLL               , 10  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_RUN_CHIPLET_SCAN0_NO_PLL );
+REG64_FLD( PERV_1_OPCG_REG0_RUN_ON_UPDATE_DR                       , 11  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_RUN_ON_UPDATE_DR );
+REG64_FLD( PERV_1_OPCG_REG0_RUN_ON_CAPTURE_DR                      , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_RUN_ON_CAPTURE_DR );
+REG64_FLD( PERV_1_OPCG_REG0_STOP_RUNN_ON_XSTOP                     , 13  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STOP_RUNN_ON_XSTOP );
+REG64_FLD( PERV_1_OPCG_REG0_STARTS_BIST                            , 14  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_STARTS_BIST );
+REG64_FLD( PERV_1_OPCG_REG0_UNUSED1520                             , 15  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNUSED1520 );
+REG64_FLD( PERV_1_OPCG_REG0_UNUSED1520_LEN                         , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNUSED1520_LEN );
+REG64_FLD( PERV_1_OPCG_REG0_LOOP_COUNT                             , 21  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_LOOP_COUNT );
+REG64_FLD( PERV_1_OPCG_REG0_LOOP_COUNT_LEN                         , 43  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_LOOP_COUNT_LEN );
+
+REG64_FLD( PERV_1_OPCG_REG1_SCAN_COUNT                             , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SCAN_COUNT );
+REG64_FLD( PERV_1_OPCG_REG1_SCAN_COUNT_LEN                         , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SCAN_COUNT_LEN );
+REG64_FLD( PERV_1_OPCG_REG1_MISR_A_VAL                             , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_MISR_A_VAL );
+REG64_FLD( PERV_1_OPCG_REG1_MISR_A_VAL_LEN                         , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_MISR_A_VAL_LEN );
+REG64_FLD( PERV_1_OPCG_REG1_MISR_B_VAL                             , 24  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_MISR_B_VAL );
+REG64_FLD( PERV_1_OPCG_REG1_MISR_B_VAL_LEN                         , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_MISR_B_VAL_LEN );
+REG64_FLD( PERV_1_OPCG_REG1_MISR_INIT_WAIT                         , 36  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_MISR_INIT_WAIT );
+REG64_FLD( PERV_1_OPCG_REG1_MISR_INIT_WAIT_LEN                     , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_MISR_INIT_WAIT_LEN );
+REG64_FLD( PERV_1_OPCG_REG1_SUPPRESS_EVEN_CLK                      , 48  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SUPPRESS_EVEN_CLK );
+REG64_FLD( PERV_1_OPCG_REG1_SCAN_CLK_USE_EVEN                      , 49  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SCAN_CLK_USE_EVEN );
+REG64_FLD( PERV_1_OPCG_REG1_UNUSED2                                , 50  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNUSED2    );
+REG64_FLD( PERV_1_OPCG_REG1_UNUSED2_LEN                            , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNUSED2_LEN );
+REG64_FLD( PERV_1_OPCG_REG1_USE_ARY_CLK_DURING_FILL                , 53  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_USE_ARY_CLK_DURING_FILL );
+REG64_FLD( PERV_1_OPCG_REG1_SG_HIGH_DURING_FILL                    , 54  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SG_HIGH_DURING_FILL );
+REG64_FLD( PERV_1_OPCG_REG1_RTIM_THOLD_FORCE                       , 55  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_RTIM_THOLD_FORCE );
+REG64_FLD( PERV_1_OPCG_REG1_LBIST_SKITTER_CTL                      , 56  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_LBIST_SKITTER_CTL );
+REG64_FLD( PERV_1_OPCG_REG1_MISR_MODE                              , 57  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_MISR_MODE  );
+REG64_FLD( PERV_1_OPCG_REG1_INFINITE_MODE                          , 58  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_INFINITE_MODE );
+REG64_FLD( PERV_1_OPCG_REG1_NSL_FILL_COUNT                         , 59  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_NSL_FILL_COUNT );
+REG64_FLD( PERV_1_OPCG_REG1_NSL_FILL_COUNT_LEN                     , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_NSL_FILL_COUNT_LEN );
+
+REG64_FLD( PERV_1_OPCG_REG2_GO2                                    , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_GO2        );
+REG64_FLD( PERV_1_OPCG_REG2_PRPG_WEIGHTING                         , 1   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PRPG_WEIGHTING );
+REG64_FLD( PERV_1_OPCG_REG2_PRPG_WEIGHTING_LEN                     , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PRPG_WEIGHTING_LEN );
+REG64_FLD( PERV_1_OPCG_REG2_PRPG_VALUE                             , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PRPG_VALUE );
+REG64_FLD( PERV_1_OPCG_REG2_PRPG_VALUE_LEN                         , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PRPG_VALUE_LEN );
+REG64_FLD( PERV_1_OPCG_REG2_PRPG_A_VAL                             , 16  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PRPG_A_VAL );
+REG64_FLD( PERV_1_OPCG_REG2_PRPG_A_VAL_LEN                         , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PRPG_A_VAL_LEN );
+REG64_FLD( PERV_1_OPCG_REG2_PRPG_B_VAL                             , 28  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PRPG_B_VAL );
+REG64_FLD( PERV_1_OPCG_REG2_PRPG_B_VAL_LEN                         , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PRPG_B_VAL_LEN );
+REG64_FLD( PERV_1_OPCG_REG2_PRPG_MODE                              , 40  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PRPG_MODE  );
+REG64_FLD( PERV_1_OPCG_REG2_UNUSED41_63                            , 41  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNUSED41_63 );
+REG64_FLD( PERV_1_OPCG_REG2_UNUSED41_63_LEN                        , 23  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNUSED41_63_LEN );
+
+REG32_FLD( PERV_PEEK4A0_FSI_A_MST_0_ACTUAL_ERROR                   , 4   ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_A_MST_0_ACTUAL_ERROR );
+REG32_FLD( PERV_PEEK4A0_FSI_A_MST_0_ACTUAL_ERROR_LEN               , 4   ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_A_MST_0_ACTUAL_ERROR_LEN );
+REG32_FLD( PERV_PEEK4A0_FSI_A_MST_0_PORT_0_ENABLE                  , 8   ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_A_MST_0_PORT_0_ENABLE );
+REG32_FLD( PERV_PEEK4A0_FSI_A_MST_0_PORT_1_ENABLE                  , 12  ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_A_MST_0_PORT_1_ENABLE );
+REG32_FLD( PERV_PEEK4A0_FSI_A_MST_0_PORT_2_ENABLE                  , 16  ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_A_MST_0_PORT_2_ENABLE );
+REG32_FLD( PERV_PEEK4A0_FSI_A_MST_0_PORT_3_ENABLE                  , 20  ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_A_MST_0_PORT_3_ENABLE );
+REG32_FLD( PERV_PEEK4A0_FSI_A_MST_0_PORT_4_ENABLE                  , 24  ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_A_MST_0_PORT_4_ENABLE );
+REG32_FLD( PERV_PEEK4A0_FSI_A_MST_0_PORT_5_ENABLE                  , 28  ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_A_MST_0_PORT_5_ENABLE );
+
+REG32_FLD( PERV_PEEK4A4_FSI_A_MST_0_PORT_6_ENABLE                  , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_A_MST_0_PORT_6_ENABLE );
+REG32_FLD( PERV_PEEK4A4_FSI_A_MST_0_PORT_7_ENABLE                  , 4   ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_A_MST_0_PORT_7_ENABLE );
+REG32_FLD( PERV_PEEK4A4_FSI_A_MST_1_ACTUAL_ERROR                   , 8   ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_A_MST_1_ACTUAL_ERROR );
+REG32_FLD( PERV_PEEK4A4_FSI_A_MST_1_ACTUAL_ERROR_LEN               , 4   ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_A_MST_1_ACTUAL_ERROR_LEN );
+REG32_FLD( PERV_PEEK4A4_FSI_A_MST_1_PORT_0_ENABLE                  , 12  ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_A_MST_1_PORT_0_ENABLE );
+REG32_FLD( PERV_PEEK4A4_FSI_A_MST_1_PORT_1_ENABLE                  , 16  ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_A_MST_1_PORT_1_ENABLE );
+REG32_FLD( PERV_PEEK4A4_FSI_A_MST_1_PORT_2_ENABLE                  , 20  ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_A_MST_1_PORT_2_ENABLE );
+REG32_FLD( PERV_PEEK4A4_FSI_A_MST_1_PORT_3_ENABLE                  , 24  ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_A_MST_1_PORT_3_ENABLE );
+REG32_FLD( PERV_PEEK4A4_FSI_A_MST_1_PORT_4_ENABLE                  , 28  ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_A_MST_1_PORT_4_ENABLE );
+
+REG32_FLD( PERV_PEEK4A8_FSI_B_MST_0_ACTUAL_ERROR                   , 4   ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_B_MST_0_ACTUAL_ERROR );
+REG32_FLD( PERV_PEEK4A8_FSI_B_MST_0_ACTUAL_ERROR_LEN               , 4   ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_B_MST_0_ACTUAL_ERROR_LEN );
+REG32_FLD( PERV_PEEK4A8_FSI_B_MST_0_PORT_0_ENABLE                  , 8   ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_B_MST_0_PORT_0_ENABLE );
+REG32_FLD( PERV_PEEK4A8_FSI_B_MST_0_PORT_1_ENABLE                  , 12  ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_B_MST_0_PORT_1_ENABLE );
+REG32_FLD( PERV_PEEK4A8_FSI_B_MST_0_PORT_2_ENABLE                  , 16  ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_B_MST_0_PORT_2_ENABLE );
+REG32_FLD( PERV_PEEK4A8_FSI_B_MST_0_PORT_3_ENABLE                  , 20  ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_B_MST_0_PORT_3_ENABLE );
+REG32_FLD( PERV_PEEK4A8_FSI_B_MST_0_PORT_4_ENABLE                  , 24  ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_B_MST_0_PORT_4_ENABLE );
+REG32_FLD( PERV_PEEK4A8_FSI_B_MST_0_PORT_5_ENABLE                  , 28  ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_B_MST_0_PORT_5_ENABLE );
+
+REG32_FLD( PERV_PEEK4AC_FSI_B_MST_0_PORT_6_ENABLE                  , 0   ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_B_MST_0_PORT_6_ENABLE );
+REG32_FLD( PERV_PEEK4AC_FSI_B_MST_0_PORT_7_ENABLE                  , 4   ,
+           SH_UNT_PERV     , SH_ACS_FSI      , SH_FLD_FSI_B_MST_0_PORT_7_ENABLE );
+
+REG64_FLD( PERV_PERV_CTRL0_TP_CHIPLET_EN_DC                        , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_CHIPLET_EN_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_PCB_EP_RESET_DC                      , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PCB_EP_RESET_DC );
+REG64_FLD( PERV_PERV_CTRL0_2_RESERVED                              , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_2_RESERVED );
+REG64_FLD( PERV_PERV_CTRL0_TP_PLL_TEST_EN_DC                       , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PLL_TEST_EN_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_PLLRST_DC                            , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PLLRST_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_PLLBYP_DC                            , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PLLBYP_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_VITL_SCAN_CLK_DC                     , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_VITL_SCAN_CLK_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_VITL_SCIN_DC                         , 7   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_VITL_SCIN_DC );
+REG64_FLD( PERV_PERV_CTRL0_8_RESERVED                              , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_8_RESERVED );
+REG64_FLD( PERV_PERV_CTRL0_TP_FLUSH_ALIGN_OVERWRITE                , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_FLUSH_ALIGN_OVERWRITE );
+REG64_FLD( PERV_PERV_CTRL0_TP_ARRAY_WRITE_ASSIST_EN_DC             , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_ARRAY_WRITE_ASSIST_EN_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_VITL_ACT_DIS_DC                      , 11  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_VITL_ACT_DIS_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_VITL_MPW1_DC_N                       , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_VITL_MPW1_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_TP_VITL_MPW2_DC_N                       , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_VITL_MPW2_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_TP_VITL_MPW3_DC_N                       , 14  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_VITL_MPW3_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_TP_VITL_DELAY_LCLKR_DC                  , 15  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_VITL_DELAY_LCLKR_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_VITL_CLKOFF_DC                       , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_VITL_CLKOFF_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_FLUSH_SCAN_DC_N                      , 17  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_FLUSH_SCAN_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_TP_FENCE_EN_DC                          , 18  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_FENCE_EN_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_RI_DC_N                              , 19  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_RI_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_TP_DI1_DC_N                             , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_DI1_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_TP_DI2_DC_N                             , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_DI2_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_22_RESERVED                             , 22  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_22_RESERVED );
+REG64_FLD( PERV_PERV_CTRL0_23_RESERVED                             , 23  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_23_RESERVED );
+REG64_FLD( PERV_PERV_CTRL0_24_RESERVED                             , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_24_RESERVED );
+REG64_FLD( PERV_PERV_CTRL0_TP_FENCE_PCB_DC                         , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_FENCE_PCB_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_LVLTRANS_FENCE_DC                    , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_LVLTRANS_FENCE_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_EDRAM_ENABLE_DC                      , 27  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_EDRAM_ENABLE_DC );
+REG64_FLD( PERV_PERV_CTRL0_28_RESERVED_FOR_HTB                     , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_28_RESERVED_FOR_HTB );
+REG64_FLD( PERV_PERV_CTRL0_29_RESERVED_FOR_HTB                     , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_29_RESERVED_FOR_HTB );
+REG64_FLD( PERV_PERV_CTRL0_30_RESERVED_FOR_HTB                     , 30  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_30_RESERVED_FOR_HTB );
+REG64_FLD( PERV_PERV_CTRL0_31_RESERVED_FOR_HTB                     , 31  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_31_RESERVED_FOR_HTB );
+
+REG64_FLD( PERV_PERV_CTRL1_UNUSED1                                 , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_UNUSED1    );
+REG64_FLD( PERV_PERV_CTRL1_UNUSED2                                 , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_UNUSED2    );
+REG64_FLD( PERV_PERV_CTRL1_UNUSED3                                 , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_UNUSED3    );
+REG64_FLD( PERV_PERV_CTRL1_3_RESERVED                              , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_3_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_4_RESERVED                              , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_4_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_5_RESERVED                              , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_5_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_6_RESERVED                              , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_6_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_7_RESERVED                              , 7   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_7_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_8_RESERVED                              , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_8_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_9_RESERVED                              , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_9_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_10_RESERVED                             , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_10_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_11_RESERVED                             , 11  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_11_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_12_RESERVED                             , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_12_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_13_RESERVED                             , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_13_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_14_RESERVED                             , 14  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_14_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_15_RESERVED                             , 15  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_15_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_TP_SEC_BUF_DRV_STRENGTH_DC              , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC );
+REG64_FLD( PERV_PERV_CTRL1_TP_SEC_BUF_DRV_STRENGTH_DC_LEN          , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC_LEN );
+REG64_FLD( PERV_PERV_CTRL1_20_RESERVED                             , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_20_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_21_RESERVED                             , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_21_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_22_RESERVED                             , 22  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_22_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_23_RESERVED                             , 23  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_23_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_24_RESERVED                             , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_24_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_TP_CLK_PULSE_ENABLE_DC                  , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_CLK_PULSE_ENABLE_DC );
+REG64_FLD( PERV_PERV_CTRL1_TP_CLK_PULSE_MODE_DC                    , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_CLK_PULSE_MODE_DC );
+REG64_FLD( PERV_PERV_CTRL1_TP_CLK_PULSE_MODE_DC_LEN                , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_CLK_PULSE_MODE_DC_LEN );
+REG64_FLD( PERV_PERV_CTRL1_TP_RESCLK_DIS_DC                        , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_RESCLK_DIS_DC );
+REG64_FLD( PERV_PERV_CTRL1_TP_CPM_CAL_SET                          , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_CPM_CAL_SET );
+REG64_FLD( PERV_PERV_CTRL1_30_RESERVED                             , 30  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_30_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_TP_PCB_PM_MUX_SEL_DC                    , 31  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PCB_PM_MUX_SEL_DC );
+
+REG64_FLD( PERV_PPE_XIDBGPRO_NULL_MSR_SIBRC                        , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PERV_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN                    , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PERV_PPE_XIDBGPRO_NULL_MSR_WE                           , 14  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_NULL_MSR_WE );
+REG64_FLD( PERV_PPE_XIDBGPRO_NULL_MSR_LP                           , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_NULL_MSR_LP );
+
+REG64_FLD( PERV_PPE_XIRAMDBG_NULL_MSR_SIBRC                        , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PERV_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN                    , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PERV_PPE_XIRAMDBG_NULL_MSR_WE                           , 14  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_NULL_MSR_WE );
+REG64_FLD( PERV_PPE_XIRAMDBG_NULL_MSR_LP                           , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_NULL_MSR_LP );
+REG64_FLD( PERV_PPE_XIRAMDBG_XIRAMRA_SPRG0                         , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( PERV_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN                     , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PERV_PPE_XIRAMEDR_XIRAMGA_IR                            , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_XIRAMGA_IR );
+REG64_FLD( PERV_PPE_XIRAMEDR_XIRAMGA_IR_LEN                        , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_XIRAMGA_IR_LEN );
+REG64_FLD( PERV_PPE_XIRAMEDR_EDR                                   , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_EDR        );
+REG64_FLD( PERV_PPE_XIRAMEDR_EDR_LEN                               , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_EDR_LEN    );
+
+REG64_FLD( PERV_PPE_XIRAMGA_IR                                     , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_IR         );
+REG64_FLD( PERV_PPE_XIRAMGA_IR_LEN                                 , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_IR_LEN     );
+REG64_FLD( PERV_PPE_XIRAMGA_XIRAMRA_SPRG0                          , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( PERV_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN                      , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PERV_PPE_XIRAMRA_XIXCR_XCR                              , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_XIXCR_XCR  );
+REG64_FLD( PERV_PPE_XIRAMRA_XIXCR_XCR_LEN                          , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_XIXCR_XCR_LEN );
+REG64_FLD( PERV_PPE_XIRAMRA_SPRG0                                  , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_SPRG0      );
+REG64_FLD( PERV_PPE_XIRAMRA_SPRG0_LEN                              , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_SPRG0_LEN  );
+
+REG64_FLD( PERV_PPE_XIXCR_XCR                                      , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_XCR        );
+REG64_FLD( PERV_PPE_XIXCR_XCR_LEN                                  , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_XCR_LEN    );
+
+REG64_FLD( PERV_1_PRE_COUNTER_REG_COUNTER                          , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_COUNTER    );
+REG64_FLD( PERV_1_PRE_COUNTER_REG_COUNTER_LEN                      , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_COUNTER_LEN );
+
+REG64_FLD( PERV_1_PROTECT_MODE_REG_READ_ENABLE                     , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_READ_ENABLE );
+REG64_FLD( PERV_1_PROTECT_MODE_REG_WRITE_ENABLE                    , 1   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_WRITE_ENABLE );
+
+REG64_FLD( PERV_PRV_DBG_PIB_RESET                                  , 0   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_PIB_RESET  );
+REG64_FLD( PERV_PRV_DBG_RESERVED_15                                , 1   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_15 );
+REG64_FLD( PERV_PRV_DBG_RESERVED_16                                , 2   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_16 );
+REG64_FLD( PERV_PRV_DBG_RESERVED_16_LEN                            , 4   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_16_LEN );
+REG64_FLD( PERV_PRV_DBG_RESERVED_17                                , 6   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_17 );
+REG64_FLD( PERV_PRV_DBG_RESERVED_17_LEN                            , 3   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_RESERVED_17_LEN );
+
+REG32_FLD( PERV_FSISHIFT_READ_BUFFER_REG                           , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REG        );
+REG32_FLD( PERV_FSISHIFT_READ_BUFFER_REG_LEN                       , 32  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REG_LEN    );
+
+REG64_FLD( PERV_REC_ACK_REG_RECEIVE_ACKNOWLEDGE_REGISTER           , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_RECEIVE_ACKNOWLEDGE_REGISTER );
+REG64_FLD( PERV_REC_ACK_REG_RECEIVE_ACKNOWLEDGE_REGISTER_LEN       , 64  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_RECEIVE_ACKNOWLEDGE_REGISTER_LEN );
+
+REG64_FLD( PERV_REC_ERR_REG0_MASTER_RESPONSE_BIT                   , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MASTER_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_MASTER_ERROR_CODE                     , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MASTER_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_MASTER_ERROR_CODE_LEN                 , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MASTER_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE1_RESPONSE_BIT                   , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE1_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE1_ERROR_CODE                     , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE1_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE1_ERROR_CODE_LEN                 , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE1_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE2_RESPONSE_BIT                   , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE2_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE2_ERROR_CODE                     , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE2_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE2_ERROR_CODE_LEN                 , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE2_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE3_RESPONSE_BIT                   , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE3_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE3_ERROR_CODE                     , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE3_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE3_ERROR_CODE_LEN                 , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE3_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE4_RESPONSE_BIT                   , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE4_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE4_ERROR_CODE                     , 17  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE4_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE4_ERROR_CODE_LEN                 , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE4_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE5_RESPONSE_BIT                   , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE5_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE5_ERROR_CODE                     , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE5_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE5_ERROR_CODE_LEN                 , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE5_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE6_RESPONSE_BIT                   , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE6_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE6_ERROR_CODE                     , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE6_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE6_ERROR_CODE_LEN                 , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE6_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE7_RESPONSE_BIT                   , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE7_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE7_ERROR_CODE                     , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE7_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE7_ERROR_CODE_LEN                 , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE7_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE8_RESPONSE_BIT                   , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE8_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE8_ERROR_CODE                     , 33  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE8_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE8_ERROR_CODE_LEN                 , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE8_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE9_RESPONSE_BIT                   , 36  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE9_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE9_ERROR_CODE                     , 37  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE9_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE9_ERROR_CODE_LEN                 , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE9_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE10_RESPONSE_BIT                  , 40  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE10_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE10_ERROR_CODE                    , 41  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE10_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE10_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE10_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE11_RESPONSE_BIT                  , 44  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE11_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE11_ERROR_CODE                    , 45  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE11_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE11_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE11_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE12_RESPONSE_BIT                  , 48  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE12_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE12_ERROR_CODE                    , 49  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE12_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE12_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE12_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE13_RESPONSE_BIT                  , 52  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE13_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE13_ERROR_CODE                    , 53  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE13_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE13_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE13_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE14_RESPONSE_BIT                  , 56  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE14_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE14_ERROR_CODE                    , 57  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE14_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE14_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE14_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE15_RESPONSE_BIT                  , 60  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE15_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE15_ERROR_CODE                    , 61  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE15_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE15_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE15_ERROR_CODE_LEN );
+
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE16_RESPONSE_BIT                  , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE16_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE16_ERROR_CODE                    , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE16_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE16_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE16_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE17_RESPONSE_BIT                  , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE17_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE17_ERROR_CODE                    , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE17_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE17_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE17_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE18_RESPONSE_BIT                  , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE18_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE18_ERROR_CODE                    , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE18_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE18_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE18_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE19_RESPONSE_BIT                  , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE19_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE19_ERROR_CODE                    , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE19_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE19_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE19_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE20_RESPONSE_BIT                  , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE20_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE20_ERROR_CODE                    , 17  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE20_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE20_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE20_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE21_RESPONSE_BIT                  , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE21_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE21_ERROR_CODE                    , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE21_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE21_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE21_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE22_RESPONSE_BIT                  , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE22_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE22_ERROR_CODE                    , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE22_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE22_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE22_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE23_RESPONSE_BIT                  , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE23_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE23_ERROR_CODE                    , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE23_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE23_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE23_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE24_RESPONSE_BIT                  , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE24_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE24_ERROR_CODE                    , 33  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE24_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE24_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE24_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE25_RESPONSE_BIT                  , 36  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE25_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE25_ERROR_CODE                    , 37  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE25_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE25_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE25_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE26_RESPONSE_BIT                  , 40  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE26_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE26_ERROR_CODE                    , 41  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE26_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE26_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE26_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE27_RESPONSE_BIT                  , 44  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE27_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE27_ERROR_CODE                    , 45  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE27_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE27_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE27_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE28_RESPONSE_BIT                  , 48  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE28_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE28_ERROR_CODE                    , 49  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE28_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE28_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE28_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE29_RESPONSE_BIT                  , 52  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE29_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE29_ERROR_CODE                    , 53  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE29_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE29_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE29_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE30_RESPONSE_BIT                  , 56  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE30_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE30_ERROR_CODE                    , 57  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE30_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE30_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE30_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE31_RESPONSE_BIT                  , 60  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE31_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE31_ERROR_CODE                    , 61  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE31_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE31_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE31_ERROR_CODE_LEN );
+
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE32_RESPONSE_BIT                  , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE32_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE32_ERROR_CODE                    , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE32_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE32_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE32_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE33_RESPONSE_BIT                  , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE33_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE33_ERROR_CODE                    , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE33_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE33_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE33_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE34_RESPONSE_BIT                  , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE34_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE34_ERROR_CODE                    , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE34_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE34_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE34_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE35_RESPONSE_BIT                  , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE35_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE35_ERROR_CODE                    , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE35_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE35_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE35_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE36_RESPONSE_BIT                  , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE36_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE36_ERROR_CODE                    , 17  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE36_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE36_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE36_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE37_RESPONSE_BIT                  , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE37_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE37_ERROR_CODE                    , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE37_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE37_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE37_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE38_RESPONSE_BIT                  , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE38_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE38_ERROR_CODE                    , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE38_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE38_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE38_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE39_RESPONSE_BIT                  , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE39_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE39_ERROR_CODE                    , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE39_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE39_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE39_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE40_RESPONSE_BIT                  , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE40_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE40_ERROR_CODE                    , 33  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE40_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE40_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE40_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE41_RESPONSE_BIT                  , 36  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE41_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE41_ERROR_CODE                    , 37  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE41_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE41_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE41_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE42_RESPONSE_BIT                  , 40  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE42_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE42_ERROR_CODE                    , 41  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE42_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE42_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE42_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE43_RESPONSE_BIT                  , 44  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE43_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE43_ERROR_CODE                    , 45  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE43_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE43_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE43_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE44_RESPONSE_BIT                  , 48  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE44_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE44_ERROR_CODE                    , 49  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE44_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE44_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE44_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE45_RESPONSE_BIT                  , 52  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE45_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE45_ERROR_CODE                    , 53  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE45_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE45_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE45_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE46_RESPONSE_BIT                  , 56  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE46_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE46_ERROR_CODE                    , 57  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE46_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE46_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE46_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE47_RESPONSE_BIT                  , 60  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE47_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE47_ERROR_CODE                    , 61  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE47_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE47_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE47_ERROR_CODE_LEN );
+
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE48_RESPONSE_BIT                  , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE48_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE48_ERROR_CODE                    , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE48_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE48_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE48_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE49_RESPONSE_BIT                  , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE49_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE49_ERROR_CODE                    , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE49_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE49_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE49_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE50_RESPONSE_BIT                  , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE50_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE50_ERROR_CODE                    , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE50_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE50_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE50_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE51_RESPONSE_BIT                  , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE51_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE51_ERROR_CODE                    , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE51_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE51_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE51_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE52_RESPONSE_BIT                  , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE52_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE52_ERROR_CODE                    , 17  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE52_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE52_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE52_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE53_RESPONSE_BIT                  , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE53_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE53_ERROR_CODE                    , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE53_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE53_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE53_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE54_RESPONSE_BIT                  , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE54_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE54_ERROR_CODE                    , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE54_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE54_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE54_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE55_RESPONSE_BIT                  , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE55_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE55_ERROR_CODE                    , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE55_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE55_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE55_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE56_RESPONSE_BIT                  , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE56_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE56_ERROR_CODE                    , 33  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE56_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE56_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE56_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE57_RESPONSE_BIT                  , 36  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE57_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE57_ERROR_CODE                    , 37  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE57_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE57_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE57_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE58_RESPONSE_BIT                  , 40  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE58_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE58_ERROR_CODE                    , 41  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE58_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE58_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE58_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE59_RESPONSE_BIT                  , 44  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE59_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE59_ERROR_CODE                    , 45  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE59_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE59_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE59_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE60_RESPONSE_BIT                  , 48  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE60_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE60_ERROR_CODE                    , 49  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE60_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE60_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE60_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE61_RESPONSE_BIT                  , 52  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE61_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE61_ERROR_CODE                    , 53  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE61_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE61_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE61_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE62_RESPONSE_BIT                  , 56  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE62_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE62_ERROR_CODE                    , 57  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE62_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE62_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE62_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE63_RESPONSE_BIT                  , 60  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE63_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE63_ERROR_CODE                    , 61  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE63_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE63_ERROR_CODE_LEN                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SLAVE63_ERROR_CODE_LEN );
+
+REG64_FLD( PERV_RESET_REG_PCB                                      , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_PCB        );
+REG64_FLD( PERV_RESET_REG_ENDPOINTS                                , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_ENDPOINTS  );
+REG64_FLD( PERV_RESET_REG_TIMEOUT_EN                               , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TIMEOUT_EN );
+
+REG64_FLD( PERV_ROOT_CTRL0_TPFSI_SBE_FENCE_VTLIO_DC                , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_SBE_FENCE_VTLIO_DC );
+REG64_FLD( PERV_ROOT_CTRL0_TPFSI_TP_FENCE_VTLIO_DC                 , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_TP_FENCE_VTLIO_DC );
+REG64_FLD( PERV_ROOT_CTRL0_TPFSI_TPI2C_BUS_FENCE_DC                , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_TPI2C_BUS_FENCE_DC );
+REG64_FLD( PERV_ROOT_CTRL0_TPCFSI_OPB_SW0_FENCE_DC                 , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPCFSI_OPB_SW0_FENCE_DC );
+REG64_FLD( PERV_ROOT_CTRL0_TPCFSI_OPB_SW0_FENCE_DC_LEN             , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPCFSI_OPB_SW0_FENCE_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL0_TPCFSI_OPB_SW1_FENCE_DC                 , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPCFSI_OPB_SW1_FENCE_DC );
+REG64_FLD( PERV_ROOT_CTRL0_TPCFSI_OPB_SW1_FENCE_DC_LEN             , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPCFSI_OPB_SW1_FENCE_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL0_FENCE1_DC                               , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_FENCE1_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_FENCE2_DC                               , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_FENCE2_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_FENCE3_DC                               , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_FENCE3_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_FENCE4_DC                               , 11  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_FENCE4_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_FENCE5_DC                               , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_FENCE5_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_FENCE6_DC                               , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_FENCE6_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_SPARE_FENCE_CONTROL                     , 14  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SPARE_FENCE_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_VDD2VIO_LVL_FENCE_DC                    , 15  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_VDD2VIO_LVL_FENCE_DC );
+REG64_FLD( PERV_ROOT_CTRL0_PIB2PCB_DC                              , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_PIB2PCB_DC );
+REG64_FLD( PERV_ROOT_CTRL0_OOB_MUX                                 , 17  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_OOB_MUX    );
+REG64_FLD( PERV_ROOT_CTRL0_18_SPARE_MUX_CONTROL                    , 18  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_18_SPARE_MUX_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_19_SPARE_MUX_CONTROL                    , 19  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_19_SPARE_MUX_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_FSI_CC_VSB_CBS_REQ                      , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_FSI_CC_VSB_CBS_REQ );
+REG64_FLD( PERV_ROOT_CTRL0_FSI_CC_VSB_CBS_CMD                      , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_FSI_CC_VSB_CBS_CMD );
+REG64_FLD( PERV_ROOT_CTRL0_FSI_CC_VSB_CBS_CMD_LEN                  , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_FSI_CC_VSB_CBS_CMD_LEN );
+REG64_FLD( PERV_ROOT_CTRL0_24_SPARE_CBS_CONTROL                    , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_24_SPARE_CBS_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_25_SPARE_CBS_CONTROL                    , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_25_SPARE_CBS_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_26_SPARE_CBS_CONTROL                    , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_26_SPARE_CBS_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_27_SPARE_CBS_CONTROL                    , 27  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_27_SPARE_CBS_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_28_SPARE_RESET                          , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_28_SPARE_RESET );
+REG64_FLD( PERV_ROOT_CTRL0_29_SPARE_RESET                          , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_29_SPARE_RESET );
+REG64_FLD( PERV_ROOT_CTRL0_PCB_RESET_DC                            , 30  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_PCB_RESET_DC );
+REG64_FLD( PERV_ROOT_CTRL0_GLOBAL_EP_RESET_DC                      , 31  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_GLOBAL_EP_RESET_DC );
+
+REG64_FLD( PERV_ROOT_CTRL1_TP_PROBE0_SEL_DC                        , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PROBE0_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL1_TP_PROBE0_SEL_DC_LEN                    , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PROBE0_SEL_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL1_TP_PROBE1_SEL_DC                        , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PROBE1_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL1_TP_PROBE1_SEL_DC_LEN                    , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PROBE1_SEL_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL1_TP_PROBE_MESH_SEL_DC                    , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PROBE_MESH_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL1_TP_PROBE_DRV_EN_DC                      , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PROBE_DRV_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL1_TP_PROBE_HIGHDRIVE_DC                   , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PROBE_HIGHDRIVE_DC );
+REG64_FLD( PERV_ROOT_CTRL1_TP_FSI_PROBE_SEL_DC                     , 11  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_FSI_PROBE_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL1_TP_FSI_PROBE_SEL_DC_LEN                 , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_FSI_PROBE_SEL_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL1_13_SPARE_PROBE                          , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_13_SPARE_PROBE );
+REG64_FLD( PERV_ROOT_CTRL1_14_SPARE_PROBE                          , 14  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_14_SPARE_PROBE );
+REG64_FLD( PERV_ROOT_CTRL1_15_SPARE_PROBE                          , 15  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_15_SPARE_PROBE );
+REG64_FLD( PERV_ROOT_CTRL1_TP_IDDQ_DC                              , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_IDDQ_DC );
+REG64_FLD( PERV_ROOT_CTRL1_SPARE_RI_CONTROL                        , 17  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SPARE_RI_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL1_SPARE_DI_CONTROL                        , 18  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SPARE_DI_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL1_TP_RI_DC_B                              , 19  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_RI_DC_B );
+REG64_FLD( PERV_ROOT_CTRL1_TP_DI1_DC_B                             , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_DI1_DC_B );
+REG64_FLD( PERV_ROOT_CTRL1_TP_DI2_DC_B                             , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_DI2_DC_B );
+REG64_FLD( PERV_ROOT_CTRL1_22_SPARE_TEST                           , 22  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_22_SPARE_TEST );
+REG64_FLD( PERV_ROOT_CTRL1_23_SPARE_TEST                           , 23  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_23_SPARE_TEST );
+REG64_FLD( PERV_ROOT_CTRL1_TP_TEST_BURNIN_MODE_DC                  , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_TEST_BURNIN_MODE_DC );
+REG64_FLD( PERV_ROOT_CTRL1_TPFSI_ARRAY_SET_VBL_TO_VDD_DC           , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_ARRAY_SET_VBL_TO_VDD_DC );
+REG64_FLD( PERV_ROOT_CTRL1_TPFSI_TP_LOWFREQTEST_REFCLK_DC          , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_TP_LOWFREQTEST_REFCLK_DC );
+REG64_FLD( PERV_ROOT_CTRL1_TP_GLBCK_MEM_TESTCLK_SEL_DC             , 27  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_GLBCK_MEM_TESTCLK_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL1_28_SPARE_TEST_CONTROL                   , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_28_SPARE_TEST_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL1_29_SPARE_TEST_CONTROL                   , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_29_SPARE_TEST_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL1_30_SPARE_TEST_CONTROL                   , 30  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_30_SPARE_TEST_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL1_31_SPARE_TEST_CONTROL                   , 31  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_31_SPARE_TEST_CONTROL );
+
+REG64_FLD( PERV_ROOT_CTRL2_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC        , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL2_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC    , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC );
+REG64_FLD( PERV_ROOT_CTRL2_TPFSI_TP_VSB_DBG_PCB_TYPE_PAR_DIS_DC    , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_VSB_DBG_PCB_TYPE_PAR_DIS_DC );
+REG64_FLD( PERV_ROOT_CTRL2_TPFSI_TP_VSB_PCB_GSD_LATCHED_MODE_DC    , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_VSB_PCB_GSD_LATCHED_MODE_DC );
+REG64_FLD( PERV_ROOT_CTRL2_TP_PIB_VSB_DISABLE_PARITY_DC            , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PIB_VSB_DISABLE_PARITY_DC );
+REG64_FLD( PERV_ROOT_CTRL2_TP_PIB_TRACE_MODE_DATA_DC               , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PIB_TRACE_MODE_DATA_DC );
+REG64_FLD( PERV_ROOT_CTRL2_TP_PIB_TRACE_MUX_SEL                    , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PIB_TRACE_MUX_SEL );
+REG64_FLD( PERV_ROOT_CTRL2_TP_PIB_TRACE_MUX_SEL_LEN                , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PIB_TRACE_MUX_SEL_LEN );
+REG64_FLD( PERV_ROOT_CTRL2_TP_GPIO_PIB_TIMEOUT                     , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_GPIO_PIB_TIMEOUT );
+REG64_FLD( PERV_ROOT_CTRL2_TP_GPIO_PIB_TIMEOUT_LEN                 , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_GPIO_PIB_TIMEOUT_LEN );
+REG64_FLD( PERV_ROOT_CTRL2_SPARE_PIB_CONTROL                       , 11  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SPARE_PIB_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL2_TPCFSI_OPB_SW_RESET_DC                  , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPCFSI_OPB_SW_RESET_DC );
+REG64_FLD( PERV_ROOT_CTRL2_13_SPARE_OPB_CONTROL                    , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_13_SPARE_OPB_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL2_14_SPARE_OPB_CONTROL                    , 14  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_14_SPARE_OPB_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL2_15_SPARE_OPB_CONTROL                    , 15  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_15_SPARE_OPB_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL2_16_FREE_USAGE                           , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_16_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_TP_GLBCK_VSB_NEST_VREGDLY_SHUTOFF_DC    , 17  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GLBCK_VSB_NEST_VREGDLY_SHUTOFF_DC );
+REG64_FLD( PERV_ROOT_CTRL2_TPFSI_TP_PFET_FORCE_OFF_DC              , 18  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_TP_PFET_FORCE_OFF_DC );
+REG64_FLD( PERV_ROOT_CTRL2_TPFSI_TP_PFET_OVERRIDE_ON_DC_N          , 19  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_TP_PFET_OVERRIDE_ON_DC_N );
+REG64_FLD( PERV_ROOT_CTRL2_20_FREE_USAGE                           , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_20_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_21_FREE_USAGE                           , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_21_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_22_FREE_USAGE                           , 22  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_22_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_23_FREE_USAGE                           , 23  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_23_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_24_FREE_USAGE                           , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_24_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_25_FREE_USAGE                           , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_25_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_26_FREE_USAGE                           , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_26_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_27_FREE_USAGE                           , 27  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_27_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_28_FREE_USAGE                           , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_28_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_29_FREE_USAGE                           , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_29_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_30_FREE_USAGE                           , 30  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_30_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_31_FREE_USAGE                           , 31  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_31_FREE_USAGE );
+
+REG64_FLD( PERV_ROOT_CTRL3_OSCSWITCH_CNTL0_DC                      , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_OSCSWITCH_CNTL0_DC );
+REG64_FLD( PERV_ROOT_CTRL3_OSCSWITCH_CNTL0_DC_LEN                  , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_OSCSWITCH_CNTL0_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL3_TP_GLBCK_VSB_PCIESW_USEOSC_DC           , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC );
+REG64_FLD( PERV_ROOT_CTRL3_TP_GLBCK_VSB_PCIESW_USEOSC_DC_LEN       , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL3_TP_GLBCK_VSB_PCIESW_TWEAK_DC            , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC );
+REG64_FLD( PERV_ROOT_CTRL3_TP_GLBCK_VSB_PCIESW_TWEAK_DC_LEN        , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL3_OSCSWITCH_CNTL1_DC                      , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_OSCSWITCH_CNTL1_DC );
+REG64_FLD( PERV_ROOT_CTRL3_OSCSWITCH_CNTL1_DC_LEN                  , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_OSCSWITCH_CNTL1_DC_LEN );
+
+REG64_FLD( PERV_ROOT_CTRL4_TP_OSCSWITCH_VSB                        , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_OSCSWITCH_VSB );
+REG64_FLD( PERV_ROOT_CTRL4_TP_OSCSWITCH_VSB_LEN                    , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_OSCSWITCH_VSB_LEN );
+
+REG64_FLD( PERV_ROOT_CTRL5_TPFSI_OSCSW_ERRINJ0_DC                  , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_OSCSW_ERRINJ0_DC );
+REG64_FLD( PERV_ROOT_CTRL5_TPFSI_OSCSW_ERRINJ0_DC_LEN              , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_OSCSW_ERRINJ0_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL5_TPFSI_OSCSW_ERRINJ1_DC                  , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_OSCSW_ERRINJ1_DC );
+REG64_FLD( PERV_ROOT_CTRL5_TPFSI_OSCSW_ERRINJ1_DC_LEN              , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_OSCSW_ERRINJ1_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL5_TPFSI_OSCSW_TWEAK_DC                    , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_OSCSW_TWEAK_DC );
+REG64_FLD( PERV_ROOT_CTRL5_TPFSI_OSCSW_TWEAK_DC_LEN                , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_OSCSW_TWEAK_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL5_TPFSI_OSCSW_SKEW_ADJUST_DC              , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC );
+REG64_FLD( PERV_ROOT_CTRL5_TPFSI_OSCSW_SKEW_ADJUST_DC_LEN          , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL5_TPFSI_OSCSW_SNS_CONTENT_SEL_DC          , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL5_TPFSI_OSCSW_SNS_CONTENT_SEL_DC_LEN      , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL5_15_SPARE_OSC                            , 15  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_15_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_16_SPARE_OSC                            , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_16_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_17_SPARE_OSC                            , 17  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_17_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_18_SPARE_OSC                            , 18  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_18_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_19_SPARE_OSC                            , 19  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_19_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_20_SPARE_OSC                            , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_20_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_21_SPARE_OSC                            , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_21_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_22_SPARE_OSC                            , 22  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_22_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_23_SPARE_OSC                            , 23  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_23_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_24_SPARE_OSC                            , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_24_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_25_SPARE_OSC                            , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_25_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_26_SPARE_OSC                            , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_26_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_27_SPARE_OSC                            , 27  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_27_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_28_SPARE_OSC                            , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_28_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_29_SPARE_OSC                            , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_29_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_30_SPARE_OSC                            , 30  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_30_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_31_SPARE_OSC                            , 31  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_31_SPARE_OSC );
+
+REG64_FLD( PERV_ROOT_CTRL6_TP_PLLREFCLK_RCVR_TERM_DC               , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC );
+REG64_FLD( PERV_ROOT_CTRL6_TP_PLLREFCLK_RCVR_TERM_DC_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL6_TP_PCIREFCLK_RCVR_TERM_DC               , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC );
+REG64_FLD( PERV_ROOT_CTRL6_TP_PCIREFCLK_RCVR_TERM_DC_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL6_REFCLK_0_TERM_DIS_DC                    , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_REFCLK_0_TERM_DIS_DC );
+REG64_FLD( PERV_ROOT_CTRL6_REFCLK_1_TERM_DIS_DC                    , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_REFCLK_1_TERM_DIS_DC );
+REG64_FLD( PERV_ROOT_CTRL6_6_SPARE_TERM_DIS                        , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_6_SPARE_TERM_DIS );
+REG64_FLD( PERV_ROOT_CTRL6_7_SPARE_TERM_DIS                        , 7   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_7_SPARE_TERM_DIS );
+REG64_FLD( PERV_ROOT_CTRL6_TPFSI_OSCSW0_PGOOD_N                    , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_OSCSW0_PGOOD_N );
+REG64_FLD( PERV_ROOT_CTRL6_TPFSI_OSCSW1_PGOOD                      , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_OSCSW1_PGOOD );
+REG64_FLD( PERV_ROOT_CTRL6_10_SPARE_REFCLOCK                       , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_10_SPARE_REFCLOCK );
+REG64_FLD( PERV_ROOT_CTRL6_11_SPARE_REFCLOCK                       , 11  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_11_SPARE_REFCLOCK );
+REG64_FLD( PERV_ROOT_CTRL6_TPFSI_OFFCHIP_REFCLK_EN_DC              , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL6_TPFSI_OFFCHIP_REFCLK_EN_DC_LEN          , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL6_GP_TP_GLBCK_VSB_NEST_MESH_SEL_DC        , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_GP_TP_GLBCK_VSB_NEST_MESH_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL6_25_SPARE_REFCLOCK_CONTROL               , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_25_SPARE_REFCLOCK_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL6_26_SPARE_REFCLOCK_CONTROL               , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_26_SPARE_REFCLOCK_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL6_TPFSI_ALTREFCLK_SEL                     , 27  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_ALTREFCLK_SEL );
+REG64_FLD( PERV_ROOT_CTRL6_TPFSI_ALTREFCLK_SE1                     , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TPFSI_ALTREFCLK_SE1 );
+REG64_FLD( PERV_ROOT_CTRL6_29_SPARE_REFCLOCK_CONTROL               , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_29_SPARE_REFCLOCK_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL6_30_SPARE_REFCLOCK_CONTROL               , 30  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_30_SPARE_REFCLOCK_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL6_31_SPARE_REFCLOCK_CONTROL               , 31  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_31_SPARE_REFCLOCK_CONTROL );
+
+REG64_FLD( PERV_ROOT_CTRL7_0_SPARE_SECTOR_BUFFER_CONTROL           , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_1_SPARE_SECTOR_BUFFER_CONTROL           , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_1_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_2_SPARE_SECTOR_BUFFER_CONTROL           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_2_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_3_SPARE_SECTOR_BUFFER_CONTROL           , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_3_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_4_SPARE_SECTOR_BUFFER_CONTROL           , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_4_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_5_SPARE_SECTOR_BUFFER_CONTROL           , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_5_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_6_SPARE_SECTOR_BUFFER_CONTROL           , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_6_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_7_SPARE_SECTOR_BUFFER_CONTROL           , 7   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_7_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_8_SPARE_SECTOR_BUFFER_CONTROL           , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_8_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_9_SPARE_SECTOR_BUFFER_CONTROL           , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_9_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_10_SPARE_SECTOR_BUFFER_CONTROL          , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_10_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_11_SPARE_SECTOR_BUFFER_CONTROL          , 11  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_11_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_12_SPARE_SECTOR_BUFFER_CONTROL          , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_12_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_13_SPARE_SECTOR_BUFFER_CONTROL          , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_13_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_14_SPARE_SECTOR_BUFFER_CONTROL          , 14  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_14_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_15_SPARE_SECTOR_BUFFER_CONTROL          , 15  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_15_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_16_SPARE_RESONANT_CLOCKING_CONTROL      , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_16_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_17_SPARE_RESONANT_CLOCKING_CONTROL      , 17  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_17_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_18_SPARE_RESONANT_CLOCKING_CONTROL      , 18  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_18_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_19_SPARE_RESONANT_CLOCKING_CONTROL      , 19  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_19_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_20_SPARE_RESONANT_CLOCKING_CONTROL      , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_20_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_21_SPARE_RESONANT_CLOCKING_CONTROL      , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_21_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_22_SPARE_RESONANT_CLOCKING_CONTROL      , 22  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_22_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_23_SPARE_RESONANT_CLOCKING_CONTROL      , 23  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_23_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_24_SPARE_RESONANT_CLOCKING_CONTROL      , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_24_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_25_SPARE_RESONANT_CLOCKING_CONTROL      , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_25_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_26_SPARE_RESONANT_CLOCKING_CONTROL      , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_26_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_27_SPARE_RESONANT_CLOCKING_CONTROL      , 27  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_27_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_28_SPARE_RESONANT_CLOCKING_CONTROL      , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_28_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_29_SPARE_RESONANT_CLOCKING_CONTROL      , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_29_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_30_SPARE_RESONANT_CLOCKING_CONTROL      , 30  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_30_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_31_SPARE_RESONANT_CLOCKING_CONTROL      , 31  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_31_SPARE_RESONANT_CLOCKING_CONTROL );
+
+REG64_FLD( PERV_ROOT_CTRL8_TP_SSPLL_PLL_RESET0_DC                  , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_SSPLL_PLL_RESET0_DC );
+REG64_FLD( PERV_ROOT_CTRL8_TP_SSPLL_PLL_BYPASS0_DC                 , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_SSPLL_PLL_BYPASS0_DC );
+REG64_FLD( PERV_ROOT_CTRL8_2_SPARE_SS_PLL_CONTROL                  , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_2_SPARE_SS_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_3_SPARE_SS_PLL_CONTROL                  , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_3_SPARE_SS_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_TP_FILTPLL_PLL_RESET1_DC                , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_FILTPLL_PLL_RESET1_DC );
+REG64_FLD( PERV_ROOT_CTRL8_TP_FILTPLL_PLL_BYPASS1_DC               , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_FILTPLL_PLL_BYPASS1_DC );
+REG64_FLD( PERV_ROOT_CTRL8_TP_FILTPLL_CP_ALT_BYPASS_DC             , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_FILTPLL_CP_ALT_BYPASS_DC );
+REG64_FLD( PERV_ROOT_CTRL8_TP_FILTPLL_IO_ALT_BYPASS_DC             , 7   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_FILTPLL_IO_ALT_BYPASS_DC );
+REG64_FLD( PERV_ROOT_CTRL8_8_SPARE_FILTER_PLL_CONTROL              , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_8_SPARE_FILTER_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_9_SPARE_FILTER_PLL_CONTROL              , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_9_SPARE_FILTER_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_TP_TANKPLL_TEST_PLL_BYPASS2_DC          , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_TANKPLL_TEST_PLL_BYPASS2_DC );
+REG64_FLD( PERV_ROOT_CTRL8_SPARE_TANK_PLL_CONTROL                  , 11  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SPARE_TANK_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_TP_PLL_TEST_ENABLE_DC                   , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PLL_TEST_ENABLE_DC );
+REG64_FLD( PERV_ROOT_CTRL8_TP_PLL_FORCE_OUT_EN_DC                  , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PLL_FORCE_OUT_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL8_14_SPARE_PLL                            , 14  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_14_SPARE_PLL );
+REG64_FLD( PERV_ROOT_CTRL8_15_SPARE_PLL                            , 15  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_15_SPARE_PLL );
+REG64_FLD( PERV_ROOT_CTRL8_TP_CLK_ASYNC_RESET_DC                   , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_CLK_ASYNC_RESET_DC );
+REG64_FLD( PERV_ROOT_CTRL8_TP_CLK_DIV_BYPASS_EN_DC                 , 17  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_CLK_DIV_BYPASS_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL8_TP_CLK_PDLY_BYPASS1_EN_DC               , 18  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_CLK_PDLY_BYPASS1_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL8_TP_CLK_PDLY_BYPASS2_EN_DC               , 19  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_CLK_PDLY_BYPASS2_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL8_20_SPARE_PLL_CONTROL                    , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_20_SPARE_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_21_SPARE_PLL_CONTROL                    , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_21_SPARE_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_22_SPARE_PLL_CONTROL                    , 22  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_22_SPARE_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_23_SPARE_PLL_CONTROL                    , 23  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_23_SPARE_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_TP_FSI_CLKIN_SEL_DC                     , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_FSI_CLKIN_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL8_25_SPARE_CLKIN_CONTROL                  , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_25_SPARE_CLKIN_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_26_SPARE_CLKIN_CONTROL                  , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_26_SPARE_CLKIN_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_27_SPARE_CLKIN_CONTROL                  , 27  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_27_SPARE_CLKIN_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_TP_PLL_CLKIN_SEL1_DC                    , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PLL_CLKIN_SEL1_DC );
+REG64_FLD( PERV_ROOT_CTRL8_TP_PLL_CLKIN_SEL2_DC                    , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PLL_CLKIN_SEL2_DC );
+REG64_FLD( PERV_ROOT_CTRL8_TP_PLL_CLKIN_SEL3_DC                    , 30  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PLL_CLKIN_SEL3_DC );
+REG64_FLD( PERV_ROOT_CTRL8_TP_PLL_CLKIN_SEL4_DC                    , 31  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TP_PLL_CLKIN_SEL4_DC );
+
+REG64_FLD( PERV_SBE_LCL_DBG_EN                                     , 0   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_EN         );
+REG64_FLD( PERV_SBE_LCL_DBG_HALT_ON_XSTOP                          , 1   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PERV_SBE_LCL_DBG_HALT_ON_TRIG                           , 2   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PERV_SBE_LCL_DBG_EN_RISCTRACE                           , 3   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_EN_RISCTRACE );
+REG64_FLD( PERV_SBE_LCL_DBG_EN_TRACE_FULL_IVA                      , 4   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_EN_TRACE_FULL_IVA );
+REG64_FLD( PERV_SBE_LCL_DBG_DIS_TRACE_EXTRA                        , 5   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_DIS_TRACE_EXTRA );
+REG64_FLD( PERV_SBE_LCL_DBG_DIS_TRACE_STALL                        , 6   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_DIS_TRACE_STALL );
+REG64_FLD( PERV_SBE_LCL_DBG_HTM_TRACE_MODE                         , 7   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_HTM_TRACE_MODE );
+REG64_FLD( PERV_SBE_LCL_DBG_SYNC_TIMER_SEL                         , 8   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_SYNC_TIMER_SEL );
+REG64_FLD( PERV_SBE_LCL_DBG_SYNC_TIMER_SEL_LEN                     , 4   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_SYNC_TIMER_SEL_LEN );
+REG64_FLD( PERV_SBE_LCL_DBG_FIR_TRIGGER                            , 12  ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_FIR_TRIGGER );
+REG64_FLD( PERV_SBE_LCL_DBG_MIB_GPIO                               , 13  ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_MIB_GPIO   );
+REG64_FLD( PERV_SBE_LCL_DBG_MIB_GPIO_LEN                           , 3   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PERV_SBE_LCL_DBG_HALT_INPUT                             , 16  ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_HALT_INPUT );
+
+REG64_FLD( PERV_SBE_LCL_EIMR_START0                                , 0   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START0     );
+REG64_FLD( PERV_SBE_LCL_EIMR_START1                                , 1   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START1     );
+REG64_FLD( PERV_SBE_LCL_EIMR_INTR0                                 , 2   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_INTR0      );
+REG64_FLD( PERV_SBE_LCL_EIMR_INTR1                                 , 3   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_INTR1      );
+REG64_FLD( PERV_SBE_LCL_EIMR_DRTM_REQ                              , 4   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_DRTM_REQ   );
+REG64_FLD( PERV_SBE_LCL_EIMR_SBEFIFO_RESET                         , 5   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_SBEFIFO_RESET );
+REG64_FLD( PERV_SBE_LCL_EIMR_SBEFIFO_DATA                          , 6   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_SBEFIFO_DATA );
+REG64_FLD( PERV_SBE_LCL_EIMR_SPARE                                 , 7   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_SPARE      );
+REG64_FLD( PERV_SBE_LCL_EIMR_TRIG                                  , 8   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_TRIG       );
+REG64_FLD( PERV_SBE_LCL_EIMR_XSTOP                                 , 9   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_XSTOP      );
+
+REG64_FLD( PERV_SBE_LCL_EINR_START0                                , 0   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_START0     );
+REG64_FLD( PERV_SBE_LCL_EINR_START1                                , 1   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_START1     );
+REG64_FLD( PERV_SBE_LCL_EINR_INTR0                                 , 2   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_INTR0      );
+REG64_FLD( PERV_SBE_LCL_EINR_INTR1                                 , 3   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_INTR1      );
+REG64_FLD( PERV_SBE_LCL_EINR_DRTM_REQ                              , 4   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_DRTM_REQ   );
+REG64_FLD( PERV_SBE_LCL_EINR_SBEFIFO_RESET                         , 5   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_SBEFIFO_RESET );
+REG64_FLD( PERV_SBE_LCL_EINR_SBEFIFO_DATA                          , 6   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_SBEFIFO_DATA );
+REG64_FLD( PERV_SBE_LCL_EINR_SPARE                                 , 7   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_SPARE      );
+REG64_FLD( PERV_SBE_LCL_EINR_TRIG                                  , 8   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_TRIG       );
+REG64_FLD( PERV_SBE_LCL_EINR_XSTOP                                 , 9   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_XSTOP      );
+
+REG64_FLD( PERV_SBE_LCL_EIPR_START0                                , 0   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START0     );
+REG64_FLD( PERV_SBE_LCL_EIPR_START1                                , 1   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START1     );
+REG64_FLD( PERV_SBE_LCL_EIPR_INTR0                                 , 2   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_INTR0      );
+REG64_FLD( PERV_SBE_LCL_EIPR_INTR1                                 , 3   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_INTR1      );
+REG64_FLD( PERV_SBE_LCL_EIPR_DRTM_REQ                              , 4   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_DRTM_REQ   );
+REG64_FLD( PERV_SBE_LCL_EIPR_SBEFIFO_RESET                         , 5   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_SBEFIFO_RESET );
+REG64_FLD( PERV_SBE_LCL_EIPR_SBEFIFO_DATA                          , 6   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_SBEFIFO_DATA );
+REG64_FLD( PERV_SBE_LCL_EIPR_SPARE                                 , 7   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_SPARE      );
+REG64_FLD( PERV_SBE_LCL_EIPR_TRIG                                  , 8   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_TRIG       );
+REG64_FLD( PERV_SBE_LCL_EIPR_XSTOP                                 , 9   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_XSTOP      );
+
+REG64_FLD( PERV_SBE_LCL_EISR_START0                                , 0   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START0     );
+REG64_FLD( PERV_SBE_LCL_EISR_START1                                , 1   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START1     );
+REG64_FLD( PERV_SBE_LCL_EISR_INTR0                                 , 2   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_INTR0      );
+REG64_FLD( PERV_SBE_LCL_EISR_INTR1                                 , 3   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_INTR1      );
+REG64_FLD( PERV_SBE_LCL_EISR_DRTM_REQ                              , 4   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_DRTM_REQ   );
+REG64_FLD( PERV_SBE_LCL_EISR_SBEFIFO_RESET                         , 5   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_SBEFIFO_RESET );
+REG64_FLD( PERV_SBE_LCL_EISR_SBEFIFO_DATA                          , 6   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_SBEFIFO_DATA );
+REG64_FLD( PERV_SBE_LCL_EISR_SPARE                                 , 7   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_SPARE      );
+REG64_FLD( PERV_SBE_LCL_EISR_TRIG                                  , 8   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_TRIG       );
+REG64_FLD( PERV_SBE_LCL_EISR_XSTOP                                 , 9   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_XSTOP      );
+
+REG64_FLD( PERV_SBE_LCL_EITR_START0                                , 0   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START0     );
+REG64_FLD( PERV_SBE_LCL_EITR_START1                                , 1   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_START1     );
+REG64_FLD( PERV_SBE_LCL_EITR_INTR0                                 , 2   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_INTR0      );
+REG64_FLD( PERV_SBE_LCL_EITR_INTR1                                 , 3   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_INTR1      );
+REG64_FLD( PERV_SBE_LCL_EITR_DRTM_REQ                              , 4   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_DRTM_REQ   );
+REG64_FLD( PERV_SBE_LCL_EITR_SBEFIFO_RESET                         , 5   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_SBEFIFO_RESET );
+REG64_FLD( PERV_SBE_LCL_EITR_SBEFIFO_DATA                          , 6   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_SBEFIFO_DATA );
+REG64_FLD( PERV_SBE_LCL_EITR_SPARE                                 , 7   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_SPARE      );
+REG64_FLD( PERV_SBE_LCL_EITR_TRIG                                  , 8   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_TRIG       );
+REG64_FLD( PERV_SBE_LCL_EITR_XSTOP                                 , 9   ,
+           SH_UNT_PERV     , SH_ACS_PPE2     , SH_FLD_XSTOP      );
+
+REG64_FLD( PERV_SBE_LCL_IVPR_IVPR                                  , 0   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_IVPR       );
+REG64_FLD( PERV_SBE_LCL_IVPR_IVPR_LEN                              , 23  ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_IVPR_LEN   );
+
+REG64_FLD( PERV_SBE_LCL_TBR_TIMEBASE                               , 0   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_TIMEBASE   );
+REG64_FLD( PERV_SBE_LCL_TBR_TIMEBASE_LEN                           , 32  ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_TIMEBASE_LEN );
+
+REG64_FLD( PERV_SBE_LCL_TSEL_FIT_SEL                               , 0   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_FIT_SEL    );
+REG64_FLD( PERV_SBE_LCL_TSEL_FIT_SEL_LEN                           , 4   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PERV_SBE_LCL_TSEL_WATCHDOG_SEL                          , 4   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PERV_SBE_LCL_TSEL_WATCHDOG_SEL_LEN                      , 4   ,
+           SH_UNT_PERV     , SH_ACS_PPE      , SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PERV_SB_CS_SECURE_DEBUG_MODE                            , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SECURE_DEBUG_MODE );
+REG64_FLD( PERV_SB_CS_START_RESTART_VECTOR0                        , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_START_RESTART_VECTOR0 );
+REG64_FLD( PERV_SB_CS_START_RESTART_VECTOR1                        , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_START_RESTART_VECTOR1 );
+REG64_FLD( PERV_SB_CS_INTERRUPT_S0                                 , 14  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_INTERRUPT_S0 );
+REG64_FLD( PERV_SB_CS_INTERRUPT_S1                                 , 15  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_INTERRUPT_S1 );
+REG64_FLD( PERV_SB_CS_DEBUG_BOLT_ON_CONTROL_BITS                   , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DEBUG_BOLT_ON_CONTROL_BITS );
+REG64_FLD( PERV_SB_CS_DEBUG_BOLT_ON_CONTROL_BITS_LEN               , 7   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DEBUG_BOLT_ON_CONTROL_BITS_LEN );
+
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_SYSTEM_FAST_INIT                , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SYSTEM_FAST_INIT );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_VITL                            , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_VITL       );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_PERV                            , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PERV       );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_UNIT1                           , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT1      );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_UNIT2                           , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT2      );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_UNIT3                           , 7   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT3      );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_UNIT4                           , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT4      );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_UNIT5                           , 9   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT5      );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_UNIT6                           , 10  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT6      );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_UNIT7                           , 11  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT7      );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_UNIT8                           , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT8      );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_UNIT9                           , 13  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT9      );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_UNIT10                          , 14  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT10     );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_FUNC                            , 48  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_FUNC       );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_CFG                             , 49  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CFG        );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_CCFG_GPTR                       , 50  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CCFG_GPTR  );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_REGF                            , 51  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_REGF       );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_LBIST                           , 52  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_LBIST      );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_ABIST                           , 53  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ABIST      );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_REPR                            , 54  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_REPR       );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_TIME                            , 55  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_TIME       );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_BNDY                            , 56  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_BNDY       );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_FARR                            , 57  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_FARR       );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_CMSK                            , 58  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CMSK       );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_INEX                            , 59  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_INEX       );
+
+REG64_FLD( PERV_FSI2PIB_SCRATCH0_SCRATCH_N                         , 0   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_PPE2     , SH_FLD_SCRATCH_N  );
+REG64_FLD( PERV_FSI2PIB_SCRATCH0_SCRATCH_N_LEN                     , 64  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_PPE2     , SH_FLD_SCRATCH_N_LEN );
+
+REG64_FLD( PERV_FSI2PIB_SCRATCH1_SCRATCH_N                         , 0   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_PPE2     , SH_FLD_SCRATCH_N  );
+REG64_FLD( PERV_FSI2PIB_SCRATCH1_SCRATCH_N_LEN                     , 64  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_PPE2     , SH_FLD_SCRATCH_N_LEN );
+
+REG64_FLD( PERV_FSI2PIB_SCRATCH2_SCRATCH_N                         , 0   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_PPE2     , SH_FLD_SCRATCH_N  );
+REG64_FLD( PERV_FSI2PIB_SCRATCH2_SCRATCH_N_LEN                     , 64  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_PPE2     , SH_FLD_SCRATCH_N_LEN );
+
+REG64_FLD( PERV_FSI2PIB_SCRATCH3_SCRATCH_N                         , 0   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_PPE2     , SH_FLD_SCRATCH_N  );
+REG64_FLD( PERV_FSI2PIB_SCRATCH3_SCRATCH_N_LEN                     , 64  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_PPE2     , SH_FLD_SCRATCH_N_LEN );
+
+REG64_FLD( PERV_SCRATCH_REGISTER_1_SR                              , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SR         );
+REG64_FLD( PERV_SCRATCH_REGISTER_1_SR_LEN                          , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SR_LEN     );
+
+REG64_FLD( PERV_SCRATCH_REGISTER_2_SR                              , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SR         );
+REG64_FLD( PERV_SCRATCH_REGISTER_2_SR_LEN                          , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SR_LEN     );
+
+REG64_FLD( PERV_SCRATCH_REGISTER_3_SR                              , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SR         );
+REG64_FLD( PERV_SCRATCH_REGISTER_3_SR_LEN                          , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SR_LEN     );
+
+REG64_FLD( PERV_SCRATCH_REGISTER_4_SR                              , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SR         );
+REG64_FLD( PERV_SCRATCH_REGISTER_4_SR_LEN                          , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SR_LEN     );
+
+REG64_FLD( PERV_SCRATCH_REGISTER_5_SR                              , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SR         );
+REG64_FLD( PERV_SCRATCH_REGISTER_5_SR_LEN                          , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SR_LEN     );
+
+REG64_FLD( PERV_SCRATCH_REGISTER_6_SR                              , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SR         );
+REG64_FLD( PERV_SCRATCH_REGISTER_6_SR_LEN                          , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SR_LEN     );
+
+REG64_FLD( PERV_SCRATCH_REGISTER_7_SR                              , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SR         );
+REG64_FLD( PERV_SCRATCH_REGISTER_7_SR_LEN                          , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SR_LEN     );
+
+REG64_FLD( PERV_SCRATCH_REGISTER_8_SR                              , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SR         );
+REG64_FLD( PERV_SCRATCH_REGISTER_8_SR_LEN                          , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SR_LEN     );
+
+REG32_FLD( PERV_FSISHIFT_SHIFT_CONTROL_REGISTER_2_REGISTER         , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REGISTER   );
+REG32_FLD( PERV_FSISHIFT_SHIFT_CONTROL_REGISTER_2_REGISTER_LEN     , 32  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REGISTER_LEN );
+
+REG64_FLD( PERV_1_SKITTER_CLKSRC_REG_SKITTER0                      , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SKITTER0   );
+REG64_FLD( PERV_1_SKITTER_CLKSRC_REG_SKITTER0_LEN                  , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SKITTER0_LEN );
+
+REG64_FLD( PERV_1_SKITTER_FORCE_REG_F_READ                         , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_F_READ     );
+
+REG64_FLD( PERV_1_SKITTER_MODE_REG_HOLD_SAMPLE                     , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_HOLD_SAMPLE );
+REG64_FLD( PERV_1_SKITTER_MODE_REG_DISABLE_STICKINESS              , 1   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_DISABLE_STICKINESS );
+REG64_FLD( PERV_1_SKITTER_MODE_REG_UNUSED1                         , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNUSED1    );
+REG64_FLD( PERV_1_SKITTER_MODE_REG_UNUSED1_LEN                     , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNUSED1_LEN );
+REG64_FLD( PERV_1_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL                , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_HOLD_DBGTRIG_SEL );
+REG64_FLD( PERV_1_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL_LEN            , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_HOLD_DBGTRIG_SEL_LEN );
+REG64_FLD( PERV_1_SKITTER_MODE_REG_RESET_TRIG_SEL                  , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_RESET_TRIG_SEL );
+REG64_FLD( PERV_1_SKITTER_MODE_REG_RESET_TRIG_SEL_LEN              , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_RESET_TRIG_SEL_LEN );
+REG64_FLD( PERV_1_SKITTER_MODE_REG_SAMPLE_GUTS                     , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SAMPLE_GUTS );
+REG64_FLD( PERV_1_SKITTER_MODE_REG_SAMPLE_GUTS_LEN                 , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SAMPLE_GUTS_LEN );
+REG64_FLD( PERV_1_SKITTER_MODE_REG_HOLD_SAMPLE_WITH_TRIGGER        , 44  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_HOLD_SAMPLE_WITH_TRIGGER );
+REG64_FLD( PERV_1_SKITTER_MODE_REG_DATA_V_LT                       , 45  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_DATA_V_LT  );
+
+REG64_FLD( PERV_1_SLAVE_CONFIG_REG_CFG_DISABLE_PERV_THOLD_CHECK    , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CFG_DISABLE_PERV_THOLD_CHECK );
+REG64_FLD( PERV_1_SLAVE_CONFIG_REG_CFG_DISABLE_MALF_PULSE_GEN      , 1   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CFG_DISABLE_MALF_PULSE_GEN );
+REG64_FLD( PERV_1_SLAVE_CONFIG_REG_CFG_STOP_HANG_CNT_SYS_XSTP      , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CFG_STOP_HANG_CNT_SYS_XSTP );
+REG64_FLD( PERV_1_SLAVE_CONFIG_REG_CFG_DISABLE_CL_ATOMIC_LOCK      , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CFG_DISABLE_CL_ATOMIC_LOCK );
+REG64_FLD( PERV_1_SLAVE_CONFIG_REG_CFG_DISABLE_HEARTBEAT           , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CFG_DISABLE_HEARTBEAT );
+REG64_FLD( PERV_1_SLAVE_CONFIG_REG_CFG_DISABLE_FORCE_TO_ZERO       , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CFG_DISABLE_FORCE_TO_ZERO );
+REG64_FLD( PERV_1_SLAVE_CONFIG_REG_CFG_PM_DISABLE                  , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CFG_PM_DISABLE );
+REG64_FLD( PERV_1_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE              , 7   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CFG_PM_MUX_DISABLE );
+REG64_FLD( PERV_1_SLAVE_CONFIG_REG_ERROR_MASK                      , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ERROR_MASK );
+REG64_FLD( PERV_1_SLAVE_CONFIG_REG_ERROR_MASK_LEN                  , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_ERROR_MASK_LEN );
+
+REG64_FLD( PERV_SNS1LTH_SNS1_UNUSED_0_31                           , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SNS1_UNUSED_0_31 );
+REG64_FLD( PERV_SNS1LTH_SNS1_UNUSED_0_31_LEN                       , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SNS1_UNUSED_0_31_LEN );
+
+REG64_FLD( PERV_SNS2LTH_SNS2_UNUSED_0_31                           , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SNS2_UNUSED_0_31 );
+REG64_FLD( PERV_SNS2LTH_SNS2_UNUSED_0_31_LEN                       , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SNS2_UNUSED_0_31_LEN );
+
+REG32_FLD( PERV_FSI2PIB_STATUS_ANY_ERROR                           , 0   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_ANY_ERROR  );
+REG32_FLD( PERV_FSI2PIB_STATUS_SYSTEM_CHECKSTOP                    , 1   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_SYSTEM_CHECKSTOP );
+REG32_FLD( PERV_FSI2PIB_STATUS_SPECIAL_ATTENTION                   , 2   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_SPECIAL_ATTENTION );
+REG32_FLD( PERV_FSI2PIB_STATUS_RECOVERABLE_ERROR                   , 3   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_RECOVERABLE_ERROR );
+REG32_FLD( PERV_FSI2PIB_STATUS_CHIPLET_INTERRUPT_FROM_HOST         , 4   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_CHIPLET_INTERRUPT_FROM_HOST );
+REG32_FLD( PERV_FSI2PIB_STATUS_PARITY_CHECK                        , 5   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_PARITY_CHECK );
+REG32_FLD( PERV_FSI2PIB_STATUS_POWER_MANAGEMENT_INTERRUPT          , 6   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_POWER_MANAGEMENT_INTERRUPT );
+REG32_FLD( PERV_FSI2PIB_STATUS_PROTECTION_CHECK                    , 7   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_PROTECTION_CHECK );
+REG32_FLD( PERV_FSI2PIB_STATUS_SELFBOOT_DONE                       , 8   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_SELFBOOT_DONE );
+REG32_FLD( PERV_FSI2PIB_STATUS_RESERVED_9                          , 9   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_RESERVED_9 );
+REG32_FLD( PERV_FSI2PIB_STATUS_RESERVED_10                         , 10  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_RESERVED_10 );
+REG32_FLD( PERV_FSI2PIB_STATUS_PIB_ABORT                           , 11  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_PIB_ABORT  );
+REG32_FLD( PERV_FSI2PIB_STATUS_USE_OSC_OBSERVATION                 , 12  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_USE_OSC_OBSERVATION );
+REG32_FLD( PERV_FSI2PIB_STATUS_USE_OSC_OBSERVATION_LEN             , 4   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_USE_OSC_OBSERVATION_LEN );
+REG32_FLD( PERV_FSI2PIB_STATUS_VDD_NEST_OBSERVE                    , 16  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_VDD_NEST_OBSERVE );
+REG32_FLD( PERV_FSI2PIB_STATUS_PIB_ERROR_CODE                      , 17  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_PIB_ERROR_CODE );
+REG32_FLD( PERV_FSI2PIB_STATUS_PIB_ERROR_CODE_LEN                  , 3   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_PIB_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI2PIB_STATUS_OSCILLATOR                          , 20  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_OSCILLATOR );
+REG32_FLD( PERV_FSI2PIB_STATUS_OSCILLATOR_LEN                      , 4   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_OSCILLATOR_LEN );
+REG32_FLD( PERV_FSI2PIB_STATUS_PLLLOCK_0_FILTER_PLL_NEST           , 24  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_PLLLOCK_0_FILTER_PLL_NEST );
+REG32_FLD( PERV_FSI2PIB_STATUS_PLLLOCK_1_FILTER_PLL_MC             , 25  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_PLLLOCK_1_FILTER_PLL_MC );
+REG32_FLD( PERV_FSI2PIB_STATUS_PLLLOCK_2_XBUS                      , 26  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_PLLLOCK_2_XBUS );
+REG32_FLD( PERV_FSI2PIB_STATUS_PLLLOCK_3_NEST                      , 27  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_PLLLOCK_3_NEST );
+REG32_FLD( PERV_FSI2PIB_STATUS_INTERRUPT_CONDITION_PENDING         , 28  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_INTERRUPT_CONDITION_PENDING );
+REG32_FLD( PERV_FSI2PIB_STATUS_INTERRUPT_ENABLED                   , 29  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_INTERRUPT_ENABLED );
+REG32_FLD( PERV_FSI2PIB_STATUS_SELFBOOT_ENGINE_ATTENTION           , 30  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_SELFBOOT_ENGINE_ATTENTION );
+REG32_FLD( PERV_FSI2PIB_STATUS_RESERVED_31                         , 31  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_RESERVED_31 );
+
+REG32_FLD( PERV_FSISHIFT_STATUS_4                                  , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_4          );
+REG32_FLD( PERV_FSISHIFT_STATUS_4_LEN                              , 32  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_4_LEN      );
+
+REG64_FLD( PERV_STAT_RDDAT_ERRES_CMD_PARITY_ERROR                  , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_CMD_PARITY_ERROR );
+REG64_FLD( PERV_STAT_RDDAT_ERRES_WR_DATA_PARITY_ERROR              , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_WR_DATA_PARITY_ERROR );
+REG64_FLD( PERV_STAT_RDDAT_ERRES_RD_DATA_PARITY_ERROR              , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_RD_DATA_PARITY_ERROR );
+REG64_FLD( PERV_STAT_RDDAT_ERRES_LCK_STATUS_PARITY_ERROR           , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_LCK_STATUS_PARITY_ERROR );
+REG64_FLD( PERV_STAT_RDDAT_ERRES_FSM_PARITY_ERROR                  , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_FSM_PARITY_ERROR );
+REG64_FLD( PERV_STAT_RDDAT_ERRES_OPB_PARITY_ERROR                  , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RO  , SH_FLD_OPB_PARITY_ERROR );
+
+REG64_FLD( PERV_1_SYNC_CONFIG_PULSE_DELAY                          , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PULSE_DELAY );
+REG64_FLD( PERV_1_SYNC_CONFIG_PULSE_DELAY_LEN                      , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PULSE_DELAY_LEN );
+REG64_FLD( PERV_1_SYNC_CONFIG_UNUSED3                              , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNUSED3    );
+REG64_FLD( PERV_1_SYNC_CONFIG_LISTEN_TO_PULSE_DIS                  , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_LISTEN_TO_PULSE_DIS );
+REG64_FLD( PERV_1_SYNC_CONFIG_USE_FOR_SCAN                         , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_USE_FOR_SCAN );
+REG64_FLD( PERV_1_SYNC_CONFIG_DISABLE_PCB_ITR                      , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_DISABLE_PCB_ITR );
+REG64_FLD( PERV_1_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED             , 7   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_CLEAR_CHIPLET_IS_ALIGNED );
+REG64_FLD( PERV_1_SYNC_CONFIG_UNIT_REGION_CLKCMD_ENABLE            , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT_REGION_CLKCMD_ENABLE );
+REG64_FLD( PERV_1_SYNC_CONFIG_UNUSED919                            , 9   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNUSED919  );
+REG64_FLD( PERV_1_SYNC_CONFIG_UNUSED919_LEN                        , 11  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNUSED919_LEN );
+
+REG64_FLD( PERV_1_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR               , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_DIS_CPM_BUBBLE_CORR );
+REG64_FLD( PERV_1_THERM_MODE_REG_FORCE_THRES_ACT                   , 1   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_FORCE_THRES_ACT );
+REG64_FLD( PERV_1_THERM_MODE_REG_THRES_TRIP_ENA                    , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_THRES_TRIP_ENA );
+REG64_FLD( PERV_1_THERM_MODE_REG_THRES_TRIP_ENA_LEN                , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_THRES_TRIP_ENA_LEN );
+REG64_FLD( PERV_1_THERM_MODE_REG_DTS_SAMPLE_ENA                    , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_DTS_SAMPLE_ENA );
+REG64_FLD( PERV_1_THERM_MODE_REG_SAMPLE_PULSE_CNT                  , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SAMPLE_PULSE_CNT );
+REG64_FLD( PERV_1_THERM_MODE_REG_SAMPLE_PULSE_CNT_LEN              , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_SAMPLE_PULSE_CNT_LEN );
+REG64_FLD( PERV_1_THERM_MODE_REG_THRES_ENA                         , 10  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_THRES_ENA  );
+REG64_FLD( PERV_1_THERM_MODE_REG_THRES_ENA_LEN                     , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_THRES_ENA_LEN );
+REG64_FLD( PERV_1_THERM_MODE_REG_DTS_TRIGGER                       , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_DTS_TRIGGER );
+REG64_FLD( PERV_1_THERM_MODE_REG_DTS_TRIGGER_SEL                   , 13  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_DTS_TRIGGER_SEL );
+REG64_FLD( PERV_1_THERM_MODE_REG_THRES_OVERFLOW_MASK               , 14  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_THRES_OVERFLOW_MASK );
+REG64_FLD( PERV_1_THERM_MODE_REG_UNUSED                            , 15  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNUSED     );
+REG64_FLD( PERV_1_THERM_MODE_REG_DTS_READ_SEL                      , 16  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_DTS_READ_SEL );
+REG64_FLD( PERV_1_THERM_MODE_REG_DTS_READ_SEL_LEN                  , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_DTS_READ_SEL_LEN );
+REG64_FLD( PERV_1_THERM_MODE_REG_DTS_ENABLE_L1                     , 20  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_DTS_ENABLE_L1 );
+REG64_FLD( PERV_1_THERM_MODE_REG_DTS_ENABLE_L1_LEN                 , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_DTS_ENABLE_L1_LEN );
+
+REG64_FLD( PERV_TIMEOUT_REG_REGISTER                               , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_REGISTER   );
+REG64_FLD( PERV_TIMEOUT_REG_REGISTER_LEN                           , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_REGISTER_LEN );
+
+REG64_FLD( PERV_1_TIMESTAMP_COUNTER_READ_VALUE                     , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_VALUE      );
+REG64_FLD( PERV_1_TIMESTAMP_COUNTER_READ_VALUE_LEN                 , 44  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_VALUE_LEN  );
+REG64_FLD( PERV_1_TIMESTAMP_COUNTER_READ_OVERFLOW_ERR              , 44  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM_RO  , SH_FLD_OVERFLOW_ERR );
+
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_TIMEBASE_ENABLE                  , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TIMEBASE_ENABLE );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_I_PATH_CORE_SYNC_PERIOD_SELECT   , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_I_PATH_CORE_SYNC_PERIOD_SELECT );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_I_PATH_CORE_SYNC_PERIOD_SELECT_LEN , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_I_PATH_CORE_SYNC_PERIOD_SELECT_LEN );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_I_PATH_SYNC_CHECK_DISABLE        , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_I_PATH_SYNC_CHECK_DISABLE );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_TX_TTYPE_PIB_MST_FSM_STATE_DISABLE , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TX_TTYPE_PIB_MST_FSM_STATE_DISABLE );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_RX_TTYPE_1_ON_STEP_ENABLE        , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_RX_TTYPE_1_ON_STEP_ENABLE );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_MOVE_TO_TB_ON_2X_SYNC_ENABLE     , 7   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MOVE_TO_TB_ON_2X_SYNC_ENABLE );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_USE_TB_SYNC_MECHANISM            , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_USE_TB_SYNC_MECHANISM );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_USE_TB_STEP_SYNC                 , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_USE_TB_STEP_SYNC );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_LOW_ORDER_STEP_VALUE             , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_LOW_ORDER_STEP_VALUE );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_LOW_ORDER_STEP_VALUE_LEN         , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_LOW_ORDER_STEP_VALUE_LEN );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_DISTRIBUTION_BROADCAST_MODE_ENABLE , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DISTRIBUTION_BROADCAST_MODE_ENABLE );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_17_18                 , 17  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X10_SPARE_17_18 );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_17_18_LEN             , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X10_SPARE_17_18_LEN );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_19_23                 , 19  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X10_SPARE_19_23 );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_19_23_LEN             , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X10_SPARE_19_23_LEN );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_24_25                 , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X10_SPARE_24_25 );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_24_25_LEN             , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X10_SPARE_24_25_LEN );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_TX_TTYPE_PIB_MST_IF_RESET        , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_TX_TTYPE_PIB_MST_IF_RESET );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_27                    , 27  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X10_SPARE_27 );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_M_PATH_CLOCK_OFF_ENABLE          , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_M_PATH_CLOCK_OFF_ENABLE );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_29                    , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X10_SPARE_29 );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_XSTOP_GATE                       , 30  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_XSTOP_GATE );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_STICKY_ERROR_INJECT_ENABLE       , 31  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_STICKY_ERROR_INJECT_ENABLE );
+
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X00_DATA_PARITY              , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_0X00_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_M_PATH_0_PARITY               , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_M_PATH_0_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_M_PATH_1_PARITY               , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_M_PATH_1_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X01_DATA_PARITY              , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_0X01_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X02_DATA_PARITY              , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_0X02_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X03_DATA_PARITY              , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_0X03_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X04_DATA_PARITY              , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_0X04_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X05_DATA_PARITY              , 7   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_0X05_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X06_DATA_PARITY              , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_0X06_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X07_DATA_PARITY              , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_0X07_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_S_PATH_0_PARITY               , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_S_PATH_0_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X08_DATA_PARITY              , 11  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_0X08_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X09_DATA_PARITY              , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_0X09_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X0A_DATA_PARITY              , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_0X0A_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_M_PATH_0_STEP_CHECK           , 14  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_M_PATH_0_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_M_PATH_1_STEP_CHECK           , 15  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_M_PATH_1_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_S_PATH_0_STEP_CHECK           , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_S_PATH_0_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_I_PATH_STEP_CHECK             , 17  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_I_PATH_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_PSS_HAM                       , 18  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_PSS_HAM    );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X0B_DATA_PARITY              , 19  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_0X0B_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_S_PATH_1_PARITY               , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_S_PATH_1_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_S_PATH_1_STEP_CHECK           , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_S_PATH_1_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_I_PATH_DELAY_STEP_CHECK_PARITY , 22  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_I_PATH_DELAY_STEP_CHECK_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X0C_DATA_PARITY              , 23  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_0X0C_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY ,
+           24  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X17_0X18_0X21_0X22_DATA_PARITY , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_0X17_0X18_0X21_0X22_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X1D_0X1E_0X1F_DATA_PARITY    , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_0X1D_0X1E_0X1F_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X20_DATA_PARITY              , 27  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_0X20_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X23_DATA_PARITY              , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_0X23_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X24_DATA_PARITY              , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_0X24_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X29_DATA_PARITY              , 30  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_0X29_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X30_0X31_0X32_0X33_DATA_PARITY , 31  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_0X30_0X31_0X32_0X33_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X10_DATA_PARITY              , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_0X10_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_I_PATH_SYNC_CHECK             , 33  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_I_PATH_SYNC_CHECK );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_I_PATH_FSM_STATE_PARITY       , 34  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_I_PATH_FSM_STATE_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_I_PATH_TIME_PARITY            , 35  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_I_PATH_TIME_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_I_PATH_TIME_OVERFLOW          , 36  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_I_PATH_TIME_OVERFLOW );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_WOF_LOW_ORDER_STEP_COUNTER_PARITY , 37  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_WOF_LOW_ORDER_STEP_COUNTER_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_0                    , 38  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_RX_TTYPE_0 );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_1                    , 39  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_RX_TTYPE_1 );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_2                    , 40  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_RX_TTYPE_2 );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_3                    , 41  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_RX_TTYPE_3 );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_4                    , 42  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_RX_TTYPE_4 );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_5                    , 43  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_RX_TTYPE_5 );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_PIB_SLAVE_ADDR_INVALID        , 44  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_PIB_SLAVE_ADDR_INVALID );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_PIB_SLAVE_WRITE_INVALID       , 45  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_PIB_SLAVE_WRITE_INVALID );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_PIB_SLAVE_READ_INVALID        , 46  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_PIB_SLAVE_READ_INVALID );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_PIB_SLAVE_ADDR_PARITY         , 47  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_PIB_SLAVE_ADDR_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_PIB_SLAVE_DATA_PARITY         , 48  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_PIB_SLAVE_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X27_DATA_PARITY              , 49  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_0X27_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_PIB_MASTER_RSP_INFO           , 50  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_PIB_MASTER_RSP_INFO );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_PIB_MASTER_RSP_INFO_LEN       , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_PIB_MASTER_RSP_INFO_LEN );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_INVALID              , 53  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_RX_TTYPE_INVALID );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_4_DATA_PARITY        , 54  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_RX_TTYPE_4_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_PIB_MASTER_REQUEST            , 55  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_PIB_MASTER_REQUEST );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_PIB_RESET_DURING_PIB_ACCESS   , 56  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_PIB_RESET_DURING_PIB_ACCESS );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_EXTERNAL_XSTOP                , 57  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_EXTERNAL_XSTOP );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_SPARE_58                      , 58  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_SPARE_58   );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_SPARE_59                      , 59  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_SPARE_59   );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_SPARE_60                      , 60  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_SPARE_60   );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_SPARE_61                      , 61  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_SPARE_61   );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_OSCSWITCH_INTERRUPT           , 62  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_OSCSWITCH_INTERRUPT );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_CORE_STEP                     , 63  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_CORE_STEP  );
+
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X00_DATA_PARITY                , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X00_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_M_PATH_0_PARITY                 , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M_PATH_0_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_M_PATH_1_PARITY                 , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M_PATH_1_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X01_DATA_PARITY                , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X01_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X02_DATA_PARITY                , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X02_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X03_DATA_PARITY                , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X03_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X04_DATA_PARITY                , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X04_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X05_DATA_PARITY                , 7   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X05_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X06_DATA_PARITY                , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X06_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X07_DATA_PARITY                , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X07_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_S_PATH_0_PARITY                 , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_S_PATH_0_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X08_DATA_PARITY                , 11  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X08_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X09_DATA_PARITY                , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X09_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X0A_DATA_PARITY                , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X0A_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_M_PATH_0_STEP_CHECK             , 14  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M_PATH_0_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_M_PATH_1_STEP_CHECK             , 15  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M_PATH_1_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_S_PATH_0_STEP_CHECK             , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_S_PATH_0_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_I_PATH_STEP_CHECK               , 17  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_PSS_HAM                         , 18  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PSS_HAM    );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X0B_DATA_PARITY                , 19  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X0B_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_S_PATH_1_PARITY                 , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_S_PATH_1_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_S_PATH_1_STEP_CHECK             , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_S_PATH_1_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_I_PATH_DELAY_STEP_CHECK_PARITY  , 22  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_DELAY_STEP_CHECK_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X0C_DATA_PARITY                , 23  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X0C_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY ,
+           24  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X17_0X18_0X21_0X22_DATA_PARITY , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X17_0X18_0X21_0X22_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X1D_0X1E_0X1F_DATA_PARITY      , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X1D_0X1E_0X1F_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X20_DATA_PARITY                , 27  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X20_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X23_DATA_PARITY                , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X23_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X24_DATA_PARITY                , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X24_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X29_DATA_PARITY                , 30  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X29_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X30_0X31_0X32_0X33_DATA_PARITY , 31  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X30_0X31_0X32_0X33_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X10_DATA_PARITY                , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X10_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_I_PATH_SYNC_CHECK               , 33  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_SYNC_CHECK );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_I_PATH_FSM_STATE_PARITY         , 34  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_FSM_STATE_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_I_PATH_TIME_PARITY              , 35  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_TIME_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_I_PATH_TIME_OVERFLOW            , 36  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_TIME_OVERFLOW );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_WOF_LOW_ORDER_STEP_COUNTER_PARITY , 37  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_WOF_LOW_ORDER_STEP_COUNTER_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_RX_TTYPE_0                      , 38  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_0 );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_RX_TTYPE_1                      , 39  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_1 );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_RX_TTYPE_2                      , 40  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_2 );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_RX_TTYPE_3                      , 41  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_3 );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_RX_TTYPE_4                      , 42  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_4 );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_RX_TTYPE_5                      , 43  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_5 );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_PIB_SLAVE_ADDR_INVALID          , 44  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_SLAVE_ADDR_INVALID );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_PIB_SLAVE_WRITE_INVALID         , 45  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_SLAVE_WRITE_INVALID );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_PIB_SLAVE_READ_INVALID          , 46  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_SLAVE_READ_INVALID );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_PIB_SLAVE_ADDR_PARITY           , 47  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_SLAVE_ADDR_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_PIB_SLAVE_DATA_PARITY           , 48  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_SLAVE_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X27_DATA_PARITY                , 49  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X27_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_PIB_MASTER_RSP_INFO             , 50  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_MASTER_RSP_INFO );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_PIB_MASTER_RSP_INFO_LEN         , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_MASTER_RSP_INFO_LEN );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_RX_TTYPE_INVALID                , 53  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_INVALID );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_RX_TTYPE_4_DATA_PARITY          , 54  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_4_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_PIB_MASTER_REQUEST              , 55  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_MASTER_REQUEST );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_PIB_RESET_DURING_PIB_ACCESS     , 56  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_RESET_DURING_PIB_ACCESS );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_EXTERNAL_XSTOP                  , 57  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_EXTERNAL_XSTOP );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_SPARE_58                        , 58  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SPARE_58   );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_SPARE_59                        , 59  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SPARE_59   );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_SPARE_60                        , 60  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SPARE_60   );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_SPARE_61                        , 61  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SPARE_61   );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_OSCSWITCH_INTERRUPT             , 62  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_OSCSWITCH_INTERRUPT );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_SPARE_63                        , 63  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SPARE_63   );
+
+REG64_FLD( PERV_TOD_ERROR_REG_0X00_DATA_PARITY                     , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X00_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_M_PATH_0_PARITY                      , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M_PATH_0_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_M_PATH_1_PARITY                      , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M_PATH_1_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X01_DATA_PARITY                     , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X01_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X02_DATA_PARITY                     , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X02_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X03_DATA_PARITY                     , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X03_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X04_DATA_PARITY                     , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X04_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X05_DATA_PARITY                     , 7   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X05_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X06_DATA_PARITY                     , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X06_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X07_DATA_PARITY                     , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X07_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_S_PATH_0_PARITY                      , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_S_PATH_0_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X08_DATA_PARITY                     , 11  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X08_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X09_DATA_PARITY                     , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X09_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X0A_DATA_PARITY                     , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X0A_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_M_PATH_0_STEP_CHECK                  , 14  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M_PATH_0_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_REG_M_PATH_1_STEP_CHECK                  , 15  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M_PATH_1_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_REG_S_PATH_0_STEP_CHECK                  , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_S_PATH_0_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_REG_I_PATH_STEP_CHECK                    , 17  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_REG_PSS_HAM                              , 18  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PSS_HAM    );
+REG64_FLD( PERV_TOD_ERROR_REG_0X0B_DATA_PARITY                     , 19  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X0B_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_S_PATH_1_PARITY                      , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_S_PATH_1_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_S_PATH_1_STEP_CHECK                  , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_S_PATH_1_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_REG_I_PATH_DELAY_STEP_CHECK_PARITY       , 22  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_DELAY_STEP_CHECK_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X0C_DATA_PARITY                     , 23  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X0C_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X17_0X18_0X21_0X22_DATA_PARITY      , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X17_0X18_0X21_0X22_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X1D_0X1E_0X1F_DATA_PARITY           , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X1D_0X1E_0X1F_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X20_DATA_PARITY                     , 27  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X20_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X23_DATA_PARITY                     , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X23_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X24_DATA_PARITY                     , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X24_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X29_DATA_PARITY                     , 30  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X29_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X30_0X31_0X32_0X33_DATA_PARITY      , 31  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X30_0X31_0X32_0X33_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X10_DATA_PARITY                     , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X10_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_I_PATH_SYNC_CHECK                    , 33  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_SYNC_CHECK );
+REG64_FLD( PERV_TOD_ERROR_REG_I_PATH_FSM_STATE_PARITY              , 34  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_FSM_STATE_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_I_PATH_TIME_PARITY                   , 35  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_TIME_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_I_PATH_TIME_OVERFLOW                 , 36  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_TIME_OVERFLOW );
+REG64_FLD( PERV_TOD_ERROR_REG_WOF_LOW_ORDER_STEP_COUNTER_PARITY    , 37  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_WOF_LOW_ORDER_STEP_COUNTER_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_RX_TTYPE_0                           , 38  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_0 );
+REG64_FLD( PERV_TOD_ERROR_REG_RX_TTYPE_1                           , 39  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_1 );
+REG64_FLD( PERV_TOD_ERROR_REG_RX_TTYPE_2                           , 40  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_2 );
+REG64_FLD( PERV_TOD_ERROR_REG_RX_TTYPE_3                           , 41  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_3 );
+REG64_FLD( PERV_TOD_ERROR_REG_RX_TTYPE_4                           , 42  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_4 );
+REG64_FLD( PERV_TOD_ERROR_REG_RX_TTYPE_5                           , 43  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_5 );
+REG64_FLD( PERV_TOD_ERROR_REG_PIB_SLAVE_ADDR_INVALID               , 44  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_SLAVE_ADDR_INVALID );
+REG64_FLD( PERV_TOD_ERROR_REG_PIB_SLAVE_WRITE_INVALID              , 45  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_SLAVE_WRITE_INVALID );
+REG64_FLD( PERV_TOD_ERROR_REG_PIB_SLAVE_READ_INVALID               , 46  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_SLAVE_READ_INVALID );
+REG64_FLD( PERV_TOD_ERROR_REG_PIB_SLAVE_ADDR_PARITY                , 47  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_SLAVE_ADDR_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_PIB_SLAVE_DATA_PARITY                , 48  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_SLAVE_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X27_DATA_PARITY                     , 49  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X27_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_PIB_MASTER_RSP_INFO                  , 50  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_MASTER_RSP_INFO );
+REG64_FLD( PERV_TOD_ERROR_REG_PIB_MASTER_RSP_INFO_LEN              , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_MASTER_RSP_INFO_LEN );
+REG64_FLD( PERV_TOD_ERROR_REG_RX_TTYPE_INVALID                     , 53  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_INVALID );
+REG64_FLD( PERV_TOD_ERROR_REG_RX_TTYPE_4_DATA_PARITY               , 54  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_4_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_PIB_MASTER_REQUEST                   , 55  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_MASTER_REQUEST );
+REG64_FLD( PERV_TOD_ERROR_REG_PIB_RESET_DURING_PIB_ACCESS          , 56  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_RESET_DURING_PIB_ACCESS );
+REG64_FLD( PERV_TOD_ERROR_REG_EXTERNAL_XSTOP                       , 57  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_EXTERNAL_XSTOP );
+REG64_FLD( PERV_TOD_ERROR_REG_SPARE_58                             , 58  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SPARE_58   );
+REG64_FLD( PERV_TOD_ERROR_REG_SPARE_59                             , 59  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SPARE_59   );
+REG64_FLD( PERV_TOD_ERROR_REG_SPARE_60                             , 60  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SPARE_60   );
+REG64_FLD( PERV_TOD_ERROR_REG_SPARE_61                             , 61  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SPARE_61   );
+REG64_FLD( PERV_TOD_ERROR_REG_OSCSWITCH_INTERRUPT                  , 62  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_OSCSWITCH_INTERRUPT );
+REG64_FLD( PERV_TOD_ERROR_REG_SPARE_63                             , 63  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SPARE_63   );
+
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X00_DATA_PARITY             , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X00_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_M_PATH_0_PARITY              , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M_PATH_0_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_M_PATH_1_PARITY              , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M_PATH_1_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X01_DATA_PARITY             , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X01_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X02_DATA_PARITY             , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X02_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X03_DATA_PARITY             , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X03_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X04_DATA_PARITY             , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X04_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X05_DATA_PARITY             , 7   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X05_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X06_DATA_PARITY             , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X06_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X07_DATA_PARITY             , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X07_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_S_PATH_0_PARITY              , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_S_PATH_0_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X08_DATA_PARITY             , 11  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X08_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X09_DATA_PARITY             , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X09_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X0A_DATA_PARITY             , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X0A_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_M_PATH_0_STEP_CHECK          , 14  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M_PATH_0_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_M_PATH_1_STEP_CHECK          , 15  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M_PATH_1_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_S_PATH_0_STEP_CHECK          , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_S_PATH_0_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_I_PATH_STEP_CHECK            , 17  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_PSS_HAM_CORE_INTERRUPT_MASK  , 18  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PSS_HAM_CORE_INTERRUPT_MASK );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X0B_DATA_PARITY             , 19  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X0B_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_S_PATH_1_PARITY              , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_S_PATH_1_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_S_PATH_1_STEP_CHECK          , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_S_PATH_1_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_I_PATH_DELAY_STEP_CHECK_PARITY , 22  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_DELAY_STEP_CHECK_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X0C_DATA_PARITY             , 23  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X0C_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY
+           , 24  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X17_0X18_0X21_0X22_DATA_PARITY , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X17_0X18_0X21_0X22_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X1D_0X1E_0X1F_DATA_PARITY   , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X1D_0X1E_0X1F_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X20_DATA_PARITY             , 27  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X20_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X23_DATA_PARITY             , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X23_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X24_DATA_PARITY             , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X24_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X29_DATA_PARITY             , 30  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X29_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X30_0X31_0X32_0X33_DATA_PARITY , 31  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X30_0X31_0X32_0X33_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X10_DATA_PARITY             , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X10_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_I_PATH_SYNC_CHECK            , 33  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_SYNC_CHECK );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_I_PATH_FSM_STATE_PARITY      , 34  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_FSM_STATE_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_I_PATH_TIME_PARITY           , 35  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_TIME_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_I_PATH_TIME_OVERFLOW_CORE_INTERRUPT ,
+           36  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_TIME_OVERFLOW_CORE_INTERRUPT );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_WOF_LOW_ORDER_STEP_COUNTER_PARITY , 37  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_WOF_LOW_ORDER_STEP_COUNTER_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_0                   , 38  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_0 );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_1                   , 39  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_1 );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_2                   , 40  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_2 );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_3                   , 41  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_3 );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_4                   , 42  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_4 );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_5                   , 43  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_5 );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_PIB_SLAVE_ADDR_INVALID       , 44  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_SLAVE_ADDR_INVALID );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_PIB_SLAVE_WRITE_INVALID      , 45  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_SLAVE_WRITE_INVALID );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_PIB_SLAVE_READ_INVALID       , 46  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_SLAVE_READ_INVALID );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_PIB_SLAVE_ADDR_PARITY        , 47  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_SLAVE_ADDR_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_PIB_SLAVE_DATA_PARITY        , 48  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_SLAVE_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X27_DATA_PARITY             , 49  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X27_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_PIB_MASTER_RSP_INFO          , 50  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_MASTER_RSP_INFO );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_PIB_MASTER_RSP_INFO_LEN      , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_MASTER_RSP_INFO_LEN );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_INVALID             , 53  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_INVALID );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_4_DATA_PARITY       , 54  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_TTYPE_4_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_PIB_MASTER_REQUEST           , 55  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_MASTER_REQUEST );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_PIB_RESET_DURING_PIB_ACCESS  , 56  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PIB_RESET_DURING_PIB_ACCESS );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_EXTERNAL_XSTOP               , 57  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_EXTERNAL_XSTOP );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_SPARE_58                     , 58  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SPARE_58   );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_SPARE_59                     , 59  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SPARE_59   );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_SPARE_60                     , 60  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SPARE_60   );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_SPARE_61                     , 61  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SPARE_61   );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_OSCSWITCH_INTERRUPT          , 62  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_OSCSWITCH_INTERRUPT );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_SPARE_63                     , 63  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SPARE_63   );
+
+REG64_FLD( PERV_TOD_FSM_REG_I_PATH_STATE                           , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_I_PATH_STATE );
+REG64_FLD( PERV_TOD_FSM_REG_I_PATH_STATE_LEN                       , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_I_PATH_STATE_LEN );
+REG64_FLD( PERV_TOD_FSM_REG_IS_RUNNING                             , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_IS_RUNNING );
+REG64_FLD( PERV_TOD_FSM_REG_0X24_SPARE_05_07                       , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X24_SPARE_05_07 );
+REG64_FLD( PERV_TOD_FSM_REG_0X24_SPARE_05_07_LEN                   , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X24_SPARE_05_07_LEN );
+
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_DELAY_DISABLE                  , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DELAY_DISABLE );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_DELAY_ADJUST_DISABLE           , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DELAY_ADJUST_DISABLE );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_0X06_SPARE_02_04               , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X06_SPARE_02_04 );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_0X06_SPARE_02_04_LEN           , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X06_SPARE_02_04_LEN );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_STEP_SELECT         , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_STEP_CHECK_STEP_SELECT );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION       , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_STEP_CHECK_CPS_DEVIATION );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_LEN   , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_STEP_CHECK_CPS_DEVIATION_LEN );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_CONSTANT_CPS_ENABLE , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_STEP_CHECK_CONSTANT_CPS_ENABLE );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_VALIDITY_COUNT      , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_STEP_CHECK_VALIDITY_COUNT );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_VALIDITY_COUNT_LEN  , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_STEP_CHECK_VALIDITY_COUNT_LEN );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_0X06_SPARE_16_21               , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X06_SPARE_16_21 );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_0X06_SPARE_16_21_LEN           , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X06_SPARE_16_21_LEN );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_DELAY_ADJUST_VALUE             , 22  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DELAY_ADJUST_VALUE );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_DELAY_ADJUST_VALUE_LEN         , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_DELAY_ADJUST_VALUE_LEN );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_CPS                            , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_CPS        );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_CPS_LEN                        , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_CPS_LEN    );
+
+REG64_FLD( PERV_TOD_LOAD_TOD_MOD_REG_FSM_TRIGGER                   , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_FSM_TRIGGER );
+REG64_FLD( PERV_TOD_LOAD_TOD_MOD_REG_FSM_SYNC_ENABLE               , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_FSM_SYNC_ENABLE );
+
+REG64_FLD( PERV_TOD_LOAD_TOD_REG_VALUE                             , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_VALUE      );
+REG64_FLD( PERV_TOD_LOAD_TOD_REG_VALUE_LEN                         , 60  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_VALUE_LEN  );
+REG64_FLD( PERV_TOD_LOAD_TOD_REG_WOF                               , 60  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_WOF        );
+REG64_FLD( PERV_TOD_LOAD_TOD_REG_WOF_LEN                           , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_WOF_LEN    );
+
+REG64_FLD( PERV_TOD_LOW_ORDER_STEP_REG_COUNTER_VALUE               , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_COUNTER_VALUE );
+REG64_FLD( PERV_TOD_LOW_ORDER_STEP_REG_COUNTER_VALUE_LEN           , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_COUNTER_VALUE_LEN );
+REG64_FLD( PERV_TOD_LOW_ORDER_STEP_REG_0X23_SPARE_06_07            , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X23_SPARE_06_07 );
+REG64_FLD( PERV_TOD_LOW_ORDER_STEP_REG_0X23_SPARE_06_07_LEN        , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X23_SPARE_06_07_LEN );
+
+REG64_FLD( PERV_TOD_MISC_RESET_REG_M_PATH_0_STEP_CREATE_THRESHOLD_ENABLE , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_0_STEP_CREATE_THRESHOLD_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_M_PATH_0_STEP_ALIGN_THRESHOLD_ENABLE , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_0_STEP_ALIGN_THRESHOLD_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_M_PATH_1_STEP_CREATE_THRESHOLD_ENABLE , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_1_STEP_CREATE_THRESHOLD_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_M_PATH_1_STEP_ALIGN_THRESHOLD_ENABLE , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_1_STEP_ALIGN_THRESHOLD_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_0X0B_SPARE_04_05                , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X0B_SPARE_04_05 );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_0X0B_SPARE_04_05_LEN            , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X0B_SPARE_04_05_LEN );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_DISTR_STEP_SYNC_TX_SYNC_DISABLE , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_DISTR_STEP_SYNC_TX_SYNC_DISABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_CORE_STEP_SYNC_TX_SYNC_DISABLE  , 7   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_CORE_STEP_SYNC_TX_SYNC_DISABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_PROBE_0_TOGGLE_ENABLE           , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PROBE_0_TOGGLE_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_PROBE_1_TOGGLE_ENABLE           , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PROBE_1_TOGGLE_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_PROBE_2_TOGGLE_ENABLE           , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PROBE_2_TOGGLE_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_PROBE_3_TOGGLE_ENABLE           , 11  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PROBE_3_TOGGLE_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_DISTR_STEP_SYNC_TX_DISABLE      , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_DISTR_STEP_SYNC_TX_DISABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_DISTR_STEP_SYNC_TX_TRIGGER      , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_DISTR_STEP_SYNC_TX_TRIGGER );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_CORE_STEP_SYNC_TX_ENABLE        , 14  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_CORE_STEP_SYNC_TX_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_CORE_STEP_SYNC_TX_TRIGGER       , 15  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_CORE_STEP_SYNC_TX_TRIGGER );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_TRACE_ENABLE                    , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_TRACE_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_0X0B_SPARE_17                   , 17  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X0B_SPARE_17 );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_TRACE_DATA_SELECT               , 18  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_TRACE_DATA_SELECT );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_TRACE_DATA_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_TRACE_DATA_SELECT_LEN );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_M_PATH_0_SYNC_CREATE_COUNTER_ENABLE , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_0_SYNC_CREATE_COUNTER_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_M_PATH_1_SYNC_CREATE_COUNTER_ENABLE , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_1_SYNC_CREATE_COUNTER_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_I_PATH_DELAY_TWOS_COMPL_LOAD    , 22  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_I_PATH_DELAY_ADJUST             , 23  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_DELAY_ADJUST );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE_LEN ,
+           9   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE_LEN );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_0X0B_SPARE_33_39                , 33  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X0B_SPARE_33_39 );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_0X0B_SPARE_33_39_LEN            , 7   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X0B_SPARE_33_39_LEN );
+
+REG64_FLD( PERV_TOD_MOVE_TOD_TO_TB_REG_TRIGGER                     , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_TRIGGER    );
+
+REG64_FLD( PERV_TOD_M_PATH_0_STEP_STEER_REG_MODE                   , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_MODE       );
+REG64_FLD( PERV_TOD_M_PATH_0_STEP_STEER_REG_RATE                   , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RATE       );
+REG64_FLD( PERV_TOD_M_PATH_0_STEP_STEER_REG_RATE_LEN               , 31  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RATE_LEN   );
+REG64_FLD( PERV_TOD_M_PATH_0_STEP_STEER_REG_COUNTER_LOAD_FLAG      , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_COUNTER_LOAD_FLAG );
+REG64_FLD( PERV_TOD_M_PATH_0_STEP_STEER_REG_COUNTER_LOAD_VALUE     , 33  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_COUNTER_LOAD_VALUE );
+REG64_FLD( PERV_TOD_M_PATH_0_STEP_STEER_REG_COUNTER_LOAD_VALUE_LEN , 31  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_COUNTER_LOAD_VALUE_LEN );
+
+REG64_FLD( PERV_TOD_M_PATH_1_STEP_STEER_REG_MODE                   , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_MODE       );
+REG64_FLD( PERV_TOD_M_PATH_1_STEP_STEER_REG_RATE                   , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RATE       );
+REG64_FLD( PERV_TOD_M_PATH_1_STEP_STEER_REG_RATE_LEN               , 31  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RATE_LEN   );
+REG64_FLD( PERV_TOD_M_PATH_1_STEP_STEER_REG_COUNTER_LOAD_FLAG      , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_COUNTER_LOAD_FLAG );
+REG64_FLD( PERV_TOD_M_PATH_1_STEP_STEER_REG_COUNTER_LOAD_VALUE     , 33  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_COUNTER_LOAD_VALUE );
+REG64_FLD( PERV_TOD_M_PATH_1_STEP_STEER_REG_COUNTER_LOAD_VALUE_LEN , 31  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_COUNTER_LOAD_VALUE_LEN );
+
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_0_OSC_NOT_VALID                , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_OSC_NOT_VALID );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_1_OSC_NOT_VALID                , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_OSC_NOT_VALID );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_0_STEP_ALIGN_DISABLE           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_STEP_ALIGN_DISABLE );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_1_STEP_ALIGN_DISABLE           , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_STEP_ALIGN_DISABLE );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_STEP_CREATE_DUAL_EDGE_DISABLE  , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_STEP_CREATE_DUAL_EDGE_DISABLE );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_SYNC_CREATE_SPS_SELECT         , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SYNC_CREATE_SPS_SELECT );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_SYNC_CREATE_SPS_SELECT_LEN     , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SYNC_CREATE_SPS_SELECT_LEN );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_CPS_DEVIATION     , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_STEP_CHECK_CPS_DEVIATION );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_CPS_DEVIATION_LEN , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_STEP_CHECK_CPS_DEVIATION_LEN );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_CONSTANT_CPS_ENABLE , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_STEP_CHECK_CONSTANT_CPS_ENABLE );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_VALIDITY_COUNT    , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_STEP_CHECK_VALIDITY_COUNT );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_VALIDITY_COUNT_LEN , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_STEP_CHECK_VALIDITY_COUNT_LEN );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_CPS_DEVIATION     , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_STEP_CHECK_CPS_DEVIATION );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_CPS_DEVIATION_LEN , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_STEP_CHECK_CPS_DEVIATION_LEN );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_CONSTANT_CPS_ENABLE , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_STEP_CHECK_CONSTANT_CPS_ENABLE );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_VALIDITY_COUNT    , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_STEP_CHECK_VALIDITY_COUNT );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_VALIDITY_COUNT_LEN , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_STEP_CHECK_VALIDITY_COUNT_LEN );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_0_LOCAL_STEP_MODE_ENABLE       , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_LOCAL_STEP_MODE_ENABLE );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_1_LOCAL_STEP_MODE_ENABLE       , 27  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_LOCAL_STEP_MODE_ENABLE );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_0_STEP_STEER_ENABLE            , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_STEP_STEER_ENABLE );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_1_STEP_STEER_ENABLE            , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_STEP_STEER_ENABLE );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_0X00_SPARE_30_31               , 30  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X00_SPARE_30_31 );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_0X00_SPARE_30_31_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X00_SPARE_30_31_LEN );
+
+REG64_FLD( PERV_TOD_M_PATH_STATUS_REG_0_STEP_ALIGN_THRESHOLD       , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_STEP_ALIGN_THRESHOLD );
+REG64_FLD( PERV_TOD_M_PATH_STATUS_REG_0_STEP_ALIGN_THRESHOLD_LEN   , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_STEP_ALIGN_THRESHOLD_LEN );
+REG64_FLD( PERV_TOD_M_PATH_STATUS_REG_0_CPS                        , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_CPS      );
+REG64_FLD( PERV_TOD_M_PATH_STATUS_REG_0_CPS_LEN                    , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_CPS_LEN  );
+REG64_FLD( PERV_TOD_M_PATH_STATUS_REG_1_STEP_ALIGN_THRESHOLD       , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_STEP_ALIGN_THRESHOLD );
+REG64_FLD( PERV_TOD_M_PATH_STATUS_REG_1_STEP_ALIGN_THRESHOLD_LEN   , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_STEP_ALIGN_THRESHOLD_LEN );
+REG64_FLD( PERV_TOD_M_PATH_STATUS_REG_1_CPS                        , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_CPS      );
+REG64_FLD( PERV_TOD_M_PATH_STATUS_REG_1_CPS_LEN                    , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_CPS_LEN  );
+
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_RX_SELECT                  , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_SELECT  );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_RX_SELECT_LEN              , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_0X01_SPARE_03              , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X01_SPARE_03 );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X0_TX_SELECT               , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X0_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X0_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X0_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X1_TX_SELECT               , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X1_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X1_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X1_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X2_TX_SELECT               , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X2_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X2_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X2_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X3_TX_SELECT               , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X3_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X3_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X3_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X4_TX_SELECT               , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X4_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X4_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X4_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X5_TX_SELECT               , 14  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X5_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X5_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X5_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X6_TX_SELECT               , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X6_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X6_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X6_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X7_TX_SELECT               , 18  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X7_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X7_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X7_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X0_TX_ENABLE               , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X0_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X1_TX_ENABLE               , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X1_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X2_TX_ENABLE               , 22  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X2_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X3_TX_ENABLE               , 23  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X3_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X4_TX_ENABLE               , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X4_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X5_TX_ENABLE               , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X5_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X6_TX_ENABLE               , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X6_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X7_TX_ENABLE               , 27  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X7_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_0X01_SPARE_28_31           , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X01_SPARE_28_31 );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_0X01_SPARE_28_31_LEN       , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X01_SPARE_28_31_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_I_PATH_DELAY_VALUE         , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_DELAY_VALUE );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_I_PATH_DELAY_VALUE_LEN     , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_DELAY_VALUE_LEN );
+
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_RX_SELECT                  , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_SELECT  );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_RX_SELECT_LEN              , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_0X02_SPARE_03              , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X02_SPARE_03 );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X0_TX_SELECT               , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X0_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X0_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X0_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X1_TX_SELECT               , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X1_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X1_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X1_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X2_TX_SELECT               , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X2_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X2_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X2_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X3_TX_SELECT               , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X3_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X3_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X3_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X4_TX_SELECT               , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X4_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X4_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X4_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X5_TX_SELECT               , 14  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X5_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X5_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X5_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X6_TX_SELECT               , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X6_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X6_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X6_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X7_TX_SELECT               , 18  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X7_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X7_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X7_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X0_TX_ENABLE               , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X0_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X1_TX_ENABLE               , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X1_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X2_TX_ENABLE               , 22  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X2_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X3_TX_ENABLE               , 23  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X3_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X4_TX_ENABLE               , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X4_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X5_TX_ENABLE               , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X5_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X6_TX_ENABLE               , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X6_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X7_TX_ENABLE               , 27  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X7_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_0X02_SPARE_28_31           , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X02_SPARE_28_31 );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_0X02_SPARE_28_31_LEN       , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X02_SPARE_28_31_LEN );
+
+REG64_FLD( PERV_TOD_PROBE_SELECT_REG_0_DATA                        , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_DATA     );
+REG64_FLD( PERV_TOD_PROBE_SELECT_REG_0_DATA_LEN                    , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_DATA_LEN );
+REG64_FLD( PERV_TOD_PROBE_SELECT_REG_1_DATA                        , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_DATA     );
+REG64_FLD( PERV_TOD_PROBE_SELECT_REG_1_DATA_LEN                    , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_DATA_LEN );
+REG64_FLD( PERV_TOD_PROBE_SELECT_REG_2_DATA                        , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_2_DATA     );
+REG64_FLD( PERV_TOD_PROBE_SELECT_REG_2_DATA_LEN                    , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_2_DATA_LEN );
+REG64_FLD( PERV_TOD_PROBE_SELECT_REG_3_DATA                        , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_3_DATA     );
+REG64_FLD( PERV_TOD_PROBE_SELECT_REG_3_DATA_LEN                    , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_3_DATA_LEN );
+
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_PRI_M_PATH_SELECT             , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PRI_M_PATH_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_PRI_M_S_SELECT                , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PRI_M_S_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_PRI_M_S_DRAWER_SELECT         , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PRI_M_S_DRAWER_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_PRI_S_PATH_1_STEP_CHECK_ENABLE , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PRI_S_PATH_1_STEP_CHECK_ENABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_PRI_M_PATH_0_STEP_CHECK_ENABLE , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PRI_M_PATH_0_STEP_CHECK_ENABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_PRI_M_PATH_1_STEP_CHECK_ENABLE , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PRI_M_PATH_1_STEP_CHECK_ENABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_PRI_S_PATH_0_STEP_CHECK_ENABLE , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PRI_S_PATH_0_STEP_CHECK_ENABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_PRI_I_PATH_STEP_CHECK_ENABLE  , 7   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PRI_I_PATH_STEP_CHECK_ENABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_SEC_M_PATH_SELECT             , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SEC_M_PATH_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_SEC_M_S_SELECT                , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SEC_M_S_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_SEC_M_S_DRAWER_SELECT         , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SEC_M_S_DRAWER_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_SEC_S_PATH_1_STEP_CHECK_ENABLE , 11  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SEC_S_PATH_1_STEP_CHECK_ENABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_SEC_M_PATH_0_STEP_CHECK_ENABLE , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SEC_M_PATH_0_STEP_CHECK_ENABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_SEC_M_PATH_1_STEP_CHECK_ENABLE , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SEC_M_PATH_1_STEP_CHECK_ENABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_SEC_S_PATH_0_STEP_CHECK_ENABLE , 14  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SEC_S_PATH_0_STEP_CHECK_ENABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_SEC_I_PATH_STEP_CHECK_ENABLE  , 15  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SEC_I_PATH_STEP_CHECK_ENABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_SWITCH_SYNC_ERROR_DISABLE     , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SWITCH_SYNC_ERROR_DISABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_I_PATH_STEP_CHECK_CPS_DEVIATION_X_DISABLE ,
+           17  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_STEP_CHECK_CPS_DEVIATION_X_DISABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_STEP_CHECK_ENABLE_CHICKEN_SWITCH , 18  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_STEP_CHECK_ENABLE_CHICKEN_SWITCH );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_0X07_SPARE_19                 , 19  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X07_SPARE_19 );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_0X07_SPARE_20                 , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X07_SPARE_20 );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_MISC_RESYNC_OSC_FROM          , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_MISC_RESYNC_OSC_FROM );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_0X07_SPARE_22_31              , 22  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X07_SPARE_22_31 );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_0X07_SPARE_22_31_LEN          , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X07_SPARE_22_31_LEN );
+
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_PRI_SEC_SELECT              , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_PRI_SEC_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_PRI_SEC_SELECT_LEN          , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_PRI_SEC_SELECT_LEN );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_0X08_SPARE_03               , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X08_SPARE_03 );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_0_OSC_NOT_VALID      , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_M_PATH_0_OSC_NOT_VALID );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_1_OSC_NOT_VALID      , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_M_PATH_1_OSC_NOT_VALID );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_0_STEP_CHECK_VALID   , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_M_PATH_0_STEP_CHECK_VALID );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_1_STEP_CHECK_VALID   , 7   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_M_PATH_1_STEP_CHECK_VALID );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_S_PATH_0_STEP_CHECK_VALID   , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_S_PATH_0_STEP_CHECK_VALID );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_I_PATH_STEP_CHECK_VALID     , 9   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_I_PATH_STEP_CHECK_VALID );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_S_PATH_1_STEP_CHECK_VALID   , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_S_PATH_1_STEP_CHECK_VALID );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_IS_SPECIAL                  , 11  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_IS_SPECIAL );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_PRI_M_PATH_SELECT           , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_PRI_M_PATH_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_PRI_M_S_SELECT              , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_PRI_M_S_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_PRI_M_S_DRAWER_SELECT       , 14  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_PRI_M_S_DRAWER_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_PRI_S_PATH_SELECT           , 15  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_PRI_S_PATH_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_SEC_M_PATH_SELECT           , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SEC_M_PATH_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_SEC_M_S_SELECT              , 17  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SEC_M_S_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_SEC_M_S_DRAWER_SELECT       , 18  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SEC_M_S_DRAWER_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_SEC_S_PATH_SELECT           , 19  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_SEC_S_PATH_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_IS_RUNNING                  , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_IS_RUNNING );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_IS_PRIMARY                  , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_IS_PRIMARY );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_IS_SECONDARY                , 22  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_IS_SECONDARY );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_IS_ACTIVE_MASTER            , 23  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_IS_ACTIVE_MASTER );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_IS_BACKUP_MASTER            , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_IS_BACKUP_MASTER );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_IS_SLAVE                    , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_IS_SLAVE   );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_SELECT               , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_M_PATH_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_S_PATH_SELECT               , 27  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_S_PATH_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_0_STEP_ALIGN_VALID_SWITCH , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_M_PATH_0_STEP_ALIGN_VALID_SWITCH );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_1_STEP_ALIGN_VALID_SWITCH , 29  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_M_PATH_1_STEP_ALIGN_VALID_SWITCH );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_0X08_SPARE_30               , 30  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X08_SPARE_30 );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_SWITCH_TRIGGER       , 31  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_M_PATH_SWITCH_TRIGGER );
+
+REG64_FLD( PERV_TOD_RX_TTYPE_CTRL_REG_DATA                         , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_DATA       );
+REG64_FLD( PERV_TOD_RX_TTYPE_CTRL_REG_DATA_LEN                     , 64  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_DATA_LEN   );
+
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_RX_SELECT                  , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_SELECT  );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_RX_SELECT_LEN              , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_0X03_SPARE_03              , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X03_SPARE_03 );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X0_TX_SELECT               , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X0_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X0_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X0_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X1_TX_SELECT               , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X1_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X1_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X1_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X2_TX_SELECT               , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X2_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X2_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X2_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X3_TX_SELECT               , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X3_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X3_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X3_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X4_TX_SELECT               , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X4_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X4_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X4_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X5_TX_SELECT               , 14  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X5_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X5_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X5_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X6_TX_SELECT               , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X6_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X6_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X6_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X7_TX_SELECT               , 18  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X7_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X7_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X7_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X0_TX_ENABLE               , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X0_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X1_TX_ENABLE               , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X1_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X2_TX_ENABLE               , 22  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X2_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X3_TX_ENABLE               , 23  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X3_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X4_TX_ENABLE               , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X4_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X5_TX_ENABLE               , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X5_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X6_TX_ENABLE               , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X6_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X7_TX_ENABLE               , 27  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X7_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_0X03_SPARE_28_31           , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X03_SPARE_28_31 );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_0X03_SPARE_28_31_LEN       , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X03_SPARE_28_31_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_I_PATH_DELAY_VALUE         , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_DELAY_VALUE );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_I_PATH_DELAY_VALUE_LEN     , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_PATH_DELAY_VALUE_LEN );
+
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_RX_SELECT                  , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_SELECT  );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_RX_SELECT_LEN              , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_RX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_0X04_SPARE_03              , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X04_SPARE_03 );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X0_TX_SELECT               , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X0_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X0_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X0_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X1_TX_SELECT               , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X1_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X1_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X1_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X2_TX_SELECT               , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X2_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X2_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X2_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X3_TX_SELECT               , 10  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X3_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X3_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X3_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X4_TX_SELECT               , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X4_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X4_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X4_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X5_TX_SELECT               , 14  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X5_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X5_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X5_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X6_TX_SELECT               , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X6_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X6_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X6_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X7_TX_SELECT               , 18  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X7_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X7_TX_SELECT_LEN           , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X7_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X0_TX_ENABLE               , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X0_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X1_TX_ENABLE               , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X1_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X2_TX_ENABLE               , 22  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X2_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X3_TX_ENABLE               , 23  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X3_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X4_TX_ENABLE               , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X4_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X5_TX_ENABLE               , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X5_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X6_TX_ENABLE               , 26  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X6_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X7_TX_ENABLE               , 27  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_X7_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_0X04_SPARE_28_31           , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X04_SPARE_28_31 );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_0X04_SPARE_28_31_LEN       , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X04_SPARE_28_31_LEN );
+
+REG64_FLD( PERV_TOD_START_TOD_REG_FSM_TRIGGER                      , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_FSM_TRIGGER );
+REG64_FLD( PERV_TOD_START_TOD_REG_0X22_SPARE_01                    , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X22_SPARE_01 );
+REG64_FLD( PERV_TOD_START_TOD_REG_FSM_DATA02                       , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_FSM_DATA02 );
+REG64_FLD( PERV_TOD_START_TOD_REG_0X22_SPARE_03_07                 , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X22_SPARE_03_07 );
+REG64_FLD( PERV_TOD_START_TOD_REG_0X22_SPARE_03_07_LEN             , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X22_SPARE_03_07_LEN );
+
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_PRI_SELECT                     , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_PRI_SELECT );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_0X05_SPARE_01                  , 1   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X05_SPARE_01 );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_M_CPS_ENABLE                   , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M_CPS_ENABLE );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_DISABLE            , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_REMOTE_SYNC_DISABLE );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_SEC_SELECT                     , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SEC_SELECT );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_0X05_SPARE_05                  , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X05_SPARE_05 );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR , 6   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN , 2   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_0_STEP_CHECK_CPS_DEVIATION     , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_STEP_CHECK_CPS_DEVIATION );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_0_STEP_CHECK_CPS_DEVIATION_LEN , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_STEP_CHECK_CPS_DEVIATION_LEN );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_0_STEP_CHECK_CONSTANT_CPS_ENABLE , 12  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_STEP_CHECK_CONSTANT_CPS_ENABLE );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_0_STEP_CHECK_VALIDITY_COUNT    , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_STEP_CHECK_VALIDITY_COUNT );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_0_STEP_CHECK_VALIDITY_COUNT_LEN , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_STEP_CHECK_VALIDITY_COUNT_LEN );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_1_STEP_CHECK_CPS_DEVIATION     , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_STEP_CHECK_CPS_DEVIATION );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_1_STEP_CHECK_CPS_DEVIATION_LEN , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_STEP_CHECK_CPS_DEVIATION_LEN );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_1_STEP_CHECK_CONSTANT_CPS_ENABLE , 20  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_STEP_CHECK_CONSTANT_CPS_ENABLE );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_1_STEP_CHECK_VALIDITY_COUNT    , 21  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_STEP_CHECK_VALIDITY_COUNT );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_1_STEP_CHECK_VALIDITY_COUNT_LEN , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_STEP_CHECK_VALIDITY_COUNT_LEN );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_ERROR_DISABLE      , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_REMOTE_SYNC_ERROR_DISABLE );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_CHECK_M_CPS_DISABLE , 25  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_REMOTE_SYNC_CHECK_M_CPS_DISABLE );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR ,
+           26  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR_LEN ,
+           2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR_LEN );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_CHECK_CPS_DEVIATION , 28  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_CHECK_CPS_DEVIATION_LEN , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_LEN );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_MISS_COUNT_MAX     , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_REMOTE_SYNC_MISS_COUNT_MAX );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_MISS_COUNT_MAX_LEN , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_REMOTE_SYNC_MISS_COUNT_MAX_LEN );
+
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_M_0_STEP_ALIGN_FSM_STATE     , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M_0_STEP_ALIGN_FSM_STATE );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_M_0_STEP_ALIGN_FSM_STATE_LEN , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M_0_STEP_ALIGN_FSM_STATE_LEN );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_M_1_STEP_ALIGN_FSM_STATE     , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M_1_STEP_ALIGN_FSM_STATE );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_M_1_STEP_ALIGN_FSM_STATE_LEN , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_M_1_STEP_ALIGN_FSM_STATE_LEN );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_I_DELAY_ADJUST_RATIO         , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_DELAY_ADJUST_RATIO );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_I_DELAY_ADJUST_RATIO_LEN     , 5   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_I_DELAY_ADJUST_RATIO_LEN );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_0X0A_SPARE_13_15             , 13  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X0A_SPARE_13_15 );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_0X0A_SPARE_13_15_LEN         , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0X0A_SPARE_13_15_LEN );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_0_CPS                        , 16  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_CPS      );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_0_CPS_LEN                    , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_CPS_LEN  );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_1_CPS                        , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_CPS      );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_1_CPS_LEN                    , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_CPS_LEN  );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_0_REMOTE_SYNC_LATE_SYNC_COUNT , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_REMOTE_SYNC_LATE_SYNC_COUNT );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_0_REMOTE_SYNC_LATE_SYNC_COUNT_LEN , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_0_REMOTE_SYNC_LATE_SYNC_COUNT_LEN );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_1_REMOTE_SYNC_LATE_SYNC_COUNT , 40  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_REMOTE_SYNC_LATE_SYNC_COUNT );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_1_REMOTE_SYNC_LATE_SYNC_COUNT_LEN , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_1_REMOTE_SYNC_LATE_SYNC_COUNT_LEN );
+
+REG64_FLD( PERV_TOD_TIMER_REG_VALUE                                , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_VALUE      );
+REG64_FLD( PERV_TOD_TIMER_REG_VALUE_LEN                            , 60  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_VALUE_LEN  );
+REG64_FLD( PERV_TOD_TIMER_REG_0X0D_SPARE_60_62                     , 60  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X0D_SPARE_60_62 );
+REG64_FLD( PERV_TOD_TIMER_REG_0X0D_SPARE_60_62_LEN                 , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X0D_SPARE_60_62_LEN );
+REG64_FLD( PERV_TOD_TIMER_REG_STATUS                               , 63  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_STATUS     );
+
+REG64_FLD( PERV_TOD_TRACE_DATA_1_REG_SET                           , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SET        );
+REG64_FLD( PERV_TOD_TRACE_DATA_1_REG_SET_LEN                       , 64  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SET_LEN    );
+
+REG64_FLD( PERV_TOD_TRACE_DATA_2_REG_SET                           , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SET        );
+REG64_FLD( PERV_TOD_TRACE_DATA_2_REG_SET_LEN                       , 64  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SET_LEN    );
+
+REG64_FLD( PERV_TOD_TRACE_DATA_3_REG_SET                           , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SET        );
+REG64_FLD( PERV_TOD_TRACE_DATA_3_REG_SET_LEN                       , 64  ,
+           SH_UNT_PERV     , SH_ACS_SCOM_RW  , SH_FLD_SET_LEN    );
+
+REG64_FLD( PERV_TOD_TX_TTYPE_0_REG_TRIGGER                         , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_TRIGGER    );
+
+REG64_FLD( PERV_TOD_TX_TTYPE_1_REG_TRIGGER                         , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_TRIGGER    );
+
+REG64_FLD( PERV_TOD_TX_TTYPE_2_REG_TRIGGER                         , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_TRIGGER    );
+
+REG64_FLD( PERV_TOD_TX_TTYPE_3_REG_TRIGGER                         , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_TRIGGER    );
+
+REG64_FLD( PERV_TOD_TX_TTYPE_4_REG_TRIGGER                         , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_TRIGGER    );
+
+REG64_FLD( PERV_TOD_TX_TTYPE_5_REG_TRIGGER                         , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM_WO  , SH_FLD_TRIGGER    );
+
+REG64_FLD( PERV_TOD_TX_TTYPE_CTRL_REG_MOVE_TO_TB_CORE_ADDRESS      , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MOVE_TO_TB_CORE_ADDRESS );
+REG64_FLD( PERV_TOD_TX_TTYPE_CTRL_REG_MOVE_TO_TB_CORE_ADDRESS_LEN  , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MOVE_TO_TB_CORE_ADDRESS_LEN );
+REG64_FLD( PERV_TOD_TX_TTYPE_CTRL_REG_MOVE_TO_TB_CORE_ID           , 24  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MOVE_TO_TB_CORE_ID );
+REG64_FLD( PERV_TOD_TX_TTYPE_CTRL_REG_MOVE_TO_TB_CORE_ID_LEN       , 8   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MOVE_TO_TB_CORE_ID_LEN );
+REG64_FLD( PERV_TOD_TX_TTYPE_CTRL_REG_4_SEND_MODE                  , 32  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_4_SEND_MODE );
+REG64_FLD( PERV_TOD_TX_TTYPE_CTRL_REG_4_SEND_ENABLE                , 33  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_4_SEND_ENABLE );
+REG64_FLD( PERV_TOD_TX_TTYPE_CTRL_REG_0X27_SPARE_34                , 34  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X27_SPARE_34 );
+REG64_FLD( PERV_TOD_TX_TTYPE_CTRL_REG_MOVE_TO_TB_CORE_ADDRESS_ENABLE , 35  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_MOVE_TO_TB_CORE_ADDRESS_ENABLE );
+REG64_FLD( PERV_TOD_TX_TTYPE_CTRL_REG_0X27_SPARE_36                , 36  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_0X27_SPARE_36 );
+REG64_FLD( PERV_TOD_TX_TTYPE_CTRL_REG_PIB_FSM_STATE                , 37  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_PIB_FSM_STATE );
+REG64_FLD( PERV_TOD_TX_TTYPE_CTRL_REG_PIB_FSM_STATE_LEN            , 3   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_PIB_FSM_STATE_LEN );
+
+REG64_FLD( PERV_TOD_VALUE_REG_VALUE                                , 0   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_VALUE      );
+REG64_FLD( PERV_TOD_VALUE_REG_VALUE_LEN                            , 60  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_VALUE_LEN  );
+REG64_FLD( PERV_TOD_VALUE_REG_WOF_COUNTER                          , 60  ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_WOF_COUNTER );
+REG64_FLD( PERV_TOD_VALUE_REG_WOF_COUNTER_LEN                      , 4   ,
+           SH_UNT_PERV     , SH_ACS_SCOM     , SH_FLD_WOF_COUNTER_LEN );
+
+REG32_FLD( PERV_FSI2PIB_TRUE_MASK_REG                              , 0   ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_REG        );
+REG32_FLD( PERV_FSI2PIB_TRUE_MASK_REG_LEN                          , 32  ,
+           SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_REG_LEN    );
+
+REG32_FLD( PERV_FSISHIFT_TRUE_MASK_REG                             , 0   ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REG        );
+REG32_FLD( PERV_FSISHIFT_TRUE_MASK_REG_LEN                         , 32  ,
+           SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REG_LEN    );
+
+REG32_FLD( PERV_FSII2C_WATER_MARK_REGISTER_WATERMARK_REG           , 16  ,
+           SH_UNT_PERV_FSII2C, SH_ACS_SCOM     , SH_FLD_WATERMARK_REG );
+REG32_FLD( PERV_FSII2C_WATER_MARK_REGISTER_WATERMARK_REG_LEN       , 16  ,
+           SH_UNT_PERV_FSII2C, SH_ACS_SCOM     , SH_FLD_WATERMARK_REG_LEN );
+
+REG64_FLD( PERV_1_XSTOP1_MASK_B                                    , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_MASK_B     );
+REG64_FLD( PERV_1_XSTOP1_KEEP_EDRAM_ENABLED_ON                     , 1   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_KEEP_EDRAM_ENABLED_ON );
+REG64_FLD( PERV_1_XSTOP1_TRIGGER_OPCG_ON                           , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_TRIGGER_OPCG_ON );
+REG64_FLD( PERV_1_XSTOP1_WAIT_ALLWAYS                              , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_WAIT_ALLWAYS );
+REG64_FLD( PERV_1_XSTOP1_PERV                                      , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PERV       );
+REG64_FLD( PERV_1_XSTOP1_UNIT1                                     , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT1      );
+REG64_FLD( PERV_1_XSTOP1_UNIT2                                     , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT2      );
+REG64_FLD( PERV_1_XSTOP1_UNIT3                                     , 7   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT3      );
+REG64_FLD( PERV_1_XSTOP1_UNIT4                                     , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT4      );
+REG64_FLD( PERV_1_XSTOP1_UNIT5                                     , 9   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT5      );
+REG64_FLD( PERV_1_XSTOP1_UNIT6                                     , 10  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT6      );
+REG64_FLD( PERV_1_XSTOP1_UNIT7                                     , 11  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT7      );
+REG64_FLD( PERV_1_XSTOP1_UNIT8                                     , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT8      );
+REG64_FLD( PERV_1_XSTOP1_UNIT9                                     , 13  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT9      );
+REG64_FLD( PERV_1_XSTOP1_UNIT10                                    , 14  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT10     );
+REG64_FLD( PERV_1_XSTOP1_WAIT_CYCLES                               , 48  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_WAIT_CYCLES );
+REG64_FLD( PERV_1_XSTOP1_WAIT_CYCLES_LEN                           , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( PERV_1_XSTOP2_MASK_B                                    , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_MASK_B     );
+REG64_FLD( PERV_1_XSTOP2_KEEP_EDRAM_ENABLED_ON                     , 1   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_KEEP_EDRAM_ENABLED_ON );
+REG64_FLD( PERV_1_XSTOP2_TRIGGER_OPCG_ON                           , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_TRIGGER_OPCG_ON );
+REG64_FLD( PERV_1_XSTOP2_WAIT_ALLWAYS                              , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_WAIT_ALLWAYS );
+REG64_FLD( PERV_1_XSTOP2_PERV                                      , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PERV       );
+REG64_FLD( PERV_1_XSTOP2_UNIT1                                     , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT1      );
+REG64_FLD( PERV_1_XSTOP2_UNIT2                                     , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT2      );
+REG64_FLD( PERV_1_XSTOP2_UNIT3                                     , 7   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT3      );
+REG64_FLD( PERV_1_XSTOP2_UNIT4                                     , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT4      );
+REG64_FLD( PERV_1_XSTOP2_UNIT5                                     , 9   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT5      );
+REG64_FLD( PERV_1_XSTOP2_UNIT6                                     , 10  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT6      );
+REG64_FLD( PERV_1_XSTOP2_UNIT7                                     , 11  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT7      );
+REG64_FLD( PERV_1_XSTOP2_UNIT8                                     , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT8      );
+REG64_FLD( PERV_1_XSTOP2_UNIT9                                     , 13  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT9      );
+REG64_FLD( PERV_1_XSTOP2_UNIT10                                    , 14  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT10     );
+REG64_FLD( PERV_1_XSTOP2_WAIT_CYCLES                               , 48  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_WAIT_CYCLES );
+REG64_FLD( PERV_1_XSTOP2_WAIT_CYCLES_LEN                           , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( PERV_1_XSTOP3_MASK_B                                    , 0   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_MASK_B     );
+REG64_FLD( PERV_1_XSTOP3_KEEP_EDRAM_ENABLED_ON                     , 1   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_KEEP_EDRAM_ENABLED_ON );
+REG64_FLD( PERV_1_XSTOP3_TRIGGER_OPCG_ON                           , 2   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_TRIGGER_OPCG_ON );
+REG64_FLD( PERV_1_XSTOP3_WAIT_ALLWAYS                              , 3   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_WAIT_ALLWAYS );
+REG64_FLD( PERV_1_XSTOP3_PERV                                      , 4   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_PERV       );
+REG64_FLD( PERV_1_XSTOP3_UNIT1                                     , 5   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT1      );
+REG64_FLD( PERV_1_XSTOP3_UNIT2                                     , 6   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT2      );
+REG64_FLD( PERV_1_XSTOP3_UNIT3                                     , 7   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT3      );
+REG64_FLD( PERV_1_XSTOP3_UNIT4                                     , 8   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT4      );
+REG64_FLD( PERV_1_XSTOP3_UNIT5                                     , 9   ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT5      );
+REG64_FLD( PERV_1_XSTOP3_UNIT6                                     , 10  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT6      );
+REG64_FLD( PERV_1_XSTOP3_UNIT7                                     , 11  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT7      );
+REG64_FLD( PERV_1_XSTOP3_UNIT8                                     , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT8      );
+REG64_FLD( PERV_1_XSTOP3_UNIT9                                     , 13  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT9      );
+REG64_FLD( PERV_1_XSTOP3_UNIT10                                    , 14  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_UNIT10     );
+REG64_FLD( PERV_1_XSTOP3_WAIT_CYCLES                               , 48  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_WAIT_CYCLES );
+REG64_FLD( PERV_1_XSTOP3_WAIT_CYCLES_LEN                           , 12  ,
+           SH_UNT_PERV_1   , SH_ACS_SCOM     , SH_FLD_WAIT_CYCLES_LEN );
+
+#endif
+
diff --git a/src/ppe/importtemp/common/include/perv_scom_addresses_fld_fixes.H b/src/ppe/importtemp/common/include/perv_scom_addresses_fld_fixes.H
new file mode 100644
index 0000000..d11eaca
--- /dev/null
+++ b/src/ppe/importtemp/common/include/perv_scom_addresses_fld_fixes.H
@@ -0,0 +1,49 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/common/include/perv_scom_addresses_fld_fixes.H $ */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file perv_scom_addresses_fld_fixes.H
+/// @brief The *scom_addresses_fld.H files are generated form figtree,
+///        but the figree can be wrong.  This file is included in
+///        *_scom_addresses_fld.H and allows incorrect constants to be
+///        fixed manually.
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: ? <?>
+// *HWP Team: SAO
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#ifndef __PERV_SCOM_ADDRESSES_FLD_FIXES_H
+#define __PERV_SCOM_ADDRESSES_FLD_FIXES_H
+
+//Example
+//Copy the whole line from the *scom_addresses_fld.H file.  Then add FIX in front of REG
+//and add another paramter that is the new value you want.
+//
+//FIXREG64_FLD( PU_ALTD_CMD_REG_FBC_WITH_TM_QUIESCE, 24, SH_UNT, SH_ACS_SCOM, SH_FLD_FBC_WITH_TM_QUIESCE,
+//              12);
+
+
+#endif
diff --git a/src/ppe/importtemp/common/include/scom_template_consts.H b/src/ppe/importtemp/common/include/scom_template_consts.H
new file mode 100644
index 0000000..f452b95
--- /dev/null
+++ b/src/ppe/importtemp/common/include/scom_template_consts.H
@@ -0,0 +1,14532 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/common/include/scom_template_consts.H $    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file scom_template_consts.H
+/// @brief  File generated to contain constants used to define templates
+///         for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+#ifndef __SCOM_TEMPLATE_CONSTS_H
+#define __SCOM_TEMPLATE_CONSTS_H
+
+const static uint64_t SH_UNT = 0;
+const static uint64_t SH_UNT_C = 1;
+const static uint64_t SH_UNT_CAPP = 2;
+const static uint64_t SH_UNT_CAPP_0 = 3;
+const static uint64_t SH_UNT_CAPP_1 = 4;
+const static uint64_t SH_UNT_C_0 = 5;
+const static uint64_t SH_UNT_C_1 = 6;
+const static uint64_t SH_UNT_C_10 = 7;
+const static uint64_t SH_UNT_C_11 = 8;
+const static uint64_t SH_UNT_C_12 = 9;
+const static uint64_t SH_UNT_C_13 = 10;
+const static uint64_t SH_UNT_C_14 = 11;
+const static uint64_t SH_UNT_C_15 = 12;
+const static uint64_t SH_UNT_C_16 = 13;
+const static uint64_t SH_UNT_C_17 = 14;
+const static uint64_t SH_UNT_C_18 = 15;
+const static uint64_t SH_UNT_C_19 = 16;
+const static uint64_t SH_UNT_C_2 = 17;
+const static uint64_t SH_UNT_C_20 = 18;
+const static uint64_t SH_UNT_C_21 = 19;
+const static uint64_t SH_UNT_C_22 = 20;
+const static uint64_t SH_UNT_C_23 = 21;
+const static uint64_t SH_UNT_C_3 = 22;
+const static uint64_t SH_UNT_C_4 = 23;
+const static uint64_t SH_UNT_C_5 = 24;
+const static uint64_t SH_UNT_C_6 = 25;
+const static uint64_t SH_UNT_C_7 = 26;
+const static uint64_t SH_UNT_C_8 = 27;
+const static uint64_t SH_UNT_C_9 = 28;
+const static uint64_t SH_UNT_EQ = 29;
+const static uint64_t SH_UNT_EQ_0 = 30;
+const static uint64_t SH_UNT_EQ_1 = 31;
+const static uint64_t SH_UNT_EQ_2 = 32;
+const static uint64_t SH_UNT_EQ_3 = 33;
+const static uint64_t SH_UNT_EQ_4 = 34;
+const static uint64_t SH_UNT_EQ_5 = 35;
+const static uint64_t SH_UNT_EX = 36;
+const static uint64_t SH_UNT_EX_0 = 37;
+const static uint64_t SH_UNT_EX_0_CHTMLBS0 = 38;
+const static uint64_t SH_UNT_EX_0_CHTMLBS1 = 39;
+const static uint64_t SH_UNT_EX_0_L2 = 40;
+const static uint64_t SH_UNT_EX_0_L3 = 41;
+const static uint64_t SH_UNT_EX_1 = 42;
+const static uint64_t SH_UNT_EX_10 = 43;
+const static uint64_t SH_UNT_EX_10_CHTMLBS0 = 44;
+const static uint64_t SH_UNT_EX_10_CHTMLBS1 = 45;
+const static uint64_t SH_UNT_EX_10_L2 = 46;
+const static uint64_t SH_UNT_EX_10_L3 = 47;
+const static uint64_t SH_UNT_EX_11 = 48;
+const static uint64_t SH_UNT_EX_11_CHTMLBS0 = 49;
+const static uint64_t SH_UNT_EX_11_CHTMLBS1 = 50;
+const static uint64_t SH_UNT_EX_11_L2 = 51;
+const static uint64_t SH_UNT_EX_11_L3 = 52;
+const static uint64_t SH_UNT_EX_1_CHTMLBS0 = 53;
+const static uint64_t SH_UNT_EX_1_CHTMLBS1 = 54;
+const static uint64_t SH_UNT_EX_1_L2 = 55;
+const static uint64_t SH_UNT_EX_1_L3 = 56;
+const static uint64_t SH_UNT_EX_2 = 57;
+const static uint64_t SH_UNT_EX_2_CHTMLBS0 = 58;
+const static uint64_t SH_UNT_EX_2_CHTMLBS1 = 59;
+const static uint64_t SH_UNT_EX_2_L2 = 60;
+const static uint64_t SH_UNT_EX_2_L3 = 61;
+const static uint64_t SH_UNT_EX_3 = 62;
+const static uint64_t SH_UNT_EX_3_CHTMLBS0 = 63;
+const static uint64_t SH_UNT_EX_3_CHTMLBS1 = 64;
+const static uint64_t SH_UNT_EX_3_L2 = 65;
+const static uint64_t SH_UNT_EX_3_L3 = 66;
+const static uint64_t SH_UNT_EX_4 = 67;
+const static uint64_t SH_UNT_EX_4_CHTMLBS0 = 68;
+const static uint64_t SH_UNT_EX_4_CHTMLBS1 = 69;
+const static uint64_t SH_UNT_EX_4_L2 = 70;
+const static uint64_t SH_UNT_EX_4_L3 = 71;
+const static uint64_t SH_UNT_EX_5 = 72;
+const static uint64_t SH_UNT_EX_5_CHTMLBS0 = 73;
+const static uint64_t SH_UNT_EX_5_CHTMLBS1 = 74;
+const static uint64_t SH_UNT_EX_5_L2 = 75;
+const static uint64_t SH_UNT_EX_5_L3 = 76;
+const static uint64_t SH_UNT_EX_6 = 77;
+const static uint64_t SH_UNT_EX_6_CHTMLBS0 = 78;
+const static uint64_t SH_UNT_EX_6_CHTMLBS1 = 79;
+const static uint64_t SH_UNT_EX_6_L2 = 80;
+const static uint64_t SH_UNT_EX_6_L3 = 81;
+const static uint64_t SH_UNT_EX_7 = 82;
+const static uint64_t SH_UNT_EX_7_CHTMLBS0 = 83;
+const static uint64_t SH_UNT_EX_7_CHTMLBS1 = 84;
+const static uint64_t SH_UNT_EX_7_L2 = 85;
+const static uint64_t SH_UNT_EX_7_L3 = 86;
+const static uint64_t SH_UNT_EX_8 = 87;
+const static uint64_t SH_UNT_EX_8_CHTMLBS0 = 88;
+const static uint64_t SH_UNT_EX_8_CHTMLBS1 = 89;
+const static uint64_t SH_UNT_EX_8_L2 = 90;
+const static uint64_t SH_UNT_EX_8_L3 = 91;
+const static uint64_t SH_UNT_EX_9 = 92;
+const static uint64_t SH_UNT_EX_9_CHTMLBS0 = 93;
+const static uint64_t SH_UNT_EX_9_CHTMLBS1 = 94;
+const static uint64_t SH_UNT_EX_9_L2 = 95;
+const static uint64_t SH_UNT_EX_9_L3 = 96;
+const static uint64_t SH_UNT_EX_CHTMLBS0 = 97;
+const static uint64_t SH_UNT_EX_CHTMLBS1 = 98;
+const static uint64_t SH_UNT_EX_L2 = 99;
+const static uint64_t SH_UNT_EX_L3 = 100;
+const static uint64_t SH_UNT_MCA = 101;
+const static uint64_t SH_UNT_MCA_0 = 102;
+const static uint64_t SH_UNT_MCA_0_WDF = 103;
+const static uint64_t SH_UNT_MCA_0_WREITE = 104;
+const static uint64_t SH_UNT_MCA_1 = 105;
+const static uint64_t SH_UNT_MCA_1_WDF = 106;
+const static uint64_t SH_UNT_MCA_1_WREITE = 107;
+const static uint64_t SH_UNT_MCA_2 = 108;
+const static uint64_t SH_UNT_MCA_2_WDF = 109;
+const static uint64_t SH_UNT_MCA_2_WREITE = 110;
+const static uint64_t SH_UNT_MCA_3 = 111;
+const static uint64_t SH_UNT_MCA_3_WDF = 112;
+const static uint64_t SH_UNT_MCA_3_WREITE = 113;
+const static uint64_t SH_UNT_MCA_4 = 114;
+const static uint64_t SH_UNT_MCA_4_WDF = 115;
+const static uint64_t SH_UNT_MCA_4_WREITE = 116;
+const static uint64_t SH_UNT_MCA_5 = 117;
+const static uint64_t SH_UNT_MCA_5_WDF = 118;
+const static uint64_t SH_UNT_MCA_5_WREITE = 119;
+const static uint64_t SH_UNT_MCA_6 = 120;
+const static uint64_t SH_UNT_MCA_6_WDF = 121;
+const static uint64_t SH_UNT_MCA_6_WREITE = 122;
+const static uint64_t SH_UNT_MCA_7 = 123;
+const static uint64_t SH_UNT_MCA_7_WDF = 124;
+const static uint64_t SH_UNT_MCA_7_WREITE = 125;
+const static uint64_t SH_UNT_MCA_WDF = 126;
+const static uint64_t SH_UNT_MCA_WREITE = 127;
+const static uint64_t SH_UNT_MCBIST = 128;
+const static uint64_t SH_UNT_MCBIST_0 = 129;
+const static uint64_t SH_UNT_MCBIST_1 = 130;
+const static uint64_t SH_UNT_MCS = 131;
+const static uint64_t SH_UNT_MCS_0 = 132;
+const static uint64_t SH_UNT_MCS_0_PORT02 = 133;
+const static uint64_t SH_UNT_MCS_0_PORT13 = 134;
+const static uint64_t SH_UNT_MCS_1 = 135;
+const static uint64_t SH_UNT_MCS_1_PORT02 = 136;
+const static uint64_t SH_UNT_MCS_1_PORT13 = 137;
+const static uint64_t SH_UNT_MCS_2 = 138;
+const static uint64_t SH_UNT_MCS_2_PORT02 = 139;
+const static uint64_t SH_UNT_MCS_2_PORT13 = 140;
+const static uint64_t SH_UNT_MCS_3 = 141;
+const static uint64_t SH_UNT_MCS_3_PORT02 = 142;
+const static uint64_t SH_UNT_MCS_3_PORT13 = 143;
+const static uint64_t SH_UNT_MCS_PORT02 = 144;
+const static uint64_t SH_UNT_MCS_PORT13 = 145;
+const static uint64_t SH_UNT_OBUS = 146;
+const static uint64_t SH_UNT_OBUS_0 = 147;
+const static uint64_t SH_UNT_OBUS_3 = 148;
+const static uint64_t SH_UNT_PEC = 149;
+const static uint64_t SH_UNT_PEC_0 = 150;
+const static uint64_t SH_UNT_PEC_0_STACK0 = 151;
+const static uint64_t SH_UNT_PEC_0_STACK1 = 152;
+const static uint64_t SH_UNT_PEC_0_STACK2 = 153;
+const static uint64_t SH_UNT_PEC_1 = 154;
+const static uint64_t SH_UNT_PEC_1_STACK0 = 155;
+const static uint64_t SH_UNT_PEC_1_STACK1 = 156;
+const static uint64_t SH_UNT_PEC_1_STACK2 = 157;
+const static uint64_t SH_UNT_PEC_2 = 158;
+const static uint64_t SH_UNT_PEC_2_STACK0 = 159;
+const static uint64_t SH_UNT_PEC_2_STACK1 = 160;
+const static uint64_t SH_UNT_PEC_2_STACK2 = 161;
+const static uint64_t SH_UNT_PEC_STACK0 = 162;
+const static uint64_t SH_UNT_PEC_STACK1 = 163;
+const static uint64_t SH_UNT_PEC_STACK2 = 164;
+const static uint64_t SH_UNT_PERV = 165;
+const static uint64_t SH_UNT_PERV_0 = 166;
+const static uint64_t SH_UNT_PERV_0_FSII2C = 167;
+const static uint64_t SH_UNT_PERV_1 = 168;
+const static uint64_t SH_UNT_PERV_12 = 169;
+const static uint64_t SH_UNT_PERV_13 = 170;
+const static uint64_t SH_UNT_PERV_14 = 171;
+const static uint64_t SH_UNT_PERV_15 = 172;
+const static uint64_t SH_UNT_PERV_16 = 173;
+const static uint64_t SH_UNT_PERV_17 = 174;
+const static uint64_t SH_UNT_PERV_18 = 175;
+const static uint64_t SH_UNT_PERV_19 = 176;
+const static uint64_t SH_UNT_PERV_2 = 177;
+const static uint64_t SH_UNT_PERV_20 = 178;
+const static uint64_t SH_UNT_PERV_21 = 179;
+const static uint64_t SH_UNT_PERV_3 = 180;
+const static uint64_t SH_UNT_PERV_32 = 181;
+const static uint64_t SH_UNT_PERV_33 = 182;
+const static uint64_t SH_UNT_PERV_34 = 183;
+const static uint64_t SH_UNT_PERV_35 = 184;
+const static uint64_t SH_UNT_PERV_36 = 185;
+const static uint64_t SH_UNT_PERV_37 = 186;
+const static uint64_t SH_UNT_PERV_38 = 187;
+const static uint64_t SH_UNT_PERV_39 = 188;
+const static uint64_t SH_UNT_PERV_4 = 189;
+const static uint64_t SH_UNT_PERV_40 = 190;
+const static uint64_t SH_UNT_PERV_41 = 191;
+const static uint64_t SH_UNT_PERV_42 = 192;
+const static uint64_t SH_UNT_PERV_43 = 193;
+const static uint64_t SH_UNT_PERV_44 = 194;
+const static uint64_t SH_UNT_PERV_45 = 195;
+const static uint64_t SH_UNT_PERV_46 = 196;
+const static uint64_t SH_UNT_PERV_47 = 197;
+const static uint64_t SH_UNT_PERV_48 = 198;
+const static uint64_t SH_UNT_PERV_49 = 199;
+const static uint64_t SH_UNT_PERV_5 = 200;
+const static uint64_t SH_UNT_PERV_50 = 201;
+const static uint64_t SH_UNT_PERV_51 = 202;
+const static uint64_t SH_UNT_PERV_52 = 203;
+const static uint64_t SH_UNT_PERV_53 = 204;
+const static uint64_t SH_UNT_PERV_54 = 205;
+const static uint64_t SH_UNT_PERV_55 = 206;
+const static uint64_t SH_UNT_PERV_6 = 207;
+const static uint64_t SH_UNT_PERV_7 = 208;
+const static uint64_t SH_UNT_PERV_8 = 209;
+const static uint64_t SH_UNT_PERV_9 = 210;
+const static uint64_t SH_UNT_PERV_FSB = 211;
+const static uint64_t SH_UNT_PERV_FSI2PIB = 212;
+const static uint64_t SH_UNT_PERV_FSII2C = 213;
+const static uint64_t SH_UNT_PERV_FSISHIFT = 214;
+const static uint64_t SH_UNT_PU_CME0 = 215;
+const static uint64_t SH_UNT_PU_CME1 = 216;
+const static uint64_t SH_UNT_PU_CME10 = 217;
+const static uint64_t SH_UNT_PU_CME11 = 218;
+const static uint64_t SH_UNT_PU_CME2 = 219;
+const static uint64_t SH_UNT_PU_CME3 = 220;
+const static uint64_t SH_UNT_PU_CME4 = 221;
+const static uint64_t SH_UNT_PU_CME5 = 222;
+const static uint64_t SH_UNT_PU_CME6 = 223;
+const static uint64_t SH_UNT_PU_CME7 = 224;
+const static uint64_t SH_UNT_PU_CME8 = 225;
+const static uint64_t SH_UNT_PU_CME9 = 226;
+const static uint64_t SH_UNT_PU_GPE0 = 227;
+const static uint64_t SH_UNT_PU_GPE1 = 228;
+const static uint64_t SH_UNT_PU_GPE2 = 229;
+const static uint64_t SH_UNT_PU_GPE3 = 230;
+const static uint64_t SH_UNT_PU_GPE5 = 231;
+const static uint64_t SH_UNT_PU_GPE6 = 232;
+const static uint64_t SH_UNT_PU_HTM0 = 233;
+const static uint64_t SH_UNT_PU_HTM1 = 234;
+const static uint64_t SH_UNT_PU_IOP0 = 235;
+const static uint64_t SH_UNT_PU_IOP1 = 236;
+const static uint64_t SH_UNT_PU_IOP2 = 237;
+const static uint64_t SH_UNT_PU_MCD1 = 238;
+const static uint64_t SH_UNT_PU_NMMU = 239;
+const static uint64_t SH_UNT_PU_NPU0 = 240;
+const static uint64_t SH_UNT_PU_NPU0_CTL = 241;
+const static uint64_t SH_UNT_PU_NPU0_DAT = 242;
+const static uint64_t SH_UNT_PU_NPU0_NTL0 = 243;
+const static uint64_t SH_UNT_PU_NPU0_NTL1 = 244;
+const static uint64_t SH_UNT_PU_NPU0_SM0 = 245;
+const static uint64_t SH_UNT_PU_NPU0_SM1 = 246;
+const static uint64_t SH_UNT_PU_NPU0_SM2 = 247;
+const static uint64_t SH_UNT_PU_NPU0_SM3 = 248;
+const static uint64_t SH_UNT_PU_NPU1 = 249;
+const static uint64_t SH_UNT_PU_NPU1_CTL = 250;
+const static uint64_t SH_UNT_PU_NPU1_DAT = 251;
+const static uint64_t SH_UNT_PU_NPU1_NTL0 = 252;
+const static uint64_t SH_UNT_PU_NPU1_NTL1 = 253;
+const static uint64_t SH_UNT_PU_NPU1_SM0 = 254;
+const static uint64_t SH_UNT_PU_NPU1_SM1 = 255;
+const static uint64_t SH_UNT_PU_NPU1_SM2 = 256;
+const static uint64_t SH_UNT_PU_NPU1_SM3 = 257;
+const static uint64_t SH_UNT_PU_NPU2 = 258;
+const static uint64_t SH_UNT_PU_NPU2_CTL = 259;
+const static uint64_t SH_UNT_PU_NPU2_DAT = 260;
+const static uint64_t SH_UNT_PU_NPU2_NTL0 = 261;
+const static uint64_t SH_UNT_PU_NPU2_NTL1 = 262;
+const static uint64_t SH_UNT_PU_NPU2_SM0 = 263;
+const static uint64_t SH_UNT_PU_NPU2_SM1 = 264;
+const static uint64_t SH_UNT_PU_NPU2_SM2 = 265;
+const static uint64_t SH_UNT_PU_NPU2_SM3 = 266;
+const static uint64_t SH_UNT_PU_NPU_CTL = 267;
+const static uint64_t SH_UNT_PU_NPU_DAT = 268;
+const static uint64_t SH_UNT_PU_NPU_SM0 = 269;
+const static uint64_t SH_UNT_PU_NPU_SM1 = 270;
+const static uint64_t SH_UNT_PU_NPU_SM2 = 271;
+const static uint64_t SH_UNT_PU_OTPROM0 = 272;
+const static uint64_t SH_UNT_PU_OTPROM1 = 273;
+const static uint64_t SH_UNT_PU_PBAIB0 = 274;
+const static uint64_t SH_UNT_PU_PBAIB1 = 275;
+const static uint64_t SH_UNT_PU_PBAIB2 = 276;
+const static uint64_t SH_UNT_PU_PBAIB_STACK0 = 277;
+const static uint64_t SH_UNT_PU_PBAIB_STACK1 = 278;
+const static uint64_t SH_UNT_PU_PBAIB_STACK2 = 279;
+const static uint64_t SH_UNT_PU_PBAIB_STACK3 = 280;
+const static uint64_t SH_UNT_PU_PBAIB_STACK4 = 281;
+const static uint64_t SH_UNT_PU_PBAIB_STACK5 = 282;
+const static uint64_t SH_UNT_PU_PBAIB_STACK6 = 283;
+const static uint64_t SH_UNT_PU_PBAIB_STACK7 = 284;
+const static uint64_t SH_UNT_PU_PBAIB_STACK8 = 285;
+const static uint64_t SH_UNT_PU_PIB2OPB0 = 286;
+const static uint64_t SH_UNT_PU_PIB2OPB1 = 287;
+const static uint64_t SH_UNT_XBUS_1 = 288;
+const static uint64_t SH_UNT_XBUS_2 = 289;
+
+
+const static uint64_t SH_ACS_FSI = 0;
+const static uint64_t SH_ACS_FSI0 = 1;
+const static uint64_t SH_ACS_FSI1 = 2;
+const static uint64_t SH_ACS_FSI_BYTE = 3;
+const static uint64_t SH_ACS_OCI = 4;
+const static uint64_t SH_ACS_OCI1 = 5;
+const static uint64_t SH_ACS_OCI2 = 6;
+const static uint64_t SH_ACS_PPE = 7;
+const static uint64_t SH_ACS_PPE1 = 8;
+const static uint64_t SH_ACS_PPE2 = 9;
+const static uint64_t SH_ACS_SCOM = 10;
+const static uint64_t SH_ACS_SCOM1 = 11;
+const static uint64_t SH_ACS_SCOM1_AND = 12;
+const static uint64_t SH_ACS_SCOM1_CLEAR = 13;
+const static uint64_t SH_ACS_SCOM1_NC = 14;
+const static uint64_t SH_ACS_SCOM1_OR = 15;
+const static uint64_t SH_ACS_SCOM1_RO = 16;
+const static uint64_t SH_ACS_SCOM1_WAND = 17;
+const static uint64_t SH_ACS_SCOM1_WO = 18;
+const static uint64_t SH_ACS_SCOM1_WOR = 19;
+const static uint64_t SH_ACS_SCOM2 = 20;
+const static uint64_t SH_ACS_SCOM2_AND = 21;
+const static uint64_t SH_ACS_SCOM2_CLEAR = 22;
+const static uint64_t SH_ACS_SCOM2_NC = 23;
+const static uint64_t SH_ACS_SCOM2_OR = 24;
+const static uint64_t SH_ACS_SCOM2_WAND = 25;
+const static uint64_t SH_ACS_SCOM2_WOR = 26;
+const static uint64_t SH_ACS_SCOM3 = 27;
+const static uint64_t SH_ACS_SCOM3_RW = 28;
+const static uint64_t SH_ACS_SCOMFSI0 = 29;
+const static uint64_t SH_ACS_SCOMFSI0_CLEAR = 30;
+const static uint64_t SH_ACS_SCOMFSI0_OR = 31;
+const static uint64_t SH_ACS_SCOMFSI0_RO = 32;
+const static uint64_t SH_ACS_SCOMFSI0_RW = 33;
+const static uint64_t SH_ACS_SCOMFSI1 = 34;
+const static uint64_t SH_ACS_SCOMFSI1_CLEAR = 35;
+const static uint64_t SH_ACS_SCOMFSI1_OR = 36;
+const static uint64_t SH_ACS_SCOMFSI1_RO = 37;
+const static uint64_t SH_ACS_SCOMFSI1_RW = 38;
+const static uint64_t SH_ACS_SCOM_CLRPART = 39;
+const static uint64_t SH_ACS_SCOM_NC = 40;
+const static uint64_t SH_ACS_SCOM_RCLRPART = 41;
+const static uint64_t SH_ACS_SCOM_RO = 42;
+const static uint64_t SH_ACS_SCOM_RW = 43;
+const static uint64_t SH_ACS_SCOM_W = 44;
+const static uint64_t SH_ACS_SCOM_WAND = 45;
+const static uint64_t SH_ACS_SCOM_WCLEAR = 46;
+const static uint64_t SH_ACS_SCOM_WCLRPART = 47;
+const static uint64_t SH_ACS_SCOM_WCLRREG = 48;
+const static uint64_t SH_ACS_SCOM_WO = 49;
+const static uint64_t SH_ACS_SCOM_WOR = 50;
+
+
+
+const static uint64_t SH_FLD_0 = 0; // 459
+const static uint64_t SH_FLD_01 = 1; // 96
+const static uint64_t SH_FLD_01_0_11 = 2; // 16
+const static uint64_t SH_FLD_01_0_11_LEN = 3; // 16
+const static uint64_t SH_FLD_01_12_15 = 4; // 16
+const static uint64_t SH_FLD_01_12_15_LEN = 5; // 16
+const static uint64_t SH_FLD_01_ADVANCE_PING_PONG = 6; // 16
+const static uint64_t SH_FLD_01_ADVANCE_PR_VALUE = 7; // 16
+const static uint64_t SH_FLD_01_ATEST_MUX_CTL0 = 8; // 16
+const static uint64_t SH_FLD_01_ATEST_MUX_CTL1 = 9; // 16
+const static uint64_t SH_FLD_01_ATEST_MUX_CTL2 = 10; // 16
+const static uint64_t SH_FLD_01_ATEST_MUX_CTL3 = 11; // 16
+const static uint64_t SH_FLD_01_ATEST_MUX_CTL_EN = 12; // 16
+const static uint64_t SH_FLD_01_BB_LOCK0 = 13; // 16
+const static uint64_t SH_FLD_01_BB_LOCK1 = 14; // 16
+const static uint64_t SH_FLD_01_BIG_STEP_RIGHT = 15; // 16
+const static uint64_t SH_FLD_01_BIT_CENTERED = 16; // 16
+const static uint64_t SH_FLD_01_BIT_CENTERED_LEN = 17; // 16
+const static uint64_t SH_FLD_01_BLFIFO_DIS = 18; // 16
+const static uint64_t SH_FLD_01_BUMP = 19; // 16
+const static uint64_t SH_FLD_01_CALGATE_ON = 20; // 16
+const static uint64_t SH_FLD_01_CALIBRATE_BIT = 21; // 16
+const static uint64_t SH_FLD_01_CALIBRATE_BIT_LEN = 22; // 16
+const static uint64_t SH_FLD_01_CE0DLTVCC1 = 23; // 16
+const static uint64_t SH_FLD_01_CE0DLTVCCA = 24; // 16
+const static uint64_t SH_FLD_01_CHECKER_ENABLE = 25; // 16
+const static uint64_t SH_FLD_01_CHECKER_RESET = 26; // 16
+const static uint64_t SH_FLD_01_CLK16_SINGLE_ENDED = 27; // 128
+const static uint64_t SH_FLD_01_CLK18_SINGLE_ENDED = 28; // 128
+const static uint64_t SH_FLD_01_CLK20_SINGLE_ENDED = 29; // 128
+const static uint64_t SH_FLD_01_CLK22_SINGLE_ENDED = 30; // 128
+const static uint64_t SH_FLD_01_CLK_LEVEL = 31; // 16
+const static uint64_t SH_FLD_01_CLK_LEVEL_LEN = 32; // 16
+const static uint64_t SH_FLD_01_CNTL_POL = 33; // 16
+const static uint64_t SH_FLD_01_CNTL_SRC = 34; // 16
+const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N0 = 35; // 16
+const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N0_MASK = 36; // 16
+const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N1 = 37; // 16
+const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N1_MASK = 38; // 16
+const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N2 = 39; // 16
+const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N2_MASK = 40; // 16
+const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N3 = 41; // 16
+const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N3_MASK = 42; // 16
+const static uint64_t SH_FLD_01_CONTINUOUS_UPDATE = 43; // 32
+const static uint64_t SH_FLD_01_DD2_DQS_FIX_DIS = 44; // 16
+const static uint64_t SH_FLD_01_DD2_FIX_DIS = 45; // 16
+const static uint64_t SH_FLD_01_DD2_WTRFL_SYNC_DIS = 46; // 16
+const static uint64_t SH_FLD_01_DELAY1 = 47; // 16
+const static uint64_t SH_FLD_01_DELAY10 = 48; // 16
+const static uint64_t SH_FLD_01_DELAY10_LEN = 49; // 16
+const static uint64_t SH_FLD_01_DELAY11 = 50; // 16
+const static uint64_t SH_FLD_01_DELAY11_LEN = 51; // 16
+const static uint64_t SH_FLD_01_DELAY12 = 52; // 16
+const static uint64_t SH_FLD_01_DELAY12_LEN = 53; // 16
+const static uint64_t SH_FLD_01_DELAY13 = 54; // 16
+const static uint64_t SH_FLD_01_DELAY13_LEN = 55; // 16
+const static uint64_t SH_FLD_01_DELAY14 = 56; // 16
+const static uint64_t SH_FLD_01_DELAY14_LEN = 57; // 16
+const static uint64_t SH_FLD_01_DELAY15 = 58; // 16
+const static uint64_t SH_FLD_01_DELAY15_LEN = 59; // 16
+const static uint64_t SH_FLD_01_DELAY1_LEN = 60; // 16
+const static uint64_t SH_FLD_01_DELAY2 = 61; // 16
+const static uint64_t SH_FLD_01_DELAY2_LEN = 62; // 16
+const static uint64_t SH_FLD_01_DELAY3 = 63; // 16
+const static uint64_t SH_FLD_01_DELAY3_LEN = 64; // 16
+const static uint64_t SH_FLD_01_DELAY4 = 65; // 16
+const static uint64_t SH_FLD_01_DELAY4_LEN = 66; // 16
+const static uint64_t SH_FLD_01_DELAY5 = 67; // 16
+const static uint64_t SH_FLD_01_DELAY5_LEN = 68; // 16
+const static uint64_t SH_FLD_01_DELAY6 = 69; // 16
+const static uint64_t SH_FLD_01_DELAY6_LEN = 70; // 16
+const static uint64_t SH_FLD_01_DELAY7 = 71; // 16
+const static uint64_t SH_FLD_01_DELAY7_LEN = 72; // 16
+const static uint64_t SH_FLD_01_DELAY8 = 73; // 16
+const static uint64_t SH_FLD_01_DELAY8_LEN = 74; // 16
+const static uint64_t SH_FLD_01_DELAY9 = 75; // 16
+const static uint64_t SH_FLD_01_DELAY9_LEN = 76; // 16
+const static uint64_t SH_FLD_01_DELAYG = 77; // 1280
+const static uint64_t SH_FLD_01_DELAYG_LEN = 78; // 1280
+const static uint64_t SH_FLD_01_DELAY_PING_PONG_HALF = 79; // 16
+const static uint64_t SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_HIGH = 80; // 16
+const static uint64_t SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 81; // 16
+const static uint64_t SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_LOW = 82; // 16
+const static uint64_t SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 83; // 16
+const static uint64_t SH_FLD_01_DFT_FORCE_OUTPUTS = 84; // 16
+const static uint64_t SH_FLD_01_DFT_PRBS7_GEN_EN = 85; // 16
+const static uint64_t SH_FLD_01_DIGITAL_EN = 86; // 16
+const static uint64_t SH_FLD_01_DIR_0_15 = 87; // 8
+const static uint64_t SH_FLD_01_DIR_0_15_LEN = 88; // 8
+const static uint64_t SH_FLD_01_DIR_15 = 89; // 8
+const static uint64_t SH_FLD_01_DIR_15_LEN = 90; // 8
+const static uint64_t SH_FLD_01_DISABLE_0_15 = 91; // 32
+const static uint64_t SH_FLD_01_DISABLE_0_15_LEN = 92; // 32
+const static uint64_t SH_FLD_01_DISABLE_15 = 93; // 32
+const static uint64_t SH_FLD_01_DISABLE_15_LEN = 94; // 32
+const static uint64_t SH_FLD_01_DISABLE_16_23 = 95; // 64
+const static uint64_t SH_FLD_01_DISABLE_16_23_LEN = 96; // 64
+const static uint64_t SH_FLD_01_DISABLE_PING_PONG = 97; // 16
+const static uint64_t SH_FLD_01_DISABLE_TERMINATION = 98; // 16
+const static uint64_t SH_FLD_01_DIS_CLK_GATE = 99; // 16
+const static uint64_t SH_FLD_01_DI_ADR0 = 100; // 8
+const static uint64_t SH_FLD_01_DI_ADR1 = 101; // 8
+const static uint64_t SH_FLD_01_DI_ADR10_ADR11 = 102; // 16
+const static uint64_t SH_FLD_01_DI_ADR12_ADR13 = 103; // 16
+const static uint64_t SH_FLD_01_DI_ADR14_ADR15 = 104; // 16
+const static uint64_t SH_FLD_01_DI_ADR2_ADR3 = 105; // 16
+const static uint64_t SH_FLD_01_DI_ADR4_ADR5 = 106; // 16
+const static uint64_t SH_FLD_01_DI_ADR6_ADR7 = 107; // 16
+const static uint64_t SH_FLD_01_DI_ADR8_ADR9 = 108; // 16
+const static uint64_t SH_FLD_01_DL_FORCE_ON = 109; // 16
+const static uint64_t SH_FLD_01_DONE = 110; // 32
+const static uint64_t SH_FLD_01_DQS = 111; // 16
+const static uint64_t SH_FLD_01_DQSCLK_SELECT0 = 112; // 64
+const static uint64_t SH_FLD_01_DQSCLK_SELECT0_LEN = 113; // 64
+const static uint64_t SH_FLD_01_DQSCLK_SELECT1 = 114; // 64
+const static uint64_t SH_FLD_01_DQSCLK_SELECT1_LEN = 115; // 64
+const static uint64_t SH_FLD_01_DQSCLK_SELECT2 = 116; // 64
+const static uint64_t SH_FLD_01_DQSCLK_SELECT2_LEN = 117; // 64
+const static uint64_t SH_FLD_01_DQSCLK_SELECT3 = 118; // 64
+const static uint64_t SH_FLD_01_DQSCLK_SELECT3_LEN = 119; // 64
+const static uint64_t SH_FLD_01_DQS_ALIGN_CNTR = 120; // 16
+const static uint64_t SH_FLD_01_DQS_ALIGN_CNTR_LEN = 121; // 16
+const static uint64_t SH_FLD_01_DQS_ALIGN_FIX_DIS = 122; // 16
+const static uint64_t SH_FLD_01_DQS_ALIGN_ITR_CNTR = 123; // 16
+const static uint64_t SH_FLD_01_DQS_ALIGN_ITR_CNTR_LEN = 124; // 16
+const static uint64_t SH_FLD_01_DQS_ALIGN_JITTER = 125; // 16
+const static uint64_t SH_FLD_01_DQS_ALIGN_QUAD = 126; // 16
+const static uint64_t SH_FLD_01_DQS_ALIGN_QUAD_LEN = 127; // 16
+const static uint64_t SH_FLD_01_DQS_ALIGN_SM = 128; // 16
+const static uint64_t SH_FLD_01_DQS_ALIGN_SM_LEN = 129; // 16
+const static uint64_t SH_FLD_01_DQS_LEN = 130; // 16
+const static uint64_t SH_FLD_01_DQS_PIPE_FIX_DIS = 131; // 16
+const static uint64_t SH_FLD_01_DQS_PIPE_FIX_DIS_LEN = 132; // 16
+const static uint64_t SH_FLD_01_DRIFT_ERROR = 133; // 16
+const static uint64_t SH_FLD_01_DRIFT_MASK = 134; // 16
+const static uint64_t SH_FLD_01_DYN_MCTERM_CNTL_EN = 135; // 16
+const static uint64_t SH_FLD_01_DYN_POWER_CNTL_EN = 136; // 16
+const static uint64_t SH_FLD_01_DYN_RX_GATE_CNTL_EN = 137; // 16
+const static uint64_t SH_FLD_01_ENABLE = 138; // 32
+const static uint64_t SH_FLD_01_ENABLE_0_15 = 139; // 8
+const static uint64_t SH_FLD_01_ENABLE_0_15_LEN = 140; // 8
+const static uint64_t SH_FLD_01_ENABLE_15 = 141; // 8
+const static uint64_t SH_FLD_01_ENABLE_15_LEN = 142; // 8
+const static uint64_t SH_FLD_01_ENABLE_16_23 = 143; // 16
+const static uint64_t SH_FLD_01_ENABLE_16_23_LEN = 144; // 16
+const static uint64_t SH_FLD_01_EN_DQS_OFFSET = 145; // 16
+const static uint64_t SH_FLD_01_EN_N_WR = 146; // 16
+const static uint64_t SH_FLD_01_EN_N_WR_LEN = 147; // 16
+const static uint64_t SH_FLD_01_EN_P_WR = 148; // 32
+const static uint64_t SH_FLD_01_EN_P_WR_LEN = 149; // 32
+const static uint64_t SH_FLD_01_ERROR = 150; // 16
+const static uint64_t SH_FLD_01_ERROR_LEN = 151; // 16
+const static uint64_t SH_FLD_01_ERR_CLK22_MASK = 152; // 16
+const static uint64_t SH_FLD_01_EYE_CLIPPING = 153; // 16
+const static uint64_t SH_FLD_01_EYE_CLIPPING_MASK = 154; // 16
+const static uint64_t SH_FLD_01_FINE_STEPPING = 155; // 16
+const static uint64_t SH_FLD_01_FORCE_FIFO_CAPTURE = 156; // 16
+const static uint64_t SH_FLD_01_FW_LEFT_SIDE = 157; // 16
+const static uint64_t SH_FLD_01_FW_LEFT_SIDE_LEN = 158; // 16
+const static uint64_t SH_FLD_01_FW_RIGHT_SIDE = 159; // 16
+const static uint64_t SH_FLD_01_FW_RIGHT_SIDE_LEN = 160; // 16
+const static uint64_t SH_FLD_01_HS_PROBE_A = 161; // 16
+const static uint64_t SH_FLD_01_HS_PROBE_A_LEN = 162; // 16
+const static uint64_t SH_FLD_01_HS_PROBE_B = 163; // 16
+const static uint64_t SH_FLD_01_HS_PROBE_B_LEN = 164; // 16
+const static uint64_t SH_FLD_01_HW_VALUE = 165; // 16
+const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N0 = 166; // 16
+const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N0_MASK = 167; // 16
+const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N1 = 168; // 16
+const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N1_MASK = 169; // 16
+const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N2 = 170; // 16
+const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N2_MASK = 171; // 16
+const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N3 = 172; // 16
+const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N3_MASK = 173; // 16
+const static uint64_t SH_FLD_01_INIT_RXDLL_CAL_RESET = 174; // 32
+const static uint64_t SH_FLD_01_INIT_RXDLL_CAL_UPDATE = 175; // 32
+const static uint64_t SH_FLD_01_INTERP_SIG_SLEW = 176; // 16
+const static uint64_t SH_FLD_01_INTERP_SIG_SLEW_LEN = 177; // 16
+const static uint64_t SH_FLD_01_INVALID_NS_BIG_R = 178; // 16
+const static uint64_t SH_FLD_01_INVALID_NS_BIG_R_MASK = 179; // 16
+const static uint64_t SH_FLD_01_INVALID_NS_SMALL_L = 180; // 16
+const static uint64_t SH_FLD_01_INVALID_NS_SMALL_L_MASK = 181; // 16
+const static uint64_t SH_FLD_01_INVALID_NS_SMALL_R = 182; // 16
+const static uint64_t SH_FLD_01_INVALID_NS_SMALL_R_MASK = 183; // 16
+const static uint64_t SH_FLD_01_JUMP_BACK_RIGHT = 184; // 16
+const static uint64_t SH_FLD_01_LANE__0_11_PD = 185; // 16
+const static uint64_t SH_FLD_01_LANE__0_11_PD_LEN = 186; // 16
+const static uint64_t SH_FLD_01_LANE__12_15_PD = 187; // 16
+const static uint64_t SH_FLD_01_LANE__12_15_PD_LEN = 188; // 16
+const static uint64_t SH_FLD_01_LEADING_EDGE_FOUND_MASK = 189; // 16
+const static uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND = 190; // 16
+const static uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_0_15 = 191; // 8
+const static uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_0_15_LEN = 192; // 8
+const static uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_15 = 193; // 8
+const static uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_15_LEN = 194; // 8
+const static uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_16_23 = 195; // 16
+const static uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_16_23_LEN = 196; // 16
+const static uint64_t SH_FLD_01_LEN = 197; // 96
+const static uint64_t SH_FLD_01_LOOPBACK_DLY12 = 198; // 16
+const static uint64_t SH_FLD_01_LOOPBACK_FIX_EN = 199; // 16
+const static uint64_t SH_FLD_01_MATCH_STEP_RIGHT = 200; // 16
+const static uint64_t SH_FLD_01_MAX_DQS = 201; // 16
+const static uint64_t SH_FLD_01_MAX_DQS_ITER = 202; // 16
+const static uint64_t SH_FLD_01_MAX_DQS_LEN = 203; // 16
+const static uint64_t SH_FLD_01_MEMINTD00 = 204; // 16
+const static uint64_t SH_FLD_01_MEMINTD00_LEN = 205; // 16
+const static uint64_t SH_FLD_01_MEMINTD01 = 206; // 16
+const static uint64_t SH_FLD_01_MEMINTD01_LEN = 207; // 16
+const static uint64_t SH_FLD_01_MEMINTD02 = 208; // 16
+const static uint64_t SH_FLD_01_MEMINTD02_LEN = 209; // 16
+const static uint64_t SH_FLD_01_MEMINTD03 = 210; // 16
+const static uint64_t SH_FLD_01_MEMINTD03_LEN = 211; // 16
+const static uint64_t SH_FLD_01_MEMINTD04 = 212; // 16
+const static uint64_t SH_FLD_01_MEMINTD04_LEN = 213; // 16
+const static uint64_t SH_FLD_01_MEMINTD05 = 214; // 16
+const static uint64_t SH_FLD_01_MEMINTD05_LEN = 215; // 16
+const static uint64_t SH_FLD_01_MEMINTD06 = 216; // 16
+const static uint64_t SH_FLD_01_MEMINTD06_LEN = 217; // 16
+const static uint64_t SH_FLD_01_MEMINTD07 = 218; // 16
+const static uint64_t SH_FLD_01_MEMINTD07_LEN = 219; // 16
+const static uint64_t SH_FLD_01_MEMINTD08 = 220; // 16
+const static uint64_t SH_FLD_01_MEMINTD08_LEN = 221; // 16
+const static uint64_t SH_FLD_01_MEMINTD09 = 222; // 16
+const static uint64_t SH_FLD_01_MEMINTD09_LEN = 223; // 16
+const static uint64_t SH_FLD_01_MEMINTD10 = 224; // 16
+const static uint64_t SH_FLD_01_MEMINTD10_LEN = 225; // 16
+const static uint64_t SH_FLD_01_MEMINTD11 = 226; // 16
+const static uint64_t SH_FLD_01_MEMINTD11_LEN = 227; // 16
+const static uint64_t SH_FLD_01_MEMINTD12 = 228; // 16
+const static uint64_t SH_FLD_01_MEMINTD12_LEN = 229; // 16
+const static uint64_t SH_FLD_01_MEMINTD13 = 230; // 16
+const static uint64_t SH_FLD_01_MEMINTD13_LEN = 231; // 16
+const static uint64_t SH_FLD_01_MEMINTD14 = 232; // 16
+const static uint64_t SH_FLD_01_MEMINTD14_LEN = 233; // 16
+const static uint64_t SH_FLD_01_MEMINTD15 = 234; // 16
+const static uint64_t SH_FLD_01_MEMINTD15_LEN = 235; // 16
+const static uint64_t SH_FLD_01_MEMINTD16 = 236; // 16
+const static uint64_t SH_FLD_01_MEMINTD16_LEN = 237; // 16
+const static uint64_t SH_FLD_01_MEMINTD17 = 238; // 16
+const static uint64_t SH_FLD_01_MEMINTD17_LEN = 239; // 16
+const static uint64_t SH_FLD_01_MEMINTD18 = 240; // 16
+const static uint64_t SH_FLD_01_MEMINTD18_LEN = 241; // 16
+const static uint64_t SH_FLD_01_MEMINTD19 = 242; // 16
+const static uint64_t SH_FLD_01_MEMINTD19_LEN = 243; // 16
+const static uint64_t SH_FLD_01_MEMINTD20 = 244; // 16
+const static uint64_t SH_FLD_01_MEMINTD20_LEN = 245; // 16
+const static uint64_t SH_FLD_01_MEMINTD21 = 246; // 16
+const static uint64_t SH_FLD_01_MEMINTD21_LEN = 247; // 16
+const static uint64_t SH_FLD_01_MEMINTD22 = 248; // 16
+const static uint64_t SH_FLD_01_MEMINTD22_LEN = 249; // 16
+const static uint64_t SH_FLD_01_MEMINTD23 = 250; // 16
+const static uint64_t SH_FLD_01_MEMINTD23_LEN = 251; // 16
+const static uint64_t SH_FLD_01_MIN_EYE = 252; // 16
+const static uint64_t SH_FLD_01_MIN_EYE_MASK = 253; // 16
+const static uint64_t SH_FLD_01_MIN_RD_EYE_SIZE = 254; // 16
+const static uint64_t SH_FLD_01_MIN_RD_EYE_SIZE_LEN = 255; // 16
+const static uint64_t SH_FLD_01_MRS_CMD_N0 = 256; // 16
+const static uint64_t SH_FLD_01_MRS_CMD_N1 = 257; // 16
+const static uint64_t SH_FLD_01_MRS_CMD_N2 = 258; // 16
+const static uint64_t SH_FLD_01_MRS_CMD_N3 = 259; // 16
+const static uint64_t SH_FLD_01_N0 = 260; // 128
+const static uint64_t SH_FLD_01_N0_LEN = 261; // 128
+const static uint64_t SH_FLD_01_N1 = 262; // 128
+const static uint64_t SH_FLD_01_N1_LEN = 263; // 128
+const static uint64_t SH_FLD_01_N2 = 264; // 128
+const static uint64_t SH_FLD_01_N2_LEN = 265; // 128
+const static uint64_t SH_FLD_01_N3 = 266; // 128
+const static uint64_t SH_FLD_01_N3_LEN = 267; // 128
+const static uint64_t SH_FLD_01_NIB0 = 268; // 16
+const static uint64_t SH_FLD_01_NIB0TCFLIP_DC = 269; // 16
+const static uint64_t SH_FLD_01_NIB0_LEN = 270; // 16
+const static uint64_t SH_FLD_01_NIB1 = 271; // 16
+const static uint64_t SH_FLD_01_NIB1TCFLIP_DC = 272; // 16
+const static uint64_t SH_FLD_01_NIB1_LEN = 273; // 16
+const static uint64_t SH_FLD_01_NIB2 = 274; // 16
+const static uint64_t SH_FLD_01_NIB2TCFLIP_DC = 275; // 16
+const static uint64_t SH_FLD_01_NIB2_LEN = 276; // 16
+const static uint64_t SH_FLD_01_NIB3 = 277; // 16
+const static uint64_t SH_FLD_01_NIB3TCFLIP_DC = 278; // 16
+const static uint64_t SH_FLD_01_NIB3_LEN = 279; // 16
+const static uint64_t SH_FLD_01_NIB_0_2_DQSEL_CAP = 280; // 16
+const static uint64_t SH_FLD_01_NIB_0_2_DQSEL_CAP_LEN = 281; // 16
+const static uint64_t SH_FLD_01_NIB_0_2_DQSEL_IND = 282; // 16
+const static uint64_t SH_FLD_01_NIB_0_2_DQSEL_IND_LEN = 283; // 16
+const static uint64_t SH_FLD_01_NIB_0_2_DQSEL_RES = 284; // 16
+const static uint64_t SH_FLD_01_NIB_0_2_DQSEL_RES_LEN = 285; // 16
+const static uint64_t SH_FLD_01_NIB_1_3_DQSEL_CAP = 286; // 16
+const static uint64_t SH_FLD_01_NIB_1_3_DQSEL_CAP_LEN = 287; // 16
+const static uint64_t SH_FLD_01_NIB_1_3_DQSEL_IND = 288; // 16
+const static uint64_t SH_FLD_01_NIB_1_3_DQSEL_IND_LEN = 289; // 16
+const static uint64_t SH_FLD_01_NIB_1_3_DQSEL_RES = 290; // 16
+const static uint64_t SH_FLD_01_NIB_1_3_DQSEL_RES_LEN = 291; // 16
+const static uint64_t SH_FLD_01_NIB_2_DQSEL_CAP = 292; // 16
+const static uint64_t SH_FLD_01_NIB_2_DQSEL_CAP_LEN = 293; // 16
+const static uint64_t SH_FLD_01_NIB_2_DQSEL_IND = 294; // 16
+const static uint64_t SH_FLD_01_NIB_2_DQSEL_IND_LEN = 295; // 16
+const static uint64_t SH_FLD_01_NIB_2_DQSEL_RES = 296; // 16
+const static uint64_t SH_FLD_01_NIB_2_DQSEL_RES_LEN = 297; // 16
+const static uint64_t SH_FLD_01_NIB_3_DQSEL_CAP = 298; // 16
+const static uint64_t SH_FLD_01_NIB_3_DQSEL_CAP_LEN = 299; // 16
+const static uint64_t SH_FLD_01_NIB_3_DQSEL_IND = 300; // 16
+const static uint64_t SH_FLD_01_NIB_3_DQSEL_IND_LEN = 301; // 16
+const static uint64_t SH_FLD_01_NIB_3_DQSEL_RES = 302; // 16
+const static uint64_t SH_FLD_01_NIB_3_DQSEL_RES_LEN = 303; // 16
+const static uint64_t SH_FLD_01_NO_DQS = 304; // 16
+const static uint64_t SH_FLD_01_NO_DQS_MASK = 305; // 16
+const static uint64_t SH_FLD_01_NO_EYE_DETECTED = 306; // 16
+const static uint64_t SH_FLD_01_NO_EYE_DETECTED_MASK = 307; // 16
+const static uint64_t SH_FLD_01_NO_LOCK = 308; // 16
+const static uint64_t SH_FLD_01_NO_LOCK_MASK = 309; // 16
+const static uint64_t SH_FLD_01_OFFSET0 = 310; // 16
+const static uint64_t SH_FLD_01_OFFSET0_LEN = 311; // 16
+const static uint64_t SH_FLD_01_OFFSET1 = 312; // 16
+const static uint64_t SH_FLD_01_OFFSET1_LEN = 313; // 16
+const static uint64_t SH_FLD_01_OFFSET2 = 314; // 32
+const static uint64_t SH_FLD_01_OFFSET2_LEN = 315; // 32
+const static uint64_t SH_FLD_01_OFFSET3 = 316; // 32
+const static uint64_t SH_FLD_01_OFFSET3_LEN = 317; // 32
+const static uint64_t SH_FLD_01_OFFSET4 = 318; // 32
+const static uint64_t SH_FLD_01_OFFSET4_LEN = 319; // 32
+const static uint64_t SH_FLD_01_OFFSET5 = 320; // 32
+const static uint64_t SH_FLD_01_OFFSET5_LEN = 321; // 32
+const static uint64_t SH_FLD_01_OFFSET6 = 322; // 32
+const static uint64_t SH_FLD_01_OFFSET6_LEN = 323; // 32
+const static uint64_t SH_FLD_01_OFFSET7 = 324; // 32
+const static uint64_t SH_FLD_01_OFFSET7_LEN = 325; // 32
+const static uint64_t SH_FLD_01_OFFSET_ERR = 326; // 16
+const static uint64_t SH_FLD_01_OFFSET_ERR_MASK = 327; // 16
+const static uint64_t SH_FLD_01_OPERATE_MODE = 328; // 16
+const static uint64_t SH_FLD_01_OPERATE_MODE_LEN = 329; // 16
+const static uint64_t SH_FLD_01_PERCAL_PWR_DIS = 330; // 16
+const static uint64_t SH_FLD_01_PER_CAL_UPDATE_DISABLE = 331; // 16
+const static uint64_t SH_FLD_01_PHASE_ALIGN_RESET = 332; // 32
+const static uint64_t SH_FLD_01_PHASE_CNTL_EN = 333; // 32
+const static uint64_t SH_FLD_01_PHASE_DEFAULT_EN = 334; // 32
+const static uint64_t SH_FLD_01_POS_EDGE_ALIGN = 335; // 32
+const static uint64_t SH_FLD_01_QUAD0 = 336; // 16
+const static uint64_t SH_FLD_01_QUAD0_CLK16 = 337; // 128
+const static uint64_t SH_FLD_01_QUAD0_CLK18 = 338; // 128
+const static uint64_t SH_FLD_01_QUAD0_LEN = 339; // 16
+const static uint64_t SH_FLD_01_QUAD1 = 340; // 16
+const static uint64_t SH_FLD_01_QUAD1_CLK16 = 341; // 128
+const static uint64_t SH_FLD_01_QUAD1_CLK18 = 342; // 128
+const static uint64_t SH_FLD_01_QUAD1_LEN = 343; // 16
+const static uint64_t SH_FLD_01_QUAD2 = 344; // 16
+const static uint64_t SH_FLD_01_QUAD2_CLK16 = 345; // 128
+const static uint64_t SH_FLD_01_QUAD2_CLK18 = 346; // 64
+const static uint64_t SH_FLD_01_QUAD2_CLK20 = 347; // 128
+const static uint64_t SH_FLD_01_QUAD2_CLK22 = 348; // 128
+const static uint64_t SH_FLD_01_QUAD2_LEN = 349; // 16
+const static uint64_t SH_FLD_01_QUAD3 = 350; // 16
+const static uint64_t SH_FLD_01_QUAD3_CLK16 = 351; // 128
+const static uint64_t SH_FLD_01_QUAD3_CLK18 = 352; // 64
+const static uint64_t SH_FLD_01_QUAD3_CLK20 = 353; // 128
+const static uint64_t SH_FLD_01_QUAD3_CLK22 = 354; // 128
+const static uint64_t SH_FLD_01_QUAD3_LEN = 355; // 16
+const static uint64_t SH_FLD_01_RD = 356; // 272
+const static uint64_t SH_FLD_01_RDCLK_SELECT0 = 357; // 64
+const static uint64_t SH_FLD_01_RDCLK_SELECT0_LEN = 358; // 64
+const static uint64_t SH_FLD_01_RDCLK_SELECT1 = 359; // 64
+const static uint64_t SH_FLD_01_RDCLK_SELECT1_LEN = 360; // 64
+const static uint64_t SH_FLD_01_RDCLK_SELECT2 = 361; // 64
+const static uint64_t SH_FLD_01_RDCLK_SELECT2_LEN = 362; // 64
+const static uint64_t SH_FLD_01_RDCLK_SELECT3 = 363; // 64
+const static uint64_t SH_FLD_01_RDCLK_SELECT3_LEN = 364; // 64
+const static uint64_t SH_FLD_01_RD_DELAY0 = 365; // 112
+const static uint64_t SH_FLD_01_RD_DELAY0_LEN = 366; // 112
+const static uint64_t SH_FLD_01_RD_DELAY1 = 367; // 112
+const static uint64_t SH_FLD_01_RD_DELAY1_LEN = 368; // 112
+const static uint64_t SH_FLD_01_RD_DELAY2 = 369; // 112
+const static uint64_t SH_FLD_01_RD_DELAY2_LEN = 370; // 112
+const static uint64_t SH_FLD_01_RD_DELAY3 = 371; // 112
+const static uint64_t SH_FLD_01_RD_DELAY3_LEN = 372; // 112
+const static uint64_t SH_FLD_01_RD_DELAY4 = 373; // 112
+const static uint64_t SH_FLD_01_RD_DELAY4_LEN = 374; // 112
+const static uint64_t SH_FLD_01_RD_DELAY5 = 375; // 112
+const static uint64_t SH_FLD_01_RD_DELAY5_LEN = 376; // 112
+const static uint64_t SH_FLD_01_RD_DELAY6 = 377; // 112
+const static uint64_t SH_FLD_01_RD_DELAY6_LEN = 378; // 112
+const static uint64_t SH_FLD_01_RD_DELAY7 = 379; // 112
+const static uint64_t SH_FLD_01_RD_DELAY7_LEN = 380; // 112
+const static uint64_t SH_FLD_01_RD_LEN = 381; // 272
+const static uint64_t SH_FLD_01_RD_SIZE0 = 382; // 176
+const static uint64_t SH_FLD_01_RD_SIZE0_LEN = 383; // 176
+const static uint64_t SH_FLD_01_RD_SIZE1 = 384; // 176
+const static uint64_t SH_FLD_01_RD_SIZE1_LEN = 385; // 176
+const static uint64_t SH_FLD_01_RD_SIZE2 = 386; // 176
+const static uint64_t SH_FLD_01_RD_SIZE2_LEN = 387; // 176
+const static uint64_t SH_FLD_01_RD_SIZE3 = 388; // 176
+const static uint64_t SH_FLD_01_RD_SIZE3_LEN = 389; // 176
+const static uint64_t SH_FLD_01_RD_SIZE4 = 390; // 176
+const static uint64_t SH_FLD_01_RD_SIZE4_LEN = 391; // 176
+const static uint64_t SH_FLD_01_RD_SIZE5 = 392; // 176
+const static uint64_t SH_FLD_01_RD_SIZE5_LEN = 393; // 176
+const static uint64_t SH_FLD_01_RD_SIZE6 = 394; // 176
+const static uint64_t SH_FLD_01_RD_SIZE6_LEN = 395; // 176
+const static uint64_t SH_FLD_01_RD_SIZE7 = 396; // 176
+const static uint64_t SH_FLD_01_RD_SIZE7_LEN = 397; // 176
+const static uint64_t SH_FLD_01_READ_CENTERING_MODE = 398; // 16
+const static uint64_t SH_FLD_01_READ_CENTERING_MODE_LEN = 399; // 16
+const static uint64_t SH_FLD_01_REFERENCE1 = 400; // 16
+const static uint64_t SH_FLD_01_REFERENCE1_LEN = 401; // 16
+const static uint64_t SH_FLD_01_REFERENCE2 = 402; // 16
+const static uint64_t SH_FLD_01_REFERENCE2_LEN = 403; // 16
+const static uint64_t SH_FLD_01_REFERENCE3 = 404; // 16
+const static uint64_t SH_FLD_01_REFERENCE3_LEN = 405; // 16
+const static uint64_t SH_FLD_01_REGS_RXDLL_CAL_SKIP = 406; // 32
+const static uint64_t SH_FLD_01_REGS_RXDLL_CAL_SKIP_LEN = 407; // 32
+const static uint64_t SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY2 = 408; // 32
+const static uint64_t SH_FLD_01_REGS_RXDLL_COARSE_EN = 409; // 32
+const static uint64_t SH_FLD_01_REGS_RXDLL_COARSE_EN_LEN = 410; // 32
+const static uint64_t SH_FLD_01_REGS_RXDLL_DAC_COARSE = 411; // 32
+const static uint64_t SH_FLD_01_REGS_RXDLL_DAC_COARSE_LEN = 412; // 32
+const static uint64_t SH_FLD_01_REGS_RXDLL_VREG_LOWER = 413; // 32
+const static uint64_t SH_FLD_01_REGS_RXDLL_VREG_LOWER_LEN = 414; // 32
+const static uint64_t SH_FLD_01_REGS_RXDLL_VREG_UPPER = 415; // 32
+const static uint64_t SH_FLD_01_REGS_RXDLL_VREG_UPPER_LEN = 416; // 32
+const static uint64_t SH_FLD_01_RESERVED_56_63 = 417; // 16
+const static uint64_t SH_FLD_01_RESERVED_56_63_LEN = 418; // 16
+const static uint64_t SH_FLD_01_ROT0 = 419; // 16
+const static uint64_t SH_FLD_01_ROT0_LEN = 420; // 16
+const static uint64_t SH_FLD_01_ROT1 = 421; // 16
+const static uint64_t SH_FLD_01_ROT1_LEN = 422; // 16
+const static uint64_t SH_FLD_01_ROT_CLK_N0 = 423; // 128
+const static uint64_t SH_FLD_01_ROT_CLK_N0_LEN = 424; // 128
+const static uint64_t SH_FLD_01_ROT_CLK_N1 = 425; // 128
+const static uint64_t SH_FLD_01_ROT_CLK_N1_LEN = 426; // 128
+const static uint64_t SH_FLD_01_ROT_N0 = 427; // 128
+const static uint64_t SH_FLD_01_ROT_N0_LEN = 428; // 128
+const static uint64_t SH_FLD_01_ROT_N1 = 429; // 128
+const static uint64_t SH_FLD_01_ROT_N1_LEN = 430; // 128
+const static uint64_t SH_FLD_01_ROT_OVERRIDE = 431; // 32
+const static uint64_t SH_FLD_01_ROT_OVERRIDE_EN = 432; // 32
+const static uint64_t SH_FLD_01_ROT_OVERRIDE_LEN = 433; // 32
+const static uint64_t SH_FLD_01_RXREG_COMPCON_DC = 434; // 32
+const static uint64_t SH_FLD_01_RXREG_COMPCON_DC_LEN = 435; // 32
+const static uint64_t SH_FLD_01_RXREG_CON_DC = 436; // 32
+const static uint64_t SH_FLD_01_RXREG_DAC_PULLUP_DC = 437; // 32
+const static uint64_t SH_FLD_01_RXREG_DRVCON_DC = 438; // 32
+const static uint64_t SH_FLD_01_RXREG_DRVCON_DC_LEN = 439; // 32
+const static uint64_t SH_FLD_01_RXREG_FILTER_LENGTH_DC = 440; // 32
+const static uint64_t SH_FLD_01_RXREG_FILTER_LENGTH_DC_LEN = 441; // 32
+const static uint64_t SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC = 442; // 32
+const static uint64_t SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 443; // 32
+const static uint64_t SH_FLD_01_RXREG_REF_SEL_DC = 444; // 32
+const static uint64_t SH_FLD_01_RXREG_REF_SEL_DC_LEN = 445; // 32
+const static uint64_t SH_FLD_01_S0ACENSLICENDRV_DC = 446; // 16
+const static uint64_t SH_FLD_01_S0ACENSLICENDRV_DC_LEN = 447; // 16
+const static uint64_t SH_FLD_01_S0ACENSLICEPDRV_DC = 448; // 16
+const static uint64_t SH_FLD_01_S0ACENSLICEPDRV_DC_LEN = 449; // 16
+const static uint64_t SH_FLD_01_S0ACENSLICEPTERM_DC = 450; // 16
+const static uint64_t SH_FLD_01_S0ACENSLICEPTERM_DC_LEN = 451; // 16
+const static uint64_t SH_FLD_01_S0INSDLYTAP = 452; // 16
+const static uint64_t SH_FLD_01_S1ACENSLICENDRV_DC = 453; // 16
+const static uint64_t SH_FLD_01_S1ACENSLICENDRV_DC_LEN = 454; // 16
+const static uint64_t SH_FLD_01_S1ACENSLICEPDRV_DC = 455; // 16
+const static uint64_t SH_FLD_01_S1ACENSLICEPDRV_DC_LEN = 456; // 16
+const static uint64_t SH_FLD_01_S1ACENSLICEPTERM_DC = 457; // 16
+const static uint64_t SH_FLD_01_S1ACENSLICEPTERM_DC_LEN = 458; // 16
+const static uint64_t SH_FLD_01_S1INSDLYTAP = 459; // 16
+const static uint64_t SH_FLD_01_SEL0 = 460; // 32
+const static uint64_t SH_FLD_01_SEL0_LEN = 461; // 16
+const static uint64_t SH_FLD_01_SEL1 = 462; // 32
+const static uint64_t SH_FLD_01_SEL10 = 463; // 32
+const static uint64_t SH_FLD_01_SEL10_LEN = 464; // 32
+const static uint64_t SH_FLD_01_SEL11 = 465; // 32
+const static uint64_t SH_FLD_01_SEL11_LEN = 466; // 32
+const static uint64_t SH_FLD_01_SEL12 = 467; // 32
+const static uint64_t SH_FLD_01_SEL12_LEN = 468; // 32
+const static uint64_t SH_FLD_01_SEL13 = 469; // 32
+const static uint64_t SH_FLD_01_SEL13_LEN = 470; // 32
+const static uint64_t SH_FLD_01_SEL14 = 471; // 32
+const static uint64_t SH_FLD_01_SEL14_LEN = 472; // 32
+const static uint64_t SH_FLD_01_SEL15 = 473; // 32
+const static uint64_t SH_FLD_01_SEL15_LEN = 474; // 32
+const static uint64_t SH_FLD_01_SEL1_LEN = 475; // 32
+const static uint64_t SH_FLD_01_SEL2 = 476; // 32
+const static uint64_t SH_FLD_01_SEL2_LEN = 477; // 32
+const static uint64_t SH_FLD_01_SEL3 = 478; // 32
+const static uint64_t SH_FLD_01_SEL3_LEN = 479; // 32
+const static uint64_t SH_FLD_01_SEL4 = 480; // 32
+const static uint64_t SH_FLD_01_SEL4_LEN = 481; // 32
+const static uint64_t SH_FLD_01_SEL5 = 482; // 32
+const static uint64_t SH_FLD_01_SEL5_LEN = 483; // 32
+const static uint64_t SH_FLD_01_SEL6 = 484; // 32
+const static uint64_t SH_FLD_01_SEL6_LEN = 485; // 32
+const static uint64_t SH_FLD_01_SEL7 = 486; // 32
+const static uint64_t SH_FLD_01_SEL7_LEN = 487; // 32
+const static uint64_t SH_FLD_01_SEL8 = 488; // 32
+const static uint64_t SH_FLD_01_SEL8_LEN = 489; // 16
+const static uint64_t SH_FLD_01_SEL9 = 490; // 32
+const static uint64_t SH_FLD_01_SEL9_LEN = 491; // 32
+const static uint64_t SH_FLD_01_SMALL_STEP_LEFT = 492; // 16
+const static uint64_t SH_FLD_01_SMALL_STEP_RIGHT = 493; // 16
+const static uint64_t SH_FLD_01_SYNC = 494; // 16
+const static uint64_t SH_FLD_01_SYNC_LEN = 495; // 16
+const static uint64_t SH_FLD_01_SYSCLK_DQSCLK_OFFSET = 496; // 16
+const static uint64_t SH_FLD_01_SYSCLK_DQSCLK_OFFSET_LEN = 497; // 16
+const static uint64_t SH_FLD_01_SYSCLK_RDCLK_OFFSET = 498; // 16
+const static uint64_t SH_FLD_01_SYSCLK_RDCLK_OFFSET_LEN = 499; // 16
+const static uint64_t SH_FLD_01_TEST_4TO1_MODE = 500; // 16
+const static uint64_t SH_FLD_01_TEST_CHECK_EN = 501; // 16
+const static uint64_t SH_FLD_01_TEST_CLEAR_ERROR = 502; // 16
+const static uint64_t SH_FLD_01_TEST_DATA_EN = 503; // 16
+const static uint64_t SH_FLD_01_TEST_GEN_EN = 504; // 16
+const static uint64_t SH_FLD_01_TEST_LANE_PAIR_FAIL = 505; // 16
+const static uint64_t SH_FLD_01_TEST_LANE_PAIR_FAIL_LEN = 506; // 16
+const static uint64_t SH_FLD_01_TEST_MODE = 507; // 16
+const static uint64_t SH_FLD_01_TEST_MODE_LEN = 508; // 16
+const static uint64_t SH_FLD_01_TEST_RESET = 509; // 16
+const static uint64_t SH_FLD_01_TOXDRV_HIBERNATE = 510; // 16
+const static uint64_t SH_FLD_01_TRAILING_EDGE_FOUND_MASK = 511; // 16
+const static uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND = 512; // 16
+const static uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_0_15 = 513; // 8
+const static uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 514; // 8
+const static uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_15 = 515; // 8
+const static uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_15_LEN = 516; // 8
+const static uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_16_23 = 517; // 16
+const static uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 518; // 16
+const static uint64_t SH_FLD_01_TRIG_PERIOD = 519; // 16
+const static uint64_t SH_FLD_01_TSYS = 520; // 16
+const static uint64_t SH_FLD_01_TSYS_LEN = 521; // 16
+const static uint64_t SH_FLD_01_TUNEATST = 522; // 8
+const static uint64_t SH_FLD_01_TUNEATST_0 = 523; // 8
+const static uint64_t SH_FLD_01_TUNETDIV_0_2 = 524; // 8
+const static uint64_t SH_FLD_01_TUNETDIV_0_2_LEN = 525; // 8
+const static uint64_t SH_FLD_01_TUNETDIV_2 = 526; // 8
+const static uint64_t SH_FLD_01_TUNETDIV_2_LEN = 527; // 8
+const static uint64_t SH_FLD_01_VALID_NS_BIG_L = 528; // 16
+const static uint64_t SH_FLD_01_VALID_NS_BIG_L_MASK = 529; // 16
+const static uint64_t SH_FLD_01_VALID_NS_BIG_R = 530; // 16
+const static uint64_t SH_FLD_01_VALID_NS_BIG_R_MASK = 531; // 16
+const static uint64_t SH_FLD_01_VALID_NS_JUMP_BACK = 532; // 16
+const static uint64_t SH_FLD_01_VALID_NS_JUMP_BACK_MASK = 533; // 16
+const static uint64_t SH_FLD_01_WL_ADVANCE_DISABLE = 534; // 16
+const static uint64_t SH_FLD_01_WL_ERR_CLK16 = 535; // 32
+const static uint64_t SH_FLD_01_WL_ERR_CLK16_MASK = 536; // 16
+const static uint64_t SH_FLD_01_WL_ERR_CLK18 = 537; // 32
+const static uint64_t SH_FLD_01_WL_ERR_CLK18_MASK = 538; // 16
+const static uint64_t SH_FLD_01_WL_ERR_CLK20 = 539; // 32
+const static uint64_t SH_FLD_01_WL_ERR_CLK20_MASK = 540; // 16
+const static uint64_t SH_FLD_01_WL_ERR_CLK22 = 541; // 32
+const static uint64_t SH_FLD_01_WR = 542; // 16
+const static uint64_t SH_FLD_01_WRAPSEL = 543; // 16
+const static uint64_t SH_FLD_01_WR_LEN = 544; // 16
+const static uint64_t SH_FLD_01_WTRFL_AVE_DIS = 545; // 16
+const static uint64_t SH_FLD_01_ZERO_DETECTED = 546; // 16
+const static uint64_t SH_FLD_0X00_DATA_PARITY = 547; // 4
+const static uint64_t SH_FLD_0X00_SPARE_30_31 = 548; // 1
+const static uint64_t SH_FLD_0X00_SPARE_30_31_LEN = 549; // 1
+const static uint64_t SH_FLD_0X01_DATA_PARITY = 550; // 4
+const static uint64_t SH_FLD_0X01_SPARE_03 = 551; // 1
+const static uint64_t SH_FLD_0X01_SPARE_28_31 = 552; // 1
+const static uint64_t SH_FLD_0X01_SPARE_28_31_LEN = 553; // 1
+const static uint64_t SH_FLD_0X02_DATA_PARITY = 554; // 4
+const static uint64_t SH_FLD_0X02_SPARE_03 = 555; // 1
+const static uint64_t SH_FLD_0X02_SPARE_28_31 = 556; // 1
+const static uint64_t SH_FLD_0X02_SPARE_28_31_LEN = 557; // 1
+const static uint64_t SH_FLD_0X03_DATA_PARITY = 558; // 4
+const static uint64_t SH_FLD_0X03_SPARE_03 = 559; // 1
+const static uint64_t SH_FLD_0X03_SPARE_28_31 = 560; // 1
+const static uint64_t SH_FLD_0X03_SPARE_28_31_LEN = 561; // 1
+const static uint64_t SH_FLD_0X04_DATA_PARITY = 562; // 4
+const static uint64_t SH_FLD_0X04_SPARE_03 = 563; // 1
+const static uint64_t SH_FLD_0X04_SPARE_28_31 = 564; // 1
+const static uint64_t SH_FLD_0X04_SPARE_28_31_LEN = 565; // 1
+const static uint64_t SH_FLD_0X05_DATA_PARITY = 566; // 4
+const static uint64_t SH_FLD_0X05_SPARE_01 = 567; // 1
+const static uint64_t SH_FLD_0X05_SPARE_05 = 568; // 1
+const static uint64_t SH_FLD_0X06_DATA_PARITY = 569; // 4
+const static uint64_t SH_FLD_0X06_SPARE_02_04 = 570; // 1
+const static uint64_t SH_FLD_0X06_SPARE_02_04_LEN = 571; // 1
+const static uint64_t SH_FLD_0X06_SPARE_16_21 = 572; // 1
+const static uint64_t SH_FLD_0X06_SPARE_16_21_LEN = 573; // 1
+const static uint64_t SH_FLD_0X07_DATA_PARITY = 574; // 4
+const static uint64_t SH_FLD_0X07_SPARE_19 = 575; // 1
+const static uint64_t SH_FLD_0X07_SPARE_20 = 576; // 1
+const static uint64_t SH_FLD_0X07_SPARE_22_31 = 577; // 1
+const static uint64_t SH_FLD_0X07_SPARE_22_31_LEN = 578; // 1
+const static uint64_t SH_FLD_0X08_DATA_PARITY = 579; // 4
+const static uint64_t SH_FLD_0X08_SPARE_03 = 580; // 1
+const static uint64_t SH_FLD_0X08_SPARE_30 = 581; // 1
+const static uint64_t SH_FLD_0X09_DATA_PARITY = 582; // 4
+const static uint64_t SH_FLD_0X0A_DATA_PARITY = 583; // 4
+const static uint64_t SH_FLD_0X0A_SPARE_13_15 = 584; // 1
+const static uint64_t SH_FLD_0X0A_SPARE_13_15_LEN = 585; // 1
+const static uint64_t SH_FLD_0X0B_DATA_PARITY = 586; // 4
+const static uint64_t SH_FLD_0X0B_SPARE_04_05 = 587; // 1
+const static uint64_t SH_FLD_0X0B_SPARE_04_05_LEN = 588; // 1
+const static uint64_t SH_FLD_0X0B_SPARE_17 = 589; // 1
+const static uint64_t SH_FLD_0X0B_SPARE_33_39 = 590; // 1
+const static uint64_t SH_FLD_0X0B_SPARE_33_39_LEN = 591; // 1
+const static uint64_t SH_FLD_0X0C_DATA_PARITY = 592; // 4
+const static uint64_t SH_FLD_0X0D_SPARE_60_62 = 593; // 1
+const static uint64_t SH_FLD_0X0D_SPARE_60_62_LEN = 594; // 1
+const static uint64_t SH_FLD_0X10_DATA_PARITY = 595; // 4
+const static uint64_t SH_FLD_0X10_SPARE_17_18 = 596; // 1
+const static uint64_t SH_FLD_0X10_SPARE_17_18_LEN = 597; // 1
+const static uint64_t SH_FLD_0X10_SPARE_19_23 = 598; // 1
+const static uint64_t SH_FLD_0X10_SPARE_19_23_LEN = 599; // 1
+const static uint64_t SH_FLD_0X10_SPARE_24_25 = 600; // 1
+const static uint64_t SH_FLD_0X10_SPARE_24_25_LEN = 601; // 1
+const static uint64_t SH_FLD_0X10_SPARE_27 = 602; // 1
+const static uint64_t SH_FLD_0X10_SPARE_29 = 603; // 1
+const static uint64_t SH_FLD_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY =
+    604; // 4
+const static uint64_t SH_FLD_0X17_0X18_0X21_0X22_DATA_PARITY = 605; // 4
+const static uint64_t SH_FLD_0X1D_0X1E_0X1F_DATA_PARITY = 606; // 4
+const static uint64_t SH_FLD_0X20_DATA_PARITY = 607; // 4
+const static uint64_t SH_FLD_0X22_SPARE_01 = 608; // 1
+const static uint64_t SH_FLD_0X22_SPARE_03_07 = 609; // 1
+const static uint64_t SH_FLD_0X22_SPARE_03_07_LEN = 610; // 1
+const static uint64_t SH_FLD_0X23_DATA_PARITY = 611; // 4
+const static uint64_t SH_FLD_0X23_SPARE_06_07 = 612; // 1
+const static uint64_t SH_FLD_0X23_SPARE_06_07_LEN = 613; // 1
+const static uint64_t SH_FLD_0X24_DATA_PARITY = 614; // 4
+const static uint64_t SH_FLD_0X24_SPARE_05_07 = 615; // 1
+const static uint64_t SH_FLD_0X24_SPARE_05_07_LEN = 616; // 1
+const static uint64_t SH_FLD_0X27_DATA_PARITY = 617; // 4
+const static uint64_t SH_FLD_0X27_SPARE_34 = 618; // 1
+const static uint64_t SH_FLD_0X27_SPARE_36 = 619; // 1
+const static uint64_t SH_FLD_0X29_DATA_PARITY = 620; // 4
+const static uint64_t SH_FLD_0X30_0X31_0X32_0X33_DATA_PARITY = 621; // 4
+const static uint64_t SH_FLD_0_2 = 622; // 16
+const static uint64_t SH_FLD_0_CANNED_0 = 623; // 2
+const static uint64_t SH_FLD_0_CANNED_0_LEN = 624; // 2
+const static uint64_t SH_FLD_0_CANNED_1 = 625; // 2
+const static uint64_t SH_FLD_0_CANNED_1_LEN = 626; // 2
+const static uint64_t SH_FLD_0_CPS = 627; // 2
+const static uint64_t SH_FLD_0_CPS_LEN = 628; // 2
+const static uint64_t SH_FLD_0_DATA = 629; // 1
+const static uint64_t SH_FLD_0_DATA_LEN = 630; // 1
+const static uint64_t SH_FLD_0_LEN = 631; // 47
+const static uint64_t SH_FLD_0_LOCAL_STEP_MODE_ENABLE = 632; // 1
+const static uint64_t SH_FLD_0_OSC_NOT_VALID = 633; // 1
+const static uint64_t SH_FLD_0_REMOTE_SYNC_LATE_SYNC_COUNT = 634; // 1
+const static uint64_t SH_FLD_0_REMOTE_SYNC_LATE_SYNC_COUNT_LEN = 635; // 1
+const static uint64_t SH_FLD_0_RESULT = 636; // 43
+const static uint64_t SH_FLD_0_RESULT_LEN = 637; // 43
+const static uint64_t SH_FLD_0_SPARE_SECTOR_BUFFER_CONTROL = 638; // 1
+const static uint64_t SH_FLD_0_STEP_ALIGN_DISABLE = 639; // 1
+const static uint64_t SH_FLD_0_STEP_ALIGN_THRESHOLD = 640; // 1
+const static uint64_t SH_FLD_0_STEP_ALIGN_THRESHOLD_LEN = 641; // 1
+const static uint64_t SH_FLD_0_STEP_CHECK_CONSTANT_CPS_ENABLE = 642; // 2
+const static uint64_t SH_FLD_0_STEP_CHECK_CPS_DEVIATION = 643; // 2
+const static uint64_t SH_FLD_0_STEP_CHECK_CPS_DEVIATION_LEN = 644; // 2
+const static uint64_t SH_FLD_0_STEP_CHECK_VALIDITY_COUNT = 645; // 2
+const static uint64_t SH_FLD_0_STEP_CHECK_VALIDITY_COUNT_LEN = 646; // 2
+const static uint64_t SH_FLD_0_STEP_STEER_ENABLE = 647; // 1
+const static uint64_t SH_FLD_1 = 648; // 502
+const static uint64_t SH_FLD_10_RESERVED = 649; // 1
+const static uint64_t SH_FLD_10_SPARE_REFCLOCK = 650; // 1
+const static uint64_t SH_FLD_10_SPARE_SECTOR_BUFFER_CONTROL = 651; // 1
+const static uint64_t SH_FLD_11_RESERVED = 652; // 1
+const static uint64_t SH_FLD_11_SPARE_REFCLOCK = 653; // 1
+const static uint64_t SH_FLD_11_SPARE_SECTOR_BUFFER_CONTROL = 654; // 1
+const static uint64_t SH_FLD_12GB_ENABLE = 655; // 8
+const static uint64_t SH_FLD_12_RESERVED = 656; // 1
+const static uint64_t SH_FLD_12_SPARE_SECTOR_BUFFER_CONTROL = 657; // 1
+const static uint64_t SH_FLD_13_RESERVED = 658; // 1
+const static uint64_t SH_FLD_13_SPARE_OPB_CONTROL = 659; // 1
+const static uint64_t SH_FLD_13_SPARE_PROBE = 660; // 1
+const static uint64_t SH_FLD_13_SPARE_SECTOR_BUFFER_CONTROL = 661; // 1
+const static uint64_t SH_FLD_14_RESERVED = 662; // 1
+const static uint64_t SH_FLD_14_SPARE_OPB_CONTROL = 663; // 1
+const static uint64_t SH_FLD_14_SPARE_PLL = 664; // 1
+const static uint64_t SH_FLD_14_SPARE_PROBE = 665; // 1
+const static uint64_t SH_FLD_14_SPARE_SECTOR_BUFFER_CONTROL = 666; // 1
+const static uint64_t SH_FLD_15_RESERVED = 667; // 1
+const static uint64_t SH_FLD_15_SPARE_OPB_CONTROL = 668; // 1
+const static uint64_t SH_FLD_15_SPARE_OSC = 669; // 1
+const static uint64_t SH_FLD_15_SPARE_PLL = 670; // 1
+const static uint64_t SH_FLD_15_SPARE_PROBE = 671; // 1
+const static uint64_t SH_FLD_15_SPARE_SECTOR_BUFFER_CONTROL = 672; // 1
+const static uint64_t SH_FLD_16_FREE_USAGE = 673; // 1
+const static uint64_t SH_FLD_16_SPARE_OSC = 674; // 1
+const static uint64_t SH_FLD_16_SPARE_RESONANT_CLOCKING_CONTROL = 675; // 1
+const static uint64_t SH_FLD_17_SPARE_OSC = 676; // 1
+const static uint64_t SH_FLD_17_SPARE_RESONANT_CLOCKING_CONTROL = 677; // 1
+const static uint64_t SH_FLD_18_31_SPARE = 678; // 8
+const static uint64_t SH_FLD_18_31_SPARE_LEN = 679; // 8
+const static uint64_t SH_FLD_18_SPARE_MUX_CONTROL = 680; // 1
+const static uint64_t SH_FLD_18_SPARE_OSC = 681; // 1
+const static uint64_t SH_FLD_18_SPARE_RESONANT_CLOCKING_CONTROL = 682; // 1
+const static uint64_t SH_FLD_19_SPARE_MUX_CONTROL = 683; // 1
+const static uint64_t SH_FLD_19_SPARE_OSC = 684; // 1
+const static uint64_t SH_FLD_19_SPARE_RESONANT_CLOCKING_CONTROL = 685; // 1
+const static uint64_t SH_FLD_1_3 = 686; // 16
+const static uint64_t SH_FLD_1_CANNED_0 = 687; // 2
+const static uint64_t SH_FLD_1_CANNED_0_LEN = 688; // 2
+const static uint64_t SH_FLD_1_CANNED_1 = 689; // 2
+const static uint64_t SH_FLD_1_CANNED_1_LEN = 690; // 2
+const static uint64_t SH_FLD_1_CPS = 691; // 2
+const static uint64_t SH_FLD_1_CPS_LEN = 692; // 2
+const static uint64_t SH_FLD_1_DATA = 693; // 1
+const static uint64_t SH_FLD_1_DATA_LEN = 694; // 1
+const static uint64_t SH_FLD_1_LEN = 695; // 90
+const static uint64_t SH_FLD_1_LOCAL_STEP_MODE_ENABLE = 696; // 1
+const static uint64_t SH_FLD_1_OSC_NOT_VALID = 697; // 1
+const static uint64_t SH_FLD_1_REMOTE_SYNC_LATE_SYNC_COUNT = 698; // 1
+const static uint64_t SH_FLD_1_REMOTE_SYNC_LATE_SYNC_COUNT_LEN = 699; // 1
+const static uint64_t SH_FLD_1_RESULT = 700; // 43
+const static uint64_t SH_FLD_1_RESULT_LEN = 701; // 43
+const static uint64_t SH_FLD_1_SPARE_SECTOR_BUFFER_CONTROL = 702; // 1
+const static uint64_t SH_FLD_1_STEP_ALIGN_DISABLE = 703; // 1
+const static uint64_t SH_FLD_1_STEP_ALIGN_THRESHOLD = 704; // 1
+const static uint64_t SH_FLD_1_STEP_ALIGN_THRESHOLD_LEN = 705; // 1
+const static uint64_t SH_FLD_1_STEP_CHECK_CONSTANT_CPS_ENABLE = 706; // 2
+const static uint64_t SH_FLD_1_STEP_CHECK_CPS_DEVIATION = 707; // 2
+const static uint64_t SH_FLD_1_STEP_CHECK_CPS_DEVIATION_LEN = 708; // 2
+const static uint64_t SH_FLD_1_STEP_CHECK_VALIDITY_COUNT = 709; // 2
+const static uint64_t SH_FLD_1_STEP_CHECK_VALIDITY_COUNT_LEN = 710; // 2
+const static uint64_t SH_FLD_1_STEP_STEER_ENABLE = 711; // 1
+const static uint64_t SH_FLD_2 = 712; // 458
+const static uint64_t SH_FLD_20_FREE_USAGE = 713; // 1
+const static uint64_t SH_FLD_20_RESERVED = 714; // 1
+const static uint64_t SH_FLD_20_SPARE_OSC = 715; // 1
+const static uint64_t SH_FLD_20_SPARE_PLL_CONTROL = 716; // 1
+const static uint64_t SH_FLD_20_SPARE_RESONANT_CLOCKING_CONTROL = 717; // 1
+const static uint64_t SH_FLD_21_FREE_USAGE = 718; // 1
+const static uint64_t SH_FLD_21_RESERVED = 719; // 1
+const static uint64_t SH_FLD_21_SPARE_OSC = 720; // 1
+const static uint64_t SH_FLD_21_SPARE_PLL_CONTROL = 721; // 1
+const static uint64_t SH_FLD_21_SPARE_RESONANT_CLOCKING_CONTROL = 722; // 1
+const static uint64_t SH_FLD_22_FREE_USAGE = 723; // 1
+const static uint64_t SH_FLD_22_RESERVED = 724; // 2
+const static uint64_t SH_FLD_22_SPARE_OSC = 725; // 1
+const static uint64_t SH_FLD_22_SPARE_PLL_CONTROL = 726; // 1
+const static uint64_t SH_FLD_22_SPARE_RESONANT_CLOCKING_CONTROL = 727; // 1
+const static uint64_t SH_FLD_22_SPARE_TEST = 728; // 1
+const static uint64_t SH_FLD_23 = 729; // 96
+const static uint64_t SH_FLD_23_0_11 = 730; // 16
+const static uint64_t SH_FLD_23_0_11_LEN = 731; // 16
+const static uint64_t SH_FLD_23_12_15 = 732; // 16
+const static uint64_t SH_FLD_23_12_15_LEN = 733; // 16
+const static uint64_t SH_FLD_23_ADVANCE_PING_PONG = 734; // 16
+const static uint64_t SH_FLD_23_ADVANCE_PR_VALUE = 735; // 16
+const static uint64_t SH_FLD_23_ATEST_MUX_CTL0 = 736; // 16
+const static uint64_t SH_FLD_23_ATEST_MUX_CTL1 = 737; // 16
+const static uint64_t SH_FLD_23_ATEST_MUX_CTL2 = 738; // 16
+const static uint64_t SH_FLD_23_ATEST_MUX_CTL3 = 739; // 16
+const static uint64_t SH_FLD_23_ATEST_MUX_CTL_EN = 740; // 16
+const static uint64_t SH_FLD_23_BB_LOCK0 = 741; // 16
+const static uint64_t SH_FLD_23_BB_LOCK1 = 742; // 16
+const static uint64_t SH_FLD_23_BIG_STEP_RIGHT = 743; // 16
+const static uint64_t SH_FLD_23_BIT_CENTERED = 744; // 16
+const static uint64_t SH_FLD_23_BIT_CENTERED_LEN = 745; // 16
+const static uint64_t SH_FLD_23_BLFIFO_DIS = 746; // 16
+const static uint64_t SH_FLD_23_BUMP = 747; // 16
+const static uint64_t SH_FLD_23_CALGATE_ON = 748; // 16
+const static uint64_t SH_FLD_23_CALIBRATE_BIT = 749; // 16
+const static uint64_t SH_FLD_23_CALIBRATE_BIT_LEN = 750; // 16
+const static uint64_t SH_FLD_23_CE0DLTVCC1 = 751; // 16
+const static uint64_t SH_FLD_23_CE0DLTVCCA = 752; // 16
+const static uint64_t SH_FLD_23_CHECKER_ENABLE = 753; // 16
+const static uint64_t SH_FLD_23_CHECKER_RESET = 754; // 16
+const static uint64_t SH_FLD_23_CLK16_SINGLE_ENDED = 755; // 128
+const static uint64_t SH_FLD_23_CLK18_SINGLE_ENDED = 756; // 128
+const static uint64_t SH_FLD_23_CLK20_SINGLE_ENDED = 757; // 128
+const static uint64_t SH_FLD_23_CLK22_SINGLE_ENDED = 758; // 128
+const static uint64_t SH_FLD_23_CLK_LEVEL = 759; // 16
+const static uint64_t SH_FLD_23_CLK_LEVEL_LEN = 760; // 16
+const static uint64_t SH_FLD_23_CNTL_POL = 761; // 16
+const static uint64_t SH_FLD_23_CNTL_SRC = 762; // 16
+const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N0 = 763; // 16
+const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N0_MASK = 764; // 16
+const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N1 = 765; // 16
+const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N1_MASK = 766; // 16
+const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N2 = 767; // 16
+const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N2_MASK = 768; // 16
+const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N3 = 769; // 16
+const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N3_MASK = 770; // 16
+const static uint64_t SH_FLD_23_CONTINUOUS_UPDATE = 771; // 32
+const static uint64_t SH_FLD_23_DD2_DQS_FIX_DIS = 772; // 16
+const static uint64_t SH_FLD_23_DD2_FIX_DIS = 773; // 16
+const static uint64_t SH_FLD_23_DD2_WTRFL_SYNC_DIS = 774; // 16
+const static uint64_t SH_FLD_23_DELAY1 = 775; // 16
+const static uint64_t SH_FLD_23_DELAY10 = 776; // 16
+const static uint64_t SH_FLD_23_DELAY10_LEN = 777; // 16
+const static uint64_t SH_FLD_23_DELAY11 = 778; // 16
+const static uint64_t SH_FLD_23_DELAY11_LEN = 779; // 16
+const static uint64_t SH_FLD_23_DELAY12 = 780; // 16
+const static uint64_t SH_FLD_23_DELAY12_LEN = 781; // 16
+const static uint64_t SH_FLD_23_DELAY13 = 782; // 16
+const static uint64_t SH_FLD_23_DELAY13_LEN = 783; // 16
+const static uint64_t SH_FLD_23_DELAY14 = 784; // 16
+const static uint64_t SH_FLD_23_DELAY14_LEN = 785; // 16
+const static uint64_t SH_FLD_23_DELAY15 = 786; // 16
+const static uint64_t SH_FLD_23_DELAY15_LEN = 787; // 16
+const static uint64_t SH_FLD_23_DELAY1_LEN = 788; // 16
+const static uint64_t SH_FLD_23_DELAY2 = 789; // 16
+const static uint64_t SH_FLD_23_DELAY2_LEN = 790; // 16
+const static uint64_t SH_FLD_23_DELAY3 = 791; // 16
+const static uint64_t SH_FLD_23_DELAY3_LEN = 792; // 16
+const static uint64_t SH_FLD_23_DELAY4 = 793; // 16
+const static uint64_t SH_FLD_23_DELAY4_LEN = 794; // 16
+const static uint64_t SH_FLD_23_DELAY5 = 795; // 16
+const static uint64_t SH_FLD_23_DELAY5_LEN = 796; // 16
+const static uint64_t SH_FLD_23_DELAY6 = 797; // 16
+const static uint64_t SH_FLD_23_DELAY6_LEN = 798; // 16
+const static uint64_t SH_FLD_23_DELAY7 = 799; // 16
+const static uint64_t SH_FLD_23_DELAY7_LEN = 800; // 16
+const static uint64_t SH_FLD_23_DELAY8 = 801; // 16
+const static uint64_t SH_FLD_23_DELAY8_LEN = 802; // 16
+const static uint64_t SH_FLD_23_DELAY9 = 803; // 16
+const static uint64_t SH_FLD_23_DELAY9_LEN = 804; // 16
+const static uint64_t SH_FLD_23_DELAYG = 805; // 1280
+const static uint64_t SH_FLD_23_DELAYG_LEN = 806; // 1280
+const static uint64_t SH_FLD_23_DELAY_PING_PONG_HALF = 807; // 16
+const static uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_HIGH = 808; // 16
+const static uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 809; // 16
+const static uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_LOW = 810; // 16
+const static uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 811; // 16
+const static uint64_t SH_FLD_23_DFT_FORCE_OUTPUTS = 812; // 16
+const static uint64_t SH_FLD_23_DFT_PRBS7_GEN_EN = 813; // 16
+const static uint64_t SH_FLD_23_DIGITAL_EN = 814; // 16
+const static uint64_t SH_FLD_23_DIR_0_15 = 815; // 16
+const static uint64_t SH_FLD_23_DIR_0_15_LEN = 816; // 16
+const static uint64_t SH_FLD_23_DISABLE_0_15 = 817; // 64
+const static uint64_t SH_FLD_23_DISABLE_0_15_LEN = 818; // 64
+const static uint64_t SH_FLD_23_DISABLE_16_23 = 819; // 64
+const static uint64_t SH_FLD_23_DISABLE_16_23_LEN = 820; // 64
+const static uint64_t SH_FLD_23_DISABLE_PING_PONG = 821; // 16
+const static uint64_t SH_FLD_23_DISABLE_TERMINATION = 822; // 16
+const static uint64_t SH_FLD_23_DIS_CLK_GATE = 823; // 16
+const static uint64_t SH_FLD_23_DI_ADR0_ADR1 = 824; // 16
+const static uint64_t SH_FLD_23_DI_ADR10_ADR11 = 825; // 16
+const static uint64_t SH_FLD_23_DI_ADR12_ADR13 = 826; // 16
+const static uint64_t SH_FLD_23_DI_ADR14_ADR15 = 827; // 16
+const static uint64_t SH_FLD_23_DI_ADR2 = 828; // 8
+const static uint64_t SH_FLD_23_DI_ADR3 = 829; // 8
+const static uint64_t SH_FLD_23_DI_ADR4_ADR5 = 830; // 16
+const static uint64_t SH_FLD_23_DI_ADR6_ADR7 = 831; // 16
+const static uint64_t SH_FLD_23_DI_ADR8_ADR9 = 832; // 16
+const static uint64_t SH_FLD_23_DL_FORCE_ON = 833; // 16
+const static uint64_t SH_FLD_23_DONE = 834; // 32
+const static uint64_t SH_FLD_23_DQS = 835; // 16
+const static uint64_t SH_FLD_23_DQSCLK_SELECT0 = 836; // 64
+const static uint64_t SH_FLD_23_DQSCLK_SELECT0_LEN = 837; // 64
+const static uint64_t SH_FLD_23_DQSCLK_SELECT1 = 838; // 64
+const static uint64_t SH_FLD_23_DQSCLK_SELECT1_LEN = 839; // 64
+const static uint64_t SH_FLD_23_DQSCLK_SELECT2 = 840; // 64
+const static uint64_t SH_FLD_23_DQSCLK_SELECT2_LEN = 841; // 64
+const static uint64_t SH_FLD_23_DQSCLK_SELECT3 = 842; // 64
+const static uint64_t SH_FLD_23_DQSCLK_SELECT3_LEN = 843; // 64
+const static uint64_t SH_FLD_23_DQS_ALIGN_CNTR = 844; // 16
+const static uint64_t SH_FLD_23_DQS_ALIGN_CNTR_LEN = 845; // 16
+const static uint64_t SH_FLD_23_DQS_ALIGN_FIX_DIS = 846; // 16
+const static uint64_t SH_FLD_23_DQS_ALIGN_ITR_CNTR = 847; // 16
+const static uint64_t SH_FLD_23_DQS_ALIGN_ITR_CNTR_LEN = 848; // 16
+const static uint64_t SH_FLD_23_DQS_ALIGN_JITTER = 849; // 16
+const static uint64_t SH_FLD_23_DQS_ALIGN_QUAD = 850; // 16
+const static uint64_t SH_FLD_23_DQS_ALIGN_QUAD_LEN = 851; // 16
+const static uint64_t SH_FLD_23_DQS_ALIGN_SM = 852; // 16
+const static uint64_t SH_FLD_23_DQS_ALIGN_SM_LEN = 853; // 16
+const static uint64_t SH_FLD_23_DQS_LEN = 854; // 16
+const static uint64_t SH_FLD_23_DQS_PIPE_FIX_DIS = 855; // 16
+const static uint64_t SH_FLD_23_DQS_PIPE_FIX_DIS_LEN = 856; // 16
+const static uint64_t SH_FLD_23_DRIFT_ERROR = 857; // 16
+const static uint64_t SH_FLD_23_DRIFT_MASK = 858; // 16
+const static uint64_t SH_FLD_23_DYN_MCTERM_CNTL_EN = 859; // 16
+const static uint64_t SH_FLD_23_DYN_POWER_CNTL_EN = 860; // 16
+const static uint64_t SH_FLD_23_DYN_RX_GATE_CNTL_EN = 861; // 16
+const static uint64_t SH_FLD_23_ENABLE = 862; // 32
+const static uint64_t SH_FLD_23_ENABLE_0_15 = 863; // 16
+const static uint64_t SH_FLD_23_ENABLE_0_15_LEN = 864; // 16
+const static uint64_t SH_FLD_23_ENABLE_16_23 = 865; // 16
+const static uint64_t SH_FLD_23_ENABLE_16_23_LEN = 866; // 16
+const static uint64_t SH_FLD_23_EN_DQS_OFFSET = 867; // 16
+const static uint64_t SH_FLD_23_EN_N_WR = 868; // 16
+const static uint64_t SH_FLD_23_EN_N_WR_LEN = 869; // 16
+const static uint64_t SH_FLD_23_EN_P_WR = 870; // 32
+const static uint64_t SH_FLD_23_EN_P_WR_LEN = 871; // 32
+const static uint64_t SH_FLD_23_ERROR = 872; // 16
+const static uint64_t SH_FLD_23_ERROR_LEN = 873; // 16
+const static uint64_t SH_FLD_23_ERR_CLK22_MASK = 874; // 16
+const static uint64_t SH_FLD_23_EYE_CLIPPING = 875; // 16
+const static uint64_t SH_FLD_23_EYE_CLIPPING_MASK = 876; // 16
+const static uint64_t SH_FLD_23_FINE_STEPPING = 877; // 16
+const static uint64_t SH_FLD_23_FORCE_FIFO_CAPTURE = 878; // 16
+const static uint64_t SH_FLD_23_FREE_USAGE = 879; // 1
+const static uint64_t SH_FLD_23_FW_LEFT_SIDE = 880; // 16
+const static uint64_t SH_FLD_23_FW_LEFT_SIDE_LEN = 881; // 16
+const static uint64_t SH_FLD_23_FW_RIGHT_SIDE = 882; // 16
+const static uint64_t SH_FLD_23_FW_RIGHT_SIDE_LEN = 883; // 16
+const static uint64_t SH_FLD_23_HS_PROBE_A = 884; // 16
+const static uint64_t SH_FLD_23_HS_PROBE_A_LEN = 885; // 16
+const static uint64_t SH_FLD_23_HS_PROBE_B = 886; // 16
+const static uint64_t SH_FLD_23_HS_PROBE_B_LEN = 887; // 16
+const static uint64_t SH_FLD_23_HW_VALUE = 888; // 16
+const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N0 = 889; // 16
+const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N0_MASK = 890; // 16
+const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N1 = 891; // 16
+const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N1_MASK = 892; // 16
+const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N2 = 893; // 16
+const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N2_MASK = 894; // 16
+const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N3 = 895; // 16
+const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N3_MASK = 896; // 16
+const static uint64_t SH_FLD_23_INIT_RXDLL_CAL_RESET = 897; // 32
+const static uint64_t SH_FLD_23_INIT_RXDLL_CAL_UPDATE = 898; // 32
+const static uint64_t SH_FLD_23_INTERP_SIG_SLEW = 899; // 16
+const static uint64_t SH_FLD_23_INTERP_SIG_SLEW_LEN = 900; // 16
+const static uint64_t SH_FLD_23_INVALID_NS_BIG_R = 901; // 16
+const static uint64_t SH_FLD_23_INVALID_NS_BIG_R_MASK = 902; // 16
+const static uint64_t SH_FLD_23_INVALID_NS_SMALL_L = 903; // 16
+const static uint64_t SH_FLD_23_INVALID_NS_SMALL_L_MASK = 904; // 16
+const static uint64_t SH_FLD_23_INVALID_NS_SMALL_R = 905; // 16
+const static uint64_t SH_FLD_23_INVALID_NS_SMALL_R_MASK = 906; // 16
+const static uint64_t SH_FLD_23_JUMP_BACK_RIGHT = 907; // 16
+const static uint64_t SH_FLD_23_LANE__0_11_PD = 908; // 16
+const static uint64_t SH_FLD_23_LANE__0_11_PD_LEN = 909; // 16
+const static uint64_t SH_FLD_23_LANE__12_15_PD = 910; // 16
+const static uint64_t SH_FLD_23_LANE__12_15_PD_LEN = 911; // 16
+const static uint64_t SH_FLD_23_LEADING_EDGE_FOUND_MASK = 912; // 16
+const static uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND = 913; // 16
+const static uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_0_15 = 914; // 16
+const static uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_0_15_LEN = 915; // 16
+const static uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_16_23 = 916; // 16
+const static uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_16_23_LEN = 917; // 16
+const static uint64_t SH_FLD_23_LEN = 918; // 96
+const static uint64_t SH_FLD_23_LOOPBACK_DLY12 = 919; // 16
+const static uint64_t SH_FLD_23_LOOPBACK_FIX_EN = 920; // 16
+const static uint64_t SH_FLD_23_MATCH_STEP_RIGHT = 921; // 16
+const static uint64_t SH_FLD_23_MAX_DQS = 922; // 16
+const static uint64_t SH_FLD_23_MAX_DQS_ITER = 923; // 16
+const static uint64_t SH_FLD_23_MAX_DQS_LEN = 924; // 16
+const static uint64_t SH_FLD_23_MEMINTD00 = 925; // 16
+const static uint64_t SH_FLD_23_MEMINTD00_LEN = 926; // 16
+const static uint64_t SH_FLD_23_MEMINTD01 = 927; // 16
+const static uint64_t SH_FLD_23_MEMINTD01_LEN = 928; // 16
+const static uint64_t SH_FLD_23_MEMINTD02 = 929; // 16
+const static uint64_t SH_FLD_23_MEMINTD02_LEN = 930; // 16
+const static uint64_t SH_FLD_23_MEMINTD03 = 931; // 16
+const static uint64_t SH_FLD_23_MEMINTD03_LEN = 932; // 16
+const static uint64_t SH_FLD_23_MEMINTD04 = 933; // 16
+const static uint64_t SH_FLD_23_MEMINTD04_LEN = 934; // 16
+const static uint64_t SH_FLD_23_MEMINTD05 = 935; // 16
+const static uint64_t SH_FLD_23_MEMINTD05_LEN = 936; // 16
+const static uint64_t SH_FLD_23_MEMINTD06 = 937; // 16
+const static uint64_t SH_FLD_23_MEMINTD06_LEN = 938; // 16
+const static uint64_t SH_FLD_23_MEMINTD07 = 939; // 16
+const static uint64_t SH_FLD_23_MEMINTD07_LEN = 940; // 16
+const static uint64_t SH_FLD_23_MEMINTD08 = 941; // 16
+const static uint64_t SH_FLD_23_MEMINTD08_LEN = 942; // 16
+const static uint64_t SH_FLD_23_MEMINTD09 = 943; // 16
+const static uint64_t SH_FLD_23_MEMINTD09_LEN = 944; // 16
+const static uint64_t SH_FLD_23_MEMINTD10 = 945; // 16
+const static uint64_t SH_FLD_23_MEMINTD10_LEN = 946; // 16
+const static uint64_t SH_FLD_23_MEMINTD11 = 947; // 16
+const static uint64_t SH_FLD_23_MEMINTD11_LEN = 948; // 16
+const static uint64_t SH_FLD_23_MEMINTD12 = 949; // 16
+const static uint64_t SH_FLD_23_MEMINTD12_LEN = 950; // 16
+const static uint64_t SH_FLD_23_MEMINTD13 = 951; // 16
+const static uint64_t SH_FLD_23_MEMINTD13_LEN = 952; // 16
+const static uint64_t SH_FLD_23_MEMINTD14 = 953; // 16
+const static uint64_t SH_FLD_23_MEMINTD14_LEN = 954; // 16
+const static uint64_t SH_FLD_23_MEMINTD15 = 955; // 16
+const static uint64_t SH_FLD_23_MEMINTD15_LEN = 956; // 16
+const static uint64_t SH_FLD_23_MEMINTD16 = 957; // 16
+const static uint64_t SH_FLD_23_MEMINTD16_LEN = 958; // 16
+const static uint64_t SH_FLD_23_MEMINTD17 = 959; // 16
+const static uint64_t SH_FLD_23_MEMINTD17_LEN = 960; // 16
+const static uint64_t SH_FLD_23_MEMINTD18 = 961; // 16
+const static uint64_t SH_FLD_23_MEMINTD18_LEN = 962; // 16
+const static uint64_t SH_FLD_23_MEMINTD19 = 963; // 16
+const static uint64_t SH_FLD_23_MEMINTD19_LEN = 964; // 16
+const static uint64_t SH_FLD_23_MEMINTD20 = 965; // 16
+const static uint64_t SH_FLD_23_MEMINTD20_LEN = 966; // 16
+const static uint64_t SH_FLD_23_MEMINTD21 = 967; // 16
+const static uint64_t SH_FLD_23_MEMINTD21_LEN = 968; // 16
+const static uint64_t SH_FLD_23_MEMINTD22 = 969; // 16
+const static uint64_t SH_FLD_23_MEMINTD22_LEN = 970; // 16
+const static uint64_t SH_FLD_23_MEMINTD23 = 971; // 16
+const static uint64_t SH_FLD_23_MEMINTD23_LEN = 972; // 16
+const static uint64_t SH_FLD_23_MIN_EYE = 973; // 16
+const static uint64_t SH_FLD_23_MIN_EYE_MASK = 974; // 16
+const static uint64_t SH_FLD_23_MIN_RD_EYE_SIZE = 975; // 16
+const static uint64_t SH_FLD_23_MIN_RD_EYE_SIZE_LEN = 976; // 16
+const static uint64_t SH_FLD_23_MRS_CMD_N0 = 977; // 16
+const static uint64_t SH_FLD_23_MRS_CMD_N1 = 978; // 16
+const static uint64_t SH_FLD_23_MRS_CMD_N2 = 979; // 16
+const static uint64_t SH_FLD_23_MRS_CMD_N3 = 980; // 16
+const static uint64_t SH_FLD_23_N0 = 981; // 128
+const static uint64_t SH_FLD_23_N0_LEN = 982; // 128
+const static uint64_t SH_FLD_23_N1 = 983; // 128
+const static uint64_t SH_FLD_23_N1_LEN = 984; // 128
+const static uint64_t SH_FLD_23_N2 = 985; // 128
+const static uint64_t SH_FLD_23_N2_LEN = 986; // 128
+const static uint64_t SH_FLD_23_N3 = 987; // 128
+const static uint64_t SH_FLD_23_N3_LEN = 988; // 128
+const static uint64_t SH_FLD_23_NIB0 = 989; // 16
+const static uint64_t SH_FLD_23_NIB0TCFLIP_DC = 990; // 16
+const static uint64_t SH_FLD_23_NIB0_LEN = 991; // 16
+const static uint64_t SH_FLD_23_NIB1 = 992; // 16
+const static uint64_t SH_FLD_23_NIB1TCFLIP_DC = 993; // 16
+const static uint64_t SH_FLD_23_NIB1_LEN = 994; // 16
+const static uint64_t SH_FLD_23_NIB2 = 995; // 16
+const static uint64_t SH_FLD_23_NIB2TCFLIP_DC = 996; // 16
+const static uint64_t SH_FLD_23_NIB2_LEN = 997; // 16
+const static uint64_t SH_FLD_23_NIB3 = 998; // 16
+const static uint64_t SH_FLD_23_NIB3TCFLIP_DC = 999; // 16
+const static uint64_t SH_FLD_23_NIB3_LEN = 1000; // 16
+const static uint64_t SH_FLD_23_NIB_0_2_DQSEL_CAP = 1001; // 16
+const static uint64_t SH_FLD_23_NIB_0_2_DQSEL_CAP_LEN = 1002; // 16
+const static uint64_t SH_FLD_23_NIB_0_2_DQSEL_IND = 1003; // 16
+const static uint64_t SH_FLD_23_NIB_0_2_DQSEL_IND_LEN = 1004; // 16
+const static uint64_t SH_FLD_23_NIB_0_2_DQSEL_RES = 1005; // 16
+const static uint64_t SH_FLD_23_NIB_0_2_DQSEL_RES_LEN = 1006; // 16
+const static uint64_t SH_FLD_23_NIB_0_DQSEL_CAP = 1007; // 16
+const static uint64_t SH_FLD_23_NIB_0_DQSEL_CAP_LEN = 1008; // 16
+const static uint64_t SH_FLD_23_NIB_0_DQSEL_IND = 1009; // 16
+const static uint64_t SH_FLD_23_NIB_0_DQSEL_IND_LEN = 1010; // 16
+const static uint64_t SH_FLD_23_NIB_0_DQSEL_RES = 1011; // 16
+const static uint64_t SH_FLD_23_NIB_0_DQSEL_RES_LEN = 1012; // 16
+const static uint64_t SH_FLD_23_NIB_1_3_DQSEL_CAP = 1013; // 16
+const static uint64_t SH_FLD_23_NIB_1_3_DQSEL_CAP_LEN = 1014; // 16
+const static uint64_t SH_FLD_23_NIB_1_3_DQSEL_IND = 1015; // 16
+const static uint64_t SH_FLD_23_NIB_1_3_DQSEL_IND_LEN = 1016; // 16
+const static uint64_t SH_FLD_23_NIB_1_3_DQSEL_RES = 1017; // 16
+const static uint64_t SH_FLD_23_NIB_1_3_DQSEL_RES_LEN = 1018; // 16
+const static uint64_t SH_FLD_23_NIB_1_DQSEL_CAP = 1019; // 16
+const static uint64_t SH_FLD_23_NIB_1_DQSEL_CAP_LEN = 1020; // 16
+const static uint64_t SH_FLD_23_NIB_1_DQSEL_IND = 1021; // 16
+const static uint64_t SH_FLD_23_NIB_1_DQSEL_IND_LEN = 1022; // 16
+const static uint64_t SH_FLD_23_NIB_1_DQSEL_RES = 1023; // 16
+const static uint64_t SH_FLD_23_NIB_1_DQSEL_RES_LEN = 1024; // 16
+const static uint64_t SH_FLD_23_NO_DQS = 1025; // 16
+const static uint64_t SH_FLD_23_NO_DQS_MASK = 1026; // 16
+const static uint64_t SH_FLD_23_NO_EYE_DETECTED = 1027; // 16
+const static uint64_t SH_FLD_23_NO_EYE_DETECTED_MASK = 1028; // 16
+const static uint64_t SH_FLD_23_NO_LOCK = 1029; // 16
+const static uint64_t SH_FLD_23_NO_LOCK_MASK = 1030; // 16
+const static uint64_t SH_FLD_23_OFFSET0 = 1031; // 16
+const static uint64_t SH_FLD_23_OFFSET0_LEN = 1032; // 16
+const static uint64_t SH_FLD_23_OFFSET1 = 1033; // 16
+const static uint64_t SH_FLD_23_OFFSET1_LEN = 1034; // 16
+const static uint64_t SH_FLD_23_OFFSET2 = 1035; // 32
+const static uint64_t SH_FLD_23_OFFSET2_LEN = 1036; // 32
+const static uint64_t SH_FLD_23_OFFSET3 = 1037; // 32
+const static uint64_t SH_FLD_23_OFFSET3_LEN = 1038; // 32
+const static uint64_t SH_FLD_23_OFFSET4 = 1039; // 32
+const static uint64_t SH_FLD_23_OFFSET4_LEN = 1040; // 32
+const static uint64_t SH_FLD_23_OFFSET5 = 1041; // 32
+const static uint64_t SH_FLD_23_OFFSET5_LEN = 1042; // 32
+const static uint64_t SH_FLD_23_OFFSET6 = 1043; // 32
+const static uint64_t SH_FLD_23_OFFSET6_LEN = 1044; // 32
+const static uint64_t SH_FLD_23_OFFSET7 = 1045; // 32
+const static uint64_t SH_FLD_23_OFFSET7_LEN = 1046; // 32
+const static uint64_t SH_FLD_23_OFFSET_ERR = 1047; // 16
+const static uint64_t SH_FLD_23_OFFSET_ERR_MASK = 1048; // 16
+const static uint64_t SH_FLD_23_OPERATE_MODE = 1049; // 16
+const static uint64_t SH_FLD_23_OPERATE_MODE_LEN = 1050; // 16
+const static uint64_t SH_FLD_23_PERCAL_PWR_DIS = 1051; // 16
+const static uint64_t SH_FLD_23_PER_CAL_UPDATE_DISABLE = 1052; // 16
+const static uint64_t SH_FLD_23_PHASE_ALIGN_RESET = 1053; // 32
+const static uint64_t SH_FLD_23_PHASE_CNTL_EN = 1054; // 32
+const static uint64_t SH_FLD_23_PHASE_DEFAULT_EN = 1055; // 32
+const static uint64_t SH_FLD_23_POS_EDGE_ALIGN = 1056; // 32
+const static uint64_t SH_FLD_23_QUAD0 = 1057; // 16
+const static uint64_t SH_FLD_23_QUAD0_CLK16 = 1058; // 128
+const static uint64_t SH_FLD_23_QUAD0_CLK18 = 1059; // 128
+const static uint64_t SH_FLD_23_QUAD0_LEN = 1060; // 16
+const static uint64_t SH_FLD_23_QUAD1 = 1061; // 16
+const static uint64_t SH_FLD_23_QUAD1_CLK16 = 1062; // 128
+const static uint64_t SH_FLD_23_QUAD1_CLK18 = 1063; // 128
+const static uint64_t SH_FLD_23_QUAD1_LEN = 1064; // 16
+const static uint64_t SH_FLD_23_QUAD2 = 1065; // 16
+const static uint64_t SH_FLD_23_QUAD2_CLK16 = 1066; // 128
+const static uint64_t SH_FLD_23_QUAD2_CLK18 = 1067; // 64
+const static uint64_t SH_FLD_23_QUAD2_CLK20 = 1068; // 128
+const static uint64_t SH_FLD_23_QUAD2_CLK22 = 1069; // 128
+const static uint64_t SH_FLD_23_QUAD2_LEN = 1070; // 16
+const static uint64_t SH_FLD_23_QUAD3 = 1071; // 16
+const static uint64_t SH_FLD_23_QUAD3_CLK16 = 1072; // 128
+const static uint64_t SH_FLD_23_QUAD3_CLK18 = 1073; // 64
+const static uint64_t SH_FLD_23_QUAD3_CLK20 = 1074; // 128
+const static uint64_t SH_FLD_23_QUAD3_CLK22 = 1075; // 128
+const static uint64_t SH_FLD_23_QUAD3_LEN = 1076; // 16
+const static uint64_t SH_FLD_23_RD = 1077; // 272
+const static uint64_t SH_FLD_23_RDCLK_SELECT0 = 1078; // 64
+const static uint64_t SH_FLD_23_RDCLK_SELECT0_LEN = 1079; // 64
+const static uint64_t SH_FLD_23_RDCLK_SELECT1 = 1080; // 64
+const static uint64_t SH_FLD_23_RDCLK_SELECT1_LEN = 1081; // 64
+const static uint64_t SH_FLD_23_RDCLK_SELECT2 = 1082; // 64
+const static uint64_t SH_FLD_23_RDCLK_SELECT2_LEN = 1083; // 64
+const static uint64_t SH_FLD_23_RDCLK_SELECT3 = 1084; // 64
+const static uint64_t SH_FLD_23_RDCLK_SELECT3_LEN = 1085; // 64
+const static uint64_t SH_FLD_23_RD_DELAY0 = 1086; // 112
+const static uint64_t SH_FLD_23_RD_DELAY0_LEN = 1087; // 112
+const static uint64_t SH_FLD_23_RD_DELAY1 = 1088; // 112
+const static uint64_t SH_FLD_23_RD_DELAY1_LEN = 1089; // 112
+const static uint64_t SH_FLD_23_RD_DELAY2 = 1090; // 112
+const static uint64_t SH_FLD_23_RD_DELAY2_LEN = 1091; // 112
+const static uint64_t SH_FLD_23_RD_DELAY3 = 1092; // 112
+const static uint64_t SH_FLD_23_RD_DELAY3_LEN = 1093; // 112
+const static uint64_t SH_FLD_23_RD_DELAY4 = 1094; // 112
+const static uint64_t SH_FLD_23_RD_DELAY4_LEN = 1095; // 112
+const static uint64_t SH_FLD_23_RD_DELAY5 = 1096; // 112
+const static uint64_t SH_FLD_23_RD_DELAY5_LEN = 1097; // 112
+const static uint64_t SH_FLD_23_RD_DELAY6 = 1098; // 112
+const static uint64_t SH_FLD_23_RD_DELAY6_LEN = 1099; // 112
+const static uint64_t SH_FLD_23_RD_DELAY7 = 1100; // 112
+const static uint64_t SH_FLD_23_RD_DELAY7_LEN = 1101; // 112
+const static uint64_t SH_FLD_23_RD_LEN = 1102; // 272
+const static uint64_t SH_FLD_23_RD_SIZE0 = 1103; // 176
+const static uint64_t SH_FLD_23_RD_SIZE0_LEN = 1104; // 176
+const static uint64_t SH_FLD_23_RD_SIZE1 = 1105; // 176
+const static uint64_t SH_FLD_23_RD_SIZE1_LEN = 1106; // 176
+const static uint64_t SH_FLD_23_RD_SIZE2 = 1107; // 176
+const static uint64_t SH_FLD_23_RD_SIZE2_LEN = 1108; // 176
+const static uint64_t SH_FLD_23_RD_SIZE3 = 1109; // 176
+const static uint64_t SH_FLD_23_RD_SIZE3_LEN = 1110; // 176
+const static uint64_t SH_FLD_23_RD_SIZE4 = 1111; // 176
+const static uint64_t SH_FLD_23_RD_SIZE4_LEN = 1112; // 176
+const static uint64_t SH_FLD_23_RD_SIZE5 = 1113; // 176
+const static uint64_t SH_FLD_23_RD_SIZE5_LEN = 1114; // 176
+const static uint64_t SH_FLD_23_RD_SIZE6 = 1115; // 176
+const static uint64_t SH_FLD_23_RD_SIZE6_LEN = 1116; // 176
+const static uint64_t SH_FLD_23_RD_SIZE7 = 1117; // 176
+const static uint64_t SH_FLD_23_RD_SIZE7_LEN = 1118; // 176
+const static uint64_t SH_FLD_23_READ_CENTERING_MODE = 1119; // 16
+const static uint64_t SH_FLD_23_READ_CENTERING_MODE_LEN = 1120; // 16
+const static uint64_t SH_FLD_23_REFERENCE1 = 1121; // 16
+const static uint64_t SH_FLD_23_REFERENCE1_LEN = 1122; // 16
+const static uint64_t SH_FLD_23_REFERENCE2 = 1123; // 16
+const static uint64_t SH_FLD_23_REFERENCE2_LEN = 1124; // 16
+const static uint64_t SH_FLD_23_REFERENCE3 = 1125; // 16
+const static uint64_t SH_FLD_23_REFERENCE3_LEN = 1126; // 16
+const static uint64_t SH_FLD_23_REGS_RXDLL_CAL_SKIP = 1127; // 32
+const static uint64_t SH_FLD_23_REGS_RXDLL_CAL_SKIP_LEN = 1128; // 32
+const static uint64_t SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY2 = 1129; // 32
+const static uint64_t SH_FLD_23_REGS_RXDLL_COARSE_EN = 1130; // 32
+const static uint64_t SH_FLD_23_REGS_RXDLL_COARSE_EN_LEN = 1131; // 32
+const static uint64_t SH_FLD_23_REGS_RXDLL_DAC_COARSE = 1132; // 32
+const static uint64_t SH_FLD_23_REGS_RXDLL_DAC_COARSE_LEN = 1133; // 32
+const static uint64_t SH_FLD_23_REGS_RXDLL_VREG_LOWER = 1134; // 32
+const static uint64_t SH_FLD_23_REGS_RXDLL_VREG_LOWER_LEN = 1135; // 32
+const static uint64_t SH_FLD_23_REGS_RXDLL_VREG_UPPER = 1136; // 32
+const static uint64_t SH_FLD_23_REGS_RXDLL_VREG_UPPER_LEN = 1137; // 32
+const static uint64_t SH_FLD_23_RESERVED = 1138; // 2
+const static uint64_t SH_FLD_23_RESERVED_56_63 = 1139; // 16
+const static uint64_t SH_FLD_23_RESERVED_56_63_LEN = 1140; // 16
+const static uint64_t SH_FLD_23_ROT0 = 1141; // 16
+const static uint64_t SH_FLD_23_ROT0_LEN = 1142; // 16
+const static uint64_t SH_FLD_23_ROT1 = 1143; // 16
+const static uint64_t SH_FLD_23_ROT1_LEN = 1144; // 16
+const static uint64_t SH_FLD_23_ROT_CLK_N0 = 1145; // 128
+const static uint64_t SH_FLD_23_ROT_CLK_N0_LEN = 1146; // 128
+const static uint64_t SH_FLD_23_ROT_CLK_N1 = 1147; // 128
+const static uint64_t SH_FLD_23_ROT_CLK_N1_LEN = 1148; // 128
+const static uint64_t SH_FLD_23_ROT_N0 = 1149; // 128
+const static uint64_t SH_FLD_23_ROT_N0_LEN = 1150; // 128
+const static uint64_t SH_FLD_23_ROT_N1 = 1151; // 128
+const static uint64_t SH_FLD_23_ROT_N1_LEN = 1152; // 128
+const static uint64_t SH_FLD_23_ROT_OVERRIDE = 1153; // 32
+const static uint64_t SH_FLD_23_ROT_OVERRIDE_EN = 1154; // 32
+const static uint64_t SH_FLD_23_ROT_OVERRIDE_LEN = 1155; // 32
+const static uint64_t SH_FLD_23_RXREG_COMPCON_DC = 1156; // 32
+const static uint64_t SH_FLD_23_RXREG_COMPCON_DC_LEN = 1157; // 32
+const static uint64_t SH_FLD_23_RXREG_CON_DC = 1158; // 32
+const static uint64_t SH_FLD_23_RXREG_DAC_PULLUP_DC = 1159; // 32
+const static uint64_t SH_FLD_23_RXREG_DRVCON_DC = 1160; // 32
+const static uint64_t SH_FLD_23_RXREG_DRVCON_DC_LEN = 1161; // 32
+const static uint64_t SH_FLD_23_RXREG_FILTER_LENGTH_DC = 1162; // 32
+const static uint64_t SH_FLD_23_RXREG_FILTER_LENGTH_DC_LEN = 1163; // 32
+const static uint64_t SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC = 1164; // 32
+const static uint64_t SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 1165; // 32
+const static uint64_t SH_FLD_23_RXREG_REF_SEL_DC = 1166; // 32
+const static uint64_t SH_FLD_23_RXREG_REF_SEL_DC_LEN = 1167; // 32
+const static uint64_t SH_FLD_23_S0ACENSLICENDRV_DC = 1168; // 16
+const static uint64_t SH_FLD_23_S0ACENSLICENDRV_DC_LEN = 1169; // 16
+const static uint64_t SH_FLD_23_S0ACENSLICEPDRV_DC = 1170; // 16
+const static uint64_t SH_FLD_23_S0ACENSLICEPDRV_DC_LEN = 1171; // 16
+const static uint64_t SH_FLD_23_S0ACENSLICEPTERM_DC = 1172; // 16
+const static uint64_t SH_FLD_23_S0ACENSLICEPTERM_DC_LEN = 1173; // 16
+const static uint64_t SH_FLD_23_S0INSDLYTAP = 1174; // 16
+const static uint64_t SH_FLD_23_S1ACENSLICENDRV_DC = 1175; // 16
+const static uint64_t SH_FLD_23_S1ACENSLICENDRV_DC_LEN = 1176; // 16
+const static uint64_t SH_FLD_23_S1ACENSLICEPDRV_DC = 1177; // 16
+const static uint64_t SH_FLD_23_S1ACENSLICEPDRV_DC_LEN = 1178; // 16
+const static uint64_t SH_FLD_23_S1ACENSLICEPTERM_DC = 1179; // 16
+const static uint64_t SH_FLD_23_S1ACENSLICEPTERM_DC_LEN = 1180; // 16
+const static uint64_t SH_FLD_23_S1INSDLYTAP = 1181; // 16
+const static uint64_t SH_FLD_23_SEL0 = 1182; // 32
+const static uint64_t SH_FLD_23_SEL0_LEN = 1183; // 16
+const static uint64_t SH_FLD_23_SEL1 = 1184; // 32
+const static uint64_t SH_FLD_23_SEL10 = 1185; // 32
+const static uint64_t SH_FLD_23_SEL10_LEN = 1186; // 32
+const static uint64_t SH_FLD_23_SEL11 = 1187; // 32
+const static uint64_t SH_FLD_23_SEL11_LEN = 1188; // 32
+const static uint64_t SH_FLD_23_SEL12 = 1189; // 32
+const static uint64_t SH_FLD_23_SEL12_LEN = 1190; // 32
+const static uint64_t SH_FLD_23_SEL13 = 1191; // 32
+const static uint64_t SH_FLD_23_SEL13_LEN = 1192; // 32
+const static uint64_t SH_FLD_23_SEL14 = 1193; // 32
+const static uint64_t SH_FLD_23_SEL14_LEN = 1194; // 32
+const static uint64_t SH_FLD_23_SEL15 = 1195; // 32
+const static uint64_t SH_FLD_23_SEL15_LEN = 1196; // 32
+const static uint64_t SH_FLD_23_SEL1_LEN = 1197; // 32
+const static uint64_t SH_FLD_23_SEL2 = 1198; // 32
+const static uint64_t SH_FLD_23_SEL2_LEN = 1199; // 32
+const static uint64_t SH_FLD_23_SEL3 = 1200; // 32
+const static uint64_t SH_FLD_23_SEL3_LEN = 1201; // 32
+const static uint64_t SH_FLD_23_SEL4 = 1202; // 32
+const static uint64_t SH_FLD_23_SEL4_LEN = 1203; // 32
+const static uint64_t SH_FLD_23_SEL5 = 1204; // 32
+const static uint64_t SH_FLD_23_SEL5_LEN = 1205; // 32
+const static uint64_t SH_FLD_23_SEL6 = 1206; // 32
+const static uint64_t SH_FLD_23_SEL6_LEN = 1207; // 32
+const static uint64_t SH_FLD_23_SEL7 = 1208; // 32
+const static uint64_t SH_FLD_23_SEL7_LEN = 1209; // 32
+const static uint64_t SH_FLD_23_SEL8 = 1210; // 32
+const static uint64_t SH_FLD_23_SEL8_LEN = 1211; // 16
+const static uint64_t SH_FLD_23_SEL9 = 1212; // 32
+const static uint64_t SH_FLD_23_SEL9_LEN = 1213; // 32
+const static uint64_t SH_FLD_23_SMALL_STEP_LEFT = 1214; // 16
+const static uint64_t SH_FLD_23_SMALL_STEP_RIGHT = 1215; // 16
+const static uint64_t SH_FLD_23_SPARE_OSC = 1216; // 1
+const static uint64_t SH_FLD_23_SPARE_PLL_CONTROL = 1217; // 1
+const static uint64_t SH_FLD_23_SPARE_RESONANT_CLOCKING_CONTROL = 1218; // 1
+const static uint64_t SH_FLD_23_SPARE_TEST = 1219; // 1
+const static uint64_t SH_FLD_23_SYNC = 1220; // 16
+const static uint64_t SH_FLD_23_SYNC_LEN = 1221; // 16
+const static uint64_t SH_FLD_23_SYSCLK_DQSCLK_OFFSET = 1222; // 16
+const static uint64_t SH_FLD_23_SYSCLK_DQSCLK_OFFSET_LEN = 1223; // 16
+const static uint64_t SH_FLD_23_SYSCLK_RDCLK_OFFSET = 1224; // 16
+const static uint64_t SH_FLD_23_SYSCLK_RDCLK_OFFSET_LEN = 1225; // 16
+const static uint64_t SH_FLD_23_TEST_4TO1_MODE = 1226; // 16
+const static uint64_t SH_FLD_23_TEST_CHECK_EN = 1227; // 16
+const static uint64_t SH_FLD_23_TEST_CLEAR_ERROR = 1228; // 16
+const static uint64_t SH_FLD_23_TEST_DATA_EN = 1229; // 16
+const static uint64_t SH_FLD_23_TEST_GEN_EN = 1230; // 16
+const static uint64_t SH_FLD_23_TEST_LANE_PAIR_FAIL = 1231; // 16
+const static uint64_t SH_FLD_23_TEST_LANE_PAIR_FAIL_LEN = 1232; // 16
+const static uint64_t SH_FLD_23_TEST_MODE = 1233; // 16
+const static uint64_t SH_FLD_23_TEST_MODE_LEN = 1234; // 16
+const static uint64_t SH_FLD_23_TEST_RESET = 1235; // 16
+const static uint64_t SH_FLD_23_TOXDRV_HIBERNATE = 1236; // 16
+const static uint64_t SH_FLD_23_TRAILING_EDGE_FOUND_MASK = 1237; // 16
+const static uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND = 1238; // 16
+const static uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_0_15 = 1239; // 16
+const static uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 1240; // 16
+const static uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_16_23 = 1241; // 16
+const static uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 1242; // 16
+const static uint64_t SH_FLD_23_TRIG_PERIOD = 1243; // 16
+const static uint64_t SH_FLD_23_TSYS = 1244; // 16
+const static uint64_t SH_FLD_23_TSYS_LEN = 1245; // 16
+const static uint64_t SH_FLD_23_TUNEATST_0 = 1246; // 16
+const static uint64_t SH_FLD_23_TUNETDIV_0 = 1247; // 8
+const static uint64_t SH_FLD_23_TUNETDIV_0_2 = 1248; // 8
+const static uint64_t SH_FLD_23_TUNETDIV_0_2_LEN = 1249; // 8
+const static uint64_t SH_FLD_23_TUNETDIV_0_LEN = 1250; // 8
+const static uint64_t SH_FLD_23_VALID_NS_BIG_L = 1251; // 16
+const static uint64_t SH_FLD_23_VALID_NS_BIG_L_MASK = 1252; // 16
+const static uint64_t SH_FLD_23_VALID_NS_BIG_R = 1253; // 16
+const static uint64_t SH_FLD_23_VALID_NS_BIG_R_MASK = 1254; // 16
+const static uint64_t SH_FLD_23_VALID_NS_JUMP_BACK = 1255; // 16
+const static uint64_t SH_FLD_23_VALID_NS_JUMP_BACK_MASK = 1256; // 16
+const static uint64_t SH_FLD_23_WL_ADVANCE_DISABLE = 1257; // 16
+const static uint64_t SH_FLD_23_WL_ERR_CLK16 = 1258; // 32
+const static uint64_t SH_FLD_23_WL_ERR_CLK16_MASK = 1259; // 16
+const static uint64_t SH_FLD_23_WL_ERR_CLK18 = 1260; // 32
+const static uint64_t SH_FLD_23_WL_ERR_CLK18_MASK = 1261; // 16
+const static uint64_t SH_FLD_23_WL_ERR_CLK20 = 1262; // 32
+const static uint64_t SH_FLD_23_WL_ERR_CLK20_MASK = 1263; // 16
+const static uint64_t SH_FLD_23_WL_ERR_CLK22 = 1264; // 32
+const static uint64_t SH_FLD_23_WR = 1265; // 16
+const static uint64_t SH_FLD_23_WRAPSEL = 1266; // 16
+const static uint64_t SH_FLD_23_WR_LEN = 1267; // 16
+const static uint64_t SH_FLD_23_WTRFL_AVE_DIS = 1268; // 16
+const static uint64_t SH_FLD_23_ZERO_DETECTED = 1269; // 16
+const static uint64_t SH_FLD_24CORE_EN = 1270; // 1
+const static uint64_t SH_FLD_24_FREE_USAGE = 1271; // 1
+const static uint64_t SH_FLD_24_RESERVED = 1272; // 2
+const static uint64_t SH_FLD_24_SPARE_CBS_CONTROL = 1273; // 1
+const static uint64_t SH_FLD_24_SPARE_OSC = 1274; // 1
+const static uint64_t SH_FLD_24_SPARE_RESONANT_CLOCKING_CONTROL = 1275; // 1
+const static uint64_t SH_FLD_25_FREE_USAGE = 1276; // 1
+const static uint64_t SH_FLD_25_SPARE_CBS_CONTROL = 1277; // 1
+const static uint64_t SH_FLD_25_SPARE_CLKIN_CONTROL = 1278; // 1
+const static uint64_t SH_FLD_25_SPARE_OSC = 1279; // 1
+const static uint64_t SH_FLD_25_SPARE_REFCLOCK_CONTROL = 1280; // 1
+const static uint64_t SH_FLD_25_SPARE_RESONANT_CLOCKING_CONTROL = 1281; // 1
+const static uint64_t SH_FLD_26_FREE_USAGE = 1282; // 1
+const static uint64_t SH_FLD_26_SPARE_CBS_CONTROL = 1283; // 1
+const static uint64_t SH_FLD_26_SPARE_CLKIN_CONTROL = 1284; // 1
+const static uint64_t SH_FLD_26_SPARE_OSC = 1285; // 1
+const static uint64_t SH_FLD_26_SPARE_REFCLOCK_CONTROL = 1286; // 1
+const static uint64_t SH_FLD_26_SPARE_RESONANT_CLOCKING_CONTROL = 1287; // 1
+const static uint64_t SH_FLD_27_FREE_USAGE = 1288; // 1
+const static uint64_t SH_FLD_27_SPARE_CBS_CONTROL = 1289; // 1
+const static uint64_t SH_FLD_27_SPARE_CLKIN_CONTROL = 1290; // 1
+const static uint64_t SH_FLD_27_SPARE_OSC = 1291; // 1
+const static uint64_t SH_FLD_27_SPARE_RESONANT_CLOCKING_CONTROL = 1292; // 1
+const static uint64_t SH_FLD_28_FREE_USAGE = 1293; // 1
+const static uint64_t SH_FLD_28_RESERVED_FOR_HTB = 1294; // 1
+const static uint64_t SH_FLD_28_SPARE_OSC = 1295; // 1
+const static uint64_t SH_FLD_28_SPARE_RESET = 1296; // 1
+const static uint64_t SH_FLD_28_SPARE_RESONANT_CLOCKING_CONTROL = 1297; // 1
+const static uint64_t SH_FLD_28_SPARE_TEST_CONTROL = 1298; // 1
+const static uint64_t SH_FLD_29_FREE_USAGE = 1299; // 1
+const static uint64_t SH_FLD_29_RESERVED_FOR_HTB = 1300; // 1
+const static uint64_t SH_FLD_29_SPARE_OSC = 1301; // 1
+const static uint64_t SH_FLD_29_SPARE_REFCLOCK_CONTROL = 1302; // 1
+const static uint64_t SH_FLD_29_SPARE_RESET = 1303; // 1
+const static uint64_t SH_FLD_29_SPARE_RESONANT_CLOCKING_CONTROL = 1304; // 1
+const static uint64_t SH_FLD_29_SPARE_TEST_CONTROL = 1305; // 1
+const static uint64_t SH_FLD_2_CANNED_0 = 1306; // 2
+const static uint64_t SH_FLD_2_CANNED_0_LEN = 1307; // 2
+const static uint64_t SH_FLD_2_CANNED_1 = 1308; // 2
+const static uint64_t SH_FLD_2_CANNED_1_LEN = 1309; // 2
+const static uint64_t SH_FLD_2_DATA = 1310; // 1
+const static uint64_t SH_FLD_2_DATA_LEN = 1311; // 1
+const static uint64_t SH_FLD_2_LEN = 1312; // 46
+const static uint64_t SH_FLD_2_RESERVED = 1313; // 1
+const static uint64_t SH_FLD_2_SPARE_SECTOR_BUFFER_CONTROL = 1314; // 1
+const static uint64_t SH_FLD_2_SPARE_SS_PLL_CONTROL = 1315; // 1
+const static uint64_t SH_FLD_3 = 1316; // 458
+const static uint64_t SH_FLD_30_FREE_USAGE = 1317; // 1
+const static uint64_t SH_FLD_30_RESERVED = 1318; // 1
+const static uint64_t SH_FLD_30_RESERVED_FOR_HTB = 1319; // 1
+const static uint64_t SH_FLD_30_SPARE_OSC = 1320; // 1
+const static uint64_t SH_FLD_30_SPARE_REFCLOCK_CONTROL = 1321; // 1
+const static uint64_t SH_FLD_30_SPARE_RESONANT_CLOCKING_CONTROL = 1322; // 1
+const static uint64_t SH_FLD_30_SPARE_TEST_CONTROL = 1323; // 1
+const static uint64_t SH_FLD_31_FREE_USAGE = 1324; // 1
+const static uint64_t SH_FLD_31_RESERVED_FOR_HTB = 1325; // 1
+const static uint64_t SH_FLD_31_SPARE_OSC = 1326; // 1
+const static uint64_t SH_FLD_31_SPARE_REFCLOCK_CONTROL = 1327; // 1
+const static uint64_t SH_FLD_31_SPARE_RESONANT_CLOCKING_CONTROL = 1328; // 1
+const static uint64_t SH_FLD_31_SPARE_TEST_CONTROL = 1329; // 1
+const static uint64_t SH_FLD_3_DATA = 1330; // 1
+const static uint64_t SH_FLD_3_DATA_LEN = 1331; // 1
+const static uint64_t SH_FLD_3_LEN = 1332; // 46
+const static uint64_t SH_FLD_3_RESERVED = 1333; // 1
+const static uint64_t SH_FLD_3_SPARE_SECTOR_BUFFER_CONTROL = 1334; // 1
+const static uint64_t SH_FLD_3_SPARE_SS_PLL_CONTROL = 1335; // 1
+const static uint64_t SH_FLD_4 = 1336; // 496
+const static uint64_t SH_FLD_46_55 = 1337; // 1
+const static uint64_t SH_FLD_46_55_LEN = 1338; // 1
+const static uint64_t SH_FLD_4X4_MODE = 1339; // 2
+const static uint64_t SH_FLD_4_ADVANCE_PING_PONG = 1340; // 8
+const static uint64_t SH_FLD_4_ADVANCE_PR_VALUE = 1341; // 8
+const static uint64_t SH_FLD_4_ATEST_MUX_CTL0 = 1342; // 8
+const static uint64_t SH_FLD_4_ATEST_MUX_CTL1 = 1343; // 8
+const static uint64_t SH_FLD_4_ATEST_MUX_CTL2 = 1344; // 8
+const static uint64_t SH_FLD_4_ATEST_MUX_CTL3 = 1345; // 8
+const static uint64_t SH_FLD_4_ATEST_MUX_CTL_EN = 1346; // 8
+const static uint64_t SH_FLD_4_BB_LOCK0 = 1347; // 8
+const static uint64_t SH_FLD_4_BB_LOCK1 = 1348; // 8
+const static uint64_t SH_FLD_4_BIG_STEP_RIGHT = 1349; // 8
+const static uint64_t SH_FLD_4_BIT_CENTERED = 1350; // 8
+const static uint64_t SH_FLD_4_BIT_CENTERED_LEN = 1351; // 8
+const static uint64_t SH_FLD_4_BLFIFO_DIS = 1352; // 8
+const static uint64_t SH_FLD_4_BUMP = 1353; // 8
+const static uint64_t SH_FLD_4_CALGATE_ON = 1354; // 8
+const static uint64_t SH_FLD_4_CALIBRATE_BIT = 1355; // 8
+const static uint64_t SH_FLD_4_CALIBRATE_BIT_LEN = 1356; // 8
+const static uint64_t SH_FLD_4_CE0DLTVCC1 = 1357; // 8
+const static uint64_t SH_FLD_4_CE0DLTVCCA = 1358; // 8
+const static uint64_t SH_FLD_4_CHECKER_ENABLE = 1359; // 8
+const static uint64_t SH_FLD_4_CHECKER_RESET = 1360; // 8
+const static uint64_t SH_FLD_4_CLK16_SINGLE_ENDED = 1361; // 64
+const static uint64_t SH_FLD_4_CLK18_SINGLE_ENDED = 1362; // 64
+const static uint64_t SH_FLD_4_CLK20_SINGLE_ENDED = 1363; // 64
+const static uint64_t SH_FLD_4_CLK22_SINGLE_ENDED = 1364; // 64
+const static uint64_t SH_FLD_4_CLK_LEVEL = 1365; // 8
+const static uint64_t SH_FLD_4_CLK_LEVEL_LEN = 1366; // 8
+const static uint64_t SH_FLD_4_CNTL_POL = 1367; // 8
+const static uint64_t SH_FLD_4_CNTL_SRC = 1368; // 8
+const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N0 = 1369; // 8
+const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N0_MASK = 1370; // 8
+const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N1 = 1371; // 8
+const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N1_MASK = 1372; // 8
+const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N2 = 1373; // 8
+const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N2_MASK = 1374; // 8
+const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N3 = 1375; // 8
+const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N3_MASK = 1376; // 8
+const static uint64_t SH_FLD_4_CONTINUOUS_UPDATE = 1377; // 16
+const static uint64_t SH_FLD_4_DD2_DQS_FIX_DIS = 1378; // 8
+const static uint64_t SH_FLD_4_DD2_FIX_DIS = 1379; // 8
+const static uint64_t SH_FLD_4_DD2_WTRFL_SYNC_DIS = 1380; // 8
+const static uint64_t SH_FLD_4_DELAYG = 1381; // 608
+const static uint64_t SH_FLD_4_DELAYG_LEN = 1382; // 608
+const static uint64_t SH_FLD_4_DELAY_PING_PONG_HALF = 1383; // 8
+const static uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_HIGH = 1384; // 8
+const static uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 1385; // 8
+const static uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_LOW = 1386; // 8
+const static uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 1387; // 8
+const static uint64_t SH_FLD_4_DFT_FORCE_OUTPUTS = 1388; // 8
+const static uint64_t SH_FLD_4_DFT_PRBS7_GEN_EN = 1389; // 8
+const static uint64_t SH_FLD_4_DIGITAL_EN = 1390; // 8
+const static uint64_t SH_FLD_4_DIR_0_15 = 1391; // 8
+const static uint64_t SH_FLD_4_DIR_0_15_LEN = 1392; // 8
+const static uint64_t SH_FLD_4_DISABLE_0_15 = 1393; // 32
+const static uint64_t SH_FLD_4_DISABLE_0_15_LEN = 1394; // 32
+const static uint64_t SH_FLD_4_DISABLE_16_23 = 1395; // 32
+const static uint64_t SH_FLD_4_DISABLE_16_23_LEN = 1396; // 32
+const static uint64_t SH_FLD_4_DISABLE_PING_PONG = 1397; // 8
+const static uint64_t SH_FLD_4_DISABLE_TERMINATION = 1398; // 8
+const static uint64_t SH_FLD_4_DIS_CLK_GATE = 1399; // 8
+const static uint64_t SH_FLD_4_DL_FORCE_ON = 1400; // 8
+const static uint64_t SH_FLD_4_DONE = 1401; // 16
+const static uint64_t SH_FLD_4_DQS = 1402; // 8
+const static uint64_t SH_FLD_4_DQSCLK_SELECT0 = 1403; // 32
+const static uint64_t SH_FLD_4_DQSCLK_SELECT0_LEN = 1404; // 32
+const static uint64_t SH_FLD_4_DQSCLK_SELECT1 = 1405; // 32
+const static uint64_t SH_FLD_4_DQSCLK_SELECT1_LEN = 1406; // 32
+const static uint64_t SH_FLD_4_DQSCLK_SELECT2 = 1407; // 32
+const static uint64_t SH_FLD_4_DQSCLK_SELECT2_LEN = 1408; // 32
+const static uint64_t SH_FLD_4_DQSCLK_SELECT3 = 1409; // 32
+const static uint64_t SH_FLD_4_DQSCLK_SELECT3_LEN = 1410; // 32
+const static uint64_t SH_FLD_4_DQS_ALIGN_CNTR = 1411; // 8
+const static uint64_t SH_FLD_4_DQS_ALIGN_CNTR_LEN = 1412; // 8
+const static uint64_t SH_FLD_4_DQS_ALIGN_FIX_DIS = 1413; // 8
+const static uint64_t SH_FLD_4_DQS_ALIGN_ITR_CNTR = 1414; // 8
+const static uint64_t SH_FLD_4_DQS_ALIGN_ITR_CNTR_LEN = 1415; // 8
+const static uint64_t SH_FLD_4_DQS_ALIGN_JITTER = 1416; // 8
+const static uint64_t SH_FLD_4_DQS_ALIGN_QUAD = 1417; // 8
+const static uint64_t SH_FLD_4_DQS_ALIGN_QUAD_LEN = 1418; // 8
+const static uint64_t SH_FLD_4_DQS_ALIGN_SM = 1419; // 8
+const static uint64_t SH_FLD_4_DQS_ALIGN_SM_LEN = 1420; // 8
+const static uint64_t SH_FLD_4_DQS_LEN = 1421; // 8
+const static uint64_t SH_FLD_4_DQS_PIPE_FIX_DIS = 1422; // 8
+const static uint64_t SH_FLD_4_DQS_PIPE_FIX_DIS_LEN = 1423; // 8
+const static uint64_t SH_FLD_4_DRIFT_ERROR = 1424; // 8
+const static uint64_t SH_FLD_4_DRIFT_MASK = 1425; // 8
+const static uint64_t SH_FLD_4_DYN_MCTERM_CNTL_EN = 1426; // 8
+const static uint64_t SH_FLD_4_DYN_POWER_CNTL_EN = 1427; // 8
+const static uint64_t SH_FLD_4_DYN_RX_GATE_CNTL_EN = 1428; // 8
+const static uint64_t SH_FLD_4_ENABLE = 1429; // 16
+const static uint64_t SH_FLD_4_ENABLE_0_15 = 1430; // 8
+const static uint64_t SH_FLD_4_ENABLE_0_15_LEN = 1431; // 8
+const static uint64_t SH_FLD_4_ENABLE_16_23 = 1432; // 8
+const static uint64_t SH_FLD_4_ENABLE_16_23_LEN = 1433; // 8
+const static uint64_t SH_FLD_4_EN_DQS_OFFSET = 1434; // 8
+const static uint64_t SH_FLD_4_EN_N_WR = 1435; // 8
+const static uint64_t SH_FLD_4_EN_N_WR_LEN = 1436; // 8
+const static uint64_t SH_FLD_4_EN_P_WR = 1437; // 16
+const static uint64_t SH_FLD_4_EN_P_WR_LEN = 1438; // 16
+const static uint64_t SH_FLD_4_ERROR = 1439; // 8
+const static uint64_t SH_FLD_4_ERROR_LEN = 1440; // 8
+const static uint64_t SH_FLD_4_ERR_CLK22_MASK = 1441; // 8
+const static uint64_t SH_FLD_4_EYE_CLIPPING = 1442; // 8
+const static uint64_t SH_FLD_4_EYE_CLIPPING_MASK = 1443; // 8
+const static uint64_t SH_FLD_4_FINE_STEPPING = 1444; // 8
+const static uint64_t SH_FLD_4_FORCE_FIFO_CAPTURE = 1445; // 8
+const static uint64_t SH_FLD_4_FW_LEFT_SIDE = 1446; // 8
+const static uint64_t SH_FLD_4_FW_LEFT_SIDE_LEN = 1447; // 8
+const static uint64_t SH_FLD_4_FW_RIGHT_SIDE = 1448; // 8
+const static uint64_t SH_FLD_4_FW_RIGHT_SIDE_LEN = 1449; // 8
+const static uint64_t SH_FLD_4_HS_PROBE_A = 1450; // 8
+const static uint64_t SH_FLD_4_HS_PROBE_A_LEN = 1451; // 8
+const static uint64_t SH_FLD_4_HS_PROBE_B = 1452; // 8
+const static uint64_t SH_FLD_4_HS_PROBE_B_LEN = 1453; // 8
+const static uint64_t SH_FLD_4_HW_VALUE = 1454; // 8
+const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N0 = 1455; // 8
+const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N0_MASK = 1456; // 8
+const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N1 = 1457; // 8
+const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N1_MASK = 1458; // 8
+const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N2 = 1459; // 8
+const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N2_MASK = 1460; // 8
+const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N3 = 1461; // 8
+const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N3_MASK = 1462; // 8
+const static uint64_t SH_FLD_4_INIT_RXDLL_CAL_RESET = 1463; // 16
+const static uint64_t SH_FLD_4_INIT_RXDLL_CAL_UPDATE = 1464; // 16
+const static uint64_t SH_FLD_4_INTERP_SIG_SLEW = 1465; // 8
+const static uint64_t SH_FLD_4_INTERP_SIG_SLEW_LEN = 1466; // 8
+const static uint64_t SH_FLD_4_INVALID_NS_BIG_R = 1467; // 8
+const static uint64_t SH_FLD_4_INVALID_NS_BIG_R_MASK = 1468; // 8
+const static uint64_t SH_FLD_4_INVALID_NS_SMALL_L = 1469; // 8
+const static uint64_t SH_FLD_4_INVALID_NS_SMALL_L_MASK = 1470; // 8
+const static uint64_t SH_FLD_4_INVALID_NS_SMALL_R = 1471; // 8
+const static uint64_t SH_FLD_4_INVALID_NS_SMALL_R_MASK = 1472; // 8
+const static uint64_t SH_FLD_4_JUMP_BACK_RIGHT = 1473; // 8
+const static uint64_t SH_FLD_4_LEADING_EDGE_FOUND_MASK = 1474; // 8
+const static uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND = 1475; // 8
+const static uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_0_15 = 1476; // 8
+const static uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_0_15_LEN = 1477; // 8
+const static uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_16_23 = 1478; // 8
+const static uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_16_23_LEN = 1479; // 8
+const static uint64_t SH_FLD_4_LEN = 1480; // 84
+const static uint64_t SH_FLD_4_LOOPBACK_DLY12 = 1481; // 8
+const static uint64_t SH_FLD_4_LOOPBACK_FIX_EN = 1482; // 8
+const static uint64_t SH_FLD_4_MATCH_STEP_RIGHT = 1483; // 8
+const static uint64_t SH_FLD_4_MAX_DQS = 1484; // 8
+const static uint64_t SH_FLD_4_MAX_DQS_ITER = 1485; // 8
+const static uint64_t SH_FLD_4_MAX_DQS_LEN = 1486; // 8
+const static uint64_t SH_FLD_4_MEMINTD00 = 1487; // 8
+const static uint64_t SH_FLD_4_MEMINTD00_LEN = 1488; // 8
+const static uint64_t SH_FLD_4_MEMINTD01 = 1489; // 8
+const static uint64_t SH_FLD_4_MEMINTD01_LEN = 1490; // 8
+const static uint64_t SH_FLD_4_MEMINTD02 = 1491; // 8
+const static uint64_t SH_FLD_4_MEMINTD02_LEN = 1492; // 8
+const static uint64_t SH_FLD_4_MEMINTD03 = 1493; // 8
+const static uint64_t SH_FLD_4_MEMINTD03_LEN = 1494; // 8
+const static uint64_t SH_FLD_4_MEMINTD04 = 1495; // 8
+const static uint64_t SH_FLD_4_MEMINTD04_LEN = 1496; // 8
+const static uint64_t SH_FLD_4_MEMINTD05 = 1497; // 8
+const static uint64_t SH_FLD_4_MEMINTD05_LEN = 1498; // 8
+const static uint64_t SH_FLD_4_MEMINTD06 = 1499; // 8
+const static uint64_t SH_FLD_4_MEMINTD06_LEN = 1500; // 8
+const static uint64_t SH_FLD_4_MEMINTD07 = 1501; // 8
+const static uint64_t SH_FLD_4_MEMINTD07_LEN = 1502; // 8
+const static uint64_t SH_FLD_4_MEMINTD08 = 1503; // 8
+const static uint64_t SH_FLD_4_MEMINTD08_LEN = 1504; // 8
+const static uint64_t SH_FLD_4_MEMINTD09 = 1505; // 8
+const static uint64_t SH_FLD_4_MEMINTD09_LEN = 1506; // 8
+const static uint64_t SH_FLD_4_MEMINTD10 = 1507; // 8
+const static uint64_t SH_FLD_4_MEMINTD10_LEN = 1508; // 8
+const static uint64_t SH_FLD_4_MEMINTD11 = 1509; // 8
+const static uint64_t SH_FLD_4_MEMINTD11_LEN = 1510; // 8
+const static uint64_t SH_FLD_4_MEMINTD12 = 1511; // 8
+const static uint64_t SH_FLD_4_MEMINTD12_LEN = 1512; // 8
+const static uint64_t SH_FLD_4_MEMINTD13 = 1513; // 8
+const static uint64_t SH_FLD_4_MEMINTD13_LEN = 1514; // 8
+const static uint64_t SH_FLD_4_MEMINTD14 = 1515; // 8
+const static uint64_t SH_FLD_4_MEMINTD14_LEN = 1516; // 8
+const static uint64_t SH_FLD_4_MEMINTD15 = 1517; // 8
+const static uint64_t SH_FLD_4_MEMINTD15_LEN = 1518; // 8
+const static uint64_t SH_FLD_4_MEMINTD16 = 1519; // 8
+const static uint64_t SH_FLD_4_MEMINTD16_LEN = 1520; // 8
+const static uint64_t SH_FLD_4_MEMINTD17 = 1521; // 8
+const static uint64_t SH_FLD_4_MEMINTD17_LEN = 1522; // 8
+const static uint64_t SH_FLD_4_MEMINTD18 = 1523; // 8
+const static uint64_t SH_FLD_4_MEMINTD18_LEN = 1524; // 8
+const static uint64_t SH_FLD_4_MEMINTD19 = 1525; // 8
+const static uint64_t SH_FLD_4_MEMINTD19_LEN = 1526; // 8
+const static uint64_t SH_FLD_4_MEMINTD20 = 1527; // 8
+const static uint64_t SH_FLD_4_MEMINTD20_LEN = 1528; // 8
+const static uint64_t SH_FLD_4_MEMINTD21 = 1529; // 8
+const static uint64_t SH_FLD_4_MEMINTD21_LEN = 1530; // 8
+const static uint64_t SH_FLD_4_MEMINTD22 = 1531; // 8
+const static uint64_t SH_FLD_4_MEMINTD22_LEN = 1532; // 8
+const static uint64_t SH_FLD_4_MEMINTD23 = 1533; // 8
+const static uint64_t SH_FLD_4_MEMINTD23_LEN = 1534; // 8
+const static uint64_t SH_FLD_4_MIN_EYE = 1535; // 8
+const static uint64_t SH_FLD_4_MIN_EYE_MASK = 1536; // 8
+const static uint64_t SH_FLD_4_MIN_RD_EYE_SIZE = 1537; // 8
+const static uint64_t SH_FLD_4_MIN_RD_EYE_SIZE_LEN = 1538; // 8
+const static uint64_t SH_FLD_4_MRS_CMD_N0 = 1539; // 8
+const static uint64_t SH_FLD_4_MRS_CMD_N1 = 1540; // 8
+const static uint64_t SH_FLD_4_MRS_CMD_N2 = 1541; // 8
+const static uint64_t SH_FLD_4_MRS_CMD_N3 = 1542; // 8
+const static uint64_t SH_FLD_4_N0 = 1543; // 64
+const static uint64_t SH_FLD_4_N0_LEN = 1544; // 64
+const static uint64_t SH_FLD_4_N1 = 1545; // 64
+const static uint64_t SH_FLD_4_N1_LEN = 1546; // 64
+const static uint64_t SH_FLD_4_N2 = 1547; // 64
+const static uint64_t SH_FLD_4_N2_LEN = 1548; // 64
+const static uint64_t SH_FLD_4_N3 = 1549; // 64
+const static uint64_t SH_FLD_4_N3_LEN = 1550; // 64
+const static uint64_t SH_FLD_4_NIB0 = 1551; // 8
+const static uint64_t SH_FLD_4_NIB0TCFLIP_DC = 1552; // 8
+const static uint64_t SH_FLD_4_NIB0_LEN = 1553; // 8
+const static uint64_t SH_FLD_4_NIB1 = 1554; // 8
+const static uint64_t SH_FLD_4_NIB1TCFLIP_DC = 1555; // 8
+const static uint64_t SH_FLD_4_NIB1_LEN = 1556; // 8
+const static uint64_t SH_FLD_4_NIB2 = 1557; // 8
+const static uint64_t SH_FLD_4_NIB2TCFLIP_DC = 1558; // 8
+const static uint64_t SH_FLD_4_NIB2_LEN = 1559; // 8
+const static uint64_t SH_FLD_4_NIB3 = 1560; // 8
+const static uint64_t SH_FLD_4_NIB3TCFLIP_DC = 1561; // 8
+const static uint64_t SH_FLD_4_NIB3_LEN = 1562; // 8
+const static uint64_t SH_FLD_4_NIB_0_2_DQSEL_CAP = 1563; // 16
+const static uint64_t SH_FLD_4_NIB_0_2_DQSEL_CAP_LEN = 1564; // 16
+const static uint64_t SH_FLD_4_NIB_0_2_DQSEL_IND = 1565; // 16
+const static uint64_t SH_FLD_4_NIB_0_2_DQSEL_IND_LEN = 1566; // 16
+const static uint64_t SH_FLD_4_NIB_0_2_DQSEL_RES = 1567; // 16
+const static uint64_t SH_FLD_4_NIB_0_2_DQSEL_RES_LEN = 1568; // 16
+const static uint64_t SH_FLD_4_NIB_1_3_DQSEL_CAP = 1569; // 16
+const static uint64_t SH_FLD_4_NIB_1_3_DQSEL_CAP_LEN = 1570; // 16
+const static uint64_t SH_FLD_4_NIB_1_3_DQSEL_IND = 1571; // 16
+const static uint64_t SH_FLD_4_NIB_1_3_DQSEL_IND_LEN = 1572; // 16
+const static uint64_t SH_FLD_4_NIB_1_3_DQSEL_RES = 1573; // 16
+const static uint64_t SH_FLD_4_NIB_1_3_DQSEL_RES_LEN = 1574; // 16
+const static uint64_t SH_FLD_4_NO_DQS = 1575; // 8
+const static uint64_t SH_FLD_4_NO_DQS_MASK = 1576; // 8
+const static uint64_t SH_FLD_4_NO_EYE_DETECTED = 1577; // 8
+const static uint64_t SH_FLD_4_NO_EYE_DETECTED_MASK = 1578; // 8
+const static uint64_t SH_FLD_4_NO_LOCK = 1579; // 8
+const static uint64_t SH_FLD_4_NO_LOCK_MASK = 1580; // 8
+const static uint64_t SH_FLD_4_OFFSET0 = 1581; // 8
+const static uint64_t SH_FLD_4_OFFSET0_LEN = 1582; // 8
+const static uint64_t SH_FLD_4_OFFSET1 = 1583; // 8
+const static uint64_t SH_FLD_4_OFFSET1_LEN = 1584; // 8
+const static uint64_t SH_FLD_4_OFFSET2 = 1585; // 16
+const static uint64_t SH_FLD_4_OFFSET2_LEN = 1586; // 16
+const static uint64_t SH_FLD_4_OFFSET3 = 1587; // 16
+const static uint64_t SH_FLD_4_OFFSET3_LEN = 1588; // 16
+const static uint64_t SH_FLD_4_OFFSET4 = 1589; // 16
+const static uint64_t SH_FLD_4_OFFSET4_LEN = 1590; // 16
+const static uint64_t SH_FLD_4_OFFSET5 = 1591; // 16
+const static uint64_t SH_FLD_4_OFFSET5_LEN = 1592; // 16
+const static uint64_t SH_FLD_4_OFFSET6 = 1593; // 16
+const static uint64_t SH_FLD_4_OFFSET6_LEN = 1594; // 16
+const static uint64_t SH_FLD_4_OFFSET7 = 1595; // 16
+const static uint64_t SH_FLD_4_OFFSET7_LEN = 1596; // 16
+const static uint64_t SH_FLD_4_OFFSET_ERR = 1597; // 8
+const static uint64_t SH_FLD_4_OFFSET_ERR_MASK = 1598; // 8
+const static uint64_t SH_FLD_4_OPERATE_MODE = 1599; // 8
+const static uint64_t SH_FLD_4_OPERATE_MODE_LEN = 1600; // 8
+const static uint64_t SH_FLD_4_PERCAL_PWR_DIS = 1601; // 8
+const static uint64_t SH_FLD_4_PER_CAL_UPDATE_DISABLE = 1602; // 8
+const static uint64_t SH_FLD_4_PHASE_ALIGN_RESET = 1603; // 16
+const static uint64_t SH_FLD_4_PHASE_CNTL_EN = 1604; // 16
+const static uint64_t SH_FLD_4_PHASE_DEFAULT_EN = 1605; // 16
+const static uint64_t SH_FLD_4_POS_EDGE_ALIGN = 1606; // 16
+const static uint64_t SH_FLD_4_QUAD0 = 1607; // 8
+const static uint64_t SH_FLD_4_QUAD0_CLK16 = 1608; // 64
+const static uint64_t SH_FLD_4_QUAD0_CLK18 = 1609; // 64
+const static uint64_t SH_FLD_4_QUAD0_LEN = 1610; // 8
+const static uint64_t SH_FLD_4_QUAD1 = 1611; // 8
+const static uint64_t SH_FLD_4_QUAD1_CLK16 = 1612; // 64
+const static uint64_t SH_FLD_4_QUAD1_CLK18 = 1613; // 64
+const static uint64_t SH_FLD_4_QUAD1_LEN = 1614; // 8
+const static uint64_t SH_FLD_4_QUAD2 = 1615; // 8
+const static uint64_t SH_FLD_4_QUAD2_CLK16 = 1616; // 64
+const static uint64_t SH_FLD_4_QUAD2_CLK18 = 1617; // 32
+const static uint64_t SH_FLD_4_QUAD2_CLK20 = 1618; // 64
+const static uint64_t SH_FLD_4_QUAD2_CLK22 = 1619; // 64
+const static uint64_t SH_FLD_4_QUAD2_LEN = 1620; // 8
+const static uint64_t SH_FLD_4_QUAD3 = 1621; // 8
+const static uint64_t SH_FLD_4_QUAD3_CLK16 = 1622; // 64
+const static uint64_t SH_FLD_4_QUAD3_CLK18 = 1623; // 32
+const static uint64_t SH_FLD_4_QUAD3_CLK20 = 1624; // 64
+const static uint64_t SH_FLD_4_QUAD3_CLK22 = 1625; // 64
+const static uint64_t SH_FLD_4_QUAD3_LEN = 1626; // 8
+const static uint64_t SH_FLD_4_RD = 1627; // 136
+const static uint64_t SH_FLD_4_RDCLK_SELECT0 = 1628; // 32
+const static uint64_t SH_FLD_4_RDCLK_SELECT0_LEN = 1629; // 32
+const static uint64_t SH_FLD_4_RDCLK_SELECT1 = 1630; // 32
+const static uint64_t SH_FLD_4_RDCLK_SELECT1_LEN = 1631; // 32
+const static uint64_t SH_FLD_4_RDCLK_SELECT2 = 1632; // 32
+const static uint64_t SH_FLD_4_RDCLK_SELECT2_LEN = 1633; // 32
+const static uint64_t SH_FLD_4_RDCLK_SELECT3 = 1634; // 32
+const static uint64_t SH_FLD_4_RDCLK_SELECT3_LEN = 1635; // 32
+const static uint64_t SH_FLD_4_RD_DELAY0 = 1636; // 56
+const static uint64_t SH_FLD_4_RD_DELAY0_LEN = 1637; // 56
+const static uint64_t SH_FLD_4_RD_DELAY1 = 1638; // 56
+const static uint64_t SH_FLD_4_RD_DELAY1_LEN = 1639; // 56
+const static uint64_t SH_FLD_4_RD_DELAY2 = 1640; // 56
+const static uint64_t SH_FLD_4_RD_DELAY2_LEN = 1641; // 56
+const static uint64_t SH_FLD_4_RD_DELAY3 = 1642; // 56
+const static uint64_t SH_FLD_4_RD_DELAY3_LEN = 1643; // 56
+const static uint64_t SH_FLD_4_RD_DELAY4 = 1644; // 56
+const static uint64_t SH_FLD_4_RD_DELAY4_LEN = 1645; // 56
+const static uint64_t SH_FLD_4_RD_DELAY5 = 1646; // 56
+const static uint64_t SH_FLD_4_RD_DELAY5_LEN = 1647; // 56
+const static uint64_t SH_FLD_4_RD_DELAY6 = 1648; // 56
+const static uint64_t SH_FLD_4_RD_DELAY6_LEN = 1649; // 56
+const static uint64_t SH_FLD_4_RD_DELAY7 = 1650; // 56
+const static uint64_t SH_FLD_4_RD_DELAY7_LEN = 1651; // 56
+const static uint64_t SH_FLD_4_RD_LEN = 1652; // 136
+const static uint64_t SH_FLD_4_RD_SIZE0 = 1653; // 88
+const static uint64_t SH_FLD_4_RD_SIZE0_LEN = 1654; // 88
+const static uint64_t SH_FLD_4_RD_SIZE1 = 1655; // 88
+const static uint64_t SH_FLD_4_RD_SIZE1_LEN = 1656; // 88
+const static uint64_t SH_FLD_4_RD_SIZE2 = 1657; // 88
+const static uint64_t SH_FLD_4_RD_SIZE2_LEN = 1658; // 88
+const static uint64_t SH_FLD_4_RD_SIZE3 = 1659; // 88
+const static uint64_t SH_FLD_4_RD_SIZE3_LEN = 1660; // 88
+const static uint64_t SH_FLD_4_RD_SIZE4 = 1661; // 88
+const static uint64_t SH_FLD_4_RD_SIZE4_LEN = 1662; // 88
+const static uint64_t SH_FLD_4_RD_SIZE5 = 1663; // 88
+const static uint64_t SH_FLD_4_RD_SIZE5_LEN = 1664; // 88
+const static uint64_t SH_FLD_4_RD_SIZE6 = 1665; // 88
+const static uint64_t SH_FLD_4_RD_SIZE6_LEN = 1666; // 88
+const static uint64_t SH_FLD_4_RD_SIZE7 = 1667; // 88
+const static uint64_t SH_FLD_4_RD_SIZE7_LEN = 1668; // 88
+const static uint64_t SH_FLD_4_READ_CENTERING_MODE = 1669; // 8
+const static uint64_t SH_FLD_4_READ_CENTERING_MODE_LEN = 1670; // 8
+const static uint64_t SH_FLD_4_REFERENCE1 = 1671; // 8
+const static uint64_t SH_FLD_4_REFERENCE1_LEN = 1672; // 8
+const static uint64_t SH_FLD_4_REFERENCE2 = 1673; // 8
+const static uint64_t SH_FLD_4_REFERENCE2_LEN = 1674; // 8
+const static uint64_t SH_FLD_4_REFERENCE3 = 1675; // 8
+const static uint64_t SH_FLD_4_REFERENCE3_LEN = 1676; // 8
+const static uint64_t SH_FLD_4_REGS_RXDLL_CAL_SKIP = 1677; // 16
+const static uint64_t SH_FLD_4_REGS_RXDLL_CAL_SKIP_LEN = 1678; // 16
+const static uint64_t SH_FLD_4_REGS_RXDLL_COARSE_ADJ_BY2 = 1679; // 16
+const static uint64_t SH_FLD_4_REGS_RXDLL_COARSE_EN = 1680; // 16
+const static uint64_t SH_FLD_4_REGS_RXDLL_COARSE_EN_LEN = 1681; // 16
+const static uint64_t SH_FLD_4_REGS_RXDLL_DAC_COARSE = 1682; // 16
+const static uint64_t SH_FLD_4_REGS_RXDLL_DAC_COARSE_LEN = 1683; // 16
+const static uint64_t SH_FLD_4_REGS_RXDLL_VREG_LOWER = 1684; // 16
+const static uint64_t SH_FLD_4_REGS_RXDLL_VREG_LOWER_LEN = 1685; // 16
+const static uint64_t SH_FLD_4_REGS_RXDLL_VREG_UPPER = 1686; // 16
+const static uint64_t SH_FLD_4_REGS_RXDLL_VREG_UPPER_LEN = 1687; // 16
+const static uint64_t SH_FLD_4_RESERVED = 1688; // 1
+const static uint64_t SH_FLD_4_RESERVED_56_63 = 1689; // 8
+const static uint64_t SH_FLD_4_RESERVED_56_63_LEN = 1690; // 8
+const static uint64_t SH_FLD_4_ROT0 = 1691; // 8
+const static uint64_t SH_FLD_4_ROT0_LEN = 1692; // 8
+const static uint64_t SH_FLD_4_ROT1 = 1693; // 8
+const static uint64_t SH_FLD_4_ROT1_LEN = 1694; // 8
+const static uint64_t SH_FLD_4_ROT_CLK_N0 = 1695; // 64
+const static uint64_t SH_FLD_4_ROT_CLK_N0_LEN = 1696; // 64
+const static uint64_t SH_FLD_4_ROT_CLK_N1 = 1697; // 64
+const static uint64_t SH_FLD_4_ROT_CLK_N1_LEN = 1698; // 64
+const static uint64_t SH_FLD_4_ROT_N0 = 1699; // 64
+const static uint64_t SH_FLD_4_ROT_N0_LEN = 1700; // 64
+const static uint64_t SH_FLD_4_ROT_N1 = 1701; // 64
+const static uint64_t SH_FLD_4_ROT_N1_LEN = 1702; // 64
+const static uint64_t SH_FLD_4_ROT_OVERRIDE = 1703; // 16
+const static uint64_t SH_FLD_4_ROT_OVERRIDE_EN = 1704; // 16
+const static uint64_t SH_FLD_4_ROT_OVERRIDE_LEN = 1705; // 16
+const static uint64_t SH_FLD_4_RXREG_COMPCON_DC = 1706; // 16
+const static uint64_t SH_FLD_4_RXREG_COMPCON_DC_LEN = 1707; // 16
+const static uint64_t SH_FLD_4_RXREG_CON_DC = 1708; // 16
+const static uint64_t SH_FLD_4_RXREG_DAC_PULLUP_DC = 1709; // 16
+const static uint64_t SH_FLD_4_RXREG_DRVCON_DC = 1710; // 16
+const static uint64_t SH_FLD_4_RXREG_DRVCON_DC_LEN = 1711; // 16
+const static uint64_t SH_FLD_4_RXREG_FILTER_LENGTH_DC = 1712; // 16
+const static uint64_t SH_FLD_4_RXREG_FILTER_LENGTH_DC_LEN = 1713; // 16
+const static uint64_t SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC = 1714; // 16
+const static uint64_t SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 1715; // 16
+const static uint64_t SH_FLD_4_RXREG_REF_SEL_DC = 1716; // 16
+const static uint64_t SH_FLD_4_RXREG_REF_SEL_DC_LEN = 1717; // 16
+const static uint64_t SH_FLD_4_S0ACENSLICENDRV_DC = 1718; // 8
+const static uint64_t SH_FLD_4_S0ACENSLICENDRV_DC_LEN = 1719; // 8
+const static uint64_t SH_FLD_4_S0ACENSLICEPDRV_DC = 1720; // 8
+const static uint64_t SH_FLD_4_S0ACENSLICEPDRV_DC_LEN = 1721; // 8
+const static uint64_t SH_FLD_4_S0ACENSLICEPTERM_DC = 1722; // 8
+const static uint64_t SH_FLD_4_S0ACENSLICEPTERM_DC_LEN = 1723; // 8
+const static uint64_t SH_FLD_4_S0INSDLYTAP = 1724; // 8
+const static uint64_t SH_FLD_4_S1ACENSLICENDRV_DC = 1725; // 8
+const static uint64_t SH_FLD_4_S1ACENSLICENDRV_DC_LEN = 1726; // 8
+const static uint64_t SH_FLD_4_S1ACENSLICEPDRV_DC = 1727; // 8
+const static uint64_t SH_FLD_4_S1ACENSLICEPDRV_DC_LEN = 1728; // 8
+const static uint64_t SH_FLD_4_S1ACENSLICEPTERM_DC = 1729; // 8
+const static uint64_t SH_FLD_4_S1ACENSLICEPTERM_DC_LEN = 1730; // 8
+const static uint64_t SH_FLD_4_S1INSDLYTAP = 1731; // 8
+const static uint64_t SH_FLD_4_SEND_ENABLE = 1732; // 1
+const static uint64_t SH_FLD_4_SEND_MODE = 1733; // 1
+const static uint64_t SH_FLD_4_SMALL_STEP_LEFT = 1734; // 8
+const static uint64_t SH_FLD_4_SMALL_STEP_RIGHT = 1735; // 8
+const static uint64_t SH_FLD_4_SPARE_SECTOR_BUFFER_CONTROL = 1736; // 1
+const static uint64_t SH_FLD_4_SYNC = 1737; // 8
+const static uint64_t SH_FLD_4_SYNC_LEN = 1738; // 8
+const static uint64_t SH_FLD_4_SYSCLK_DQSCLK_OFFSET = 1739; // 8
+const static uint64_t SH_FLD_4_SYSCLK_DQSCLK_OFFSET_LEN = 1740; // 8
+const static uint64_t SH_FLD_4_SYSCLK_RDCLK_OFFSET = 1741; // 8
+const static uint64_t SH_FLD_4_SYSCLK_RDCLK_OFFSET_LEN = 1742; // 8
+const static uint64_t SH_FLD_4_TOXDRV_HIBERNATE = 1743; // 8
+const static uint64_t SH_FLD_4_TRAILING_EDGE_FOUND_MASK = 1744; // 8
+const static uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND = 1745; // 8
+const static uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_0_15 = 1746; // 8
+const static uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 1747; // 8
+const static uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_16_23 = 1748; // 8
+const static uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 1749; // 8
+const static uint64_t SH_FLD_4_TRIG_PERIOD = 1750; // 8
+const static uint64_t SH_FLD_4_TSYS = 1751; // 8
+const static uint64_t SH_FLD_4_TSYS_LEN = 1752; // 8
+const static uint64_t SH_FLD_4_TUNEATST_0 = 1753; // 8
+const static uint64_t SH_FLD_4_TUNETDIV_0_2 = 1754; // 8
+const static uint64_t SH_FLD_4_TUNETDIV_0_2_LEN = 1755; // 8
+const static uint64_t SH_FLD_4_VALID_NS_BIG_L = 1756; // 8
+const static uint64_t SH_FLD_4_VALID_NS_BIG_L_MASK = 1757; // 8
+const static uint64_t SH_FLD_4_VALID_NS_BIG_R = 1758; // 8
+const static uint64_t SH_FLD_4_VALID_NS_BIG_R_MASK = 1759; // 8
+const static uint64_t SH_FLD_4_VALID_NS_JUMP_BACK = 1760; // 8
+const static uint64_t SH_FLD_4_VALID_NS_JUMP_BACK_MASK = 1761; // 8
+const static uint64_t SH_FLD_4_WL_ADVANCE_DISABLE = 1762; // 8
+const static uint64_t SH_FLD_4_WL_ERR_CLK16 = 1763; // 16
+const static uint64_t SH_FLD_4_WL_ERR_CLK16_MASK = 1764; // 8
+const static uint64_t SH_FLD_4_WL_ERR_CLK18 = 1765; // 16
+const static uint64_t SH_FLD_4_WL_ERR_CLK18_MASK = 1766; // 8
+const static uint64_t SH_FLD_4_WL_ERR_CLK20 = 1767; // 16
+const static uint64_t SH_FLD_4_WL_ERR_CLK20_MASK = 1768; // 8
+const static uint64_t SH_FLD_4_WL_ERR_CLK22 = 1769; // 16
+const static uint64_t SH_FLD_4_WR = 1770; // 8
+const static uint64_t SH_FLD_4_WRAPSEL = 1771; // 8
+const static uint64_t SH_FLD_4_WR_LEN = 1772; // 8
+const static uint64_t SH_FLD_4_WTRFL_AVE_DIS = 1773; // 8
+const static uint64_t SH_FLD_4_ZERO_DETECTED = 1774; // 8
+const static uint64_t SH_FLD_5 = 1775; // 449
+const static uint64_t SH_FLD_5_LEN = 1776; // 43
+const static uint64_t SH_FLD_5_RESERVED = 1777; // 1
+const static uint64_t SH_FLD_5_SPARE_SECTOR_BUFFER_CONTROL = 1778; // 1
+const static uint64_t SH_FLD_6 = 1779; // 449
+const static uint64_t SH_FLD_6_LEN = 1780; // 43
+const static uint64_t SH_FLD_6_RESERVED = 1781; // 1
+const static uint64_t SH_FLD_6_SPARE_SECTOR_BUFFER_CONTROL = 1782; // 1
+const static uint64_t SH_FLD_6_SPARE_TERM_DIS = 1783; // 1
+const static uint64_t SH_FLD_7 = 1784; // 406
+const static uint64_t SH_FLD_7_RESERVED = 1785; // 1
+const static uint64_t SH_FLD_7_SPARE_SECTOR_BUFFER_CONTROL = 1786; // 1
+const static uint64_t SH_FLD_7_SPARE_TERM_DIS = 1787; // 1
+const static uint64_t SH_FLD_842_FC_SELECT = 1788; // 1
+const static uint64_t SH_FLD_842_FC_SELECT_LEN = 1789; // 1
+const static uint64_t SH_FLD_842_LATENCY_CFG = 1790; // 1
+const static uint64_t SH_FLD_8_11_SPARE = 1791; // 8
+const static uint64_t SH_FLD_8_11_SPARE_LEN = 1792; // 8
+const static uint64_t SH_FLD_8_9 = 1793; // 6
+const static uint64_t SH_FLD_8_9_LEN = 1794; // 6
+const static uint64_t SH_FLD_8_RESERVED = 1795; // 2
+const static uint64_t SH_FLD_8_SPARE_FILTER_PLL_CONTROL = 1796; // 1
+const static uint64_t SH_FLD_8_SPARE_SECTOR_BUFFER_CONTROL = 1797; // 1
+const static uint64_t SH_FLD_9_RESERVED = 1798; // 1
+const static uint64_t SH_FLD_9_SPARE_FILTER_PLL_CONTROL = 1799; // 1
+const static uint64_t SH_FLD_9_SPARE_SECTOR_BUFFER_CONTROL = 1800; // 1
+const static uint64_t SH_FLD_ABIST = 1801; // 43
+const static uint64_t SH_FLD_ABORT = 1802; // 6
+const static uint64_t SH_FLD_ABORTED_CMD = 1803; // 1
+const static uint64_t SH_FLD_ABORT_CHECK_TIMEOUT_SEL = 1804; // 6
+const static uint64_t SH_FLD_ABORT_CHECK_TIMEOUT_SEL_LEN = 1805; // 6
+const static uint64_t SH_FLD_ABORT_ON_ERROR = 1806; // 8
+const static uint64_t SH_FLD_ABORT_ON_ERR_EN = 1807; // 8
+const static uint64_t SH_FLD_ACCR_OVERRIDE_EN = 1808; // 12
+const static uint64_t SH_FLD_ACCUM = 1809; // 6
+const static uint64_t SH_FLD_ACCUM_LEN = 1810; // 6
+const static uint64_t SH_FLD_ACM_EN = 1811; // 1
+const static uint64_t SH_FLD_ACT = 1812; // 53
+const static uint64_t SH_FLD_ACTCYCLECNT = 1813; // 3
+const static uint64_t SH_FLD_ACTCYCLECNT_LEN = 1814; // 3
+const static uint64_t SH_FLD_ACTION0 = 1815; // 48
+const static uint64_t SH_FLD_ACTION0_LEN = 1816; // 48
+const static uint64_t SH_FLD_ACTION1 = 1817; // 48
+const static uint64_t SH_FLD_ACTION1_LEN = 1818; // 48
+const static uint64_t SH_FLD_ACTION_0 = 1819; // 4
+const static uint64_t SH_FLD_ACTION_0_LEN = 1820; // 4
+const static uint64_t SH_FLD_ACTION_1 = 1821; // 4
+const static uint64_t SH_FLD_ACTION_1_LEN = 1822; // 4
+const static uint64_t SH_FLD_ACTIVATE_COUNT = 1823; // 8
+const static uint64_t SH_FLD_ACTIVATE_COUNT_LEN = 1824; // 8
+const static uint64_t SH_FLD_ACTIVE_CHANNEL_CNT = 1825; // 1
+const static uint64_t SH_FLD_ACTIVE_CHANNEL_CNT_LEN = 1826; // 1
+const static uint64_t SH_FLD_ACTIVITY = 1827; // 129
+const static uint64_t SH_FLD_ACTIVITY_LEN = 1828; // 129
+const static uint64_t SH_FLD_ACTUAL_CLK_SB_PULSE_MODE = 1829; // 24
+const static uint64_t SH_FLD_ACTUAL_CLK_SB_PULSE_MODE_EN = 1830; // 24
+const static uint64_t SH_FLD_ACTUAL_CLK_SB_PULSE_MODE_LEN = 1831; // 24
+const static uint64_t SH_FLD_ACTUAL_CLK_SB_SPARE = 1832; // 24
+const static uint64_t SH_FLD_ACTUAL_CLK_SB_STRENGTH = 1833; // 24
+const static uint64_t SH_FLD_ACTUAL_CLK_SB_STRENGTH_LEN = 1834; // 24
+const static uint64_t SH_FLD_ACTUAL_CLK_SW_RESCLK = 1835; // 24
+const static uint64_t SH_FLD_ACTUAL_CLK_SW_RESCLK_LEN = 1836; // 24
+const static uint64_t SH_FLD_ACTUAL_CLK_SW_SPARE = 1837; // 24
+const static uint64_t SH_FLD_ACTUAL_ERROR = 1838; // 3
+const static uint64_t SH_FLD_ACTUAL_ERROR_LEN = 1839; // 3
+const static uint64_t SH_FLD_ACT_CHECK_TIMEOUT_SEL = 1840; // 4
+const static uint64_t SH_FLD_ACT_CHECK_TIMEOUT_SEL_LEN = 1841; // 4
+const static uint64_t SH_FLD_ACT_DIS = 1842; // 43
+const static uint64_t SH_FLD_ACT_STOP_LEVEL = 1843; // 30
+const static uint64_t SH_FLD_ACT_STOP_LEVEL_FSP = 1844; // 30
+const static uint64_t SH_FLD_ACT_STOP_LEVEL_FSP_LEN = 1845; // 30
+const static uint64_t SH_FLD_ACT_STOP_LEVEL_HYP = 1846; // 30
+const static uint64_t SH_FLD_ACT_STOP_LEVEL_HYP_LEN = 1847; // 30
+const static uint64_t SH_FLD_ACT_STOP_LEVEL_LEN = 1848; // 30
+const static uint64_t SH_FLD_ACT_STOP_LEVEL_OCC = 1849; // 30
+const static uint64_t SH_FLD_ACT_STOP_LEVEL_OCC_LEN = 1850; // 30
+const static uint64_t SH_FLD_ACT_STOP_LEVEL_OTR = 1851; // 30
+const static uint64_t SH_FLD_ACT_STOP_LEVEL_OTR_LEN = 1852; // 30
+const static uint64_t SH_FLD_ADAPTEST_1BIT_ENABLE = 1853; // 1
+const static uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MAX = 1854; // 1
+const static uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MAX_LEN = 1855; // 1
+const static uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MIN = 1856; // 1
+const static uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MIN_LEN = 1857; // 1
+const static uint64_t SH_FLD_ADAPTEST_CRN_RNG0_MATCH_TH = 1858; // 1
+const static uint64_t SH_FLD_ADAPTEST_CRN_RNG0_MATCH_TH_LEN = 1859; // 1
+const static uint64_t SH_FLD_ADAPTEST_CRN_RNG1_MATCH_TH = 1860; // 1
+const static uint64_t SH_FLD_ADAPTEST_CRN_RNG1_MATCH_TH_LEN = 1861; // 1
+const static uint64_t SH_FLD_ADAPTEST_ENABLE = 1862; // 1
+const static uint64_t SH_FLD_ADAPTEST_RRN_RNG0_MATCH_TH = 1863; // 1
+const static uint64_t SH_FLD_ADAPTEST_RRN_RNG0_MATCH_TH_LEN = 1864; // 1
+const static uint64_t SH_FLD_ADAPTEST_RRN_RNG1_MATCH_TH = 1865; // 1
+const static uint64_t SH_FLD_ADAPTEST_RRN_RNG1_MATCH_TH_LEN = 1866; // 1
+const static uint64_t SH_FLD_ADAPTEST_SAMPLE_SIZE = 1867; // 1
+const static uint64_t SH_FLD_ADAPTEST_SAMPLE_SIZE_LEN = 1868; // 1
+const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0 = 1869; // 1
+const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0_LEN = 1870; // 1
+const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1 = 1871; // 1
+const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1_LEN = 1872; // 1
+const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0 = 1873; // 1
+const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0_LEN = 1874; // 1
+const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1 = 1875; // 1
+const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1_LEN = 1876; // 1
+const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_TH = 1877; // 1
+const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_TH_LEN = 1878; // 1
+const static uint64_t SH_FLD_ADAPTEST_WINDOW_SIZE = 1879; // 1
+const static uint64_t SH_FLD_ADAPTEST_WINDOW_SIZE_LEN = 1880; // 1
+const static uint64_t SH_FLD_ADCFSM_ONGOING = 1881; // 1
+const static uint64_t SH_FLD_ADDR = 1882; // 38
+const static uint64_t SH_FLD_ADDR0 = 1883; // 8
+const static uint64_t SH_FLD_ADDR0_LEN = 1884; // 8
+const static uint64_t SH_FLD_ADDR1 = 1885; // 8
+const static uint64_t SH_FLD_ADDR1_LEN = 1886; // 8
+const static uint64_t SH_FLD_ADDR2 = 1887; // 16
+const static uint64_t SH_FLD_ADDR2_LEN = 1888; // 16
+const static uint64_t SH_FLD_ADDR3 = 1889; // 16
+const static uint64_t SH_FLD_ADDR3_LEN = 1890; // 16
+const static uint64_t SH_FLD_ADDR4 = 1891; // 16
+const static uint64_t SH_FLD_ADDR4_LEN = 1892; // 16
+const static uint64_t SH_FLD_ADDRESS = 1893; // 221
+const static uint64_t SH_FLD_ADDRESS_8_63 = 1894; // 1
+const static uint64_t SH_FLD_ADDRESS_8_63_LEN = 1895; // 1
+const static uint64_t SH_FLD_ADDRESS_LEN = 1896; // 220
+const static uint64_t SH_FLD_ADDRESS_PARITY = 1897; // 43
+const static uint64_t SH_FLD_ADDRESS_PIPELINE_MASTERWAIT_COUNT = 1898; // 2
+const static uint64_t SH_FLD_ADDRESS_PIPELINE_MASTERWAIT_COUNT_LEN = 1899; // 2
+const static uint64_t SH_FLD_ADDR_21_37 = 1900; // 1
+const static uint64_t SH_FLD_ADDR_21_37_LEN = 1901; // 1
+const static uint64_t SH_FLD_ADDR_26_38 = 1902; // 1
+const static uint64_t SH_FLD_ADDR_26_38_LEN = 1903; // 1
+const static uint64_t SH_FLD_ADDR_8_37 = 1904; // 1
+const static uint64_t SH_FLD_ADDR_8_37_LEN = 1905; // 1
+const static uint64_t SH_FLD_ADDR_8_38 = 1906; // 1
+const static uint64_t SH_FLD_ADDR_8_38_LEN = 1907; // 1
+const static uint64_t SH_FLD_ADDR_8_48 = 1908; // 1
+const static uint64_t SH_FLD_ADDR_8_48_LEN = 1909; // 1
+const static uint64_t SH_FLD_ADDR_8_49 = 1910; // 2
+const static uint64_t SH_FLD_ADDR_8_49_LEN = 1911; // 2
+const static uint64_t SH_FLD_ADDR_BAR = 1912; // 1
+const static uint64_t SH_FLD_ADDR_BAR_MODE = 1913; // 2
+const static uint64_t SH_FLD_ADDR_BUFFER = 1914; // 43
+const static uint64_t SH_FLD_ADDR_ERROR = 1915; // 2
+const static uint64_t SH_FLD_ADDR_ERROR_PULSE = 1916; // 2
+const static uint64_t SH_FLD_ADDR_INVALID_FACES = 1917; // 1
+const static uint64_t SH_FLD_ADDR_INVALID_PIB = 1918; // 1
+const static uint64_t SH_FLD_ADDR_LEN = 1919; // 38
+const static uint64_t SH_FLD_ADDR_MIRROR_A11_A13 = 1920; // 8
+const static uint64_t SH_FLD_ADDR_MIRROR_A3_A4 = 1921; // 8
+const static uint64_t SH_FLD_ADDR_MIRROR_A5_A6 = 1922; // 8
+const static uint64_t SH_FLD_ADDR_MIRROR_A7_A8 = 1923; // 8
+const static uint64_t SH_FLD_ADDR_MIRROR_BA0_BA1 = 1924; // 8
+const static uint64_t SH_FLD_ADDR_MIRROR_BG0_BG1 = 1925; // 8
+const static uint64_t SH_FLD_ADDR_MIRROR_RP0_PRI = 1926; // 8
+const static uint64_t SH_FLD_ADDR_MIRROR_RP0_QUA = 1927; // 8
+const static uint64_t SH_FLD_ADDR_MIRROR_RP0_SEC = 1928; // 8
+const static uint64_t SH_FLD_ADDR_MIRROR_RP0_TER = 1929; // 8
+const static uint64_t SH_FLD_ADDR_MIRROR_RP1_PRI = 1930; // 8
+const static uint64_t SH_FLD_ADDR_MIRROR_RP1_QUA = 1931; // 8
+const static uint64_t SH_FLD_ADDR_MIRROR_RP1_SEC = 1932; // 8
+const static uint64_t SH_FLD_ADDR_MIRROR_RP1_TER = 1933; // 8
+const static uint64_t SH_FLD_ADDR_MIRROR_RP2_PRI = 1934; // 8
+const static uint64_t SH_FLD_ADDR_MIRROR_RP2_QUA = 1935; // 8
+const static uint64_t SH_FLD_ADDR_MIRROR_RP2_SEC = 1936; // 8
+const static uint64_t SH_FLD_ADDR_MIRROR_RP2_TER = 1937; // 8
+const static uint64_t SH_FLD_ADDR_MIRROR_RP3_PRI = 1938; // 8
+const static uint64_t SH_FLD_ADDR_MIRROR_RP3_QUA = 1939; // 8
+const static uint64_t SH_FLD_ADDR_MIRROR_RP3_SEC = 1940; // 8
+const static uint64_t SH_FLD_ADDR_MIRROR_RP3_TER = 1941; // 8
+const static uint64_t SH_FLD_ADDR_NVLD = 1942; // 1
+const static uint64_t SH_FLD_ADDR_PARITY_ERR = 1943; // 4
+const static uint64_t SH_FLD_ADDR_RESET_INTR_FACES = 1944; // 1
+const static uint64_t SH_FLD_ADDR_RESET_INTR_FACES_LEN = 1945; // 1
+const static uint64_t SH_FLD_ADDR_RESET_INTR_PIB = 1946; // 1
+const static uint64_t SH_FLD_ADDR_RESET_INTR_PIB_LEN = 1947; // 1
+const static uint64_t SH_FLD_ADDR_TAG = 1948; // 1
+const static uint64_t SH_FLD_ADDR_TAG_LEN = 1949; // 1
+const static uint64_t SH_FLD_ADR = 1950; // 4
+const static uint64_t SH_FLD_ADR0_ANALOG_WRAPON = 1951; // 8
+const static uint64_t SH_FLD_ADR0_ATEST1CTL0 = 1952; // 8
+const static uint64_t SH_FLD_ADR0_ATEST1CTL1 = 1953; // 8
+const static uint64_t SH_FLD_ADR0_ATEST1CTL2 = 1954; // 8
+const static uint64_t SH_FLD_ADR0_ATEST1CTL3 = 1955; // 8
+const static uint64_t SH_FLD_ADR0_BB_LOCK = 1956; // 8
+const static uint64_t SH_FLD_ADR0_CE0DLTVCC = 1957; // 8
+const static uint64_t SH_FLD_ADR0_CE0DLTVCC_LEN = 1958; // 8
+const static uint64_t SH_FLD_ADR0_CONTINUOUS_UPDATE = 1959; // 8
+const static uint64_t SH_FLD_ADR0_EN = 1960; // 8
+const static uint64_t SH_FLD_ADR0_ENABLE = 1961; // 8
+const static uint64_t SH_FLD_ADR0_FLUSH = 1962; // 8
+const static uint64_t SH_FLD_ADR0_HS_PROBE_A_SEL = 1963; // 8
+const static uint64_t SH_FLD_ADR0_HS_PROBE_A_SEL_LEN = 1964; // 8
+const static uint64_t SH_FLD_ADR0_HS_PROBE_B_SEL = 1965; // 8
+const static uint64_t SH_FLD_ADR0_HS_PROBE_B_SEL_LEN = 1966; // 8
+const static uint64_t SH_FLD_ADR0_INIT_RXDLL_CAL_RESET = 1967; // 8
+const static uint64_t SH_FLD_ADR0_INIT_RXDLL_CAL_UPDATE = 1968; // 8
+const static uint64_t SH_FLD_ADR0_INTERP_SIG_SLEW = 1969; // 8
+const static uint64_t SH_FLD_ADR0_INTERP_SIG_SLEW_LEN = 1970; // 8
+const static uint64_t SH_FLD_ADR0_OVERRIDE = 1971; // 8
+const static uint64_t SH_FLD_ADR0_OVERRIDE_EN = 1972; // 8
+const static uint64_t SH_FLD_ADR0_OVERRIDE_LEN = 1973; // 8
+const static uint64_t SH_FLD_ADR0_PHASE_ALIGN_RESET = 1974; // 8
+const static uint64_t SH_FLD_ADR0_PHASE_DEFAULT_EN = 1975; // 8
+const static uint64_t SH_FLD_ADR0_PHASE_EN = 1976; // 8
+const static uint64_t SH_FLD_ADR0_POS_EDGE_ALIGN = 1977; // 8
+const static uint64_t SH_FLD_ADR0_RANGE_0 = 1978; // 8
+const static uint64_t SH_FLD_ADR0_RANGE_0_LEN = 1979; // 8
+const static uint64_t SH_FLD_ADR0_REGS_RXDLL_CAL_SKIP = 1980; // 8
+const static uint64_t SH_FLD_ADR0_REGS_RXDLL_CAL_SKIP_LEN = 1981; // 8
+const static uint64_t SH_FLD_ADR0_REGS_RXDLL_COARSE_ADJ_BY2 = 1982; // 8
+const static uint64_t SH_FLD_ADR0_REGS_RXDLL_DAC = 1983; // 8
+const static uint64_t SH_FLD_ADR0_REGS_RXDLL_DAC_LEN = 1984; // 8
+const static uint64_t SH_FLD_ADR0_REGS_RXDLL_EN = 1985; // 8
+const static uint64_t SH_FLD_ADR0_REGS_RXDLL_EN_LEN = 1986; // 8
+const static uint64_t SH_FLD_ADR0_REGS_RXDLL_VREG = 1987; // 16
+const static uint64_t SH_FLD_ADR0_REGS_RXDLL_VREG_LEN = 1988; // 16
+const static uint64_t SH_FLD_ADR0_RESERVED_60_63 = 1989; // 8
+const static uint64_t SH_FLD_ADR0_RESERVED_60_63_LEN = 1990; // 8
+const static uint64_t SH_FLD_ADR0_ROT = 1991; // 8
+const static uint64_t SH_FLD_ADR0_ROT_LEN = 1992; // 8
+const static uint64_t SH_FLD_ADR0_ROT_OVERRIDE = 1993; // 8
+const static uint64_t SH_FLD_ADR0_ROT_OVERRIDE_EN = 1994; // 8
+const static uint64_t SH_FLD_ADR0_ROT_OVERRIDE_LEN = 1995; // 8
+const static uint64_t SH_FLD_ADR0_RXREG_COMPCON_DC = 1996; // 8
+const static uint64_t SH_FLD_ADR0_RXREG_COMPCON_DC_LEN = 1997; // 8
+const static uint64_t SH_FLD_ADR0_RXREG_CON_DC = 1998; // 8
+const static uint64_t SH_FLD_ADR0_RXREG_DAC_PULLUP_DC = 1999; // 8
+const static uint64_t SH_FLD_ADR0_RXREG_DRVCON_DC = 2000; // 8
+const static uint64_t SH_FLD_ADR0_RXREG_DRVCON_DC_LEN = 2001; // 8
+const static uint64_t SH_FLD_ADR0_RXREG_FILTER_LENGTH_DC = 2002; // 8
+const static uint64_t SH_FLD_ADR0_RXREG_FILTER_LENGTH_DC_LEN = 2003; // 8
+const static uint64_t SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC = 2004; // 8
+const static uint64_t SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 2005; // 8
+const static uint64_t SH_FLD_ADR0_RXREG_REF_SEL_DC = 2006; // 8
+const static uint64_t SH_FLD_ADR0_RXREG_REF_SEL_DC_LEN = 2007; // 8
+const static uint64_t SH_FLD_ADR0_SLEW_DONE_STATUS = 2008; // 8
+const static uint64_t SH_FLD_ADR0_SLEW_DONE_STATUS_LEN = 2009; // 8
+const static uint64_t SH_FLD_ADR0_START = 2010; // 8
+const static uint64_t SH_FLD_ADR0_TARGET_PR_OFFSET = 2011; // 8
+const static uint64_t SH_FLD_ADR0_TARGET_PR_OFFSET_LEN = 2012; // 8
+const static uint64_t SH_FLD_ADR0_TSYS = 2013; // 8
+const static uint64_t SH_FLD_ADR0_TSYS_LEN = 2014; // 8
+const static uint64_t SH_FLD_ADR0_TUNEATST_0 = 2015; // 8
+const static uint64_t SH_FLD_ADR0_TUNEATST_0_LEN = 2016; // 8
+const static uint64_t SH_FLD_ADR0_TUNETDIV_0_2 = 2017; // 8
+const static uint64_t SH_FLD_ADR0_TUNETDIV_0_2_LEN = 2018; // 8
+const static uint64_t SH_FLD_ADR0_VALUE = 2019; // 16
+const static uint64_t SH_FLD_ADR0_VALUE_LEN = 2020; // 16
+const static uint64_t SH_FLD_ADR0_VCCTUNE_0 = 2021; // 8
+const static uint64_t SH_FLD_ADR0_VCCTUNE_0_LEN = 2022; // 8
+const static uint64_t SH_FLD_ADR1_ANALOG_WRAPON = 2023; // 8
+const static uint64_t SH_FLD_ADR1_ATEST1CTL0 = 2024; // 8
+const static uint64_t SH_FLD_ADR1_ATEST1CTL1 = 2025; // 8
+const static uint64_t SH_FLD_ADR1_ATEST1CTL2 = 2026; // 8
+const static uint64_t SH_FLD_ADR1_ATEST1CTL3 = 2027; // 8
+const static uint64_t SH_FLD_ADR1_BB_LOCK = 2028; // 8
+const static uint64_t SH_FLD_ADR1_CE0DLTVCC = 2029; // 8
+const static uint64_t SH_FLD_ADR1_CE0DLTVCC_LEN = 2030; // 8
+const static uint64_t SH_FLD_ADR1_CONTINUOUS_UPDATE = 2031; // 8
+const static uint64_t SH_FLD_ADR1_EN = 2032; // 8
+const static uint64_t SH_FLD_ADR1_ENABLE = 2033; // 8
+const static uint64_t SH_FLD_ADR1_FLUSH = 2034; // 8
+const static uint64_t SH_FLD_ADR1_HS_PROBE_A_SEL = 2035; // 8
+const static uint64_t SH_FLD_ADR1_HS_PROBE_A_SEL_LEN = 2036; // 8
+const static uint64_t SH_FLD_ADR1_HS_PROBE_B_SEL = 2037; // 8
+const static uint64_t SH_FLD_ADR1_HS_PROBE_B_SEL_LEN = 2038; // 8
+const static uint64_t SH_FLD_ADR1_INIT_RXDLL_CAL_RESET = 2039; // 8
+const static uint64_t SH_FLD_ADR1_INIT_RXDLL_CAL_UPDATE = 2040; // 8
+const static uint64_t SH_FLD_ADR1_INTERP_SIG_SLEW = 2041; // 8
+const static uint64_t SH_FLD_ADR1_INTERP_SIG_SLEW_LEN = 2042; // 8
+const static uint64_t SH_FLD_ADR1_OVERRIDE = 2043; // 8
+const static uint64_t SH_FLD_ADR1_OVERRIDE_EN = 2044; // 8
+const static uint64_t SH_FLD_ADR1_OVERRIDE_LEN = 2045; // 8
+const static uint64_t SH_FLD_ADR1_PHASE_ALIGN_RESET = 2046; // 8
+const static uint64_t SH_FLD_ADR1_PHASE_DEFAULT_EN = 2047; // 8
+const static uint64_t SH_FLD_ADR1_PHASE_EN = 2048; // 8
+const static uint64_t SH_FLD_ADR1_POS_EDGE_ALIGN = 2049; // 8
+const static uint64_t SH_FLD_ADR1_RANGE_0 = 2050; // 8
+const static uint64_t SH_FLD_ADR1_RANGE_0_LEN = 2051; // 8
+const static uint64_t SH_FLD_ADR1_REGS_RXDLL_CAL_SKIP = 2052; // 8
+const static uint64_t SH_FLD_ADR1_REGS_RXDLL_CAL_SKIP_LEN = 2053; // 8
+const static uint64_t SH_FLD_ADR1_REGS_RXDLL_COARSE_ADJ_BY2 = 2054; // 8
+const static uint64_t SH_FLD_ADR1_REGS_RXDLL_DAC = 2055; // 8
+const static uint64_t SH_FLD_ADR1_REGS_RXDLL_DAC_LEN = 2056; // 8
+const static uint64_t SH_FLD_ADR1_REGS_RXDLL_EN = 2057; // 8
+const static uint64_t SH_FLD_ADR1_REGS_RXDLL_EN_LEN = 2058; // 8
+const static uint64_t SH_FLD_ADR1_REGS_RXDLL_VREG = 2059; // 16
+const static uint64_t SH_FLD_ADR1_REGS_RXDLL_VREG_LEN = 2060; // 16
+const static uint64_t SH_FLD_ADR1_RESERVED_60_63 = 2061; // 8
+const static uint64_t SH_FLD_ADR1_RESERVED_60_63_LEN = 2062; // 8
+const static uint64_t SH_FLD_ADR1_ROT = 2063; // 8
+const static uint64_t SH_FLD_ADR1_ROT_LEN = 2064; // 8
+const static uint64_t SH_FLD_ADR1_ROT_OVERRIDE = 2065; // 8
+const static uint64_t SH_FLD_ADR1_ROT_OVERRIDE_EN = 2066; // 8
+const static uint64_t SH_FLD_ADR1_ROT_OVERRIDE_LEN = 2067; // 8
+const static uint64_t SH_FLD_ADR1_RXREG_COMPCON_DC = 2068; // 8
+const static uint64_t SH_FLD_ADR1_RXREG_COMPCON_DC_LEN = 2069; // 8
+const static uint64_t SH_FLD_ADR1_RXREG_CON_DC = 2070; // 8
+const static uint64_t SH_FLD_ADR1_RXREG_DAC_PULLUP_DC = 2071; // 8
+const static uint64_t SH_FLD_ADR1_RXREG_DRVCON_DC = 2072; // 8
+const static uint64_t SH_FLD_ADR1_RXREG_DRVCON_DC_LEN = 2073; // 8
+const static uint64_t SH_FLD_ADR1_RXREG_FILTER_LENGTH_DC = 2074; // 8
+const static uint64_t SH_FLD_ADR1_RXREG_FILTER_LENGTH_DC_LEN = 2075; // 8
+const static uint64_t SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC = 2076; // 8
+const static uint64_t SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 2077; // 8
+const static uint64_t SH_FLD_ADR1_RXREG_REF_SEL_DC = 2078; // 8
+const static uint64_t SH_FLD_ADR1_RXREG_REF_SEL_DC_LEN = 2079; // 8
+const static uint64_t SH_FLD_ADR1_SLEW_DONE_STATUS = 2080; // 8
+const static uint64_t SH_FLD_ADR1_SLEW_DONE_STATUS_LEN = 2081; // 8
+const static uint64_t SH_FLD_ADR1_START = 2082; // 8
+const static uint64_t SH_FLD_ADR1_TARGET_PR_OFFSET = 2083; // 8
+const static uint64_t SH_FLD_ADR1_TARGET_PR_OFFSET_LEN = 2084; // 8
+const static uint64_t SH_FLD_ADR1_TSYS = 2085; // 8
+const static uint64_t SH_FLD_ADR1_TSYS_LEN = 2086; // 8
+const static uint64_t SH_FLD_ADR1_TUNEATST_0 = 2087; // 8
+const static uint64_t SH_FLD_ADR1_TUNEATST_0_LEN = 2088; // 8
+const static uint64_t SH_FLD_ADR1_TUNETDIV_0_2 = 2089; // 8
+const static uint64_t SH_FLD_ADR1_TUNETDIV_0_2_LEN = 2090; // 8
+const static uint64_t SH_FLD_ADR1_VALUE = 2091; // 16
+const static uint64_t SH_FLD_ADR1_VALUE_LEN = 2092; // 16
+const static uint64_t SH_FLD_ADR1_VCCTUNE_0 = 2093; // 8
+const static uint64_t SH_FLD_ADR1_VCCTUNE_0_LEN = 2094; // 8
+const static uint64_t SH_FLD_ADR_LEN = 2095; // 4
+const static uint64_t SH_FLD_ADR_RX_PD = 2096; // 8
+const static uint64_t SH_FLD_ADS_HANG = 2097; // 1
+const static uint64_t SH_FLD_ADU_MALF_ALERT = 2098; // 1
+const static uint64_t SH_FLD_ADVANCE_RD_VALID = 2099; // 8
+const static uint64_t SH_FLD_AESSHA_LATENCY_CFG = 2100; // 1
+const static uint64_t SH_FLD_AES_LATENCY_CFG = 2101; // 1
+const static uint64_t SH_FLD_AIB_FENCE = 2102; // 9
+const static uint64_t SH_FLD_AIB_FENCE_MASK = 2103; // 9
+const static uint64_t SH_FLD_AIB_PE = 2104; // 9
+const static uint64_t SH_FLD_AIB_PE_MASK = 2105; // 9
+const static uint64_t SH_FLD_ALIGN_ON_EVEN_CYCLES = 2106; // 8
+const static uint64_t SH_FLD_ALINK_NOTPHB_MODE = 2107; // 2
+const static uint64_t SH_FLD_ALLOW_CRYPTO = 2108; // 1
+const static uint64_t SH_FLD_ALLOW_RD_FIFO_AUTO_RESET = 2109; // 8
+const static uint64_t SH_FLD_ALLOW_REG_WAKEUP_C0 = 2110; // 12
+const static uint64_t SH_FLD_ALLOW_REG_WAKEUP_C1 = 2111; // 12
+const static uint64_t SH_FLD_ALTD_DATA_ITAG = 2112; // 1
+const static uint64_t SH_FLD_ALTD_DATA_TX = 2113; // 1
+const static uint64_t SH_FLD_ALTD_DATA_TX_LEN = 2114; // 1
+const static uint64_t SH_FLD_ALTD_DATA_TX_OVERWRITE = 2115; // 1
+const static uint64_t SH_FLD_ALT_SEGSZ_DIS = 2116; // 1
+const static uint64_t SH_FLD_ALU_FLIP_ENDIAN_BIG = 2117; // 3
+const static uint64_t SH_FLD_ALU_FLIP_ENDIAN_LITTLE = 2118; // 3
+const static uint64_t SH_FLD_ALU_SAFE_LATENCY = 2119; // 3
+const static uint64_t SH_FLD_ALWAYS_RTY = 2120; // 8
+const static uint64_t SH_FLD_AMAX_HIGH = 2121; // 6
+const static uint64_t SH_FLD_AMAX_HIGH_LEN = 2122; // 6
+const static uint64_t SH_FLD_AMAX_LOW = 2123; // 6
+const static uint64_t SH_FLD_AMAX_LOW_LEN = 2124; // 6
+const static uint64_t SH_FLD_AMF_MAX_Q_DEPTH = 2125; // 1
+const static uint64_t SH_FLD_AMF_MAX_Q_DEPTH_LEN = 2126; // 1
+const static uint64_t SH_FLD_AMIN_CFG = 2127; // 6
+const static uint64_t SH_FLD_AMIN_CFG_LEN = 2128; // 6
+const static uint64_t SH_FLD_AMIN_TIMEOUT = 2129; // 6
+const static uint64_t SH_FLD_AMIN_TIMEOUT_LEN = 2130; // 6
+const static uint64_t SH_FLD_AMO_DRAM_SIZE_128B = 2131; // 8
+const static uint64_t SH_FLD_AMO_LIMIT = 2132; // 8
+const static uint64_t SH_FLD_AMO_LIMIT_LEN = 2133; // 8
+const static uint64_t SH_FLD_AMP0_FILTER_MASK = 2134; // 6
+const static uint64_t SH_FLD_AMP0_FILTER_MASK_LEN = 2135; // 6
+const static uint64_t SH_FLD_AMP1_FILTER_MASK = 2136; // 6
+const static uint64_t SH_FLD_AMP1_FILTER_MASK_LEN = 2137; // 6
+const static uint64_t SH_FLD_AMP_CFG = 2138; // 6
+const static uint64_t SH_FLD_AMP_CFG_LEN = 2139; // 6
+const static uint64_t SH_FLD_AMP_GAIN_CNT_MAX = 2140; // 6
+const static uint64_t SH_FLD_AMP_GAIN_CNT_MAX_LEN = 2141; // 6
+const static uint64_t SH_FLD_AMP_INIT_CFG = 2142; // 6
+const static uint64_t SH_FLD_AMP_INIT_CFG_LEN = 2143; // 6
+const static uint64_t SH_FLD_AMP_INIT_TIMEOUT = 2144; // 6
+const static uint64_t SH_FLD_AMP_INIT_TIMEOUT_LEN = 2145; // 6
+const static uint64_t SH_FLD_AMP_RECAL_CFG = 2146; // 6
+const static uint64_t SH_FLD_AMP_RECAL_CFG_LEN = 2147; // 6
+const static uint64_t SH_FLD_AMP_RECAL_TIMEOUT = 2148; // 6
+const static uint64_t SH_FLD_AMP_RECAL_TIMEOUT_LEN = 2149; // 6
+const static uint64_t SH_FLD_AMP_START_VAL = 2150; // 6
+const static uint64_t SH_FLD_AMP_START_VAL_LEN = 2151; // 6
+const static uint64_t SH_FLD_AMP_TIMEOUT = 2152; // 6
+const static uint64_t SH_FLD_AMP_TIMEOUT_LEN = 2153; // 6
+const static uint64_t SH_FLD_AMP_VAL = 2154; // 120
+const static uint64_t SH_FLD_AMP_VAL_LEN = 2155; // 120
+const static uint64_t SH_FLD_ANALOGTUNE = 2156; // 20
+const static uint64_t SH_FLD_ANALOGTUNE_LEN = 2157; // 20
+const static uint64_t SH_FLD_ANALOG_INPUT_STAB1 = 2158; // 8
+const static uint64_t SH_FLD_ANALOG_INPUT_STAB2 = 2159; // 8
+const static uint64_t SH_FLD_ANALOG_OUTPUT_STAB = 2160; // 8
+const static uint64_t SH_FLD_ANY_ERROR = 2161; // 1
+const static uint64_t SH_FLD_ANY_REQ_ACTIVE = 2162; // 12
+const static uint64_t SH_FLD_AP = 2163; // 144
+const static uint64_t SH_FLD_AP110_AP010_DELTA_MAX = 2164; // 6
+const static uint64_t SH_FLD_AP110_AP010_DELTA_MAX_LEN = 2165; // 6
+const static uint64_t SH_FLD_APB = 2166; // 8
+const static uint64_t SH_FLD_APB_MASK = 2167; // 8
+const static uint64_t SH_FLD_APCARY = 2168; // 4
+const static uint64_t SH_FLD_APCARY_ADDRESS = 2169; // 2
+const static uint64_t SH_FLD_APCARY_ADDRESS_LEN = 2170; // 2
+const static uint64_t SH_FLD_APCARY_LEN = 2171; // 4
+const static uint64_t SH_FLD_APCCTL_ADR_BAR_MODE = 2172; // 2
+const static uint64_t SH_FLD_APCCTL_CFG_BKILL_INC = 2173; // 2
+const static uint64_t SH_FLD_APCCTL_DISABLE_G = 2174; // 2
+const static uint64_t SH_FLD_APCCTL_DISABLE_LN = 2175; // 2
+const static uint64_t SH_FLD_APCCTL_DISABLE_NN_RN = 2176; // 2
+const static uint64_t SH_FLD_APCCTL_DISABLE_PSL_CMDQUEUE = 2177; // 2
+const static uint64_t SH_FLD_APCCTL_DISABLE_VG_NOT_SYS = 2178; // 2
+const static uint64_t SH_FLD_APCCTL_ENABLE_MASTER_RETRY_BACKOFF = 2179; // 2
+const static uint64_t SH_FLD_APCCTL_ENB_CRESP_EXAM = 2180; // 2
+const static uint64_t SH_FLD_APCCTL_HANG_ARE = 2181; // 2
+const static uint64_t SH_FLD_APCCTL_HANG_DEAD = 2182; // 2
+const static uint64_t SH_FLD_APCCTL_MAX_RETRY = 2183; // 2
+const static uint64_t SH_FLD_APCCTL_MAX_RETRY_LEN = 2184; // 2
+const static uint64_t SH_FLD_APCCTL_P9_MODE = 2185; // 2
+const static uint64_t SH_FLD_APCCTL_PHB_SEL = 2186; // 2
+const static uint64_t SH_FLD_APCCTL_PHB_SEL_LEN = 2187; // 2
+const static uint64_t SH_FLD_APCCTL_SKIP_G = 2188; // 2
+const static uint64_t SH_FLD_APCCTL_SYSADDR = 2189; // 2
+const static uint64_t SH_FLD_APCCTL_SYSADDR_LEN = 2190; // 2
+const static uint64_t SH_FLD_APC_ARRAY_CMD_CE_ERPT = 2191; // 4
+const static uint64_t SH_FLD_APC_ARRAY_CMD_UE_ERPT = 2192; // 4
+const static uint64_t SH_FLD_AP_LEN = 2193; // 144
+const static uint64_t SH_FLD_ARBITRATION_LOST_ERROR_0 = 2194; // 2
+const static uint64_t SH_FLD_ARBITRATION_LOST_ERROR_1 = 2195; // 2
+const static uint64_t SH_FLD_ARBITRATION_LOST_ERROR_2 = 2196; // 2
+const static uint64_t SH_FLD_ARBITRATION_LOST_ERROR_3 = 2197; // 2
+const static uint64_t SH_FLD_ARB_EN_SEND_ALL_WRITES = 2198; // 1
+const static uint64_t SH_FLD_ARB_STALL = 2199; // 1
+const static uint64_t SH_FLD_ARB_STOP = 2200; // 1
+const static uint64_t SH_FLD_ARRAY_SELECT = 2201; // 1
+const static uint64_t SH_FLD_ARRAY_SELECT_LEN = 2202; // 1
+const static uint64_t SH_FLD_ARRAY_WRITE_ASSIST_EN = 2203; // 43
+const static uint64_t SH_FLD_ARY_ECC_CE = 2204; // 9
+const static uint64_t SH_FLD_ARY_ECC_CE_MASK = 2205; // 9
+const static uint64_t SH_FLD_ARY_ECC_SUE = 2206; // 9
+const static uint64_t SH_FLD_ARY_ECC_SUE_MASK = 2207; // 9
+const static uint64_t SH_FLD_ARY_ECC_UE = 2208; // 9
+const static uint64_t SH_FLD_ARY_ECC_UE_MASK = 2209; // 9
+const static uint64_t SH_FLD_ASSN_DONE = 2210; // 1
+const static uint64_t SH_FLD_ASYNC_INJ = 2211; // 16
+const static uint64_t SH_FLD_ASYNC_INJ_LEN = 2212; // 16
+const static uint64_t SH_FLD_ASYNC_MODE = 2213; // 6
+const static uint64_t SH_FLD_AS_INTERRUPT_ENABLE = 2214; // 2
+const static uint64_t SH_FLD_ATAG_0_15 = 2215; // 1
+const static uint64_t SH_FLD_ATAG_0_15_LEN = 2216; // 1
+const static uint64_t SH_FLD_ATOMIC_ALT_CE_INJ = 2217; // 2
+const static uint64_t SH_FLD_ATOMIC_ALT_CHIP_KILL_INJ = 2218; // 2
+const static uint64_t SH_FLD_ATOMIC_ALT_INJ_DATA_SEL = 2219; // 2
+const static uint64_t SH_FLD_ATOMIC_ALT_INJ_SYM_SEL = 2220; // 2
+const static uint64_t SH_FLD_ATOMIC_ALT_INJ_SYM_SEL_LEN = 2221; // 2
+const static uint64_t SH_FLD_ATOMIC_ALT_SD_UE_INJ = 2222; // 2
+const static uint64_t SH_FLD_ATOMIC_ALT_SUE_INJ = 2223; // 2
+const static uint64_t SH_FLD_ATSTSEL = 2224; // 17
+const static uint64_t SH_FLD_ATSTSEL_LEN = 2225; // 17
+const static uint64_t SH_FLD_ATTENTION = 2226; // 1
+const static uint64_t SH_FLD_ATX_PRIO_FOR_EQC_EOI_EQP = 2227; // 1
+const static uint64_t SH_FLD_ATX_PRIO_FOR_EQC_EOI_EQP_LEN = 2228; // 1
+const static uint64_t SH_FLD_ATX_PRIO_FOR_EQD_DMA = 2229; // 1
+const static uint64_t SH_FLD_ATX_PRIO_FOR_EQD_DMA_LEN = 2230; // 1
+const static uint64_t SH_FLD_ATX_PRIO_FOR_IRQ = 2231; // 1
+const static uint64_t SH_FLD_ATX_PRIO_FOR_IRQ_LEN = 2232; // 1
+const static uint64_t SH_FLD_ATX_PRIO_FOR_IVC = 2233; // 1
+const static uint64_t SH_FLD_ATX_PRIO_FOR_IVC_LEN = 2234; // 1
+const static uint64_t SH_FLD_ATX_PRIO_FOR_LSS_CI_LOAD = 2235; // 1
+const static uint64_t SH_FLD_ATX_PRIO_FOR_LSS_CI_LOAD_LEN = 2236; // 1
+const static uint64_t SH_FLD_ATX_PRIO_FOR_REGS = 2237; // 1
+const static uint64_t SH_FLD_ATX_PRIO_FOR_REGS_LEN = 2238; // 1
+const static uint64_t SH_FLD_ATX_PRIO_FOR_SBC_DMA = 2239; // 1
+const static uint64_t SH_FLD_ATX_PRIO_FOR_SBC_DMA_LEN = 2240; // 1
+const static uint64_t SH_FLD_ATX_PRIO_FOR_SBC_EOI_RESP = 2241; // 1
+const static uint64_t SH_FLD_ATX_PRIO_FOR_SBC_EOI_RESP_LEN = 2242; // 1
+const static uint64_t SH_FLD_ATX_PRIO_FOR_TRIG_FWD = 2243; // 1
+const static uint64_t SH_FLD_ATX_PRIO_FOR_TRIG_FWD_LEN = 2244; // 1
+const static uint64_t SH_FLD_AUE = 2245; // 2
+const static uint64_t SH_FLD_AUE_LEN = 2246; // 2
+const static uint64_t SH_FLD_AUTOINC = 2247; // 12
+const static uint64_t SH_FLD_AUTO_INCREMENT = 2248; // 3
+const static uint64_t SH_FLD_AUTO_POST_DECREMENT_FACES = 2249; // 1
+const static uint64_t SH_FLD_AUTO_POST_DECREMENT_PIB = 2250; // 1
+const static uint64_t SH_FLD_AUTO_PRE_INCREMENT_FACES = 2251; // 1
+const static uint64_t SH_FLD_AUTO_PRE_INCREMENT_PIB = 2252; // 1
+const static uint64_t SH_FLD_AUTO_RELOAD_N = 2253; // 2
+const static uint64_t SH_FLD_AUTO_STOP1_DISABLE = 2254; // 12
+const static uint64_t SH_FLD_AVAIL_GROUPS = 2255; // 2
+const static uint64_t SH_FLD_AVAIL_GROUPS_LEN = 2256; // 2
+const static uint64_t SH_FLD_AVG_CYCLE_SAMPLE = 2257; // 12
+const static uint64_t SH_FLD_AVG_CYCLE_SAMPLE_LEN = 2258; // 12
+const static uint64_t SH_FLD_AVS_SLAVE0 = 2259; // 1
+const static uint64_t SH_FLD_AVS_SLAVE1 = 2260; // 1
+const static uint64_t SH_FLD_AXFLOW_ERR = 2261; // 1
+const static uint64_t SH_FLD_AXFLOW_ERR_MASK = 2262; // 1
+const static uint64_t SH_FLD_AXPUSH_WRERR = 2263; // 1
+const static uint64_t SH_FLD_AXPUSH_WRERR_MASK = 2264; // 1
+const static uint64_t SH_FLD_AXRCV_DLO_ERR = 2265; // 1
+const static uint64_t SH_FLD_AXRCV_DLO_ERR_MASK = 2266; // 1
+const static uint64_t SH_FLD_AXRCV_DLO_TO = 2267; // 1
+const static uint64_t SH_FLD_AXRCV_DLO_TO_MASK = 2268; // 1
+const static uint64_t SH_FLD_AXRCV_RSVDATA_TO = 2269; // 1
+const static uint64_t SH_FLD_AXRCV_RSVDATA_TO_MASK = 2270; // 1
+const static uint64_t SH_FLD_AXSND_DHI_RTYTO = 2271; // 1
+const static uint64_t SH_FLD_AXSND_DHI_RTYTO_MASK = 2272; // 1
+const static uint64_t SH_FLD_AXSND_DLO_RTYTO = 2273; // 1
+const static uint64_t SH_FLD_AXSND_DLO_RTYTO_MASK = 2274; // 1
+const static uint64_t SH_FLD_AXSND_RSVERR = 2275; // 1
+const static uint64_t SH_FLD_AXSND_RSVERR_MASK = 2276; // 1
+const static uint64_t SH_FLD_AXSND_RSVTO = 2277; // 1
+const static uint64_t SH_FLD_AXSND_RSVTO_MASK = 2278; // 1
+const static uint64_t SH_FLD_A_BAD_DFE_CONV = 2279; // 144
+const static uint64_t SH_FLD_A_BANK_CONTROLS = 2280; // 120
+const static uint64_t SH_FLD_A_BANK_CONTROLS_LEN = 2281; // 120
+const static uint64_t SH_FLD_A_BIST_EN = 2282; // 6
+const static uint64_t SH_FLD_A_CONTROLS = 2283; // 120
+const static uint64_t SH_FLD_A_CONTROLS_LEN = 2284; // 120
+const static uint64_t SH_FLD_A_CTLE_COARSE = 2285; // 48
+const static uint64_t SH_FLD_A_CTLE_COARSE_LEN = 2286; // 48
+const static uint64_t SH_FLD_A_CTLE_GAIN = 2287; // 120
+const static uint64_t SH_FLD_A_CTLE_GAIN_LEN = 2288; // 120
+const static uint64_t SH_FLD_A_CTLE_PEAK = 2289; // 72
+const static uint64_t SH_FLD_A_CTLE_PEAK_LEN = 2290; // 72
+const static uint64_t SH_FLD_A_EVEN_INTEG_FINE_GAIN = 2291; // 120
+const static uint64_t SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN = 2292; // 120
+const static uint64_t SH_FLD_A_H10_VAL = 2293; // 72
+const static uint64_t SH_FLD_A_H10_VAL_LEN = 2294; // 72
+const static uint64_t SH_FLD_A_H11_VAL = 2295; // 72
+const static uint64_t SH_FLD_A_H11_VAL_LEN = 2296; // 72
+const static uint64_t SH_FLD_A_H12_VAL = 2297; // 72
+const static uint64_t SH_FLD_A_H12_VAL_LEN = 2298; // 72
+const static uint64_t SH_FLD_A_H1AP_AT_LIMIT = 2299; // 144
+const static uint64_t SH_FLD_A_H1ARATIO_VAL = 2300; // 72
+const static uint64_t SH_FLD_A_H1ARATIO_VAL_LEN = 2301; // 72
+const static uint64_t SH_FLD_A_H1CAL_EN = 2302; // 72
+const static uint64_t SH_FLD_A_H1CAL_VAL = 2303; // 72
+const static uint64_t SH_FLD_A_H1CAL_VAL_LEN = 2304; // 72
+const static uint64_t SH_FLD_A_H1E_VAL = 2305; // 120
+const static uint64_t SH_FLD_A_H1E_VAL_LEN = 2306; // 120
+const static uint64_t SH_FLD_A_H1O_VAL = 2307; // 120
+const static uint64_t SH_FLD_A_H1O_VAL_LEN = 2308; // 120
+const static uint64_t SH_FLD_A_H2E_VAL = 2309; // 72
+const static uint64_t SH_FLD_A_H2E_VAL_LEN = 2310; // 72
+const static uint64_t SH_FLD_A_H2O_VAL = 2311; // 72
+const static uint64_t SH_FLD_A_H2O_VAL_LEN = 2312; // 72
+const static uint64_t SH_FLD_A_H3E_VAL = 2313; // 72
+const static uint64_t SH_FLD_A_H3E_VAL_LEN = 2314; // 72
+const static uint64_t SH_FLD_A_H3O_VAL = 2315; // 72
+const static uint64_t SH_FLD_A_H3O_VAL_LEN = 2316; // 72
+const static uint64_t SH_FLD_A_H4E_VAL = 2317; // 72
+const static uint64_t SH_FLD_A_H4E_VAL_LEN = 2318; // 72
+const static uint64_t SH_FLD_A_H4O_VAL = 2319; // 72
+const static uint64_t SH_FLD_A_H4O_VAL_LEN = 2320; // 72
+const static uint64_t SH_FLD_A_H5E_VAL = 2321; // 72
+const static uint64_t SH_FLD_A_H5E_VAL_LEN = 2322; // 72
+const static uint64_t SH_FLD_A_H5O_VAL = 2323; // 72
+const static uint64_t SH_FLD_A_H5O_VAL_LEN = 2324; // 72
+const static uint64_t SH_FLD_A_H6_VAL = 2325; // 72
+const static uint64_t SH_FLD_A_H6_VAL_LEN = 2326; // 72
+const static uint64_t SH_FLD_A_H7_VAL = 2327; // 72
+const static uint64_t SH_FLD_A_H7_VAL_LEN = 2328; // 72
+const static uint64_t SH_FLD_A_H8_VAL = 2329; // 72
+const static uint64_t SH_FLD_A_H8_VAL_LEN = 2330; // 72
+const static uint64_t SH_FLD_A_H9_VAL = 2331; // 72
+const static uint64_t SH_FLD_A_H9_VAL_LEN = 2332; // 72
+const static uint64_t SH_FLD_A_INTEG_COARSE_GAIN = 2333; // 120
+const static uint64_t SH_FLD_A_INTEG_COARSE_GAIN_LEN = 2334; // 120
+const static uint64_t SH_FLD_A_ODD_INTEG_FINE_GAIN = 2335; // 120
+const static uint64_t SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN = 2336; // 120
+const static uint64_t SH_FLD_A_OFFSET_E0 = 2337; // 120
+const static uint64_t SH_FLD_A_OFFSET_E0_LEN = 2338; // 120
+const static uint64_t SH_FLD_A_OFFSET_E1 = 2339; // 120
+const static uint64_t SH_FLD_A_OFFSET_E1_LEN = 2340; // 120
+const static uint64_t SH_FLD_A_OFFSET_O0 = 2341; // 120
+const static uint64_t SH_FLD_A_OFFSET_O0_LEN = 2342; // 120
+const static uint64_t SH_FLD_A_OFFSET_O1 = 2343; // 120
+const static uint64_t SH_FLD_A_OFFSET_O1_LEN = 2344; // 120
+const static uint64_t SH_FLD_A_PATH_OFFSET_E = 2345; // 144
+const static uint64_t SH_FLD_A_PATH_OFFSET_E_LEN = 2346; // 144
+const static uint64_t SH_FLD_A_PATH_OFFSET_O = 2347; // 144
+const static uint64_t SH_FLD_A_PATH_OFFSET_O_LEN = 2348; // 144
+const static uint64_t SH_FLD_A_PR_DFE_CLKADJ = 2349; // 120
+const static uint64_t SH_FLD_A_PR_DFE_CLKADJ_LEN = 2350; // 120
+const static uint64_t SH_FLD_B0_63 = 2351; // 2
+const static uint64_t SH_FLD_B0_63_LEN = 2352; // 2
+const static uint64_t SH_FLD_B64_87 = 2353; // 2
+const static uint64_t SH_FLD_B64_87_LEN = 2354; // 2
+const static uint64_t SH_FLD_BACKUP_SEEPROM_SELECT = 2355; // 1
+const static uint64_t SH_FLD_BAD_ARRAY_ADDRESS_FACES = 2356; // 1
+const static uint64_t SH_FLD_BAD_ARRAY_ADDR_FACES = 2357; // 1
+const static uint64_t SH_FLD_BAD_ARRAY_ADDR_PIB = 2358; // 1
+const static uint64_t SH_FLD_BAD_BLOCK_LOCK = 2359; // 96
+const static uint64_t SH_FLD_BAD_BUS_LANE_ERR_CNTR_DIS_CLR = 2360; // 4
+const static uint64_t SH_FLD_BAD_DESKEW = 2361; // 96
+const static uint64_t SH_FLD_BAD_EYE_OPT_BER = 2362; // 96
+const static uint64_t SH_FLD_BAD_EYE_OPT_DDC = 2363; // 96
+const static uint64_t SH_FLD_BAD_EYE_OPT_HEIGHT = 2364; // 96
+const static uint64_t SH_FLD_BAD_EYE_OPT_WIDTH = 2365; // 96
+const static uint64_t SH_FLD_BAD_LANE1_GCRMSG = 2366; // 4
+const static uint64_t SH_FLD_BAD_LANE1_GCRMSG_LEN = 2367; // 4
+const static uint64_t SH_FLD_BAD_LANE2_GCRMSG = 2368; // 4
+const static uint64_t SH_FLD_BAD_LANE2_GCRMSG_LEN = 2369; // 4
+const static uint64_t SH_FLD_BAD_LANE_CODE_GCRMSG = 2370; // 4
+const static uint64_t SH_FLD_BAD_LANE_CODE_GCRMSG_LEN = 2371; // 4
+const static uint64_t SH_FLD_BAD_SKEW = 2372; // 96
+const static uint64_t SH_FLD_BANDSEL = 2373; // 20
+const static uint64_t SH_FLD_BANDSEL_LEN = 2374; // 20
+const static uint64_t SH_FLD_BANK = 2375; // 24
+const static uint64_t SH_FLD_BANK0_BIT_MAP = 2376; // 8
+const static uint64_t SH_FLD_BANK0_BIT_MAP_LEN = 2377; // 8
+const static uint64_t SH_FLD_BANK1_BIT_MAP = 2378; // 8
+const static uint64_t SH_FLD_BANK1_BIT_MAP_LEN = 2379; // 8
+const static uint64_t SH_FLD_BANK2_BIT_MAP = 2380; // 8
+const static uint64_t SH_FLD_BANK2_BIT_MAP_LEN = 2381; // 8
+const static uint64_t SH_FLD_BANK_GROUP0_BIT_MAP = 2382; // 8
+const static uint64_t SH_FLD_BANK_GROUP0_BIT_MAP_LEN = 2383; // 8
+const static uint64_t SH_FLD_BANK_GROUP1_BIT_MAP = 2384; // 8
+const static uint64_t SH_FLD_BANK_GROUP1_BIT_MAP_LEN = 2385; // 8
+const static uint64_t SH_FLD_BANK_PDWN = 2386; // 48
+const static uint64_t SH_FLD_BANK_PDWN_LEN = 2387; // 48
+const static uint64_t SH_FLD_BANK_SEL_A = 2388; // 48
+const static uint64_t SH_FLD_BAR = 2389; // 6
+const static uint64_t SH_FLD_BAR1_EN = 2390; // 4
+const static uint64_t SH_FLD_BAR1_MS_GROUP_CHIP = 2391; // 2
+const static uint64_t SH_FLD_BAR1_MS_GROUP_CHIP_LEN = 2392; // 2
+const static uint64_t SH_FLD_BAR1_SIZE = 2393; // 2
+const static uint64_t SH_FLD_BAR1_SIZE_LEN = 2394; // 2
+const static uint64_t SH_FLD_BAR1_STARTING_ADDRESS = 2395; // 4
+const static uint64_t SH_FLD_BAR1_STARTING_ADDRESS_LEN = 2396; // 4
+const static uint64_t SH_FLD_BAR1_SYSTEM = 2397; // 2
+const static uint64_t SH_FLD_BAR1_SYSTEM_LEN = 2398; // 2
+const static uint64_t SH_FLD_BARSEL = 2399; // 12
+const static uint64_t SH_FLD_BAR_LEN = 2400; // 6
+const static uint64_t SH_FLD_BAR_PE = 2401; // 13
+const static uint64_t SH_FLD_BAR_PE_MASK = 2402; // 9
+const static uint64_t SH_FLD_BAR_PIB_ON_ERROR1 = 2403; // 1
+const static uint64_t SH_FLD_BAR_PIB_ON_ERROR2 = 2404; // 1
+const static uint64_t SH_FLD_BAR_PIB_ON_ERROR3 = 2405; // 1
+const static uint64_t SH_FLD_BAR_PIB_ON_ERROR4 = 2406; // 1
+const static uint64_t SH_FLD_BAR_PIB_ON_ERROR5 = 2407; // 1
+const static uint64_t SH_FLD_BAR_PIB_ON_ERROR6 = 2408; // 1
+const static uint64_t SH_FLD_BAR_PIB_ON_ERROR7 = 2409; // 1
+const static uint64_t SH_FLD_BASE = 2410; // 26
+const static uint64_t SH_FLD_BASE_ADDR = 2411; // 2
+const static uint64_t SH_FLD_BASE_ADDR_LEN = 2412; // 2
+const static uint64_t SH_FLD_BASE_IDLE_COUNT = 2413; // 8
+const static uint64_t SH_FLD_BASE_IDLE_COUNT_LEN = 2414; // 8
+const static uint64_t SH_FLD_BASE_LEN = 2415; // 26
+const static uint64_t SH_FLD_BASE_UPPER_BITS = 2416; // 1
+const static uint64_t SH_FLD_BASE_UPPER_BITS_LEN = 2417; // 1
+const static uint64_t SH_FLD_BBWR_MASK = 2418; // 3
+const static uint64_t SH_FLD_BBWR_MASK_LEN = 2419; // 3
+const static uint64_t SH_FLD_BCAST_DONE = 2420; // 1
+const static uint64_t SH_FLD_BCDE_CE = 2421; // 1
+const static uint64_t SH_FLD_BCDE_CE_MASK = 2422; // 1
+const static uint64_t SH_FLD_BCDE_OCITRANS = 2423; // 1
+const static uint64_t SH_FLD_BCDE_OCITRANS_LEN = 2424; // 1
+const static uint64_t SH_FLD_BCDE_OCI_DATERR = 2425; // 1
+const static uint64_t SH_FLD_BCDE_OCI_DATERR_MASK = 2426; // 1
+const static uint64_t SH_FLD_BCDE_PB_ACK_DEAD = 2427; // 1
+const static uint64_t SH_FLD_BCDE_PB_ACK_DEAD_MASK = 2428; // 1
+const static uint64_t SH_FLD_BCDE_PB_ADRERR = 2429; // 1
+const static uint64_t SH_FLD_BCDE_PB_ADRERR_MASK = 2430; // 1
+const static uint64_t SH_FLD_BCDE_RDDATATO_ERR = 2431; // 1
+const static uint64_t SH_FLD_BCDE_RDDATATO_ERR_MASK = 2432; // 1
+const static uint64_t SH_FLD_BCDE_SETUP_ERR = 2433; // 1
+const static uint64_t SH_FLD_BCDE_SETUP_ERR_MASK = 2434; // 1
+const static uint64_t SH_FLD_BCDE_SUE_ERR = 2435; // 1
+const static uint64_t SH_FLD_BCDE_SUE_ERR_MASK = 2436; // 1
+const static uint64_t SH_FLD_BCDE_UE_ERR = 2437; // 1
+const static uint64_t SH_FLD_BCDE_UE_ERR_MASK = 2438; // 1
+const static uint64_t SH_FLD_BCESCR_OVERRIDE_EN = 2439; // 12
+const static uint64_t SH_FLD_BCE_BUSY_HIGH = 2440; // 12
+const static uint64_t SH_FLD_BCE_BUSY_LOW = 2441; // 12
+const static uint64_t SH_FLD_BCE_ERROR = 2442; // 12
+const static uint64_t SH_FLD_BCE_TIMEOUT = 2443; // 24
+const static uint64_t SH_FLD_BCUE_OCITRANS = 2444; // 1
+const static uint64_t SH_FLD_BCUE_OCITRANS_LEN = 2445; // 1
+const static uint64_t SH_FLD_BCUE_OCI_DATERR = 2446; // 1
+const static uint64_t SH_FLD_BCUE_OCI_DATERR_MASK = 2447; // 1
+const static uint64_t SH_FLD_BCUE_PB_ACK_DEAD = 2448; // 1
+const static uint64_t SH_FLD_BCUE_PB_ACK_DEAD_MASK = 2449; // 1
+const static uint64_t SH_FLD_BCUE_PB_ADRERR = 2450; // 1
+const static uint64_t SH_FLD_BCUE_PB_ADRERR_MASK = 2451; // 1
+const static uint64_t SH_FLD_BCUE_SETUP_ERR = 2452; // 1
+const static uint64_t SH_FLD_BCUE_SETUP_ERR_MASK = 2453; // 1
+const static uint64_t SH_FLD_BDF = 2454; // 18
+const static uint64_t SH_FLD_BDF_LEN = 2455; // 18
+const static uint64_t SH_FLD_BEAT_NUM = 2456; // 1
+const static uint64_t SH_FLD_BEAT_NUM_ERR = 2457; // 1
+const static uint64_t SH_FLD_BEAT_REC = 2458; // 1
+const static uint64_t SH_FLD_BEAT_REC_ERR = 2459; // 1
+const static uint64_t SH_FLD_BENIGN_PTR_DATA = 2460; // 2
+const static uint64_t SH_FLD_BER_CFG = 2461; // 120
+const static uint64_t SH_FLD_BER_CFG_LEN = 2462; // 120
+const static uint64_t SH_FLD_BER_CLR_COUNT_ON_READ_EN = 2463; // 6
+const static uint64_t SH_FLD_BER_CLR_TIMER_ON_READ_EN = 2464; // 6
+const static uint64_t SH_FLD_BER_COUNT_FREEZE_EN = 2465; // 6
+const static uint64_t SH_FLD_BER_COUNT_SEL = 2466; // 6
+const static uint64_t SH_FLD_BER_COUNT_SEL_LEN = 2467; // 6
+const static uint64_t SH_FLD_BER_DPIPE_MUX_SEL = 2468; // 120
+const static uint64_t SH_FLD_BER_EN = 2469; // 6
+const static uint64_t SH_FLD_BER_TIMEOUT = 2470; // 6
+const static uint64_t SH_FLD_BER_TIMEOUT_LEN = 2471; // 6
+const static uint64_t SH_FLD_BER_TIMER_FREEZE_EN = 2472; // 6
+const static uint64_t SH_FLD_BER_TIMER_SEL = 2473; // 6
+const static uint64_t SH_FLD_BER_TIMER_SEL_LEN = 2474; // 6
+const static uint64_t SH_FLD_BE_ACC_ERROR_0 = 2475; // 2
+const static uint64_t SH_FLD_BE_ACC_ERROR_1 = 2476; // 2
+const static uint64_t SH_FLD_BE_ACC_ERROR_2 = 2477; // 2
+const static uint64_t SH_FLD_BE_ACC_ERROR_3 = 2478; // 2
+const static uint64_t SH_FLD_BE_OV_ERROR_0 = 2479; // 2
+const static uint64_t SH_FLD_BE_OV_ERROR_1 = 2480; // 2
+const static uint64_t SH_FLD_BE_OV_ERROR_2 = 2481; // 2
+const static uint64_t SH_FLD_BE_OV_ERROR_3 = 2482; // 2
+const static uint64_t SH_FLD_BGOFFSET = 2483; // 14
+const static uint64_t SH_FLD_BGOFFSET_LEN = 2484; // 14
+const static uint64_t SH_FLD_BG_SCAN_RATE = 2485; // 2
+const static uint64_t SH_FLD_BG_SCAN_RATE_LEN = 2486; // 2
+const static uint64_t SH_FLD_BHR_DIR_STATE = 2487; // 2
+const static uint64_t SH_FLD_BHR_DIR_STATE_LEN = 2488; // 2
+const static uint64_t SH_FLD_BIG_RSP = 2489; // 1
+const static uint64_t SH_FLD_BIG_STEP = 2490; // 8
+const static uint64_t SH_FLD_BIG_STEP_LEN = 2491; // 8
+const static uint64_t SH_FLD_BISTCLK_EN = 2492; // 6
+const static uint64_t SH_FLD_BISTCLK_EN_LEN = 2493; // 2
+const static uint64_t SH_FLD_BIST_BIT_FAIL_TH = 2494; // 1
+const static uint64_t SH_FLD_BIST_BIT_FAIL_TH_LEN = 2495; // 1
+const static uint64_t SH_FLD_BIST_BUS_DATA_MODE = 2496; // 6
+const static uint64_t SH_FLD_BIST_COMPLETE = 2497; // 1
+const static uint64_t SH_FLD_BIST_CUPLL_LOCK_CHECK_EN = 2498; // 6
+const static uint64_t SH_FLD_BIST_DONE = 2499; // 6
+const static uint64_t SH_FLD_BIST_EN = 2500; // 13
+const static uint64_t SH_FLD_BIST_ENABLE = 2501; // 1
+const static uint64_t SH_FLD_BIST_ERR = 2502; // 96
+const static uint64_t SH_FLD_BIST_ERROR = 2503; // 1
+const static uint64_t SH_FLD_BIST_ERROR_LEN = 2504; // 1
+const static uint64_t SH_FLD_BIST_ERR_A = 2505; // 48
+const static uint64_t SH_FLD_BIST_ERR_B = 2506; // 48
+const static uint64_t SH_FLD_BIST_ERR_E = 2507; // 48
+const static uint64_t SH_FLD_BIST_EXT_START_MODE = 2508; // 6
+const static uint64_t SH_FLD_BIST_EYE_A_WIDTH = 2509; // 6
+const static uint64_t SH_FLD_BIST_EYE_A_WIDTH_LEN = 2510; // 6
+const static uint64_t SH_FLD_BIST_EYE_B_WIDTH = 2511; // 6
+const static uint64_t SH_FLD_BIST_EYE_B_WIDTH_LEN = 2512; // 6
+const static uint64_t SH_FLD_BIST_INIT_DISABLE = 2513; // 6
+const static uint64_t SH_FLD_BIST_INIT_DISABLE_LEN = 2514; // 6
+const static uint64_t SH_FLD_BIST_INIT_DONE = 2515; // 6
+const static uint64_t SH_FLD_BIST_JITTER_PULSE_SEL = 2516; // 4
+const static uint64_t SH_FLD_BIST_JITTER_PULSE_SEL_LEN = 2517; // 4
+const static uint64_t SH_FLD_BIST_LL_ERR = 2518; // 6
+const static uint64_t SH_FLD_BIST_LL_TEST_EN = 2519; // 6
+const static uint64_t SH_FLD_BIST_MIN_EYE_WIDTH = 2520; // 6
+const static uint64_t SH_FLD_BIST_MIN_EYE_WIDTH_LEN = 2521; // 6
+const static uint64_t SH_FLD_BIST_NO_EDGE_DET = 2522; // 6
+const static uint64_t SH_FLD_BIST_PLL_LOCK_TIMEOUT = 2523; // 4
+const static uint64_t SH_FLD_BIST_PLL_LOCK_TIMEOUT_LEN = 2524; // 4
+const static uint64_t SH_FLD_BIST_PRBS_PROP_TIME = 2525; // 6
+const static uint64_t SH_FLD_BIST_PRBS_PROP_TIME_LEN = 2526; // 6
+const static uint64_t SH_FLD_BIST_PRBS_TEST_TIME = 2527; // 6
+const static uint64_t SH_FLD_BIST_PRBS_TEST_TIME_LEN = 2528; // 6
+const static uint64_t SH_FLD_BIST_STORE_EYES_BANK_SEL = 2529; // 6
+const static uint64_t SH_FLD_BIST_STORE_EYES_BANK_SEL_LEN = 2530; // 6
+const static uint64_t SH_FLD_BIST_STORE_EYES_LANE_SEL = 2531; // 6
+const static uint64_t SH_FLD_BIST_STORE_EYES_LANE_SEL_LEN = 2532; // 6
+const static uint64_t SH_FLD_BITS = 2533; // 16
+const static uint64_t SH_FLD_BITSEL = 2534; // 3
+const static uint64_t SH_FLD_BITSEL_LEN = 2535; // 3
+const static uint64_t SH_FLD_BITS_LEN = 2536; // 16
+const static uint64_t SH_FLD_BIT_RATE_DIVISOR = 2537; // 1
+const static uint64_t SH_FLD_BIT_RATE_DIVISOR_0 = 2538; // 3
+const static uint64_t SH_FLD_BIT_RATE_DIVISOR_0_LEN = 2539; // 3
+const static uint64_t SH_FLD_BIT_RATE_DIVISOR_1 = 2540; // 3
+const static uint64_t SH_FLD_BIT_RATE_DIVISOR_1_LEN = 2541; // 3
+const static uint64_t SH_FLD_BIT_RATE_DIVISOR_2 = 2542; // 3
+const static uint64_t SH_FLD_BIT_RATE_DIVISOR_2_LEN = 2543; // 3
+const static uint64_t SH_FLD_BIT_RATE_DIVISOR_3 = 2544; // 3
+const static uint64_t SH_FLD_BIT_RATE_DIVISOR_3_LEN = 2545; // 3
+const static uint64_t SH_FLD_BIT_RATE_DIVISOR_LEN = 2546; // 1
+const static uint64_t SH_FLD_BIT_RATE_DIVISOR_VALUE = 2547; // 1
+const static uint64_t SH_FLD_BIT_RATE_DIVISOR_VALUE_LEN = 2548; // 1
+const static uint64_t SH_FLD_BKINV_INTERLOCK_DIS = 2549; // 1
+const static uint64_t SH_FLD_BLKU_DONE = 2550; // 1
+const static uint64_t SH_FLD_BLOCKID = 2551; // 9
+const static uint64_t SH_FLD_BLOCKID_LEN = 2552; // 9
+const static uint64_t SH_FLD_BLOCK_ALL_WKUP_SOURCES = 2553; // 30
+const static uint64_t SH_FLD_BLOCK_FIR_ERR_INJ = 2554; // 24
+const static uint64_t SH_FLD_BLOCK_GROUP_EN = 2555; // 1
+const static uint64_t SH_FLD_BLOCK_MUX_PORT_SEL = 2556; // 2
+const static uint64_t SH_FLD_BLOCK_MUX_PORT_SEL_LEN = 2557; // 2
+const static uint64_t SH_FLD_BLOCK_REG_WKUP_SOURCES = 2558; // 30
+const static uint64_t SH_FLD_BLOCK_SEL = 2559; // 2
+const static uint64_t SH_FLD_BLOCK_SEL_LEN = 2560; // 2
+const static uint64_t SH_FLD_BLOCK_TRACK_EN = 2561; // 1
+const static uint64_t SH_FLD_BLOCK_TRACK_RESET_DELAY = 2562; // 1
+const static uint64_t SH_FLD_BLOCK_TRACK_RESET_DELAY_LEN = 2563; // 1
+const static uint64_t SH_FLD_BNDY = 2564; // 43
+const static uint64_t SH_FLD_BOOT_VECTOR_WORD0 = 2565; // 1
+const static uint64_t SH_FLD_BOOT_VECTOR_WORD0_LEN = 2566; // 1
+const static uint64_t SH_FLD_BOOT_VECTOR_WORD1 = 2567; // 1
+const static uint64_t SH_FLD_BOOT_VECTOR_WORD1_LEN = 2568; // 1
+const static uint64_t SH_FLD_BOOT_VECTOR_WORD2 = 2569; // 1
+const static uint64_t SH_FLD_BOOT_VECTOR_WORD2_LEN = 2570; // 1
+const static uint64_t SH_FLD_BOOT_VECTOR_WORD3 = 2571; // 1
+const static uint64_t SH_FLD_BOOT_VECTOR_WORD3_LEN = 2572; // 1
+const static uint64_t SH_FLD_BRAZOS = 2573; // 1
+const static uint64_t SH_FLD_BRICK_DEBUG_MODE = 2574; // 6
+const static uint64_t SH_FLD_BRICK_ENABLE = 2575; // 6
+const static uint64_t SH_FLD_BRIDGE_ENABLE = 2576; // 1
+const static uint64_t SH_FLD_BRK0TO2 = 2577; // 1
+const static uint64_t SH_FLD_BRK0TO2_LEN = 2578; // 1
+const static uint64_t SH_FLD_BRK0_CLUSTER = 2579; // 1
+const static uint64_t SH_FLD_BRK0_CLUSTER_LEN = 2580; // 1
+const static uint64_t SH_FLD_BRK1_CLUSTER = 2581; // 1
+const static uint64_t SH_FLD_BRK1_CLUSTER_LEN = 2582; // 1
+const static uint64_t SH_FLD_BRK2_CLUSTER = 2583; // 1
+const static uint64_t SH_FLD_BRK2_CLUSTER_LEN = 2584; // 1
+const static uint64_t SH_FLD_BRK3_CLUSTER = 2585; // 1
+const static uint64_t SH_FLD_BRK3_CLUSTER_LEN = 2586; // 1
+const static uint64_t SH_FLD_BRK4_CLUSTER = 2587; // 1
+const static uint64_t SH_FLD_BRK4_CLUSTER_LEN = 2588; // 1
+const static uint64_t SH_FLD_BRK5_CLUSTER = 2589; // 1
+const static uint64_t SH_FLD_BRK5_CLUSTER_LEN = 2590; // 1
+const static uint64_t SH_FLD_BROADCAST_SYNC_EN = 2591; // 2
+const static uint64_t SH_FLD_BROADCAST_SYNC_WAIT = 2592; // 2
+const static uint64_t SH_FLD_BROADCAST_SYNC_WAIT_LEN = 2593; // 2
+const static uint64_t SH_FLD_BUF0_REG_DATA0 = 2594; // 2
+const static uint64_t SH_FLD_BUF0_REG_DATA0_LEN = 2595; // 2
+const static uint64_t SH_FLD_BUF1_REG_DATA0 = 2596; // 1
+const static uint64_t SH_FLD_BUF1_REG_DATA0_LEN = 2597; // 1
+const static uint64_t SH_FLD_BUF1_REG_DATA1 = 2598; // 1
+const static uint64_t SH_FLD_BUF1_REG_DATA1_LEN = 2599; // 1
+const static uint64_t SH_FLD_BUFFER = 2600; // 12
+const static uint64_t SH_FLD_BUFFER_OVERRUN = 2601; // 8
+const static uint64_t SH_FLD_BUFFER_STATUS = 2602; // 6
+const static uint64_t SH_FLD_BUFFER_STATUS_LEN = 2603; // 6
+const static uint64_t SH_FLD_BUF_ALLOC_A = 2604; // 4
+const static uint64_t SH_FLD_BUF_ALLOC_B = 2605; // 4
+const static uint64_t SH_FLD_BUF_ALLOC_C = 2606; // 4
+const static uint64_t SH_FLD_BUF_ALLOC_W = 2607; // 4
+const static uint64_t SH_FLD_BUF_INVALIDATE_CTL = 2608; // 4
+const static uint64_t SH_FLD_BURST_INTERVAL = 2609; // 2
+const static uint64_t SH_FLD_BURST_INTERVAL_LEN = 2610; // 2
+const static uint64_t SH_FLD_BURST_WINDOW = 2611; // 10
+const static uint64_t SH_FLD_BURST_WINDOW_LEN = 2612; // 10
+const static uint64_t SH_FLD_BURST_WINDOW_SEL = 2613; // 2
+const static uint64_t SH_FLD_BUSY = 2614; // 43
+const static uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD0 = 2615; // 8
+const static uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD0_LEN = 2616; // 8
+const static uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD1 = 2617; // 8
+const static uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD1_LEN = 2618; // 8
+const static uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD2 = 2619; // 8
+const static uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD2_LEN = 2620; // 8
+const static uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD3 = 2621; // 8
+const static uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD3_LEN = 2622; // 8
+const static uint64_t SH_FLD_BUSY_COUNTER_WINDOW_SELECT = 2623; // 8
+const static uint64_t SH_FLD_BUSY_COUNTER_WINDOW_SELECT_LEN = 2624; // 8
+const static uint64_t SH_FLD_BUSY_RESPONSE_CODE = 2625; // 1
+const static uint64_t SH_FLD_BUSY_RESPONSE_CODE_LEN = 2626; // 1
+const static uint64_t SH_FLD_BUSY_RESPONSE_CODE_NO_1 = 2627; // 1
+const static uint64_t SH_FLD_BUSY_RESPONSE_CODE_NO_1_LEN = 2628; // 1
+const static uint64_t SH_FLD_BUSY_STATUS = 2629; // 1
+const static uint64_t SH_FLD_BUSY_STATUS_LEN = 2630; // 1
+const static uint64_t SH_FLD_BUS_ADDR_NVLD_0 = 2631; // 1
+const static uint64_t SH_FLD_BUS_ADDR_NVLD_1 = 2632; // 1
+const static uint64_t SH_FLD_BUS_ADDR_NVLD_2 = 2633; // 1
+const static uint64_t SH_FLD_BUS_ADDR_NVLD_3 = 2634; // 1
+const static uint64_t SH_FLD_BUS_ADDR_P_ERR_0 = 2635; // 1
+const static uint64_t SH_FLD_BUS_ADDR_P_ERR_1 = 2636; // 1
+const static uint64_t SH_FLD_BUS_ADDR_P_ERR_2 = 2637; // 1
+const static uint64_t SH_FLD_BUS_ADDR_P_ERR_3 = 2638; // 1
+const static uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_0 = 2639; // 1
+const static uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_1 = 2640; // 1
+const static uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_2 = 2641; // 1
+const static uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_3 = 2642; // 1
+const static uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_0 = 2643; // 1
+const static uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_1 = 2644; // 1
+const static uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_2 = 2645; // 1
+const static uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_3 = 2646; // 1
+const static uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_0 = 2647; // 1
+const static uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_1 = 2648; // 1
+const static uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_2 = 2649; // 1
+const static uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_3 = 2650; // 1
+const static uint64_t SH_FLD_BUS_BUSY_0 = 2651; // 1
+const static uint64_t SH_FLD_BUS_BUSY_1 = 2652; // 1
+const static uint64_t SH_FLD_BUS_BUSY_2 = 2653; // 1
+const static uint64_t SH_FLD_BUS_BUSY_3 = 2654; // 1
+const static uint64_t SH_FLD_BUS_COMMAND_COMPLETE_0 = 2655; // 1
+const static uint64_t SH_FLD_BUS_COMMAND_COMPLETE_1 = 2656; // 1
+const static uint64_t SH_FLD_BUS_COMMAND_COMPLETE_2 = 2657; // 1
+const static uint64_t SH_FLD_BUS_COMMAND_COMPLETE_3 = 2658; // 1
+const static uint64_t SH_FLD_BUS_DATA_REQUEST_0 = 2659; // 1
+const static uint64_t SH_FLD_BUS_DATA_REQUEST_1 = 2660; // 1
+const static uint64_t SH_FLD_BUS_DATA_REQUEST_2 = 2661; // 1
+const static uint64_t SH_FLD_BUS_DATA_REQUEST_3 = 2662; // 1
+const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_0 = 2663; // 1
+const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_0_LEN = 2664; // 1
+const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_1 = 2665; // 1
+const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_1_LEN = 2666; // 1
+const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_2 = 2667; // 1
+const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_2_LEN = 2668; // 1
+const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_3 = 2669; // 1
+const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_3_LEN = 2670; // 1
+const static uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_0 = 2671; // 1
+const static uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_1 = 2672; // 1
+const static uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_2 = 2673; // 1
+const static uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_3 = 2674; // 1
+const static uint64_t SH_FLD_BUS_I2C_PORT_BUSY_0 = 2675; // 1
+const static uint64_t SH_FLD_BUS_I2C_PORT_BUSY_1 = 2676; // 1
+const static uint64_t SH_FLD_BUS_I2C_PORT_BUSY_2 = 2677; // 1
+const static uint64_t SH_FLD_BUS_I2C_PORT_BUSY_3 = 2678; // 1
+const static uint64_t SH_FLD_BUS_ID = 2679; // 12
+const static uint64_t SH_FLD_BUS_ID_LEN = 2680; // 12
+const static uint64_t SH_FLD_BUS_INVALID_COMMAND_0 = 2681; // 1
+const static uint64_t SH_FLD_BUS_INVALID_COMMAND_1 = 2682; // 1
+const static uint64_t SH_FLD_BUS_INVALID_COMMAND_2 = 2683; // 1
+const static uint64_t SH_FLD_BUS_INVALID_COMMAND_3 = 2684; // 1
+const static uint64_t SH_FLD_BUS_LB_PARITY_ERROR_0 = 2685; // 1
+const static uint64_t SH_FLD_BUS_LB_PARITY_ERROR_1 = 2686; // 1
+const static uint64_t SH_FLD_BUS_LB_PARITY_ERROR_2 = 2687; // 1
+const static uint64_t SH_FLD_BUS_LB_PARITY_ERROR_3 = 2688; // 1
+const static uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_0 = 2689; // 1
+const static uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_1 = 2690; // 1
+const static uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_2 = 2691; // 1
+const static uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_3 = 2692; // 1
+const static uint64_t SH_FLD_BUS_PARITY_ERROR_0 = 2693; // 1
+const static uint64_t SH_FLD_BUS_PARITY_ERROR_1 = 2694; // 1
+const static uint64_t SH_FLD_BUS_PARITY_ERROR_2 = 2695; // 1
+const static uint64_t SH_FLD_BUS_PARITY_ERROR_3 = 2696; // 1
+const static uint64_t SH_FLD_BUS_PAR_ERR_0 = 2697; // 1
+const static uint64_t SH_FLD_BUS_PAR_ERR_1 = 2698; // 1
+const static uint64_t SH_FLD_BUS_PAR_ERR_2 = 2699; // 1
+const static uint64_t SH_FLD_BUS_PAR_ERR_3 = 2700; // 1
+const static uint64_t SH_FLD_BUS_READ_NVLD_0 = 2701; // 1
+const static uint64_t SH_FLD_BUS_READ_NVLD_1 = 2702; // 1
+const static uint64_t SH_FLD_BUS_READ_NVLD_2 = 2703; // 1
+const static uint64_t SH_FLD_BUS_READ_NVLD_3 = 2704; // 1
+const static uint64_t SH_FLD_BUS_STOP_ERROR_0 = 2705; // 1
+const static uint64_t SH_FLD_BUS_STOP_ERROR_1 = 2706; // 1
+const static uint64_t SH_FLD_BUS_STOP_ERROR_2 = 2707; // 1
+const static uint64_t SH_FLD_BUS_STOP_ERROR_3 = 2708; // 1
+const static uint64_t SH_FLD_BUS_WIDTH = 2709; // 4
+const static uint64_t SH_FLD_BUS_WIDTH_LEN = 2710; // 4
+const static uint64_t SH_FLD_BUS_WRITE_NVLD_0 = 2711; // 1
+const static uint64_t SH_FLD_BUS_WRITE_NVLD_1 = 2712; // 1
+const static uint64_t SH_FLD_BUS_WRITE_NVLD_2 = 2713; // 1
+const static uint64_t SH_FLD_BUS_WRITE_NVLD_3 = 2714; // 1
+const static uint64_t SH_FLD_BYPASSCLKOUT = 2715; // 3
+const static uint64_t SH_FLD_BYPASSN = 2716; // 10
+const static uint64_t SH_FLD_B_BAD_DFE_CONV = 2717; // 144
+const static uint64_t SH_FLD_B_BANK_CONTROLS = 2718; // 48
+const static uint64_t SH_FLD_B_BANK_CONTROLS_LEN = 2719; // 48
+const static uint64_t SH_FLD_B_BIST_EN = 2720; // 2
+const static uint64_t SH_FLD_B_CONTROLS = 2721; // 48
+const static uint64_t SH_FLD_B_CONTROLS_LEN = 2722; // 48
+const static uint64_t SH_FLD_B_CTLE_COARSE = 2723; // 48
+const static uint64_t SH_FLD_B_CTLE_COARSE_LEN = 2724; // 48
+const static uint64_t SH_FLD_B_CTLE_GAIN = 2725; // 48
+const static uint64_t SH_FLD_B_CTLE_GAIN_LEN = 2726; // 48
+const static uint64_t SH_FLD_B_EVEN_INTEG_FINE_GAIN = 2727; // 48
+const static uint64_t SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN = 2728; // 48
+const static uint64_t SH_FLD_B_H1AP_AT_LIMIT = 2729; // 144
+const static uint64_t SH_FLD_B_H1E_VAL = 2730; // 48
+const static uint64_t SH_FLD_B_H1E_VAL_LEN = 2731; // 48
+const static uint64_t SH_FLD_B_H1O_VAL = 2732; // 48
+const static uint64_t SH_FLD_B_H1O_VAL_LEN = 2733; // 48
+const static uint64_t SH_FLD_B_INTEG_COARSE_GAIN = 2734; // 48
+const static uint64_t SH_FLD_B_INTEG_COARSE_GAIN_LEN = 2735; // 48
+const static uint64_t SH_FLD_B_ODD_INTEG_FINE_GAIN = 2736; // 48
+const static uint64_t SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN = 2737; // 48
+const static uint64_t SH_FLD_B_OFFSET_E0 = 2738; // 48
+const static uint64_t SH_FLD_B_OFFSET_E0_LEN = 2739; // 48
+const static uint64_t SH_FLD_B_OFFSET_E1 = 2740; // 48
+const static uint64_t SH_FLD_B_OFFSET_E1_LEN = 2741; // 48
+const static uint64_t SH_FLD_B_OFFSET_O0 = 2742; // 48
+const static uint64_t SH_FLD_B_OFFSET_O0_LEN = 2743; // 48
+const static uint64_t SH_FLD_B_OFFSET_O1 = 2744; // 48
+const static uint64_t SH_FLD_B_OFFSET_O1_LEN = 2745; // 48
+const static uint64_t SH_FLD_B_PATH_OFFSET_E = 2746; // 48
+const static uint64_t SH_FLD_B_PATH_OFFSET_E_LEN = 2747; // 48
+const static uint64_t SH_FLD_B_PATH_OFFSET_O = 2748; // 48
+const static uint64_t SH_FLD_B_PATH_OFFSET_O_LEN = 2749; // 48
+const static uint64_t SH_FLD_B_PR_DFE_CLKADJ = 2750; // 48
+const static uint64_t SH_FLD_B_PR_DFE_CLKADJ_LEN = 2751; // 48
+const static uint64_t SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE = 2752; // 12
+const static uint64_t SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE = 2753; // 12
+const static uint64_t SH_FLD_CACHE_CTRL_ARY_SELECT = 2754; // 3
+const static uint64_t SH_FLD_CACHE_CTRL_ARY_SELECT_LEN = 2755; // 3
+const static uint64_t SH_FLD_CACHE_INHIBITED_HIT_CACHEABLE_ERROR = 2756; // 12
+const static uint64_t SH_FLD_CACHE_RD_CE = 2757; // 12
+const static uint64_t SH_FLD_CACHE_RD_CE_AND_UE = 2758; // 12
+const static uint64_t SH_FLD_CACHE_RD_SUE = 2759; // 12
+const static uint64_t SH_FLD_CACHE_RD_UE = 2760; // 12
+const static uint64_t SH_FLD_CACHE_UE_SUE_DETECTED_ON_MODIFIED_LINE_BY_CO =
+    2761; // 12
+const static uint64_t SH_FLD_CACHE_UE_SUE_DETECTED_ON_NON_MODIFIED_LINE_BY_CO =
+    2762; // 12
+const static uint64_t SH_FLD_CAC_ALLOC_DIS = 2763; // 2
+const static uint64_t SH_FLD_CAL0_INVALID_ACCESS = 2764; // 8
+const static uint64_t SH_FLD_CAL0_PE = 2765; // 8
+const static uint64_t SH_FLD_CAL1_INVALID_ACCESS = 2766; // 8
+const static uint64_t SH_FLD_CAL1_PE = 2767; // 8
+const static uint64_t SH_FLD_CAL2_INVALID_ACCESS = 2768; // 8
+const static uint64_t SH_FLD_CAL2_PE = 2769; // 8
+const static uint64_t SH_FLD_CAL3_INVALID_ACCESS = 2770; // 8
+const static uint64_t SH_FLD_CAL3_PE = 2771; // 8
+const static uint64_t SH_FLD_CALRECAL = 2772; // 10
+const static uint64_t SH_FLD_CALREQ = 2773; // 10
+const static uint64_t SH_FLD_CAL_LANE_GCRMSG = 2774; // 4
+const static uint64_t SH_FLD_CAL_LANE_GCRMSG_LEN = 2775; // 4
+const static uint64_t SH_FLD_CAL_LANE_PHY_GCRMSG = 2776; // 6
+const static uint64_t SH_FLD_CAL_LANE_PHY_GCRMSG_LEN = 2777; // 6
+const static uint64_t SH_FLD_CAL_LANE_SEL = 2778; // 188
+const static uint64_t SH_FLD_CAL_LANE_VAL_GCRMSG = 2779; // 4
+const static uint64_t SH_FLD_CAL_SM_1HOT = 2780; // 8
+const static uint64_t SH_FLD_CAM256_MAX_CNT = 2781; // 6
+const static uint64_t SH_FLD_CAM256_MAX_CNT_LEN = 2782; // 6
+const static uint64_t SH_FLD_CAPP_ERROR = 2783; // 9
+const static uint64_t SH_FLD_CAPP_ERROR_MASK = 2784; // 9
+const static uint64_t SH_FLD_CAPSEL = 2785; // 4
+const static uint64_t SH_FLD_CASCADE = 2786; // 2
+const static uint64_t SH_FLD_CASCADE_LEN = 2787; // 2
+const static uint64_t SH_FLD_CC = 2788; // 10
+const static uint64_t SH_FLD_CCALBANDSEL = 2789; // 10
+const static uint64_t SH_FLD_CCALBANDSEL_LEN = 2790; // 10
+const static uint64_t SH_FLD_CCALCOMP = 2791; // 10
+const static uint64_t SH_FLD_CCALCVHOLD = 2792; // 10
+const static uint64_t SH_FLD_CCALERR = 2793; // 10
+const static uint64_t SH_FLD_CCALFMAX = 2794; // 10
+const static uint64_t SH_FLD_CCALFMIN = 2795; // 10
+const static uint64_t SH_FLD_CCALLOAD = 2796; // 10
+const static uint64_t SH_FLD_CCALMETH = 2797; // 10
+const static uint64_t SH_FLD_CCFG_GPTR = 2798; // 43
+const static uint64_t SH_FLD_CCS_ARRAY_CE_ERR_INJ = 2799; // 2
+const static uint64_t SH_FLD_CCS_ARRAY_CE_ERR_INJ_MODE = 2800; // 2
+const static uint64_t SH_FLD_CCS_ARRAY_UE_ERR_INJ = 2801; // 2
+const static uint64_t SH_FLD_CCS_ARRAY_UE_ERR_INJ_MODE = 2802; // 2
+const static uint64_t SH_FLD_CCS_CNTLQ_PE = 2803; // 2
+const static uint64_t SH_FLD_CCS_INTERNAL_FSM_INJ_MODE = 2804; // 2
+const static uint64_t SH_FLD_CCS_INTERNAL_FSM_INJ_REG = 2805; // 2
+const static uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE0 = 2806; // 2
+const static uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE0_LEN = 2807; // 2
+const static uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE1 = 2808; // 2
+const static uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE1_LEN = 2809; // 2
+const static uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE2 = 2810; // 2
+const static uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE2_LEN = 2811; // 2
+const static uint64_t SH_FLD_CC_CTRL_CHIPLET_IS_ALIGNED_DC = 2812; // 43
+const static uint64_t SH_FLD_CC_CTRL_OPCG_DONE_DC = 2813; // 43
+const static uint64_t SH_FLD_CC_MASK = 2814; // 8
+const static uint64_t SH_FLD_CD_ALL_DONE_GCRMSG = 2815; // 4
+const static uint64_t SH_FLD_CD_PREV_DONE_GCRMSG = 2816; // 4
+const static uint64_t SH_FLD_CE = 2817; // 46
+const static uint64_t SH_FLD_CE1_0_OUT = 2818; // 4
+const static uint64_t SH_FLD_CE1_1_OUT = 2819; // 4
+const static uint64_t SH_FLD_CE1_2_OUT = 2820; // 4
+const static uint64_t SH_FLD_CE1_3_OUT = 2821; // 4
+const static uint64_t SH_FLD_CE1_4_OUT = 2822; // 4
+const static uint64_t SH_FLD_CE1_5_OUT = 2823; // 4
+const static uint64_t SH_FLD_CE1_6_OUT = 2824; // 4
+const static uint64_t SH_FLD_CE1_7_OUT = 2825; // 4
+const static uint64_t SH_FLD_CE2_0_OUT = 2826; // 4
+const static uint64_t SH_FLD_CE2_1_OUT = 2827; // 4
+const static uint64_t SH_FLD_CE2_2_OUT = 2828; // 4
+const static uint64_t SH_FLD_CE2_3_OUT = 2829; // 4
+const static uint64_t SH_FLD_CE2_4_OUT = 2830; // 4
+const static uint64_t SH_FLD_CE2_5_OUT = 2831; // 4
+const static uint64_t SH_FLD_CE2_6_OUT = 2832; // 4
+const static uint64_t SH_FLD_CE2_7_OUT = 2833; // 4
+const static uint64_t SH_FLD_CEC_PSI_INTERRUPT = 2834; // 1
+const static uint64_t SH_FLD_CENTAURP_ENABLE_64B_READ_OPS = 2835; // 4
+const static uint64_t SH_FLD_CENTAURP_ENABLE_BYPASS_CMD = 2836; // 4
+const static uint64_t SH_FLD_CENTAURP_ENABLE_CENTAURP_CMD = 2837; // 4
+const static uint64_t SH_FLD_CENTAURP_ENABLE_CP_ME = 2838; // 4
+const static uint64_t SH_FLD_CENTAURP_ENABLE_CR_SIDEBAND = 2839; // 4
+const static uint64_t SH_FLD_CENTAURP_ENABLE_DTAG_CR = 2840; // 4
+const static uint64_t SH_FLD_CENTAURP_ENABLE_DYNAMIC_WRBUF_ALLOC = 2841; // 4
+const static uint64_t SH_FLD_CENTAURP_ENABLE_ECRESP = 2842; // 4
+const static uint64_t SH_FLD_CENTAURP_ENABLE_NEW_AMO = 2843; // 4
+const static uint64_t SH_FLD_CENTAURP_INBAND_IS_63 = 2844; // 4
+const static uint64_t SH_FLD_CENTAUR_MODE = 2845; // 4
+const static uint64_t SH_FLD_CENTAUR_SYNC_COMMAND_DETECTED = 2846; // 4
+const static uint64_t SH_FLD_CERR_AXFLOW_ERR = 2847; // 1
+const static uint64_t SH_FLD_CERR_AXFLOW_ERR_LEN = 2848; // 1
+const static uint64_t SH_FLD_CERR_AXPUSH_WRERR = 2849; // 1
+const static uint64_t SH_FLD_CERR_AXPUSH_WRERR_LEN = 2850; // 1
+const static uint64_t SH_FLD_CERR_BAR_PARITY_ERR = 2851; // 1
+const static uint64_t SH_FLD_CERR_BCDE_INTERNAL_ERR = 2852; // 1
+const static uint64_t SH_FLD_CERR_BCDE_INTERNAL_ERR_LEN = 2853; // 1
+const static uint64_t SH_FLD_CERR_BCDE_SETUP_ERR = 2854; // 1
+const static uint64_t SH_FLD_CERR_BCDE_SETUP_ERR_LEN = 2855; // 1
+const static uint64_t SH_FLD_CERR_BCUE_INTERNAL_ERR = 2856; // 1
+const static uint64_t SH_FLD_CERR_BCUE_INTERNAL_ERR_LEN = 2857; // 1
+const static uint64_t SH_FLD_CERR_BCUE_OCI_DATAERR = 2858; // 1
+const static uint64_t SH_FLD_CERR_BCUE_OCI_DATAERR_LEN = 2859; // 1
+const static uint64_t SH_FLD_CERR_BCUE_SETUP_ERR = 2860; // 1
+const static uint64_t SH_FLD_CERR_BCUE_SETUP_ERR_LEN = 2861; // 1
+const static uint64_t SH_FLD_CERR_PBDOUT_PARITY_ERR = 2862; // 1
+const static uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_RD = 2863; // 1
+const static uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_RD_LEN = 2864; // 1
+const static uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_WR = 2865; // 1
+const static uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_WR_LEN = 2866; // 1
+const static uint64_t SH_FLD_CERR_PB_BADCRESP = 2867; // 1
+const static uint64_t SH_FLD_CERR_PB_BADCRESP_LEN = 2868; // 1
+const static uint64_t SH_FLD_CERR_PB_OPERTO = 2869; // 1
+const static uint64_t SH_FLD_CERR_PB_OPERTO_LEN = 2870; // 1
+const static uint64_t SH_FLD_CERR_PB_PARITY_ERR = 2871; // 1
+const static uint64_t SH_FLD_CERR_PB_PARITY_ERR_LEN = 2872; // 1
+const static uint64_t SH_FLD_CERR_PB_RDADRERR_FW = 2873; // 1
+const static uint64_t SH_FLD_CERR_PB_RDADRERR_FW_LEN = 2874; // 1
+const static uint64_t SH_FLD_CERR_PB_RDDATATO_FW = 2875; // 1
+const static uint64_t SH_FLD_CERR_PB_RDDATATO_FW_LEN = 2876; // 1
+const static uint64_t SH_FLD_CERR_PB_UNEXPCRESP = 2877; // 1
+const static uint64_t SH_FLD_CERR_PB_UNEXPCRESP_LEN = 2878; // 1
+const static uint64_t SH_FLD_CERR_PB_UNEXPDATA = 2879; // 1
+const static uint64_t SH_FLD_CERR_PB_UNEXPDATA_LEN = 2880; // 1
+const static uint64_t SH_FLD_CERR_PB_WRADRERR_FW = 2881; // 1
+const static uint64_t SH_FLD_CERR_PB_WRADRERR_FW_LEN = 2882; // 1
+const static uint64_t SH_FLD_CERR_SCOMTB_ERR = 2883; // 1
+const static uint64_t SH_FLD_CERR_SLV_INTERNAL_ERR = 2884; // 1
+const static uint64_t SH_FLD_CERR_SLV_INTERNAL_ERR_LEN = 2885; // 1
+const static uint64_t SH_FLD_CERR_SPARE = 2886; // 1
+const static uint64_t SH_FLD_CERR_SPARE_LEN = 2887; // 1
+const static uint64_t SH_FLD_CE_CMD = 2888; // 3
+const static uint64_t SH_FLD_CE_CMD_LEN = 2889; // 3
+const static uint64_t SH_FLD_CE_LEN = 2890; // 3
+const static uint64_t SH_FLD_CE_THRESH = 2891; // 3
+const static uint64_t SH_FLD_CE_THRESH_LEN = 2892; // 3
+const static uint64_t SH_FLD_CE_WVAL = 2893; // 3
+const static uint64_t SH_FLD_CE_WVAL_LEN = 2894; // 3
+const static uint64_t SH_FLD_CFG = 2895; // 43
+const static uint64_t SH_FLD_CFG_2N_ADDR = 2896; // 8
+const static uint64_t SH_FLD_CFG_ACT_TO_DIFF_RANK_DLY = 2897; // 8
+const static uint64_t SH_FLD_CFG_ACT_TO_DIFF_RANK_DLY_LEN = 2898; // 8
+const static uint64_t SH_FLD_CFG_ADDRESS_COUNTER = 2899; // 2
+const static uint64_t SH_FLD_CFG_ADDRESS_COUNTER_LEN = 2900; // 2
+const static uint64_t SH_FLD_CFG_ADDR_COUNTER_MODE = 2901; // 2
+const static uint64_t SH_FLD_CFG_ADDR_COUNTER_MODE_LEN = 2902; // 2
+const static uint64_t SH_FLD_CFG_ALL_PERIODIC_LENGTH = 2903; // 8
+const static uint64_t SH_FLD_CFG_ALL_PERIODIC_LENGTH_LEN = 2904; // 8
+const static uint64_t SH_FLD_CFG_ALL_PERIODIC_TB = 2905; // 8
+const static uint64_t SH_FLD_CFG_ALL_PERIODIC_TB_LEN = 2906; // 8
+const static uint64_t SH_FLD_CFG_ALWAYS_WAIT_ACT_TIME = 2907; // 8
+const static uint64_t SH_FLD_CFG_AMAP_BANK0 = 2908; // 2
+const static uint64_t SH_FLD_CFG_AMAP_BANK0_LEN = 2909; // 2
+const static uint64_t SH_FLD_CFG_AMAP_BANK1 = 2910; // 2
+const static uint64_t SH_FLD_CFG_AMAP_BANK1_LEN = 2911; // 2
+const static uint64_t SH_FLD_CFG_AMAP_BANK2 = 2912; // 2
+const static uint64_t SH_FLD_CFG_AMAP_BANK2_LEN = 2913; // 2
+const static uint64_t SH_FLD_CFG_AMAP_BANK_GROUP0 = 2914; // 2
+const static uint64_t SH_FLD_CFG_AMAP_BANK_GROUP0_LEN = 2915; // 2
+const static uint64_t SH_FLD_CFG_AMAP_BANK_GROUP1 = 2916; // 2
+const static uint64_t SH_FLD_CFG_AMAP_BANK_GROUP1_LEN = 2917; // 2
+const static uint64_t SH_FLD_CFG_AMAP_COL2 = 2918; // 2
+const static uint64_t SH_FLD_CFG_AMAP_COL2_LEN = 2919; // 2
+const static uint64_t SH_FLD_CFG_AMAP_COL3 = 2920; // 2
+const static uint64_t SH_FLD_CFG_AMAP_COL3_LEN = 2921; // 2
+const static uint64_t SH_FLD_CFG_AMAP_COL4 = 2922; // 2
+const static uint64_t SH_FLD_CFG_AMAP_COL4_LEN = 2923; // 2
+const static uint64_t SH_FLD_CFG_AMAP_COL5 = 2924; // 2
+const static uint64_t SH_FLD_CFG_AMAP_COL5_LEN = 2925; // 2
+const static uint64_t SH_FLD_CFG_AMAP_COL6 = 2926; // 2
+const static uint64_t SH_FLD_CFG_AMAP_COL6_LEN = 2927; // 2
+const static uint64_t SH_FLD_CFG_AMAP_COL7 = 2928; // 2
+const static uint64_t SH_FLD_CFG_AMAP_COL7_LEN = 2929; // 2
+const static uint64_t SH_FLD_CFG_AMAP_COL8 = 2930; // 2
+const static uint64_t SH_FLD_CFG_AMAP_COL8_LEN = 2931; // 2
+const static uint64_t SH_FLD_CFG_AMAP_COL9 = 2932; // 2
+const static uint64_t SH_FLD_CFG_AMAP_COL9_LEN = 2933; // 2
+const static uint64_t SH_FLD_CFG_AMAP_DIMM_SELECT = 2934; // 2
+const static uint64_t SH_FLD_CFG_AMAP_DIMM_SELECT_LEN = 2935; // 2
+const static uint64_t SH_FLD_CFG_AMAP_MRANK0 = 2936; // 2
+const static uint64_t SH_FLD_CFG_AMAP_MRANK0_LEN = 2937; // 2
+const static uint64_t SH_FLD_CFG_AMAP_MRANK1 = 2938; // 2
+const static uint64_t SH_FLD_CFG_AMAP_MRANK1_LEN = 2939; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW0 = 2940; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW0_LEN = 2941; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW1 = 2942; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW10 = 2943; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW10_LEN = 2944; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW11 = 2945; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW11_LEN = 2946; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW12 = 2947; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW12_LEN = 2948; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW13 = 2949; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW13_LEN = 2950; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW14 = 2951; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW14_LEN = 2952; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW15 = 2953; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW15_LEN = 2954; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW16 = 2955; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW16_LEN = 2956; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW17 = 2957; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW17_LEN = 2958; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW1_LEN = 2959; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW2 = 2960; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW2_LEN = 2961; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW3 = 2962; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW3_LEN = 2963; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW4 = 2964; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW4_LEN = 2965; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW5 = 2966; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW5_LEN = 2967; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW6 = 2968; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW6_LEN = 2969; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW7 = 2970; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW7_LEN = 2971; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW8 = 2972; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW8_LEN = 2973; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW9 = 2974; // 2
+const static uint64_t SH_FLD_CFG_AMAP_ROW9_LEN = 2975; // 2
+const static uint64_t SH_FLD_CFG_AMAP_SRANK0 = 2976; // 2
+const static uint64_t SH_FLD_CFG_AMAP_SRANK0_LEN = 2977; // 2
+const static uint64_t SH_FLD_CFG_AMAP_SRANK1 = 2978; // 2
+const static uint64_t SH_FLD_CFG_AMAP_SRANK1_LEN = 2979; // 2
+const static uint64_t SH_FLD_CFG_AMAP_SRANK2 = 2980; // 2
+const static uint64_t SH_FLD_CFG_AMAP_SRANK2_LEN = 2981; // 2
+const static uint64_t SH_FLD_CFG_ARB_PRIO_PULL = 2982; // 1
+const static uint64_t SH_FLD_CFG_ARB_PRIO_PULL_LEN = 2983; // 1
+const static uint64_t SH_FLD_CFG_ARB_PRIO_PUSH = 2984; // 1
+const static uint64_t SH_FLD_CFG_ARB_PRIO_PUSH_LEN = 2985; // 1
+const static uint64_t SH_FLD_CFG_ARB_PRIO_QUERY = 2986; // 1
+const static uint64_t SH_FLD_CFG_ARB_PRIO_QUERY_LEN = 2987; // 1
+const static uint64_t SH_FLD_CFG_ARB_PRIO_RR = 2988; // 1
+const static uint64_t SH_FLD_CFG_ARB_PRIO_RR_LEN = 2989; // 1
+const static uint64_t SH_FLD_CFG_ARB_PULL_PRIO_HYP = 2990; // 1
+const static uint64_t SH_FLD_CFG_ARB_PULL_PRIO_HYP_LEN = 2991; // 1
+const static uint64_t SH_FLD_CFG_ARB_PUSH_PRIO_HYP = 2992; // 1
+const static uint64_t SH_FLD_CFG_ARB_PUSH_PRIO_HYP_LEN = 2993; // 1
+const static uint64_t SH_FLD_CFG_AUTOPC_THRESHOLD = 2994; // 8
+const static uint64_t SH_FLD_CFG_AUTOPC_THRESHOLD_LEN = 2995; // 8
+const static uint64_t SH_FLD_CFG_BANK_BUSY_FSM_DIS = 2996; // 8
+const static uint64_t SH_FLD_CFG_BANK_BUSY_FSM_DIS_LEN = 2997; // 8
+const static uint64_t SH_FLD_CFG_BANK_BUSY_OPEN_PAGE_DIS = 2998; // 8
+const static uint64_t SH_FLD_CFG_BANK_BUSY_OPEN_PAGE_DIS_LEN = 2999; // 8
+const static uint64_t SH_FLD_CFG_BC4_EN = 3000; // 2
+const static uint64_t SH_FLD_CFG_BW_SNAPSHOT = 3001; // 8
+const static uint64_t SH_FLD_CFG_BW_SNAPSHOT_LEN = 3002; // 8
+const static uint64_t SH_FLD_CFG_C0 = 3003; // 1
+const static uint64_t SH_FLD_CFG_C0_L2_PB_ARB_RATE_SEL = 3004; // 12
+const static uint64_t SH_FLD_CFG_C0_L2_PB_ARB_RATE_SEL_LEN = 3005; // 12
+const static uint64_t SH_FLD_CFG_C0_LEN = 3006; // 1
+const static uint64_t SH_FLD_CFG_C1 = 3007; // 1
+const static uint64_t SH_FLD_CFG_C10 = 3008; // 1
+const static uint64_t SH_FLD_CFG_C10_LEN = 3009; // 1
+const static uint64_t SH_FLD_CFG_C11 = 3010; // 1
+const static uint64_t SH_FLD_CFG_C11_LEN = 3011; // 1
+const static uint64_t SH_FLD_CFG_C1_L2_PB_ARB_RATE_SEL = 3012; // 12
+const static uint64_t SH_FLD_CFG_C1_L2_PB_ARB_RATE_SEL_LEN = 3013; // 12
+const static uint64_t SH_FLD_CFG_C1_LEN = 3014; // 1
+const static uint64_t SH_FLD_CFG_C2 = 3015; // 1
+const static uint64_t SH_FLD_CFG_C2_LEN = 3016; // 1
+const static uint64_t SH_FLD_CFG_C3 = 3017; // 1
+const static uint64_t SH_FLD_CFG_C3_LEN = 3018; // 1
+const static uint64_t SH_FLD_CFG_C4 = 3019; // 1
+const static uint64_t SH_FLD_CFG_C4_LEN = 3020; // 1
+const static uint64_t SH_FLD_CFG_C5 = 3021; // 1
+const static uint64_t SH_FLD_CFG_C5_LEN = 3022; // 1
+const static uint64_t SH_FLD_CFG_C6 = 3023; // 1
+const static uint64_t SH_FLD_CFG_C6_LEN = 3024; // 1
+const static uint64_t SH_FLD_CFG_C7 = 3025; // 1
+const static uint64_t SH_FLD_CFG_C7_LEN = 3026; // 1
+const static uint64_t SH_FLD_CFG_C8 = 3027; // 1
+const static uint64_t SH_FLD_CFG_C8_LEN = 3028; // 1
+const static uint64_t SH_FLD_CFG_C9 = 3029; // 1
+const static uint64_t SH_FLD_CFG_C9_LEN = 3030; // 1
+const static uint64_t SH_FLD_CFG_CAC_ERR_REPAIR_EN = 3031; // 12
+const static uint64_t SH_FLD_CFG_CAL_INTERVAL_TMR0_ENABLE = 3032; // 8
+const static uint64_t SH_FLD_CFG_CAL_INTERVAL_TMR1_ENABLE = 3033; // 8
+const static uint64_t SH_FLD_CFG_CAL_INTERVAL_TMR2_ENABLE = 3034; // 8
+const static uint64_t SH_FLD_CFG_CAL_RANK_ENABLE = 3035; // 8
+const static uint64_t SH_FLD_CFG_CAL_RANK_ENABLE_LEN = 3036; // 8
+const static uint64_t SH_FLD_CFG_CAL_SINGLE_PORT_MODE = 3037; // 8
+const static uint64_t SH_FLD_CFG_CAL_SINGLE_PORT_MODE_LEN = 3038; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_DDR_DONE = 3039; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_ENABLE = 3040; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_TYPE = 3041; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_TYPE_LEN = 3042; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_DDR_DONE = 3043; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_ENABLE = 3044; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_TYPE = 3045; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_TYPE_LEN = 3046; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_DDR_DONE = 3047; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_ENABLE = 3048; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_TYPE = 3049; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_TYPE_LEN = 3050; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_ENABLE = 3051; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR = 3052; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_LEN = 3053; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_TB = 3054; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_TB_LEN = 3055; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR0_SINGLE_RANK = 3056; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR0_Z_SYNC = 3057; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR0_Z_SYNC_LEN = 3058; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_DDR_DONE = 3059; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_ENABLE = 3060; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_TYPE = 3061; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_TYPE_LEN = 3062; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_DDR_DONE = 3063; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_ENABLE = 3064; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_TYPE = 3065; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_TYPE_LEN = 3066; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_DDR_DONE = 3067; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_ENABLE = 3068; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_TYPE = 3069; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_TYPE_LEN = 3070; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR1_SINGLE_RANK = 3071; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR1_Z_SYNC = 3072; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR1_Z_SYNC_LEN = 3073; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_DDR_DONE = 3074; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_ENABLE = 3075; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_TYPE = 3076; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_TYPE_LEN = 3077; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_DDR_DONE = 3078; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_ENABLE = 3079; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_TYPE = 3080; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_TYPE_LEN = 3081; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_DDR_DONE = 3082; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_ENABLE = 3083; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_TYPE = 3084; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_TYPE_LEN = 3085; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR2_SINGLE_RANK = 3086; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR2_WAT_EVENT_ENABLE = 3087; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR2_Z_SYNC = 3088; // 8
+const static uint64_t SH_FLD_CFG_CAL_TMR2_Z_SYNC_LEN = 3089; // 8
+const static uint64_t SH_FLD_CFG_CCS_ADDR_MUX_SEL = 3090; // 8
+const static uint64_t SH_FLD_CFG_CCS_INST_RESET_ENABLE = 3091; // 8
+const static uint64_t SH_FLD_CFG_CKE_PUP_STATE = 3092; // 8
+const static uint64_t SH_FLD_CFG_CKE_PUP_STATE_LEN = 3093; // 8
+const static uint64_t SH_FLD_CFG_CO_SOFT_PURGE_ALL_LINES_EN = 3094; // 12
+const static uint64_t SH_FLD_CFG_CO_SOFT_PURGE_ME_SX_EN = 3095; // 12
+const static uint64_t SH_FLD_CFG_CURRENT_ADDR_TRAP = 3096; // 2
+const static uint64_t SH_FLD_CFG_CURRENT_ADDR_TRAP_LEN = 3097; // 2
+const static uint64_t SH_FLD_CFG_CURRENT_PORT_DIMM_TRAP = 3098; // 2
+const static uint64_t SH_FLD_CFG_CURRENT_PORT_DIMM_TRAP_LEN = 3099; // 2
+const static uint64_t SH_FLD_CFG_CURR_ADDR_TRAP_ENABLE = 3100; // 2
+const static uint64_t SH_FLD_CFG_DATA_ROT = 3101; // 2
+const static uint64_t SH_FLD_CFG_DATA_ROT_LEN = 3102; // 2
+const static uint64_t SH_FLD_CFG_DATA_ROT_SEED = 3103; // 4
+const static uint64_t SH_FLD_CFG_DATA_ROT_SEED_LEN = 3104; // 4
+const static uint64_t SH_FLD_CFG_DATA_SEED_MODE = 3105; // 2
+const static uint64_t SH_FLD_CFG_DATA_SEED_MODE_LEN = 3106; // 2
+const static uint64_t SH_FLD_CFG_DCACHE_CAPP_LPC_EN = 3107; // 12
+const static uint64_t SH_FLD_CFG_DCBZ_TRASHMODE_EN = 3108; // 12
+const static uint64_t SH_FLD_CFG_DDR4_PARITY_ON_CID_DIS = 3109; // 8
+const static uint64_t SH_FLD_CFG_DDR_DPHY_NCLK = 3110; // 8
+const static uint64_t SH_FLD_CFG_DDR_DPHY_NCLK_LEN = 3111; // 8
+const static uint64_t SH_FLD_CFG_DDR_DPHY_PCLK = 3112; // 8
+const static uint64_t SH_FLD_CFG_DDR_DPHY_PCLK_LEN = 3113; // 8
+const static uint64_t SH_FLD_CFG_DDR_RESETN = 3114; // 8
+const static uint64_t SH_FLD_CFG_DGEN_FIXED_MODE = 3115; // 2
+const static uint64_t SH_FLD_CFG_DISABLE_CL_ATOMIC_LOCK = 3116; // 43
+const static uint64_t SH_FLD_CFG_DISABLE_FAST_PATH = 3117; // 8
+const static uint64_t SH_FLD_CFG_DISABLE_FORCE_TO_ZERO = 3118; // 43
+const static uint64_t SH_FLD_CFG_DISABLE_HEARTBEAT = 3119; // 43
+const static uint64_t SH_FLD_CFG_DISABLE_MALF_PULSE_GEN = 3120; // 43
+const static uint64_t SH_FLD_CFG_DISABLE_PERV_THOLD_CHECK = 3121; // 43
+const static uint64_t SH_FLD_CFG_DISABLE_RCD_RECOVERY = 3122; // 8
+const static uint64_t SH_FLD_CFG_DISABLE_RD_PG_MODE = 3123; // 8
+const static uint64_t SH_FLD_CFG_DISABLE_REFRESH_DURING_NOISE_WDW = 3124; // 8
+const static uint64_t SH_FLD_CFG_DISABLE_WR_PG_MODE = 3125; // 8
+const static uint64_t SH_FLD_CFG_DIS_CLK_IN_STR = 3126; // 8
+const static uint64_t SH_FLD_CFG_DIS_SMDR = 3127; // 8
+const static uint64_t SH_FLD_CFG_DONE_IACK_PRIO_HYP = 3128; // 1
+const static uint64_t SH_FLD_CFG_DONE_IACK_PRIO_HYP_LEN = 3129; // 1
+const static uint64_t SH_FLD_CFG_DONE_PARSE_IACK_RR_SEL = 3130; // 1
+const static uint64_t SH_FLD_CFG_DONE_PARSE_IACK_RR_SEL_LEN = 3131; // 1
+const static uint64_t SH_FLD_CFG_DONE_PARSE_PULL_RR_SEL = 3132; // 1
+const static uint64_t SH_FLD_CFG_DONE_PARSE_PULL_RR_SEL_LEN = 3133; // 1
+const static uint64_t SH_FLD_CFG_DONE_PRIO_IACK = 3134; // 1
+const static uint64_t SH_FLD_CFG_DONE_PRIO_IACK_LEN = 3135; // 1
+const static uint64_t SH_FLD_CFG_DONE_PULL_PRIO_HYP = 3136; // 1
+const static uint64_t SH_FLD_CFG_DONE_PULL_PRIO_HYP_LEN = 3137; // 1
+const static uint64_t SH_FLD_CFG_DQS_ALIGNMENT_LENGTH = 3138; // 8
+const static uint64_t SH_FLD_CFG_DQS_ALIGNMENT_LENGTH_LEN = 3139; // 8
+const static uint64_t SH_FLD_CFG_DQS_ALIGNMENT_TB = 3140; // 8
+const static uint64_t SH_FLD_CFG_DQS_ALIGNMENT_TB_LEN = 3141; // 8
+const static uint64_t SH_FLD_CFG_ECCCK_CE_UE_SUE_ERR_DET_DIS = 3142; // 12
+const static uint64_t SH_FLD_CFG_ECCCK_UE_SUE_DET_DIS = 3143; // 12
+const static uint64_t SH_FLD_CFG_EMER_MIN_MAX_DOMAIN = 3144; // 8
+const static uint64_t SH_FLD_CFG_EMER_MIN_MAX_DOMAIN_LEN = 3145; // 8
+const static uint64_t SH_FLD_CFG_ENABLE_RCD_RW_RETRY = 3146; // 8
+const static uint64_t SH_FLD_CFG_END_ADDR_0 = 3147; // 2
+const static uint64_t SH_FLD_CFG_END_ADDR_0_LEN = 3148; // 2
+const static uint64_t SH_FLD_CFG_END_ADDR_1 = 3149; // 2
+const static uint64_t SH_FLD_CFG_END_ADDR_1_LEN = 3150; // 2
+const static uint64_t SH_FLD_CFG_END_ADDR_2 = 3151; // 2
+const static uint64_t SH_FLD_CFG_END_ADDR_2_LEN = 3152; // 2
+const static uint64_t SH_FLD_CFG_END_ADDR_3 = 3153; // 2
+const static uint64_t SH_FLD_CFG_END_ADDR_3_LEN = 3154; // 2
+const static uint64_t SH_FLD_CFG_ENTER_STR_TIME = 3155; // 8
+const static uint64_t SH_FLD_CFG_ENTER_STR_TIME_LEN = 3156; // 8
+const static uint64_t SH_FLD_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR = 3157; // 8
+const static uint64_t SH_FLD_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR_LEN = 3158; // 8
+const static uint64_t SH_FLD_CFG_EN_RANDCMD_GAP = 3159; // 2
+const static uint64_t SH_FLD_CFG_EXTERNAL_ZQ_LENGTH = 3160; // 8
+const static uint64_t SH_FLD_CFG_EXTERNAL_ZQ_LENGTH_LEN = 3161; // 8
+const static uint64_t SH_FLD_CFG_EXTERNAL_ZQ_TB = 3162; // 8
+const static uint64_t SH_FLD_CFG_EXTERNAL_ZQ_TB_LEN = 3163; // 8
+const static uint64_t SH_FLD_CFG_FIXED_SEED = 3164; // 16
+const static uint64_t SH_FLD_CFG_FIXED_SEED1 = 3165; // 2
+const static uint64_t SH_FLD_CFG_FIXED_SEED1_LEN = 3166; // 2
+const static uint64_t SH_FLD_CFG_FIXED_SEED2 = 3167; // 2
+const static uint64_t SH_FLD_CFG_FIXED_SEED2_LEN = 3168; // 2
+const static uint64_t SH_FLD_CFG_FIXED_SEED3 = 3169; // 2
+const static uint64_t SH_FLD_CFG_FIXED_SEED3_LEN = 3170; // 2
+const static uint64_t SH_FLD_CFG_FIXED_SEED4 = 3171; // 2
+const static uint64_t SH_FLD_CFG_FIXED_SEED4_LEN = 3172; // 2
+const static uint64_t SH_FLD_CFG_FIXED_SEED5 = 3173; // 2
+const static uint64_t SH_FLD_CFG_FIXED_SEED5_LEN = 3174; // 2
+const static uint64_t SH_FLD_CFG_FIXED_SEED6 = 3175; // 2
+const static uint64_t SH_FLD_CFG_FIXED_SEED6_LEN = 3176; // 2
+const static uint64_t SH_FLD_CFG_FIXED_SEED7 = 3177; // 2
+const static uint64_t SH_FLD_CFG_FIXED_SEED7_LEN = 3178; // 2
+const static uint64_t SH_FLD_CFG_FIXED_SEED8 = 3179; // 2
+const static uint64_t SH_FLD_CFG_FIXED_SEED8_LEN = 3180; // 2
+const static uint64_t SH_FLD_CFG_FIXED_SEED_LEN = 3181; // 16
+const static uint64_t SH_FLD_CFG_FIXED_WIDTH = 3182; // 2
+const static uint64_t SH_FLD_CFG_FIXED_WIDTH_LEN = 3183; // 2
+const static uint64_t SH_FLD_CFG_FORCE_MCLK_LOW_N = 3184; // 8
+const static uint64_t SH_FLD_CFG_FORCE_SPARE_PUP = 3185; // 8
+const static uint64_t SH_FLD_CFG_FREEZE_ON_PARITY_ERROR_DIS = 3186; // 8
+const static uint64_t SH_FLD_CFG_GP_BIT_3_ENABLE = 3187; // 8
+const static uint64_t SH_FLD_CFG_HASH_L3_ADDR_EN = 3188; // 12
+const static uint64_t SH_FLD_CFG_HW_TRIG_LINEDEL_LDDISP_CE_EN = 3189; // 12
+const static uint64_t SH_FLD_CFG_IGNORE_RCD_PARITY_ERR = 3190; // 8
+const static uint64_t SH_FLD_CFG_INJECT_PARITY_ERR_ADDR5 = 3191; // 8
+const static uint64_t SH_FLD_CFG_INJECT_PARITY_ERR_CONSTANT = 3192; // 8
+const static uint64_t SH_FLD_CFG_INJECT_PARITY_ERR_WEN = 3193; // 8
+const static uint64_t SH_FLD_CFG_INTERNAL_ZQ_LENGTH = 3194; // 8
+const static uint64_t SH_FLD_CFG_INTERNAL_ZQ_LENGTH_LEN = 3195; // 8
+const static uint64_t SH_FLD_CFG_INTERNAL_ZQ_TB = 3196; // 8
+const static uint64_t SH_FLD_CFG_INTERNAL_ZQ_TB_LEN = 3197; // 8
+const static uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR0 = 3198; // 8
+const static uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR0_LEN = 3199; // 8
+const static uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR1 = 3200; // 8
+const static uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR1_LEN = 3201; // 8
+const static uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR2 = 3202; // 8
+const static uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR2_LEN = 3203; // 8
+const static uint64_t SH_FLD_CFG_INVERT_DATA = 3204; // 2
+const static uint64_t SH_FLD_CFG_L3_DIS = 3205; // 12
+const static uint64_t SH_FLD_CFG_LDST_PRIO_RSP_LD = 3206; // 1
+const static uint64_t SH_FLD_CFG_LDST_PRIO_RSP_LD_LEN = 3207; // 1
+const static uint64_t SH_FLD_CFG_LDST_PRIO_SET_LD = 3208; // 1
+const static uint64_t SH_FLD_CFG_LDST_PRIO_SET_LD_LEN = 3209; // 1
+const static uint64_t SH_FLD_CFG_LFSR_MASK_A0 = 3210; // 2
+const static uint64_t SH_FLD_CFG_LFSR_MASK_A0_LEN = 3211; // 2
+const static uint64_t SH_FLD_CFG_LINEDEL_ON_CAC_UE_EN = 3212; // 12
+const static uint64_t SH_FLD_CFG_LP_SUB_CNT = 3213; // 8
+const static uint64_t SH_FLD_CFG_LP_SUB_CNT_LEN = 3214; // 8
+const static uint64_t SH_FLD_CFG_LRU_DIRECT_MAP = 3215; // 12
+const static uint64_t SH_FLD_CFG_MAINT_ADDR_MODE_EN = 3216; // 2
+const static uint64_t SH_FLD_CFG_MAINT_BROADCAST_MODE_EN = 3217; // 2
+const static uint64_t SH_FLD_CFG_MAINT_RCE_WITH_CE = 3218; // 2
+const static uint64_t SH_FLD_CFG_MAX = 3219; // 1
+const static uint64_t SH_FLD_CFG_MAX_LEN = 3220; // 1
+const static uint64_t SH_FLD_CFG_MAX_READS_IN_A_ROW = 3221; // 8
+const static uint64_t SH_FLD_CFG_MAX_READS_IN_A_ROW_LEN = 3222; // 8
+const static uint64_t SH_FLD_CFG_MAX_WRITES_IN_A_ROW = 3223; // 8
+const static uint64_t SH_FLD_CFG_MAX_WRITES_IN_A_ROW_LEN = 3224; // 8
+const static uint64_t SH_FLD_CFG_MCB_LEN64 = 3225; // 2
+const static uint64_t SH_FLD_CFG_MCE_HARD_SYMBOL_COUNT_ENABLE = 3226; // 2
+const static uint64_t SH_FLD_CFG_MCE_INTER_SYMBOL_COUNT_ENABLE = 3227; // 2
+const static uint64_t SH_FLD_CFG_MCE_SOFT_SYMBOL_COUNT_ENABLE = 3228; // 2
+const static uint64_t SH_FLD_CFG_MIN_CMD_GAP = 3229; // 2
+const static uint64_t SH_FLD_CFG_MIN_CMD_GAP_LEN = 3230; // 2
+const static uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_CNT_REFR_INT = 3231; // 8
+const static uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_ENABLE = 3232; // 8
+const static uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_TIME = 3233; // 8
+const static uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_TIME_LEN = 3234; // 8
+const static uint64_t SH_FLD_CFG_MIN_GAP_TIMEBASE = 3235; // 2
+const static uint64_t SH_FLD_CFG_MIN_MAX_DOMAINS = 3236; // 8
+const static uint64_t SH_FLD_CFG_MIN_MAX_DOMAINS_ENABLE = 3237; // 8
+const static uint64_t SH_FLD_CFG_MIN_MAX_DOMAINS_LEN = 3238; // 8
+const static uint64_t SH_FLD_CFG_MISR_BLOCK = 3239; // 8
+const static uint64_t SH_FLD_CFG_MISR_BLOCK_LEN = 3240; // 8
+const static uint64_t SH_FLD_CFG_MISR_FEEDBACK_ENABLE = 3241; // 8
+const static uint64_t SH_FLD_CFG_MPR_READEYE_LENGTH = 3242; // 8
+const static uint64_t SH_FLD_CFG_MPR_READEYE_LENGTH_LEN = 3243; // 8
+const static uint64_t SH_FLD_CFG_MPR_READEYE_TB = 3244; // 8
+const static uint64_t SH_FLD_CFG_MPR_READEYE_TB_LEN = 3245; // 8
+const static uint64_t SH_FLD_CFG_NCE_HARD_SYMBOL_COUNT_ENABLE = 3246; // 2
+const static uint64_t SH_FLD_CFG_NCE_INTER_SYMBOL_COUNT_ENABLE = 3247; // 2
+const static uint64_t SH_FLD_CFG_NCE_SOFT_SYMBOL_COUNT_ENABLE = 3248; // 2
+const static uint64_t SH_FLD_CFG_NM_CAS_WEIGHT = 3249; // 8
+const static uint64_t SH_FLD_CFG_NM_CAS_WEIGHT_LEN = 3250; // 8
+const static uint64_t SH_FLD_CFG_NM_CHANGE_AFTER_SYNC = 3251; // 8
+const static uint64_t SH_FLD_CFG_NM_M = 3252; // 8
+const static uint64_t SH_FLD_CFG_NM_M_LEN = 3253; // 8
+const static uint64_t SH_FLD_CFG_NM_N_PER_PORT = 3254; // 8
+const static uint64_t SH_FLD_CFG_NM_N_PER_PORT_LEN = 3255; // 8
+const static uint64_t SH_FLD_CFG_NM_N_PER_SLOT = 3256; // 8
+const static uint64_t SH_FLD_CFG_NM_N_PER_SLOT_LEN = 3257; // 8
+const static uint64_t SH_FLD_CFG_NM_RAS_WEIGHT = 3258; // 8
+const static uint64_t SH_FLD_CFG_NM_RAS_WEIGHT_LEN = 3259; // 8
+const static uint64_t SH_FLD_CFG_NOISE_WAIT_TIME = 3260; // 8
+const static uint64_t SH_FLD_CFG_NOISE_WAIT_TIME_LEN = 3261; // 8
+const static uint64_t SH_FLD_CFG_OCC_DEADMAN_TIMER_SEL = 3262; // 8
+const static uint64_t SH_FLD_CFG_OCC_DEADMAN_TIMER_SEL_LEN = 3263; // 8
+const static uint64_t SH_FLD_CFG_OE_ALL_CKE_POWERED_DOWN = 3264; // 8
+const static uint64_t SH_FLD_CFG_OE_ALWAYS_ON = 3265; // 8
+const static uint64_t SH_FLD_CFG_OPT_RD_SIZE = 3266; // 8
+const static uint64_t SH_FLD_CFG_OPT_RD_SIZE_LEN = 3267; // 8
+const static uint64_t SH_FLD_CFG_PARITY_AFTER_CMD = 3268; // 8
+const static uint64_t SH_FLD_CFG_PARITY_DETECT_TIME = 3269; // 8
+const static uint64_t SH_FLD_CFG_PARITY_DETECT_TIME_LEN = 3270; // 8
+const static uint64_t SH_FLD_CFG_PARSE_PULL_RR_SEL = 3271; // 1
+const static uint64_t SH_FLD_CFG_PARSE_PULL_RR_SEL_LEN = 3272; // 1
+const static uint64_t SH_FLD_CFG_PARSE_PUSH_RR_SEL = 3273; // 1
+const static uint64_t SH_FLD_CFG_PARSE_PUSH_RR_SEL_LEN = 3274; // 1
+const static uint64_t SH_FLD_CFG_PARSE_QUERY_RR_SEL = 3275; // 1
+const static uint64_t SH_FLD_CFG_PARSE_QUERY_RR_SEL_LEN = 3276; // 1
+const static uint64_t SH_FLD_CFG_PAUSE_MCB_ERROR = 3277; // 2
+const static uint64_t SH_FLD_CFG_PAUSE_MCB_LOG_FULL = 3278; // 2
+const static uint64_t SH_FLD_CFG_PAUSE_ON_AUE = 3279; // 2
+const static uint64_t SH_FLD_CFG_PAUSE_ON_ERROR_MODE = 3280; // 2
+const static uint64_t SH_FLD_CFG_PAUSE_ON_ERROR_MODE_LEN = 3281; // 2
+const static uint64_t SH_FLD_CFG_PAUSE_ON_MCE = 3282; // 2
+const static uint64_t SH_FLD_CFG_PAUSE_ON_MPE = 3283; // 2
+const static uint64_t SH_FLD_CFG_PAUSE_ON_RCD = 3284; // 2
+const static uint64_t SH_FLD_CFG_PAUSE_ON_SCE = 3285; // 2
+const static uint64_t SH_FLD_CFG_PAUSE_ON_SUE = 3286; // 2
+const static uint64_t SH_FLD_CFG_PAUSE_ON_UE = 3287; // 2
+const static uint64_t SH_FLD_CFG_PCMD_PRIO_DONE = 3288; // 1
+const static uint64_t SH_FLD_CFG_PCMD_PRIO_DONE_LEN = 3289; // 1
+const static uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_RSP = 3290; // 1
+const static uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_RSP_LEN = 3291; // 1
+const static uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_SET = 3292; // 1
+const static uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_SET_LEN = 3293; // 1
+const static uint64_t SH_FLD_CFG_PCMD_PRIO_RR = 3294; // 1
+const static uint64_t SH_FLD_CFG_PCMD_PRIO_RR_LEN = 3295; // 1
+const static uint64_t SH_FLD_CFG_PDN_PUP = 3296; // 8
+const static uint64_t SH_FLD_CFG_PDN_PUP_LEN = 3297; // 8
+const static uint64_t SH_FLD_CFG_PERFMON_INFO_SRC_ED_SEL = 3298; // 12
+const static uint64_t SH_FLD_CFG_PER_BANK_REFRESH = 3299; // 8
+const static uint64_t SH_FLD_CFG_PM_DISABLE = 3300; // 43
+const static uint64_t SH_FLD_CFG_PM_MUX_DISABLE = 3301; // 43
+const static uint64_t SH_FLD_CFG_PRECHARGE_WAIT_TIME = 3302; // 8
+const static uint64_t SH_FLD_CFG_PRECHARGE_WAIT_TIME_LEN = 3303; // 8
+const static uint64_t SH_FLD_CFG_PRIO_LSI = 3304; // 1
+const static uint64_t SH_FLD_CFG_PRIO_LSI_LEN = 3305; // 1
+const static uint64_t SH_FLD_CFG_PRIO_MMIO = 3306; // 1
+const static uint64_t SH_FLD_CFG_PRIO_MMIO_LEN = 3307; // 1
+const static uint64_t SH_FLD_CFG_PRIO_PULL = 3308; // 1
+const static uint64_t SH_FLD_CFG_PRIO_PULL_LEN = 3309; // 1
+const static uint64_t SH_FLD_CFG_PRIO_PUSH_ARX = 3310; // 1
+const static uint64_t SH_FLD_CFG_PRIO_PUSH_ARX_LEN = 3311; // 1
+const static uint64_t SH_FLD_CFG_PRIO_PUSH_LCL = 3312; // 1
+const static uint64_t SH_FLD_CFG_PRIO_PUSH_LCL_LEN = 3313; // 1
+const static uint64_t SH_FLD_CFG_PRIO_RR = 3314; // 2
+const static uint64_t SH_FLD_CFG_PRIO_RR_LEN = 3315; // 2
+const static uint64_t SH_FLD_CFG_PRIO_RSVD = 3316; // 1
+const static uint64_t SH_FLD_CFG_PRIO_RSVD_LEN = 3317; // 1
+const static uint64_t SH_FLD_CFG_PRIO_VRQ_REQ = 3318; // 1
+const static uint64_t SH_FLD_CFG_PRIO_VRQ_REQ_LEN = 3319; // 1
+const static uint64_t SH_FLD_CFG_PRIO_VRQ_RSP = 3320; // 1
+const static uint64_t SH_FLD_CFG_PRIO_VRQ_RSP_LEN = 3321; // 1
+const static uint64_t SH_FLD_CFG_PULL_RSVD = 3322; // 1
+const static uint64_t SH_FLD_CFG_PULL_RSVD_LEN = 3323; // 1
+const static uint64_t SH_FLD_CFG_PUMP = 3324; // 1
+const static uint64_t SH_FLD_CFG_PUMP_MODE = 3325; // 1
+const static uint64_t SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_ENABLE = 3326; // 8
+const static uint64_t SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME = 3327; // 8
+const static uint64_t SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME_LEN = 3328; // 8
+const static uint64_t SH_FLD_CFG_PUP_ALL_WRITES_PENDING = 3329; // 8
+const static uint64_t SH_FLD_CFG_PUP_AVAIL = 3330; // 8
+const static uint64_t SH_FLD_CFG_PUP_AVAIL_LEN = 3331; // 8
+const static uint64_t SH_FLD_CFG_PUP_PDN = 3332; // 8
+const static uint64_t SH_FLD_CFG_PUP_PDN_LEN = 3333; // 8
+const static uint64_t SH_FLD_CFG_PUSH_ARX_RSVD = 3334; // 1
+const static uint64_t SH_FLD_CFG_PUSH_ARX_RSVD_LEN = 3335; // 1
+const static uint64_t SH_FLD_CFG_QUEUE_ECC_CORR_EN = 3336; // 1
+const static uint64_t SH_FLD_CFG_QUEUE_SIZE_PULL = 3337; // 1
+const static uint64_t SH_FLD_CFG_QUEUE_SIZE_PULL_LEN = 3338; // 1
+const static uint64_t SH_FLD_CFG_QUEUE_SIZE_PUSH_LCL = 3339; // 1
+const static uint64_t SH_FLD_CFG_QUEUE_SIZE_PUSH_LCL_LEN = 3340; // 1
+const static uint64_t SH_FLD_CFG_Q_BIT_TID_MASK = 3341; // 12
+const static uint64_t SH_FLD_CFG_Q_BIT_TID_MASK_LEN = 3342; // 12
+const static uint64_t SH_FLD_CFG_RANDCMD_WGT = 3343; // 2
+const static uint64_t SH_FLD_CFG_RANDCMD_WGT_LEN = 3344; // 2
+const static uint64_t SH_FLD_CFG_RANDGAP_WGT = 3345; // 2
+const static uint64_t SH_FLD_CFG_RANDGAP_WGT_LEN = 3346; // 2
+const static uint64_t SH_FLD_CFG_RANDOM_EN = 3347; // 12
+const static uint64_t SH_FLD_CFG_RANK0_RD_ODT = 3348; // 8
+const static uint64_t SH_FLD_CFG_RANK0_RD_ODT_LEN = 3349; // 8
+const static uint64_t SH_FLD_CFG_RANK0_WR_ODT = 3350; // 8
+const static uint64_t SH_FLD_CFG_RANK0_WR_ODT_LEN = 3351; // 8
+const static uint64_t SH_FLD_CFG_RANK1_RD_ODT = 3352; // 8
+const static uint64_t SH_FLD_CFG_RANK1_RD_ODT_LEN = 3353; // 8
+const static uint64_t SH_FLD_CFG_RANK1_WR_ODT = 3354; // 8
+const static uint64_t SH_FLD_CFG_RANK1_WR_ODT_LEN = 3355; // 8
+const static uint64_t SH_FLD_CFG_RANK2_RD_ODT = 3356; // 8
+const static uint64_t SH_FLD_CFG_RANK2_RD_ODT_LEN = 3357; // 8
+const static uint64_t SH_FLD_CFG_RANK2_WR_ODT = 3358; // 8
+const static uint64_t SH_FLD_CFG_RANK2_WR_ODT_LEN = 3359; // 8
+const static uint64_t SH_FLD_CFG_RANK3_RD_ODT = 3360; // 8
+const static uint64_t SH_FLD_CFG_RANK3_RD_ODT_LEN = 3361; // 8
+const static uint64_t SH_FLD_CFG_RANK3_WR_ODT = 3362; // 8
+const static uint64_t SH_FLD_CFG_RANK3_WR_ODT_LEN = 3363; // 8
+const static uint64_t SH_FLD_CFG_RANK4_RD_ODT = 3364; // 8
+const static uint64_t SH_FLD_CFG_RANK4_RD_ODT_LEN = 3365; // 8
+const static uint64_t SH_FLD_CFG_RANK4_WR_ODT = 3366; // 8
+const static uint64_t SH_FLD_CFG_RANK4_WR_ODT_LEN = 3367; // 8
+const static uint64_t SH_FLD_CFG_RANK5_RD_ODT = 3368; // 8
+const static uint64_t SH_FLD_CFG_RANK5_RD_ODT_LEN = 3369; // 8
+const static uint64_t SH_FLD_CFG_RANK5_WR_ODT = 3370; // 8
+const static uint64_t SH_FLD_CFG_RANK5_WR_ODT_LEN = 3371; // 8
+const static uint64_t SH_FLD_CFG_RANK6_RD_ODT = 3372; // 8
+const static uint64_t SH_FLD_CFG_RANK6_RD_ODT_LEN = 3373; // 8
+const static uint64_t SH_FLD_CFG_RANK6_WR_ODT = 3374; // 8
+const static uint64_t SH_FLD_CFG_RANK6_WR_ODT_LEN = 3375; // 8
+const static uint64_t SH_FLD_CFG_RANK7_RD_ODT = 3376; // 8
+const static uint64_t SH_FLD_CFG_RANK7_RD_ODT_LEN = 3377; // 8
+const static uint64_t SH_FLD_CFG_RANK7_WR_ODT = 3378; // 8
+const static uint64_t SH_FLD_CFG_RANK7_WR_ODT_LEN = 3379; // 8
+const static uint64_t SH_FLD_CFG_RCD_PROTECTION_TIME = 3380; // 8
+const static uint64_t SH_FLD_CFG_RCD_PROTECTION_TIME_LEN = 3381; // 8
+const static uint64_t SH_FLD_CFG_RC_FRC_DISP_EQ_NTM_INIG_SI_TO_RCR_EN =
+    3382; // 12
+const static uint64_t SH_FLD_CFG_RD2PRE = 3383; // 8
+const static uint64_t SH_FLD_CFG_RD2PRE_LEN = 3384; // 8
+const static uint64_t SH_FLD_CFG_RDBUFF_CAPACITY_LIMIT = 3385; // 8
+const static uint64_t SH_FLD_CFG_RDBUFF_CAPACITY_LIMIT_LEN = 3386; // 8
+const static uint64_t SH_FLD_CFG_RDCLK_SYSCLK_LENGTH = 3387; // 8
+const static uint64_t SH_FLD_CFG_RDCLK_SYSCLK_LENGTH_LEN = 3388; // 8
+const static uint64_t SH_FLD_CFG_RDCLK_SYSCLK_TB = 3389; // 8
+const static uint64_t SH_FLD_CFG_RDCLK_SYSCLK_TB_LEN = 3390; // 8
+const static uint64_t SH_FLD_CFG_RDTAG_DLY = 3391; // 8
+const static uint64_t SH_FLD_CFG_RDTAG_DLY_LEN = 3392; // 8
+const static uint64_t SH_FLD_CFG_RDTAG_MBX_CYCLE = 3393; // 8
+const static uint64_t SH_FLD_CFG_RD_IDLE_ALLOW_WR = 3394; // 8
+const static uint64_t SH_FLD_CFG_RD_IDLE_ALLOW_WR_LEN = 3395; // 8
+const static uint64_t SH_FLD_CFG_REFRESH_ENABLE = 3396; // 8
+const static uint64_t SH_FLD_CFG_REFRESH_HP_RANK_BLOCK_ENABLE = 3397; // 8
+const static uint64_t SH_FLD_CFG_REFRESH_INTERVAL = 3398; // 8
+const static uint64_t SH_FLD_CFG_REFRESH_INTERVAL_LEN = 3399; // 8
+const static uint64_t SH_FLD_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT = 3400; // 8
+const static uint64_t SH_FLD_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT_LEN =
+    3401; // 8
+const static uint64_t SH_FLD_CFG_REFRESH_PRIORITY_THRESHOLD = 3402; // 8
+const static uint64_t SH_FLD_CFG_REFRESH_PRIORITY_THRESHOLD_LEN = 3403; // 8
+const static uint64_t SH_FLD_CFG_REFRESH_RESET_INTERVAL = 3404; // 8
+const static uint64_t SH_FLD_CFG_REFRESH_RESET_INTERVAL_LEN = 3405; // 8
+const static uint64_t SH_FLD_CFG_REFR_CHECK_INTERVAL = 3406; // 8
+const static uint64_t SH_FLD_CFG_REFR_CHECK_INTERVAL_LEN = 3407; // 8
+const static uint64_t SH_FLD_CFG_REFR_TSV_STACK = 3408; // 8
+const static uint64_t SH_FLD_CFG_REFR_TSV_STACK_LEN = 3409; // 8
+const static uint64_t SH_FLD_CFG_REF_BLOCK_STOP_DLY = 3410; // 8
+const static uint64_t SH_FLD_CFG_REF_BLOCK_STOP_DLY_LEN = 3411; // 8
+const static uint64_t SH_FLD_CFG_RMWBUFF_CAPACITY_LIMIT = 3412; // 8
+const static uint64_t SH_FLD_CFG_RMWBUFF_CAPACITY_LIMIT_LEN = 3413; // 8
+const static uint64_t SH_FLD_CFG_RODT_BC4_END_DLY = 3414; // 8
+const static uint64_t SH_FLD_CFG_RODT_BC4_END_DLY_LEN = 3415; // 8
+const static uint64_t SH_FLD_CFG_RODT_END_DLY = 3416; // 8
+const static uint64_t SH_FLD_CFG_RODT_END_DLY_LEN = 3417; // 8
+const static uint64_t SH_FLD_CFG_RODT_START_DLY = 3418; // 8
+const static uint64_t SH_FLD_CFG_RODT_START_DLY_LEN = 3419; // 8
+const static uint64_t SH_FLD_CFG_RQ_HANG_THRESHOLD = 3420; // 8
+const static uint64_t SH_FLD_CFG_RQ_HANG_THRESHOLD_LEN = 3421; // 8
+const static uint64_t SH_FLD_CFG_RRQ_ACT_NUM_READS_PENDING = 3422; // 8
+const static uint64_t SH_FLD_CFG_RRQ_ACT_NUM_READS_PENDING_LEN = 3423; // 8
+const static uint64_t SH_FLD_CFG_RRQ_DEPTH = 3424; // 8
+const static uint64_t SH_FLD_CFG_RRQ_DEPTH_LEN = 3425; // 8
+const static uint64_t SH_FLD_CFG_RRQ_REORDER_DEPTH = 3426; // 8
+const static uint64_t SH_FLD_CFG_RRQ_REORDER_DEPTH_LEN = 3427; // 8
+const static uint64_t SH_FLD_CFG_RRQ_SKIP_LIMIT = 3428; // 8
+const static uint64_t SH_FLD_CFG_RRQ_SKIP_LIMIT_LEN = 3429; // 8
+const static uint64_t SH_FLD_CFG_RSV0 = 3430; // 8
+const static uint64_t SH_FLD_CFG_RSV0_LEN = 3431; // 8
+const static uint64_t SH_FLD_CFG_RUNTIME_CTR = 3432; // 2
+const static uint64_t SH_FLD_CFG_RUNTIME_CTR_LEN = 3433; // 2
+const static uint64_t SH_FLD_CFG_RUNTIME_MCBALL = 3434; // 2
+const static uint64_t SH_FLD_CFG_RUNTIME_OVERHEAD = 3435; // 2
+const static uint64_t SH_FLD_CFG_RUNTIME_SUBTEST = 3436; // 2
+const static uint64_t SH_FLD_CFG_RUNTIME_SUBTEST_LEN = 3437; // 2
+const static uint64_t SH_FLD_CFG_SAFE_REFRESH_INTERVAL = 3438; // 8
+const static uint64_t SH_FLD_CFG_SAFE_REFRESH_INTERVAL_LEN = 3439; // 8
+const static uint64_t SH_FLD_CFG_SIM_FAST_NOISE_WINDOW = 3440; // 8
+const static uint64_t SH_FLD_CFG_SINGLE_MEM = 3441; // 12
+const static uint64_t SH_FLD_CFG_SINGLE_MEM_EN = 3442; // 12
+const static uint64_t SH_FLD_CFG_SINGLE_MEM_LEN = 3443; // 12
+const static uint64_t SH_FLD_CFG_SLOT0_S0_CID = 3444; // 8
+const static uint64_t SH_FLD_CFG_SLOT0_S0_CID_LEN = 3445; // 8
+const static uint64_t SH_FLD_CFG_SLOT0_S1_CID = 3446; // 8
+const static uint64_t SH_FLD_CFG_SLOT0_S1_CID_LEN = 3447; // 8
+const static uint64_t SH_FLD_CFG_SLOT0_S2_CID = 3448; // 8
+const static uint64_t SH_FLD_CFG_SLOT0_S2_CID_LEN = 3449; // 8
+const static uint64_t SH_FLD_CFG_SLOT0_S3_CID = 3450; // 8
+const static uint64_t SH_FLD_CFG_SLOT0_S3_CID_LEN = 3451; // 8
+const static uint64_t SH_FLD_CFG_SLOT0_S4_CID = 3452; // 8
+const static uint64_t SH_FLD_CFG_SLOT0_S4_CID_LEN = 3453; // 8
+const static uint64_t SH_FLD_CFG_SLOT0_S5_CID = 3454; // 8
+const static uint64_t SH_FLD_CFG_SLOT0_S5_CID_LEN = 3455; // 8
+const static uint64_t SH_FLD_CFG_SLOT0_S6_CID = 3456; // 8
+const static uint64_t SH_FLD_CFG_SLOT0_S6_CID_LEN = 3457; // 8
+const static uint64_t SH_FLD_CFG_SLOT0_S7_CID = 3458; // 8
+const static uint64_t SH_FLD_CFG_SLOT0_S7_CID_LEN = 3459; // 8
+const static uint64_t SH_FLD_CFG_SLOT1_S0_CID = 3460; // 8
+const static uint64_t SH_FLD_CFG_SLOT1_S0_CID_LEN = 3461; // 8
+const static uint64_t SH_FLD_CFG_SLOT1_S1_CID = 3462; // 8
+const static uint64_t SH_FLD_CFG_SLOT1_S1_CID_LEN = 3463; // 8
+const static uint64_t SH_FLD_CFG_SLOT1_S2_CID = 3464; // 8
+const static uint64_t SH_FLD_CFG_SLOT1_S2_CID_LEN = 3465; // 8
+const static uint64_t SH_FLD_CFG_SLOT1_S3_CID = 3466; // 8
+const static uint64_t SH_FLD_CFG_SLOT1_S3_CID_LEN = 3467; // 8
+const static uint64_t SH_FLD_CFG_SLOT1_S4_CID = 3468; // 8
+const static uint64_t SH_FLD_CFG_SLOT1_S4_CID_LEN = 3469; // 8
+const static uint64_t SH_FLD_CFG_SLOT1_S5_CID = 3470; // 8
+const static uint64_t SH_FLD_CFG_SLOT1_S5_CID_LEN = 3471; // 8
+const static uint64_t SH_FLD_CFG_SLOT1_S6_CID = 3472; // 8
+const static uint64_t SH_FLD_CFG_SLOT1_S6_CID_LEN = 3473; // 8
+const static uint64_t SH_FLD_CFG_SLOT1_S7_CID = 3474; // 8
+const static uint64_t SH_FLD_CFG_SLOT1_S7_CID_LEN = 3475; // 8
+const static uint64_t SH_FLD_CFG_STALL = 3476; // 1
+const static uint64_t SH_FLD_CFG_START_ADDR_0 = 3477; // 2
+const static uint64_t SH_FLD_CFG_START_ADDR_0_LEN = 3478; // 2
+const static uint64_t SH_FLD_CFG_START_ADDR_1 = 3479; // 2
+const static uint64_t SH_FLD_CFG_START_ADDR_1_LEN = 3480; // 2
+const static uint64_t SH_FLD_CFG_START_ADDR_2 = 3481; // 2
+const static uint64_t SH_FLD_CFG_START_ADDR_2_LEN = 3482; // 2
+const static uint64_t SH_FLD_CFG_START_ADDR_3 = 3483; // 2
+const static uint64_t SH_FLD_CFG_START_ADDR_3_LEN = 3484; // 2
+const static uint64_t SH_FLD_CFG_STATIC_IDLE_DLY = 3485; // 8
+const static uint64_t SH_FLD_CFG_STATIC_IDLE_DLY_LEN = 3486; // 8
+const static uint64_t SH_FLD_CFG_STOP_HANG_CNT_SYS_XSTP = 3487; // 43
+const static uint64_t SH_FLD_CFG_STQ_PF_EN = 3488; // 12
+const static uint64_t SH_FLD_CFG_STR_ENABLE = 3489; // 8
+const static uint64_t SH_FLD_CFG_STR_STATE = 3490; // 8
+const static uint64_t SH_FLD_CFG_SYMBOL_COUNTER_MODE = 3491; // 2
+const static uint64_t SH_FLD_CFG_SYMBOL_COUNTER_MODE_LEN = 3492; // 2
+const static uint64_t SH_FLD_CFG_SYSMAP_SM_NOT_LG_SEL = 3493; // 12
+const static uint64_t SH_FLD_CFG_TCKESR = 3494; // 8
+const static uint64_t SH_FLD_CFG_TCKESR_LEN = 3495; // 8
+const static uint64_t SH_FLD_CFG_TCKSRE = 3496; // 8
+const static uint64_t SH_FLD_CFG_TCKSRE_LEN = 3497; // 8
+const static uint64_t SH_FLD_CFG_TCKSRX = 3498; // 8
+const static uint64_t SH_FLD_CFG_TCKSRX_LEN = 3499; // 8
+const static uint64_t SH_FLD_CFG_TFAW = 3500; // 8
+const static uint64_t SH_FLD_CFG_TFAW_LEN = 3501; // 8
+const static uint64_t SH_FLD_CFG_THRESH_MAG_ICE = 3502; // 2
+const static uint64_t SH_FLD_CFG_THRESH_MAG_ICE_LEN = 3503; // 2
+const static uint64_t SH_FLD_CFG_THRESH_MAG_MCE_HARD = 3504; // 2
+const static uint64_t SH_FLD_CFG_THRESH_MAG_MCE_HARD_LEN = 3505; // 2
+const static uint64_t SH_FLD_CFG_THRESH_MAG_MCE_INT = 3506; // 2
+const static uint64_t SH_FLD_CFG_THRESH_MAG_MCE_INT_LEN = 3507; // 2
+const static uint64_t SH_FLD_CFG_THRESH_MAG_MCE_SOFT = 3508; // 2
+const static uint64_t SH_FLD_CFG_THRESH_MAG_MCE_SOFT_LEN = 3509; // 2
+const static uint64_t SH_FLD_CFG_THRESH_MAG_NCE_HARD = 3510; // 2
+const static uint64_t SH_FLD_CFG_THRESH_MAG_NCE_HARD_LEN = 3511; // 2
+const static uint64_t SH_FLD_CFG_THRESH_MAG_NCE_INT = 3512; // 2
+const static uint64_t SH_FLD_CFG_THRESH_MAG_NCE_INT_LEN = 3513; // 2
+const static uint64_t SH_FLD_CFG_THRESH_MAG_NCE_SOFT = 3514; // 2
+const static uint64_t SH_FLD_CFG_THRESH_MAG_NCE_SOFT_LEN = 3515; // 2
+const static uint64_t SH_FLD_CFG_THRESH_MAG_RCE = 3516; // 2
+const static uint64_t SH_FLD_CFG_THRESH_MAG_RCE_LEN = 3517; // 2
+const static uint64_t SH_FLD_CFG_TIME_BASE_TMR0 = 3518; // 8
+const static uint64_t SH_FLD_CFG_TIME_BASE_TMR0_LEN = 3519; // 8
+const static uint64_t SH_FLD_CFG_TIME_BASE_TMR1 = 3520; // 8
+const static uint64_t SH_FLD_CFG_TIME_BASE_TMR1_LEN = 3521; // 8
+const static uint64_t SH_FLD_CFG_TIME_BASE_TMR2 = 3522; // 8
+const static uint64_t SH_FLD_CFG_TIME_BASE_TMR2_LEN = 3523; // 8
+const static uint64_t SH_FLD_CFG_TRAS = 3524; // 8
+const static uint64_t SH_FLD_CFG_TRAS_LEN = 3525; // 8
+const static uint64_t SH_FLD_CFG_TRCD = 3526; // 8
+const static uint64_t SH_FLD_CFG_TRCD_LEN = 3527; // 8
+const static uint64_t SH_FLD_CFG_TRFC = 3528; // 8
+const static uint64_t SH_FLD_CFG_TRFC_COUNTER_DIS = 3529; // 8
+const static uint64_t SH_FLD_CFG_TRFC_COUNTER_DIS_LEN = 3530; // 8
+const static uint64_t SH_FLD_CFG_TRFC_LEN = 3531; // 8
+const static uint64_t SH_FLD_CFG_TRFC_STACK_GATE_ALL_REF = 3532; // 8
+const static uint64_t SH_FLD_CFG_TRP = 3533; // 8
+const static uint64_t SH_FLD_CFG_TRP_LEN = 3534; // 8
+const static uint64_t SH_FLD_CFG_TXSDLL = 3535; // 8
+const static uint64_t SH_FLD_CFG_TXSDLL_LEN = 3536; // 8
+const static uint64_t SH_FLD_CFG_VPC_PULL_LMIT = 3537; // 1
+const static uint64_t SH_FLD_CFG_VPC_PULL_LMIT_LEN = 3538; // 1
+const static uint64_t SH_FLD_CFG_VPC_PUSH_ARX_LMIT = 3539; // 1
+const static uint64_t SH_FLD_CFG_VPC_PUSH_ARX_LMIT_LEN = 3540; // 1
+const static uint64_t SH_FLD_CFG_VPC_PUSH_LCL_LMIT = 3541; // 1
+const static uint64_t SH_FLD_CFG_VPC_PUSH_LCL_LMIT_LEN = 3542; // 1
+const static uint64_t SH_FLD_CFG_VPC_PUSH_LCL_RSVD = 3543; // 1
+const static uint64_t SH_FLD_CFG_VPC_PUSH_LCL_RSVD_LEN = 3544; // 1
+const static uint64_t SH_FLD_CFG_WDF_SERIAL_SEQ_MODE = 3545; // 8
+const static uint64_t SH_FLD_CFG_WODT_BC4_END_DLY = 3546; // 8
+const static uint64_t SH_FLD_CFG_WODT_BC4_END_DLY_LEN = 3547; // 8
+const static uint64_t SH_FLD_CFG_WODT_END_DLY = 3548; // 8
+const static uint64_t SH_FLD_CFG_WODT_END_DLY_LEN = 3549; // 8
+const static uint64_t SH_FLD_CFG_WODT_START_DLY = 3550; // 8
+const static uint64_t SH_FLD_CFG_WODT_START_DLY_LEN = 3551; // 8
+const static uint64_t SH_FLD_CFG_WR2PRE = 3552; // 8
+const static uint64_t SH_FLD_CFG_WR2PRE_LEN = 3553; // 8
+const static uint64_t SH_FLD_CFG_WRDATA_DLY = 3554; // 8
+const static uint64_t SH_FLD_CFG_WRDATA_DLY_LEN = 3555; // 8
+const static uint64_t SH_FLD_CFG_WRDONE_DLY = 3556; // 8
+const static uint64_t SH_FLD_CFG_WRDONE_DLY_LEN = 3557; // 8
+const static uint64_t SH_FLD_CFG_WRITE_HW_MARK = 3558; // 8
+const static uint64_t SH_FLD_CFG_WRITE_HW_MARK_LEN = 3559; // 8
+const static uint64_t SH_FLD_CFG_WRITE_LW_MARK = 3560; // 8
+const static uint64_t SH_FLD_CFG_WRITE_LW_MARK_LEN = 3561; // 8
+const static uint64_t SH_FLD_CFG_WRITE_MODE_ECC_CHK_DIS = 3562; // 16
+const static uint64_t SH_FLD_CFG_WRITE_MODE_ECC_COR_DIS = 3563; // 16
+const static uint64_t SH_FLD_CFG_WRQ_ACT_NUM_WRITES_PENDING = 3564; // 8
+const static uint64_t SH_FLD_CFG_WRQ_ACT_NUM_WRITES_PENDING_LEN = 3565; // 8
+const static uint64_t SH_FLD_CFG_WRQ_DEPTH = 3566; // 8
+const static uint64_t SH_FLD_CFG_WRQ_DEPTH_LEN = 3567; // 8
+const static uint64_t SH_FLD_CFG_WRQ_ENABLE_NON_HP_WR = 3568; // 8
+const static uint64_t SH_FLD_CFG_WRQ_ENTRY0_HP_DLY = 3569; // 8
+const static uint64_t SH_FLD_CFG_WRQ_ENTRY0_HP_DLY_LEN = 3570; // 8
+const static uint64_t SH_FLD_CFG_WRQ_FIFO_MODE = 3571; // 8
+const static uint64_t SH_FLD_CFG_WRQ_FLUSH_WR_RANK = 3572; // 8
+const static uint64_t SH_FLD_CFG_WRQ_FRC_ST_RD_HIT_WR = 3573; // 8
+const static uint64_t SH_FLD_CFG_WRQ_SKIP_LIMIT = 3574; // 8
+const static uint64_t SH_FLD_CFG_WRQ_SKIP_LIMIT_LEN = 3575; // 8
+const static uint64_t SH_FLD_CGC = 3576; // 24
+const static uint64_t SH_FLD_CGC_LEN = 3577; // 24
+const static uint64_t SH_FLD_CH0 = 3578; // 2
+const static uint64_t SH_FLD_CH0EFT_ACTION = 3579; // 1
+const static uint64_t SH_FLD_CH0EFT_ENA = 3580; // 1
+const static uint64_t SH_FLD_CH0EFT_SELECT = 3581; // 1
+const static uint64_t SH_FLD_CH0EFT_SELECT_LEN = 3582; // 1
+const static uint64_t SH_FLD_CH0EFT_TYPE = 3583; // 1
+const static uint64_t SH_FLD_CH0_842_ECC_CE = 3584; // 1
+const static uint64_t SH_FLD_CH0_842_ECC_UE = 3585; // 1
+const static uint64_t SH_FLD_CH0_CMD_CREDITS_0_5 = 3586; // 1
+const static uint64_t SH_FLD_CH0_CMD_CREDITS_0_5_LEN = 3587; // 1
+const static uint64_t SH_FLD_CH0_EFT = 3588; // 1
+const static uint64_t SH_FLD_CH0_INVALID_STATE = 3589; // 1
+const static uint64_t SH_FLD_CH0_LEN = 3590; // 2
+const static uint64_t SH_FLD_CH0_REF_DIV = 3591; // 1
+const static uint64_t SH_FLD_CH0_REF_DIV_LEN = 3592; // 1
+const static uint64_t SH_FLD_CH0_TIMER_ENBL = 3593; // 1
+const static uint64_t SH_FLD_CH1 = 3594; // 2
+const static uint64_t SH_FLD_CH1EFT_ACTION = 3595; // 1
+const static uint64_t SH_FLD_CH1EFT_ENA = 3596; // 1
+const static uint64_t SH_FLD_CH1EFT_SELECT = 3597; // 1
+const static uint64_t SH_FLD_CH1EFT_SELECT_LEN = 3598; // 1
+const static uint64_t SH_FLD_CH1EFT_TYPE = 3599; // 1
+const static uint64_t SH_FLD_CH1_842_ECC_CE = 3600; // 1
+const static uint64_t SH_FLD_CH1_842_ECC_UE = 3601; // 1
+const static uint64_t SH_FLD_CH1_CMD_CREDITS_0_5 = 3602; // 1
+const static uint64_t SH_FLD_CH1_CMD_CREDITS_0_5_LEN = 3603; // 1
+const static uint64_t SH_FLD_CH1_DAT_CREDITS_0_5 = 3604; // 1
+const static uint64_t SH_FLD_CH1_DAT_CREDITS_0_5_LEN = 3605; // 1
+const static uint64_t SH_FLD_CH1_EFT = 3606; // 1
+const static uint64_t SH_FLD_CH1_INVALID_STATE = 3607; // 1
+const static uint64_t SH_FLD_CH1_LEN = 3608; // 2
+const static uint64_t SH_FLD_CH1_REF_DIV = 3609; // 1
+const static uint64_t SH_FLD_CH1_REF_DIV_LEN = 3610; // 1
+const static uint64_t SH_FLD_CH1_TIMER_ENBL = 3611; // 1
+const static uint64_t SH_FLD_CH2 = 3612; // 2
+const static uint64_t SH_FLD_CH2_CMD_CREDITS_PC_0_5 = 3613; // 1
+const static uint64_t SH_FLD_CH2_CMD_CREDITS_PC_0_5_LEN = 3614; // 1
+const static uint64_t SH_FLD_CH2_CMD_CREDITS_VC_0_5 = 3615; // 1
+const static uint64_t SH_FLD_CH2_CMD_CREDITS_VC_0_5_LEN = 3616; // 1
+const static uint64_t SH_FLD_CH2_INVALID_STATE = 3617; // 1
+const static uint64_t SH_FLD_CH2_LEN = 3618; // 2
+const static uint64_t SH_FLD_CH2_REF_DIV = 3619; // 1
+const static uint64_t SH_FLD_CH2_REF_DIV_LEN = 3620; // 1
+const static uint64_t SH_FLD_CH2_SYM = 3621; // 1
+const static uint64_t SH_FLD_CH2_TIMER_ENBL = 3622; // 1
+const static uint64_t SH_FLD_CH3 = 3623; // 2
+const static uint64_t SH_FLD_CH3_INVALID_STATE = 3624; // 1
+const static uint64_t SH_FLD_CH3_LEN = 3625; // 2
+const static uint64_t SH_FLD_CH3_REF_DIV = 3626; // 1
+const static uint64_t SH_FLD_CH3_REF_DIV_LEN = 3627; // 1
+const static uint64_t SH_FLD_CH3_SYM = 3628; // 1
+const static uint64_t SH_FLD_CH3_TIMER_ENBL = 3629; // 1
+const static uint64_t SH_FLD_CH4GZIP_ACTION = 3630; // 1
+const static uint64_t SH_FLD_CH4GZIP_ENA = 3631; // 1
+const static uint64_t SH_FLD_CH4GZIP_SELECT = 3632; // 1
+const static uint64_t SH_FLD_CH4GZIP_SELECT_LEN = 3633; // 1
+const static uint64_t SH_FLD_CH4GZIP_TYPE = 3634; // 1
+const static uint64_t SH_FLD_CH4_AMF_ECC_CE = 3635; // 1
+const static uint64_t SH_FLD_CH4_AMF_ECC_UE = 3636; // 1
+const static uint64_t SH_FLD_CH4_GZIP = 3637; // 1
+const static uint64_t SH_FLD_CH4_INVALID_STATE = 3638; // 1
+const static uint64_t SH_FLD_CH4_REF_DIV = 3639; // 1
+const static uint64_t SH_FLD_CH4_REF_DIV_LEN = 3640; // 1
+const static uint64_t SH_FLD_CH4_TIMER_ENBL = 3641; // 1
+const static uint64_t SH_FLD_CH5_AMF_ECC_CE = 3642; // 1
+const static uint64_t SH_FLD_CH5_AMF_ECC_UE = 3643; // 1
+const static uint64_t SH_FLD_CH5_INVALID_STATE = 3644; // 1
+const static uint64_t SH_FLD_CH6_AMF_ECC_CE = 3645; // 1
+const static uint64_t SH_FLD_CH6_AMF_ECC_UE = 3646; // 1
+const static uint64_t SH_FLD_CH6_INVALID_STATE = 3647; // 1
+const static uint64_t SH_FLD_CH7_AMF_ECC_CE = 3648; // 1
+const static uint64_t SH_FLD_CH7_AMF_ECC_UE = 3649; // 1
+const static uint64_t SH_FLD_CH7_INVALID_STATE = 3650; // 1
+const static uint64_t SH_FLD_CHANGE_IN_PROGRESS = 3651; // 2
+const static uint64_t SH_FLD_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION = 3652; // 4
+const static uint64_t SH_FLD_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION_LEN =
+    3653; // 4
+const static uint64_t SH_FLD_CHANNEL_0_TIMEOUT_ERROR = 3654; // 4
+const static uint64_t SH_FLD_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION = 3655; // 4
+const static uint64_t SH_FLD_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION_LEN =
+    3656; // 4
+const static uint64_t SH_FLD_CHANNEL_1_TIMEOUT_ERROR = 3657; // 4
+const static uint64_t SH_FLD_CHANNEL_SELECT = 3658; // 4
+const static uint64_t SH_FLD_CHANNEL_SELECT_LEN = 3659; // 4
+const static uint64_t SH_FLD_CHECKSTOP = 3660; // 1
+const static uint64_t SH_FLD_CHECK_CMDS = 3661; // 2
+const static uint64_t SH_FLD_CHECK_CMDS_EN = 3662; // 2
+const static uint64_t SH_FLD_CHECK_CMDS_LEN = 3663; // 2
+const static uint64_t SH_FLD_CHECK_STOP_GPE0 = 3664; // 1
+const static uint64_t SH_FLD_CHECK_STOP_GPE1 = 3665; // 1
+const static uint64_t SH_FLD_CHECK_STOP_GPE2 = 3666; // 1
+const static uint64_t SH_FLD_CHECK_STOP_GPE3 = 3667; // 1
+const static uint64_t SH_FLD_CHECK_STOP_PPC405 = 3668; // 1
+const static uint64_t SH_FLD_CHIPID = 3669; // 1
+const static uint64_t SH_FLD_CHIPID_LEN = 3670; // 1
+const static uint64_t SH_FLD_CHIPID_OVERRIDE = 3671; // 1
+const static uint64_t SH_FLD_CHIPLET_ATOMIC_LOCK = 3672; // 43
+const static uint64_t SH_FLD_CHIPLET_ENABLE = 3673; // 43
+const static uint64_t SH_FLD_CHIPLET_ERRORS = 3674; // 43
+const static uint64_t SH_FLD_CHIPLET_ERRORS_LEN = 3675; // 43
+const static uint64_t SH_FLD_CHIPLET_GRID_SKITTER = 3676; // 43
+const static uint64_t SH_FLD_CHIPLET_INTERRUPT_FROM_HOST = 3677; // 1
+const static uint64_t SH_FLD_CHIPLET_IS_ALIGNED = 3678; // 43
+const static uint64_t SH_FLD_CHIPLET_OFFLINE = 3679; // 43
+const static uint64_t SH_FLD_CHIPMARK = 3680; // 72
+const static uint64_t SH_FLD_CHIPMARK_LEN = 3681; // 72
+const static uint64_t SH_FLD_CHIP_INTERFACEMODE = 3682; // 2
+const static uint64_t SH_FLD_CHIP_PERSONALISATION = 3683; // 2
+const static uint64_t SH_FLD_CHIP_RESET = 3684; // 1
+const static uint64_t SH_FLD_CHIP_STATUS = 3685; // 194
+const static uint64_t SH_FLD_CHIP_STATUS_LEN = 3686; // 194
+const static uint64_t SH_FLD_CHIP_TOD_STATUS = 3687; // 98
+const static uint64_t SH_FLD_CHIP_TOD_STATUS_LEN = 3688; // 98
+const static uint64_t SH_FLD_CHKSW_ALLOW1_RD = 3689; // 1
+const static uint64_t SH_FLD_CHKSW_ALLOW1_RDWR = 3690; // 1
+const static uint64_t SH_FLD_CHKSW_ALLOW1_WR = 3691; // 1
+const static uint64_t SH_FLD_CHKSW_I2C_BUSY = 3692; // 1
+const static uint64_t SH_FLD_CHKSW_I2C_BUSY_0 = 3693; // 1
+const static uint64_t SH_FLD_CHKSW_I2C_BUSY_1 = 3694; // 1
+const static uint64_t SH_FLD_CHKSW_I2C_BUSY_2 = 3695; // 1
+const static uint64_t SH_FLD_CHKSW_I2C_BUSY_3 = 3696; // 1
+const static uint64_t SH_FLD_CHKSW_OCI_PARCHK_DIS = 3697; // 1
+const static uint64_t SH_FLD_CHKSW_SO_SPARE = 3698; // 1
+const static uint64_t SH_FLD_CHKSW_SO_SPARE_LEN = 3699; // 1
+const static uint64_t SH_FLD_CHKSW_SPARE_6 = 3700; // 1
+const static uint64_t SH_FLD_CHKSW_TANK_RDDATA_PARCHK_DIS = 3701; // 1
+const static uint64_t SH_FLD_CHKSW_VAL_BE_ADDR_CHK_DIS = 3702; // 1
+const static uint64_t SH_FLD_CHKSW_WRFSM_DLY_DIS = 3703; // 1
+const static uint64_t SH_FLD_CHOP1G = 3704; // 1
+const static uint64_t SH_FLD_CHSW_DIS_DATA_HANG = 3705; // 1
+const static uint64_t SH_FLD_CHSW_DIS_ECC_CHECK = 3706; // 1
+const static uint64_t SH_FLD_CHSW_DIS_GROUP_SCOPE = 3707; // 1
+const static uint64_t SH_FLD_CHSW_DIS_OCIABUSPAR_CHECK = 3708; // 1
+const static uint64_t SH_FLD_CHSW_DIS_OCIBEPAR_CHECK = 3709; // 1
+const static uint64_t SH_FLD_CHSW_DIS_OCIDATAPAR_CHECK = 3710; // 1
+const static uint64_t SH_FLD_CHSW_DIS_OCIDATAPAR_GEN = 3711; // 1
+const static uint64_t SH_FLD_CHSW_DIS_OPER_HANG = 3712; // 1
+const static uint64_t SH_FLD_CHSW_DIS_PB_PARITY_CHK = 3713; // 1
+const static uint64_t SH_FLD_CHSW_DIS_RETRY_BACKOFF = 3714; // 1
+const static uint64_t SH_FLD_CHSW_DIS_RTAG_PARITY_CHK = 3715; // 1
+const static uint64_t SH_FLD_CHSW_DIS_WRITE_MATCH_REARB = 3716; // 1
+const static uint64_t SH_FLD_CHSW_EXIT_ON_INVALID_CRESP = 3717; // 1
+const static uint64_t SH_FLD_CHSW_HANG_ON_ADRERROR = 3718; // 1
+const static uint64_t SH_FLD_CHSW_HANG_ON_DERROR = 3719; // 1
+const static uint64_t SH_FLD_CHSW_SKIP_GROUP_SCOPE = 3720; // 1
+const static uint64_t SH_FLD_CHSW_USE_CL_DMA_INJ = 3721; // 1
+const static uint64_t SH_FLD_CHSW_USE_PR_DMA_INJ = 3722; // 1
+const static uint64_t SH_FLD_CHTM_PURGE_C0 = 3723; // 12
+const static uint64_t SH_FLD_CHTM_PURGE_C1 = 3724; // 12
+const static uint64_t SH_FLD_CHTM_PURGE_DONE_C0 = 3725; // 24
+const static uint64_t SH_FLD_CHTM_PURGE_DONE_C1 = 3726; // 24
+const static uint64_t SH_FLD_CIABR_EN = 3727; // 24
+const static uint64_t SH_FLD_CI_BUFF_AVAIL = 3728; // 2
+const static uint64_t SH_FLD_CI_LOAD = 3729; // 1
+const static uint64_t SH_FLD_CI_LOAD_LEN = 3730; // 1
+const static uint64_t SH_FLD_CI_MACHINE_HANG_ERR = 3731; // 12
+const static uint64_t SH_FLD_CI_READ = 3732; // 1
+const static uint64_t SH_FLD_CI_STORE = 3733; // 1
+const static uint64_t SH_FLD_CI_STORE_BUFFER_THRESHOLD = 3734; // 2
+const static uint64_t SH_FLD_CI_STORE_BUFFER_THRESHOLD_LEN = 3735; // 2
+const static uint64_t SH_FLD_CI_STORE_LEN = 3736; // 1
+const static uint64_t SH_FLD_CI_WRITE = 3737; // 1
+const static uint64_t SH_FLD_CKINSM_DIS = 3738; // 1
+const static uint64_t SH_FLD_CKINSM_DIS_LEN = 3739; // 1
+const static uint64_t SH_FLD_CLEAR = 3740; // 1
+const static uint64_t SH_FLD_CLEAR_CHIPLET_IS_ALIGNED = 3741; // 43
+const static uint64_t SH_FLD_CLKGLM_ASYNC_RESET = 3742; // 30
+const static uint64_t SH_FLD_CLKGLM_DIRECT_VALUE = 3743; // 30
+const static uint64_t SH_FLD_CLKGLM_SEL = 3744; // 30
+const static uint64_t SH_FLD_CLKGLM_SEL_LEN = 3745; // 30
+const static uint64_t SH_FLD_CLK_ASYNC_RESET = 3746; // 43
+const static uint64_t SH_FLD_CLK_BIST_ACTIVITY_DET = 3747; // 4
+const static uint64_t SH_FLD_CLK_BIST_ERR = 3748; // 4
+const static uint64_t SH_FLD_CLK_DIV_BYPASS_EN = 3749; // 43
+const static uint64_t SH_FLD_CLK_DLY = 3750; // 1
+const static uint64_t SH_FLD_CLK_DLY_LEN = 3751; // 1
+const static uint64_t SH_FLD_CLK_HALF_WIDTH_MODE = 3752; // 4
+const static uint64_t SH_FLD_CLK_INVERT = 3753; // 6
+const static uint64_t SH_FLD_CLK_PDLY_BYPASS_EN = 3754; // 43
+const static uint64_t SH_FLD_CLK_PULSE_EN = 3755; // 43
+const static uint64_t SH_FLD_CLK_PULSE_MODE = 3756; // 43
+const static uint64_t SH_FLD_CLK_PULSE_MODE_LEN = 3757; // 43
+const static uint64_t SH_FLD_CLK_QUIESCE = 3758; // 4
+const static uint64_t SH_FLD_CLK_QUIESCE_LEN = 3759; // 4
+const static uint64_t SH_FLD_CLK_QUIESCE_N = 3760; // 1
+const static uint64_t SH_FLD_CLK_QUIESCE_N_LEN = 3761; // 1
+const static uint64_t SH_FLD_CLK_QUIESCE_P = 3762; // 1
+const static uint64_t SH_FLD_CLK_QUIESCE_P_LEN = 3763; // 1
+const static uint64_t SH_FLD_CLK_RATE = 3764; // 4
+const static uint64_t SH_FLD_CLK_RATE_LEN = 3765; // 4
+const static uint64_t SH_FLD_CLK_RATE_SEL = 3766; // 1
+const static uint64_t SH_FLD_CLK_RATE_SEL_LEN = 3767; // 1
+const static uint64_t SH_FLD_CLK_RUN_COUNT = 3768; // 4
+const static uint64_t SH_FLD_CLK_SB_PULSE_MODE = 3769; // 24
+const static uint64_t SH_FLD_CLK_SB_PULSE_MODE_EN = 3770; // 24
+const static uint64_t SH_FLD_CLK_SB_PULSE_MODE_LEN = 3771; // 24
+const static uint64_t SH_FLD_CLK_SB_SPARE = 3772; // 24
+const static uint64_t SH_FLD_CLK_SB_STRENGTH = 3773; // 24
+const static uint64_t SH_FLD_CLK_SB_STRENGTH_LEN = 3774; // 24
+const static uint64_t SH_FLD_CLK_SW_RESCLK = 3775; // 24
+const static uint64_t SH_FLD_CLK_SW_RESCLK_LEN = 3776; // 24
+const static uint64_t SH_FLD_CLK_SW_SPARE = 3777; // 24
+const static uint64_t SH_FLD_CLK_SYNC = 3778; // 24
+const static uint64_t SH_FLD_CLK_SYNC_DONE = 3779; // 24
+const static uint64_t SH_FLD_CLK_SYNC_ENABLE = 3780; // 24
+const static uint64_t SH_FLD_CLK_UNLOAD_CLK_DISABLE = 3781; // 4
+const static uint64_t SH_FLD_CLK_UNLOAD_SEL = 3782; // 4
+const static uint64_t SH_FLD_CLK_UNLOAD_SEL_LEN = 3783; // 4
+const static uint64_t SH_FLD_CLOCK_CMD = 3784; // 43
+const static uint64_t SH_FLD_CLOCK_CMD_LEN = 3785; // 43
+const static uint64_t SH_FLD_CLOCK_DIVIDER = 3786; // 1
+const static uint64_t SH_FLD_CLOCK_DIVIDER_LEN = 3787; // 1
+const static uint64_t SH_FLD_CLOCK_DIV_4 = 3788; // 3
+const static uint64_t SH_FLD_CLOCK_PERV = 3789; // 43
+const static uint64_t SH_FLD_CLOCK_PULSE_USE_EVEN = 3790; // 43
+const static uint64_t SH_FLD_CLOCK_RATE_SELECTION = 3791; // 3
+const static uint64_t SH_FLD_CLOCK_RATE_SELECTION_0 = 3792; // 1
+const static uint64_t SH_FLD_CLOCK_RATE_SELECTION_0_LEN = 3793; // 1
+const static uint64_t SH_FLD_CLOCK_RATE_SELECTION_1 = 3794; // 2
+const static uint64_t SH_FLD_CLOCK_RATE_SELECTION_1_LEN = 3795; // 2
+const static uint64_t SH_FLD_CLOCK_RATE_SELECTION_LEN = 3796; // 3
+const static uint64_t SH_FLD_CLOCK_UNIT1 = 3797; // 43
+const static uint64_t SH_FLD_CLOCK_UNIT10 = 3798; // 43
+const static uint64_t SH_FLD_CLOCK_UNIT2 = 3799; // 43
+const static uint64_t SH_FLD_CLOCK_UNIT3 = 3800; // 43
+const static uint64_t SH_FLD_CLOCK_UNIT4 = 3801; // 43
+const static uint64_t SH_FLD_CLOCK_UNIT5 = 3802; // 43
+const static uint64_t SH_FLD_CLOCK_UNIT6 = 3803; // 43
+const static uint64_t SH_FLD_CLOCK_UNIT7 = 3804; // 43
+const static uint64_t SH_FLD_CLOCK_UNIT8 = 3805; // 43
+const static uint64_t SH_FLD_CLOCK_UNIT9 = 3806; // 43
+const static uint64_t SH_FLD_CLONE_CS_MODE = 3807; // 8
+const static uint64_t SH_FLD_CLR_PAR_ERRS = 3808; // 16
+const static uint64_t SH_FLD_CL_DATA = 3809; // 43
+const static uint64_t SH_FLD_CL_FINE_DISABLE = 3810; // 4
+const static uint64_t SH_FLD_CL_FINE_DISABLE_LEN = 3811; // 4
+const static uint64_t SH_FLD_CL_FSM = 3812; // 43
+const static uint64_t SH_FLD_CL_GLOBAL_DISABLE = 3813; // 4
+const static uint64_t SH_FLD_CL_GLOBAL_DISABLE_LEN = 3814; // 4
+const static uint64_t SH_FLD_CL_TIMEOUT_SEL = 3815; // 4
+const static uint64_t SH_FLD_CL_TIMEOUT_SEL_LEN = 3816; // 4
+const static uint64_t SH_FLD_CMD = 3817; // 43
+const static uint64_t SH_FLD_CMDREG_BROADCAST_FLAG = 3818; // 1
+const static uint64_t SH_FLD_CMDREG_SCAN_ADDRESS = 3819; // 1
+const static uint64_t SH_FLD_CMDREG_SCAN_ADDRESS_LEN = 3820; // 1
+const static uint64_t SH_FLD_CMDREG_SCAN_REGION = 3821; // 1
+const static uint64_t SH_FLD_CMDREG_SCAN_REGION_LEN = 3822; // 1
+const static uint64_t SH_FLD_CMDREG_SCAN_TYPE = 3823; // 1
+const static uint64_t SH_FLD_CMDREG_SCAN_TYPE_LEN = 3824; // 1
+const static uint64_t SH_FLD_CMDREG_WRITE_FLAG = 3825; // 1
+const static uint64_t SH_FLD_CMD_BANK = 3826; // 2
+const static uint64_t SH_FLD_CMD_BANK_LEN = 3827; // 2
+const static uint64_t SH_FLD_CMD_BUFFER_PAR_ERR = 3828; // 4
+const static uint64_t SH_FLD_CMD_COL = 3829; // 2
+const static uint64_t SH_FLD_CMD_COL_LEN = 3830; // 2
+const static uint64_t SH_FLD_CMD_COUNT_ERR = 3831; // 1
+const static uint64_t SH_FLD_CMD_DIMM_SELECT = 3832; // 2
+const static uint64_t SH_FLD_CMD_ERR_STATUS = 3833; // 2
+const static uint64_t SH_FLD_CMD_ERR_STATUS_LEN = 3834; // 2
+const static uint64_t SH_FLD_CMD_IN_PROG = 3835; // 1
+const static uint64_t SH_FLD_CMD_LEN = 3836; // 43
+const static uint64_t SH_FLD_CMD_MASTER_RANK0 = 3837; // 2
+const static uint64_t SH_FLD_CMD_MASTER_RANK1 = 3838; // 2
+const static uint64_t SH_FLD_CMD_MASTER_RANK2 = 3839; // 2
+const static uint64_t SH_FLD_CMD_PARITY_ERROR = 3840; // 3
+const static uint64_t SH_FLD_CMD_REG = 3841; // 2
+const static uint64_t SH_FLD_CMD_REG_ADDR_1 = 3842; // 1
+const static uint64_t SH_FLD_CMD_REG_ADDR_1_LEN = 3843; // 1
+const static uint64_t SH_FLD_CMD_REG_ADDR_2 = 3844; // 1
+const static uint64_t SH_FLD_CMD_REG_ADDR_2_LEN = 3845; // 1
+const static uint64_t SH_FLD_CMD_REG_ADDR_3 = 3846; // 1
+const static uint64_t SH_FLD_CMD_REG_ADDR_3_LEN = 3847; // 1
+const static uint64_t SH_FLD_CMD_REG_ADDR_4 = 3848; // 1
+const static uint64_t SH_FLD_CMD_REG_ADDR_4_LEN = 3849; // 1
+const static uint64_t SH_FLD_CMD_REG_BIT_READCONT = 3850; // 1
+const static uint64_t SH_FLD_CMD_REG_BIT_RNW = 3851; // 1
+const static uint64_t SH_FLD_CMD_REG_BIT_WITHADDR = 3852; // 1
+const static uint64_t SH_FLD_CMD_REG_BIT_WITHSTART = 3853; // 1
+const static uint64_t SH_FLD_CMD_REG_BIT_WITHSTOP = 3854; // 1
+const static uint64_t SH_FLD_CMD_REG_LEN = 3855; // 2
+const static uint64_t SH_FLD_CMD_REG_LENGTH = 3856; // 1
+const static uint64_t SH_FLD_CMD_REG_LENGTH_LEN = 3857; // 1
+const static uint64_t SH_FLD_CMD_ROW = 3858; // 2
+const static uint64_t SH_FLD_CMD_ROW17 = 3859; // 4
+const static uint64_t SH_FLD_CMD_ROW_LEN = 3860; // 2
+const static uint64_t SH_FLD_CMD_SCOPE = 3861; // 4
+const static uint64_t SH_FLD_CMD_SCOPE_LEN = 3862; // 4
+const static uint64_t SH_FLD_CMD_SLAVE_RANK = 3863; // 2
+const static uint64_t SH_FLD_CMD_SLAVE_RANK_LEN = 3864; // 2
+const static uint64_t SH_FLD_CMD_STATUS = 3865; // 1
+const static uint64_t SH_FLD_CMD_STATUS_LEN = 3866; // 1
+const static uint64_t SH_FLD_CMD_TIMEOUT_SEL = 3867; // 2
+const static uint64_t SH_FLD_CMD_TIMEOUT_SEL_LEN = 3868; // 2
+const static uint64_t SH_FLD_CMD_TO_CMD_COUNT = 3869; // 8
+const static uint64_t SH_FLD_CMD_TO_CMD_COUNT_LEN = 3870; // 8
+const static uint64_t SH_FLD_CME_ERR_NOTIFY_EN = 3871; // 24
+const static uint64_t SH_FLD_CME_INTERPPM_ACLK_ENABLE = 3872; // 6
+const static uint64_t SH_FLD_CME_INTERPPM_ACLK_SEL = 3873; // 6
+const static uint64_t SH_FLD_CME_INTERPPM_DPLL_ENABLE = 3874; // 6
+const static uint64_t SH_FLD_CME_INTERPPM_DPLL_SEL = 3875; // 6
+const static uint64_t SH_FLD_CME_INTERPPM_IVRM_ENABLE = 3876; // 6
+const static uint64_t SH_FLD_CME_INTERPPM_IVRM_SEL = 3877; // 6
+const static uint64_t SH_FLD_CME_INTERPPM_VDM_ENABLE = 3878; // 6
+const static uint64_t SH_FLD_CME_INTERPPM_VDM_SEL = 3879; // 6
+const static uint64_t SH_FLD_CME_MESSAGE = 3880; // 24
+const static uint64_t SH_FLD_CME_MESSAGE_HI = 3881; // 24
+const static uint64_t SH_FLD_CME_MESSAGE_HI_LEN = 3882; // 24
+const static uint64_t SH_FLD_CME_MESSAGE_LEN = 3883; // 24
+const static uint64_t SH_FLD_CME_MESSAGE_NUMBER0 = 3884; // 24
+const static uint64_t SH_FLD_CME_MESSAGE_NUMBER0_LEN = 3885; // 24
+const static uint64_t SH_FLD_CME_MESSAGE_NUMBER_N = 3886; // 72
+const static uint64_t SH_FLD_CME_MESSAGE_NUMBER_N_LEN = 3887; // 72
+const static uint64_t SH_FLD_CME_REQUEST = 3888; // 96
+const static uint64_t SH_FLD_CMFSI_ACCESS_PROTCT = 3889; // 1
+const static uint64_t SH_FLD_CMLEN = 3890; // 10
+const static uint64_t SH_FLD_CMP_MSK_LT_B_64_TO_87 = 3891; // 90
+const static uint64_t SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN = 3892; // 90
+const static uint64_t SH_FLD_CMP_MSK_LT_B_TO_63 = 3893; // 90
+const static uint64_t SH_FLD_CMP_MSK_LT_B_TO_63_LEN = 3894; // 90
+const static uint64_t SH_FLD_CMSK = 3895; // 43
+const static uint64_t SH_FLD_CM_CFG = 3896; // 6
+const static uint64_t SH_FLD_CM_CFG_LEN = 3897; // 6
+const static uint64_t SH_FLD_CM_CNTL = 3898; // 120
+const static uint64_t SH_FLD_CM_CNTL_LEN = 3899; // 120
+const static uint64_t SH_FLD_CM_OFFSET_VAL = 3900; // 6
+const static uint64_t SH_FLD_CM_OFFSET_VAL_LEN = 3901; // 6
+const static uint64_t SH_FLD_CM_TIMEOUT = 3902; // 6
+const static uint64_t SH_FLD_CM_TIMEOUT_LEN = 3903; // 6
+const static uint64_t SH_FLD_CND_HWD_DOES_DEM_IVE = 3904; // 1
+const static uint64_t SH_FLD_CND_HWD_DOES_DEM_IVE_LEN = 3905; // 1
+const static uint64_t SH_FLD_CNT0_BIT_PAIR_SEL = 3906; // 1
+const static uint64_t SH_FLD_CNT0_BIT_PAIR_SEL_LEN = 3907; // 1
+const static uint64_t SH_FLD_CNT0_ENABLE = 3908; // 1
+const static uint64_t SH_FLD_CNT0_EVENT_SEL = 3909; // 1
+const static uint64_t SH_FLD_CNT0_EVENT_SEL_LEN = 3910; // 1
+const static uint64_t SH_FLD_CNT0_MUX_SEL = 3911; // 2
+const static uint64_t SH_FLD_CNT0_MUX_SEL_LEN = 3912; // 2
+const static uint64_t SH_FLD_CNT0_PAIR_OP = 3913; // 2
+const static uint64_t SH_FLD_CNT0_PAIR_OP_LEN = 3914; // 2
+const static uint64_t SH_FLD_CNT0_POSEDGE_SEL = 3915; // 1
+const static uint64_t SH_FLD_CNT1_BIT_PAIR_SEL = 3916; // 1
+const static uint64_t SH_FLD_CNT1_BIT_PAIR_SEL_LEN = 3917; // 1
+const static uint64_t SH_FLD_CNT1_ENABLE = 3918; // 1
+const static uint64_t SH_FLD_CNT1_EVENT_SEL = 3919; // 1
+const static uint64_t SH_FLD_CNT1_EVENT_SEL_LEN = 3920; // 1
+const static uint64_t SH_FLD_CNT1_MUX_SEL = 3921; // 2
+const static uint64_t SH_FLD_CNT1_MUX_SEL_LEN = 3922; // 2
+const static uint64_t SH_FLD_CNT1_PAIR_OP = 3923; // 2
+const static uint64_t SH_FLD_CNT1_PAIR_OP_LEN = 3924; // 2
+const static uint64_t SH_FLD_CNT1_POSEDGE_SEL = 3925; // 1
+const static uint64_t SH_FLD_CNT2_BIT_PAIR_SEL = 3926; // 1
+const static uint64_t SH_FLD_CNT2_BIT_PAIR_SEL_LEN = 3927; // 1
+const static uint64_t SH_FLD_CNT2_ENABLE = 3928; // 1
+const static uint64_t SH_FLD_CNT2_EVENT_SEL = 3929; // 1
+const static uint64_t SH_FLD_CNT2_EVENT_SEL_LEN = 3930; // 1
+const static uint64_t SH_FLD_CNT2_MUX_SEL = 3931; // 2
+const static uint64_t SH_FLD_CNT2_MUX_SEL_LEN = 3932; // 2
+const static uint64_t SH_FLD_CNT2_PAIR_OP = 3933; // 2
+const static uint64_t SH_FLD_CNT2_PAIR_OP_LEN = 3934; // 2
+const static uint64_t SH_FLD_CNT2_POSEDGE_SEL = 3935; // 1
+const static uint64_t SH_FLD_CNT3_BIT_PAIR_SEL = 3936; // 1
+const static uint64_t SH_FLD_CNT3_BIT_PAIR_SEL_LEN = 3937; // 1
+const static uint64_t SH_FLD_CNT3_ENABLE = 3938; // 1
+const static uint64_t SH_FLD_CNT3_EVENT_SEL = 3939; // 1
+const static uint64_t SH_FLD_CNT3_EVENT_SEL_LEN = 3940; // 1
+const static uint64_t SH_FLD_CNT3_MUX_SEL = 3941; // 2
+const static uint64_t SH_FLD_CNT3_MUX_SEL_LEN = 3942; // 2
+const static uint64_t SH_FLD_CNT3_PAIR_OP = 3943; // 2
+const static uint64_t SH_FLD_CNT3_PAIR_OP_LEN = 3944; // 2
+const static uint64_t SH_FLD_CNT3_POSEDGE_SEL = 3945; // 1
+const static uint64_t SH_FLD_CNTL = 3946; // 8
+const static uint64_t SH_FLD_CNTLS_PREV_LDED_GCRMSG = 3947; // 4
+const static uint64_t SH_FLD_CNTL_LEN = 3948; // 8
+const static uint64_t SH_FLD_CNT_BROADCAST = 3949; // 1
+const static uint64_t SH_FLD_CNT_BROADCAST_LEN = 3950; // 1
+const static uint64_t SH_FLD_CNT_CI_STORE_REPLAY = 3951; // 1
+const static uint64_t SH_FLD_CNT_CI_STORE_REPLAY_LEN = 3952; // 1
+const static uint64_t SH_FLD_CNT_DEM_CACHE_HIT = 3953; // 1
+const static uint64_t SH_FLD_CNT_DEM_CACHE_HIT_LEN = 3954; // 1
+const static uint64_t SH_FLD_CNT_DMA_RD = 3955; // 6
+const static uint64_t SH_FLD_CNT_DMA_RD_LEN = 3956; // 6
+const static uint64_t SH_FLD_CNT_DMA_WR = 3957; // 6
+const static uint64_t SH_FLD_CNT_DMA_WR_LEN = 3958; // 6
+const static uint64_t SH_FLD_CNT_EOI_CACHE_HIT = 3959; // 1
+const static uint64_t SH_FLD_CNT_EOI_CACHE_HIT_LEN = 3960; // 1
+const static uint64_t SH_FLD_CNT_EOI_RESP_REPLAY = 3961; // 2
+const static uint64_t SH_FLD_CNT_EOI_RESP_REPLAY_LEN = 3962; // 2
+const static uint64_t SH_FLD_CNT_EQC_COMMAND = 3963; // 1
+const static uint64_t SH_FLD_CNT_EQC_COMMAND_LEN = 3964; // 1
+const static uint64_t SH_FLD_CNT_EQD_FETCH = 3965; // 1
+const static uint64_t SH_FLD_CNT_EQD_FETCH_LEN = 3966; // 1
+const static uint64_t SH_FLD_CNT_EQD_FETCH_REPLAY = 3967; // 1
+const static uint64_t SH_FLD_CNT_EQD_FETCH_REPLAY_LEN = 3968; // 1
+const static uint64_t SH_FLD_CNT_EQP = 3969; // 1
+const static uint64_t SH_FLD_CNT_EQP_LEN = 3970; // 1
+const static uint64_t SH_FLD_CNT_EQP_REPLAY = 3971; // 1
+const static uint64_t SH_FLD_CNT_EQP_REPLAY_LEN = 3972; // 1
+const static uint64_t SH_FLD_CNT_EQ_FWD = 3973; // 1
+const static uint64_t SH_FLD_CNT_EQ_FWD_LEN = 3974; // 1
+const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_1ESC = 3975; // 1
+const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_1ESC_LEN = 3976; // 1
+const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_2ESC = 3977; // 1
+const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_2ESC_LEN = 3978; // 1
+const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_HWD = 3979; // 1
+const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_HWD_LEN = 3980; // 1
+const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_IPI = 3981; // 1
+const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_IPI_LEN = 3982; // 1
+const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_REDIS = 3983; // 1
+const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_REDIS_LEN = 3984; // 1
+const static uint64_t SH_FLD_CNT_EQ_TRIG_CACHE_HIT = 3985; // 1
+const static uint64_t SH_FLD_CNT_EQ_TRIG_CACHE_HIT_LEN = 3986; // 1
+const static uint64_t SH_FLD_CNT_ESCALATE = 3987; // 1
+const static uint64_t SH_FLD_CNT_ESCALATE_LEN = 3988; // 1
+const static uint64_t SH_FLD_CNT_FIFO_FULL = 3989; // 6
+const static uint64_t SH_FLD_CNT_FIFO_FULL_LEN = 3990; // 6
+const static uint64_t SH_FLD_CNT_GROUP = 3991; // 1
+const static uint64_t SH_FLD_CNT_GROUP_LEN = 3992; // 1
+const static uint64_t SH_FLD_CNT_HWD_DOES_PRF_IVE = 3993; // 1
+const static uint64_t SH_FLD_CNT_HWD_DOES_PRF_IVE_LEN = 3994; // 1
+const static uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE = 3995; // 1
+const static uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE_LEN = 3996; // 1
+const static uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE_SBC = 3997; // 1
+const static uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE_SBC_LEN = 3998; // 1
+const static uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE = 3999; // 1
+const static uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE_LEN = 4000; // 1
+const static uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE_SBC = 4001; // 1
+const static uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE_SBC_LEN = 4002; // 1
+const static uint64_t SH_FLD_CNT_ISB_FETCH = 4003; // 1
+const static uint64_t SH_FLD_CNT_ISB_FETCH_LEN = 4004; // 1
+const static uint64_t SH_FLD_CNT_ISB_FETCH_REPLAY = 4005; // 1
+const static uint64_t SH_FLD_CNT_ISB_FETCH_REPLAY_LEN = 4006; // 1
+const static uint64_t SH_FLD_CNT_ISB_WRITE = 4007; // 1
+const static uint64_t SH_FLD_CNT_ISB_WRITE_LEN = 4008; // 1
+const static uint64_t SH_FLD_CNT_IVC_DEMAND = 4009; // 1
+const static uint64_t SH_FLD_CNT_IVC_DEMAND_LEN = 4010; // 1
+const static uint64_t SH_FLD_CNT_IVC_PRF = 4011; // 1
+const static uint64_t SH_FLD_CNT_IVC_PRF_LEN = 4012; // 1
+const static uint64_t SH_FLD_CNT_IVC_RESP_REPLAY = 4013; // 1
+const static uint64_t SH_FLD_CNT_IVC_RESP_REPLAY_LEN = 4014; // 1
+const static uint64_t SH_FLD_CNT_IVE_FETCH = 4015; // 1
+const static uint64_t SH_FLD_CNT_IVE_FETCH_LEN = 4016; // 1
+const static uint64_t SH_FLD_CNT_IVE_FETCH_REPLAY = 4017; // 1
+const static uint64_t SH_FLD_CNT_IVE_FETCH_REPLAY_LEN = 4018; // 1
+const static uint64_t SH_FLD_CNT_IVVC_RESP = 4019; // 1
+const static uint64_t SH_FLD_CNT_IVVC_RESP_LEN = 4020; // 1
+const static uint64_t SH_FLD_CNT_LOCAL_ESCALATE = 4021; // 1
+const static uint64_t SH_FLD_CNT_LOCAL_ESCALATE_LEN = 4022; // 1
+const static uint64_t SH_FLD_CNT_LOCAL_ESC_CACHE_HIT = 4023; // 1
+const static uint64_t SH_FLD_CNT_LOCAL_ESC_CACHE_HIT_LEN = 4024; // 1
+const static uint64_t SH_FLD_CNT_LOCAL_ESC_REPLAY = 4025; // 1
+const static uint64_t SH_FLD_CNT_LOCAL_ESC_REPLAY_LEN = 4026; // 1
+const static uint64_t SH_FLD_CNT_LOCAL_SBC_REPLAY = 4027; // 1
+const static uint64_t SH_FLD_CNT_LOCAL_SBC_REPLAY_LEN = 4028; // 1
+const static uint64_t SH_FLD_CNT_LOCAL_SBC_UPD = 4029; // 1
+const static uint64_t SH_FLD_CNT_LOCAL_SBC_UPD_LEN = 4030; // 1
+const static uint64_t SH_FLD_CNT_LOCAL_VPC_REPLAY = 4031; // 1
+const static uint64_t SH_FLD_CNT_LOCAL_VPC_REPLAY_LEN = 4032; // 1
+const static uint64_t SH_FLD_CNT_LOCAL_VPC_UPD = 4033; // 1
+const static uint64_t SH_FLD_CNT_LOCAL_VPC_UPD_LEN = 4034; // 1
+const static uint64_t SH_FLD_CNT_LS = 4035; // 1
+const static uint64_t SH_FLD_CNT_LS_LEN = 4036; // 1
+const static uint64_t SH_FLD_CNT_NEW_CMD_STALLED = 4037; // 1
+const static uint64_t SH_FLD_CNT_NEW_CMD_STALLED_LEN = 4038; // 1
+const static uint64_t SH_FLD_CNT_NON_SPEC_EOI = 4039; // 1
+const static uint64_t SH_FLD_CNT_NON_SPEC_EOI_LEN = 4040; // 1
+const static uint64_t SH_FLD_CNT_NON_SPEC_EOI_NOTOWNED = 4041; // 1
+const static uint64_t SH_FLD_CNT_NON_SPEC_EOI_NOTOWNED_LEN = 4042; // 1
+const static uint64_t SH_FLD_CNT_NON_SPEC_EOI_OWNED = 4043; // 1
+const static uint64_t SH_FLD_CNT_NON_SPEC_EOI_OWNED_LEN = 4044; // 1
+const static uint64_t SH_FLD_CNT_OTHER_CACHE_HIT = 4045; // 1
+const static uint64_t SH_FLD_CNT_OTHER_CACHE_HIT_LEN = 4046; // 1
+const static uint64_t SH_FLD_CNT_PRF_CACHE_HIT = 4047; // 2
+const static uint64_t SH_FLD_CNT_PRF_CACHE_HIT_LEN = 4048; // 2
+const static uint64_t SH_FLD_CNT_R0 = 4049; // 3
+const static uint64_t SH_FLD_CNT_R0_LEN = 4050; // 3
+const static uint64_t SH_FLD_CNT_R10R = 4051; // 3
+const static uint64_t SH_FLD_CNT_R10R_LEN = 4052; // 3
+const static uint64_t SH_FLD_CNT_R10W = 4053; // 3
+const static uint64_t SH_FLD_CNT_R10W_LEN = 4054; // 3
+const static uint64_t SH_FLD_CNT_R1R = 4055; // 3
+const static uint64_t SH_FLD_CNT_R1R_LEN = 4056; // 3
+const static uint64_t SH_FLD_CNT_R1W = 4057; // 3
+const static uint64_t SH_FLD_CNT_R1W_LEN = 4058; // 3
+const static uint64_t SH_FLD_CNT_R2 = 4059; // 3
+const static uint64_t SH_FLD_CNT_R2_LEN = 4060; // 3
+const static uint64_t SH_FLD_CNT_R3 = 4061; // 3
+const static uint64_t SH_FLD_CNT_R3_LEN = 4062; // 3
+const static uint64_t SH_FLD_CNT_R4 = 4063; // 3
+const static uint64_t SH_FLD_CNT_R4_LEN = 4064; // 3
+const static uint64_t SH_FLD_CNT_R5R = 4065; // 3
+const static uint64_t SH_FLD_CNT_R5R_LEN = 4066; // 3
+const static uint64_t SH_FLD_CNT_R5W = 4067; // 3
+const static uint64_t SH_FLD_CNT_R5W_LEN = 4068; // 3
+const static uint64_t SH_FLD_CNT_R6 = 4069; // 3
+const static uint64_t SH_FLD_CNT_R6_LEN = 4070; // 3
+const static uint64_t SH_FLD_CNT_R7EQP = 4071; // 3
+const static uint64_t SH_FLD_CNT_R7EQP_LEN = 4072; // 3
+const static uint64_t SH_FLD_CNT_R7INT = 4073; // 3
+const static uint64_t SH_FLD_CNT_R7INT_LEN = 4074; // 3
+const static uint64_t SH_FLD_CNT_R7RSP = 4075; // 3
+const static uint64_t SH_FLD_CNT_R7RSP_LEN = 4076; // 3
+const static uint64_t SH_FLD_CNT_R8 = 4077; // 3
+const static uint64_t SH_FLD_CNT_R8_LEN = 4078; // 3
+const static uint64_t SH_FLD_CNT_R9 = 4079; // 3
+const static uint64_t SH_FLD_CNT_R9_LEN = 4080; // 3
+const static uint64_t SH_FLD_CNT_REMOTE_CI_LOAD_REPLAY = 4081; // 1
+const static uint64_t SH_FLD_CNT_REMOTE_CI_LOAD_REPLAY_LEN = 4082; // 1
+const static uint64_t SH_FLD_CNT_REMOTE_SBC_UPD = 4083; // 1
+const static uint64_t SH_FLD_CNT_REMOTE_SBC_UPD_LEN = 4084; // 1
+const static uint64_t SH_FLD_CNT_REMOTE_VPC_UPD = 4085; // 1
+const static uint64_t SH_FLD_CNT_REMOTE_VPC_UPD_LEN = 4086; // 1
+const static uint64_t SH_FLD_CNT_REPLAY = 4087; // 1
+const static uint64_t SH_FLD_CNT_REPLAY_LEN = 4088; // 1
+const static uint64_t SH_FLD_CNT_RETRY = 4089; // 2
+const static uint64_t SH_FLD_CNT_RETRY_LEN = 4090; // 2
+const static uint64_t SH_FLD_CNT_SBC_LOOKUP = 4091; // 1
+const static uint64_t SH_FLD_CNT_SBC_LOOKUP_LEN = 4092; // 1
+const static uint64_t SH_FLD_CNT_SBC_LOOKUP_REPLAY = 4093; // 1
+const static uint64_t SH_FLD_CNT_SBC_LOOKUP_REPLAY_LEN = 4094; // 1
+const static uint64_t SH_FLD_CNT_SPEC_EOI = 4095; // 1
+const static uint64_t SH_FLD_CNT_SPEC_EOI_CACHE_HIT = 4096; // 1
+const static uint64_t SH_FLD_CNT_SPEC_EOI_CACHE_HIT_LEN = 4097; // 1
+const static uint64_t SH_FLD_CNT_SPEC_EOI_LEN = 4098; // 1
+const static uint64_t SH_FLD_CNT_TOO_MANY_ENTRIES = 4099; // 2
+const static uint64_t SH_FLD_CNT_TOO_MANY_ENTRIES_LEN = 4100; // 2
+const static uint64_t SH_FLD_CNT_TRIG_DROPPED = 4101; // 6
+const static uint64_t SH_FLD_CNT_TRIG_DROPPED_LEN = 4102; // 6
+const static uint64_t SH_FLD_CNT_TRIG_FROM_AIB = 4103; // 6
+const static uint64_t SH_FLD_CNT_TRIG_FROM_AIB_LEN = 4104; // 6
+const static uint64_t SH_FLD_CNT_TRIG_FWD_TO_EQC = 4105; // 6
+const static uint64_t SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN = 4106; // 6
+const static uint64_t SH_FLD_CNT_USE_L2_DIVIDER_EN = 4107; // 12
+const static uint64_t SH_FLD_CNT_VICTIM_IS_1ST_USABLE = 4108; // 2
+const static uint64_t SH_FLD_CNT_VICTIM_IS_1ST_USABLE_LEN = 4109; // 2
+const static uint64_t SH_FLD_CNT_VICTIM_IS_FIRST_USABLE = 4110; // 1
+const static uint64_t SH_FLD_CNT_VICTIM_IS_FIRST_USABLE_LEN = 4111; // 1
+const static uint64_t SH_FLD_CNT_VICTIM_IS_LRU = 4112; // 3
+const static uint64_t SH_FLD_CNT_VICTIM_IS_LRU_LEN = 4113; // 3
+const static uint64_t SH_FLD_CNT_VP = 4114; // 1
+const static uint64_t SH_FLD_CNT_VP_LEN = 4115; // 1
+const static uint64_t SH_FLD_CNT_WAKEUP = 4116; // 1
+const static uint64_t SH_FLD_CNT_WAKEUP_LEN = 4117; // 1
+const static uint64_t SH_FLD_COARSE_CAL_STEP_SIZE = 4118; // 8
+const static uint64_t SH_FLD_COARSE_CAL_STEP_SIZE_LEN = 4119; // 8
+const static uint64_t SH_FLD_COARSE_DIR_ENABLE = 4120; // 2
+const static uint64_t SH_FLD_COARSE_DIR_SECTORS = 4121; // 2
+const static uint64_t SH_FLD_COARSE_RD = 4122; // 8
+const static uint64_t SH_FLD_COFSM_ADDR_ERR = 4123; // 12
+const static uint64_t SH_FLD_COL4_BIT_MAP = 4124; // 8
+const static uint64_t SH_FLD_COL4_BIT_MAP_LEN = 4125; // 8
+const static uint64_t SH_FLD_COL5_BIT_MAP = 4126; // 8
+const static uint64_t SH_FLD_COL5_BIT_MAP_LEN = 4127; // 8
+const static uint64_t SH_FLD_COL6_BIT_MAP = 4128; // 8
+const static uint64_t SH_FLD_COL6_BIT_MAP_LEN = 4129; // 8
+const static uint64_t SH_FLD_COL7_BIT_MAP = 4130; // 8
+const static uint64_t SH_FLD_COL7_BIT_MAP_LEN = 4131; // 8
+const static uint64_t SH_FLD_COL8_BIT_MAP = 4132; // 8
+const static uint64_t SH_FLD_COL8_BIT_MAP_LEN = 4133; // 8
+const static uint64_t SH_FLD_COL9_BIT_MAP = 4134; // 8
+const static uint64_t SH_FLD_COL9_BIT_MAP_LEN = 4135; // 8
+const static uint64_t SH_FLD_COLLISION_MODES = 4136; // 4
+const static uint64_t SH_FLD_COLLISION_MODES_LEN = 4137; // 4
+const static uint64_t SH_FLD_COLLISON = 4138; // 1
+const static uint64_t SH_FLD_COMMAND_ADDRESS_TIMEOUT = 4139; // 10
+const static uint64_t SH_FLD_COMMAND_COMPLETE = 4140; // 1
+const static uint64_t SH_FLD_COMMAND_COMPLETE_WO_ENA_ERR_ATTN = 4141; // 4
+const static uint64_t SH_FLD_COMMAND_LIST_TIMEOUT = 4142; // 4
+const static uint64_t SH_FLD_COMMAND_LIST_TIMEOUT_SPEC = 4143; // 4
+const static uint64_t SH_FLD_COMMAND_PATTERN_TO_COUNT = 4144; // 8
+const static uint64_t SH_FLD_COMMAND_PATTERN_TO_COUNT_LEN = 4145; // 8
+const static uint64_t SH_FLD_COMMON_FREEZE_MODE = 4146; // 2
+const static uint64_t SH_FLD_COMM_ACK = 4147; // 12
+const static uint64_t SH_FLD_COMM_NACK = 4148; // 12
+const static uint64_t SH_FLD_COMM_RECV = 4149; // 12
+const static uint64_t SH_FLD_COMM_RECVD = 4150; // 12
+const static uint64_t SH_FLD_COMM_RECV_LEN = 4151; // 12
+const static uint64_t SH_FLD_COMM_SEND = 4152; // 12
+const static uint64_t SH_FLD_COMM_SEND_ACK = 4153; // 12
+const static uint64_t SH_FLD_COMM_SEND_LEN = 4154; // 12
+const static uint64_t SH_FLD_COMM_SEND_NACK = 4155; // 12
+const static uint64_t SH_FLD_COMPLETE = 4156; // 8
+const static uint64_t SH_FLD_COMPLETE_LEN = 4157; // 8
+const static uint64_t SH_FLD_COMPRESSED_RSP_ENA = 4158; // 6
+const static uint64_t SH_FLD_COND_STARTUP_TEST_FAIL = 4159; // 1
+const static uint64_t SH_FLD_CONFIG1_RESERVED0 = 4160; // 3
+const static uint64_t SH_FLD_CONFIG1_RESERVED1 = 4161; // 15
+const static uint64_t SH_FLD_CONFIG1_RESERVED1_LEN = 4162; // 3
+const static uint64_t SH_FLD_CONFIG1_RESERVED2 = 4163; // 15
+const static uint64_t SH_FLD_CONFIG1_RESERVED2_LEN = 4164; // 3
+const static uint64_t SH_FLD_CONFIG_ADDR = 4165; // 84
+const static uint64_t SH_FLD_CONFIG_ADDR_LEN = 4166; // 84
+const static uint64_t SH_FLD_CONFIG_ADR_BAR_MODE = 4167; // 15
+const static uint64_t SH_FLD_CONFIG_ARMWF_ADD = 4168; // 12
+const static uint64_t SH_FLD_CONFIG_ARMWF_AND = 4169; // 12
+const static uint64_t SH_FLD_CONFIG_ARMWF_CAS_E = 4170; // 12
+const static uint64_t SH_FLD_CONFIG_ARMWF_CAS_IMAX_S = 4171; // 12
+const static uint64_t SH_FLD_CONFIG_ARMWF_CAS_IMAX_U = 4172; // 12
+const static uint64_t SH_FLD_CONFIG_ARMWF_CAS_IMIN_S = 4173; // 12
+const static uint64_t SH_FLD_CONFIG_ARMWF_CAS_IMIN_U = 4174; // 12
+const static uint64_t SH_FLD_CONFIG_ARMWF_CAS_U = 4175; // 12
+const static uint64_t SH_FLD_CONFIG_ARMWF_OR = 4176; // 12
+const static uint64_t SH_FLD_CONFIG_ARMWF_XOR = 4177; // 12
+const static uint64_t SH_FLD_CONFIG_ARMW_ADD = 4178; // 12
+const static uint64_t SH_FLD_CONFIG_ARMW_AND = 4179; // 12
+const static uint64_t SH_FLD_CONFIG_ARMW_CAS_IMAX_S = 4180; // 12
+const static uint64_t SH_FLD_CONFIG_ARMW_CAS_IMAX_U = 4181; // 12
+const static uint64_t SH_FLD_CONFIG_ARMW_CAS_IMIN_S = 4182; // 12
+const static uint64_t SH_FLD_CONFIG_ARMW_CAS_IMIN_U = 4183; // 12
+const static uint64_t SH_FLD_CONFIG_ARMW_OR = 4184; // 12
+const static uint64_t SH_FLD_CONFIG_ARMW_XOR = 4185; // 12
+const static uint64_t SH_FLD_CONFIG_BRAZOS = 4186; // 1
+const static uint64_t SH_FLD_CONFIG_BRAZOS_MODE = 4187; // 15
+const static uint64_t SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN = 4188; // 12
+const static uint64_t SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN = 4189; // 12
+const static uint64_t SH_FLD_CONFIG_CL_DMA_INJ = 4190; // 12
+const static uint64_t SH_FLD_CONFIG_CL_DMA_W = 4191; // 12
+const static uint64_t SH_FLD_CONFIG_CL_DMA_W_HP = 4192; // 12
+const static uint64_t SH_FLD_CONFIG_DISABLE_G = 4193; // 12
+const static uint64_t SH_FLD_CONFIG_DISABLE_LN = 4194; // 12
+const static uint64_t SH_FLD_CONFIG_DISABLE_NN_RN = 4195; // 12
+const static uint64_t SH_FLD_CONFIG_DISABLE_VG_NOT_SYS = 4196; // 12
+const static uint64_t SH_FLD_CONFIG_DMA_PR_W = 4197; // 12
+const static uint64_t SH_FLD_CONFIG_ENABLE = 4198; // 84
+const static uint64_t SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC = 4199; // 12
+const static uint64_t SH_FLD_CONFIG_ENABLE_PBUS = 4200; // 12
+const static uint64_t SH_FLD_CONFIG_ENABLE_SNARF_CPM = 4201; // 12
+const static uint64_t SH_FLD_CONFIG_EVAPORATE_BY_LCO = 4202; // 12
+const static uint64_t SH_FLD_CONFIG_GEN_HEAD_DELAY = 4203; // 3
+const static uint64_t SH_FLD_CONFIG_GEN_HEAD_DELAY_LEN = 4204; // 3
+const static uint64_t SH_FLD_CONFIG_GRANULE = 4205; // 24
+const static uint64_t SH_FLD_CONFIG_INC_PRI_MASK = 4206; // 12
+const static uint64_t SH_FLD_CONFIG_INC_PRI_MASK_LEN = 4207; // 12
+const static uint64_t SH_FLD_CONFIG_L2L3NCU = 4208; // 12
+const static uint64_t SH_FLD_CONFIG_MACH_CORRENAB = 4209; // 12
+const static uint64_t SH_FLD_CONFIG_MACH_INJECT_ENABLE1 = 4210; // 12
+const static uint64_t SH_FLD_CONFIG_MACH_INJECT_ENABLE2 = 4211; // 12
+const static uint64_t SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR = 4212; // 12
+const static uint64_t SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG = 4213; // 12
+const static uint64_t SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR = 4214; // 12
+const static uint64_t SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE = 4215; // 12
+const static uint64_t SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA = 4216; // 12
+const static uint64_t SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ = 4217; // 12
+const static uint64_t SH_FLD_CONFIG_MA_MCRESP_OPT_WRP = 4218; // 12
+const static uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_B = 4219; // 12
+const static uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_C = 4220; // 12
+const static uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM = 4221; // 12
+const static uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN = 4222; // 12
+const static uint64_t SH_FLD_CONFIG_MA_SCRESP_OPT_A = 4223; // 12
+const static uint64_t SH_FLD_CONFIG_MA_SCRESP_OPT_B = 4224; // 12
+const static uint64_t SH_FLD_CONFIG_MA_SCRESP_OPT_C = 4225; // 12
+const static uint64_t SH_FLD_CONFIG_MEMTYPE = 4226; // 24
+const static uint64_t SH_FLD_CONFIG_MEMTYPE_LEN = 4227; // 24
+const static uint64_t SH_FLD_CONFIG_MODE = 4228; // 24
+const static uint64_t SH_FLD_CONFIG_MODE_LEN = 4229; // 24
+const static uint64_t SH_FLD_CONFIG_MRBGP_DIS_DYN_ADJ = 4230; // 3
+const static uint64_t SH_FLD_CONFIG_MRBGP_DIS_DYN_LVL_ADJ = 4231; // 3
+const static uint64_t SH_FLD_CONFIG_MRBGP_DIV2_COUNT_AT_EXP = 4232; // 3
+const static uint64_t SH_FLD_CONFIG_MRBGP_MAX_LEVEL = 4233; // 3
+const static uint64_t SH_FLD_CONFIG_MRBGP_MAX_LEVEL_LEN = 4234; // 3
+const static uint64_t SH_FLD_CONFIG_MRBGP_THRESH1 = 4235; // 3
+const static uint64_t SH_FLD_CONFIG_MRBGP_THRESH1_LEN = 4236; // 3
+const static uint64_t SH_FLD_CONFIG_MRBGP_THRESH2 = 4237; // 3
+const static uint64_t SH_FLD_CONFIG_MRBGP_THRESH2_LEN = 4238; // 3
+const static uint64_t SH_FLD_CONFIG_MRBGP_TRACK_ALL = 4239; // 12
+const static uint64_t SH_FLD_CONFIG_MRBSP_DIS_DYN_ADJ = 4240; // 3
+const static uint64_t SH_FLD_CONFIG_MRBSP_DIS_DYN_LVL_ADJ = 4241; // 3
+const static uint64_t SH_FLD_CONFIG_MRBSP_DIV2_COUNT_AT_EXP = 4242; // 3
+const static uint64_t SH_FLD_CONFIG_MRBSP_MAX_LEVEL = 4243; // 3
+const static uint64_t SH_FLD_CONFIG_MRBSP_MAX_LEVEL_LEN = 4244; // 3
+const static uint64_t SH_FLD_CONFIG_MRBSP_THRESH1 = 4245; // 3
+const static uint64_t SH_FLD_CONFIG_MRBSP_THRESH1_LEN = 4246; // 3
+const static uint64_t SH_FLD_CONFIG_MRBSP_THRESH2 = 4247; // 3
+const static uint64_t SH_FLD_CONFIG_MRBSP_THRESH2_LEN = 4248; // 3
+const static uint64_t SH_FLD_CONFIG_MRBSP_TRACK_ALL = 4249; // 12
+const static uint64_t SH_FLD_CONFIG_NPU = 4250; // 12
+const static uint64_t SH_FLD_CONFIG_NX = 4251; // 12
+const static uint64_t SH_FLD_CONFIG_PARITY = 4252; // 43
+const static uint64_t SH_FLD_CONFIG_PCIE = 4253; // 12
+const static uint64_t SH_FLD_CONFIG_PCIE_LEN = 4254; // 12
+const static uint64_t SH_FLD_CONFIG_PRB0 = 4255; // 24
+const static uint64_t SH_FLD_CONFIG_PRB0_LEN = 4256; // 24
+const static uint64_t SH_FLD_CONFIG_PRB1 = 4257; // 24
+const static uint64_t SH_FLD_CONFIG_PRB1_LEN = 4258; // 24
+const static uint64_t SH_FLD_CONFIG_PR_DMA_INJ = 4259; // 12
+const static uint64_t SH_FLD_CONFIG_PWR0 = 4260; // 24
+const static uint64_t SH_FLD_CONFIG_PWR0_LEN = 4261; // 24
+const static uint64_t SH_FLD_CONFIG_PWR1 = 4262; // 24
+const static uint64_t SH_FLD_CONFIG_PWR1_LEN = 4263; // 24
+const static uint64_t SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK = 4264; // 12
+const static uint64_t SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN = 4265; // 12
+const static uint64_t SH_FLD_CONFIG_REQ0 = 4266; // 24
+const static uint64_t SH_FLD_CONFIG_REQ0_LEN = 4267; // 24
+const static uint64_t SH_FLD_CONFIG_REQ1 = 4268; // 24
+const static uint64_t SH_FLD_CONFIG_REQ1_LEN = 4269; // 24
+const static uint64_t SH_FLD_CONFIG_RESERVED4 = 4270; // 12
+const static uint64_t SH_FLD_CONFIG_RSI_CORRENAB = 4271; // 12
+const static uint64_t SH_FLD_CONFIG_RSI_INJECT_ENABLE1 = 4272; // 12
+const static uint64_t SH_FLD_CONFIG_RSI_INJECT_ENABLE2 = 4273; // 12
+const static uint64_t SH_FLD_CONFIG_RXO_CORRENAB = 4274; // 12
+const static uint64_t SH_FLD_CONFIG_RXO_INJECT_ENABLE1 = 4275; // 12
+const static uint64_t SH_FLD_CONFIG_RXO_INJECT_ENABLE2 = 4276; // 12
+const static uint64_t SH_FLD_CONFIG_SIZE = 4277; // 24
+const static uint64_t SH_FLD_CONFIG_SIZE_LEN = 4278; // 24
+const static uint64_t SH_FLD_CONFIG_SKIP_G = 4279; // 12
+const static uint64_t SH_FLD_CONFIG_VAS = 4280; // 12
+const static uint64_t SH_FLD_CONFIG_XATS = 4281; // 24
+const static uint64_t SH_FLD_CONFIG_XATS_LEN = 4282; // 24
+const static uint64_t SH_FLD_CONFIRMED = 4283; // 64
+const static uint64_t SH_FLD_CONFLICT = 4284; // 1
+const static uint64_t SH_FLD_CONG = 4285; // 1
+const static uint64_t SH_FLD_CONG_LEN = 4286; // 1
+const static uint64_t SH_FLD_CONSEQ_PASS = 4287; // 8
+const static uint64_t SH_FLD_CONSEQ_PASS_LEN = 4288; // 8
+const static uint64_t SH_FLD_CONSUMED_BUF_COUNT = 4289; // 1
+const static uint64_t SH_FLD_CONSUMED_BUF_COUNT_LEN = 4290; // 1
+const static uint64_t SH_FLD_CONTENT = 4291; // 3
+const static uint64_t SH_FLD_CONTENT_LEN = 4292; // 3
+const static uint64_t SH_FLD_CONTINUOUS = 4293; // 2
+const static uint64_t SH_FLD_CONTROL = 4294; // 15
+const static uint64_t SH_FLD_CONTROL_ERR = 4295; // 24
+const static uint64_t SH_FLD_CONTROL_LEN = 4296; // 15
+const static uint64_t SH_FLD_CONTROL_N = 4297; // 2
+const static uint64_t SH_FLD_CONVERGED_END_COUNT = 4298; // 6
+const static uint64_t SH_FLD_CONVERGED_END_COUNT_LEN = 4299; // 6
+const static uint64_t SH_FLD_COPY_CKE_TO_SPARE_CKE = 4300; // 2
+const static uint64_t SH_FLD_COPY_LENGTH = 4301; // 2
+const static uint64_t SH_FLD_COPY_LENGTH_LEN = 4302; // 2
+const static uint64_t SH_FLD_CORE0_REQ_ACTIVE = 4303; // 12
+const static uint64_t SH_FLD_CORE1_REQ_ACTIVE = 4304; // 12
+const static uint64_t SH_FLD_COREID = 4305; // 1
+const static uint64_t SH_FLD_COREID_LEN = 4306; // 1
+const static uint64_t SH_FLD_CORES_ENABLED = 4307; // 1
+const static uint64_t SH_FLD_CORES_ENABLED_LEN = 4308; // 1
+const static uint64_t SH_FLD_CORE_CHECKSTOP = 4309; // 12
+const static uint64_t SH_FLD_CORE_CLK_SB_PULSE_MODE = 4310; // 6
+const static uint64_t SH_FLD_CORE_CLK_SB_PULSE_MODE_EN = 4311; // 6
+const static uint64_t SH_FLD_CORE_CLK_SB_PULSE_MODE_LEN = 4312; // 6
+const static uint64_t SH_FLD_CORE_CLK_SB_SPARE = 4313; // 6
+const static uint64_t SH_FLD_CORE_CLK_SB_STRENGTH = 4314; // 6
+const static uint64_t SH_FLD_CORE_CLK_SB_STRENGTH_LEN = 4315; // 6
+const static uint64_t SH_FLD_CORE_CLK_SW_RESCLK = 4316; // 6
+const static uint64_t SH_FLD_CORE_CLK_SW_RESCLK_LEN = 4317; // 6
+const static uint64_t SH_FLD_CORE_CLK_SW_SPARE = 4318; // 6
+const static uint64_t SH_FLD_CORE_CONFIG = 4319; // 2
+const static uint64_t SH_FLD_CORE_CONFIG_LEN = 4320; // 2
+const static uint64_t SH_FLD_CORE_EXT_INTR = 4321; // 1
+const static uint64_t SH_FLD_CORE_OR_SNP_REQ_ACTIVE = 4322; // 12
+const static uint64_t SH_FLD_CORE_RESET = 4323; // 1
+const static uint64_t SH_FLD_CORE_STEP = 4324; // 1
+const static uint64_t SH_FLD_CORE_STEP_SYNC_TX_ENABLE = 4325; // 1
+const static uint64_t SH_FLD_CORE_STEP_SYNC_TX_SYNC_DISABLE = 4326; // 1
+const static uint64_t SH_FLD_CORE_STEP_SYNC_TX_TRIGGER = 4327; // 1
+const static uint64_t SH_FLD_CORR_DIS_BR = 4328; // 3
+const static uint64_t SH_FLD_CORR_DIS_IR = 4329; // 3
+const static uint64_t SH_FLD_CORR_DIS_OR = 4330; // 3
+const static uint64_t SH_FLD_CORR_DIS_PR = 4331; // 3
+const static uint64_t SH_FLD_CORR_DIS_PT = 4332; // 3
+const static uint64_t SH_FLD_CORR_ERR = 4333; // 1
+const static uint64_t SH_FLD_COUNT = 4334; // 44
+const static uint64_t SH_FLD_COUNTER = 4335; // 43
+const static uint64_t SH_FLD_COUNTER0 = 4336; // 16
+const static uint64_t SH_FLD_COUNTER0_LEN = 4337; // 16
+const static uint64_t SH_FLD_COUNTER1 = 4338; // 16
+const static uint64_t SH_FLD_COUNTER1_LEN = 4339; // 16
+const static uint64_t SH_FLD_COUNTER2 = 4340; // 16
+const static uint64_t SH_FLD_COUNTER2_LEN = 4341; // 16
+const static uint64_t SH_FLD_COUNTER3 = 4342; // 16
+const static uint64_t SH_FLD_COUNTER3_LEN = 4343; // 16
+const static uint64_t SH_FLD_COUNTERA_0 = 4344; // 2
+const static uint64_t SH_FLD_COUNTERA_0_LEN = 4345; // 2
+const static uint64_t SH_FLD_COUNTERA_1 = 4346; // 2
+const static uint64_t SH_FLD_COUNTERA_1_LEN = 4347; // 2
+const static uint64_t SH_FLD_COUNTERA_2 = 4348; // 2
+const static uint64_t SH_FLD_COUNTERA_2_LEN = 4349; // 2
+const static uint64_t SH_FLD_COUNTERA_3 = 4350; // 2
+const static uint64_t SH_FLD_COUNTERA_3_LEN = 4351; // 2
+const static uint64_t SH_FLD_COUNTERB_0 = 4352; // 2
+const static uint64_t SH_FLD_COUNTERB_0_LEN = 4353; // 2
+const static uint64_t SH_FLD_COUNTERB_1 = 4354; // 2
+const static uint64_t SH_FLD_COUNTERB_1_LEN = 4355; // 2
+const static uint64_t SH_FLD_COUNTERB_2 = 4356; // 2
+const static uint64_t SH_FLD_COUNTERB_2_LEN = 4357; // 2
+const static uint64_t SH_FLD_COUNTERB_3 = 4358; // 2
+const static uint64_t SH_FLD_COUNTERB_3_LEN = 4359; // 2
+const static uint64_t SH_FLD_COUNTER_LEN = 4360; // 43
+const static uint64_t SH_FLD_COUNTER_LOAD_FLAG = 4361; // 2
+const static uint64_t SH_FLD_COUNTER_LOAD_VALUE = 4362; // 2
+const static uint64_t SH_FLD_COUNTER_LOAD_VALUE_LEN = 4363; // 2
+const static uint64_t SH_FLD_COUNTER_VALUE = 4364; // 1
+const static uint64_t SH_FLD_COUNTER_VALUE_LEN = 4365; // 1
+const static uint64_t SH_FLD_COUNT_0_47 = 4366; // 7
+const static uint64_t SH_FLD_COUNT_0_47_LEN = 4367; // 7
+const static uint64_t SH_FLD_COUNT_47 = 4368; // 1
+const static uint64_t SH_FLD_COUNT_47_LEN = 4369; // 1
+const static uint64_t SH_FLD_COUNT_DIS_BR = 4370; // 3
+const static uint64_t SH_FLD_COUNT_DIS_IR = 4371; // 3
+const static uint64_t SH_FLD_COUNT_DIS_OR = 4372; // 3
+const static uint64_t SH_FLD_COUNT_DIS_PR = 4373; // 3
+const static uint64_t SH_FLD_COUNT_DIS_PT = 4374; // 3
+const static uint64_t SH_FLD_COUNT_LEN = 4375; // 44
+const static uint64_t SH_FLD_COUNT_STATE_MASK = 4376; // 43
+const static uint64_t SH_FLD_COURSE_DIR_FLUSH_FAILED = 4377; // 2
+const static uint64_t SH_FLD_CO_MACHINE_HANG_ERR = 4378; // 12
+const static uint64_t SH_FLD_CO_UNSOLICITED_CRESP_ERR = 4379; // 12
+const static uint64_t SH_FLD_CO_UNSOLICITED_CRESP_ERR_LEN = 4380; // 12
+const static uint64_t SH_FLD_CP = 4381; // 2
+const static uint64_t SH_FLD_CPG = 4382; // 8
+const static uint64_t SH_FLD_CPHA = 4383; // 1
+const static uint64_t SH_FLD_CPISEL = 4384; // 20
+const static uint64_t SH_FLD_CPISEL_LEN = 4385; // 20
+const static uint64_t SH_FLD_CPI_TYPE = 4386; // 12
+const static uint64_t SH_FLD_CPI_TYPE_LEN = 4387; // 12
+const static uint64_t SH_FLD_CPLITE = 4388; // 2
+const static uint64_t SH_FLD_CPLITE_LEN = 4389; // 2
+const static uint64_t SH_FLD_CPLTMASK0 = 4390; // 43
+const static uint64_t SH_FLD_CPLTMASK0_LEN = 4391; // 43
+const static uint64_t SH_FLD_CPM_CAL_SET = 4392; // 43
+const static uint64_t SH_FLD_CPOL = 4393; // 1
+const static uint64_t SH_FLD_CPS = 4394; // 1
+const static uint64_t SH_FLD_CPS_LEN = 4395; // 1
+const static uint64_t SH_FLD_CP_LEN = 4396; // 2
+const static uint64_t SH_FLD_CP_RETRY_THRESH = 4397; // 4
+const static uint64_t SH_FLD_CP_RETRY_THRESH_LEN = 4398; // 4
+const static uint64_t SH_FLD_CQ_CERR_BITS = 4399; // 1
+const static uint64_t SH_FLD_CQ_CERR_BITS_LEN = 4400; // 1
+const static uint64_t SH_FLD_CQ_CERR_RESET = 4401; // 1
+const static uint64_t SH_FLD_CQ_DRAIN_THRESHOLD = 4402; // 1
+const static uint64_t SH_FLD_CQ_DRAIN_THRESHOLD_LEN = 4403; // 1
+const static uint64_t SH_FLD_CQ_ECC_CE_ERROR = 4404; // 2
+const static uint64_t SH_FLD_CQ_ECC_SUE_ERROR = 4405; // 2
+const static uint64_t SH_FLD_CQ_ECC_UE_ERROR = 4406; // 2
+const static uint64_t SH_FLD_CQ_FILL_THRESHOLD = 4407; // 1
+const static uint64_t SH_FLD_CQ_FILL_THRESHOLD_LEN = 4408; // 1
+const static uint64_t SH_FLD_CQ_LFSR_RESEED_EN = 4409; // 1
+const static uint64_t SH_FLD_CQ_LOGIC_HW_ERROR = 4410; // 2
+const static uint64_t SH_FLD_CQ_PB_LINK_ABORT = 4411; // 2
+const static uint64_t SH_FLD_CQ_PB_MASTER_FSM_HANG = 4412; // 2
+const static uint64_t SH_FLD_CQ_PB_OB_CE_ERROR = 4413; // 2
+const static uint64_t SH_FLD_CQ_PB_OB_UE_ERROR = 4414; // 2
+const static uint64_t SH_FLD_CQ_PB_PARITY_ERROR = 4415; // 2
+const static uint64_t SH_FLD_CQ_PB_RD_ADDR_ERROR = 4416; // 2
+const static uint64_t SH_FLD_CQ_PB_RD_LINK_ERROR = 4417; // 2
+const static uint64_t SH_FLD_CQ_PB_WR_ADDR_ERROR = 4418; // 2
+const static uint64_t SH_FLD_CQ_PB_WR_LINK_ERROR = 4419; // 2
+const static uint64_t SH_FLD_CQ_READ_RTY_RATIO = 4420; // 1
+const static uint64_t SH_FLD_CQ_READ_RTY_RATIO_LEN = 4421; // 1
+const static uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_HI = 4422; // 1
+const static uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_HI_LEN = 4423; // 1
+const static uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_LO = 4424; // 1
+const static uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_LO_LEN = 4425; // 1
+const static uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_01 = 4426; // 1
+const static uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_01_LEN = 4427; // 1
+const static uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_23 = 4428; // 1
+const static uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_23_LEN = 4429; // 1
+const static uint64_t SH_FLD_CR0_ATAG_PERR = 4430; // 1
+const static uint64_t SH_FLD_CR0_TTAG_PERR = 4431; // 1
+const static uint64_t SH_FLD_CR1_ATAG_PERR = 4432; // 1
+const static uint64_t SH_FLD_CR1_TTAG_PERR = 4433; // 1
+const static uint64_t SH_FLD_CR2_ATAG_PERR = 4434; // 1
+const static uint64_t SH_FLD_CR2_TTAG_PERR = 4435; // 1
+const static uint64_t SH_FLD_CR3_ATAG_PERR = 4436; // 1
+const static uint64_t SH_FLD_CR3_TTAG_PERR = 4437; // 1
+const static uint64_t SH_FLD_CRBKILL_WITH_ISN_UE = 4438; // 1
+const static uint64_t SH_FLD_CRB_ECC_SUE = 4439; // 1
+const static uint64_t SH_FLD_CRB_ECC_UE = 4440; // 1
+const static uint64_t SH_FLD_CRB_READS_ENBL = 4441; // 1
+const static uint64_t SH_FLD_CRB_READS_HALTED = 4442; // 1
+const static uint64_t SH_FLD_CRC_MODE = 4443; // 2
+const static uint64_t SH_FLD_CRD_REQUEST = 4444; // 1
+const static uint64_t SH_FLD_CREDIT_UPDATE_PENDING = 4445; // 6
+const static uint64_t SH_FLD_CREQ_AE_ALWAYS = 4446; // 6
+const static uint64_t SH_FLD_CREQ_BE_128 = 4447; // 6
+const static uint64_t SH_FLD_CRESP_0_4 = 4448; // 1
+const static uint64_t SH_FLD_CRESP_0_4_LEN = 4449; // 1
+const static uint64_t SH_FLD_CRESP_ATAG_P_ERR = 4450; // 12
+const static uint64_t SH_FLD_CRESP_ATAG_P_ERR_LEN = 4451; // 12
+const static uint64_t SH_FLD_CRESP_HANG = 4452; // 1
+const static uint64_t SH_FLD_CRESP_TTAG_P_ERR = 4453; // 12
+const static uint64_t SH_FLD_CRESP_TTAG_P_ERR_LEN = 4454; // 12
+const static uint64_t SH_FLD_CRITICAL_INTERRUPT = 4455; // 1
+const static uint64_t SH_FLD_CR_ATAG_PAR = 4456; // 1
+const static uint64_t SH_FLD_CR_TTAG_PAR = 4457; // 1
+const static uint64_t SH_FLD_CS0_INIT_CAL_VALUE = 4458; // 8
+const static uint64_t SH_FLD_CS1_INIT_CAL_VALUE = 4459; // 8
+const static uint64_t SH_FLD_CS2_INIT_CAL_VALUE = 4460; // 8
+const static uint64_t SH_FLD_CS3_INIT_CAL_VALUE = 4461; // 8
+const static uint64_t SH_FLD_CS4_INIT_CAL_VALUE = 4462; // 8
+const static uint64_t SH_FLD_CS5_INIT_CAL_VALUE = 4463; // 8
+const static uint64_t SH_FLD_CS6_INIT_CAL_VALUE = 4464; // 8
+const static uint64_t SH_FLD_CS7_INIT_CAL_VALUE = 4465; // 8
+const static uint64_t SH_FLD_CSEL = 4466; // 10
+const static uint64_t SH_FLD_CSEL_LEN = 4467; // 10
+const static uint64_t SH_FLD_CS_CHIP_ID_2N_MODE = 4468; // 2
+const static uint64_t SH_FLD_CTLE_GAIN_MAX = 4469; // 6
+const static uint64_t SH_FLD_CTLE_GAIN_MAX_LEN = 4470; // 6
+const static uint64_t SH_FLD_CTLE_UPDATE_MODE = 4471; // 6
+const static uint64_t SH_FLD_CTLR_HP_THRESH = 4472; // 3
+const static uint64_t SH_FLD_CTLR_HP_THRESH_LEN = 4473; // 3
+const static uint64_t SH_FLD_CTLW_HP_THRESH = 4474; // 3
+const static uint64_t SH_FLD_CTLW_HP_THRESH_LEN = 4475; // 3
+const static uint64_t SH_FLD_CTL_SM_0 = 4476; // 6
+const static uint64_t SH_FLD_CTL_SM_1 = 4477; // 6
+const static uint64_t SH_FLD_CTL_SM_2 = 4478; // 6
+const static uint64_t SH_FLD_CTL_SM_3 = 4479; // 6
+const static uint64_t SH_FLD_CTL_SM_4 = 4480; // 6
+const static uint64_t SH_FLD_CTL_SM_5 = 4481; // 6
+const static uint64_t SH_FLD_CTL_SM_6 = 4482; // 6
+const static uint64_t SH_FLD_CTL_SM_7 = 4483; // 6
+const static uint64_t SH_FLD_CTL_TRACE_EN = 4484; // 1
+const static uint64_t SH_FLD_CTL_TRACE_SEL = 4485; // 1
+const static uint64_t SH_FLD_CTRL_BUSY = 4486; // 1
+const static uint64_t SH_FLD_CTRL_CC_ABIST_RECOV_DISABLE_DC = 4487; // 43
+const static uint64_t SH_FLD_CTRL_CC_ABSTCLK_MUXSEL_DC = 4488; // 43
+const static uint64_t SH_FLD_CTRL_CC_DCTEST_DC = 4489; // 43
+const static uint64_t SH_FLD_CTRL_CC_FLUSHMODE_INH_DC = 4490; // 43
+const static uint64_t SH_FLD_CTRL_CC_FORCE_ALIGN_DC = 4491; // 43
+const static uint64_t SH_FLD_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC = 4492; // 43
+const static uint64_t SH_FLD_CTRL_CC_OFLOW_FEH_SEL_DC = 4493; // 43
+const static uint64_t SH_FLD_CTRL_CC_OTP_PRGMODE_DC = 4494; // 43
+const static uint64_t SH_FLD_CTRL_CC_PIN_LBIST_DC = 4495; // 43
+const static uint64_t SH_FLD_CTRL_CC_SCAN_PROTECT_DC = 4496; // 43
+const static uint64_t SH_FLD_CTRL_CC_SDIS_DC_N = 4497; // 43
+const static uint64_t SH_FLD_CTRL_CC_SSS_CALIBRATE_DC = 4498; // 43
+const static uint64_t SH_FLD_CTRL_EPS_MASK_VITL_PCB_ERR_DC = 4499; // 43
+const static uint64_t SH_FLD_CTRL_MISC_CLKDIV_SEL_DC = 4500; // 43
+const static uint64_t SH_FLD_CTRL_MISC_CLKDIV_SEL_DC_LEN = 4501; // 43
+const static uint64_t SH_FLD_CTRL_MISC_PROBE0_SEL_DC = 4502; // 43
+const static uint64_t SH_FLD_CTRL_MISC_PROBE0_SEL_DC_LEN = 4503; // 43
+const static uint64_t SH_FLD_CTRL_MISC_PROBE1_SEL_DC = 4504; // 43
+const static uint64_t SH_FLD_CTRL_MISC_PROBE1_SEL_DC_LEN = 4505; // 43
+const static uint64_t SH_FLD_CTRL_MISC_PROBE2_SEL_DC = 4506; // 43
+const static uint64_t SH_FLD_CTRL_MISC_PROBE2_SEL_DC_LEN = 4507; // 43
+const static uint64_t SH_FLD_CTRL_MISC_PROBE3_SEL_DC = 4508; // 43
+const static uint64_t SH_FLD_CTRL_MISC_PROBE3_SEL_DC_LEN = 4509; // 43
+const static uint64_t SH_FLD_CTRL_PARITY = 4510; // 43
+const static uint64_t SH_FLD_CT_COMPARE_VECTOR = 4511; // 2
+const static uint64_t SH_FLD_CT_COMPARE_VECTOR_LEN = 4512; // 2
+const static uint64_t SH_FLD_CURRENT_OPCG_MODE = 4513; // 43
+const static uint64_t SH_FLD_CURRENT_OPCG_MODE_LEN = 4514; // 43
+const static uint64_t SH_FLD_CUR_RD_ADDR = 4515; // 6
+const static uint64_t SH_FLD_CUR_RD_ADDR_LEN = 4516; // 6
+const static uint64_t SH_FLD_CUSTOM_INIT_WRITE = 4517; // 8
+const static uint64_t SH_FLD_CUSTOM_RD = 4518; // 8
+const static uint64_t SH_FLD_CUSTOM_WR = 4519; // 8
+const static uint64_t SH_FLD_CW_MIRROR = 4520; // 8
+const static uint64_t SH_FLD_CW_TYPE = 4521; // 12
+const static uint64_t SH_FLD_CW_TYPE_LEN = 4522; // 12
+const static uint64_t SH_FLD_CYCLECNT = 4523; // 3
+const static uint64_t SH_FLD_CYCLECNT_LEN = 4524; // 3
+const static uint64_t SH_FLD_CYCLES = 4525; // 12
+const static uint64_t SH_FLD_CYCLES_LEN = 4526; // 12
+const static uint64_t SH_FLD_CYCLE_COUNT = 4527; // 24
+const static uint64_t SH_FLD_CYCLE_COUNT_LEN = 4528; // 24
+const static uint64_t SH_FLD_C_ERR_RPT_HOLD_DATA = 4529; // 2
+const static uint64_t SH_FLD_C_ERR_RPT_HOLD_DATA_LEN = 4530; // 2
+const static uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT =
+    4531; // 4
+const static uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT_LEN =
+    4532; // 4
+const static uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT =
+    4533; // 4
+const static uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT_LEN =
+    4534; // 4
+const static uint64_t SH_FLD_DACTEST_HLMT = 4535; // 6
+const static uint64_t SH_FLD_DACTEST_HLMT_LEN = 4536; // 6
+const static uint64_t SH_FLD_DACTEST_LLMT = 4537; // 6
+const static uint64_t SH_FLD_DACTEST_LLMT_LEN = 4538; // 6
+const static uint64_t SH_FLD_DACTEST_RESET = 4539; // 6
+const static uint64_t SH_FLD_DACTEST_START = 4540; // 6
+const static uint64_t SH_FLD_DAC_BO_CFG = 4541; // 6
+const static uint64_t SH_FLD_DAC_BO_CFG_LEN = 4542; // 6
+const static uint64_t SH_FLD_DAT0 = 4543; // 1
+const static uint64_t SH_FLD_DAT0_LEN = 4544; // 1
+const static uint64_t SH_FLD_DAT1 = 4545; // 1
+const static uint64_t SH_FLD_DAT1_LEN = 4546; // 1
+const static uint64_t SH_FLD_DATA = 4547; // 377
+const static uint64_t SH_FLD_DATA_0_63 = 4548; // 2
+const static uint64_t SH_FLD_DATA_0_63_LEN = 4549; // 2
+const static uint64_t SH_FLD_DATA_64_79 = 4550; // 2
+const static uint64_t SH_FLD_DATA_64_79_LEN = 4551; // 2
+const static uint64_t SH_FLD_DATA_ARB_LFSR_CONFIG = 4552; // 1
+const static uint64_t SH_FLD_DATA_ARB_LFSR_CONFIG_LEN = 4553; // 1
+const static uint64_t SH_FLD_DATA_BUFFER = 4554; // 43
+const static uint64_t SH_FLD_DATA_COMPARE_BURST_SEL = 4555; // 2
+const static uint64_t SH_FLD_DATA_COMPARE_BURST_SEL_LEN = 4556; // 2
+const static uint64_t SH_FLD_DATA_DLY = 4557; // 1
+const static uint64_t SH_FLD_DATA_DLY_LEN = 4558; // 1
+const static uint64_t SH_FLD_DATA_HANG_DETECTED = 4559; // 2
+const static uint64_t SH_FLD_DATA_HANG_POLL_SCALE = 4560; // 2
+const static uint64_t SH_FLD_DATA_HANG_POLL_SCALE_LEN = 4561; // 2
+const static uint64_t SH_FLD_DATA_LEN = 4562; // 377
+const static uint64_t SH_FLD_DATA_MUX4_1MODE = 4563; // 8
+const static uint64_t SH_FLD_DATA_PARITY_ERR = 4564; // 4
+const static uint64_t SH_FLD_DATA_PIPE_CLR_ON_READ_MODE = 4565; // 6
+const static uint64_t SH_FLD_DATA_POISON_SUE_ENA = 4566; // 6
+const static uint64_t SH_FLD_DATA_POLL_PULSE_DIV = 4567; // 12
+const static uint64_t SH_FLD_DATA_POLL_PULSE_DIV_LEN = 4568; // 12
+const static uint64_t SH_FLD_DATA_REG0 = 4569; // 8
+const static uint64_t SH_FLD_DATA_REG0_LEN = 4570; // 8
+const static uint64_t SH_FLD_DATA_REG1 = 4571; // 8
+const static uint64_t SH_FLD_DATA_REG1_LEN = 4572; // 8
+const static uint64_t SH_FLD_DATA_REG_0_31 = 4573; // 1
+const static uint64_t SH_FLD_DATA_REG_0_31_LEN = 4574; // 1
+const static uint64_t SH_FLD_DATA_REQUEST_0 = 4575; // 2
+const static uint64_t SH_FLD_DATA_REQUEST_1 = 4576; // 2
+const static uint64_t SH_FLD_DATA_REQUEST_2 = 4577; // 2
+const static uint64_t SH_FLD_DATA_REQUEST_3 = 4578; // 2
+const static uint64_t SH_FLD_DATA_RTAG_P_ERR = 4579; // 12
+const static uint64_t SH_FLD_DATA_V_LT = 4580; // 43
+const static uint64_t SH_FLD_DAT_ARR_ECC_CORR_ENA = 4581; // 6
+const static uint64_t SH_FLD_DAT_ARR_ECC_SUE_ENA = 4582; // 6
+const static uint64_t SH_FLD_DAT_BUFFER_PAR_ERR = 4583; // 4
+const static uint64_t SH_FLD_DBG_BUS_BIT = 4584; // 8
+const static uint64_t SH_FLD_DBG_HALT = 4585; // 1
+const static uint64_t SH_FLD_DBG_SEL_IN = 4586; // 8
+const static uint64_t SH_FLD_DBG_SEL_PWCTL_DEBUG = 4587; // 8
+const static uint64_t SH_FLD_DBG_SEL_PWSEQ0_DEBUG_0 = 4588; // 8
+const static uint64_t SH_FLD_DBG_SEL_PWSEQ0_DEBUG_1 = 4589; // 8
+const static uint64_t SH_FLD_DBG_SEL_PWSEQ1_DEBUG_0 = 4590; // 8
+const static uint64_t SH_FLD_DBG_SEL_PWSEQ1_DEBUG_1 = 4591; // 8
+const static uint64_t SH_FLD_DBG_SEL_PWSEQ2_DEBUG_0 = 4592; // 8
+const static uint64_t SH_FLD_DBG_SEL_PWSEQ2_DEBUG_1 = 4593; // 8
+const static uint64_t SH_FLD_DBG_SEL_PWSEQ3_DEBUG_0 = 4594; // 8
+const static uint64_t SH_FLD_DBG_SEL_PWSEQ3_DEBUG_1 = 4595; // 8
+const static uint64_t SH_FLD_DBG_SEL_PWSEQ4_DEBUG_0 = 4596; // 8
+const static uint64_t SH_FLD_DBG_SEL_PWSEQ4_DEBUG_1 = 4597; // 8
+const static uint64_t SH_FLD_DBG_SEL_PWSEQ5_DEBUG_0 = 4598; // 8
+const static uint64_t SH_FLD_DBG_SEL_PWSEQ5_DEBUG_1 = 4599; // 8
+const static uint64_t SH_FLD_DBG_SEL_SEC_WDFRD_DEBUG_0 = 4600; // 8
+const static uint64_t SH_FLD_DBG_SEL_SEC_WDFRD_DEBUG_1 = 4601; // 8
+const static uint64_t SH_FLD_DBG_SEL_WDF = 4602; // 8
+const static uint64_t SH_FLD_DBG_SEL_WDFMGR_DEBUG = 4603; // 8
+const static uint64_t SH_FLD_DBG_SEL_WDFRD_DEBUG_0 = 4604; // 8
+const static uint64_t SH_FLD_DBG_SEL_WDFRD_DEBUG_1 = 4605; // 8
+const static uint64_t SH_FLD_DBG_SEL_WDFWR_DEBUG_0 = 4606; // 8
+const static uint64_t SH_FLD_DBG_SEL_WDFWR_DEBUG_1 = 4607; // 8
+const static uint64_t SH_FLD_DBG_UNCONDITIONAL_EVENT = 4608; // 1
+const static uint64_t SH_FLD_DCACHE_ERR = 4609; // 4
+const static uint64_t SH_FLD_DCACHE_TAG_ADDR = 4610; // 4
+const static uint64_t SH_FLD_DCACHE_TAG_ADDR_LEN = 4611; // 4
+const static uint64_t SH_FLD_DCLKSEL = 4612; // 6
+const static uint64_t SH_FLD_DCLKSEL_LEN = 4613; // 6
+const static uint64_t SH_FLD_DCOMP_ENABLE = 4614; // 1
+const static uint64_t SH_FLD_DCOMP_ENGINE_BUSY = 4615; // 1
+const static uint64_t SH_FLD_DCOMP_ERR = 4616; // 1
+const static uint64_t SH_FLD_DCO_DECR = 4617; // 6
+const static uint64_t SH_FLD_DCO_INCR = 4618; // 6
+const static uint64_t SH_FLD_DCO_OVERRIDE = 4619; // 6
+const static uint64_t SH_FLD_DCU_RNW = 4620; // 1
+const static uint64_t SH_FLD_DCU_TIMEOUT_ERROR = 4621; // 1
+const static uint64_t SH_FLD_DD2_FIX_DIS = 4622; // 8
+const static uint64_t SH_FLD_DDC_CFG = 4623; // 120
+const static uint64_t SH_FLD_DDC_CFG_LEN = 4624; // 120
+const static uint64_t SH_FLD_DDR4_CMD_SIG_REDUCTION = 4625; // 8
+const static uint64_t SH_FLD_DDR4_IPW_LOOP_DIS = 4626; // 8
+const static uint64_t SH_FLD_DDR4_LATENCY_SW = 4627; // 8
+const static uint64_t SH_FLD_DDR4_MRS_CMD_DQ_EN = 4628; // 8
+const static uint64_t SH_FLD_DDR4_VLEVEL_BANK_GROUP = 4629; // 8
+const static uint64_t SH_FLD_DDR_ACTN = 4630; // 64
+const static uint64_t SH_FLD_DDR_ADDRESS = 4631; // 8
+const static uint64_t SH_FLD_DDR_ADDRESS_0 = 4632; // 2
+const static uint64_t SH_FLD_DDR_ADDRESS_0_13 = 4633; // 62
+const static uint64_t SH_FLD_DDR_ADDRESS_0_13_LEN = 4634; // 62
+const static uint64_t SH_FLD_DDR_ADDRESS_0_LEN = 4635; // 2
+const static uint64_t SH_FLD_DDR_ADDRESS_14 = 4636; // 62
+const static uint64_t SH_FLD_DDR_ADDRESS_15 = 4637; // 62
+const static uint64_t SH_FLD_DDR_ADDRESS_16 = 4638; // 62
+const static uint64_t SH_FLD_DDR_ADDRESS_17 = 4639; // 62
+const static uint64_t SH_FLD_DDR_BANK_0_1 = 4640; // 64
+const static uint64_t SH_FLD_DDR_BANK_0_1_LEN = 4641; // 64
+const static uint64_t SH_FLD_DDR_BANK_2 = 4642; // 64
+const static uint64_t SH_FLD_DDR_BANK_GROUP_0 = 4643; // 64
+const static uint64_t SH_FLD_DDR_BANK_GROUP_1 = 4644; // 64
+const static uint64_t SH_FLD_DDR_CALIBRATION_ENABLE = 4645; // 64
+const static uint64_t SH_FLD_DDR_CAL_RANK = 4646; // 64
+const static uint64_t SH_FLD_DDR_CAL_RANK_LEN = 4647; // 64
+const static uint64_t SH_FLD_DDR_CAL_RESET_TIMEOUT = 4648; // 16
+const static uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT = 4649; // 2
+const static uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT_LEN = 4650; // 2
+const static uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT_MULT = 4651; // 2
+const static uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT_MULT_LEN = 4652; // 2
+const static uint64_t SH_FLD_DDR_CAL_TIMEOUT_ERR = 4653; // 16
+const static uint64_t SH_FLD_DDR_CAL_TYPE = 4654; // 64
+const static uint64_t SH_FLD_DDR_CAL_TYPE_LEN = 4655; // 64
+const static uint64_t SH_FLD_DDR_CID_0_1 = 4656; // 64
+const static uint64_t SH_FLD_DDR_CID_0_1_LEN = 4657; // 64
+const static uint64_t SH_FLD_DDR_CID_2 = 4658; // 64
+const static uint64_t SH_FLD_DDR_CKE = 4659; // 64
+const static uint64_t SH_FLD_DDR_CKE_LEN = 4660; // 64
+const static uint64_t SH_FLD_DDR_CSN_0_1 = 4661; // 64
+const static uint64_t SH_FLD_DDR_CSN_0_1_LEN = 4662; // 64
+const static uint64_t SH_FLD_DDR_CSN_2_3 = 4663; // 64
+const static uint64_t SH_FLD_DDR_CSN_2_3_LEN = 4664; // 64
+const static uint64_t SH_FLD_DDR_IF_SM_1HOT = 4665; // 8
+const static uint64_t SH_FLD_DDR_INVALID_ACCESS = 4666; // 8
+const static uint64_t SH_FLD_DDR_MBA_EVENT_N = 4667; // 16
+const static uint64_t SH_FLD_DDR_ODT = 4668; // 64
+const static uint64_t SH_FLD_DDR_ODT_LEN = 4669; // 64
+const static uint64_t SH_FLD_DDR_PARITY = 4670; // 64
+const static uint64_t SH_FLD_DDR_PARITY_ENABLE = 4671; // 2
+const static uint64_t SH_FLD_DDR_RESETN = 4672; // 64
+const static uint64_t SH_FLD_DEAD = 4673; // 43
+const static uint64_t SH_FLD_DEBUG = 4674; // 2
+const static uint64_t SH_FLD_DEBUGGER = 4675; // 25
+const static uint64_t SH_FLD_DEBUG_BOLT_ON_CONTROL_BITS = 4676; // 1
+const static uint64_t SH_FLD_DEBUG_BOLT_ON_CONTROL_BITS_LEN = 4677; // 1
+const static uint64_t SH_FLD_DEBUG_BUS_SEL_LO = 4678; // 8
+const static uint64_t SH_FLD_DEBUG_LEN = 4679; // 2
+const static uint64_t SH_FLD_DEBUG_OCI_MODE = 4680; // 1
+const static uint64_t SH_FLD_DEBUG_OCI_MODE_LEN = 4681; // 1
+const static uint64_t SH_FLD_DEBUG_PB_NOT_OCI = 4682; // 1
+const static uint64_t SH_FLD_DEBUG_TRIGGER = 4683; // 24
+const static uint64_t SH_FLD_DEBUG__BUS_SEL_HI = 4684; // 8
+const static uint64_t SH_FLD_DEBUG__BUS_SEL_HI_LEN = 4685; // 8
+const static uint64_t SH_FLD_DECONFIGURED_INTR = 4686; // 24
+const static uint64_t SH_FLD_DECOUPLE_EDGE_A = 4687; // 48
+const static uint64_t SH_FLD_DECOUPLE_EDGE_B = 4688; // 48
+const static uint64_t SH_FLD_DEC_EXIT_ENABLE = 4689; // 96
+const static uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_FSP = 4690; // 30
+const static uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_FSP_LEN = 4691; // 30
+const static uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_HYP = 4692; // 30
+const static uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_HYP_LEN = 4693; // 30
+const static uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_OCC = 4694; // 30
+const static uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_OCC_LEN = 4695; // 30
+const static uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_OTR = 4696; // 30
+const static uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_OTR_LEN = 4697; // 30
+const static uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_FSP = 4698; // 30
+const static uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_FSP_LEN = 4699; // 30
+const static uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_HYP = 4700; // 30
+const static uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_HYP_LEN = 4701; // 30
+const static uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_OCC = 4702; // 30
+const static uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_OCC_LEN = 4703; // 30
+const static uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_OTR = 4704; // 30
+const static uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_OTR_LEN = 4705; // 30
+const static uint64_t SH_FLD_DEF_VALUES = 4706; // 8
+const static uint64_t SH_FLD_DEF_VALUES_LEN = 4707; // 8
+const static uint64_t SH_FLD_DEGLITCH_CLK_DLY = 4708; // 1
+const static uint64_t SH_FLD_DEGLITCH_CLK_DLY_LEN = 4709; // 1
+const static uint64_t SH_FLD_DEGLITCH_DATA_DLY = 4710; // 1
+const static uint64_t SH_FLD_DEGLITCH_DATA_DLY_LEN = 4711; // 1
+const static uint64_t SH_FLD_DELAY = 4712; // 1
+const static uint64_t SH_FLD_DELAY1_ID = 4713; // 12
+const static uint64_t SH_FLD_DELAY1_ID_LEN = 4714; // 12
+const static uint64_t SH_FLD_DELAY1_VALID = 4715; // 12
+const static uint64_t SH_FLD_DELAY2_ID = 4716; // 12
+const static uint64_t SH_FLD_DELAY2_ID_LEN = 4717; // 12
+const static uint64_t SH_FLD_DELAY2_VALID = 4718; // 12
+const static uint64_t SH_FLD_DELAY3_ID = 4719; // 12
+const static uint64_t SH_FLD_DELAY3_ID_LEN = 4720; // 12
+const static uint64_t SH_FLD_DELAY3_VALID = 4721; // 12
+const static uint64_t SH_FLD_DELAY4_ID = 4722; // 12
+const static uint64_t SH_FLD_DELAY4_ID_LEN = 4723; // 12
+const static uint64_t SH_FLD_DELAY4_VALID = 4724; // 12
+const static uint64_t SH_FLD_DELAY5_ID = 4725; // 12
+const static uint64_t SH_FLD_DELAY5_ID_LEN = 4726; // 12
+const static uint64_t SH_FLD_DELAY5_VALID = 4727; // 12
+const static uint64_t SH_FLD_DELAY6_ID = 4728; // 12
+const static uint64_t SH_FLD_DELAY6_ID_LEN = 4729; // 12
+const static uint64_t SH_FLD_DELAY6_VALID = 4730; // 12
+const static uint64_t SH_FLD_DELAY7_ID = 4731; // 12
+const static uint64_t SH_FLD_DELAY7_ID_LEN = 4732; // 12
+const static uint64_t SH_FLD_DELAY7_VALID = 4733; // 12
+const static uint64_t SH_FLD_DELAY8_ID = 4734; // 12
+const static uint64_t SH_FLD_DELAY8_ID_LEN = 4735; // 12
+const static uint64_t SH_FLD_DELAY8_VALID = 4736; // 12
+const static uint64_t SH_FLD_DELAYED_PAR = 4737; // 8
+const static uint64_t SH_FLD_DELAYG = 4738; // 32
+const static uint64_t SH_FLD_DELAYG_LEN = 4739; // 32
+const static uint64_t SH_FLD_DELAY_ADJUST_DISABLE = 4740; // 1
+const static uint64_t SH_FLD_DELAY_ADJUST_VALUE = 4741; // 1
+const static uint64_t SH_FLD_DELAY_ADJUST_VALUE_LEN = 4742; // 1
+const static uint64_t SH_FLD_DELAY_DISABLE = 4743; // 1
+const static uint64_t SH_FLD_DELAY_LCLKR = 4744; // 43
+const static uint64_t SH_FLD_DELAY_LEN = 4745; // 1
+const static uint64_t SH_FLD_DELAY_LINE_CTL_OVERRIDE = 4746; // 8
+const static uint64_t SH_FLD_DEQUEUED_EOT_FLAG = 4747; // 1
+const static uint64_t SH_FLD_DESKEW_DONE = 4748; // 4
+const static uint64_t SH_FLD_DESKEW_FAILED = 4749; // 4
+const static uint64_t SH_FLD_DESKEW_MAXSKEW_GRP = 4750; // 4
+const static uint64_t SH_FLD_DESKEW_MAXSKEW_GRP_LEN = 4751; // 4
+const static uint64_t SH_FLD_DESKEW_MAX_LIMIT = 4752; // 4
+const static uint64_t SH_FLD_DESKEW_MAX_LIMIT_LEN = 4753; // 4
+const static uint64_t SH_FLD_DESKEW_MINSKEW_GRP = 4754; // 4
+const static uint64_t SH_FLD_DESKEW_MINSKEW_GRP_LEN = 4755; // 4
+const static uint64_t SH_FLD_DESKEW_RATE = 4756; // 8
+const static uint64_t SH_FLD_DESKEW_SEQ_GCRMSG = 4757; // 4
+const static uint64_t SH_FLD_DESKEW_SEQ_GCRMSG_LEN = 4758; // 4
+const static uint64_t SH_FLD_DESKEW_SKMAX_GCRMSG = 4759; // 4
+const static uint64_t SH_FLD_DESKEW_SKMAX_GCRMSG_LEN = 4760; // 4
+const static uint64_t SH_FLD_DESKEW_SKMIN_GCRMSG = 4761; // 4
+const static uint64_t SH_FLD_DESKEW_SKMIN_GCRMSG_LEN = 4762; // 4
+const static uint64_t SH_FLD_DEST_CHIPID = 4763; // 1
+const static uint64_t SH_FLD_DEST_CHIPID_LEN = 4764; // 1
+const static uint64_t SH_FLD_DEST_GROUPID = 4765; // 1
+const static uint64_t SH_FLD_DEST_GROUPID_LEN = 4766; // 1
+const static uint64_t SH_FLD_DEVICE = 4767; // 1
+const static uint64_t SH_FLD_DEVICE_ADDRESS_0 = 4768; // 1
+const static uint64_t SH_FLD_DEVICE_ADDRESS_0_LEN = 4769; // 1
+const static uint64_t SH_FLD_DEVICE_ADDRESS_1 = 4770; // 1
+const static uint64_t SH_FLD_DEVICE_ADDRESS_1_LEN = 4771; // 1
+const static uint64_t SH_FLD_DEVICE_ADDRESS_2 = 4772; // 1
+const static uint64_t SH_FLD_DEVICE_ADDRESS_2_LEN = 4773; // 1
+const static uint64_t SH_FLD_DEVICE_ADDRESS_3 = 4774; // 1
+const static uint64_t SH_FLD_DEVICE_ADDRESS_3_LEN = 4775; // 1
+const static uint64_t SH_FLD_DEVICE_ID = 4776; // 4
+const static uint64_t SH_FLD_DEVICE_ID_LEN = 4777; // 4
+const static uint64_t SH_FLD_DFE_CA_CFG = 4778; // 6
+const static uint64_t SH_FLD_DFE_CA_CFG_LEN = 4779; // 6
+const static uint64_t SH_FLD_DFE_CONVERGED_CNT_MAX = 4780; // 6
+const static uint64_t SH_FLD_DFE_CONVERGED_CNT_MAX_LEN = 4781; // 6
+const static uint64_t SH_FLD_DGD_AE_ALWAYS = 4782; // 6
+const static uint64_t SH_FLD_DGD_BE_128 = 4783; // 6
+const static uint64_t SH_FLD_DGEN_RNDD_DATA_MAPPING = 4784; // 2
+const static uint64_t SH_FLD_DGEN_RNDD_DATA_MAPPING_LEN = 4785; // 2
+const static uint64_t SH_FLD_DGEN_RNDD_SEED0 = 4786; // 2
+const static uint64_t SH_FLD_DGEN_RNDD_SEED0_LEN = 4787; // 2
+const static uint64_t SH_FLD_DGEN_RNDD_SEED1 = 4788; // 2
+const static uint64_t SH_FLD_DGEN_RNDD_SEED1_LEN = 4789; // 2
+const static uint64_t SH_FLD_DGEN_RNDD_SEED2 = 4790; // 2
+const static uint64_t SH_FLD_DGEN_RNDD_SEED2_LEN = 4791; // 2
+const static uint64_t SH_FLD_DI1_N = 4792; // 43
+const static uint64_t SH_FLD_DI2_N = 4793; // 43
+const static uint64_t SH_FLD_DIAG = 4794; // 1
+const static uint64_t SH_FLD_DIAG_0 = 4795; // 1
+const static uint64_t SH_FLD_DIAG_1 = 4796; // 1
+const static uint64_t SH_FLD_DIAG_2 = 4797; // 1
+const static uint64_t SH_FLD_DIAG_3 = 4798; // 1
+const static uint64_t SH_FLD_DIB01_ERR = 4799; // 2
+const static uint64_t SH_FLD_DIB01_SPARE = 4800; // 1
+const static uint64_t SH_FLD_DIB01_SPARE_LEN = 4801; // 1
+const static uint64_t SH_FLD_DIB23_ERR = 4802; // 2
+const static uint64_t SH_FLD_DIB45_ERR = 4803; // 2
+const static uint64_t SH_FLD_DIB67_ERR = 4804; // 1
+const static uint64_t SH_FLD_DIB67_SPARE = 4805; // 1
+const static uint64_t SH_FLD_DIB67_SPARE_LEN = 4806; // 1
+const static uint64_t SH_FLD_DIGITAL_EYE = 4807; // 8
+const static uint64_t SH_FLD_DIRECT_ATTACH_MODE = 4808; // 4
+const static uint64_t SH_FLD_DIRECT_BRIDGE_SOURCE = 4809; // 1
+const static uint64_t SH_FLD_DIR_CE_DETECTED = 4810; // 12
+const static uint64_t SH_FLD_DIR_SBCE_REPAIR_FAILED = 4811; // 12
+const static uint64_t SH_FLD_DIR_STUCK_BIT_CE = 4812; // 12
+const static uint64_t SH_FLD_DIR_UE_DETECTED = 4813; // 12
+const static uint64_t SH_FLD_DISABLE = 4814; // 1
+const static uint64_t SH_FLD_DISABLE_1 = 4815; // 1
+const static uint64_t SH_FLD_DISABLE_1_LEN = 4816; // 1
+const static uint64_t SH_FLD_DISABLE_2 = 4817; // 1
+const static uint64_t SH_FLD_DISABLE_2K_SPEC_FILTER = 4818; // 4
+const static uint64_t SH_FLD_DISABLE_2N_MODE = 4819; // 2
+const static uint64_t SH_FLD_DISABLE_2_LEN = 4820; // 1
+const static uint64_t SH_FLD_DISABLE_ALL_SPEC_OPS = 4821; // 4
+const static uint64_t SH_FLD_DISABLE_BANK_PDWN = 4822; // 2
+const static uint64_t SH_FLD_DISABLE_BYPASS_IN_READ_DATAFLOW = 4823; // 4
+const static uint64_t SH_FLD_DISABLE_CENTAUR_BAD_CRESP = 4824; // 4
+const static uint64_t SH_FLD_DISABLE_CENTAUR_CMD_PREFETCH = 4825; // 4
+const static uint64_t SH_FLD_DISABLE_CENTAUR_CMD_PREFETCH_LEN = 4826; // 4
+const static uint64_t SH_FLD_DISABLE_CHARB_BYPASS = 4827; // 4
+const static uint64_t SH_FLD_DISABLE_CHECKSTOP = 4828; // 1
+const static uint64_t SH_FLD_DISABLE_CI = 4829; // 4
+const static uint64_t SH_FLD_DISABLE_CI_LEN = 4830; // 4
+const static uint64_t SH_FLD_DISABLE_CL_AO_QUEUES = 4831; // 4
+const static uint64_t SH_FLD_DISABLE_COMMAND_BYPASS = 4832; // 4
+const static uint64_t SH_FLD_DISABLE_COMMAND_BYPASS_LEN = 4833; // 4
+const static uint64_t SH_FLD_DISABLE_COMPRESSION = 4834; // 90
+const static uint64_t SH_FLD_DISABLE_CRC_ECC_BYPASS = 4835; // 4
+const static uint64_t SH_FLD_DISABLE_CRC_ECC_BYPASS_LEN = 4836; // 4
+const static uint64_t SH_FLD_DISABLE_CRC_ECC_FP_BYPASS = 4837; // 4
+const static uint64_t SH_FLD_DISABLE_DROPABLE = 4838; // 8
+const static uint64_t SH_FLD_DISABLE_ECC = 4839; // 1
+const static uint64_t SH_FLD_DISABLE_ECC_ARRAY_CHK = 4840; // 2
+const static uint64_t SH_FLD_DISABLE_ECC_ARRAY_CORRECTION = 4841; // 2
+const static uint64_t SH_FLD_DISABLE_ECC_CHK = 4842; // 1
+const static uint64_t SH_FLD_DISABLE_ECC_CORRECTION = 4843; // 1
+const static uint64_t SH_FLD_DISABLE_ECC_COR_GXC_PSI = 4844; // 1
+const static uint64_t SH_FLD_DISABLE_ECC_COR_RXRF_PSI = 4845; // 1
+const static uint64_t SH_FLD_DISABLE_ECC_COR_TXRF_PSI = 4846; // 1
+const static uint64_t SH_FLD_DISABLE_ERR_CMD = 4847; // 1
+const static uint64_t SH_FLD_DISABLE_EXTRA_FIFO_ACCESSES = 4848; // 1
+const static uint64_t SH_FLD_DISABLE_EXTRA_HASH_ACCESSES = 4849; // 1
+const static uint64_t SH_FLD_DISABLE_FAR_HISTORY = 4850; // 1
+const static uint64_t SH_FLD_DISABLE_FASTPATH = 4851; // 4
+const static uint64_t SH_FLD_DISABLE_FENCE_RESET = 4852; // 4
+const static uint64_t SH_FLD_DISABLE_FLOW_SCOPE = 4853; // 1
+const static uint64_t SH_FLD_DISABLE_FP_COMMAND_BYPASS = 4854; // 4
+const static uint64_t SH_FLD_DISABLE_FP_M_BIT = 4855; // 4
+const static uint64_t SH_FLD_DISABLE_G = 4856; // 1
+const static uint64_t SH_FLD_DISABLE_G_RD = 4857; // 1
+const static uint64_t SH_FLD_DISABLE_G_WR = 4858; // 1
+const static uint64_t SH_FLD_DISABLE_H1_CLEAR = 4859; // 6
+const static uint64_t SH_FLD_DISABLE_HIGH_PRIORITY = 4860; // 4
+const static uint64_t SH_FLD_DISABLE_HIGH_PRIORITY_LEN = 4861; // 4
+const static uint64_t SH_FLD_DISABLE_HIT_UNDER_BARRIER = 4862; // 1
+const static uint64_t SH_FLD_DISABLE_HTM_CMD = 4863; // 1
+const static uint64_t SH_FLD_DISABLE_INJECT = 4864; // 1
+const static uint64_t SH_FLD_DISABLE_LFSR = 4865; // 1
+const static uint64_t SH_FLD_DISABLE_LN = 4866; // 1
+const static uint64_t SH_FLD_DISABLE_LN_RD = 4867; // 1
+const static uint64_t SH_FLD_DISABLE_LN_WR = 4868; // 1
+const static uint64_t SH_FLD_DISABLE_LPC_CMDS = 4869; // 3
+const static uint64_t SH_FLD_DISABLE_MDI0 = 4870; // 4
+const static uint64_t SH_FLD_DISABLE_MDI0_LEN = 4871; // 4
+const static uint64_t SH_FLD_DISABLE_MEMCTL_CAL = 4872; // 8
+const static uint64_t SH_FLD_DISABLE_NEAR_HISTORY = 4873; // 1
+const static uint64_t SH_FLD_DISABLE_NN_RD = 4874; // 1
+const static uint64_t SH_FLD_DISABLE_NN_RN = 4875; // 1
+const static uint64_t SH_FLD_DISABLE_NN_WR = 4876; // 1
+const static uint64_t SH_FLD_DISABLE_PARITY_CHECKER = 4877; // 8
+const static uint64_t SH_FLD_DISABLE_PCB_ITR = 4878; // 43
+const static uint64_t SH_FLD_DISABLE_PMU_SNOOPING = 4879; // 1
+const static uint64_t SH_FLD_DISABLE_PTAG_IN_AIBTAG = 4880; // 1
+const static uint64_t SH_FLD_DISABLE_RCMD_CLKGATE = 4881; // 3
+const static uint64_t SH_FLD_DISABLE_RESET_2K_COUNT_IF_HINT_BIT_SET = 4882; // 4
+const static uint64_t SH_FLD_DISABLE_RETRY_LOST_CLAIM = 4883; // 4
+const static uint64_t SH_FLD_DISABLE_SHARD_PRESP_ABORT = 4884; // 4
+const static uint64_t SH_FLD_DISABLE_SPEC_DISABLE_HINT_BIT = 4885; // 4
+const static uint64_t SH_FLD_DISABLE_SPEC_OP = 4886; // 4
+const static uint64_t SH_FLD_DISABLE_SPEC_OP_LEN = 4887; // 4
+const static uint64_t SH_FLD_DISABLE_SPEC_SOURCE_SCOPE = 4888; // 4
+const static uint64_t SH_FLD_DISABLE_SPEC_SOURCE_SCOPE_LEN = 4889; // 4
+const static uint64_t SH_FLD_DISABLE_STICKINESS = 4890; // 43
+const static uint64_t SH_FLD_DISABLE_TIMEOUT_AND_RETRY = 4891; // 1
+const static uint64_t SH_FLD_DISABLE_TOD_CMD = 4892; // 1
+const static uint64_t SH_FLD_DISABLE_TRACE_CMD = 4893; // 1
+const static uint64_t SH_FLD_DISABLE_VG_NOT_SYS = 4894; // 1
+const static uint64_t SH_FLD_DISABLE_VG_RD = 4895; // 1
+const static uint64_t SH_FLD_DISABLE_VG_WR = 4896; // 1
+const static uint64_t SH_FLD_DISABLE_WRP = 4897; // 1
+const static uint64_t SH_FLD_DISABLE_XSCOM_CMD = 4898; // 1
+const static uint64_t SH_FLD_DISPATCH_SLOT_KILLED_CNT = 4899; // 1
+const static uint64_t SH_FLD_DISPATCH_SLOT_KILLED_CNT_LEN = 4900; // 1
+const static uint64_t SH_FLD_DISTRIBUTION_BROADCAST_MODE_ENABLE = 4901; // 1
+const static uint64_t SH_FLD_DISTR_STEP_SYNC_TX_DISABLE = 4902; // 1
+const static uint64_t SH_FLD_DISTR_STEP_SYNC_TX_SYNC_DISABLE = 4903; // 1
+const static uint64_t SH_FLD_DISTR_STEP_SYNC_TX_TRIGGER = 4904; // 1
+const static uint64_t SH_FLD_DIS_AIB_IN_ECC_CORRECTION = 4905; // 1
+const static uint64_t SH_FLD_DIS_ARX_ECC_CORRECTION = 4906; // 1
+const static uint64_t SH_FLD_DIS_AT_SRAM_ECC_CORRECTION = 4907; // 1
+const static uint64_t SH_FLD_DIS_BAR_SRAM_ECC_CORRECTION = 4908; // 1
+const static uint64_t SH_FLD_DIS_CHGRATE_COUNT = 4909; // 1
+const static uint64_t SH_FLD_DIS_CPM_BUBBLE_CORR = 4910; // 43
+const static uint64_t SH_FLD_DIS_CTRLBUF_ECC_CORRECTION = 4911; // 1
+const static uint64_t SH_FLD_DIS_DATA_ECC_CORRECTION = 4912; // 3
+const static uint64_t SH_FLD_DIS_DATA_ECC_CORRECTION_LEN = 4913; // 3
+const static uint64_t SH_FLD_DIS_DMA_W = 4914; // 1
+const static uint64_t SH_FLD_DIS_ECCCHK = 4915; // 1
+const static uint64_t SH_FLD_DIS_ECCCHK_CLO = 4916; // 1
+const static uint64_t SH_FLD_DIS_ECCCHK_IN = 4917; // 1
+const static uint64_t SH_FLD_DIS_ECCCHK_LDO = 4918; // 1
+const static uint64_t SH_FLD_DIS_ECCCHK_STO = 4919; // 1
+const static uint64_t SH_FLD_DIS_ECCCHK_WRO = 4920; // 1
+const static uint64_t SH_FLD_DIS_GLOB_SCOM = 4921; // 2
+const static uint64_t SH_FLD_DIS_IRQ_ECC_CORRECTION = 4922; // 1
+const static uint64_t SH_FLD_DIS_MASTER_RD_PIPE = 4923; // 1
+const static uint64_t SH_FLD_DIS_MASTER_WR_PIPE = 4924; // 1
+const static uint64_t SH_FLD_DIS_MSTID_MATCH_PREF_INV = 4925; // 1
+const static uint64_t SH_FLD_DIS_NCNP = 4926; // 1
+const static uint64_t SH_FLD_DIS_REARB = 4927; // 1
+const static uint64_t SH_FLD_DIS_RECOVERY = 4928; // 24
+const static uint64_t SH_FLD_DIS_REREQUEST_TO = 4929; // 1
+const static uint64_t SH_FLD_DIS_SLAVE_RDPIPE = 4930; // 1
+const static uint64_t SH_FLD_DIS_SLAVE_WRPIPE = 4931; // 1
+const static uint64_t SH_FLD_DIS_STATE_ECC_CORRECTION = 4932; // 3
+const static uint64_t SH_FLD_DIS_STATE_ECC_CORRECTION_LEN = 4933; // 1
+const static uint64_t SH_FLD_DIS_TAG_ECC_CORRECTION = 4934; // 3
+const static uint64_t SH_FLD_DIS_TAG_ECC_CORRECTION_LEN = 4935; // 3
+const static uint64_t SH_FLD_DIS_TAG_SRAM_ECC_CORRECTION = 4936; // 1
+const static uint64_t SH_FLD_DIS_TRACE = 4937; // 24
+const static uint64_t SH_FLD_DIS_TRACE_EXTRA = 4938; // 17
+const static uint64_t SH_FLD_DIS_TRACE_STALL = 4939; // 17
+const static uint64_t SH_FLD_DIS_WRITE_GATHER = 4940; // 4
+const static uint64_t SH_FLD_DIVIDER_MODE = 4941; // 12
+const static uint64_t SH_FLD_DIVIDER_MODE_LEN = 4942; // 12
+const static uint64_t SH_FLD_DIVSELB = 4943; // 10
+const static uint64_t SH_FLD_DIVSELB_LEN = 4944; // 10
+const static uint64_t SH_FLD_DIVSELFB = 4945; // 10
+const static uint64_t SH_FLD_DIVSELFB_LEN = 4946; // 10
+const static uint64_t SH_FLD_DIV_PARITY = 4947; // 43
+const static uint64_t SH_FLD_DMAP_MODE_EN = 4948; // 2
+const static uint64_t SH_FLD_DMA_CH0_IDLE = 4949; // 1
+const static uint64_t SH_FLD_DMA_CH1_IDLE = 4950; // 1
+const static uint64_t SH_FLD_DMA_CH2_IDLE = 4951; // 1
+const static uint64_t SH_FLD_DMA_CH3_IDLE = 4952; // 1
+const static uint64_t SH_FLD_DMA_CH4_IDLE = 4953; // 1
+const static uint64_t SH_FLD_DMA_CRBARRAY_ACTION = 4954; // 1
+const static uint64_t SH_FLD_DMA_CRBARRAY_ENA = 4955; // 1
+const static uint64_t SH_FLD_DMA_CRBARRAY_SELECT = 4956; // 1
+const static uint64_t SH_FLD_DMA_CRBARRAY_TYPE = 4957; // 1
+const static uint64_t SH_FLD_DMA_EGRARRAY_ACTION = 4958; // 1
+const static uint64_t SH_FLD_DMA_EGRARRAY_ENA = 4959; // 1
+const static uint64_t SH_FLD_DMA_EGRARRAY_SELECT = 4960; // 1
+const static uint64_t SH_FLD_DMA_EGRARRAY_SELECT_LEN = 4961; // 1
+const static uint64_t SH_FLD_DMA_EGRARRAY_TYPE = 4962; // 1
+const static uint64_t SH_FLD_DMA_INGARRAY_ACTION = 4963; // 1
+const static uint64_t SH_FLD_DMA_INGARRAY_ENA = 4964; // 1
+const static uint64_t SH_FLD_DMA_INGARRAY_SELECT = 4965; // 1
+const static uint64_t SH_FLD_DMA_INGARRAY_SELECT_LEN = 4966; // 1
+const static uint64_t SH_FLD_DMA_INGARRAY_TYPE = 4967; // 1
+const static uint64_t SH_FLD_DMA_INWR_ACTION = 4968; // 1
+const static uint64_t SH_FLD_DMA_INWR_ENA = 4969; // 1
+const static uint64_t SH_FLD_DMA_INWR_TYPE = 4970; // 1
+const static uint64_t SH_FLD_DMA_OUTWR_ACTION = 4971; // 1
+const static uint64_t SH_FLD_DMA_OUTWR_ENA = 4972; // 1
+const static uint64_t SH_FLD_DMA_OUTWR_TYPE = 4973; // 1
+const static uint64_t SH_FLD_DMA_PARTIAL_WRT_NOT_INJECT = 4974; // 1
+const static uint64_t SH_FLD_DMA_PART_WR_NOT_INJ = 4975; // 1
+const static uint64_t SH_FLD_DMA_RD_DISABLE_GROUP = 4976; // 1
+const static uint64_t SH_FLD_DMA_RD_DISABLE_LN = 4977; // 1
+const static uint64_t SH_FLD_DMA_RD_DISABLE_NN_RN = 4978; // 1
+const static uint64_t SH_FLD_DMA_RD_DISABLE_VG_NOT_SYS = 4979; // 1
+const static uint64_t SH_FLD_DMA_RD_VG_RESET_TIMER_MASK = 4980; // 1
+const static uint64_t SH_FLD_DMA_RD_VG_RESET_TIMER_MASK_LEN = 4981; // 1
+const static uint64_t SH_FLD_DMA_RD_VG_RST_TMASK = 4982; // 1
+const static uint64_t SH_FLD_DMA_RD_VG_RST_TMASK_LEN = 4983; // 1
+const static uint64_t SH_FLD_DMA_READ = 4984; // 3
+const static uint64_t SH_FLD_DMA_READ_LEN = 4985; // 3
+const static uint64_t SH_FLD_DMA_TIMER_ENBL = 4986; // 1
+const static uint64_t SH_FLD_DMA_TIMER_REF_DIV = 4987; // 1
+const static uint64_t SH_FLD_DMA_TIMER_REF_DIV_LEN = 4988; // 1
+const static uint64_t SH_FLD_DMA_WRITE = 4989; // 3
+const static uint64_t SH_FLD_DMA_WRITE_LEN = 4990; // 2
+const static uint64_t SH_FLD_DMA_WR_DISABLE_GROUP = 4991; // 1
+const static uint64_t SH_FLD_DMA_WR_DISABLE_LN = 4992; // 1
+const static uint64_t SH_FLD_DMA_WR_DISABLE_NN_RN = 4993; // 1
+const static uint64_t SH_FLD_DMA_WR_DISABLE_VG_NOT_SYS = 4994; // 1
+const static uint64_t SH_FLD_DMA_WR_NOT_INJ = 4995; // 1
+const static uint64_t SH_FLD_DMA_WR_NOT_INJECT = 4996; // 1
+const static uint64_t SH_FLD_DMA_WR_VG_RESET_TIMER_MASK = 4997; // 1
+const static uint64_t SH_FLD_DMA_WR_VG_RESET_TIMER_MASK_LEN = 4998; // 1
+const static uint64_t SH_FLD_DMA_WR_VG_RST_TMASK = 4999; // 1
+const static uint64_t SH_FLD_DMA_WR_VG_RST_TMASK_LEN = 5000; // 1
+const static uint64_t SH_FLD_DNFIFO_DEQUEUED_EOT_FLAG = 5001; // 1
+const static uint64_t SH_FLD_DNFIFO_FIFO_EMPTY = 5002; // 1
+const static uint64_t SH_FLD_DNFIFO_FIFO_ENTRY_COUNT = 5003; // 1
+const static uint64_t SH_FLD_DNFIFO_FIFO_ENTRY_COUNT_LEN = 5004; // 1
+const static uint64_t SH_FLD_DNFIFO_FIFO_EOT_FLAGS = 5005; // 1
+const static uint64_t SH_FLD_DNFIFO_FIFO_EOT_FLAGS_LEN = 5006; // 1
+const static uint64_t SH_FLD_DNFIFO_FIFO_FULL = 5007; // 1
+const static uint64_t SH_FLD_DNFIFO_FIFO_VALID_FLAGS = 5008; // 1
+const static uint64_t SH_FLD_DNFIFO_FIFO_VALID_FLAGS_LEN = 5009; // 1
+const static uint64_t SH_FLD_DNFIFO_REQ_RESET_FR_SBE = 5010; // 1
+const static uint64_t SH_FLD_DNFIFO_REQ_RESET_FR_SP = 5011; // 1
+const static uint64_t SH_FLD_DOB01_CE = 5012; // 4
+const static uint64_t SH_FLD_DOB01_ERR = 5013; // 2
+const static uint64_t SH_FLD_DOB01_SUE = 5014; // 4
+const static uint64_t SH_FLD_DOB01_UE = 5015; // 4
+const static uint64_t SH_FLD_DOB23_CE = 5016; // 4
+const static uint64_t SH_FLD_DOB23_ERR = 5017; // 2
+const static uint64_t SH_FLD_DOB23_SUE = 5018; // 4
+const static uint64_t SH_FLD_DOB23_UE = 5019; // 4
+const static uint64_t SH_FLD_DOB45_CE = 5020; // 4
+const static uint64_t SH_FLD_DOB45_ERR = 5021; // 2
+const static uint64_t SH_FLD_DOB45_SUE = 5022; // 4
+const static uint64_t SH_FLD_DOB45_UE = 5023; // 4
+const static uint64_t SH_FLD_DOB67_CE = 5024; // 2
+const static uint64_t SH_FLD_DOB67_ERR = 5025; // 1
+const static uint64_t SH_FLD_DOB67_SUE = 5026; // 2
+const static uint64_t SH_FLD_DOB67_UE = 5027; // 2
+const static uint64_t SH_FLD_DONE = 5028; // 22
+const static uint64_t SH_FLD_DOORBELL0 = 5029; // 1
+const static uint64_t SH_FLD_DOORBELL0_C0 = 5030; // 12
+const static uint64_t SH_FLD_DOORBELL0_C1 = 5031; // 12
+const static uint64_t SH_FLD_DOORBELL1 = 5032; // 1
+const static uint64_t SH_FLD_DOORBELL1_C0 = 5033; // 12
+const static uint64_t SH_FLD_DOORBELL1_C1 = 5034; // 12
+const static uint64_t SH_FLD_DOORBELL2_C0 = 5035; // 12
+const static uint64_t SH_FLD_DOORBELL2_C1 = 5036; // 12
+const static uint64_t SH_FLD_DOORBELL3_C0 = 5037; // 12
+const static uint64_t SH_FLD_DOORBELL3_C1 = 5038; // 12
+const static uint64_t SH_FLD_DOUBLE_EPSILON_LENGTH = 5039; // 4
+const static uint64_t SH_FLD_DO_DR = 5040; // 1
+const static uint64_t SH_FLD_DO_IR = 5041; // 1
+const static uint64_t SH_FLD_DO_TAP_RESET = 5042; // 1
+const static uint64_t SH_FLD_DP18_RX_PD = 5043; // 8
+const static uint64_t SH_FLD_DP18_RX_PD_LEN = 5044; // 8
+const static uint64_t SH_FLD_DPLL_DCO_EMPTY = 5045; // 6
+const static uint64_t SH_FLD_DPLL_DCO_FULL = 5046; // 6
+const static uint64_t SH_FLD_DPLL_DYN_FMIN = 5047; // 6
+const static uint64_t SH_FLD_DPLL_INT = 5048; // 6
+const static uint64_t SH_FLD_DQS_ALIGN = 5049; // 8
+const static uint64_t SH_FLD_DQ_SEL_LANE = 5050; // 8
+const static uint64_t SH_FLD_DQ_SEL_LANE_LEN = 5051; // 8
+const static uint64_t SH_FLD_DQ_SEL_QUAD = 5052; // 8
+const static uint64_t SH_FLD_DQ_SEL_QUAD_LEN = 5053; // 8
+const static uint64_t SH_FLD_DRAM_ABIST_DONE_DC = 5054; // 43
+const static uint64_t SH_FLD_DROP_COUNTER_FULL = 5055; // 4
+const static uint64_t SH_FLD_DROP_MASK_0_5 = 5056; // 1
+const static uint64_t SH_FLD_DROP_MASK_0_5_LEN = 5057; // 1
+const static uint64_t SH_FLD_DROP_PRIORITY_MASK = 5058; // 12
+const static uint64_t SH_FLD_DROP_PRIORITY_MASK_LEN = 5059; // 12
+const static uint64_t SH_FLD_DROP_PRIORITY_MODE = 5060; // 2
+const static uint64_t SH_FLD_DROP_PRI_DMA = 5061; // 1
+const static uint64_t SH_FLD_DROP_PRI_HPC_READ = 5062; // 1
+const static uint64_t SH_FLD_DROP_PRI_INTRP = 5063; // 1
+const static uint64_t SH_FLD_DRTM_REQ = 5064; // 5
+const static uint64_t SH_FLD_DRV_CLK_PATTERN_GCRMSG = 5065; // 4
+const static uint64_t SH_FLD_DRV_CLK_PATTERN_GCRMSG_LEN = 5066; // 4
+const static uint64_t SH_FLD_DRV_DATA_PATTERN_GCRMSG = 5067; // 6
+const static uint64_t SH_FLD_DRV_DATA_PATTERN_GCRMSG_LEN = 5068; // 6
+const static uint64_t SH_FLD_DRV_PATTERN_EN = 5069; // 1
+const static uint64_t SH_FLD_DSC1_ABORT_1 = 5070; // 1
+const static uint64_t SH_FLD_DSC1_DATA_COUNT = 5071; // 1
+const static uint64_t SH_FLD_DSC1_DATA_COUNT_1B = 5072; // 1
+const static uint64_t SH_FLD_DSC1_DATA_COUNT_1B_LEN = 5073; // 1
+const static uint64_t SH_FLD_DSC1_DATA_COUNT_LEN = 5074; // 1
+const static uint64_t SH_FLD_DSC1_HEADER_COUNT = 5075; // 1
+const static uint64_t SH_FLD_DSC1_HEADER_COUNT_1B = 5076; // 1
+const static uint64_t SH_FLD_DSC1_HEADER_COUNT_1B_LEN = 5077; // 1
+const static uint64_t SH_FLD_DSC1_HEADER_COUNT_LEN = 5078; // 1
+const static uint64_t SH_FLD_DSC1_LBUS_SLAVE_1B_PENDING = 5079; // 1
+const static uint64_t SH_FLD_DSC1_PERMISSION_TO_SEND_1 = 5080; // 1
+const static uint64_t SH_FLD_DSC1_PIB_SLAVE_PENDING = 5081; // 1
+const static uint64_t SH_FLD_DSC1_UNUSED_24 = 5082; // 1
+const static uint64_t SH_FLD_DSC1_UNUSED_27 = 5083; // 1
+const static uint64_t SH_FLD_DSC1_XDN_1 = 5084; // 1
+const static uint64_t SH_FLD_DSC1_XUP_1 = 5085; // 1
+const static uint64_t SH_FLD_DSC2_ABORT_2 = 5086; // 1
+const static uint64_t SH_FLD_DSC2_DATA_COUNT = 5087; // 1
+const static uint64_t SH_FLD_DSC2_DATA_COUNT_2B = 5088; // 1
+const static uint64_t SH_FLD_DSC2_DATA_COUNT_2B_LEN = 5089; // 1
+const static uint64_t SH_FLD_DSC2_DATA_COUNT_LEN = 5090; // 1
+const static uint64_t SH_FLD_DSC2_HEADER_COUNT = 5091; // 1
+const static uint64_t SH_FLD_DSC2_HEADER_COUNT_2B = 5092; // 1
+const static uint64_t SH_FLD_DSC2_HEADER_COUNT_2B_LEN = 5093; // 1
+const static uint64_t SH_FLD_DSC2_HEADER_COUNT_LEN = 5094; // 1
+const static uint64_t SH_FLD_DSC2_LBUS_SLAVE_2B_PENDING = 5095; // 1
+const static uint64_t SH_FLD_DSC2_PERMISSION_TO_SEND_2 = 5096; // 1
+const static uint64_t SH_FLD_DSC2_PIB_SLAVE_PENDING = 5097; // 1
+const static uint64_t SH_FLD_DSC2_UNUSED_24 = 5098; // 1
+const static uint64_t SH_FLD_DSC2_UNUSED_27 = 5099; // 1
+const static uint64_t SH_FLD_DSC2_XDN_2 = 5100; // 1
+const static uint64_t SH_FLD_DSC2_XUP_2 = 5101; // 1
+const static uint64_t SH_FLD_DSM_PE = 5102; // 8
+const static uint64_t SH_FLD_DS_SKEW_TIMEOUT_SEL = 5103; // 4
+const static uint64_t SH_FLD_DS_SKEW_TIMEOUT_SEL_LEN = 5104; // 4
+const static uint64_t SH_FLD_DS_TIMEOUT_SEL = 5105; // 4
+const static uint64_t SH_FLD_DS_TIMEOUT_SEL_LEN = 5106; // 4
+const static uint64_t SH_FLD_DTS_ENABLE_L1 = 5107; // 43
+const static uint64_t SH_FLD_DTS_ENABLE_L1_LEN = 5108; // 43
+const static uint64_t SH_FLD_DTS_READ_SEL = 5109; // 43
+const static uint64_t SH_FLD_DTS_READ_SEL_LEN = 5110; // 43
+const static uint64_t SH_FLD_DTS_SAMPLE_ENA = 5111; // 43
+const static uint64_t SH_FLD_DTS_TRIGGER = 5112; // 43
+const static uint64_t SH_FLD_DTS_TRIGGER_SEL = 5113; // 43
+const static uint64_t SH_FLD_DUMMY_0_ERR = 5114; // 2
+const static uint64_t SH_FLD_DUMMY_10_ERR = 5115; // 2
+const static uint64_t SH_FLD_DUMMY_11_ERR = 5116; // 2
+const static uint64_t SH_FLD_DUMMY_12_ERR = 5117; // 2
+const static uint64_t SH_FLD_DUMMY_13_ERR = 5118; // 2
+const static uint64_t SH_FLD_DUMMY_14_ERR = 5119; // 2
+const static uint64_t SH_FLD_DUMMY_15_ERR = 5120; // 2
+const static uint64_t SH_FLD_DUMMY_16_ERR = 5121; // 2
+const static uint64_t SH_FLD_DUMMY_17_ERR = 5122; // 2
+const static uint64_t SH_FLD_DUMMY_18_ERR = 5123; // 2
+const static uint64_t SH_FLD_DUMMY_19_ERR = 5124; // 2
+const static uint64_t SH_FLD_DUMMY_1_ERR = 5125; // 2
+const static uint64_t SH_FLD_DUMMY_20_ERR = 5126; // 2
+const static uint64_t SH_FLD_DUMMY_21_ERR = 5127; // 2
+const static uint64_t SH_FLD_DUMMY_22_ERR = 5128; // 2
+const static uint64_t SH_FLD_DUMMY_23_ERR = 5129; // 2
+const static uint64_t SH_FLD_DUMMY_24_ERR = 5130; // 2
+const static uint64_t SH_FLD_DUMMY_25_ERR = 5131; // 2
+const static uint64_t SH_FLD_DUMMY_26_ERR = 5132; // 2
+const static uint64_t SH_FLD_DUMMY_27_ERR = 5133; // 2
+const static uint64_t SH_FLD_DUMMY_28_ERR = 5134; // 2
+const static uint64_t SH_FLD_DUMMY_29_ERR = 5135; // 2
+const static uint64_t SH_FLD_DUMMY_2_ERR = 5136; // 2
+const static uint64_t SH_FLD_DUMMY_30_ERR = 5137; // 2
+const static uint64_t SH_FLD_DUMMY_31_ERR = 5138; // 2
+const static uint64_t SH_FLD_DUMMY_32_ERR = 5139; // 2
+const static uint64_t SH_FLD_DUMMY_33_ERR = 5140; // 2
+const static uint64_t SH_FLD_DUMMY_34_ERR = 5141; // 2
+const static uint64_t SH_FLD_DUMMY_35_ERR = 5142; // 2
+const static uint64_t SH_FLD_DUMMY_36_ERR = 5143; // 2
+const static uint64_t SH_FLD_DUMMY_37_ERR = 5144; // 2
+const static uint64_t SH_FLD_DUMMY_38_ERR = 5145; // 2
+const static uint64_t SH_FLD_DUMMY_39_ERR = 5146; // 2
+const static uint64_t SH_FLD_DUMMY_3_ERR = 5147; // 2
+const static uint64_t SH_FLD_DUMMY_40_ERR = 5148; // 2
+const static uint64_t SH_FLD_DUMMY_41_ERR = 5149; // 2
+const static uint64_t SH_FLD_DUMMY_42_ERR = 5150; // 2
+const static uint64_t SH_FLD_DUMMY_43_ERR = 5151; // 2
+const static uint64_t SH_FLD_DUMMY_44_ERR = 5152; // 2
+const static uint64_t SH_FLD_DUMMY_45_ERR = 5153; // 2
+const static uint64_t SH_FLD_DUMMY_46_ERR = 5154; // 2
+const static uint64_t SH_FLD_DUMMY_47_ERR = 5155; // 2
+const static uint64_t SH_FLD_DUMMY_48_ERR = 5156; // 2
+const static uint64_t SH_FLD_DUMMY_49_ERR = 5157; // 2
+const static uint64_t SH_FLD_DUMMY_4_ERR = 5158; // 2
+const static uint64_t SH_FLD_DUMMY_50_ERR = 5159; // 2
+const static uint64_t SH_FLD_DUMMY_51_ERR = 5160; // 2
+const static uint64_t SH_FLD_DUMMY_52_ERR = 5161; // 2
+const static uint64_t SH_FLD_DUMMY_53_ERR = 5162; // 2
+const static uint64_t SH_FLD_DUMMY_54_ERR = 5163; // 2
+const static uint64_t SH_FLD_DUMMY_55_ERR = 5164; // 2
+const static uint64_t SH_FLD_DUMMY_56_ERR = 5165; // 2
+const static uint64_t SH_FLD_DUMMY_57_ERR = 5166; // 2
+const static uint64_t SH_FLD_DUMMY_58_ERR = 5167; // 2
+const static uint64_t SH_FLD_DUMMY_59_ERR = 5168; // 2
+const static uint64_t SH_FLD_DUMMY_5_ERR = 5169; // 2
+const static uint64_t SH_FLD_DUMMY_60_ERR = 5170; // 2
+const static uint64_t SH_FLD_DUMMY_61_ERR = 5171; // 2
+const static uint64_t SH_FLD_DUMMY_6_ERR = 5172; // 2
+const static uint64_t SH_FLD_DUMMY_7_ERR = 5173; // 2
+const static uint64_t SH_FLD_DUMMY_8_ERR = 5174; // 2
+const static uint64_t SH_FLD_DUMMY_9_ERR = 5175; // 2
+const static uint64_t SH_FLD_DW0_ERR_TYPE = 5176; // 16
+const static uint64_t SH_FLD_DW0_ERR_TYPE_LEN = 5177; // 16
+const static uint64_t SH_FLD_DW0_SYNDROME = 5178; // 16
+const static uint64_t SH_FLD_DW0_SYNDROME_LEN = 5179; // 16
+const static uint64_t SH_FLD_DW1_ERR_TYPE = 5180; // 16
+const static uint64_t SH_FLD_DW1_ERR_TYPE_LEN = 5181; // 16
+const static uint64_t SH_FLD_DW1_SYNDROME = 5182; // 16
+const static uint64_t SH_FLD_DW1_SYNDROME_LEN = 5183; // 16
+const static uint64_t SH_FLD_DW2_ERR_TYPE = 5184; // 16
+const static uint64_t SH_FLD_DW2_ERR_TYPE_LEN = 5185; // 16
+const static uint64_t SH_FLD_DW2_SYNDROME = 5186; // 16
+const static uint64_t SH_FLD_DW2_SYNDROME_LEN = 5187; // 16
+const static uint64_t SH_FLD_DW3_ERR_TYPE = 5188; // 16
+const static uint64_t SH_FLD_DW3_ERR_TYPE_LEN = 5189; // 16
+const static uint64_t SH_FLD_DW3_SYNDROME = 5190; // 16
+const static uint64_t SH_FLD_DW3_SYNDROME_LEN = 5191; // 16
+const static uint64_t SH_FLD_DW_TYPE = 5192; // 12
+const static uint64_t SH_FLD_DW_TYPE_LEN = 5193; // 12
+const static uint64_t SH_FLD_DYNAMIC_FILTER_ENABLE = 5194; // 6
+const static uint64_t SH_FLD_DYNAMIC_MAX_SPARES_EXCEEDED = 5195; // 8
+const static uint64_t SH_FLD_DYNAMIC_REPAIR_ERROR = 5196; // 8
+const static uint64_t SH_FLD_DYNAMIC_SPARE_DEPLOYED = 5197; // 8
+const static uint64_t SH_FLD_DYNAMIC_WINDOW_SELECT = 5198; // 8
+const static uint64_t SH_FLD_DYNAMIC_WINDOW_SELECT_LEN = 5199; // 8
+const static uint64_t SH_FLD_DYN_RECAL_INTERVAL_TIMEOUT_SEL = 5200; // 8
+const static uint64_t SH_FLD_DYN_RECAL_INTERVAL_TIMEOUT_SEL_LEN = 5201; // 8
+const static uint64_t SH_FLD_DYN_RECAL_OVERALL_TIMEOUT_SEL = 5202; // 4
+const static uint64_t SH_FLD_DYN_RECAL_OVERALL_TIMEOUT_SEL_LEN = 5203; // 4
+const static uint64_t SH_FLD_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL = 5204; // 8
+const static uint64_t SH_FLD_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_LEN = 5205; // 8
+const static uint64_t SH_FLD_DYN_RECAL_SUSPEND = 5206; // 4
+const static uint64_t SH_FLD_DYN_RECAL_TSR_IGNORE_GCRMSG = 5207; // 4
+const static uint64_t SH_FLD_DYN_RPR_BAD_BUS_MAX = 5208; // 4
+const static uint64_t SH_FLD_DYN_RPR_BAD_BUS_MAX_LEN = 5209; // 4
+const static uint64_t SH_FLD_DYN_RPR_BAD_LANE_MAX = 5210; // 4
+const static uint64_t SH_FLD_DYN_RPR_BAD_LANE_MAX_LEN = 5211; // 4
+const static uint64_t SH_FLD_DYN_RPR_CLR_ERR_CNTR1 = 5212; // 4
+const static uint64_t SH_FLD_DYN_RPR_CLR_ERR_CNTR2 = 5213; // 4
+const static uint64_t SH_FLD_DYN_RPR_COMPLETE_GCRMSG = 5214; // 4
+const static uint64_t SH_FLD_DYN_RPR_DISABLE = 5215; // 4
+const static uint64_t SH_FLD_DYN_RPR_DISABLE2 = 5216; // 4
+const static uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT = 5217; // 4
+const static uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT_LEN = 5218; // 4
+const static uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH = 5219; // 4
+const static uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH_LEN = 5220; // 4
+const static uint64_t SH_FLD_DYN_RPR_ERR_CNTR1_DURATION = 5221; // 4
+const static uint64_t SH_FLD_DYN_RPR_ERR_CNTR1_DURATION_LEN = 5222; // 4
+const static uint64_t SH_FLD_DYN_RPR_ERR_CNTR2_DURATION = 5223; // 4
+const static uint64_t SH_FLD_DYN_RPR_ERR_CNTR2_DURATION_LEN = 5224; // 4
+const static uint64_t SH_FLD_DYN_RPR_IP_GCRMSG = 5225; // 4
+const static uint64_t SH_FLD_DYN_RPR_LANE2RPR_GCRMSG = 5226; // 4
+const static uint64_t SH_FLD_DYN_RPR_LANE2RPR_GCRMSG_LEN = 5227; // 4
+const static uint64_t SH_FLD_DYN_RPR_REQ_GCRMSG = 5228; // 4
+const static uint64_t SH_FLD_D_BIT_MAP = 5229; // 8
+const static uint64_t SH_FLD_D_BIT_MAP_LEN = 5230; // 8
+const static uint64_t SH_FLD_EARLY_REQ = 5231; // 8
+const static uint64_t SH_FLD_EARLY_REQ_ERR_MASK = 5232; // 8
+const static uint64_t SH_FLD_EARLY_REQ_SOURCE = 5233; // 8
+const static uint64_t SH_FLD_EARLY_REQ_SOURCE_LEN = 5234; // 8
+const static uint64_t SH_FLD_EBUS_ENABLE = 5235; // 1
+const static uint64_t SH_FLD_EBUS_ENABLE_LEN = 5236; // 1
+const static uint64_t SH_FLD_ECC = 5237; // 3
+const static uint64_t SH_FLD_ECCCHK_DISABLE_0 = 5238; // 1
+const static uint64_t SH_FLD_ECCCHK_DISABLE_1 = 5239; // 1
+const static uint64_t SH_FLD_ECCCHK_DISABLE_2 = 5240; // 1
+const static uint64_t SH_FLD_ECCCHK_DISABLE_3 = 5241; // 1
+const static uint64_t SH_FLD_ECCGEN = 5242; // 8
+const static uint64_t SH_FLD_ECC_CE = 5243; // 3
+const static uint64_t SH_FLD_ECC_CHK_DISABLE = 5244; // 1
+const static uint64_t SH_FLD_ECC_CLEAR = 5245; // 2
+const static uint64_t SH_FLD_ECC_CONFIG_ERROR_0 = 5246; // 1
+const static uint64_t SH_FLD_ECC_CONFIG_ERROR_1 = 5247; // 1
+const static uint64_t SH_FLD_ECC_CONFIG_ERROR_2 = 5248; // 1
+const static uint64_t SH_FLD_ECC_CONFIG_ERROR_3 = 5249; // 1
+const static uint64_t SH_FLD_ECC_CORRECTED_ERROR_0 = 5250; // 1
+const static uint64_t SH_FLD_ECC_CORRECTED_ERROR_1 = 5251; // 1
+const static uint64_t SH_FLD_ECC_CORRECTED_ERROR_2 = 5252; // 1
+const static uint64_t SH_FLD_ECC_CORRECTED_ERROR_3 = 5253; // 1
+const static uint64_t SH_FLD_ECC_CORRECTED_ERROR_FACES = 5254; // 1
+const static uint64_t SH_FLD_ECC_CORRECTED_ERROR_PIB = 5255; // 1
+const static uint64_t SH_FLD_ECC_CORRECTOR_INTERNAL_PARITY_ERROR = 5256; // 8
+const static uint64_t SH_FLD_ECC_CORRECT_DIS = 5257; // 12
+const static uint64_t SH_FLD_ECC_DETECT_DIS = 5258; // 12
+const static uint64_t SH_FLD_ECC_ENABLE = 5259; // 6
+const static uint64_t SH_FLD_ECC_ENABLE_0 = 5260; // 1
+const static uint64_t SH_FLD_ECC_ENABLE_1 = 5261; // 1
+const static uint64_t SH_FLD_ECC_ENABLE_2 = 5262; // 1
+const static uint64_t SH_FLD_ECC_ENABLE_3 = 5263; // 1
+const static uint64_t SH_FLD_ECC_ERROR_ADDR = 5264; // 2
+const static uint64_t SH_FLD_ECC_ERROR_ADDR_LEN = 5265; // 2
+const static uint64_t SH_FLD_ECC_ERROR_COUNT = 5266; // 2
+const static uint64_t SH_FLD_ECC_ERROR_COUNT_LEN = 5267; // 2
+const static uint64_t SH_FLD_ECC_ERR_INJ_ARRAY_SEL = 5268; // 3
+const static uint64_t SH_FLD_ECC_ERR_INJ_ARRAY_SEL_LEN = 5269; // 3
+const static uint64_t SH_FLD_ECC_ERR_INJ_EG_ENA = 5270; // 1
+const static uint64_t SH_FLD_ECC_ERR_INJ_EG_FRQ = 5271; // 1
+const static uint64_t SH_FLD_ECC_ERR_INJ_EG_SEL = 5272; // 1
+const static uint64_t SH_FLD_ECC_ERR_INJ_EG_TYP = 5273; // 1
+const static uint64_t SH_FLD_ECC_ERR_INJ_SELECTION = 5274; // 1
+const static uint64_t SH_FLD_ECC_ERR_INJ_SELECTION_LEN = 5275; // 1
+const static uint64_t SH_FLD_ECC_ERR_INJ_WC_ENA = 5276; // 1
+const static uint64_t SH_FLD_ECC_ERR_INJ_WC_FRQ = 5277; // 1
+const static uint64_t SH_FLD_ECC_ERR_INJ_WC_SEL = 5278; // 1
+const static uint64_t SH_FLD_ECC_ERR_INJ_WC_SEL_LEN = 5279; // 1
+const static uint64_t SH_FLD_ECC_ERR_INJ_WC_TYP = 5280; // 1
+const static uint64_t SH_FLD_ECC_GENERATOR_INTERNAL_PARITY_ERROR = 5281; // 8
+const static uint64_t SH_FLD_ECC_INJECT_ERR = 5282; // 12
+const static uint64_t SH_FLD_ECC_INJECT_TYPE = 5283; // 12
+const static uint64_t SH_FLD_ECC_LEN = 5284; // 3
+const static uint64_t SH_FLD_ECC_SYNDROME = 5285; // 2
+const static uint64_t SH_FLD_ECC_SYNDROME_LEN = 5286; // 2
+const static uint64_t SH_FLD_ECC_S_BIT_ERROR = 5287; // 1
+const static uint64_t SH_FLD_ECC_UE = 5288; // 3
+const static uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_0 = 5289; // 1
+const static uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_1 = 5290; // 1
+const static uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_2 = 5291; // 1
+const static uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_3 = 5292; // 1
+const static uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_FACES = 5293; // 1
+const static uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_PIB = 5294; // 1
+const static uint64_t SH_FLD_ECC_UNCORRECTED_ERR_FACES = 5295; // 1
+const static uint64_t SH_FLD_ECC_UNCORRECTED_ERR_PIB = 5296; // 1
+const static uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE = 5297; // 8
+const static uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE_LEN = 5298; // 8
+const static uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE_SELECT = 5299; // 8
+const static uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE_SELECT_LEN = 5300; // 8
+const static uint64_t SH_FLD_ECHO_DELAY_CYCLES = 5301; // 2
+const static uint64_t SH_FLD_ECHO_DELAY_CYCLES_LEN = 5302; // 2
+const static uint64_t SH_FLD_ECRESP_HASH_MODE = 5303; // 4
+const static uint64_t SH_FLD_EDR = 5304; // 18
+const static uint64_t SH_FLD_EDR_LEN = 5305; // 18
+const static uint64_t SH_FLD_EFTCOMP_MAX_INRD = 5306; // 1
+const static uint64_t SH_FLD_EFTCOMP_MAX_INRD_LEN = 5307; // 1
+const static uint64_t SH_FLD_EFTDECOMP_MAX_INRD = 5308; // 1
+const static uint64_t SH_FLD_EFTDECOMP_MAX_INRD_LEN = 5309; // 1
+const static uint64_t SH_FLD_EFT_COMP_PREFETCH_ENABLE = 5310; // 1
+const static uint64_t SH_FLD_EFT_DECOMP_PREFETCH_ENABLE = 5311; // 1
+const static uint64_t SH_FLD_EFT_SPBC_ENABLE = 5312; // 1
+const static uint64_t SH_FLD_EG_CERR_BITS = 5313; // 1
+const static uint64_t SH_FLD_EG_CERR_BITS_LEN = 5314; // 1
+const static uint64_t SH_FLD_EG_CERR_RESET = 5315; // 1
+const static uint64_t SH_FLD_EG_ECC_CE_ERROR = 5316; // 2
+const static uint64_t SH_FLD_EG_ECC_SUE_ERROR = 5317; // 2
+const static uint64_t SH_FLD_EG_ECC_UE_ERROR = 5318; // 2
+const static uint64_t SH_FLD_EG_LOGIC_HW_ERROR = 5319; // 2
+const static uint64_t SH_FLD_EG_TRACE_GROUP_SEL_HI = 5320; // 1
+const static uint64_t SH_FLD_EG_TRACE_GROUP_SEL_HI_LEN = 5321; // 1
+const static uint64_t SH_FLD_EG_TRACE_GROUP_SEL_LO = 5322; // 1
+const static uint64_t SH_FLD_EG_TRACE_GROUP_SEL_LO_LEN = 5323; // 1
+const static uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_01 = 5324; // 1
+const static uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_01_LEN = 5325; // 1
+const static uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_23 = 5326; // 1
+const static uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_23_LEN = 5327; // 1
+const static uint64_t SH_FLD_EMERGENCY_M = 5328; // 8
+const static uint64_t SH_FLD_EMERGENCY_M_LEN = 5329; // 8
+const static uint64_t SH_FLD_EMERGENCY_N = 5330; // 8
+const static uint64_t SH_FLD_EMERGENCY_N_LEN = 5331; // 8
+const static uint64_t SH_FLD_EMERGENCY_THROTTLE = 5332; // 16
+const static uint64_t SH_FLD_EMERGENCY_THROTTLE_ATTN = 5333; // 4
+const static uint64_t SH_FLD_EMER_THROTTLE_IP = 5334; // 8
+const static uint64_t SH_FLD_EMER_THROTTLE_IP_CLR = 5335; // 8
+const static uint64_t SH_FLD_EN = 5336; // 40
+const static uint64_t SH_FLD_ENABLE = 5337; // 178
+const static uint64_t SH_FLD_ENABLE_0_7 = 5338; // 1
+const static uint64_t SH_FLD_ENABLE_0_7_LEN = 5339; // 1
+const static uint64_t SH_FLD_ENABLE_64_128B_READ = 5340; // 4
+const static uint64_t SH_FLD_ENABLE_ATT_MAINT_CMD_DONE = 5341; // 2
+const static uint64_t SH_FLD_ENABLE_AUX_PORT_UNUSED = 5342; // 2
+const static uint64_t SH_FLD_ENABLE_BER_TEST = 5343; // 4
+const static uint64_t SH_FLD_ENABLE_BUSY_COUNTERS = 5344; // 8
+const static uint64_t SH_FLD_ENABLE_CENTAUR_CHECKSTOP_COMMAND = 5345; // 4
+const static uint64_t SH_FLD_ENABLE_CENTAUR_PERFMON_START_COMMAND = 5346; // 4
+const static uint64_t SH_FLD_ENABLE_CENTAUR_PERFMON_STOP_COMMAND = 5347; // 4
+const static uint64_t SH_FLD_ENABLE_CENTAUR_SYNC = 5348; // 4
+const static uint64_t SH_FLD_ENABLE_CENTAUR_TRACESTOP_COMMAND = 5349; // 4
+const static uint64_t SH_FLD_ENABLE_CHANNEL_ARB_DISABLE_HP_OP_LFSR = 5350; // 4
+const static uint64_t SH_FLD_ENABLE_CHANNEL_ARB_FORCE_WR_HP_LFSR = 5351; // 4
+const static uint64_t SH_FLD_ENABLE_CLEAN = 5352; // 8
+const static uint64_t SH_FLD_ENABLE_CLR_ERR_CMD = 5353; // 1
+const static uint64_t SH_FLD_ENABLE_CM_COARSE_CAL = 5354; // 6
+const static uint64_t SH_FLD_ENABLE_CM_FINE_CAL = 5355; // 6
+const static uint64_t SH_FLD_ENABLE_CQ_PMU_COUNTING = 5356; // 1
+const static uint64_t SH_FLD_ENABLE_CQ_TRACE = 5357; // 1
+const static uint64_t SH_FLD_ENABLE_CRC_BYPASS_ALWAYS = 5358; // 4
+const static uint64_t SH_FLD_ENABLE_CRC_ECC_BPASS_NODAL_ONLY = 5359; // 4
+const static uint64_t SH_FLD_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 5360; // 6
+const static uint64_t SH_FLD_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 5361; // 6
+const static uint64_t SH_FLD_ENABLE_CTLE_COARSE_CAL = 5362; // 6
+const static uint64_t SH_FLD_ENABLE_CTLE_EDGE_OFFSET_CAL = 5363; // 2
+const static uint64_t SH_FLD_ENABLE_CTLE_EDGE_TRACK_ONLY = 5364; // 4
+const static uint64_t SH_FLD_ENABLE_DAC_H1_CAL = 5365; // 6
+const static uint64_t SH_FLD_ENABLE_DAC_H1_TO_A_CAL = 5366; // 4
+const static uint64_t SH_FLD_ENABLE_DDC = 5367; // 6
+const static uint64_t SH_FLD_ENABLE_DEBUG_BUS = 5368; // 1
+const static uint64_t SH_FLD_ENABLE_DFE_H1_CAL = 5369; // 6
+const static uint64_t SH_FLD_ENABLE_DFE_H2_H12_CAL = 5370; // 4
+const static uint64_t SH_FLD_ENABLE_DFE_H2_H12_SUBSTEP = 5371; // 4
+const static uint64_t SH_FLD_ENABLE_DFE_H2_H12_SUBSTEP_LEN = 5372; // 4
+const static uint64_t SH_FLD_ENABLE_DFE_VOLTAGE_MODE = 5373; // 4
+const static uint64_t SH_FLD_ENABLE_DISABLE_PREFETCH_FOR_MIRROR_READS =
+    5374; // 4
+const static uint64_t
+SH_FLD_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_GROUP_PUMP_LOCAL_READ = 5375; // 4
+const static uint64_t
+SH_FLD_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_SYSTEM_PUMP_LOCAL_READ = 5376; // 4
+const static uint64_t SH_FLD_ENABLE_DONE_SIGNALING = 5377; // 4
+const static uint64_t SH_FLD_ENABLE_DYNAMIC_PF_USAGE = 5378; // 8
+const static uint64_t SH_FLD_ENABLE_DYNAMIC_WR_USAGE = 5379; // 8
+const static uint64_t SH_FLD_ENABLE_EG_PMU_COUNTING = 5380; // 1
+const static uint64_t SH_FLD_ENABLE_EG_TRACE = 5381; // 1
+const static uint64_t SH_FLD_ENABLE_EMER_THROTTLE = 5382; // 4
+const static uint64_t SH_FLD_ENABLE_FINAL_L2U_ADJ = 5383; // 4
+const static uint64_t SH_FLD_ENABLE_FIR_HOST_ATTN = 5384; // 4
+const static uint64_t SH_FLD_ENABLE_FIR_SPEC_ATTN = 5385; // 4
+const static uint64_t SH_FLD_ENABLE_FSAFE_UPON_HEARTBEAT_LOSS = 5386; // 6
+const static uint64_t SH_FLD_ENABLE_GCR_OFL_BUFF = 5387; // 4
+const static uint64_t SH_FLD_ENABLE_GLB_PULSE = 5388; // 1
+const static uint64_t SH_FLD_ENABLE_GLOBAL_RUN = 5389; // 2
+const static uint64_t SH_FLD_ENABLE_H1AP_TWEAK = 5390; // 6
+const static uint64_t SH_FLD_ENABLE_HW_ERROR_RECOVERY = 5391; // 5
+const static uint64_t SH_FLD_ENABLE_INTEG_LATCH_OFFSET_CAL = 5392; // 6
+const static uint64_t SH_FLD_ENABLE_IN_PMU_COUNTING = 5393; // 1
+const static uint64_t SH_FLD_ENABLE_IN_TRACE = 5394; // 1
+const static uint64_t SH_FLD_ENABLE_IPOLL_AND_DMA = 5395; // 3
+const static uint64_t SH_FLD_ENABLE_LEN = 5396; // 3
+const static uint64_t SH_FLD_ENABLE_MEMORY_BACKING = 5397; // 6
+const static uint64_t SH_FLD_ENABLE_PARITY_CHECK = 5398; // 3
+const static uint64_t SH_FLD_ENABLE_PB_SWITCH_AB = 5399; // 1
+const static uint64_t SH_FLD_ENABLE_PB_SWITCH_CD = 5400; // 1
+const static uint64_t SH_FLD_ENABLE_PECE = 5401; // 24
+const static uint64_t SH_FLD_ENABLE_PF_DROP = 5402; // 4
+const static uint64_t SH_FLD_ENABLE_PF_DROP_CMDLIST = 5403; // 4
+const static uint64_t SH_FLD_ENABLE_PF_DROP_SRQ = 5404; // 4
+const static uint64_t SH_FLD_ENABLE_PREFETCH_PROMOTE = 5405; // 4
+const static uint64_t SH_FLD_ENABLE_READ_DATA_FROM_AMOC = 5406; // 8
+const static uint64_t SH_FLD_ENABLE_READ_DATA_FROM_AMOC_LEN = 5407; // 8
+const static uint64_t SH_FLD_ENABLE_READ_LFSR_DATA = 5408; // 4
+const static uint64_t SH_FLD_ENABLE_RECEIVE_OWN_TOD = 5409; // 1
+const static uint64_t SH_FLD_ENABLE_RECEIVE_OWN_TRIGGER = 5410; // 1
+const static uint64_t SH_FLD_ENABLE_RECEIVE_OWN_TRIGGER_LEN = 5411; // 1
+const static uint64_t SH_FLD_ENABLE_REFRESH_BLOCK_DISP = 5412; // 8
+const static uint64_t SH_FLD_ENABLE_REFRESH_BLOCK_NSQ = 5413; // 8
+const static uint64_t SH_FLD_ENABLE_REFRESH_BLOCK_SQ = 5414; // 8
+const static uint64_t SH_FLD_ENABLE_RELATIVE_ADDRESS_CMDS = 5415; // 3
+const static uint64_t SH_FLD_ENABLE_REMAP = 5416; // 1
+const static uint64_t SH_FLD_ENABLE_RESULT_CHECK = 5417; // 4
+const static uint64_t SH_FLD_ENABLE_RG_PMU_COUNTING = 5418; // 1
+const static uint64_t SH_FLD_ENABLE_RG_TRACE = 5419; // 1
+const static uint64_t SH_FLD_ENABLE_SCRD_FR_RXRF = 5420; // 1
+const static uint64_t SH_FLD_ENABLE_SCWR_TO_RXRF = 5421; // 1
+const static uint64_t SH_FLD_ENABLE_SCWR_TO_TXRF = 5422; // 1
+const static uint64_t SH_FLD_ENABLE_STREAMING_MODE = 5423; // 2
+const static uint64_t SH_FLD_ENABLE_TRC_GLB_TRIG0 = 5424; // 1
+const static uint64_t SH_FLD_ENABLE_TRC_GLB_TRIG1 = 5425; // 1
+const static uint64_t SH_FLD_ENABLE_TTYPE_DECODE = 5426; // 2
+const static uint64_t SH_FLD_ENABLE_VGA_CAL = 5427; // 6
+const static uint64_t SH_FLD_ENABLE_VGA_EDGE_OFFSET_CAL = 5428; // 2
+const static uint64_t SH_FLD_ENABLE_WC_PMU_COUNTING = 5429; // 1
+const static uint64_t SH_FLD_ENABLE_WC_TRACE = 5430; // 1
+const static uint64_t SH_FLD_ENABLE_ZCAL = 5431; // 8
+const static uint64_t SH_FLD_ENA_COARSE_RD = 5432; // 8
+const static uint64_t SH_FLD_ENA_CUSTOM_RD = 5433; // 8
+const static uint64_t SH_FLD_ENA_CUSTOM_WR = 5434; // 8
+const static uint64_t SH_FLD_ENA_DIGITAL_EYE = 5435; // 8
+const static uint64_t SH_FLD_ENA_DQS_ALIGN = 5436; // 16
+const static uint64_t SH_FLD_ENA_INITIAL_COARSE_WR = 5437; // 8
+const static uint64_t SH_FLD_ENA_INITIAL_PAT_WR = 5438; // 8
+const static uint64_t SH_FLD_ENA_RANK = 5439; // 8
+const static uint64_t SH_FLD_ENA_RANK_LEN = 5440; // 8
+const static uint64_t SH_FLD_ENA_RANK_PAIR = 5441; // 16
+const static uint64_t SH_FLD_ENA_RANK_PAIR_LEN = 5442; // 16
+const static uint64_t SH_FLD_ENA_RDCLK_ALIGN = 5443; // 16
+const static uint64_t SH_FLD_ENA_READ_CTR = 5444; // 16
+const static uint64_t SH_FLD_ENA_SYSCLK_ALIGN = 5445; // 8
+const static uint64_t SH_FLD_ENA_WRITE_CTR = 5446; // 8
+const static uint64_t SH_FLD_ENA_WR_LEVEL = 5447; // 8
+const static uint64_t SH_FLD_ENA_ZCAL = 5448; // 8
+const static uint64_t SH_FLD_END = 5449; // 64
+const static uint64_t SH_FLD_ENDABLE_PMU_CNT_RESET = 5450; // 1
+const static uint64_t SH_FLD_ENDPOINTS = 5451; // 1
+const static uint64_t SH_FLD_END_BANK = 5452; // 2
+const static uint64_t SH_FLD_END_BANK_LEN = 5453; // 2
+const static uint64_t SH_FLD_END_COL = 5454; // 2
+const static uint64_t SH_FLD_END_COL_LEN = 5455; // 2
+const static uint64_t SH_FLD_END_DIMM_SELECT = 5456; // 2
+const static uint64_t SH_FLD_END_LANE_ID = 5457; // 8
+const static uint64_t SH_FLD_END_LANE_ID_LEN = 5458; // 8
+const static uint64_t SH_FLD_END_MASTER_RANK0 = 5459; // 2
+const static uint64_t SH_FLD_END_MASTER_RANK1 = 5460; // 2
+const static uint64_t SH_FLD_END_MASTER_RANK2 = 5461; // 2
+const static uint64_t SH_FLD_END_ROW = 5462; // 2
+const static uint64_t SH_FLD_END_ROW_LEN = 5463; // 2
+const static uint64_t SH_FLD_END_SLAVE_RANK = 5464; // 2
+const static uint64_t SH_FLD_END_SLAVE_RANK_LEN = 5465; // 2
+const static uint64_t SH_FLD_ENH_MODE_0 = 5466; // 1
+const static uint64_t SH_FLD_ENH_MODE_1 = 5467; // 1
+const static uint64_t SH_FLD_ENH_MODE_2 = 5468; // 1
+const static uint64_t SH_FLD_ENH_MODE_3 = 5469; // 1
+const static uint64_t SH_FLD_ENOP = 5470; // 43
+const static uint64_t SH_FLD_ENOP_FORCE_SG = 5471; // 43
+const static uint64_t SH_FLD_ENOP_LEN = 5472; // 43
+const static uint64_t SH_FLD_ENOP_WAIT = 5473; // 43
+const static uint64_t SH_FLD_ENOP_WAIT_LEN = 5474; // 43
+const static uint64_t SH_FLD_ENTRIES = 5475; // 1
+const static uint64_t SH_FLD_ENTRIES_LEN = 5476; // 1
+const static uint64_t SH_FLD_ENTRY = 5477; // 3
+const static uint64_t SH_FLD_ENTRY_LEN = 5478; // 3
+const static uint64_t SH_FLD_EN_ATTN = 5479; // 24
+const static uint64_t SH_FLD_EN_CHARB_STALL = 5480; // 4
+const static uint64_t SH_FLD_EN_DBG = 5481; // 4
+const static uint64_t SH_FLD_EN_EVENT_COUNT = 5482; // 1
+const static uint64_t SH_FLD_EN_INSTRUC_TRACE = 5483; // 24
+const static uint64_t SH_FLD_EN_MARKER_ACK = 5484; // 1
+const static uint64_t SH_FLD_EN_OR_DIS_WRITE_PROTECTION = 5485; // 1
+const static uint64_t SH_FLD_EN_OR_DIS_WRITE_PROTECTION_LEN = 5486; // 1
+const static uint64_t SH_FLD_EN_POLL_BACKOFF = 5487; // 1
+const static uint64_t SH_FLD_EN_RANDOM_BACKOFF = 5488; // 1
+const static uint64_t SH_FLD_EN_RESET_DD2_FIX_DIS = 5489; // 8
+const static uint64_t SH_FLD_EN_RESET_WR_DELAY_WL = 5490; // 8
+const static uint64_t SH_FLD_EN_RISCTRACE = 5491; // 17
+const static uint64_t SH_FLD_EN_SECOND_WRBUF = 5492; // 1
+const static uint64_t SH_FLD_EN_SLV_FAIRNESS = 5493; // 1
+const static uint64_t SH_FLD_EN_SPEC_CILD = 5494; // 1
+const static uint64_t SH_FLD_EN_TRACE_FULL_IVA = 5495; // 17
+const static uint64_t SH_FLD_EN_WIDE_TRACE = 5496; // 16
+const static uint64_t SH_FLD_EN_WT4CR_EPS_ON_LCO = 5497; // 12
+const static uint64_t SH_FLD_EN_WT4CR_EXTENDED_MODE = 5498; // 12
+const static uint64_t SH_FLD_EPOCH_TEST_VECTOR = 5499; // 2
+const static uint64_t SH_FLD_EPOCH_TEST_VECTOR_LEN = 5500; // 2
+const static uint64_t SH_FLD_EPOCH_VALUE = 5501; // 2
+const static uint64_t SH_FLD_EPOCH_VALUE_LEN = 5502; // 2
+const static uint64_t SH_FLD_EPS_CNT_USE_DIVIDER_EN = 5503; // 12
+const static uint64_t SH_FLD_EPS_DIVIDER_MODE = 5504; // 12
+const static uint64_t SH_FLD_EPS_DIVIDER_MODE_LEN = 5505; // 12
+const static uint64_t SH_FLD_EPS_MODE_SEL = 5506; // 12
+const static uint64_t SH_FLD_EPS_STEP_MODE = 5507; // 12
+const static uint64_t SH_FLD_EPS_STEP_MODE_LEN = 5508; // 12
+const static uint64_t SH_FLD_EQC_CILOAD = 5509; // 1
+const static uint64_t SH_FLD_EQC_CILOAD_LEN = 5510; // 1
+const static uint64_t SH_FLD_EQC_CISTORE = 5511; // 1
+const static uint64_t SH_FLD_EQC_CISTORE_LEN = 5512; // 1
+const static uint64_t SH_FLD_EQC_DMA = 5513; // 1
+const static uint64_t SH_FLD_EQC_DMA_LEN = 5514; // 1
+const static uint64_t SH_FLD_EQC_EOI_EQP = 5515; // 1
+const static uint64_t SH_FLD_EQC_EOI_EQP_LEN = 5516; // 1
+const static uint64_t SH_FLD_EQD_DMA_READ = 5517; // 1
+const static uint64_t SH_FLD_EQD_DMA_READ_LEN = 5518; // 1
+const static uint64_t SH_FLD_EQD_DMA_WRITE = 5519; // 1
+const static uint64_t SH_FLD_EQD_DMA_WRITE_LEN = 5520; // 1
+const static uint64_t SH_FLD_EQ_POST = 5521; // 1
+const static uint64_t SH_FLD_EQ_POST_LEN = 5522; // 1
+const static uint64_t SH_FLD_ERAT_ARRAY_CE = 5523; // 1
+const static uint64_t SH_FLD_ERAT_ARRAY_PE = 5524; // 1
+const static uint64_t SH_FLD_ERAT_ARRAY_SUE = 5525; // 1
+const static uint64_t SH_FLD_ERAT_ARRAY_UE = 5526; // 1
+const static uint64_t SH_FLD_ERAT_CICO_HANG = 5527; // 1
+const static uint64_t SH_FLD_ERAT_CNTRL_ERR = 5528; // 1
+const static uint64_t SH_FLD_ERAT_LOCAL_CSTOP = 5529; // 1
+const static uint64_t SH_FLD_ERR = 5530; // 24
+const static uint64_t SH_FLD_ERROR = 5531; // 113
+const static uint64_t SH_FLD_ERRORS = 5532; // 43
+const static uint64_t SH_FLD_ERRORS_LEN = 5533; // 43
+const static uint64_t SH_FLD_ERROR_0 = 5534; // 1
+const static uint64_t SH_FLD_ERROR_1 = 5535; // 1
+const static uint64_t SH_FLD_ERROR_2 = 5536; // 1
+const static uint64_t SH_FLD_ERROR_3 = 5537; // 1
+const static uint64_t SH_FLD_ERROR_4 = 5538; // 1
+const static uint64_t SH_FLD_ERROR_5 = 5539; // 1
+const static uint64_t SH_FLD_ERROR_ADDR = 5540; // 4
+const static uint64_t SH_FLD_ERROR_ADDRESS = 5541; // 2
+const static uint64_t SH_FLD_ERROR_ADDRESS_LEN = 5542; // 2
+const static uint64_t SH_FLD_ERROR_ADDR_LEN = 5543; // 4
+const static uint64_t SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK = 5544; // 90
+const static uint64_t SH_FLD_ERROR_COARSE_RD = 5545; // 8
+const static uint64_t SH_FLD_ERROR_CONFIG = 5546; // 6
+const static uint64_t SH_FLD_ERROR_CONFIG_LEN = 5547; // 6
+const static uint64_t SH_FLD_ERROR_CUSTOM_RD = 5548; // 8
+const static uint64_t SH_FLD_ERROR_CUSTOM_WR = 5549; // 8
+const static uint64_t SH_FLD_ERROR_DIGITAL_EYE = 5550; // 8
+const static uint64_t SH_FLD_ERROR_DQS_ALIGN = 5551; // 8
+const static uint64_t SH_FLD_ERROR_INITIAL_COARSE_WR = 5552; // 8
+const static uint64_t SH_FLD_ERROR_INITIAL_PAT_WRITE = 5553; // 8
+const static uint64_t SH_FLD_ERROR_INJECT = 5554; // 1
+const static uint64_t SH_FLD_ERROR_INJECT_ENABLE = 5555; // 1
+const static uint64_t SH_FLD_ERROR_INJECT_LEN = 5556; // 1
+const static uint64_t SH_FLD_ERROR_LEN = 5557; // 15
+const static uint64_t SH_FLD_ERROR_MASK = 5558; // 43
+const static uint64_t SH_FLD_ERROR_MASK_LEN = 5559; // 43
+const static uint64_t SH_FLD_ERROR_RDCLK_ALIGN = 5560; // 8
+const static uint64_t SH_FLD_ERROR_READ_CTR = 5561; // 8
+const static uint64_t SH_FLD_ERROR_RECOVERY_COMPLETE = 5562; // 2
+const static uint64_t SH_FLD_ERROR_RECOVERY_INITIATED = 5563; // 2
+const static uint64_t SH_FLD_ERROR_STATE = 5564; // 4
+const static uint64_t SH_FLD_ERROR_WRITE_CTR = 5565; // 8
+const static uint64_t SH_FLD_ERROR_WR_LEVEL = 5566; // 8
+const static uint64_t SH_FLD_ERRS = 5567; // 260
+const static uint64_t SH_FLD_ERRS_INJ = 5568; // 4
+const static uint64_t SH_FLD_ERRS_INJ_LEN = 5569; // 4
+const static uint64_t SH_FLD_ERRS_LEN = 5570; // 144
+const static uint64_t SH_FLD_ERR_ADDR_BEYOND_RANGE = 5571; // 1
+const static uint64_t SH_FLD_ERR_ADDR_OVERLAP = 5572; // 1
+const static uint64_t SH_FLD_ERR_CMD_OVERRUN = 5573; // 1
+const static uint64_t SH_FLD_ERR_FSM_DP18 = 5574; // 8
+const static uint64_t SH_FLD_ERR_FSM_DP18_LEN = 5575; // 8
+const static uint64_t SH_FLD_ERR_INJ = 5576; // 252
+const static uint64_t SH_FLD_ERR_INJ_ACTION = 5577; // 2
+const static uint64_t SH_FLD_ERR_INJ_ARRAY_SEL = 5578; // 2
+const static uint64_t SH_FLD_ERR_INJ_ARRAY_SEL_LEN = 5579; // 2
+const static uint64_t SH_FLD_ERR_INJ_A_BER_SEL = 5580; // 6
+const static uint64_t SH_FLD_ERR_INJ_A_BER_SEL_LEN = 5581; // 6
+const static uint64_t SH_FLD_ERR_INJ_A_COARSE_SEL = 5582; // 6
+const static uint64_t SH_FLD_ERR_INJ_A_COARSE_SEL_LEN = 5583; // 6
+const static uint64_t SH_FLD_ERR_INJ_A_ENABLE = 5584; // 116
+const static uint64_t SH_FLD_ERR_INJ_A_FINE_SEL = 5585; // 6
+const static uint64_t SH_FLD_ERR_INJ_A_FINE_SEL_LEN = 5586; // 6
+const static uint64_t SH_FLD_ERR_INJ_B_BER_SEL = 5587; // 6
+const static uint64_t SH_FLD_ERR_INJ_B_BER_SEL_LEN = 5588; // 6
+const static uint64_t SH_FLD_ERR_INJ_B_COARSE_SEL = 5589; // 6
+const static uint64_t SH_FLD_ERR_INJ_B_COARSE_SEL_LEN = 5590; // 6
+const static uint64_t SH_FLD_ERR_INJ_B_ENABLE = 5591; // 116
+const static uint64_t SH_FLD_ERR_INJ_B_FINE_SEL = 5592; // 6
+const static uint64_t SH_FLD_ERR_INJ_B_FINE_SEL_LEN = 5593; // 6
+const static uint64_t SH_FLD_ERR_INJ_CLOCK_ENABLE = 5594; // 6
+const static uint64_t SH_FLD_ERR_INJ_ENABLE = 5595; // 8
+const static uint64_t SH_FLD_ERR_INJ_LEN = 5596; // 136
+const static uint64_t SH_FLD_ERR_INJ_SLS_ALL_CMD = 5597; // 4
+const static uint64_t SH_FLD_ERR_INJ_SLS_CMD = 5598; // 4
+const static uint64_t SH_FLD_ERR_INJ_SLS_CMD_LEN = 5599; // 4
+const static uint64_t SH_FLD_ERR_INJ_SLS_MODE = 5600; // 4
+const static uint64_t SH_FLD_ERR_INJ_SLS_RECAL = 5601; // 4
+const static uint64_t SH_FLD_ERR_INJ_STATUS = 5602; // 2
+const static uint64_t SH_FLD_ERR_INJ_TYPE = 5603; // 2
+const static uint64_t SH_FLD_ERR_REG_DP18 = 5604; // 8
+const static uint64_t SH_FLD_ERR_REG_DP18_LEN = 5605; // 8
+const static uint64_t SH_FLD_ERR_SET0 = 5606; // 8
+const static uint64_t SH_FLD_ERR_SET1 = 5607; // 8
+const static uint64_t SH_FLD_ERR_SET2 = 5608; // 8
+const static uint64_t SH_FLD_ERR_SET3 = 5609; // 8
+const static uint64_t SH_FLD_ERR_SET4 = 5610; // 8
+const static uint64_t SH_FLD_ERR_SET5 = 5611; // 8
+const static uint64_t SH_FLD_ESB_OR_LSI_INTERRUPTS = 5612; // 1
+const static uint64_t SH_FLD_ESC1_PRIORITY = 5613; // 1
+const static uint64_t SH_FLD_ESC1_PRIORITY_LEN = 5614; // 1
+const static uint64_t SH_FLD_ESC1_RSD = 5615; // 1
+const static uint64_t SH_FLD_ESC1_RSD_LEN = 5616; // 1
+const static uint64_t SH_FLD_ESC2_PRIORITY = 5617; // 1
+const static uint64_t SH_FLD_ESC2_PRIORITY_LEN = 5618; // 1
+const static uint64_t SH_FLD_ESC2_RSD = 5619; // 1
+const static uint64_t SH_FLD_ESC2_RSD_LEN = 5620; // 1
+const static uint64_t SH_FLD_ESCAPE_ADDRESS = 5621; // 1
+const static uint64_t SH_FLD_ESCAPE_ADDRESS_LEN = 5622; // 1
+const static uint64_t SH_FLD_EVENT = 5623; // 6
+const static uint64_t SH_FLD_EVENT0_SEL = 5624; // 2
+const static uint64_t SH_FLD_EVENT1_SEL = 5625; // 2
+const static uint64_t SH_FLD_EVENT1_SEL_LEN = 5626; // 2
+const static uint64_t SH_FLD_EVENT2HALT_DELAY = 5627; // 1
+const static uint64_t SH_FLD_EVENT2HALT_DELAY_LEN = 5628; // 1
+const static uint64_t SH_FLD_EVENT2HALT_EN = 5629; // 1
+const static uint64_t SH_FLD_EVENT2HALT_EN_LEN = 5630; // 1
+const static uint64_t SH_FLD_EVENT2HALT_GPE0 = 5631; // 1
+const static uint64_t SH_FLD_EVENT2HALT_GPE1 = 5632; // 1
+const static uint64_t SH_FLD_EVENT2HALT_GPE2 = 5633; // 1
+const static uint64_t SH_FLD_EVENT2HALT_GPE3 = 5634; // 1
+const static uint64_t SH_FLD_EVENT2HALT_HALT_STATE = 5635; // 1
+const static uint64_t SH_FLD_EVENT2HALT_MODE = 5636; // 1
+const static uint64_t SH_FLD_EVENT2HALT_MODE_LEN = 5637; // 1
+const static uint64_t SH_FLD_EVENT2HALT_OCC = 5638; // 1
+const static uint64_t SH_FLD_EVENT2_SEL = 5639; // 2
+const static uint64_t SH_FLD_EVENT2_SEL_LEN = 5640; // 2
+const static uint64_t SH_FLD_EVENT3_SEL = 5641; // 2
+const static uint64_t SH_FLD_EVENT3_SEL_LEN = 5642; // 2
+const static uint64_t SH_FLD_EVENTCNT = 5643; // 3
+const static uint64_t SH_FLD_EVENTCNT_LEN = 5644; // 3
+const static uint64_t SH_FLD_EVENT_BUS_BYTE00_ENABLE = 5645; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE00_ENABLE_LEN = 5646; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE01_ENABLE = 5647; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE01_ENABLE_LEN = 5648; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE02_ENABLE = 5649; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE02_ENABLE_LEN = 5650; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE03_ENABLE = 5651; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE03_ENABLE_LEN = 5652; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE04_ENABLE = 5653; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE04_ENABLE_LEN = 5654; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE05_ENABLE = 5655; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE05_ENABLE_LEN = 5656; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE06_ENABLE = 5657; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE06_ENABLE_LEN = 5658; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE07_ENABLE = 5659; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE07_ENABLE_LEN = 5660; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE10_ENABLE = 5661; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE10_ENABLE_LEN = 5662; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE11_ENABLE = 5663; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE11_ENABLE_LEN = 5664; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE12_ENABLE = 5665; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE12_ENABLE_LEN = 5666; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE13_ENABLE = 5667; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE13_ENABLE_LEN = 5668; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE14_ENABLE = 5669; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE14_ENABLE_LEN = 5670; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE15_ENABLE = 5671; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE15_ENABLE_LEN = 5672; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE16_ENABLE = 5673; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE16_ENABLE_LEN = 5674; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE17_ENABLE = 5675; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE17_ENABLE_LEN = 5676; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE20_ENABLE = 5677; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE20_ENABLE_LEN = 5678; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE21_ENABLE = 5679; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE21_ENABLE_LEN = 5680; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE22_ENABLE = 5681; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE22_ENABLE_LEN = 5682; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE23_ENABLE = 5683; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE23_ENABLE_LEN = 5684; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE24_ENABLE = 5685; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE24_ENABLE_LEN = 5686; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE25_ENABLE = 5687; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE25_ENABLE_LEN = 5688; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE26_ENABLE = 5689; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE26_ENABLE_LEN = 5690; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE27_ENABLE = 5691; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE27_ENABLE_LEN = 5692; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE30_ENABLE = 5693; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE30_ENABLE_LEN = 5694; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE31_ENABLE = 5695; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE31_ENABLE_LEN = 5696; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE32_ENABLE = 5697; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE32_ENABLE_LEN = 5698; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE33_ENABLE = 5699; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE33_ENABLE_LEN = 5700; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE34_ENABLE = 5701; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE34_ENABLE_LEN = 5702; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE35_ENABLE = 5703; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE35_ENABLE_LEN = 5704; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE36_ENABLE = 5705; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE36_ENABLE_LEN = 5706; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE37_ENABLE = 5707; // 4
+const static uint64_t SH_FLD_EVENT_BUS_BYTE37_ENABLE_LEN = 5708; // 4
+const static uint64_t SH_FLD_EVENT_BUS_ENABLE = 5709; // 4
+const static uint64_t SH_FLD_EVENT_BUS_OUTPUT_BYTE0_SELECT = 5710; // 4
+const static uint64_t SH_FLD_EVENT_LEN = 5711; // 6
+const static uint64_t SH_FLD_EVENT_MUX_SELECTS = 5712; // 24
+const static uint64_t SH_FLD_EVENT_MUX_SELECTS_LEN = 5713; // 24
+const static uint64_t SH_FLD_EXBIST_MODE = 5714; // 6
+const static uint64_t SH_FLD_EXIT_1 = 5715; // 64
+const static uint64_t SH_FLD_EXIT_CRITERION_A_N = 5716; // 96
+const static uint64_t SH_FLD_EXTADDR = 5717; // 6
+const static uint64_t SH_FLD_EXTADDR_LEN = 5718; // 6
+const static uint64_t SH_FLD_EXTERNAL_TRAP = 5719; // 1
+const static uint64_t SH_FLD_EXTERNAL_XSTOP = 5720; // 4
+const static uint64_t SH_FLD_EXTRA_CMD_SPACING_0_2 = 5721; // 1
+const static uint64_t SH_FLD_EXTRA_CMD_SPACING_0_2_LEN = 5722; // 1
+const static uint64_t SH_FLD_EXTRA_DAT_SPACING_0_3 = 5723; // 1
+const static uint64_t SH_FLD_EXTRA_DAT_SPACING_0_3_LEN = 5724; // 1
+const static uint64_t SH_FLD_EXT_EBB_EXIT_ENABLE = 5725; // 96
+const static uint64_t SH_FLD_EXT_EXIT_ENABLE = 5726; // 96
+const static uint64_t SH_FLD_EXT_INTERRUPT = 5727; // 1
+const static uint64_t SH_FLD_EXT_RESUME_EXIT_ENABLE = 5728; // 96
+const static uint64_t SH_FLD_EXT_VREF_PD = 5729; // 8
+const static uint64_t SH_FLD_EYEDAC_PD = 5730; // 8
+const static uint64_t SH_FLD_EYE_OPT_DONE = 5731; // 4
+const static uint64_t SH_FLD_EYE_OPT_FAILED = 5732; // 4
+const static uint64_t SH_FLD_E_BIST_EN = 5733; // 2
+const static uint64_t SH_FLD_E_CONTROLS = 5734; // 48
+const static uint64_t SH_FLD_E_CONTROLS_LEN = 5735; // 48
+const static uint64_t SH_FLD_E_CTLE_COARSE = 5736; // 48
+const static uint64_t SH_FLD_E_CTLE_COARSE_LEN = 5737; // 48
+const static uint64_t SH_FLD_E_CTLE_GAIN = 5738; // 48
+const static uint64_t SH_FLD_E_CTLE_GAIN_LEN = 5739; // 48
+const static uint64_t SH_FLD_E_EVEN_INTEG_FINE_GAIN = 5740; // 48
+const static uint64_t SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN = 5741; // 48
+const static uint64_t SH_FLD_E_INTEG_COARSE_GAIN = 5742; // 48
+const static uint64_t SH_FLD_E_INTEG_COARSE_GAIN_LEN = 5743; // 48
+const static uint64_t SH_FLD_E_ODD_INTEG_FINE_GAIN = 5744; // 48
+const static uint64_t SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN = 5745; // 48
+const static uint64_t SH_FLD_E_OFFSET = 5746; // 48
+const static uint64_t SH_FLD_E_OFFSET_E = 5747; // 48
+const static uint64_t SH_FLD_E_OFFSET_E_LEN = 5748; // 48
+const static uint64_t SH_FLD_E_OFFSET_LEN = 5749; // 48
+const static uint64_t SH_FLD_E_TARG_MIN = 5750; // 1
+const static uint64_t SH_FLD_E_TARG_MIN_LEN = 5751; // 1
+const static uint64_t SH_FLD_FACTOR = 5752; // 24
+const static uint64_t SH_FLD_FACTOR_LEN = 5753; // 24
+const static uint64_t SH_FLD_FAIL = 5754; // 4
+const static uint64_t SH_FLD_FAILED_LINK_ON_INTERRUPT = 5755; // 1
+const static uint64_t SH_FLD_FAILING_OPB_MASTER_ACT = 5756; // 3
+const static uint64_t SH_FLD_FAILING_OPB_MASTER_ACT_LEN = 5757; // 3
+const static uint64_t SH_FLD_FAILING_OPB_MASTER_FRST = 5758; // 3
+const static uint64_t SH_FLD_FAILING_OPB_MASTER_FRST_LEN = 5759; // 3
+const static uint64_t SH_FLD_FAIL_REG = 5760; // 1
+const static uint64_t SH_FLD_FAIL_REG_LEN = 5761; // 1
+const static uint64_t SH_FLD_FAIL_TYPE = 5762; // 2
+const static uint64_t SH_FLD_FAIL_TYPE_LEN = 5763; // 2
+const static uint64_t SH_FLD_FARB_CAL_RECVFSM_1HOT = 5764; // 8
+const static uint64_t SH_FLD_FARB_PE = 5765; // 8
+const static uint64_t SH_FLD_FARR = 5766; // 43
+const static uint64_t SH_FLD_FASTPATH_LIMIT = 5767; // 8
+const static uint64_t SH_FLD_FASTPATH_LIMIT_LEN = 5768; // 8
+const static uint64_t SH_FLD_FAST_SIM_CNTR = 5769; // 8
+const static uint64_t SH_FLD_FBC = 5770; // 2
+const static uint64_t SH_FLD_FBC_ADDRESS = 5771; // 1
+const static uint64_t SH_FLD_FBC_ADDRESS_ERROR = 5772; // 1
+const static uint64_t SH_FLD_FBC_ADDRESS_LEN = 5773; // 1
+const static uint64_t SH_FLD_FBC_ADDR_DONE = 5774; // 1
+const static uint64_t SH_FLD_FBC_AFTER_QUIESCE_WAIT_COUNT = 5775; // 1
+const static uint64_t SH_FLD_FBC_AFTER_QUIESCE_WAIT_COUNT_LEN = 5776; // 1
+const static uint64_t SH_FLD_FBC_AUTOINC_ERROR = 5777; // 1
+const static uint64_t SH_FLD_FBC_AUTO_INC = 5778; // 1
+const static uint64_t SH_FLD_FBC_AXTYPE = 5779; // 1
+const static uint64_t SH_FLD_FBC_BEFORE_INIT_WAIT_COUNT = 5780; // 1
+const static uint64_t SH_FLD_FBC_BEFORE_INIT_WAIT_COUNT_LEN = 5781; // 1
+const static uint64_t SH_FLD_FBC_CLEAR_STATUS = 5782; // 1
+const static uint64_t SH_FLD_FBC_COMMAND_ERROR = 5783; // 1
+const static uint64_t SH_FLD_FBC_CRESP_VALUE = 5784; // 1
+const static uint64_t SH_FLD_FBC_CRESP_VALUE_LEN = 5785; // 1
+const static uint64_t SH_FLD_FBC_DATA_DONE = 5786; // 1
+const static uint64_t SH_FLD_FBC_DATA_ONLY = 5787; // 1
+const static uint64_t SH_FLD_FBC_DISABLE = 5788; // 1
+const static uint64_t SH_FLD_FBC_DISABLE_LOCAL_SHORTCUT = 5789; // 1
+const static uint64_t SH_FLD_FBC_DROP_PRIORITY = 5790; // 1
+const static uint64_t SH_FLD_FBC_DROP_PRIORITY_MAX = 5791; // 1
+const static uint64_t SH_FLD_FBC_ECC_CE = 5792; // 1
+const static uint64_t SH_FLD_FBC_ECC_SUE = 5793; // 1
+const static uint64_t SH_FLD_FBC_ECC_UE = 5794; // 1
+const static uint64_t SH_FLD_FBC_LEN = 5795; // 2
+const static uint64_t SH_FLD_FBC_LFSR_DIS = 5796; // 1
+const static uint64_t SH_FLD_FBC_LOCKED = 5797; // 1
+const static uint64_t SH_FLD_FBC_LOCK_ID = 5798; // 1
+const static uint64_t SH_FLD_FBC_LOCK_ID_LEN = 5799; // 1
+const static uint64_t SH_FLD_FBC_OVERRUN_ERROR = 5800; // 1
+const static uint64_t SH_FLD_FBC_OVERWRITE_PBINIT = 5801; // 1
+const static uint64_t SH_FLD_FBC_PBINIT_MISSING = 5802; // 1
+const static uint64_t SH_FLD_FBC_PB_DATA_HANG_ERR = 5803; // 1
+const static uint64_t SH_FLD_FBC_PB_OP_HANG_ERR = 5804; // 1
+const static uint64_t SH_FLD_FBC_PB_UNEXPECT_CRESP_ERR = 5805; // 1
+const static uint64_t SH_FLD_FBC_PB_UNEXPECT_DATA_ERR = 5806; // 1
+const static uint64_t SH_FLD_FBC_PIB_DIRECT = 5807; // 1
+const static uint64_t SH_FLD_FBC_PIB_DIRECT_DONE = 5808; // 1
+const static uint64_t SH_FLD_FBC_PIB_ERROR = 5809; // 1
+const static uint64_t SH_FLD_FBC_PIB_ERROR_LEN = 5810; // 1
+const static uint64_t SH_FLD_FBC_RESET = 5811; // 1
+const static uint64_t SH_FLD_FBC_RESET_FSM = 5812; // 1
+const static uint64_t SH_FLD_FBC_RNW = 5813; // 1
+const static uint64_t SH_FLD_FBC_SCOPE = 5814; // 1
+const static uint64_t SH_FLD_FBC_SCOPE_LEN = 5815; // 1
+const static uint64_t SH_FLD_FBC_START_OP = 5816; // 1
+const static uint64_t SH_FLD_FBC_TSIZE = 5817; // 1
+const static uint64_t SH_FLD_FBC_TSIZE_LEN = 5818; // 1
+const static uint64_t SH_FLD_FBC_TTYPE = 5819; // 1
+const static uint64_t SH_FLD_FBC_TTYPE_LEN = 5820; // 1
+const static uint64_t SH_FLD_FBC_WAIT_CMD_ARBIT = 5821; // 1
+const static uint64_t SH_FLD_FBC_WAIT_PIB_DIRECT = 5822; // 1
+const static uint64_t SH_FLD_FBC_WAIT_RESP = 5823; // 1
+const static uint64_t SH_FLD_FBC_WITH_PBINIT_LOW_WAIT = 5824; // 1
+const static uint64_t SH_FLD_FBC_WITH_POST_INIT = 5825; // 1
+const static uint64_t SH_FLD_FBC_WITH_PRE_QUIESCE = 5826; // 1
+const static uint64_t SH_FLD_FBC_WITH_TM_QUIESCE = 5827; // 1
+const static uint64_t SH_FLD_FENCE = 5828; // 4
+const static uint64_t SH_FLD_FENCE1_DC = 5829; // 1
+const static uint64_t SH_FLD_FENCE2_DC = 5830; // 1
+const static uint64_t SH_FLD_FENCE3_DC = 5831; // 1
+const static uint64_t SH_FLD_FENCE4_DC = 5832; // 1
+const static uint64_t SH_FLD_FENCE5_DC = 5833; // 1
+const static uint64_t SH_FLD_FENCE6_DC = 5834; // 1
+const static uint64_t SH_FLD_FENCE_EISR = 5835; // 24
+const static uint64_t SH_FLD_FENCE_EN = 5836; // 43
+const static uint64_t SH_FLD_FENCE_GX_INTERFACE = 5837; // 1
+const static uint64_t SH_FLD_FENCE_IO_INTERFACE = 5838; // 1
+const static uint64_t SH_FLD_FENCE_TLBIE = 5839; // 12
+const static uint64_t SH_FLD_FFE_BOOST_EN = 5840; // 6
+const static uint64_t SH_FLD_FF_BYPASS = 5841; // 6
+const static uint64_t SH_FLD_FF_SLEWRATE = 5842; // 6
+const static uint64_t SH_FLD_FF_SLEWRATE_LEN = 5843; // 6
+const static uint64_t SH_FLD_FGAT = 5844; // 1
+const static uint64_t SH_FLD_FGAT_0 = 5845; // 1
+const static uint64_t SH_FLD_FGAT_1 = 5846; // 1
+const static uint64_t SH_FLD_FGAT_2 = 5847; // 1
+const static uint64_t SH_FLD_FGAT_3 = 5848; // 1
+const static uint64_t SH_FLD_FIFO_BITS_READ0_0 = 5849; // 2
+const static uint64_t SH_FLD_FIFO_BITS_READ0_0_LEN = 5850; // 2
+const static uint64_t SH_FLD_FIFO_BITS_READ0_1 = 5851; // 2
+const static uint64_t SH_FLD_FIFO_BITS_READ0_1_LEN = 5852; // 2
+const static uint64_t SH_FLD_FIFO_BITS_READ0_2 = 5853; // 2
+const static uint64_t SH_FLD_FIFO_BITS_READ0_2_LEN = 5854; // 2
+const static uint64_t SH_FLD_FIFO_BITS_READ0_3 = 5855; // 2
+const static uint64_t SH_FLD_FIFO_BITS_READ0_3_LEN = 5856; // 2
+const static uint64_t SH_FLD_FIFO_DLY_CFG = 5857; // 120
+const static uint64_t SH_FLD_FIFO_DLY_CFG_LEN = 5858; // 120
+const static uint64_t SH_FLD_FIFO_EMPTY = 5859; // 1
+const static uint64_t SH_FLD_FIFO_ENTRY_COUNT = 5860; // 1
+const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_0 = 5861; // 1
+const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_0_LEN = 5862; // 1
+const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_1 = 5863; // 1
+const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_1_LEN = 5864; // 1
+const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_2 = 5865; // 1
+const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_2_LEN = 5866; // 1
+const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_3 = 5867; // 1
+const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_3_LEN = 5868; // 1
+const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_LEN = 5869; // 1
+const static uint64_t SH_FLD_FIFO_EOT_FLAGS = 5870; // 1
+const static uint64_t SH_FLD_FIFO_EOT_FLAGS_LEN = 5871; // 1
+const static uint64_t SH_FLD_FIFO_FINAL_L2U_DLY = 5872; // 4
+const static uint64_t SH_FLD_FIFO_FINAL_L2U_DLY_LEN = 5873; // 4
+const static uint64_t SH_FLD_FIFO_FULL = 5874; // 7
+const static uint64_t SH_FLD_FIFO_HALF_DEPTH_MODE = 5875; // 72
+const static uint64_t SH_FLD_FIFO_HALF_WIDTH_MODE = 5876; // 140
+const static uint64_t SH_FLD_FIFO_INITIAL_L2U_DLY = 5877; // 4
+const static uint64_t SH_FLD_FIFO_INITIAL_L2U_DLY_LEN = 5878; // 4
+const static uint64_t SH_FLD_FIFO_L2U_DLY = 5879; // 188
+const static uint64_t SH_FLD_FIFO_L2U_DLY_LEN = 5880; // 188
+const static uint64_t SH_FLD_FIFO_VALID_FLAGS = 5881; // 1
+const static uint64_t SH_FLD_FIFO_VALID_FLAGS_LEN = 5882; // 1
+const static uint64_t SH_FLD_FILTDIVSEL = 5883; // 3
+const static uint64_t SH_FLD_FILTDIVSEL_LEN = 5884; // 3
+const static uint64_t SH_FLD_FILTER_MODE = 5885; // 6
+const static uint64_t SH_FLD_FILTER_MODE_LEN = 5886; // 6
+const static uint64_t SH_FLD_FINAL_NOP_CS = 5887; // 4
+const static uint64_t SH_FLD_FINE_CAL_STEP_SIZE = 5888; // 8
+const static uint64_t SH_FLD_FINE_CAL_STEP_SIZE_LEN = 5889; // 8
+const static uint64_t SH_FLD_FIR = 5890; // 49
+const static uint64_t SH_FLD_FIR0_CR0_ATAG_PERR = 5891; // 12
+const static uint64_t SH_FLD_FIR0_CR0_TTAG_PERR = 5892; // 12
+const static uint64_t SH_FLD_FIR0_CR1_ATAG_PERR = 5893; // 12
+const static uint64_t SH_FLD_FIR0_CR1_TTAG_PERR = 5894; // 12
+const static uint64_t SH_FLD_FIR0_CR2_ATAG_PERR = 5895; // 12
+const static uint64_t SH_FLD_FIR0_CR2_TTAG_PERR = 5896; // 12
+const static uint64_t SH_FLD_FIR0_CR3_ATAG_PERR = 5897; // 12
+const static uint64_t SH_FLD_FIR0_CR3_TTAG_PERR = 5898; // 12
+const static uint64_t SH_FLD_FIR0_ILLEGAL_STORE_SIZE = 5899; // 12
+const static uint64_t SH_FLD_FIR0_IMA_FSM_TIMEOUT = 5900; // 12
+const static uint64_t SH_FLD_FIR0_LD_AMO_SEQ = 5901; // 12
+const static uint64_t SH_FLD_FIR0_OVERFLOW = 5902; // 12
+const static uint64_t SH_FLD_FIR0_PBARB_TRASHMODE = 5903; // 12
+const static uint64_t SH_FLD_FIR0_PPE_RD_FSM_TIMEOUT = 5904; // 12
+const static uint64_t SH_FLD_FIR0_PPE_WR_FSM_TIMEOUT = 5905; // 12
+const static uint64_t SH_FLD_FIR0_PURGE_ABORT_LVL_ERR1 = 5906; // 12
+const static uint64_t SH_FLD_FIR0_PURGE_ABORT_LVL_ERR2 = 5907; // 12
+const static uint64_t SH_FLD_FIR0_PURGE_DONE_LVL_ERR1 = 5908; // 12
+const static uint64_t SH_FLD_FIR0_PURGE_LVL_ERR1 = 5909; // 12
+const static uint64_t SH_FLD_FIR0_PURGE_LVL_ERR2 = 5910; // 12
+const static uint64_t SH_FLD_FIR0_SNP0_ADDR_PERR = 5911; // 12
+const static uint64_t SH_FLD_FIR0_SNP0_TTAG_PERR = 5912; // 12
+const static uint64_t SH_FLD_FIR0_SNP1_ADDR_PERR = 5913; // 12
+const static uint64_t SH_FLD_FIR0_SNP1_TTAG_PERR = 5914; // 12
+const static uint64_t SH_FLD_FIR0_TLB_DATA_PAR = 5915; // 12
+const static uint64_t SH_FLD_FIR11_LRU_MEM_INVALID_ABCD = 5916; // 12
+const static uint64_t SH_FLD_FIR11_LRU_MEM_INVALID_EFGH = 5917; // 12
+const static uint64_t SH_FLD_FIR14_B01_BOTH_ACTIVE = 5918; // 12
+const static uint64_t SH_FLD_FIR14_B0_SD_DIR_MULT_HIT = 5919; // 12
+const static uint64_t SH_FLD_FIR14_B1_SD_DIR_MULT_HIT = 5920; // 12
+const static uint64_t SH_FLD_FIR14_B2_SD_DIR_MULT_HIT = 5921; // 12
+const static uint64_t SH_FLD_FIR14_B3_SD_DIR_MULT_HIT = 5922; // 12
+const static uint64_t SH_FLD_FIR14_BAD_FP_MATE = 5923; // 12
+const static uint64_t SH_FLD_FIR14_COX_UNEXP_IDLE_PB_CRESP = 5924; // 12
+const static uint64_t SH_FLD_FIR14_CR0_ATAG_PERR = 5925; // 12
+const static uint64_t SH_FLD_FIR14_CR0_TTAG_PERR = 5926; // 12
+const static uint64_t SH_FLD_FIR14_CR1_ATAG_PERR = 5927; // 12
+const static uint64_t SH_FLD_FIR14_CR1_TTAG_PERR = 5928; // 12
+const static uint64_t SH_FLD_FIR14_CR2_ATAG_PERR = 5929; // 12
+const static uint64_t SH_FLD_FIR14_CR2_TTAG_PERR = 5930; // 12
+const static uint64_t SH_FLD_FIR14_CR3_ATAG_PERR = 5931; // 12
+const static uint64_t SH_FLD_FIR14_CR3_TTAG_PERR = 5932; // 12
+const static uint64_t SH_FLD_FIR14_DW_SET_REF_WITH_FLAG_IDLE = 5933; // 12
+const static uint64_t SH_FLD_FIR14_DW_SET_SI_BY_MACH = 5934; // 12
+const static uint64_t SH_FLD_FIR14_HANG_WAITING_FOR_FP_MATE = 5935; // 12
+const static uint64_t SH_FLD_FIR14_IFU_MULT_REQ = 5936; // 12
+const static uint64_t SH_FLD_FIR14_INVALID_SNP_CPS_STATU_RTN = 5937; // 12
+const static uint64_t SH_FLD_FIR14_KILL_REF_WITH_FLAG_IDLE = 5938; // 12
+const static uint64_t SH_FLD_FIR14_L3PF_MACH_DONE = 5939; // 12
+const static uint64_t SH_FLD_FIR14_L3PF_REQ = 5940; // 12
+const static uint64_t SH_FLD_FIR14_LSU_TAG_REUSE = 5941; // 12
+const static uint64_t SH_FLD_FIR14_NCCTL_RLD_BARRIER = 5942; // 12
+const static uint64_t SH_FLD_FIR14_NCCTL_SNP = 5943; // 12
+const static uint64_t SH_FLD_FIR14_NCCTL_SYNC = 5944; // 12
+const static uint64_t SH_FLD_FIR14_NCCTL_TLBIE_ACK = 5945; // 12
+const static uint64_t SH_FLD_FIR14_NCCTL_VSYNC = 5946; // 12
+const static uint64_t SH_FLD_FIR14_NCU_TID_DONE = 5947; // 12
+const static uint64_t SH_FLD_FIR14_PBARB_FSM_REQ_OVERFLOW = 5948; // 12
+const static uint64_t SH_FLD_FIR14_PBARB_TRASHMODE_PB_REQ = 5949; // 12
+const static uint64_t SH_FLD_FIR14_PD_DIR_MULT_HIT = 5950; // 12
+const static uint64_t SH_FLD_FIR14_PHANTOM_B01_REQ = 5951; // 12
+const static uint64_t SH_FLD_FIR14_RCMD0_ADDR_PERR = 5952; // 12
+const static uint64_t SH_FLD_FIR14_RCMD0_TTAG_PERR = 5953; // 12
+const static uint64_t SH_FLD_FIR14_RCMD1_ADDR_PERR = 5954; // 12
+const static uint64_t SH_FLD_FIR14_RCMD1_TTAG_PERR = 5955; // 12
+const static uint64_t SH_FLD_FIR14_RCMD2_ADDR_PERR = 5956; // 12
+const static uint64_t SH_FLD_FIR14_RCMD2_TTAG_PERR = 5957; // 12
+const static uint64_t SH_FLD_FIR14_RCMD3_ADDR_PERR = 5958; // 12
+const static uint64_t SH_FLD_FIR14_RCMD3_TTAG_PERR = 5959; // 12
+const static uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_L3_CRESP = 5960; // 12
+const static uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_L3_DWDONE = 5961; // 12
+const static uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_PBL3_DATA = 5962; // 12
+const static uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_PB_CRESP = 5963; // 12
+const static uint64_t SH_FLD_FIR14_RCX_UNEXP_PB_RC_DTAG_PCHK = 5964; // 12
+const static uint64_t SH_FLD_FIR14_RC_PBBUS_SFSTAT = 5965; // 12
+const static uint64_t SH_FLD_FIR14_RC_UNEXP_DIRSTAT_VS_DSECT_CHK = 5966; // 12
+const static uint64_t SH_FLD_FIR14_RC_UNEXP_F2_DATA = 5967; // 12
+const static uint64_t SH_FLD_FIR14_RC_UNEXP_PURG_HIT = 5968; // 12
+const static uint64_t SH_FLD_FIR14_RVCTL = 5969; // 12
+const static uint64_t SH_FLD_FIR14_SRCTL0_BAD_HPC = 5970; // 12
+const static uint64_t SH_FLD_FIR14_SRCTL1_BAD_HPC = 5971; // 12
+const static uint64_t SH_FLD_FIR14_SRCTL2_BAD_HPC = 5972; // 12
+const static uint64_t SH_FLD_FIR14_SRCTL3_BAD_HPC = 5973; // 12
+const static uint64_t SH_FLD_FIR14_STQ_COMING = 5974; // 12
+const static uint64_t SH_FLD_FIR14_STQ_OVERFLOW = 5975; // 12
+const static uint64_t SH_FLD_FIR14_TMA_LARXA_VS_FRCMISS_SV = 5976; // 12
+const static uint64_t SH_FLD_FIR14_TMCTL_TIDX_TEND_LDST_SEQ = 5977; // 12
+const static uint64_t SH_FLD_FIR14_XLT_QUEUE_OVRFLW = 5978; // 12
+const static uint64_t SH_FLD_FIR14_XPF_MULT_REQ = 5979; // 12
+const static uint64_t SH_FLD_FIR19_LD_TGT_NODAL_DINC = 5980; // 12
+const static uint64_t SH_FLD_FIR19_ST_TGT_NODAL_DINC = 5981; // 12
+const static uint64_t SH_FLD_FIR1_MASTER_SEQ_ID_PAR = 5982; // 12
+const static uint64_t SH_FLD_FIR1_SNOOP_TLBIE_SEQ_PARITY = 5983; // 12
+const static uint64_t SH_FLD_FIR1_TLBIE_BAD_OP = 5984; // 12
+const static uint64_t SH_FLD_FIR37_RC_TGT_NODAL_REQ_CRESP_DINC = 5985; // 12
+const static uint64_t SH_FLD_FIR37_SN_TGT_NODAL_REQ_CRESP_DINC = 5986; // 12
+const static uint64_t SH_FLD_FIR9_PEC_PHASE3_TIMEOUT = 5987; // 12
+const static uint64_t SH_FLD_FIR9_PEC_PHASE4_RCCO_DISP_FAIL = 5988; // 12
+const static uint64_t SH_FLD_FIR9_PEC_PHASE4_SAME = 5989; // 12
+const static uint64_t SH_FLD_FIR9_PEC_PHASE5_TIMEOUT = 5990; // 12
+const static uint64_t SH_FLD_FIRMWARE_ATTN0 = 5991; // 4
+const static uint64_t SH_FLD_FIRMWARE_ATTN1 = 5992; // 4
+const static uint64_t SH_FLD_FIRST_ERROR = 5993; // 3
+const static uint64_t SH_FLD_FIRST_ERROR_LEN = 5994; // 3
+const static uint64_t SH_FLD_FIR_ACTION0 = 5995; // 13
+const static uint64_t SH_FLD_FIR_ACTION0_LEN = 5996; // 13
+const static uint64_t SH_FLD_FIR_ACTION1 = 5997; // 13
+const static uint64_t SH_FLD_FIR_ACTION1_LEN = 5998; // 13
+const static uint64_t SH_FLD_FIR_LEN = 5999; // 49
+const static uint64_t SH_FLD_FIR_MASK = 6000; // 16
+const static uint64_t SH_FLD_FIR_MASK_LEN = 6001; // 16
+const static uint64_t SH_FLD_FIR_PARITY_ERR = 6002; // 13
+const static uint64_t SH_FLD_FIR_PARITY_ERR2 = 6003; // 1
+const static uint64_t SH_FLD_FIR_PARITY_ERR2_MASK = 6004; // 1
+const static uint64_t SH_FLD_FIR_PARITY_ERR_DUP = 6005; // 12
+const static uint64_t SH_FLD_FIR_PARITY_ERR_MASK = 6006; // 1
+const static uint64_t SH_FLD_FIR_RESET = 6007; // 6
+const static uint64_t SH_FLD_FIR_TRIGGER = 6008; // 17
+const static uint64_t SH_FLD_FIT_SEL = 6009; // 17
+const static uint64_t SH_FLD_FIT_SEL_LEN = 6010; // 17
+const static uint64_t SH_FLD_FLAG = 6011; // 2
+const static uint64_t SH_FLD_FLUSH_ALIGN_OVR = 6012; // 43
+const static uint64_t SH_FLD_FLUSH_CP_IG_STATE_MAP = 6013; // 2
+const static uint64_t SH_FLD_FLUSH_CP_IG_STATE_MAP_LEN = 6014; // 2
+const static uint64_t SH_FLD_FLUSH_IC = 6015; // 24
+const static uint64_t SH_FLD_FLUSH_SCAN_N = 6016; // 43
+const static uint64_t SH_FLD_FLUSH_SUE_STATE_MAP = 6017; // 2
+const static uint64_t SH_FLD_FLUSH_SUE_STATE_MAP_LEN = 6018; // 2
+const static uint64_t SH_FLD_FMAX = 6019; // 6
+const static uint64_t SH_FLD_FMAX_LEN = 6020; // 6
+const static uint64_t SH_FLD_FMIN = 6021; // 6
+const static uint64_t SH_FLD_FMIN_LEN = 6022; // 6
+const static uint64_t SH_FLD_FMR00_TRAINED = 6023; // 4
+const static uint64_t SH_FLD_FMR01_TRAINED = 6024; // 4
+const static uint64_t SH_FLD_FMR02_TRAINED = 6025; // 4
+const static uint64_t SH_FLD_FMR03_TRAINED = 6026; // 4
+const static uint64_t SH_FLD_FMR04_TRAINED = 6027; // 4
+const static uint64_t SH_FLD_FMR05_TRAINED = 6028; // 4
+const static uint64_t SH_FLD_FMR06_TRAINED = 6029; // 2
+const static uint64_t SH_FLD_FMR07_TRAINED = 6030; // 2
+const static uint64_t SH_FLD_FORCE_BYPASS = 6031; // 1
+const static uint64_t SH_FLD_FORCE_CL_INJECT = 6032; // 1
+const static uint64_t SH_FLD_FORCE_DOUBLE_BIT_ECC_ERR = 6033; // 4
+const static uint64_t SH_FLD_FORCE_ECC_CE = 6034; // 2
+const static uint64_t SH_FLD_FORCE_ECC_SEL = 6035; // 1
+const static uint64_t SH_FLD_FORCE_ECC_SEL_0_1 = 6036; // 1
+const static uint64_t SH_FLD_FORCE_ECC_SEL_0_1_LEN = 6037; // 1
+const static uint64_t SH_FLD_FORCE_ECC_UE = 6038; // 2
+const static uint64_t SH_FLD_FORCE_MAX_SCOPE_INTRP = 6039; // 1
+const static uint64_t SH_FLD_FORCE_MPR = 6040; // 8
+const static uint64_t SH_FLD_FORCE_NON_INBAND_CL_FULL = 6041; // 4
+const static uint64_t SH_FLD_FORCE_ON_CLK_GATE = 6042; // 8
+const static uint64_t SH_FLD_FORCE_PR_INJECT = 6043; // 1
+const static uint64_t SH_FLD_FORCE_RESERVED = 6044; // 8
+const static uint64_t SH_FLD_FORCE_RESET = 6045; // 1
+const static uint64_t SH_FLD_FORCE_SFSTAT_ACTIVE = 6046; // 4
+const static uint64_t SH_FLD_FORCE_SINGLE_BIT_ECC_ERR = 6047; // 4
+const static uint64_t SH_FLD_FORCE_THRES_ACT = 6048; // 43
+const static uint64_t SH_FLD_FORCE_VG_SYS_INTRP = 6049; // 1
+const static uint64_t SH_FLD_FOREIGN_LINK_HANG_ERROR = 6050; // 4
+const static uint64_t SH_FLD_FP0_CREDIT_PRIORITY_4_NOT_8 = 6051; // 2
+const static uint64_t SH_FLD_FP0_DISABLE_CMD_COMPRESSION = 6052; // 2
+const static uint64_t SH_FLD_FP0_DISABLE_GATHERING = 6053; // 2
+const static uint64_t SH_FLD_FP0_DISABLE_PRSP_COMPRESSION = 6054; // 2
+const static uint64_t SH_FLD_FP0_FMR_DISABLE = 6055; // 2
+const static uint64_t SH_FLD_FP0_FMR_SPARE = 6056; // 2
+const static uint64_t SH_FLD_FP0_FMR_SPARE_LEN = 6057; // 2
+const static uint64_t SH_FLD_FP0_LL_CREDIT_HI_LIMIT = 6058; // 2
+const static uint64_t SH_FLD_FP0_LL_CREDIT_HI_LIMIT_LEN = 6059; // 2
+const static uint64_t SH_FLD_FP0_LL_CREDIT_LO_LIMIT = 6060; // 2
+const static uint64_t SH_FLD_FP0_LL_CREDIT_LO_LIMIT_LEN = 6061; // 2
+const static uint64_t SH_FLD_FP0_PRS_DISABLE = 6062; // 2
+const static uint64_t SH_FLD_FP0_PRS_SPARE = 6063; // 2
+const static uint64_t SH_FLD_FP0_PRS_SPARE_LEN = 6064; // 2
+const static uint64_t SH_FLD_FP0_RUN_AFTER_FRAME_ERROR = 6065; // 2
+const static uint64_t SH_FLD_FP1_CREDIT_PRIORITY_4_NOT_8 = 6066; // 2
+const static uint64_t SH_FLD_FP1_DISABLE_CMD_COMPRESSION = 6067; // 2
+const static uint64_t SH_FLD_FP1_DISABLE_GATHERING = 6068; // 2
+const static uint64_t SH_FLD_FP1_DISABLE_PRSP_COMPRESSION = 6069; // 2
+const static uint64_t SH_FLD_FP1_FMR_DISABLE = 6070; // 2
+const static uint64_t SH_FLD_FP1_FMR_SPARE = 6071; // 2
+const static uint64_t SH_FLD_FP1_FMR_SPARE_LEN = 6072; // 2
+const static uint64_t SH_FLD_FP1_LL_CREDIT_HI_LIMIT = 6073; // 2
+const static uint64_t SH_FLD_FP1_LL_CREDIT_HI_LIMIT_LEN = 6074; // 2
+const static uint64_t SH_FLD_FP1_LL_CREDIT_LO_LIMIT = 6075; // 2
+const static uint64_t SH_FLD_FP1_LL_CREDIT_LO_LIMIT_LEN = 6076; // 2
+const static uint64_t SH_FLD_FP1_PRS_DISABLE = 6077; // 2
+const static uint64_t SH_FLD_FP1_PRS_SPARE = 6078; // 2
+const static uint64_t SH_FLD_FP1_PRS_SPARE_LEN = 6079; // 2
+const static uint64_t SH_FLD_FP1_RUN_AFTER_FRAME_ERROR = 6080; // 2
+const static uint64_t SH_FLD_FP2_CREDIT_PRIORITY_4_NOT_8 = 6081; // 2
+const static uint64_t SH_FLD_FP2_DISABLE_CMD_COMPRESSION = 6082; // 2
+const static uint64_t SH_FLD_FP2_DISABLE_GATHERING = 6083; // 2
+const static uint64_t SH_FLD_FP2_DISABLE_PRSP_COMPRESSION = 6084; // 2
+const static uint64_t SH_FLD_FP2_FMR_DISABLE = 6085; // 2
+const static uint64_t SH_FLD_FP2_FMR_SPARE = 6086; // 2
+const static uint64_t SH_FLD_FP2_FMR_SPARE_LEN = 6087; // 2
+const static uint64_t SH_FLD_FP2_LL_CREDIT_HI_LIMIT = 6088; // 2
+const static uint64_t SH_FLD_FP2_LL_CREDIT_HI_LIMIT_LEN = 6089; // 2
+const static uint64_t SH_FLD_FP2_LL_CREDIT_LO_LIMIT = 6090; // 2
+const static uint64_t SH_FLD_FP2_LL_CREDIT_LO_LIMIT_LEN = 6091; // 2
+const static uint64_t SH_FLD_FP2_PRS_DISABLE = 6092; // 2
+const static uint64_t SH_FLD_FP2_PRS_SPARE = 6093; // 2
+const static uint64_t SH_FLD_FP2_PRS_SPARE_LEN = 6094; // 2
+const static uint64_t SH_FLD_FP2_RUN_AFTER_FRAME_ERROR = 6095; // 2
+const static uint64_t SH_FLD_FP3_CREDIT_PRIORITY_4_NOT_8 = 6096; // 2
+const static uint64_t SH_FLD_FP3_DISABLE_CMD_COMPRESSION = 6097; // 2
+const static uint64_t SH_FLD_FP3_DISABLE_GATHERING = 6098; // 2
+const static uint64_t SH_FLD_FP3_DISABLE_PRSP_COMPRESSION = 6099; // 2
+const static uint64_t SH_FLD_FP3_FMR_DISABLE = 6100; // 2
+const static uint64_t SH_FLD_FP3_FMR_SPARE = 6101; // 2
+const static uint64_t SH_FLD_FP3_FMR_SPARE_LEN = 6102; // 2
+const static uint64_t SH_FLD_FP3_LL_CREDIT_HI_LIMIT = 6103; // 2
+const static uint64_t SH_FLD_FP3_LL_CREDIT_HI_LIMIT_LEN = 6104; // 2
+const static uint64_t SH_FLD_FP3_LL_CREDIT_LO_LIMIT = 6105; // 2
+const static uint64_t SH_FLD_FP3_LL_CREDIT_LO_LIMIT_LEN = 6106; // 2
+const static uint64_t SH_FLD_FP3_PRS_DISABLE = 6107; // 2
+const static uint64_t SH_FLD_FP3_PRS_SPARE = 6108; // 2
+const static uint64_t SH_FLD_FP3_PRS_SPARE_LEN = 6109; // 2
+const static uint64_t SH_FLD_FP3_RUN_AFTER_FRAME_ERROR = 6110; // 2
+const static uint64_t SH_FLD_FP4_CREDIT_PRIORITY_4_NOT_8 = 6111; // 2
+const static uint64_t SH_FLD_FP4_DISABLE_CMD_COMPRESSION = 6112; // 2
+const static uint64_t SH_FLD_FP4_DISABLE_GATHERING = 6113; // 2
+const static uint64_t SH_FLD_FP4_DISABLE_PRSP_COMPRESSION = 6114; // 2
+const static uint64_t SH_FLD_FP4_FMR_DISABLE = 6115; // 2
+const static uint64_t SH_FLD_FP4_FMR_SPARE = 6116; // 2
+const static uint64_t SH_FLD_FP4_FMR_SPARE_LEN = 6117; // 2
+const static uint64_t SH_FLD_FP4_LL_CREDIT_HI_LIMIT = 6118; // 2
+const static uint64_t SH_FLD_FP4_LL_CREDIT_HI_LIMIT_LEN = 6119; // 2
+const static uint64_t SH_FLD_FP4_LL_CREDIT_LO_LIMIT = 6120; // 2
+const static uint64_t SH_FLD_FP4_LL_CREDIT_LO_LIMIT_LEN = 6121; // 2
+const static uint64_t SH_FLD_FP4_PRS_DISABLE = 6122; // 2
+const static uint64_t SH_FLD_FP4_PRS_SPARE = 6123; // 2
+const static uint64_t SH_FLD_FP4_PRS_SPARE_LEN = 6124; // 2
+const static uint64_t SH_FLD_FP4_RUN_AFTER_FRAME_ERROR = 6125; // 2
+const static uint64_t SH_FLD_FP5_CREDIT_PRIORITY_4_NOT_8 = 6126; // 2
+const static uint64_t SH_FLD_FP5_DISABLE_CMD_COMPRESSION = 6127; // 2
+const static uint64_t SH_FLD_FP5_DISABLE_GATHERING = 6128; // 2
+const static uint64_t SH_FLD_FP5_DISABLE_PRSP_COMPRESSION = 6129; // 2
+const static uint64_t SH_FLD_FP5_FMR_DISABLE = 6130; // 2
+const static uint64_t SH_FLD_FP5_FMR_SPARE = 6131; // 2
+const static uint64_t SH_FLD_FP5_FMR_SPARE_LEN = 6132; // 2
+const static uint64_t SH_FLD_FP5_LL_CREDIT_HI_LIMIT = 6133; // 2
+const static uint64_t SH_FLD_FP5_LL_CREDIT_HI_LIMIT_LEN = 6134; // 2
+const static uint64_t SH_FLD_FP5_LL_CREDIT_LO_LIMIT = 6135; // 2
+const static uint64_t SH_FLD_FP5_LL_CREDIT_LO_LIMIT_LEN = 6136; // 2
+const static uint64_t SH_FLD_FP5_PRS_DISABLE = 6137; // 2
+const static uint64_t SH_FLD_FP5_PRS_SPARE = 6138; // 2
+const static uint64_t SH_FLD_FP5_PRS_SPARE_LEN = 6139; // 2
+const static uint64_t SH_FLD_FP5_RUN_AFTER_FRAME_ERROR = 6140; // 2
+const static uint64_t SH_FLD_FP6_CREDIT_PRIORITY_4_NOT_8 = 6141; // 1
+const static uint64_t SH_FLD_FP6_DISABLE_CMD_COMPRESSION = 6142; // 1
+const static uint64_t SH_FLD_FP6_DISABLE_GATHERING = 6143; // 1
+const static uint64_t SH_FLD_FP6_DISABLE_PRSP_COMPRESSION = 6144; // 1
+const static uint64_t SH_FLD_FP6_FMR_DISABLE = 6145; // 1
+const static uint64_t SH_FLD_FP6_FMR_SPARE = 6146; // 1
+const static uint64_t SH_FLD_FP6_FMR_SPARE_LEN = 6147; // 1
+const static uint64_t SH_FLD_FP6_LL_CREDIT_HI_LIMIT = 6148; // 1
+const static uint64_t SH_FLD_FP6_LL_CREDIT_HI_LIMIT_LEN = 6149; // 1
+const static uint64_t SH_FLD_FP6_LL_CREDIT_LO_LIMIT = 6150; // 1
+const static uint64_t SH_FLD_FP6_LL_CREDIT_LO_LIMIT_LEN = 6151; // 1
+const static uint64_t SH_FLD_FP6_PRS_DISABLE = 6152; // 1
+const static uint64_t SH_FLD_FP6_PRS_SPARE = 6153; // 1
+const static uint64_t SH_FLD_FP6_PRS_SPARE_LEN = 6154; // 1
+const static uint64_t SH_FLD_FP6_RUN_AFTER_FRAME_ERROR = 6155; // 1
+const static uint64_t SH_FLD_FP7_CREDIT_PRIORITY_4_NOT_8 = 6156; // 1
+const static uint64_t SH_FLD_FP7_DISABLE_CMD_COMPRESSION = 6157; // 1
+const static uint64_t SH_FLD_FP7_DISABLE_GATHERING = 6158; // 1
+const static uint64_t SH_FLD_FP7_DISABLE_PRSP_COMPRESSION = 6159; // 1
+const static uint64_t SH_FLD_FP7_FMR_DISABLE = 6160; // 1
+const static uint64_t SH_FLD_FP7_FMR_SPARE = 6161; // 1
+const static uint64_t SH_FLD_FP7_FMR_SPARE_LEN = 6162; // 1
+const static uint64_t SH_FLD_FP7_LL_CREDIT_HI_LIMIT = 6163; // 1
+const static uint64_t SH_FLD_FP7_LL_CREDIT_HI_LIMIT_LEN = 6164; // 1
+const static uint64_t SH_FLD_FP7_LL_CREDIT_LO_LIMIT = 6165; // 1
+const static uint64_t SH_FLD_FP7_LL_CREDIT_LO_LIMIT_LEN = 6166; // 1
+const static uint64_t SH_FLD_FP7_PRS_DISABLE = 6167; // 1
+const static uint64_t SH_FLD_FP7_PRS_SPARE = 6168; // 1
+const static uint64_t SH_FLD_FP7_PRS_SPARE_LEN = 6169; // 1
+const static uint64_t SH_FLD_FP7_RUN_AFTER_FRAME_ERROR = 6170; // 1
+const static uint64_t SH_FLD_FRAC1 = 6171; // 3
+const static uint64_t SH_FLD_FRAC1_LEN = 6172; // 3
+const static uint64_t SH_FLD_FRAC2 = 6173; // 3
+const static uint64_t SH_FLD_FRAC2_LEN = 6174; // 3
+const static uint64_t SH_FLD_FRAMER00_ATTN = 6175; // 4
+const static uint64_t SH_FLD_FRAMER01_ATTN = 6176; // 4
+const static uint64_t SH_FLD_FRAMER02_ATTN = 6177; // 4
+const static uint64_t SH_FLD_FRAMER03_ATTN = 6178; // 4
+const static uint64_t SH_FLD_FRAMER04_ATTN = 6179; // 4
+const static uint64_t SH_FLD_FRAMER05_ATTN = 6180; // 4
+const static uint64_t SH_FLD_FRAMER06_ATTN = 6181; // 2
+const static uint64_t SH_FLD_FRAMER07_ATTN = 6182; // 2
+const static uint64_t SH_FLD_FRAME_COUNT = 6183; // 8
+const static uint64_t SH_FLD_FRAME_COUNT_LEN = 6184; // 8
+const static uint64_t SH_FLD_FRAME_SIZE = 6185; // 1
+const static uint64_t SH_FLD_FRAME_SIZE_LEN = 6186; // 1
+const static uint64_t SH_FLD_FREEZE = 6187; // 2
+const static uint64_t SH_FLD_FREEZE_LOG_ON_ERROR1 = 6188; // 1
+const static uint64_t SH_FLD_FREEZE_LOG_ON_ERROR2 = 6189; // 1
+const static uint64_t SH_FLD_FREEZE_LOG_ON_ERROR3 = 6190; // 1
+const static uint64_t SH_FLD_FREEZE_LOG_ON_ERROR4 = 6191; // 1
+const static uint64_t SH_FLD_FREEZE_LOG_ON_ERROR5 = 6192; // 1
+const static uint64_t SH_FLD_FREEZE_LOG_ON_ERROR6 = 6193; // 1
+const static uint64_t SH_FLD_FREEZE_LOG_ON_ERROR7 = 6194; // 1
+const static uint64_t SH_FLD_FREEZE_ON_OVERFLOW = 6195; // 2
+const static uint64_t SH_FLD_FREE_USAGE_10E = 6196; // 19
+const static uint64_t SH_FLD_FREE_USAGE_11E = 6197; // 19
+const static uint64_t SH_FLD_FREE_USAGE_12D = 6198; // 38
+const static uint64_t SH_FLD_FREE_USAGE_12E = 6199; // 41
+const static uint64_t SH_FLD_FREE_USAGE_13D = 6200; // 38
+const static uint64_t SH_FLD_FREE_USAGE_13E = 6201; // 41
+const static uint64_t SH_FLD_FREE_USAGE_14D = 6202; // 16
+const static uint64_t SH_FLD_FREE_USAGE_14E = 6203; // 41
+const static uint64_t SH_FLD_FREE_USAGE_15D = 6204; // 40
+const static uint64_t SH_FLD_FREE_USAGE_15E = 6205; // 41
+const static uint64_t SH_FLD_FREE_USAGE_16D = 6206; // 38
+const static uint64_t SH_FLD_FREE_USAGE_16E = 6207; // 41
+const static uint64_t SH_FLD_FREE_USAGE_17D = 6208; // 38
+const static uint64_t SH_FLD_FREE_USAGE_17E = 6209; // 41
+const static uint64_t SH_FLD_FREE_USAGE_18D = 6210; // 40
+const static uint64_t SH_FLD_FREE_USAGE_18E = 6211; // 41
+const static uint64_t SH_FLD_FREE_USAGE_19D = 6212; // 41
+const static uint64_t SH_FLD_FREE_USAGE_19E = 6213; // 41
+const static uint64_t SH_FLD_FREE_USAGE_20D = 6214; // 41
+const static uint64_t SH_FLD_FREE_USAGE_20E = 6215; // 43
+const static uint64_t SH_FLD_FREE_USAGE_21D = 6216; // 41
+const static uint64_t SH_FLD_FREE_USAGE_21E = 6217; // 43
+const static uint64_t SH_FLD_FREE_USAGE_22D = 6218; // 41
+const static uint64_t SH_FLD_FREE_USAGE_22E = 6219; // 43
+const static uint64_t SH_FLD_FREE_USAGE_23D = 6220; // 41
+const static uint64_t SH_FLD_FREE_USAGE_23E = 6221; // 43
+const static uint64_t SH_FLD_FREE_USAGE_24D = 6222; // 41
+const static uint64_t SH_FLD_FREE_USAGE_25D = 6223; // 41
+const static uint64_t SH_FLD_FREE_USAGE_26D = 6224; // 42
+const static uint64_t SH_FLD_FREE_USAGE_27D = 6225; // 42
+const static uint64_t SH_FLD_FREE_USAGE_28D = 6226; // 40
+const static uint64_t SH_FLD_FREE_USAGE_29D = 6227; // 40
+const static uint64_t SH_FLD_FREE_USAGE_30D = 6228; // 40
+const static uint64_t SH_FLD_FREE_USAGE_31D = 6229; // 40
+const static uint64_t SH_FLD_FREE_USAGE_44C = 6230; // 43
+const static uint64_t SH_FLD_FREE_USAGE_45C = 6231; // 43
+const static uint64_t SH_FLD_FREE_USAGE_46C = 6232; // 43
+const static uint64_t SH_FLD_FREE_USAGE_47C = 6233; // 43
+const static uint64_t SH_FLD_FREE_USAGE_48A = 6234; // 43
+const static uint64_t SH_FLD_FREE_USAGE_49A = 6235; // 43
+const static uint64_t SH_FLD_FREE_USAGE_50A = 6236; // 43
+const static uint64_t SH_FLD_FREE_USAGE_51A = 6237; // 43
+const static uint64_t SH_FLD_FREE_USAGE_52A = 6238; // 43
+const static uint64_t SH_FLD_FREE_USAGE_53A = 6239; // 43
+const static uint64_t SH_FLD_FREE_USAGE_54A = 6240; // 43
+const static uint64_t SH_FLD_FREE_USAGE_55A = 6241; // 43
+const static uint64_t SH_FLD_FREE_USAGE_56A = 6242; // 43
+const static uint64_t SH_FLD_FREE_USAGE_57A = 6243; // 43
+const static uint64_t SH_FLD_FREE_USAGE_58A = 6244; // 43
+const static uint64_t SH_FLD_FREE_USAGE_59A = 6245; // 43
+const static uint64_t SH_FLD_FREE_USAGE_5A = 6246; // 24
+const static uint64_t SH_FLD_FREE_USAGE_60A = 6247; // 43
+const static uint64_t SH_FLD_FREE_USAGE_61A = 6248; // 43
+const static uint64_t SH_FLD_FREE_USAGE_62A = 6249; // 43
+const static uint64_t SH_FLD_FREE_USAGE_63A = 6250; // 43
+const static uint64_t SH_FLD_FREE_USAGE_6A = 6251; // 43
+const static uint64_t SH_FLD_FREE_USAGE_7A = 6252; // 43
+const static uint64_t SH_FLD_FREE_USAGE_9A = 6253; // 43
+const static uint64_t SH_FLD_FREQOUT = 6254; // 6
+const static uint64_t SH_FLD_FREQOUT_AVG = 6255; // 6
+const static uint64_t SH_FLD_FREQOUT_AVG_LEN = 6256; // 6
+const static uint64_t SH_FLD_FREQOUT_LEN = 6257; // 6
+const static uint64_t SH_FLD_FREQOUT_MAX = 6258; // 6
+const static uint64_t SH_FLD_FREQOUT_MAX_LEN = 6259; // 6
+const static uint64_t SH_FLD_FREQOUT_MIN = 6260; // 6
+const static uint64_t SH_FLD_FREQOUT_MIN_LEN = 6261; // 6
+const static uint64_t SH_FLD_FREQUENCY_REFERENCE = 6262; // 24
+const static uint64_t SH_FLD_FREQUENCY_REFERENCE_LEN = 6263; // 24
+const static uint64_t SH_FLD_FREQ_CHANGE = 6264; // 6
+const static uint64_t SH_FLD_FREQ_LCL_SAMPLE_EN = 6265; // 12
+const static uint64_t SH_FLD_FREQ_SCALE_A_THRESHOLD = 6266; // 24
+const static uint64_t SH_FLD_FREQ_SCALE_A_THRESHOLD_LEN = 6267; // 24
+const static uint64_t SH_FLD_FREQ_SCALE_B_THRESHOLD = 6268; // 24
+const static uint64_t SH_FLD_FREQ_SCALE_B_THRESHOLD_LEN = 6269; // 24
+const static uint64_t SH_FLD_FSAFE = 6270; // 6
+const static uint64_t SH_FLD_FSAFE_ACTIVE = 6271; // 6
+const static uint64_t SH_FLD_FSAFE_LEN = 6272; // 6
+const static uint64_t SH_FLD_FSI_A_MST_0_ACTUAL_ERROR = 6273; // 1
+const static uint64_t SH_FLD_FSI_A_MST_0_ACTUAL_ERROR_LEN = 6274; // 1
+const static uint64_t SH_FLD_FSI_A_MST_0_PORT_0_ENABLE = 6275; // 1
+const static uint64_t SH_FLD_FSI_A_MST_0_PORT_1_ENABLE = 6276; // 1
+const static uint64_t SH_FLD_FSI_A_MST_0_PORT_2_ENABLE = 6277; // 1
+const static uint64_t SH_FLD_FSI_A_MST_0_PORT_3_ENABLE = 6278; // 1
+const static uint64_t SH_FLD_FSI_A_MST_0_PORT_4_ENABLE = 6279; // 1
+const static uint64_t SH_FLD_FSI_A_MST_0_PORT_5_ENABLE = 6280; // 1
+const static uint64_t SH_FLD_FSI_A_MST_0_PORT_6_ENABLE = 6281; // 1
+const static uint64_t SH_FLD_FSI_A_MST_0_PORT_7_ENABLE = 6282; // 1
+const static uint64_t SH_FLD_FSI_A_MST_1_ACTUAL_ERROR = 6283; // 1
+const static uint64_t SH_FLD_FSI_A_MST_1_ACTUAL_ERROR_LEN = 6284; // 1
+const static uint64_t SH_FLD_FSI_A_MST_1_PORT_0_ENABLE = 6285; // 1
+const static uint64_t SH_FLD_FSI_A_MST_1_PORT_1_ENABLE = 6286; // 1
+const static uint64_t SH_FLD_FSI_A_MST_1_PORT_2_ENABLE = 6287; // 1
+const static uint64_t SH_FLD_FSI_A_MST_1_PORT_3_ENABLE = 6288; // 1
+const static uint64_t SH_FLD_FSI_A_MST_1_PORT_4_ENABLE = 6289; // 1
+const static uint64_t SH_FLD_FSI_B_MST_0_ACTUAL_ERROR = 6290; // 1
+const static uint64_t SH_FLD_FSI_B_MST_0_ACTUAL_ERROR_LEN = 6291; // 1
+const static uint64_t SH_FLD_FSI_B_MST_0_PORT_0_ENABLE = 6292; // 1
+const static uint64_t SH_FLD_FSI_B_MST_0_PORT_1_ENABLE = 6293; // 1
+const static uint64_t SH_FLD_FSI_B_MST_0_PORT_2_ENABLE = 6294; // 1
+const static uint64_t SH_FLD_FSI_B_MST_0_PORT_3_ENABLE = 6295; // 1
+const static uint64_t SH_FLD_FSI_B_MST_0_PORT_4_ENABLE = 6296; // 1
+const static uint64_t SH_FLD_FSI_B_MST_0_PORT_5_ENABLE = 6297; // 1
+const static uint64_t SH_FLD_FSI_B_MST_0_PORT_6_ENABLE = 6298; // 1
+const static uint64_t SH_FLD_FSI_B_MST_0_PORT_7_ENABLE = 6299; // 1
+const static uint64_t SH_FLD_FSI_CC_VSB_CBS_CMD = 6300; // 1
+const static uint64_t SH_FLD_FSI_CC_VSB_CBS_CMD_LEN = 6301; // 1
+const static uint64_t SH_FLD_FSI_CC_VSB_CBS_REQ = 6302; // 1
+const static uint64_t SH_FLD_FSI_SCRATCH_PAD = 6303; // 1
+const static uint64_t SH_FLD_FSI_SCRATCH_PAD_LEN = 6304; // 1
+const static uint64_t SH_FLD_FSMJ_EVENT = 6305; // 2
+const static uint64_t SH_FLD_FSMJ_EVENT_LEN = 6306; // 2
+const static uint64_t SH_FLD_FSMJ_EVENT_SEL = 6307; // 2
+const static uint64_t SH_FLD_FSMJ_EVENT_SEL_LEN = 6308; // 2
+const static uint64_t SH_FLD_FSMJ_FSM = 6309; // 2
+const static uint64_t SH_FLD_FSMJ_FSM_LEN = 6310; // 2
+const static uint64_t SH_FLD_FSMJ_FSM_SEL = 6311; // 2
+const static uint64_t SH_FLD_FSMJ_FSM_SEL_LEN = 6312; // 2
+const static uint64_t SH_FLD_FSM_DATA02 = 6313; // 1
+const static uint64_t SH_FLD_FSM_ERR = 6314; // 5
+const static uint64_t SH_FLD_FSM_ERROR = 6315; // 1
+const static uint64_t SH_FLD_FSM_PARITY_ERROR = 6316; // 3
+const static uint64_t SH_FLD_FSM_PERR = 6317; // 1
+const static uint64_t SH_FLD_FSM_PRESENT_STATE = 6318; // 1
+const static uint64_t SH_FLD_FSM_PRESENT_STATE_LEN = 6319; // 1
+const static uint64_t SH_FLD_FSM_SYNC_ENABLE = 6320; // 1
+const static uint64_t SH_FLD_FSM_TRIGGER = 6321; // 2
+const static uint64_t SH_FLD_FSP_ACCESS_TRUSTED_SPACE = 6322; // 4
+const static uint64_t SH_FLD_FSP_CMD_ENABLE = 6323; // 1
+const static uint64_t SH_FLD_FSP_ECC_ERR_CE = 6324; // 4
+const static uint64_t SH_FLD_FSP_ECC_ERR_UE = 6325; // 4
+const static uint64_t SH_FLD_FSP_ERR_RSP_ENABLE = 6326; // 1
+const static uint64_t SH_FLD_FSP_INBOUND_ACTIVE = 6327; // 1
+const static uint64_t SH_FLD_FSP_INTERRUPT = 6328; // 1
+const static uint64_t SH_FLD_FSP_INTERRUPT_VALUE = 6329; // 1
+const static uint64_t SH_FLD_FSP_INTERRUPT_VALUE_LEN = 6330; // 1
+const static uint64_t SH_FLD_FSP_INT_ENABLE = 6331; // 1
+const static uint64_t SH_FLD_FSP_INV_READ = 6332; // 1
+const static uint64_t SH_FLD_FSP_LINK_ACTIVE = 6333; // 1
+const static uint64_t SH_FLD_FSP_MMIO_ENABLE = 6334; // 1
+const static uint64_t SH_FLD_FSP_MMIO_MASK = 6335; // 1
+const static uint64_t SH_FLD_FSP_MMIO_MASK_LEN = 6336; // 1
+const static uint64_t SH_FLD_FSP_OCC_BUID = 6337; // 1
+const static uint64_t SH_FLD_FSP_OCC_BUID_LEN = 6338; // 1
+const static uint64_t SH_FLD_FSP_OUTBOUND_ACTIVE = 6339; // 1
+const static uint64_t SH_FLD_FSP_PRIORITY = 6340; // 1
+const static uint64_t SH_FLD_FSP_PRIORITY_LEN = 6341; // 1
+const static uint64_t SH_FLD_FSP_RESET = 6342; // 1
+const static uint64_t SH_FLD_FSP_SERVER_NUMBER = 6343; // 1
+const static uint64_t SH_FLD_FSP_SERVER_NUMBER_LEN = 6344; // 1
+const static uint64_t SH_FLD_FSP_SPECIAL_WKUP = 6345; // 30
+const static uint64_t SH_FLD_FSP_TCE_ENABLE = 6346; // 1
+const static uint64_t SH_FLD_FULL = 6347; // 1
+const static uint64_t SH_FLD_FULLMASK = 6348; // 1
+const static uint64_t SH_FLD_FULLMASK_LEN = 6349; // 1
+const static uint64_t SH_FLD_FULL_WRITEBACK_ENABLE = 6350; // 6
+const static uint64_t SH_FLD_FUNC = 6351; // 43
+const static uint64_t SH_FLD_FUNCTION = 6352; // 6
+const static uint64_t SH_FLD_FUNCTION_LEN = 6353; // 6
+const static uint64_t SH_FLD_FUNC_MODE_DONE = 6354; // 4
+const static uint64_t SH_FLD_FWD_PROG_RATE2 = 6355; // 12
+const static uint64_t SH_FLD_FWD_PROG_RATE2_LEN = 6356; // 12
+const static uint64_t SH_FLD_FW_RD_WR = 6357; // 8
+const static uint64_t SH_FLD_FW_RD_WR_LEN = 6358; // 8
+const static uint64_t SH_FLD_FW_WR_RD = 6359; // 8
+const static uint64_t SH_FLD_FW_WR_RD_LEN = 6360; // 8
+const static uint64_t SH_FLD_F_READ = 6361; // 43
+const static uint64_t SH_FLD_F_SKITTER_READ_MASK = 6362; // 43
+const static uint64_t SH_FLD_GAP_LENGTH_ADDER = 6363; // 8
+const static uint64_t SH_FLD_GAP_LENGTH_ADDER_LEN = 6364; // 8
+const static uint64_t SH_FLD_GCR_BUFFER_ENABLED_RO_SIGNAL = 6365; // 4
+const static uint64_t SH_FLD_GCR_HANG_DET_SEL = 6366; // 4
+const static uint64_t SH_FLD_GCR_HANG_DET_SEL_LEN = 6367; // 4
+const static uint64_t SH_FLD_GCR_HANG_ERROR_INJ = 6368; // 4
+const static uint64_t SH_FLD_GCR_HANG_ERROR_MASK = 6369; // 4
+const static uint64_t SH_FLD_GCR_TEST = 6370; // 4
+const static uint64_t SH_FLD_GENERATE_MPIPL_SEQUENCE = 6371; // 4
+const static uint64_t SH_FLD_GLOBAL_EP_RESET_DC = 6372; // 1
+const static uint64_t SH_FLD_GLOBAL_PHY_OFFSET = 6373; // 8
+const static uint64_t SH_FLD_GLOBAL_PHY_OFFSET_LEN = 6374; // 8
+const static uint64_t SH_FLD_GLOBAL_RUN_MODE = 6375; // 2
+const static uint64_t SH_FLD_GO = 6376; // 43
+const static uint64_t SH_FLD_GO2 = 6377; // 43
+const static uint64_t SH_FLD_GOTO_CMD = 6378; // 64
+const static uint64_t SH_FLD_GOTO_CMD_LEN = 6379; // 64
+const static uint64_t SH_FLD_GP = 6380; // 1
+const static uint64_t SH_FLD_GPE0_ERROR = 6381; // 1
+const static uint64_t SH_FLD_GPE1_ERROR = 6382; // 1
+const static uint64_t SH_FLD_GPE2_ERROR = 6383; // 1
+const static uint64_t SH_FLD_GPE3_ERROR = 6384; // 1
+const static uint64_t SH_FLD_GP_TP_GLBCK_VSB_NEST_MESH_SEL_DC = 6385; // 1
+const static uint64_t SH_FLD_GRANTED_PACKET = 6386; // 30
+const static uint64_t SH_FLD_GRANTED_PACKET_LEN = 6387; // 30
+const static uint64_t SH_FLD_GRANTED_SOURCE = 6388; // 30
+const static uint64_t SH_FLD_GRANTED_SOURCE_LEN = 6389; // 30
+const static uint64_t SH_FLD_GROUP = 6390; // 9
+const static uint64_t SH_FLD_GROUPING = 6391; // 8
+const static uint64_t SH_FLD_GROUPING_LEN = 6392; // 8
+const static uint64_t SH_FLD_GROUP_BASE_ADDRESS = 6393; // 8
+const static uint64_t SH_FLD_GROUP_BASE_ADDRESS_LEN = 6394; // 8
+const static uint64_t SH_FLD_GROUP_EPSILON = 6395; // 8
+const static uint64_t SH_FLD_GROUP_EPSILON_LEN = 6396; // 8
+const static uint64_t SH_FLD_GROUP_LEN = 6397; // 9
+const static uint64_t SH_FLD_GROUP_SEL_0_4 = 6398; // 1
+const static uint64_t SH_FLD_GROUP_SEL_0_4_LEN = 6399; // 1
+const static uint64_t SH_FLD_GROUP_SIZE = 6400; // 8
+const static uint64_t SH_FLD_GROUP_SIZE_LEN = 6401; // 8
+const static uint64_t SH_FLD_GRPSEL = 6402; // 2
+const static uint64_t SH_FLD_GRPSEL_LEN = 6403; // 2
+const static uint64_t SH_FLD_GRP_BASE = 6404; // 8
+const static uint64_t SH_FLD_GRP_BASE_LEN = 6405; // 8
+const static uint64_t SH_FLD_GRP_MBR_ID = 6406; // 8
+const static uint64_t SH_FLD_GRP_PDWN = 6407; // 12
+const static uint64_t SH_FLD_GRP_PDWN_LEN = 6408; // 12
+const static uint64_t SH_FLD_GRP_SIZE = 6409; // 8
+const static uint64_t SH_FLD_GRP_SIZE_LEN = 6410; // 8
+const static uint64_t SH_FLD_GX = 6411; // 2
+const static uint64_t SH_FLD_GX_ENABLE_OVERWRITE = 6412; // 1
+const static uint64_t SH_FLD_GX_LEN = 6413; // 2
+const static uint64_t SH_FLD_GZIPCOMP_MAX_INRD = 6414; // 1
+const static uint64_t SH_FLD_GZIPCOMP_MAX_INRD_LEN = 6415; // 1
+const static uint64_t SH_FLD_GZIPDECOMP_MAX_INRD = 6416; // 1
+const static uint64_t SH_FLD_GZIPDECOMP_MAX_INRD_LEN = 6417; // 1
+const static uint64_t SH_FLD_GZIP_COMP_PREFETCH_ENABLE = 6418; // 1
+const static uint64_t SH_FLD_GZIP_DECOMP_PREFETCH_ENABLE = 6419; // 1
+const static uint64_t SH_FLD_GZIP_FC_SELECT = 6420; // 1
+const static uint64_t SH_FLD_GZIP_FC_SELECT_LEN = 6421; // 1
+const static uint64_t SH_FLD_GZIP_LATENCY_CFG = 6422; // 1
+const static uint64_t SH_FLD_H1AP_CFG = 6423; // 6
+const static uint64_t SH_FLD_H1AP_CFG_LEN = 6424; // 6
+const static uint64_t SH_FLD_HALT_INPUT = 6425; // 13
+const static uint64_t SH_FLD_HALT_ON_TRIG = 6426; // 17
+const static uint64_t SH_FLD_HALT_ON_XSTOP = 6427; // 17
+const static uint64_t SH_FLD_HALT_ROTATION = 6428; // 8
+const static uint64_t SH_FLD_HANG_DATA_SCALE = 6429; // 5
+const static uint64_t SH_FLD_HANG_DATA_SCALE_LEN = 6430; // 5
+const static uint64_t SH_FLD_HANG_ON_ACK_DEAD = 6431; // 1
+const static uint64_t SH_FLD_HANG_ON_ADDR_ERROR = 6432; // 1
+const static uint64_t SH_FLD_HANG_PE_SCALE = 6433; // 3
+const static uint64_t SH_FLD_HANG_PE_SCALE_LEN = 6434; // 3
+const static uint64_t SH_FLD_HANG_PIB_RESET = 6435; // 1
+const static uint64_t SH_FLD_HANG_POLL_ENABLE = 6436; // 2
+const static uint64_t SH_FLD_HANG_POLL_PULSE_DIV = 6437; // 24
+const static uint64_t SH_FLD_HANG_POLL_PULSE_DIV_LEN = 6438; // 24
+const static uint64_t SH_FLD_HANG_POLL_SCALE = 6439; // 7
+const static uint64_t SH_FLD_HANG_POLL_SCALE_LEN = 6440; // 7
+const static uint64_t SH_FLD_HANG_RESET = 6441; // 1
+const static uint64_t SH_FLD_HANG_SHM_SCALE = 6442; // 2
+const static uint64_t SH_FLD_HANG_SHM_SCALE_LEN = 6443; // 2
+const static uint64_t SH_FLD_HANG_SM_ON_ARE = 6444; // 2
+const static uint64_t SH_FLD_HANG_SM_ON_LINK_FAIL = 6445; // 2
+const static uint64_t SH_FLD_HARD_CE_COUNT = 6446; // 2
+const static uint64_t SH_FLD_HARD_CE_COUNT_LEN = 6447; // 2
+const static uint64_t SH_FLD_HARD_CE_ETE_ATTN = 6448; // 4
+const static uint64_t SH_FLD_HARD_CHIPID_IN_BLOCK_EN = 6449; // 1
+const static uint64_t SH_FLD_HARD_MCE_COUNT = 6450; // 2
+const static uint64_t SH_FLD_HARD_MCE_COUNT_LEN = 6451; // 2
+const static uint64_t SH_FLD_HARD_NCE_ETE_ATTN = 6452; // 10
+const static uint64_t SH_FLD_HASH_LPID_DIS = 6453; // 1
+const static uint64_t SH_FLD_HASH_PID_DIS = 6454; // 1
+const static uint64_t SH_FLD_HASH_SIZE_MASK = 6455; // 1
+const static uint64_t SH_FLD_HASH_SIZE_MASK_LEN = 6456; // 1
+const static uint64_t SH_FLD_HA_ILLEGAL_CONSUMER_ACCESS = 6457; // 4
+const static uint64_t SH_FLD_HA_ILLEGAL_PRODUCER_ACCESS = 6458; // 4
+const static uint64_t SH_FLD_HDICE = 6459; // 96
+const static uint64_t SH_FLD_HDR_ARR_ECC_CORR_ENA = 6460; // 6
+const static uint64_t SH_FLD_HDR_ARR_ECC_SUE_ENA = 6461; // 6
+const static uint64_t SH_FLD_HI = 6462; // 1
+const static uint64_t SH_FLD_HIGH = 6463; // 1
+const static uint64_t SH_FLD_HIGH_IDLE_COUNT = 6464; // 8
+const static uint64_t SH_FLD_HIGH_IDLE_COUNT_LEN = 6465; // 8
+const static uint64_t SH_FLD_HIGH_IDLE_THRESHOLD = 6466; // 8
+const static uint64_t SH_FLD_HIGH_IDLE_THRESHOLD_LEN = 6467; // 8
+const static uint64_t SH_FLD_HIGH_LEN = 6468; // 1
+const static uint64_t SH_FLD_HILE = 6469; // 24
+const static uint64_t SH_FLD_HIRES_FMAX = 6470; // 6
+const static uint64_t SH_FLD_HIRES_FMAX_LEN = 6471; // 6
+const static uint64_t SH_FLD_HIRES_FMIN = 6472; // 6
+const static uint64_t SH_FLD_HIRES_FMIN_LEN = 6473; // 6
+const static uint64_t SH_FLD_HIRES_FREQOUT = 6474; // 6
+const static uint64_t SH_FLD_HIRES_FREQOUT_AVG = 6475; // 6
+const static uint64_t SH_FLD_HIRES_FREQOUT_AVG_LEN = 6476; // 6
+const static uint64_t SH_FLD_HIRES_FREQOUT_LEN = 6477; // 6
+const static uint64_t SH_FLD_HIRES_FREQOUT_MAX = 6478; // 6
+const static uint64_t SH_FLD_HIRES_FREQOUT_MAX_LEN = 6479; // 6
+const static uint64_t SH_FLD_HIRES_FREQOUT_MIN = 6480; // 6
+const static uint64_t SH_FLD_HIRES_FREQOUT_MIN_LEN = 6481; // 6
+const static uint64_t SH_FLD_HIST = 6482; // 6
+const static uint64_t SH_FLD_HIST_ADDRESS = 6483; // 1
+const static uint64_t SH_FLD_HIST_ADDRESS_LEN = 6484; // 1
+const static uint64_t SH_FLD_HIST_DONE = 6485; // 1
+const static uint64_t SH_FLD_HIST_FREEZE_HISTORY = 6486; // 1
+const static uint64_t SH_FLD_HIST_LEN = 6487; // 6
+const static uint64_t SH_FLD_HIST_MANUAL_MODE_EN = 6488; // 1
+const static uint64_t SH_FLD_HIST_MASK = 6489; // 1
+const static uint64_t SH_FLD_HIST_MASK_LEN = 6490; // 1
+const static uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT = 6491; // 6
+const static uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_LANE = 6492; // 6
+const static uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_LANE_LEN = 6493; // 6
+const static uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_LEN = 6494; // 6
+const static uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_MODE = 6495; // 6
+const static uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_MODE_LEN = 6496; // 6
+const static uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_VALID = 6497; // 6
+const static uint64_t SH_FLD_HIST_MIN_EYE_WIDTH = 6498; // 6
+const static uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_LANE = 6499; // 6
+const static uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_LANE_LEN = 6500; // 6
+const static uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_LEN = 6501; // 6
+const static uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_MODE = 6502; // 6
+const static uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_MODE_LEN = 6503; // 6
+const static uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_VALID = 6504; // 6
+const static uint64_t SH_FLD_HIST_RESERVED = 6505; // 1
+const static uint64_t SH_FLD_HIST_RESERVED_LEN = 6506; // 1
+const static uint64_t SH_FLD_HIST_RESET_HISTORY = 6507; // 1
+const static uint64_t SH_FLD_HIST_START_NOT_STOP = 6508; // 1
+const static uint64_t SH_FLD_HIST_STOP_ON_ERROR_GT = 6509; // 1
+const static uint64_t SH_FLD_HIST_STOP_ON_ERROR_GT_LEN = 6510; // 1
+const static uint64_t SH_FLD_HIST_TRACE_TRAFFIC = 6511; // 1
+const static uint64_t SH_FLD_HMI_ACTIVE = 6512; // 1
+const static uint64_t SH_FLD_HMI_EXIT_ENABLE = 6513; // 96
+const static uint64_t SH_FLD_HMI_REQUEST_C0 = 6514; // 12
+const static uint64_t SH_FLD_HMI_REQUEST_C1 = 6515; // 12
+const static uint64_t SH_FLD_HOLD = 6516; // 2
+const static uint64_t SH_FLD_HOLD_0_51 = 6517; // 1
+const static uint64_t SH_FLD_HOLD_0_51_LEN = 6518; // 1
+const static uint64_t SH_FLD_HOLD_ADDRESS = 6519; // 90
+const static uint64_t SH_FLD_HOLD_ADDRESS_LEN = 6520; // 90
+const static uint64_t SH_FLD_HOLD_DBGTRIG_SEL = 6521; // 43
+const static uint64_t SH_FLD_HOLD_DBGTRIG_SEL_LEN = 6522; // 43
+const static uint64_t SH_FLD_HOLD_LEN = 6523; // 2
+const static uint64_t SH_FLD_HOLD_SAMPLE = 6524; // 43
+const static uint64_t SH_FLD_HOLD_SAMPLE_WITH_TRIGGER = 6525; // 43
+const static uint64_t SH_FLD_HOLE0_LOWER_ADDRESS = 6526; // 8
+const static uint64_t SH_FLD_HOLE0_LOWER_ADDRESS_LEN = 6527; // 8
+const static uint64_t SH_FLD_HOLE0_UPPER_ADDRESS = 6528; // 8
+const static uint64_t SH_FLD_HOLE0_UPPER_ADDRESS_LEN = 6529; // 8
+const static uint64_t SH_FLD_HOLE0_VALID = 6530; // 8
+const static uint64_t SH_FLD_HOLE1_LOWER_ADDRESS = 6531; // 8
+const static uint64_t SH_FLD_HOLE1_LOWER_ADDRESS_LEN = 6532; // 8
+const static uint64_t SH_FLD_HOLE1_UPPER_ADDRESS = 6533; // 8
+const static uint64_t SH_FLD_HOLE1_UPPER_ADDRESS_LEN = 6534; // 8
+const static uint64_t SH_FLD_HOLE1_VALID = 6535; // 8
+const static uint64_t SH_FLD_HRMOR = 6536; // 1
+const static uint64_t SH_FLD_HRMOR_LEN = 6537; // 1
+const static uint64_t SH_FLD_HSSCALERR = 6538; // 6
+const static uint64_t SH_FLD_HSSPLLAERR = 6539; // 6
+const static uint64_t SH_FLD_HSSPLLBERR = 6540; // 6
+const static uint64_t SH_FLD_HSSPLLFASTCAL = 6541; // 6
+const static uint64_t SH_FLD_HSSRECAL = 6542; // 6
+const static uint64_t SH_FLD_HSSRESYNC = 6543; // 6
+const static uint64_t SH_FLD_HTB_EXTEST = 6544; // 43
+const static uint64_t SH_FLD_HTB_INTEST = 6545; // 43
+const static uint64_t SH_FLD_HTMCO_STATUS_ADDR_ERROR = 6546; // 26
+const static uint64_t SH_FLD_HTMCO_STATUS_BUF_WAIT = 6547; // 26
+const static uint64_t SH_FLD_HTMCO_STATUS_COMPLETE = 6548; // 26
+const static uint64_t SH_FLD_HTMCO_STATUS_CRESP_OV = 6549; // 26
+const static uint64_t SH_FLD_HTMCO_STATUS_ENABLE = 6550; // 26
+const static uint64_t SH_FLD_HTMCO_STATUS_FLUSH = 6551; // 26
+const static uint64_t SH_FLD_HTMCO_STATUS_INIT = 6552; // 26
+const static uint64_t SH_FLD_HTMCO_STATUS_PAUSED = 6553; // 26
+const static uint64_t SH_FLD_HTMCO_STATUS_PREREQ = 6554; // 26
+const static uint64_t SH_FLD_HTMCO_STATUS_PURGE_DONE = 6555; // 24
+const static uint64_t SH_FLD_HTMCO_STATUS_PURGE_IN_PROG = 6556; // 24
+const static uint64_t SH_FLD_HTMCO_STATUS_READY = 6557; // 26
+const static uint64_t SH_FLD_HTMCO_STATUS_REPAIR = 6558; // 26
+const static uint64_t SH_FLD_HTMCO_STATUS_SPARE = 6559; // 2
+const static uint64_t SH_FLD_HTMCO_STATUS_SPARE_LEN = 6560; // 2
+const static uint64_t SH_FLD_HTMCO_STATUS_STAMP = 6561; // 26
+const static uint64_t SH_FLD_HTMCO_STATUS_TRACING = 6562; // 26
+const static uint64_t SH_FLD_HTMSC = 6563; // 24
+const static uint64_t SH_FLD_HTMSC_ALLOC = 6564; // 26
+const static uint64_t SH_FLD_HTMSC_BASE = 6565; // 26
+const static uint64_t SH_FLD_HTMSC_BASE_LEN = 6566; // 26
+const static uint64_t SH_FLD_HTMSC_CAPTURE = 6567; // 26
+const static uint64_t SH_FLD_HTMSC_CAPTURE_LEN = 6568; // 26
+const static uint64_t SH_FLD_HTMSC_CHIP0_STOP = 6569; // 24
+const static uint64_t SH_FLD_HTMSC_CHIP1_STOP = 6570; // 24
+const static uint64_t SH_FLD_HTMSC_CONTENT_SEL = 6571; // 26
+const static uint64_t SH_FLD_HTMSC_CONTENT_SEL_LEN = 6572; // 26
+const static uint64_t SH_FLD_HTMSC_COUNT = 6573; // 24
+const static uint64_t SH_FLD_HTMSC_COUNT_LEN = 6574; // 24
+const static uint64_t SH_FLD_HTMSC_CRESPFILT_INVERT = 6575; // 2
+const static uint64_t SH_FLD_HTMSC_CRESP_MASK = 6576; // 2
+const static uint64_t SH_FLD_HTMSC_CRESP_MASK_LEN = 6577; // 2
+const static uint64_t SH_FLD_HTMSC_CRESP_PAT = 6578; // 2
+const static uint64_t SH_FLD_HTMSC_CRESP_PAT_LEN = 6579; // 2
+const static uint64_t SH_FLD_HTMSC_DBG0_STOP = 6580; // 26
+const static uint64_t SH_FLD_HTMSC_DBG1_STOP = 6581; // 26
+const static uint64_t SH_FLD_HTMSC_DD1EQUIV = 6582; // 24
+const static uint64_t SH_FLD_HTMSC_DIS_DRP_PRIORITY_INCR = 6583; // 2
+const static uint64_t SH_FLD_HTMSC_DIS_FORCE_GROUP_SCOPE = 6584; // 2
+const static uint64_t SH_FLD_HTMSC_DIS_GROUP = 6585; // 24
+const static uint64_t SH_FLD_HTMSC_DIS_OPER_HANG = 6586; // 2
+const static uint64_t SH_FLD_HTMSC_DIS_RETRY_BACKOFF = 6587; // 2
+const static uint64_t SH_FLD_HTMSC_DIS_STALL = 6588; // 24
+const static uint64_t SH_FLD_HTMSC_DIS_TSTAMP = 6589; // 26
+const static uint64_t SH_FLD_HTMSC_ENABLE = 6590; // 26
+const static uint64_t SH_FLD_HTMSC_ENABLE_SPLIT_CORE = 6591; // 24
+const static uint64_t SH_FLD_HTMSC_ERROR = 6592; // 24
+const static uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL0 = 6593; // 2
+const static uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL0_LEN = 6594; // 2
+const static uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL1 = 6595; // 2
+const static uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL1_LEN = 6596; // 2
+const static uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL2 = 6597; // 2
+const static uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL2_LEN = 6598; // 2
+const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL0 = 6599; // 2
+const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL0_LEN = 6600; // 2
+const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL1 = 6601; // 2
+const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL1_LEN = 6602; // 2
+const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL2 = 6603; // 2
+const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL2_LEN = 6604; // 2
+const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL3 = 6605; // 2
+const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL3_LEN = 6606; // 2
+const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL4 = 6607; // 2
+const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL4_LEN = 6608; // 2
+const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL5 = 6609; // 2
+const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL5_LEN = 6610; // 2
+const static uint64_t SH_FLD_HTMSC_FSM = 6611; // 24
+const static uint64_t SH_FLD_HTMSC_FSM_LEN = 6612; // 24
+const static uint64_t SH_FLD_HTMSC_INVERT = 6613; // 2
+const static uint64_t SH_FLD_HTMSC_LEN = 6614; // 24
+const static uint64_t SH_FLD_HTMSC_MARK = 6615; // 26
+const static uint64_t SH_FLD_HTMSC_MARKERS_ONLY = 6616; // 26
+const static uint64_t SH_FLD_HTMSC_MARK_LEN = 6617; // 26
+const static uint64_t SH_FLD_HTMSC_MARK_TYPE = 6618; // 26
+const static uint64_t SH_FLD_HTMSC_MARK_TYPE_LEN = 6619; // 26
+const static uint64_t SH_FLD_HTMSC_MARK_VALID = 6620; // 26
+const static uint64_t SH_FLD_HTMSC_MASK = 6621; // 4
+const static uint64_t SH_FLD_HTMSC_MASK_LEN = 6622; // 4
+const static uint64_t SH_FLD_HTMSC_MTSPR_MARK = 6623; // 24
+const static uint64_t SH_FLD_HTMSC_MTSPR_TRIG = 6624; // 24
+const static uint64_t SH_FLD_HTMSC_OPER_HANG_DIV_RATIO = 6625; // 2
+const static uint64_t SH_FLD_HTMSC_OPER_HANG_DIV_RATIO_LEN = 6626; // 2
+const static uint64_t SH_FLD_HTMSC_OTHER_DBG0_STOP = 6627; // 2
+const static uint64_t SH_FLD_HTMSC_PAT = 6628; // 4
+const static uint64_t SH_FLD_HTMSC_PAT_LEN = 6629; // 4
+const static uint64_t SH_FLD_HTMSC_PAUSE = 6630; // 26
+const static uint64_t SH_FLD_HTMSC_PDBAR_ERROR = 6631; // 24
+const static uint64_t SH_FLD_HTMSC_PRIORITY = 6632; // 26
+const static uint64_t SH_FLD_HTMSC_RESERVED = 6633; // 24
+const static uint64_t SH_FLD_HTMSC_RESERVED_LEN = 6634; // 24
+const static uint64_t SH_FLD_HTMSC_RESET = 6635; // 26
+const static uint64_t SH_FLD_HTMSC_RTY_DRP_COUNT = 6636; // 2
+const static uint64_t SH_FLD_HTMSC_RTY_DRP_COUNT_LEN = 6637; // 2
+const static uint64_t SH_FLD_HTMSC_RUN_STOP = 6638; // 26
+const static uint64_t SH_FLD_HTMSC_SCOPE = 6639; // 50
+const static uint64_t SH_FLD_HTMSC_SCOPE_LEN = 6640; // 50
+const static uint64_t SH_FLD_HTMSC_SINGLE_TSTAMP = 6641; // 26
+const static uint64_t SH_FLD_HTMSC_SIZE = 6642; // 26
+const static uint64_t SH_FLD_HTMSC_SIZE_LEN = 6643; // 26
+const static uint64_t SH_FLD_HTMSC_SIZE_SMALL = 6644; // 26
+const static uint64_t SH_FLD_HTMSC_SPARE = 6645; // 24
+const static uint64_t SH_FLD_HTMSC_SPARE0 = 6646; // 24
+const static uint64_t SH_FLD_HTMSC_SPARE1012 = 6647; // 2
+const static uint64_t SH_FLD_HTMSC_SPARE1012_LEN = 6648; // 2
+const static uint64_t SH_FLD_HTMSC_SPARE1112 = 6649; // 24
+const static uint64_t SH_FLD_HTMSC_SPARE1112_LEN = 6650; // 24
+const static uint64_t SH_FLD_HTMSC_SPARE1415 = 6651; // 26
+const static uint64_t SH_FLD_HTMSC_SPARE1415_LEN = 6652; // 26
+const static uint64_t SH_FLD_HTMSC_SPARE16 = 6653; // 2
+const static uint64_t SH_FLD_HTMSC_SPARE23 = 6654; // 2
+const static uint64_t SH_FLD_HTMSC_SPARE2TO4 = 6655; // 24
+const static uint64_t SH_FLD_HTMSC_SPARE2TO4_LEN = 6656; // 24
+const static uint64_t SH_FLD_HTMSC_SPARE3 = 6657; // 2
+const static uint64_t SH_FLD_HTMSC_SPARE4043 = 6658; // 2
+const static uint64_t SH_FLD_HTMSC_SPARE4043_LEN = 6659; // 2
+const static uint64_t SH_FLD_HTMSC_SPARE67 = 6660; // 2
+const static uint64_t SH_FLD_HTMSC_SPARE67_LEN = 6661; // 2
+const static uint64_t SH_FLD_HTMSC_SPARES = 6662; // 24
+const static uint64_t SH_FLD_HTMSC_SPARES_LEN = 6663; // 24
+const static uint64_t SH_FLD_HTMSC_SPARE_1TO2 = 6664; // 24
+const static uint64_t SH_FLD_HTMSC_SPARE_1TO2_LEN = 6665; // 24
+const static uint64_t SH_FLD_HTMSC_SPARE_LEN = 6666; // 24
+const static uint64_t SH_FLD_HTMSC_START = 6667; // 26
+const static uint64_t SH_FLD_HTMSC_STOP = 6668; // 26
+const static uint64_t SH_FLD_HTMSC_STOP_ALT = 6669; // 26
+const static uint64_t SH_FLD_HTMSC_SYNC_STAMP_FORCE = 6670; // 2
+const static uint64_t SH_FLD_HTMSC_SYNC_STAMP_FORCE_LEN = 6671; // 2
+const static uint64_t SH_FLD_HTMSC_TRACE_ACTIVE = 6672; // 24
+const static uint64_t SH_FLD_HTMSC_TRIG = 6673; // 26
+const static uint64_t SH_FLD_HTMSC_TRIG_LEN = 6674; // 26
+const static uint64_t SH_FLD_HTMSC_TSIZEFILT_MASK = 6675; // 2
+const static uint64_t SH_FLD_HTMSC_TSIZEFILT_MASK_LEN = 6676; // 2
+const static uint64_t SH_FLD_HTMSC_TSIZEFILT_PAT = 6677; // 2
+const static uint64_t SH_FLD_HTMSC_TSIZEFILT_PAT_LEN = 6678; // 2
+const static uint64_t SH_FLD_HTMSC_VGTARGET = 6679; // 26
+const static uint64_t SH_FLD_HTMSC_VGTARGET_LEN = 6680; // 26
+const static uint64_t SH_FLD_HTMSC_WRAP = 6681; // 26
+const static uint64_t SH_FLD_HTMSC_WRITETOIO = 6682; // 2
+const static uint64_t SH_FLD_HTMSC_XSTOP_STOP = 6683; // 26
+const static uint64_t SH_FLD_HTM_CMD_OVERRUN = 6684; // 1
+const static uint64_t SH_FLD_HTM_IMA_TIMEOUT = 6685; // 12
+const static uint64_t SH_FLD_HTM_MARKER_SLAVE_ADRS = 6686; // 1
+const static uint64_t SH_FLD_HTM_MARKER_SLAVE_ADRS_LEN = 6687; // 1
+const static uint64_t SH_FLD_HTM_QUEUE_LIMIT = 6688; // 12
+const static uint64_t SH_FLD_HTM_QUEUE_LIMIT_LEN = 6689; // 12
+const static uint64_t SH_FLD_HTM_SRC_SEL = 6690; // 1
+const static uint64_t SH_FLD_HTM_SRC_SEL_LEN = 6691; // 1
+const static uint64_t SH_FLD_HTM_STOP = 6692; // 1
+const static uint64_t SH_FLD_HTM_TRACE_MODE = 6693; // 1
+const static uint64_t SH_FLD_HWCTRL = 6694; // 2
+const static uint64_t SH_FLD_HWCTRL_CLOCK_DIVIDER = 6695; // 1
+const static uint64_t SH_FLD_HWCTRL_CLOCK_DIVIDER_LEN = 6696; // 1
+const static uint64_t SH_FLD_HWCTRL_CPHA = 6697; // 1
+const static uint64_t SH_FLD_HWCTRL_CPOL = 6698; // 1
+const static uint64_t SH_FLD_HWCTRL_DEVICE = 6699; // 1
+const static uint64_t SH_FLD_HWCTRL_FRAME_SIZE = 6700; // 1
+const static uint64_t SH_FLD_HWCTRL_FRAME_SIZE_LEN = 6701; // 1
+const static uint64_t SH_FLD_HWCTRL_FSM_ENABLE = 6702; // 1
+const static uint64_t SH_FLD_HWCTRL_FSM_ERR = 6703; // 1
+const static uint64_t SH_FLD_HWCTRL_INTER_FRAME_DELAY = 6704; // 1
+const static uint64_t SH_FLD_HWCTRL_INTER_FRAME_DELAY_LEN = 6705; // 1
+const static uint64_t SH_FLD_HWCTRL_INVALID_NUMBER_OF_FRAMES = 6706; // 1
+const static uint64_t SH_FLD_HWCTRL_IN_COUNT = 6707; // 1
+const static uint64_t SH_FLD_HWCTRL_IN_COUNT_LEN = 6708; // 1
+const static uint64_t SH_FLD_HWCTRL_IN_DELAY = 6709; // 1
+const static uint64_t SH_FLD_HWCTRL_IN_DELAY_LEN = 6710; // 1
+const static uint64_t SH_FLD_HWCTRL_LEN = 6711; // 2
+const static uint64_t SH_FLD_HWCTRL_NR_OF_FRAMES = 6712; // 1
+const static uint64_t SH_FLD_HWCTRL_NR_OF_FRAMES_LEN = 6713; // 1
+const static uint64_t SH_FLD_HWCTRL_ONGOING = 6714; // 1
+const static uint64_t SH_FLD_HWCTRL_OUT_COUNT = 6715; // 1
+const static uint64_t SH_FLD_HWCTRL_OUT_COUNT_LEN = 6716; // 1
+const static uint64_t SH_FLD_HWCTRL_RDATA0 = 6717; // 1
+const static uint64_t SH_FLD_HWCTRL_RDATA0_LEN = 6718; // 1
+const static uint64_t SH_FLD_HWCTRL_RDATA1 = 6719; // 1
+const static uint64_t SH_FLD_HWCTRL_RDATA1_LEN = 6720; // 1
+const static uint64_t SH_FLD_HWCTRL_RDATA2 = 6721; // 1
+const static uint64_t SH_FLD_HWCTRL_RDATA2_LEN = 6722; // 1
+const static uint64_t SH_FLD_HWCTRL_RDATA3 = 6723; // 1
+const static uint64_t SH_FLD_HWCTRL_RDATA3_LEN = 6724; // 1
+const static uint64_t SH_FLD_HWCTRL_START_SAMPLING = 6725; // 1
+const static uint64_t SH_FLD_HWCTRL_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN =
+    6726; // 1
+const static uint64_t SH_FLD_HWCTRL_WRITE_WHILE_FSM_BUSY_ERR = 6727; // 1
+const static uint64_t SH_FLD_HWD = 6728; // 1
+const static uint64_t SH_FLD_HWD_0 = 6729; // 1
+const static uint64_t SH_FLD_HWD_0_LEN = 6730; // 1
+const static uint64_t SH_FLD_HWD_10 = 6731; // 1
+const static uint64_t SH_FLD_HWD_10_LEN = 6732; // 1
+const static uint64_t SH_FLD_HWD_11 = 6733; // 1
+const static uint64_t SH_FLD_HWD_11_LEN = 6734; // 1
+const static uint64_t SH_FLD_HWD_12 = 6735; // 1
+const static uint64_t SH_FLD_HWD_12_LEN = 6736; // 1
+const static uint64_t SH_FLD_HWD_13 = 6737; // 1
+const static uint64_t SH_FLD_HWD_13_LEN = 6738; // 1
+const static uint64_t SH_FLD_HWD_14 = 6739; // 1
+const static uint64_t SH_FLD_HWD_14_LEN = 6740; // 1
+const static uint64_t SH_FLD_HWD_15 = 6741; // 1
+const static uint64_t SH_FLD_HWD_15_LEN = 6742; // 1
+const static uint64_t SH_FLD_HWD_2 = 6743; // 1
+const static uint64_t SH_FLD_HWD_2_LEN = 6744; // 1
+const static uint64_t SH_FLD_HWD_3 = 6745; // 1
+const static uint64_t SH_FLD_HWD_3_LEN = 6746; // 1
+const static uint64_t SH_FLD_HWD_4 = 6747; // 1
+const static uint64_t SH_FLD_HWD_4_LEN = 6748; // 1
+const static uint64_t SH_FLD_HWD_5 = 6749; // 1
+const static uint64_t SH_FLD_HWD_5_LEN = 6750; // 1
+const static uint64_t SH_FLD_HWD_6 = 6751; // 1
+const static uint64_t SH_FLD_HWD_6_LEN = 6752; // 1
+const static uint64_t SH_FLD_HWD_7 = 6753; // 1
+const static uint64_t SH_FLD_HWD_7_LEN = 6754; // 1
+const static uint64_t SH_FLD_HWD_8 = 6755; // 1
+const static uint64_t SH_FLD_HWD_8_LEN = 6756; // 1
+const static uint64_t SH_FLD_HWD_9 = 6757; // 1
+const static uint64_t SH_FLD_HWD_9_LEN = 6758; // 1
+const static uint64_t SH_FLD_HWD_LEN = 6759; // 1
+const static uint64_t SH_FLD_HWD_PRIORITY = 6760; // 1
+const static uint64_t SH_FLD_HWD_PRIORITY_LEN = 6761; // 1
+const static uint64_t SH_FLD_HWD_RSD = 6762; // 1
+const static uint64_t SH_FLD_HWD_RSD_LEN = 6763; // 1
+const static uint64_t SH_FLD_HW_CONTROL_ERROR = 6764; // 12
+const static uint64_t SH_FLD_HW_DIR_INTIATED_LINE_DELETE_OCCURRED = 6765; // 12
+const static uint64_t SH_FLD_HW_ERRORS = 6766; // 9
+const static uint64_t SH_FLD_HW_ERRORS_MASK = 6767; // 9
+const static uint64_t SH_FLD_HYPERVISOR = 6768; // 2
+const static uint64_t SH_FLD_HYP_RECOURCE_ERR = 6769; // 96
+const static uint64_t SH_FLD_HYP_SPECIAL_WKUP = 6770; // 30
+const static uint64_t SH_FLD_HYP_VIRT_EXIT_ENABLE = 6771; // 96
+const static uint64_t SH_FLD_I2CM_ECC_ERRORS = 6772; // 1
+const static uint64_t SH_FLD_I2CM_ECC_ERRORS_LEN = 6773; // 1
+const static uint64_t SH_FLD_I2CM_I2C_ERRORS = 6774; // 1
+const static uint64_t SH_FLD_I2CM_I2C_ERRORS_LEN = 6775; // 1
+const static uint64_t SH_FLD_I2CM_PIB_ERRORS = 6776; // 1
+const static uint64_t SH_FLD_I2CM_PIB_ERRORS_LEN = 6777; // 1
+const static uint64_t SH_FLD_I2C_BUS_HELD_MODE_ENABLE = 6778; // 1
+const static uint64_t SH_FLD_I2C_EXTENDER = 6779; // 1
+const static uint64_t SH_FLD_I2C_SPEED_MUX = 6780; // 1
+const static uint64_t SH_FLD_I2C_SPEED_MUX_LEN = 6781; // 1
+const static uint64_t SH_FLD_I2C_TIMEOUT = 6782; // 1
+const static uint64_t SH_FLD_I2C_TIMEOUT_LEN = 6783; // 1
+const static uint64_t SH_FLD_IBWR_MASK = 6784; // 3
+const static uint64_t SH_FLD_IBWR_MASK_LEN = 6785; // 3
+const static uint64_t SH_FLD_ICACHE_ERR = 6786; // 18
+const static uint64_t SH_FLD_ICACHE_TAG_ADDR = 6787; // 18
+const static uint64_t SH_FLD_ICACHE_TAG_ADDR_LEN = 6788; // 18
+const static uint64_t SH_FLD_ICACHE_VALID = 6789; // 18
+const static uint64_t SH_FLD_ICACHE_VALID_LEN = 6790; // 18
+const static uint64_t SH_FLD_ICE_COUNT = 6791; // 2
+const static uint64_t SH_FLD_ICE_COUNT_LEN = 6792; // 2
+const static uint64_t SH_FLD_ICE_ETE_ATTN = 6793; // 10
+const static uint64_t SH_FLD_ICS_INVALID_STATE = 6794; // 1
+const static uint64_t SH_FLD_ICU_RNW = 6795; // 1
+const static uint64_t SH_FLD_ICU_TIMEOUT_ERROR = 6796; // 1
+const static uint64_t SH_FLD_ID = 6797; // 131
+const static uint64_t SH_FLD_IDIAL = 6798; // 165
+const static uint64_t SH_FLD_IDIAL_AMO_ADDR = 6799; // 3
+const static uint64_t SH_FLD_IDIAL_BBRD = 6800; // 3
+const static uint64_t SH_FLD_IDIAL_BBRD_LEN = 6801; // 3
+const static uint64_t SH_FLD_IDIAL_BR_CE = 6802; // 3
+const static uint64_t SH_FLD_IDIAL_BR_CE_LEN = 6803; // 3
+const static uint64_t SH_FLD_IDIAL_BR_SUE = 6804; // 3
+const static uint64_t SH_FLD_IDIAL_BR_SUE_LEN = 6805; // 3
+const static uint64_t SH_FLD_IDIAL_BR_UE = 6806; // 3
+const static uint64_t SH_FLD_IDIAL_BR_UE_LEN = 6807; // 3
+const static uint64_t SH_FLD_IDIAL_CE_COUNT_OVER_THRESH = 6808; // 3
+const static uint64_t SH_FLD_IDIAL_CONFIG1 = 6809; // 3
+const static uint64_t SH_FLD_IDIAL_DEBUG0_CONFIG = 6810; // 3
+const static uint64_t SH_FLD_IDIAL_DEBUG1_CONFIG = 6811; // 3
+const static uint64_t SH_FLD_IDIAL_ECC_CONFIG = 6812; // 3
+const static uint64_t SH_FLD_IDIAL_ERRINJ = 6813; // 3
+const static uint64_t SH_FLD_IDIAL_IBRD = 6814; // 3
+const static uint64_t SH_FLD_IDIAL_IBRD_LEN = 6815; // 3
+const static uint64_t SH_FLD_IDIAL_IBUF_STATE = 6816; // 3
+const static uint64_t SH_FLD_IDIAL_IBUF_WRITE = 6817; // 3
+const static uint64_t SH_FLD_IDIAL_IR_CE = 6818; // 3
+const static uint64_t SH_FLD_IDIAL_IR_CE_LEN = 6819; // 3
+const static uint64_t SH_FLD_IDIAL_IR_SUE = 6820; // 3
+const static uint64_t SH_FLD_IDIAL_IR_SUE_LEN = 6821; // 3
+const static uint64_t SH_FLD_IDIAL_IR_UE = 6822; // 3
+const static uint64_t SH_FLD_IDIAL_IR_UE_LEN = 6823; // 3
+const static uint64_t SH_FLD_IDIAL_ISSYNC = 6824; // 1
+const static uint64_t SH_FLD_IDIAL_ISSYNC_LEN = 6825; // 1
+const static uint64_t SH_FLD_IDIAL_LEN = 6826; // 165
+const static uint64_t SH_FLD_IDIAL_MISC_STATE = 6827; // 3
+const static uint64_t SH_FLD_IDIAL_MRG_STATE = 6828; // 3
+const static uint64_t SH_FLD_IDIAL_OBRD = 6829; // 3
+const static uint64_t SH_FLD_IDIAL_OBRD_LEN = 6830; // 3
+const static uint64_t SH_FLD_IDIAL_OBUF_STATE = 6831; // 3
+const static uint64_t SH_FLD_IDIAL_OR_CE = 6832; // 3
+const static uint64_t SH_FLD_IDIAL_OR_CE_LEN = 6833; // 3
+const static uint64_t SH_FLD_IDIAL_OR_SUE = 6834; // 3
+const static uint64_t SH_FLD_IDIAL_OR_SUE_LEN = 6835; // 3
+const static uint64_t SH_FLD_IDIAL_OR_UE = 6836; // 3
+const static uint64_t SH_FLD_IDIAL_OR_UE_LEN = 6837; // 3
+const static uint64_t SH_FLD_IDIAL_PBRX_RTAG = 6838; // 6
+const static uint64_t SH_FLD_IDIAL_PBTX_AMO = 6839; // 3
+const static uint64_t SH_FLD_IDIAL_PBTX_AMO_LEN = 6840; // 3
+const static uint64_t SH_FLD_IDIAL_PBTX_STATE = 6841; // 3
+const static uint64_t SH_FLD_IDIAL_PR_CE = 6842; // 3
+const static uint64_t SH_FLD_IDIAL_PR_CE_LEN = 6843; // 3
+const static uint64_t SH_FLD_IDIAL_PR_SUE = 6844; // 3
+const static uint64_t SH_FLD_IDIAL_PR_SUE_LEN = 6845; // 3
+const static uint64_t SH_FLD_IDIAL_PR_UE = 6846; // 3
+const static uint64_t SH_FLD_IDIAL_PR_UE_LEN = 6847; // 3
+const static uint64_t SH_FLD_IDIAL_PT_CE = 6848; // 3
+const static uint64_t SH_FLD_IDIAL_PT_CE_LEN = 6849; // 3
+const static uint64_t SH_FLD_IDIAL_PT_SUE = 6850; // 3
+const static uint64_t SH_FLD_IDIAL_PT_SUE_LEN = 6851; // 3
+const static uint64_t SH_FLD_IDIAL_PT_UE = 6852; // 3
+const static uint64_t SH_FLD_IDIAL_PT_UE_LEN = 6853; // 3
+const static uint64_t SH_FLD_IDIAL_RESERVED = 6854; // 3
+const static uint64_t SH_FLD_IDIAL_RQIN_STATE = 6855; // 3
+const static uint64_t SH_FLD_IDLE = 6856; // 2
+const static uint64_t SH_FLD_IDLES = 6857; // 64
+const static uint64_t SH_FLD_IDLES_LEN = 6858; // 64
+const static uint64_t SH_FLD_IDLE_PAT_ACTN = 6859; // 2
+const static uint64_t SH_FLD_IDLE_PAT_ADDRESS_0_13 = 6860; // 2
+const static uint64_t SH_FLD_IDLE_PAT_ADDRESS_0_13_LEN = 6861; // 2
+const static uint64_t SH_FLD_IDLE_PAT_ADDRESS_14 = 6862; // 2
+const static uint64_t SH_FLD_IDLE_PAT_ADDRESS_15 = 6863; // 2
+const static uint64_t SH_FLD_IDLE_PAT_ADDRESS_16 = 6864; // 2
+const static uint64_t SH_FLD_IDLE_PAT_ADDRESS_17 = 6865; // 2
+const static uint64_t SH_FLD_IDLE_PAT_BANK_0_1 = 6866; // 2
+const static uint64_t SH_FLD_IDLE_PAT_BANK_0_1_LEN = 6867; // 2
+const static uint64_t SH_FLD_IDLE_PAT_BANK_2 = 6868; // 2
+const static uint64_t SH_FLD_IDLE_PAT_BANK_GROUP_0 = 6869; // 2
+const static uint64_t SH_FLD_IDLE_PAT_BANK_GROUP_1 = 6870; // 2
+const static uint64_t SH_FLD_ID_LEN = 6871; // 129
+const static uint64_t SH_FLD_IGNORE_PECE = 6872; // 12
+const static uint64_t SH_FLD_ILLEGAL_CACHE_OP = 6873; // 1
+const static uint64_t SH_FLD_ILLEGAL_CACHE_OP_MASK = 6874; // 1
+const static uint64_t SH_FLD_ILLEGAL_LPC_BAR_ACCESS = 6875; // 4
+const static uint64_t SH_FLD_ILL_CRESP = 6876; // 1
+const static uint64_t SH_FLD_IMA_ACK_DEAD = 6877; // 12
+const static uint64_t SH_FLD_IMA_CRESP_ADDR_ERR = 6878; // 24
+const static uint64_t SH_FLD_IMA_FOREIGN0_ACK_DEAD = 6879; // 12
+const static uint64_t SH_FLD_IMA_FOREIGN1_ACK_DEAD = 6880; // 12
+const static uint64_t SH_FLD_IN = 6881; // 130
+const static uint64_t SH_FLD_IN0 = 6882; // 43
+const static uint64_t SH_FLD_IN1 = 6883; // 43
+const static uint64_t SH_FLD_IN10 = 6884; // 43
+const static uint64_t SH_FLD_IN11 = 6885; // 43
+const static uint64_t SH_FLD_IN2 = 6886; // 43
+const static uint64_t SH_FLD_IN3 = 6887; // 43
+const static uint64_t SH_FLD_IN4 = 6888; // 43
+const static uint64_t SH_FLD_IN5 = 6889; // 43
+const static uint64_t SH_FLD_IN6 = 6890; // 43
+const static uint64_t SH_FLD_IN7 = 6891; // 43
+const static uint64_t SH_FLD_IN8 = 6892; // 43
+const static uint64_t SH_FLD_IN9 = 6893; // 43
+const static uint64_t SH_FLD_INBAND_BAR_HIT_WITH_INCORRECT_TTYPE = 6894; // 4
+const static uint64_t SH_FLD_INBD_ARRAY_ECC_CE = 6895; // 2
+const static uint64_t SH_FLD_INBD_ARRAY_ECC_UE = 6896; // 2
+const static uint64_t SH_FLD_INCLUDE_TRAFFIC = 6897; // 1
+const static uint64_t SH_FLD_INCOMING_PB_PARITY_ERR = 6898; // 2
+const static uint64_t SH_FLD_INDEX = 6899; // 1
+const static uint64_t SH_FLD_INDEX_LEN = 6900; // 1
+const static uint64_t SH_FLD_INDIRECT_BRIDGE_0_SOURCE = 6901; // 1
+const static uint64_t SH_FLD_INDIRECT_BRIDGE_1_SOURCE = 6902; // 1
+const static uint64_t SH_FLD_INDIRECT_BRIDGE_2_SOURCE = 6903; // 1
+const static uint64_t SH_FLD_INDIRECT_BRIDGE_3_SOURCE = 6904; // 1
+const static uint64_t SH_FLD_INDIRECT_MODE = 6905; // 2
+const static uint64_t SH_FLD_INEX = 6906; // 43
+const static uint64_t SH_FLD_INFINITE_MODE = 6907; // 43
+const static uint64_t SH_FLD_INFO = 6908; // 43
+const static uint64_t SH_FLD_INFORMATION = 6909; // 8
+const static uint64_t SH_FLD_INFORMATION_LEN = 6910; // 8
+const static uint64_t SH_FLD_INFO_CAPTURED = 6911; // 4
+const static uint64_t SH_FLD_INIT = 6912; // 1
+const static uint64_t SH_FLD_INITIAL_COARSE_WR = 6913; // 8
+const static uint64_t SH_FLD_INITIAL_PAT_WRITE = 6914; // 8
+const static uint64_t SH_FLD_INIT_DONE_DL_MASK = 6915; // 2
+const static uint64_t SH_FLD_INIT_TMR_CFG = 6916; // 72
+const static uint64_t SH_FLD_INIT_TMR_CFG_LEN = 6917; // 72
+const static uint64_t SH_FLD_INJ = 6918; // 1
+const static uint64_t SH_FLD_INJECT_1HOT_SM_ERROR = 6919; // 8
+const static uint64_t SH_FLD_INJECT_CAL0_PAR_ERROR = 6920; // 8
+const static uint64_t SH_FLD_INJECT_ENABLE = 6921; // 1
+const static uint64_t SH_FLD_INJECT_ERR = 6922; // 12
+const static uint64_t SH_FLD_INJECT_FIR_ERR0 = 6923; // 8
+const static uint64_t SH_FLD_INJECT_FIR_ERR1 = 6924; // 8
+const static uint64_t SH_FLD_INJECT_FIR_ERR2 = 6925; // 8
+const static uint64_t SH_FLD_INJECT_FIR_ERR3 = 6926; // 8
+const static uint64_t SH_FLD_INJECT_FIR_ERR4 = 6927; // 8
+const static uint64_t SH_FLD_INJECT_MODE = 6928; // 2
+const static uint64_t SH_FLD_INJECT_MODE_LEN = 6929; // 2
+const static uint64_t SH_FLD_INJECT_TYPE = 6930; // 2
+const static uint64_t SH_FLD_INJECT_TYPE_LEN = 6931; // 2
+const static uint64_t SH_FLD_INJ_LEN = 6932; // 1
+const static uint64_t SH_FLD_INOP = 6933; // 43
+const static uint64_t SH_FLD_INOP_FORCE_SG = 6934; // 43
+const static uint64_t SH_FLD_INOP_LEN = 6935; // 43
+const static uint64_t SH_FLD_INOP_WAIT = 6936; // 43
+const static uint64_t SH_FLD_INOP_WAIT_LEN = 6937; // 43
+const static uint64_t SH_FLD_INPROG_WR_ERR = 6938; // 1
+const static uint64_t SH_FLD_INRD_DONE_ERR = 6939; // 1
+const static uint64_t SH_FLD_INSTANT_CACHE_VDM_DATA = 6940; // 12
+const static uint64_t SH_FLD_INSTANT_CACHE_VDM_DATA_LEN = 6941; // 12
+const static uint64_t SH_FLD_INSTANT_CORE0_VDM_DATA = 6942; // 12
+const static uint64_t SH_FLD_INSTANT_CORE0_VDM_DATA_LEN = 6943; // 12
+const static uint64_t SH_FLD_INSTANT_CORE1_VDM_DATA = 6944; // 12
+const static uint64_t SH_FLD_INSTANT_CORE1_VDM_DATA_LEN = 6945; // 12
+const static uint64_t SH_FLD_INSTANT_CORE2_VDM_DATA = 6946; // 12
+const static uint64_t SH_FLD_INSTANT_CORE2_VDM_DATA_LEN = 6947; // 12
+const static uint64_t SH_FLD_INSTANT_CORE3_VDM_DATA = 6948; // 12
+const static uint64_t SH_FLD_INSTANT_CORE3_VDM_DATA_LEN = 6949; // 12
+const static uint64_t SH_FLD_INSTANT_VDM_CONTROL_SUMMARY = 6950; // 12
+const static uint64_t SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN = 6951; // 12
+const static uint64_t SH_FLD_INSTR0_BUSYCNT_RUNNING = 6952; // 1
+const static uint64_t SH_FLD_INSTR0_CYCLECNT_RUNNING = 6953; // 1
+const static uint64_t SH_FLD_INSTR0_MODE = 6954; // 1
+const static uint64_t SH_FLD_INSTR0_MODE_LEN = 6955; // 1
+const static uint64_t SH_FLD_INSTR0_RESET = 6956; // 1
+const static uint64_t SH_FLD_INSTR0_START = 6957; // 1
+const static uint64_t SH_FLD_INSTR0_STOP = 6958; // 1
+const static uint64_t SH_FLD_INSTR0_STOPPED_ON_ERROR = 6959; // 1
+const static uint64_t SH_FLD_INSTR0_STOP_ON_ERROR_GT = 6960; // 1
+const static uint64_t SH_FLD_INSTR0_STOP_ON_ERROR_GT_LEN = 6961; // 1
+const static uint64_t SH_FLD_INSTR0_STOP_TIMER_EN = 6962; // 1
+const static uint64_t SH_FLD_INSTR1_BUSYCNT_RUNNING = 6963; // 1
+const static uint64_t SH_FLD_INSTR1_CYCLECNT_RUNNING = 6964; // 1
+const static uint64_t SH_FLD_INSTR1_MODE = 6965; // 1
+const static uint64_t SH_FLD_INSTR1_MODE_LEN = 6966; // 1
+const static uint64_t SH_FLD_INSTR1_RESET = 6967; // 1
+const static uint64_t SH_FLD_INSTR1_START = 6968; // 1
+const static uint64_t SH_FLD_INSTR1_STOP = 6969; // 1
+const static uint64_t SH_FLD_INSTR1_STOPPED_ON_ERROR = 6970; // 1
+const static uint64_t SH_FLD_INSTR1_STOP_ON_ERROR_GT = 6971; // 1
+const static uint64_t SH_FLD_INSTR1_STOP_ON_ERROR_GT_LEN = 6972; // 1
+const static uint64_t SH_FLD_INSTR1_STOP_TIMER_EN = 6973; // 1
+const static uint64_t SH_FLD_INSTR2_BUSYCNT_RUNNING = 6974; // 1
+const static uint64_t SH_FLD_INSTR2_CYCLECNT_RUNNING = 6975; // 1
+const static uint64_t SH_FLD_INSTR2_MODE = 6976; // 1
+const static uint64_t SH_FLD_INSTR2_MODE_LEN = 6977; // 1
+const static uint64_t SH_FLD_INSTR2_RESET = 6978; // 1
+const static uint64_t SH_FLD_INSTR2_START = 6979; // 1
+const static uint64_t SH_FLD_INSTR2_STOP = 6980; // 1
+const static uint64_t SH_FLD_INSTR2_STOPPED_ON_ERROR = 6981; // 1
+const static uint64_t SH_FLD_INSTR2_STOP_ON_ERROR_GT = 6982; // 1
+const static uint64_t SH_FLD_INSTR2_STOP_ON_ERROR_GT_LEN = 6983; // 1
+const static uint64_t SH_FLD_INSTR2_STOP_TIMER_EN = 6984; // 1
+const static uint64_t SH_FLD_INST_CYCLE_SAMPLE = 6985; // 12
+const static uint64_t SH_FLD_INST_CYCLE_SAMPLE_LEN = 6986; // 12
+const static uint64_t SH_FLD_INT = 6987; // 1
+const static uint64_t SH_FLD_INTERMITTENT_CE_COUNT = 6988; // 2
+const static uint64_t SH_FLD_INTERMITTENT_CE_COUNT_LEN = 6989; // 2
+const static uint64_t SH_FLD_INTERMITTENT_ETE_ATTN = 6990; // 4
+const static uint64_t SH_FLD_INTERMITTENT_MCE_COUNT = 6991; // 2
+const static uint64_t SH_FLD_INTERMITTENT_MCE_COUNT_LEN = 6992; // 2
+const static uint64_t SH_FLD_INTERNAL_ERR = 6993; // 1
+const static uint64_t SH_FLD_INTERNAL_ERROR = 6994; // 4
+const static uint64_t SH_FLD_INTERNAL_ERR_MASK = 6995; // 1
+const static uint64_t SH_FLD_INTERNAL_FSM_ERROR = 6996; // 10
+const static uint64_t SH_FLD_INTERNAL_SCOM_ERROR = 6997; // 40
+const static uint64_t SH_FLD_INTERNAL_SCOM_ERROR_CLONE = 6998; // 16
+const static uint64_t SH_FLD_INTERNAL_SCOM_ERROR_COPY = 6999; // 24
+const static uint64_t SH_FLD_INTERRUPT0_ADDRESS_ERROR = 7000; // 4
+const static uint64_t SH_FLD_INTERRUPT1 = 7001; // 1
+const static uint64_t SH_FLD_INTERRUPT1_ADDRESS_ERROR = 7002; // 4
+const static uint64_t SH_FLD_INTERRUPT1_LEN = 7003; // 1
+const static uint64_t SH_FLD_INTERRUPT2 = 7004; // 2
+const static uint64_t SH_FLD_INTERRUPT2_ADDRESS_ERROR = 7005; // 4
+const static uint64_t SH_FLD_INTERRUPT2_LEN = 7006; // 2
+const static uint64_t SH_FLD_INTERRUPT3 = 7007; // 2
+const static uint64_t SH_FLD_INTERRUPT3_ADDRESS_ERROR = 7008; // 4
+const static uint64_t SH_FLD_INTERRUPT3_LEN = 7009; // 2
+const static uint64_t SH_FLD_INTERRUPT4 = 7010; // 2
+const static uint64_t SH_FLD_INTERRUPT4_ADDRESS_ERROR = 7011; // 4
+const static uint64_t SH_FLD_INTERRUPT4_LEN = 7012; // 2
+const static uint64_t SH_FLD_INTERRUPT5_ADDRESS_ERROR = 7013; // 4
+const static uint64_t SH_FLD_INTERRUPT_CHANGE_WHILE_ACTIVE = 7014; // 4
+const static uint64_t SH_FLD_INTERRUPT_CONDITION_PENDING = 7015; // 1
+const static uint64_t SH_FLD_INTERRUPT_DISABLE = 7016; // 1
+const static uint64_t SH_FLD_INTERRUPT_DISABLE_LEN = 7017; // 1
+const static uint64_t SH_FLD_INTERRUPT_EDGE_POL_N = 7018; // 2
+const static uint64_t SH_FLD_INTERRUPT_EDGE_POL_N_LEN = 7019; // 2
+const static uint64_t SH_FLD_INTERRUPT_ENABLE = 7020; // 2
+const static uint64_t SH_FLD_INTERRUPT_ENABLED = 7021; // 1
+const static uint64_t SH_FLD_INTERRUPT_FROM_ERROR = 7022; // 4
+const static uint64_t SH_FLD_INTERRUPT_FROM_FSP = 7023; // 4
+const static uint64_t SH_FLD_INTERRUPT_INPUT = 7024; // 12
+const static uint64_t SH_FLD_INTERRUPT_INPUT_LEN = 7025; // 12
+const static uint64_t SH_FLD_INTERRUPT_MASK = 7026; // 12
+const static uint64_t SH_FLD_INTERRUPT_MASK_LEN = 7027; // 12
+const static uint64_t SH_FLD_INTERRUPT_MASK_N = 7028; // 2
+const static uint64_t SH_FLD_INTERRUPT_MASK_N_LEN = 7029; // 2
+const static uint64_t SH_FLD_INTERRUPT_POLARITY = 7030; // 12
+const static uint64_t SH_FLD_INTERRUPT_POLARITY_LEN = 7031; // 12
+const static uint64_t SH_FLD_INTERRUPT_ROUTE_A_N = 7032; // 6
+const static uint64_t SH_FLD_INTERRUPT_ROUTE_A_N_LEN = 7033; // 6
+const static uint64_t SH_FLD_INTERRUPT_S0 = 7034; // 1
+const static uint64_t SH_FLD_INTERRUPT_S1 = 7035; // 1
+const static uint64_t SH_FLD_INTERRUPT_SENT = 7036; // 1
+const static uint64_t SH_FLD_INTERRUPT_TYPE = 7037; // 12
+const static uint64_t SH_FLD_INTERRUPT_TYPE_LEN = 7038; // 12
+const static uint64_t SH_FLD_INTERRUPT_TYPE_N = 7039; // 2
+const static uint64_t SH_FLD_INTERRUPT_TYPE_N_LEN = 7040; // 2
+const static uint64_t SH_FLD_INTER_FRAME_DELAY = 7041; // 1
+const static uint64_t SH_FLD_INTER_FRAME_DELAY_LEN = 7042; // 1
+const static uint64_t SH_FLD_INTQ_FSM_PERR = 7043; // 1
+const static uint64_t SH_FLD_INTQ_OVERFLOW = 7044; // 1
+const static uint64_t SH_FLD_INTR0 = 7045; // 5
+const static uint64_t SH_FLD_INTR1 = 7046; // 5
+const static uint64_t SH_FLD_INTR_GRANTED = 7047; // 30
+const static uint64_t SH_FLD_INT_0 = 7048; // 2
+const static uint64_t SH_FLD_INT_0_LEN = 7049; // 2
+const static uint64_t SH_FLD_INT_1 = 7050; // 2
+const static uint64_t SH_FLD_INT_1_LEN = 7051; // 2
+const static uint64_t SH_FLD_INT_2 = 7052; // 2
+const static uint64_t SH_FLD_INT_2_LEN = 7053; // 2
+const static uint64_t SH_FLD_INT_3 = 7054; // 2
+const static uint64_t SH_FLD_INT_3_LEN = 7055; // 2
+const static uint64_t SH_FLD_INT_CNTR_REF = 7056; // 1
+const static uint64_t SH_FLD_INT_CNTR_REF_LEN = 7057; // 1
+const static uint64_t SH_FLD_INT_CURRENT_STATE = 7058; // 6
+const static uint64_t SH_FLD_INT_CURRENT_STATE_LEN = 7059; // 6
+const static uint64_t SH_FLD_INT_ENA = 7060; // 1
+const static uint64_t SH_FLD_INT_ENABLE_ENC = 7061; // 6
+const static uint64_t SH_FLD_INT_ENABLE_ENC_LEN = 7062; // 6
+const static uint64_t SH_FLD_INT_GOTO_STATE = 7063; // 6
+const static uint64_t SH_FLD_INT_GOTO_STATE_LEN = 7064; // 6
+const static uint64_t SH_FLD_INT_LEN = 7065; // 1
+const static uint64_t SH_FLD_INT_MAX_Q_DEPTH = 7066; // 1
+const static uint64_t SH_FLD_INT_MAX_Q_DEPTH_LEN = 7067; // 1
+const static uint64_t SH_FLD_INT_MODE = 7068; // 6
+const static uint64_t SH_FLD_INT_MODE_LEN = 7069; // 6
+const static uint64_t SH_FLD_INT_NCE_ETE_ATTN = 7070; // 10
+const static uint64_t SH_FLD_INT_NEXT_STATE = 7071; // 6
+const static uint64_t SH_FLD_INT_NEXT_STATE_LEN = 7072; // 6
+const static uint64_t SH_FLD_INT_RETURN_STATE = 7073; // 6
+const static uint64_t SH_FLD_INT_RETURN_STATE_LEN = 7074; // 6
+const static uint64_t SH_FLD_INT_RX_FSM = 7075; // 43
+const static uint64_t SH_FLD_INT_TX_FSM = 7076; // 43
+const static uint64_t SH_FLD_INT_TYPE = 7077; // 43
+const static uint64_t SH_FLD_INVALIDATE_ADDRESS = 7078; // 1
+const static uint64_t SH_FLD_INVALIDATE_ADDRESS_LEN = 7079; // 1
+const static uint64_t SH_FLD_INVALIDATE_ALL = 7080; // 1
+const static uint64_t SH_FLD_INVALIDATE_ONE = 7081; // 1
+const static uint64_t SH_FLD_INVALIDATE_PE_NUMBER = 7082; // 1
+const static uint64_t SH_FLD_INVALIDATE_PE_NUMBER_LEN = 7083; // 1
+const static uint64_t SH_FLD_INVALIDCRESP = 7084; // 9
+const static uint64_t SH_FLD_INVALIDCRESP_MASK = 7085; // 9
+const static uint64_t SH_FLD_INVALID_ADDRESS = 7086; // 12
+const static uint64_t SH_FLD_INVALID_ADDRESS_ALIGNMENT = 7087; // 4
+const static uint64_t SH_FLD_INVALID_ADDRESS_MASK = 7088; // 8
+const static uint64_t SH_FLD_INVALID_CMD_0 = 7089; // 2
+const static uint64_t SH_FLD_INVALID_CMD_1 = 7090; // 2
+const static uint64_t SH_FLD_INVALID_CMD_2 = 7091; // 2
+const static uint64_t SH_FLD_INVALID_CMD_3 = 7092; // 2
+const static uint64_t SH_FLD_INVALID_COMMAND = 7093; // 4
+const static uint64_t SH_FLD_INVALID_CRESP = 7094; // 4
+const static uint64_t SH_FLD_INVALID_CRESP_ERR = 7095; // 1
+const static uint64_t SH_FLD_INVALID_CRESP_ERROR = 7096; // 2
+const static uint64_t SH_FLD_INVALID_MAINT_ADDRESS = 7097; // 10
+const static uint64_t SH_FLD_INVALID_REQTYPE = 7098; // 16
+const static uint64_t SH_FLD_INVALID_REQTYPE_ERR_MASK = 7099; // 8
+const static uint64_t SH_FLD_INVALID_REQTYPE_LEN = 7100; // 8
+const static uint64_t SH_FLD_INVALID_REQ_SOURCE = 7101; // 8
+const static uint64_t SH_FLD_INVALID_REQ_SOURCE_LEN = 7102; // 8
+const static uint64_t SH_FLD_INVALID_STATE_RECOV = 7103; // 1
+const static uint64_t SH_FLD_INVALID_STATE_UNRECOV = 7104; // 1
+const static uint64_t SH_FLD_INVALID_TRANSFER_SIZE = 7105; // 4
+const static uint64_t SH_FLD_INVALID_TTYPE = 7106; // 4
+const static uint64_t SH_FLD_INVLD_CMD_ERR = 7107; // 1
+const static uint64_t SH_FLD_INVLD_PRGM_ERR = 7108; // 1
+const static uint64_t SH_FLD_INV_SINGLE_THREAD_EN = 7109; // 1
+const static uint64_t SH_FLD_IN_BAD_OP_ERR = 7110; // 2
+const static uint64_t SH_FLD_IN_CERR_BITS = 7111; // 1
+const static uint64_t SH_FLD_IN_CERR_BITS_LEN = 7112; // 1
+const static uint64_t SH_FLD_IN_CERR_RESET = 7113; // 1
+const static uint64_t SH_FLD_IN_COUNT1 = 7114; // 1
+const static uint64_t SH_FLD_IN_COUNT1_LEN = 7115; // 1
+const static uint64_t SH_FLD_IN_COUNT2 = 7116; // 1
+const static uint64_t SH_FLD_IN_COUNT2_LEN = 7117; // 1
+const static uint64_t SH_FLD_IN_DELAY1 = 7118; // 1
+const static uint64_t SH_FLD_IN_DELAY1_LEN = 7119; // 1
+const static uint64_t SH_FLD_IN_DELAY2 = 7120; // 1
+const static uint64_t SH_FLD_IN_DELAY2_LEN = 7121; // 1
+const static uint64_t SH_FLD_IN_ECC_CE_ERROR = 7122; // 2
+const static uint64_t SH_FLD_IN_ECC_SUE_ERROR = 7123; // 2
+const static uint64_t SH_FLD_IN_ECC_UE_ERROR = 7124; // 2
+const static uint64_t SH_FLD_IN_LEN = 7125; // 130
+const static uint64_t SH_FLD_IN_LOGIC_HW_ERROR = 7126; // 2
+const static uint64_t SH_FLD_IN_MASTER_MODE = 7127; // 43
+const static uint64_t SH_FLD_IN_PARITY_ERROR = 7128; // 2
+const static uint64_t SH_FLD_IN_PROG = 7129; // 1
+const static uint64_t SH_FLD_IN_PROG_LEN = 7130; // 1
+const static uint64_t SH_FLD_IN_SEQ_ERR = 7131; // 2
+const static uint64_t SH_FLD_IN_SEQ_PERR = 7132; // 2
+const static uint64_t SH_FLD_IN_SLAVE_MODE = 7133; // 43
+const static uint64_t SH_FLD_IN_SNP_ADDR_PERR = 7134; // 2
+const static uint64_t SH_FLD_IN_SNP_TTAG_PERR = 7135; // 2
+const static uint64_t SH_FLD_IN_SW_CAST_ERROR = 7136; // 2
+const static uint64_t SH_FLD_IN_TIMEOUT = 7137; // 2
+const static uint64_t SH_FLD_IN_TRACE_GROUP_SEL_HI = 7138; // 1
+const static uint64_t SH_FLD_IN_TRACE_GROUP_SEL_HI_LEN = 7139; // 1
+const static uint64_t SH_FLD_IN_TRACE_GROUP_SEL_LO = 7140; // 1
+const static uint64_t SH_FLD_IN_TRACE_GROUP_SEL_LO_LEN = 7141; // 1
+const static uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_01 = 7142; // 1
+const static uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_01_LEN = 7143; // 1
+const static uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_23 = 7144; // 1
+const static uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_23_LEN = 7145; // 1
+const static uint64_t SH_FLD_IOE01_IS_LOGICAL_PAIR = 7146; // 1
+const static uint64_t SH_FLD_IOE23_IS_LOGICAL_PAIR = 7147; // 1
+const static uint64_t SH_FLD_IOE45_IS_LOGICAL_PAIR = 7148; // 1
+const static uint64_t SH_FLD_IOO01_IS_LOGICAL_PAIR = 7149; // 1
+const static uint64_t SH_FLD_IOO23_IS_LOGICAL_PAIR = 7150; // 1
+const static uint64_t SH_FLD_IOO45_IS_LOGICAL_PAIR = 7151; // 1
+const static uint64_t SH_FLD_IOO67_IS_LOGICAL_PAIR = 7152; // 1
+const static uint64_t SH_FLD_IORESET_HARD_BUS0 = 7153; // 4
+const static uint64_t SH_FLD_IORESET_HARD_BUS0_LEN = 7154; // 4
+const static uint64_t SH_FLD_IORESET_VEC_0_15 = 7155; // 4
+const static uint64_t SH_FLD_IORESET_VEC_0_15_LEN = 7156; // 4
+const static uint64_t SH_FLD_IORESET_VEC_16_23 = 7157; // 4
+const static uint64_t SH_FLD_IORESET_VEC_16_23_LEN = 7158; // 4
+const static uint64_t SH_FLD_IOVALID = 7159; // 1
+const static uint64_t SH_FLD_IOVALID_10D = 7160; // 41
+const static uint64_t SH_FLD_IOVALID_11D = 7161; // 41
+const static uint64_t SH_FLD_IOVALID_4D = 7162; // 37
+const static uint64_t SH_FLD_IOVALID_5D = 7163; // 38
+const static uint64_t SH_FLD_IOVALID_6D = 7164; // 41
+const static uint64_t SH_FLD_IOVALID_7D = 7165; // 41
+const static uint64_t SH_FLD_IOVALID_8D = 7166; // 41
+const static uint64_t SH_FLD_IOVALID_9D = 7167; // 41
+const static uint64_t SH_FLD_IP = 7168; // 4
+const static uint64_t SH_FLD_IPI = 7169; // 1
+const static uint64_t SH_FLD_IPI0_HI_PRIORITY = 7170; // 1
+const static uint64_t SH_FLD_IPI0_LO_PRIORITY = 7171; // 1
+const static uint64_t SH_FLD_IPI1_HI_PRIORITY = 7172; // 1
+const static uint64_t SH_FLD_IPI1_LO_PRIORITY = 7173; // 1
+const static uint64_t SH_FLD_IPI2_HI_PRIORITY = 7174; // 1
+const static uint64_t SH_FLD_IPI2_LO_PRIORITY = 7175; // 1
+const static uint64_t SH_FLD_IPI3_HI_PRIORITY = 7176; // 1
+const static uint64_t SH_FLD_IPI3_LO_PRIORITY = 7177; // 1
+const static uint64_t SH_FLD_IPI4_HI_PRIORITY = 7178; // 1
+const static uint64_t SH_FLD_IPI4_LO_PRIORITY = 7179; // 1
+const static uint64_t SH_FLD_IPI_LEN = 7180; // 1
+const static uint64_t SH_FLD_IPI_PRIORITY = 7181; // 1
+const static uint64_t SH_FLD_IPI_PRIORITY_LEN = 7182; // 1
+const static uint64_t SH_FLD_IPI_RSD = 7183; // 1
+const static uint64_t SH_FLD_IPI_RSD_LEN = 7184; // 1
+const static uint64_t SH_FLD_IPOLL_0 = 7185; // 1
+const static uint64_t SH_FLD_IPOLL_1 = 7186; // 1
+const static uint64_t SH_FLD_IPOLL_2 = 7187; // 1
+const static uint64_t SH_FLD_IPOLL_3 = 7188; // 1
+const static uint64_t SH_FLD_IPOLL_4 = 7189; // 1
+const static uint64_t SH_FLD_IPOLL_5 = 7190; // 1
+const static uint64_t SH_FLD_IPW_SIDEAB_SEL = 7191; // 8
+const static uint64_t SH_FLD_IPW_WR_WR = 7192; // 8
+const static uint64_t SH_FLD_IPW_WR_WR_LEN = 7193; // 8
+const static uint64_t SH_FLD_IQHISPD_EN = 7194; // 4
+const static uint64_t SH_FLD_IR = 7195; // 18
+const static uint64_t SH_FLD_IREF_BYPASS = 7196; // 2
+const static uint64_t SH_FLD_IREF_PDWN_B = 7197; // 2
+const static uint64_t SH_FLD_IREF_RES_DAC = 7198; // 2
+const static uint64_t SH_FLD_IREF_RES_DAC_LEN = 7199; // 2
+const static uint64_t SH_FLD_IRQ = 7200; // 1
+const static uint64_t SH_FLD_IRQ_LEN = 7201; // 1
+const static uint64_t SH_FLD_IRQ_TRACE_ENABLE = 7202; // 1
+const static uint64_t SH_FLD_IR_DR_EQ0_ERR = 7203; // 1
+const static uint64_t SH_FLD_IR_LEN = 7204; // 18
+const static uint64_t SH_FLD_IS_ACTIVE_MASTER = 7205; // 1
+const static uint64_t SH_FLD_IS_BACKUP_MASTER = 7206; // 1
+const static uint64_t SH_FLD_IS_PRIMARY = 7207; // 1
+const static uint64_t SH_FLD_IS_RUNNING = 7208; // 2
+const static uint64_t SH_FLD_IS_SECONDARY = 7209; // 1
+const static uint64_t SH_FLD_IS_SLAVE = 7210; // 1
+const static uint64_t SH_FLD_IS_SPECIAL = 7211; // 1
+const static uint64_t SH_FLD_ITUNE = 7212; // 4
+const static uint64_t SH_FLD_ITUNE_LEN = 7213; // 4
+const static uint64_t SH_FLD_IVC = 7214; // 1
+const static uint64_t SH_FLD_IVC_INTF_DISABLE = 7215; // 6
+const static uint64_t SH_FLD_IVC_LEN = 7216; // 1
+const static uint64_t SH_FLD_IVPR = 7217; // 5
+const static uint64_t SH_FLD_IVPR_LEN = 7218; // 5
+const static uint64_t SH_FLD_IVRM_BYPASS_B = 7219; // 60
+const static uint64_t SH_FLD_IVRM_IVID = 7220; // 60
+const static uint64_t SH_FLD_IVRM_IVID_LEN = 7221; // 60
+const static uint64_t SH_FLD_IVRM_LOCAL_CONTROL = 7222; // 24
+const static uint64_t SH_FLD_IVRM_PFET_STRENGTH_CACHE = 7223; // 60
+const static uint64_t SH_FLD_IVRM_PFET_STRENGTH_CACHE_LEN = 7224; // 60
+const static uint64_t SH_FLD_IVRM_PFET_STRENGTH_CORE = 7225; // 60
+const static uint64_t SH_FLD_IVRM_PFET_STRENGTH_CORE_LEN = 7226; // 60
+const static uint64_t SH_FLD_IVRM_POWERON = 7227; // 60
+const static uint64_t SH_FLD_IVRM_PVREF_ERROR = 7228; // 1
+const static uint64_t SH_FLD_IVRM_UREG_TEST_EN = 7229; // 24
+const static uint64_t SH_FLD_IVRM_UREG_TEST_ID = 7230; // 24
+const static uint64_t SH_FLD_IVRM_UREG_TEST_ID_LEN = 7231; // 24
+const static uint64_t SH_FLD_IVRM_VID_DONE = 7232; // 30
+const static uint64_t SH_FLD_IVRM_VID_VALID = 7233; // 60
+const static uint64_t SH_FLD_IVRM_VREG_SLOW_DC = 7234; // 60
+const static uint64_t SH_FLD_I_DELAY_ADJUST_RATIO = 7235; // 1
+const static uint64_t SH_FLD_I_DELAY_ADJUST_RATIO_LEN = 7236; // 1
+const static uint64_t SH_FLD_I_PATH_CORE_SYNC_PERIOD_SELECT = 7237; // 1
+const static uint64_t SH_FLD_I_PATH_CORE_SYNC_PERIOD_SELECT_LEN = 7238; // 1
+const static uint64_t SH_FLD_I_PATH_DELAY_ADJUST = 7239; // 1
+const static uint64_t SH_FLD_I_PATH_DELAY_STEP_CHECK_PARITY = 7240; // 4
+const static uint64_t SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD = 7241; // 1
+const static uint64_t SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE = 7242; // 1
+const static uint64_t SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE_LEN = 7243; // 1
+const static uint64_t SH_FLD_I_PATH_DELAY_VALUE = 7244; // 2
+const static uint64_t SH_FLD_I_PATH_DELAY_VALUE_LEN = 7245; // 2
+const static uint64_t SH_FLD_I_PATH_FSM_STATE_PARITY = 7246; // 4
+const static uint64_t SH_FLD_I_PATH_STATE = 7247; // 1
+const static uint64_t SH_FLD_I_PATH_STATE_LEN = 7248; // 1
+const static uint64_t SH_FLD_I_PATH_STEP_CHECK = 7249; // 4
+const static uint64_t SH_FLD_I_PATH_STEP_CHECK_CPS_DEVIATION_X_DISABLE =
+    7250; // 1
+const static uint64_t SH_FLD_I_PATH_STEP_CHECK_VALID = 7251; // 1
+const static uint64_t SH_FLD_I_PATH_SYNC_CHECK = 7252; // 4
+const static uint64_t SH_FLD_I_PATH_SYNC_CHECK_DISABLE = 7253; // 1
+const static uint64_t SH_FLD_I_PATH_TIME_OVERFLOW = 7254; // 3
+const static uint64_t SH_FLD_I_PATH_TIME_OVERFLOW_CORE_INTERRUPT = 7255; // 1
+const static uint64_t SH_FLD_I_PATH_TIME_PARITY = 7256; // 4
+const static uint64_t SH_FLD_JITTER_EPSILON = 7257; // 8
+const static uint64_t SH_FLD_JITTER_EPSILON_LEN = 7258; // 8
+const static uint64_t SH_FLD_JTAG_INPROG = 7259; // 1
+const static uint64_t SH_FLD_JTAG_INSTR = 7260; // 1
+const static uint64_t SH_FLD_JTAG_INSTR_LEN = 7261; // 1
+const static uint64_t SH_FLD_JTAG_SRC_SEL = 7262; // 1
+const static uint64_t SH_FLD_JTAG_TDI = 7263; // 1
+const static uint64_t SH_FLD_JTAG_TDI_LEN = 7264; // 1
+const static uint64_t SH_FLD_JTAG_TDO = 7265; // 1
+const static uint64_t SH_FLD_JTAG_TDO_LEN = 7266; // 1
+const static uint64_t SH_FLD_JTAG_TRST_B = 7267; // 1
+const static uint64_t SH_FLD_KEEP_EDRAM_ENABLED_ON = 7268; // 129
+const static uint64_t SH_FLD_KEEP_MS_MODE = 7269; // 43
+const static uint64_t SH_FLD_L2 = 7270; // 12
+const static uint64_t SH_FLD_L2_CORE_INTF_QUIESCE_C0 = 7271; // 12
+const static uint64_t SH_FLD_L2_CORE_INTF_QUIESCE_C1 = 7272; // 12
+const static uint64_t SH_FLD_L2_EX0_CLKGLM_ASYNC_RESET = 7273; // 6
+const static uint64_t SH_FLD_L2_EX0_CLKGLM_DIRECT_VALUE = 7274; // 6
+const static uint64_t SH_FLD_L2_EX0_CLKGLM_SEL = 7275; // 6
+const static uint64_t SH_FLD_L2_EX0_CLKGLM_SEL_LEN = 7276; // 6
+const static uint64_t SH_FLD_L2_EX0_CLK_SB_PULSE_MODE = 7277; // 6
+const static uint64_t SH_FLD_L2_EX0_CLK_SB_PULSE_MODE_EN = 7278; // 6
+const static uint64_t SH_FLD_L2_EX0_CLK_SB_PULSE_MODE_LEN = 7279; // 6
+const static uint64_t SH_FLD_L2_EX0_CLK_SB_SPARE0 = 7280; // 6
+const static uint64_t SH_FLD_L2_EX0_CLK_SB_STRENGTH = 7281; // 6
+const static uint64_t SH_FLD_L2_EX0_CLK_SB_STRENGTH_LEN = 7282; // 6
+const static uint64_t SH_FLD_L2_EX0_CLK_SW_RESCLK = 7283; // 6
+const static uint64_t SH_FLD_L2_EX0_CLK_SW_RESCLK_LEN = 7284; // 6
+const static uint64_t SH_FLD_L2_EX0_CLK_SW_SPARE1 = 7285; // 6
+const static uint64_t SH_FLD_L2_EX0_CLK_SYNC = 7286; // 6
+const static uint64_t SH_FLD_L2_EX0_CLK_SYNC_DONE = 7287; // 6
+const static uint64_t SH_FLD_L2_EX0_CLK_SYNC_ENABLE = 7288; // 6
+const static uint64_t SH_FLD_L2_EX1_CLKGLM_ASYNC_RESET = 7289; // 6
+const static uint64_t SH_FLD_L2_EX1_CLKGLM_DIRECT_VALUE = 7290; // 6
+const static uint64_t SH_FLD_L2_EX1_CLKGLM_SEL = 7291; // 6
+const static uint64_t SH_FLD_L2_EX1_CLKGLM_SEL_LEN = 7292; // 6
+const static uint64_t SH_FLD_L2_EX1_CLK_SB_PULSE_MODE = 7293; // 6
+const static uint64_t SH_FLD_L2_EX1_CLK_SB_PULSE_MODE_EN = 7294; // 6
+const static uint64_t SH_FLD_L2_EX1_CLK_SB_PULSE_MODE_LEN = 7295; // 6
+const static uint64_t SH_FLD_L2_EX1_CLK_SB_SPARE0 = 7296; // 6
+const static uint64_t SH_FLD_L2_EX1_CLK_SB_STRENGTH = 7297; // 6
+const static uint64_t SH_FLD_L2_EX1_CLK_SB_STRENGTH_LEN = 7298; // 6
+const static uint64_t SH_FLD_L2_EX1_CLK_SW_RESCLK = 7299; // 6
+const static uint64_t SH_FLD_L2_EX1_CLK_SW_RESCLK_LEN = 7300; // 6
+const static uint64_t SH_FLD_L2_EX1_CLK_SW_SPARE1 = 7301; // 6
+const static uint64_t SH_FLD_L2_EX1_CLK_SYNC = 7302; // 6
+const static uint64_t SH_FLD_L2_EX1_CLK_SYNC_DONE = 7303; // 6
+const static uint64_t SH_FLD_L2_EX1_CLK_SYNC_ENABLE = 7304; // 6
+const static uint64_t SH_FLD_L2_LEN = 7305; // 12
+const static uint64_t SH_FLD_L2_PURGE = 7306; // 12
+const static uint64_t SH_FLD_L2_PURGE_ABORT = 7307; // 12
+const static uint64_t SH_FLD_L2_PURGE_DONE = 7308; // 24
+const static uint64_t SH_FLD_L2_STEP_MODE = 7309; // 12
+const static uint64_t SH_FLD_L2_STEP_MODE_LEN = 7310; // 12
+const static uint64_t SH_FLD_L2_STOPPED = 7311; // 1
+const static uint64_t SH_FLD_L2_STOPPED_LEN = 7312; // 1
+const static uint64_t SH_FLD_L3 = 7313; // 24
+const static uint64_t SH_FLD_L3CERRS_CFG_DCACHE_CAPP = 7314; // 12
+const static uint64_t SH_FLD_L3CERRS_LCO_RETRY_THROTL_DIS = 7315; // 12
+const static uint64_t SH_FLD_L3CICTL_CI_OVERRUN_CK_ERR = 7316; // 12
+const static uint64_t SH_FLD_L3CORTR_NO_LCO_TGTS_ERR = 7317; // 12
+const static uint64_t SH_FLD_L3L2CTL_PF_OVERRUN_CK_ERR = 7318; // 12
+const static uint64_t SH_FLD_L3L2CTL_RD_OVERRUN_CK_ERR = 7319; // 12
+const static uint64_t SH_FLD_L3PBEXCA0_OVERFLOW_ERR = 7320; // 12
+const static uint64_t SH_FLD_L3PBEXCA0_UNDERFLOW_ERR = 7321; // 12
+const static uint64_t SH_FLD_L3PBEXCA1_OVERFLOW_ERR = 7322; // 12
+const static uint64_t SH_FLD_L3PBEXCA1_UNDERFLOW_ERR = 7323; // 12
+const static uint64_t SH_FLD_L3SDRTL0_CACHE_INHIBIT_ERR = 7324; // 12
+const static uint64_t SH_FLD_L3SDRTL0_CHECKSTOP_ERR = 7325; // 12
+const static uint64_t SH_FLD_L3SDRTL1_CACHE_INHIBIT_ERR = 7326; // 12
+const static uint64_t SH_FLD_L3SDRTL1_CHECKSTOP_ERR = 7327; // 12
+const static uint64_t SH_FLD_L3XMEMA0_CRW_DIR_HIT_ERR = 7328; // 12
+const static uint64_t SH_FLD_L3XMEMA0_DW_DIR_HIT_ERR = 7329; // 12
+const static uint64_t SH_FLD_L3XMEMA1_CRW_DIR_HIT_ERR = 7330; // 12
+const static uint64_t SH_FLD_L3XMEMA1_DW_DIR_HIT_ERR = 7331; // 12
+const static uint64_t SH_FLD_L3_1ST_BEAT_SYNDROME = 7332; // 12
+const static uint64_t SH_FLD_L3_1ST_BEAT_SYNDROME_LEN = 7333; // 12
+const static uint64_t SH_FLD_L3_1ST_BEAT_UE = 7334; // 12
+const static uint64_t SH_FLD_L3_2ND_BEAT_SYNDROME = 7335; // 12
+const static uint64_t SH_FLD_L3_2ND_BEAT_SYNDROME_LEN = 7336; // 12
+const static uint64_t SH_FLD_L3_2ND_BEAT_UE = 7337; // 12
+const static uint64_t SH_FLD_L3_ADDR_HANG_DETECTED = 7338; // 12
+const static uint64_t SH_FLD_L3_ADDR_HASH_EN_CFG = 7339; // 12
+const static uint64_t SH_FLD_L3_ALL_MEMBERS_DELETED_ERROR = 7340; // 12
+const static uint64_t SH_FLD_L3_BANK = 7341; // 12
+const static uint64_t SH_FLD_L3_BANK_LEN = 7342; // 12
+const static uint64_t SH_FLD_L3_BUSY_ERR = 7343; // 36
+const static uint64_t SH_FLD_L3_CAC_RD_CE_DET_NOT_LINDEL_REQ = 7344; // 12
+const static uint64_t SH_FLD_L3_CAC_RD_SUE_DET = 7345; // 12
+const static uint64_t SH_FLD_L3_CAC_RD_UE_DET = 7346; // 12
+const static uint64_t SH_FLD_L3_CAC_TYPE = 7347; // 12
+const static uint64_t SH_FLD_L3_CAC_TYPE_LEN = 7348; // 12
+const static uint64_t SH_FLD_L3_CAC_WR_DATA_CE_FROM_L2 = 7349; // 12
+const static uint64_t SH_FLD_L3_CAC_WR_DATA_CE_FROM_PB = 7350; // 12
+const static uint64_t SH_FLD_L3_CAC_WR_DATA_SUE_FROM_L2_OR_WIHPC = 7351; // 12
+const static uint64_t SH_FLD_L3_CAC_WR_DATA_SUE_FROM_PB = 7352; // 12
+const static uint64_t SH_FLD_L3_CAC_WR_DATA_UE_FROM_L2 = 7353; // 12
+const static uint64_t SH_FLD_L3_CAC_WR_DATA_UE_FROM_PB = 7354; // 12
+const static uint64_t SH_FLD_L3_CFG = 7355; // 12
+const static uint64_t SH_FLD_L3_CLK_SB_PULSE_MODE = 7356; // 6
+const static uint64_t SH_FLD_L3_CLK_SB_PULSE_MODE_EN = 7357; // 6
+const static uint64_t SH_FLD_L3_CLK_SB_PULSE_MODE_LEN = 7358; // 6
+const static uint64_t SH_FLD_L3_CLK_SB_SPARE0 = 7359; // 6
+const static uint64_t SH_FLD_L3_CLK_SB_STRENGTH = 7360; // 6
+const static uint64_t SH_FLD_L3_CLK_SB_STRENGTH_LEN = 7361; // 6
+const static uint64_t SH_FLD_L3_COLUMN_MD_CFG = 7362; // 12
+const static uint64_t SH_FLD_L3_COLUMN_MD_CFG_LEN = 7363; // 12
+const static uint64_t SH_FLD_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG = 7364; // 12
+const static uint64_t SH_FLD_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG_LEN = 7365; // 12
+const static uint64_t SH_FLD_L3_CO_SN_CRESP_ADDR_ERR = 7366; // 12
+const static uint64_t SH_FLD_L3_CP_UTIL_EN_DC = 7367; // 12
+const static uint64_t SH_FLD_L3_CP_UTIL_EXT_SEL = 7368; // 12
+const static uint64_t SH_FLD_L3_CP_UTIL_EXT_SEL_LEN = 7369; // 12
+const static uint64_t SH_FLD_L3_CP_UTIL_SEL_DC = 7370; // 12
+const static uint64_t SH_FLD_L3_CP_UTIL_SEL_DC_LEN = 7371; // 12
+const static uint64_t SH_FLD_L3_DATA_POLL_PULSE_DIV = 7372; // 12
+const static uint64_t SH_FLD_L3_DATA_POLL_PULSE_DIV_LEN = 7373; // 12
+const static uint64_t SH_FLD_L3_DIR_ADDR = 7374; // 24
+const static uint64_t SH_FLD_L3_DIR_ADDR_LEN = 7375; // 24
+const static uint64_t SH_FLD_L3_DIR_RD_CE_DET = 7376; // 12
+const static uint64_t SH_FLD_L3_DIR_RD_PHANTOM_ERROR = 7377; // 12
+const static uint64_t SH_FLD_L3_DIR_RD_UE_DET = 7378; // 12
+const static uint64_t SH_FLD_L3_DIR_TYPE = 7379; // 12
+const static uint64_t SH_FLD_L3_DISABLED_CFG = 7380; // 12
+const static uint64_t SH_FLD_L3_DMAP_CI_EN_CFG = 7381; // 12
+const static uint64_t SH_FLD_L3_DRAM_ERROR = 7382; // 12
+const static uint64_t SH_FLD_L3_DRAM_POS_WORDLINE_FAIL = 7383; // 12
+const static uint64_t SH_FLD_L3_DW = 7384; // 12
+const static uint64_t SH_FLD_L3_DW_LEN = 7385; // 12
+const static uint64_t SH_FLD_L3_EDRAM_ENABLE = 7386; // 43
+const static uint64_t SH_FLD_L3_HANG_POLL_PULSE_DIV = 7387; // 12
+const static uint64_t SH_FLD_L3_HANG_POLL_PULSE_DIV_LEN = 7388; // 12
+const static uint64_t SH_FLD_L3_HW_CONTROL_ERR = 7389; // 12
+const static uint64_t SH_FLD_L3_IS_ECO_CFG = 7390; // 12
+const static uint64_t SH_FLD_L3_LCO_ADDR_TGT_ENABLE = 7391; // 12
+const static uint64_t SH_FLD_L3_LCO_ENABLE_CFG = 7392; // 12
+const static uint64_t SH_FLD_L3_LCO_HASH_GLOBAL_DIS = 7393; // 12
+const static uint64_t SH_FLD_L3_LCO_RTY_LIMIT_DISABLE = 7394; // 12
+const static uint64_t SH_FLD_L3_LCO_TARGET_GROUP = 7395; // 12
+const static uint64_t SH_FLD_L3_LCO_TARGET_ID = 7396; // 12
+const static uint64_t SH_FLD_L3_LCO_TARGET_ID_LEN = 7397; // 12
+const static uint64_t SH_FLD_L3_LCO_TARGET_VICTIMS = 7398; // 12
+const static uint64_t SH_FLD_L3_LCO_TARGET_VICTIMS_LEN = 7399; // 12
+const static uint64_t SH_FLD_L3_LEN = 7400; // 24
+const static uint64_t SH_FLD_L3_LINE_DEL_CE_DONE = 7401; // 12
+const static uint64_t SH_FLD_L3_LINE_DEL_ON_ALL_CE = 7402; // 24
+const static uint64_t SH_FLD_L3_LINE_DEL_ON_NEXT_CE = 7403; // 24
+const static uint64_t SH_FLD_L3_LRU_ERROR = 7404; // 12
+const static uint64_t SH_FLD_L3_LRU_INVAL_CNT = 7405; // 12
+const static uint64_t SH_FLD_L3_MACH_HANG_DETECTED = 7406; // 12
+const static uint64_t SH_FLD_L3_MEMBER = 7407; // 24
+const static uint64_t SH_FLD_L3_MEMBER_LEN = 7408; // 24
+const static uint64_t SH_FLD_L3_NO_ALLOCATE_ACTIVE = 7409; // 12
+const static uint64_t SH_FLD_L3_NO_ALLOCATE_EN = 7410; // 12
+const static uint64_t SH_FLD_L3_PF_CRESP_ADDR_ERR = 7411; // 12
+const static uint64_t SH_FLD_L3_PPE_RD_CE_DET = 7412; // 12
+const static uint64_t SH_FLD_L3_PPE_RD_SUE_DET = 7413; // 12
+const static uint64_t SH_FLD_L3_PPE_RD_UE_DET = 7414; // 12
+const static uint64_t SH_FLD_L3_RA = 7415; // 12
+const static uint64_t SH_FLD_L3_RA_LEN = 7416; // 12
+const static uint64_t SH_FLD_L3_RDSN_LINEDEL_UE_EN = 7417; // 12
+const static uint64_t SH_FLD_L3_REFRESH_TIMER_ERROR = 7418; // 12
+const static uint64_t SH_FLD_L3_REQ = 7419; // 36
+const static uint64_t SH_FLD_L3_SCOM_FENCE_LVL = 7420; // 12
+const static uint64_t SH_FLD_L3_SCOM_INIT = 7421; // 12
+const static uint64_t SH_FLD_L3_SCOM_QUIESCE_CACHE = 7422; // 12
+const static uint64_t SH_FLD_L3_SCOM_QUIESCE_CACHE_LFSR = 7423; // 12
+const static uint64_t SH_FLD_L3_SCOM_QUIESCE_REFRESH = 7424; // 12
+const static uint64_t SH_FLD_L3_SINGLE_CAC = 7425; // 12
+const static uint64_t SH_FLD_L3_SINGLE_DIR = 7426; // 12
+const static uint64_t SH_FLD_L3_SINGLE_LRU = 7427; // 12
+const static uint64_t SH_FLD_L3_SNOOP_SW_ERR_DETECTED = 7428; // 12
+const static uint64_t SH_FLD_L3_SOLID_CAC = 7429; // 12
+const static uint64_t SH_FLD_L3_SOLID_DIR = 7430; // 12
+const static uint64_t SH_FLD_L3_SOLID_LRU = 7431; // 12
+const static uint64_t SH_FLD_L3_SPARE3 = 7432; // 12
+const static uint64_t SH_FLD_L3_SPARE5 = 7433; // 12
+const static uint64_t SH_FLD_L3_SPARE7 = 7434; // 12
+const static uint64_t SH_FLD_L3_STOPPED = 7435; // 1
+const static uint64_t SH_FLD_L3_STOPPED_LEN = 7436; // 1
+const static uint64_t SH_FLD_L3_SYSMAP_SM_NOT_LG_SEL = 7437; // 12
+const static uint64_t SH_FLD_L3_TIMER_DIVIDE = 7438; // 12
+const static uint64_t SH_FLD_L3_TIMER_DIVIDE_LEN = 7439; // 12
+const static uint64_t SH_FLD_L3_TTYPE = 7440; // 24
+const static uint64_t SH_FLD_L3_TTYPE_LEN = 7441; // 24
+const static uint64_t SH_FLD_L3_UTIL_MON_BITS = 7442; // 12
+const static uint64_t SH_FLD_L3_UTIL_MON_BITS_LEN = 7443; // 12
+const static uint64_t SH_FLD_L3_VAL = 7444; // 12
+const static uint64_t SH_FLD_LANE0_DISABLED = 7445; // 4
+const static uint64_t SH_FLD_LANE_ANA_PDWN = 7446; // 120
+const static uint64_t SH_FLD_LANE_BAD_VEC_0_15 = 7447; // 4
+const static uint64_t SH_FLD_LANE_BAD_VEC_0_15_LEN = 7448; // 4
+const static uint64_t SH_FLD_LANE_BAD_VEC_16_23 = 7449; // 4
+const static uint64_t SH_FLD_LANE_BAD_VEC_16_23_LEN = 7450; // 4
+const static uint64_t SH_FLD_LANE_BIST_ACTVITY_DET = 7451; // 116
+const static uint64_t SH_FLD_LANE_BIST_ERR = 7452; // 116
+const static uint64_t SH_FLD_LANE_DIG_PDWN = 7453; // 120
+const static uint64_t SH_FLD_LANE_DISABLED_VEC_0_15 = 7454; // 6
+const static uint64_t SH_FLD_LANE_DISABLED_VEC_0_15_LEN = 7455; // 6
+const static uint64_t SH_FLD_LANE_DISABLED_VEC_16_23 = 7456; // 6
+const static uint64_t SH_FLD_LANE_DISABLED_VEC_16_23_LEN = 7457; // 6
+const static uint64_t SH_FLD_LANE_INVALID = 7458; // 72
+const static uint64_t SH_FLD_LANE_INVERT = 7459; // 190
+const static uint64_t SH_FLD_LANE_PDWN = 7460; // 116
+const static uint64_t SH_FLD_LANE_QUIESCE = 7461; // 117
+const static uint64_t SH_FLD_LANE_QUIESCE_LEN = 7462; // 117
+const static uint64_t SH_FLD_LANE_SCRAMBLE_DISABLE = 7463; // 140
+const static uint64_t SH_FLD_LANE_SWAPPED_VEC_0_15 = 7464; // 4
+const static uint64_t SH_FLD_LANE_SWAPPED_VEC_0_15_LEN = 7465; // 4
+const static uint64_t SH_FLD_LANE_SWAPPED_VEC_16_23 = 7466; // 4
+const static uint64_t SH_FLD_LANE_SWAPPED_VEC_16_23_LEN = 7467; // 4
+const static uint64_t SH_FLD_LAST_BANK = 7468; // 90
+const static uint64_t SH_FLD_LAST_BANK_LEN = 7469; // 90
+const static uint64_t SH_FLD_LAST_BANK_VALID = 7470; // 90
+const static uint64_t SH_FLD_LAST_OPCG_MODE = 7471; // 43
+const static uint64_t SH_FLD_LAST_OPCG_MODE_LEN = 7472; // 43
+const static uint64_t SH_FLD_LATE_LAUNCH_PRIMARY = 7473; // 1
+const static uint64_t SH_FLD_LATE_LAUNCH_SECONDARY = 7474; // 1
+const static uint64_t SH_FLD_LBIST = 7475; // 43
+const static uint64_t SH_FLD_LBIST_SKITTER_CTL = 7476; // 43
+const static uint64_t SH_FLD_LBS_IDX0_SEL = 7477; // 1
+const static uint64_t SH_FLD_LBUS_CLOCK_DIVIDER = 7478; // 2
+const static uint64_t SH_FLD_LBUS_CLOCK_DIVIDER_LEN = 7479; // 2
+const static uint64_t SH_FLD_LBUS_PARITY_ERR1_0 = 7480; // 12
+const static uint64_t SH_FLD_LBUS_PARITY_ERR1_1 = 7481; // 12
+const static uint64_t SH_FLD_LBUS_PARITY_ERR1_2 = 7482; // 12
+const static uint64_t SH_FLD_LBUS_PARITY_ERR1_3 = 7483; // 12
+const static uint64_t SH_FLD_LBUS_PARITY_ERROR_0 = 7484; // 2
+const static uint64_t SH_FLD_LBUS_PARITY_ERROR_1 = 7485; // 2
+const static uint64_t SH_FLD_LBUS_PARITY_ERROR_2 = 7486; // 2
+const static uint64_t SH_FLD_LBUS_PARITY_ERROR_3 = 7487; // 2
+const static uint64_t SH_FLD_LCK_STATUS_PARITY_ERROR = 7488; // 3
+const static uint64_t SH_FLD_LD = 7489; // 96
+const static uint64_t SH_FLD_LDQ_EQD_MAX_0_4 = 7490; // 1
+const static uint64_t SH_FLD_LDQ_EQD_MAX_0_4_LEN = 7491; // 1
+const static uint64_t SH_FLD_LDQ_EQD_MIN_0_4 = 7492; // 1
+const static uint64_t SH_FLD_LDQ_EQD_MIN_0_4_LEN = 7493; // 1
+const static uint64_t SH_FLD_LDQ_FSM_PERR = 7494; // 1
+const static uint64_t SH_FLD_LDQ_IVE_MAX_0_4 = 7495; // 1
+const static uint64_t SH_FLD_LDQ_IVE_MAX_0_4_LEN = 7496; // 1
+const static uint64_t SH_FLD_LDQ_IVE_MIN_0_4 = 7497; // 1
+const static uint64_t SH_FLD_LDQ_IVE_MIN_0_4_LEN = 7498; // 1
+const static uint64_t SH_FLD_LDQ_REG_MAX_0_4 = 7499; // 1
+const static uint64_t SH_FLD_LDQ_REG_MAX_0_4_LEN = 7500; // 1
+const static uint64_t SH_FLD_LDQ_REG_MIN_0_4 = 7501; // 1
+const static uint64_t SH_FLD_LDQ_REG_MIN_0_4_LEN = 7502; // 1
+const static uint64_t SH_FLD_LDQ_REG_ORDER_ALL = 7503; // 1
+const static uint64_t SH_FLD_LDQ_THR_MAX_0_4 = 7504; // 1
+const static uint64_t SH_FLD_LDQ_THR_MAX_0_4_LEN = 7505; // 1
+const static uint64_t SH_FLD_LDQ_THR_MIN_0_4 = 7506; // 1
+const static uint64_t SH_FLD_LDQ_THR_MIN_0_4_LEN = 7507; // 1
+const static uint64_t SH_FLD_LDQ_VPC_MAX_0_4 = 7508; // 1
+const static uint64_t SH_FLD_LDQ_VPC_MAX_0_4_LEN = 7509; // 1
+const static uint64_t SH_FLD_LDQ_VPC_MIN_0_4 = 7510; // 1
+const static uint64_t SH_FLD_LDQ_VPC_MIN_0_4_LEN = 7511; // 1
+const static uint64_t SH_FLD_LD_ACK_DEAD = 7512; // 12
+const static uint64_t SH_FLD_LD_ADDR_ERR = 7513; // 24
+const static uint64_t SH_FLD_LD_CLASS_CMD_ADDR_ERR = 7514; // 4
+const static uint64_t SH_FLD_LD_CLASS_CMD_FOREIGN_LINK_FAIL = 7515; // 4
+const static uint64_t SH_FLD_LD_FOREIGN0_ACK_DEAD = 7516; // 12
+const static uint64_t SH_FLD_LD_FOREIGN1_ACK_DEAD = 7517; // 12
+const static uint64_t SH_FLD_LD_UNLD_DLY = 7518; // 1
+const static uint64_t SH_FLD_LD_UNLD_DLY_LEN = 7519; // 1
+const static uint64_t SH_FLD_LENGTH_IN_BYTES_0 = 7520; // 1
+const static uint64_t SH_FLD_LENGTH_IN_BYTES_0_LEN = 7521; // 1
+const static uint64_t SH_FLD_LENGTH_IN_BYTES_1 = 7522; // 1
+const static uint64_t SH_FLD_LENGTH_IN_BYTES_1_LEN = 7523; // 1
+const static uint64_t SH_FLD_LENGTH_IN_BYTES_2 = 7524; // 1
+const static uint64_t SH_FLD_LENGTH_IN_BYTES_2_LEN = 7525; // 1
+const static uint64_t SH_FLD_LENGTH_IN_BYTES_3 = 7526; // 1
+const static uint64_t SH_FLD_LENGTH_IN_BYTES_3_LEN = 7527; // 1
+const static uint64_t SH_FLD_LEVEL_TRANSITION_RATE_A_N = 7528; // 96
+const static uint64_t SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN = 7529; // 96
+const static uint64_t SH_FLD_LFIR_IN = 7530; // 43
+const static uint64_t SH_FLD_LFIR_IN_LEN = 7531; // 43
+const static uint64_t SH_FLD_LFSR_ARB_MODE = 7532; // 3
+const static uint64_t SH_FLD_LFSR_DIS = 7533; // 1
+const static uint64_t SH_FLD_LFSR_FAIRNESS_MASK = 7534; // 1
+const static uint64_t SH_FLD_LFSR_FAIRNESS_MASK_LEN = 7535; // 1
+const static uint64_t SH_FLD_LIMIT = 7536; // 2
+const static uint64_t SH_FLD_LIMIT_LEN = 7537; // 2
+const static uint64_t SH_FLD_LINEAR_WINDOW_BAR = 7538; // 4
+const static uint64_t SH_FLD_LINEAR_WINDOW_BAR_LEN = 7539; // 4
+const static uint64_t SH_FLD_LINEAR_WINDOW_BASE = 7540; // 4
+const static uint64_t SH_FLD_LINEAR_WINDOW_BASE_LEN = 7541; // 4
+const static uint64_t SH_FLD_LINEAR_WINDOW_ENABLE = 7542; // 4
+const static uint64_t SH_FLD_LINEAR_WINDOW_MASK = 7543; // 4
+const static uint64_t SH_FLD_LINEAR_WINDOW_MASK_LEN = 7544; // 4
+const static uint64_t SH_FLD_LINEAR_WINDOW_REGION = 7545; // 4
+const static uint64_t SH_FLD_LINEAR_WINDOW_REGION_LEN = 7546; // 4
+const static uint64_t SH_FLD_LINEAR_WINDOW_SCRESP = 7547; // 4
+const static uint64_t SH_FLD_LINEAR_WINDOW_SCRESP_LEN = 7548; // 4
+const static uint64_t SH_FLD_LINK00_HI = 7549; // 2
+const static uint64_t SH_FLD_LINK00_HI_LEN = 7550; // 2
+const static uint64_t SH_FLD_LINK00_LO = 7551; // 2
+const static uint64_t SH_FLD_LINK00_LO_LEN = 7552; // 2
+const static uint64_t SH_FLD_LINK01_CAPP_MODE = 7553; // 1
+const static uint64_t SH_FLD_LINK01_DIB_VC_LIMIT = 7554; // 2
+const static uint64_t SH_FLD_LINK01_DIB_VC_LIMIT_LEN = 7555; // 2
+const static uint64_t SH_FLD_LINK01_HI = 7556; // 2
+const static uint64_t SH_FLD_LINK01_HI_LEN = 7557; // 2
+const static uint64_t SH_FLD_LINK01_HRB_INIT_STATE = 7558; // 1
+const static uint64_t SH_FLD_LINK01_LO = 7559; // 2
+const static uint64_t SH_FLD_LINK01_LO_LEN = 7560; // 2
+const static uint64_t SH_FLD_LINK02_HI = 7561; // 2
+const static uint64_t SH_FLD_LINK02_HI_LEN = 7562; // 2
+const static uint64_t SH_FLD_LINK02_LO = 7563; // 2
+const static uint64_t SH_FLD_LINK02_LO_LEN = 7564; // 2
+const static uint64_t SH_FLD_LINK03_HI = 7565; // 2
+const static uint64_t SH_FLD_LINK03_HI_LEN = 7566; // 2
+const static uint64_t SH_FLD_LINK03_LO = 7567; // 2
+const static uint64_t SH_FLD_LINK03_LO_LEN = 7568; // 2
+const static uint64_t SH_FLD_LINK04_HI = 7569; // 2
+const static uint64_t SH_FLD_LINK04_HI_LEN = 7570; // 2
+const static uint64_t SH_FLD_LINK04_LO = 7571; // 2
+const static uint64_t SH_FLD_LINK04_LO_LEN = 7572; // 2
+const static uint64_t SH_FLD_LINK05_HI = 7573; // 2
+const static uint64_t SH_FLD_LINK05_HI_LEN = 7574; // 2
+const static uint64_t SH_FLD_LINK05_LO = 7575; // 2
+const static uint64_t SH_FLD_LINK05_LO_LEN = 7576; // 2
+const static uint64_t SH_FLD_LINK06_HI = 7577; // 1
+const static uint64_t SH_FLD_LINK06_HI_LEN = 7578; // 1
+const static uint64_t SH_FLD_LINK06_LO = 7579; // 1
+const static uint64_t SH_FLD_LINK06_LO_LEN = 7580; // 1
+const static uint64_t SH_FLD_LINK07_HI = 7581; // 1
+const static uint64_t SH_FLD_LINK07_HI_LEN = 7582; // 1
+const static uint64_t SH_FLD_LINK07_LO = 7583; // 1
+const static uint64_t SH_FLD_LINK07_LO_LEN = 7584; // 1
+const static uint64_t SH_FLD_LINK0_DOB_LIMIT = 7585; // 1
+const static uint64_t SH_FLD_LINK0_DOB_LIMIT_LEN = 7586; // 1
+const static uint64_t SH_FLD_LINK0_DOB_VC0_LIMIT = 7587; // 2
+const static uint64_t SH_FLD_LINK0_DOB_VC0_LIMIT_LEN = 7588; // 2
+const static uint64_t SH_FLD_LINK0_DOB_VC1_LIMIT = 7589; // 2
+const static uint64_t SH_FLD_LINK0_DOB_VC1_LIMIT_LEN = 7590; // 2
+const static uint64_t SH_FLD_LINK0_SPARE = 7591; // 1
+const static uint64_t SH_FLD_LINK0_SPARE_LEN = 7592; // 1
+const static uint64_t SH_FLD_LINK1_DOB_LIMIT = 7593; // 1
+const static uint64_t SH_FLD_LINK1_DOB_LIMIT_LEN = 7594; // 1
+const static uint64_t SH_FLD_LINK1_DOB_VC0_LIMIT = 7595; // 2
+const static uint64_t SH_FLD_LINK1_DOB_VC0_LIMIT_LEN = 7596; // 2
+const static uint64_t SH_FLD_LINK1_DOB_VC1_LIMIT = 7597; // 2
+const static uint64_t SH_FLD_LINK1_DOB_VC1_LIMIT_LEN = 7598; // 2
+const static uint64_t SH_FLD_LINK1_SPARE = 7599; // 1
+const static uint64_t SH_FLD_LINK1_SPARE_LEN = 7600; // 1
+const static uint64_t SH_FLD_LINK23_DIB_VC_LIMIT = 7601; // 2
+const static uint64_t SH_FLD_LINK23_DIB_VC_LIMIT_LEN = 7602; // 2
+const static uint64_t SH_FLD_LINK2_DOB_LIMIT = 7603; // 2
+const static uint64_t SH_FLD_LINK2_DOB_LIMIT_LEN = 7604; // 2
+const static uint64_t SH_FLD_LINK2_DOB_VC0_LIMIT = 7605; // 2
+const static uint64_t SH_FLD_LINK2_DOB_VC0_LIMIT_LEN = 7606; // 2
+const static uint64_t SH_FLD_LINK2_DOB_VC1_LIMIT = 7607; // 2
+const static uint64_t SH_FLD_LINK2_DOB_VC1_LIMIT_LEN = 7608; // 2
+const static uint64_t SH_FLD_LINK3_DOB_LIMIT = 7609; // 2
+const static uint64_t SH_FLD_LINK3_DOB_LIMIT_LEN = 7610; // 2
+const static uint64_t SH_FLD_LINK3_DOB_VC0_LIMIT = 7611; // 2
+const static uint64_t SH_FLD_LINK3_DOB_VC0_LIMIT_LEN = 7612; // 2
+const static uint64_t SH_FLD_LINK3_DOB_VC1_LIMIT = 7613; // 2
+const static uint64_t SH_FLD_LINK3_DOB_VC1_LIMIT_LEN = 7614; // 2
+const static uint64_t SH_FLD_LINK45_DIB_VC_LIMIT = 7615; // 2
+const static uint64_t SH_FLD_LINK45_DIB_VC_LIMIT_LEN = 7616; // 2
+const static uint64_t SH_FLD_LINK4_DOB_LIMIT = 7617; // 2
+const static uint64_t SH_FLD_LINK4_DOB_LIMIT_LEN = 7618; // 2
+const static uint64_t SH_FLD_LINK4_DOB_VC0_LIMIT = 7619; // 2
+const static uint64_t SH_FLD_LINK4_DOB_VC0_LIMIT_LEN = 7620; // 2
+const static uint64_t SH_FLD_LINK4_DOB_VC1_LIMIT = 7621; // 2
+const static uint64_t SH_FLD_LINK4_DOB_VC1_LIMIT_LEN = 7622; // 2
+const static uint64_t SH_FLD_LINK5_DOB_LIMIT = 7623; // 2
+const static uint64_t SH_FLD_LINK5_DOB_LIMIT_LEN = 7624; // 2
+const static uint64_t SH_FLD_LINK5_DOB_VC0_LIMIT = 7625; // 2
+const static uint64_t SH_FLD_LINK5_DOB_VC0_LIMIT_LEN = 7626; // 2
+const static uint64_t SH_FLD_LINK5_DOB_VC1_LIMIT = 7627; // 2
+const static uint64_t SH_FLD_LINK5_DOB_VC1_LIMIT_LEN = 7628; // 2
+const static uint64_t SH_FLD_LINK67_CAPP_MODE = 7629; // 1
+const static uint64_t SH_FLD_LINK67_DIB_VC_LIMIT = 7630; // 1
+const static uint64_t SH_FLD_LINK67_DIB_VC_LIMIT_LEN = 7631; // 1
+const static uint64_t SH_FLD_LINK67_HRB_INIT_STATE = 7632; // 1
+const static uint64_t SH_FLD_LINK6_DOB_VC0_LIMIT = 7633; // 1
+const static uint64_t SH_FLD_LINK6_DOB_VC0_LIMIT_LEN = 7634; // 1
+const static uint64_t SH_FLD_LINK6_DOB_VC1_LIMIT = 7635; // 1
+const static uint64_t SH_FLD_LINK6_DOB_VC1_LIMIT_LEN = 7636; // 1
+const static uint64_t SH_FLD_LINK6_SPARE = 7637; // 1
+const static uint64_t SH_FLD_LINK6_SPARE_LEN = 7638; // 1
+const static uint64_t SH_FLD_LINK7_DOB_VC0_LIMIT = 7639; // 1
+const static uint64_t SH_FLD_LINK7_DOB_VC0_LIMIT_LEN = 7640; // 1
+const static uint64_t SH_FLD_LINK7_DOB_VC1_LIMIT = 7641; // 1
+const static uint64_t SH_FLD_LINK7_DOB_VC1_LIMIT_LEN = 7642; // 1
+const static uint64_t SH_FLD_LINK7_SPARE = 7643; // 1
+const static uint64_t SH_FLD_LINK7_SPARE_LEN = 7644; // 1
+const static uint64_t SH_FLD_LINKS01_TOD_ENABLE = 7645; // 1
+const static uint64_t SH_FLD_LINKS23_TOD_ENABLE = 7646; // 1
+const static uint64_t SH_FLD_LINKS45_TOD_ENABLE = 7647; // 1
+const static uint64_t SH_FLD_LINKS67_TOD_ENABLE = 7648; // 1
+const static uint64_t SH_FLD_LINK_AVP_MODE = 7649; // 2
+const static uint64_t SH_FLD_LINUX_TRIG_MODE = 7650; // 1
+const static uint64_t SH_FLD_LISTEN_TO_PULSE_DIS = 7651; // 43
+const static uint64_t SH_FLD_LO = 7652; // 1
+const static uint64_t SH_FLD_LOCALITY_4_ACCESS = 7653; // 1
+const static uint64_t SH_FLD_LOCAL_HIGH_PRIORITY = 7654; // 4
+const static uint64_t SH_FLD_LOCAL_HIGH_PRIORITY_LEN = 7655; // 4
+const static uint64_t SH_FLD_LOCAL_LOW_PRIORITY = 7656; // 4
+const static uint64_t SH_FLD_LOCAL_LOW_PRIORITY_LEN = 7657; // 4
+const static uint64_t SH_FLD_LOCAL_NODE_EPSILON = 7658; // 8
+const static uint64_t SH_FLD_LOCAL_NODE_EPSILON_LEN = 7659; // 8
+const static uint64_t SH_FLD_LOCAL_QUIESCE_ACHIEVED = 7660; // 1
+const static uint64_t SH_FLD_LOCK = 7661; // 32
+const static uint64_t SH_FLD_LOCKED_FSM_STATE = 7662; // 1
+const static uint64_t SH_FLD_LOCKED_FSM_STATE_LEN = 7663; // 1
+const static uint64_t SH_FLD_LOCKED_PIBM_ADDR = 7664; // 1
+const static uint64_t SH_FLD_LOCKED_PIBM_ADDR_LEN = 7665; // 1
+const static uint64_t SH_FLD_LOCKED_SEEPROM_ADDRESS = 7666; // 1
+const static uint64_t SH_FLD_LOCKED_SEEPROM_ADDRESS_LEN = 7667; // 1
+const static uint64_t SH_FLD_LOCK_LEN = 7668; // 16
+const static uint64_t SH_FLD_LOCK_PCB_ON_ERR = 7669; // 12
+const static uint64_t SH_FLD_LOCK_SEL = 7670; // 6
+const static uint64_t SH_FLD_LOFF_AMP_EN = 7671; // 6
+const static uint64_t SH_FLD_LOG = 7672; // 1
+const static uint64_t SH_FLD_LOG_LEN = 7673; // 1
+const static uint64_t SH_FLD_LOOP_BREAK_MODE = 7674; // 64
+const static uint64_t SH_FLD_LOOP_BREAK_MODE_LEN = 7675; // 64
+const static uint64_t SH_FLD_LOOP_COUNT = 7676; // 43
+const static uint64_t SH_FLD_LOOP_COUNT_LEN = 7677; // 43
+const static uint64_t SH_FLD_LOW = 7678; // 1
+const static uint64_t SH_FLD_LOW_IDLE_COUNT = 7679; // 8
+const static uint64_t SH_FLD_LOW_IDLE_COUNT_LEN = 7680; // 8
+const static uint64_t SH_FLD_LOW_IDLE_THRESHOLD = 7681; // 8
+const static uint64_t SH_FLD_LOW_IDLE_THRESHOLD_LEN = 7682; // 8
+const static uint64_t SH_FLD_LOW_LATENCY = 7683; // 8
+const static uint64_t SH_FLD_LOW_LEN = 7684; // 1
+const static uint64_t SH_FLD_LOW_ORDER_STEP_VALUE = 7685; // 1
+const static uint64_t SH_FLD_LOW_ORDER_STEP_VALUE_LEN = 7686; // 1
+const static uint64_t SH_FLD_LPC_MODE = 7687; // 2
+const static uint64_t SH_FLD_LPC_MODE_LEN = 7688; // 2
+const static uint64_t SH_FLD_LPID = 7689; // 9
+const static uint64_t SH_FLD_LPID_LEN = 7690; // 9
+const static uint64_t SH_FLD_LPID_MASK = 7691; // 1
+const static uint64_t SH_FLD_LPID_MASK_LEN = 7692; // 1
+const static uint64_t SH_FLD_LP_CNT_THRESH = 7693; // 6
+const static uint64_t SH_FLD_LP_CNT_THRESH_LEN = 7694; // 6
+const static uint64_t SH_FLD_LP_MAX_CRED_THRESH = 7695; // 6
+const static uint64_t SH_FLD_LP_MAX_CRED_THRESH_LEN = 7696; // 6
+const static uint64_t SH_FLD_LP_MIN_CRED_THRESH = 7697; // 6
+const static uint64_t SH_FLD_LP_MIN_CRED_THRESH_LEN = 7698; // 6
+const static uint64_t SH_FLD_LP_MODE_ENABLE = 7699; // 6
+const static uint64_t SH_FLD_LP_ONLY_MODE = 7700; // 6
+const static uint64_t SH_FLD_LP_TIMER_TICK_CONFIG = 7701; // 6
+const static uint64_t SH_FLD_LP_TIMER_TICK_CONFIG_LEN = 7702; // 6
+const static uint64_t SH_FLD_LRDIMM = 7703; // 2
+const static uint64_t SH_FLD_LRDIMM_CONTEXT = 7704; // 8
+const static uint64_t SH_FLD_LRDIMM_LEN = 7705; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD1 = 7706; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD10 = 7707; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD10_LEN = 7708; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD11 = 7709; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD11_LEN = 7710; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD12 = 7711; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD12_LEN = 7712; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD13 = 7713; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD13_LEN = 7714; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD14 = 7715; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD14_LEN = 7716; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD15 = 7717; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD15_LEN = 7718; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD1_LEN = 7719; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD2 = 7720; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD2_LEN = 7721; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD3 = 7722; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD3_LEN = 7723; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD4 = 7724; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD4_LEN = 7725; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD5 = 7726; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD5_LEN = 7727; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD6 = 7728; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD6_LEN = 7729; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD7 = 7730; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD7_LEN = 7731; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD8 = 7732; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD8_LEN = 7733; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD9 = 7734; // 2
+const static uint64_t SH_FLD_LRDIMM_WORD9_LEN = 7735; // 2
+const static uint64_t SH_FLD_LRU_ALL_MEMBERS_IN_CGC_ARE_LINE_DELETED =
+    7736; // 12
+const static uint64_t SH_FLD_LRU_READ_ERROR_DETECTED = 7737; // 12
+const static uint64_t SH_FLD_LTE_EN = 7738; // 4
+const static uint64_t SH_FLD_LVDIR_EN = 7739; // 12
+const static uint64_t SH_FLD_LVDIR_PERR = 7740; // 12
+const static uint64_t SH_FLD_LVLTRANS_FENCE = 7741; // 43
+const static uint64_t SH_FLD_M = 7742; // 1
+const static uint64_t SH_FLD_M0_BIT_MAP = 7743; // 8
+const static uint64_t SH_FLD_M0_BIT_MAP_LEN = 7744; // 8
+const static uint64_t SH_FLD_M0_PRIORITY = 7745; // 1
+const static uint64_t SH_FLD_M0_PRIORITY_LEN = 7746; // 1
+const static uint64_t SH_FLD_M0_PRIORITY_SEL = 7747; // 1
+const static uint64_t SH_FLD_M1HC0A = 7748; // 1
+const static uint64_t SH_FLD_M1HC0A_LEN = 7749; // 1
+const static uint64_t SH_FLD_M1HC0B = 7750; // 1
+const static uint64_t SH_FLD_M1HC0B_LEN = 7751; // 1
+const static uint64_t SH_FLD_M1HC1A = 7752; // 1
+const static uint64_t SH_FLD_M1HC1A_LEN = 7753; // 1
+const static uint64_t SH_FLD_M1HC1B = 7754; // 1
+const static uint64_t SH_FLD_M1HC1B_LEN = 7755; // 1
+const static uint64_t SH_FLD_M1HC2A = 7756; // 1
+const static uint64_t SH_FLD_M1HC2A_LEN = 7757; // 1
+const static uint64_t SH_FLD_M1HC2B = 7758; // 1
+const static uint64_t SH_FLD_M1HC2B_LEN = 7759; // 1
+const static uint64_t SH_FLD_M1SASIM1_ENABLE_PIB_ERROR = 7760; // 1
+const static uint64_t SH_FLD_M1SASIM1_ENABLE_PIB_PENDING = 7761; // 1
+const static uint64_t SH_FLD_M1SASIM1_ENABLE_XUP = 7762; // 1
+const static uint64_t SH_FLD_M1_BIT_MAP = 7763; // 8
+const static uint64_t SH_FLD_M1_BIT_MAP_LEN = 7764; // 8
+const static uint64_t SH_FLD_M1_PRIORITY = 7765; // 1
+const static uint64_t SH_FLD_M1_PRIORITY_LEN = 7766; // 1
+const static uint64_t SH_FLD_M1_PRIORITY_SEL = 7767; // 1
+const static uint64_t SH_FLD_M2HC0A = 7768; // 1
+const static uint64_t SH_FLD_M2HC0A_LEN = 7769; // 1
+const static uint64_t SH_FLD_M2HC0B = 7770; // 1
+const static uint64_t SH_FLD_M2HC0B_LEN = 7771; // 1
+const static uint64_t SH_FLD_M2HC1A = 7772; // 1
+const static uint64_t SH_FLD_M2HC1A_LEN = 7773; // 1
+const static uint64_t SH_FLD_M2HC1B = 7774; // 1
+const static uint64_t SH_FLD_M2HC1B_LEN = 7775; // 1
+const static uint64_t SH_FLD_M2HC2A = 7776; // 1
+const static uint64_t SH_FLD_M2HC2A_LEN = 7777; // 1
+const static uint64_t SH_FLD_M2HC2B = 7778; // 1
+const static uint64_t SH_FLD_M2HC2B_LEN = 7779; // 1
+const static uint64_t SH_FLD_M2_PRIORITY = 7780; // 1
+const static uint64_t SH_FLD_M2_PRIORITY_LEN = 7781; // 1
+const static uint64_t SH_FLD_M2_PRIORITY_SEL = 7782; // 1
+const static uint64_t SH_FLD_M3_PRIORITY = 7783; // 1
+const static uint64_t SH_FLD_M3_PRIORITY_LEN = 7784; // 1
+const static uint64_t SH_FLD_M3_PRIORITY_SEL = 7785; // 1
+const static uint64_t SH_FLD_M4_PRIORITY = 7786; // 1
+const static uint64_t SH_FLD_M4_PRIORITY_LEN = 7787; // 1
+const static uint64_t SH_FLD_M5_PRIORITY = 7788; // 1
+const static uint64_t SH_FLD_M5_PRIORITY_LEN = 7789; // 1
+const static uint64_t SH_FLD_M5_PRIORITY_SEL = 7790; // 1
+const static uint64_t SH_FLD_M6_PRIORITY = 7791; // 1
+const static uint64_t SH_FLD_M6_PRIORITY_LEN = 7792; // 1
+const static uint64_t SH_FLD_M7_PRIORITY = 7793; // 1
+const static uint64_t SH_FLD_M7_PRIORITY_LEN = 7794; // 1
+const static uint64_t SH_FLD_M7_PRIORITY_SEL = 7795; // 1
+const static uint64_t SH_FLD_MAGIC_COOKIE = 7796; // 1
+const static uint64_t SH_FLD_MAGIC_COOKIE_LEN = 7797; // 1
+const static uint64_t SH_FLD_MAINLINE_AUE = 7798; // 8
+const static uint64_t SH_FLD_MAINLINE_IAUE = 7799; // 8
+const static uint64_t SH_FLD_MAINLINE_IMPE = 7800; // 8
+const static uint64_t SH_FLD_MAINLINE_IRCD = 7801; // 8
+const static uint64_t SH_FLD_MAINLINE_IUE = 7802; // 8
+const static uint64_t SH_FLD_MAINLINE_MCE = 7803; // 8
+const static uint64_t SH_FLD_MAINLINE_MPE_RANK_0_TO_7 = 7804; // 8
+const static uint64_t SH_FLD_MAINLINE_MPE_RANK_0_TO_7_LEN = 7805; // 8
+const static uint64_t SH_FLD_MAINLINE_NCE = 7806; // 8
+const static uint64_t SH_FLD_MAINLINE_RCD = 7807; // 8
+const static uint64_t SH_FLD_MAINLINE_SCE = 7808; // 8
+const static uint64_t SH_FLD_MAINLINE_SUE = 7809; // 8
+const static uint64_t SH_FLD_MAINLINE_TCE = 7810; // 8
+const static uint64_t SH_FLD_MAINLINE_UE = 7811; // 8
+const static uint64_t SH_FLD_MAINTENANCE_AUE = 7812; // 8
+const static uint64_t SH_FLD_MAINTENANCE_IAUE = 7813; // 8
+const static uint64_t SH_FLD_MAINTENANCE_IMPE = 7814; // 8
+const static uint64_t SH_FLD_MAINTENANCE_IRCD = 7815; // 8
+const static uint64_t SH_FLD_MAINTENANCE_IUE = 7816; // 8
+const static uint64_t SH_FLD_MAINTENANCE_MCE = 7817; // 8
+const static uint64_t SH_FLD_MAINTENANCE_MPE_RANK_0_TO_7 = 7818; // 8
+const static uint64_t SH_FLD_MAINTENANCE_MPE_RANK_0_TO_7_LEN = 7819; // 8
+const static uint64_t SH_FLD_MAINTENANCE_NCE = 7820; // 8
+const static uint64_t SH_FLD_MAINTENANCE_RCD = 7821; // 8
+const static uint64_t SH_FLD_MAINTENANCE_SCE = 7822; // 8
+const static uint64_t SH_FLD_MAINTENANCE_SUE = 7823; // 8
+const static uint64_t SH_FLD_MAINTENANCE_TCE = 7824; // 8
+const static uint64_t SH_FLD_MAINTENANCE_UE = 7825; // 8
+const static uint64_t SH_FLD_MAINT_CCS_PE = 7826; // 2
+const static uint64_t SH_FLD_MAINT_CMD_IP = 7827; // 2
+const static uint64_t SH_FLD_MAINT_CMD_START = 7828; // 2
+const static uint64_t SH_FLD_MAINT_CMD_STOP = 7829; // 2
+const static uint64_t SH_FLD_MAINT_CMD_TYPE = 7830; // 2
+const static uint64_t SH_FLD_MAINT_CMD_TYPE_LEN = 7831; // 2
+const static uint64_t SH_FLD_MAINT_INTERNAL_FSM_INJ_MODE = 7832; // 2
+const static uint64_t SH_FLD_MAINT_INTERNAL_FSM_INJ_REG = 7833; // 2
+const static uint64_t SH_FLD_MAIN_SLICE_EN_ENC = 7834; // 1
+const static uint64_t SH_FLD_MAIN_SLICE_EN_ENC_LEN = 7835; // 1
+const static uint64_t SH_FLD_MALFUNCTION_ALERT = 7836; // 96
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP0 = 7837; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP0_LEN = 7838; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP1 = 7839; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP10 = 7840; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP10_LEN = 7841; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP11 = 7842; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP11_LEN = 7843; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP12 = 7844; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP12_LEN = 7845; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP13 = 7846; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP13_LEN = 7847; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP14 = 7848; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP14_LEN = 7849; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP15 = 7850; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP15_LEN = 7851; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP1_LEN = 7852; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP2 = 7853; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP2_LEN = 7854; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP3 = 7855; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP3_LEN = 7856; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP4 = 7857; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP4_LEN = 7858; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP5 = 7859; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP5_LEN = 7860; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP6 = 7861; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP6_LEN = 7862; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP7 = 7863; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP7_LEN = 7864; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP8 = 7865; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP8_LEN = 7866; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP9 = 7867; // 1
+const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP9_LEN = 7868; // 1
+const static uint64_t SH_FLD_MANUAL_CLR_PB_STOP = 7869; // 1
+const static uint64_t SH_FLD_MANUAL_PB_SWITCH_ABCD = 7870; // 1
+const static uint64_t SH_FLD_MANUAL_SET_PB_STOP = 7871; // 1
+const static uint64_t SH_FLD_MARGINPD_SEL = 7872; // 6
+const static uint64_t SH_FLD_MARGINPD_SEL_LEN = 7873; // 6
+const static uint64_t SH_FLD_MARGINPU_SEL = 7874; // 6
+const static uint64_t SH_FLD_MARGINPU_SEL_LEN = 7875; // 6
+const static uint64_t SH_FLD_MARK = 7876; // 64
+const static uint64_t SH_FLD_MARK_LEN = 7877; // 64
+const static uint64_t SH_FLD_MASK = 7878; // 13
+const static uint64_t SH_FLD_MASKA = 7879; // 90
+const static uint64_t SH_FLD_MASKA_LEN = 7880; // 90
+const static uint64_t SH_FLD_MASKB = 7881; // 90
+const static uint64_t SH_FLD_MASKB_LEN = 7882; // 90
+const static uint64_t SH_FLD_MASKC = 7883; // 90
+const static uint64_t SH_FLD_MASKC_LEN = 7884; // 90
+const static uint64_t SH_FLD_MASKD = 7885; // 90
+const static uint64_t SH_FLD_MASKD_LEN = 7886; // 90
+const static uint64_t SH_FLD_MASK_AGV_DISABLE_MODE = 7887; // 2
+const static uint64_t SH_FLD_MASK_B = 7888; // 129
+const static uint64_t SH_FLD_MASK_LEN = 7889; // 5
+const static uint64_t SH_FLD_MASK_PURGE_INTERFACE = 7890; // 12
+const static uint64_t SH_FLD_MASK_TOGGLE_ENABLE = 7891; // 1
+const static uint64_t SH_FLD_MASTERID = 7892; // 6
+const static uint64_t SH_FLD_MASTERID_LEN = 7893; // 6
+const static uint64_t SH_FLD_MASTER_ARRAY_CE = 7894; // 4
+const static uint64_t SH_FLD_MASTER_ARRAY_UE = 7895; // 4
+const static uint64_t SH_FLD_MASTER_CP_DATA_POLL_PULSE_DIV = 7896; // 12
+const static uint64_t SH_FLD_MASTER_CP_DATA_POLL_PULSE_DIV_LEN = 7897; // 12
+const static uint64_t SH_FLD_MASTER_ERROR_CODE = 7898; // 1
+const static uint64_t SH_FLD_MASTER_ERROR_CODE_LEN = 7899; // 1
+const static uint64_t SH_FLD_MASTER_IDLE = 7900; // 1
+const static uint64_t SH_FLD_MASTER_MODE = 7901; // 47
+const static uint64_t SH_FLD_MASTER_PD_CNTL = 7902; // 8
+const static uint64_t SH_FLD_MASTER_RECOVERABLE_ERROR = 7903; // 4
+const static uint64_t SH_FLD_MASTER_RESPONSE_BIT = 7904; // 1
+const static uint64_t SH_FLD_MASTER_SYS_XSTOP_ERROR = 7905; // 4
+const static uint64_t SH_FLD_MASTER_TLB_DATA_POLL_PULSE_DIV = 7906; // 12
+const static uint64_t SH_FLD_MASTER_TLB_DATA_POLL_PULSE_DIV_LEN = 7907; // 12
+const static uint64_t SH_FLD_MATCHA_MUXSEL = 7908; // 90
+const static uint64_t SH_FLD_MATCHA_MUXSEL_LEN = 7909; // 90
+const static uint64_t SH_FLD_MATCHB_MUXSEL = 7910; // 90
+const static uint64_t SH_FLD_MATCHB_MUXSEL_LEN = 7911; // 90
+const static uint64_t SH_FLD_MATCHC_MUXSEL = 7912; // 90
+const static uint64_t SH_FLD_MATCHC_MUXSEL_LEN = 7913; // 90
+const static uint64_t SH_FLD_MATCHD_MUXSEL = 7914; // 90
+const static uint64_t SH_FLD_MATCHD_MUXSEL_LEN = 7915; // 90
+const static uint64_t SH_FLD_MATCH_NOT_MODE = 7916; // 90
+const static uint64_t SH_FLD_MATCH_NOT_MODE_LEN = 7917; // 90
+const static uint64_t SH_FLD_MAXCYCLECNT = 7918; // 3
+const static uint64_t SH_FLD_MAXCYCLECNT_LEN = 7919; // 3
+const static uint64_t SH_FLD_MAX_ALL_POLL_BCST_0_4 = 7920; // 1
+const static uint64_t SH_FLD_MAX_ALL_POLL_BCST_0_4_LEN = 7921; // 1
+const static uint64_t SH_FLD_MAX_BAD_LANES = 7922; // 4
+const static uint64_t SH_FLD_MAX_BAD_LANES_LEN = 7923; // 4
+const static uint64_t SH_FLD_MAX_BER_CHECK_COUNT = 7924; // 4
+const static uint64_t SH_FLD_MAX_BER_CHECK_COUNT_LEN = 7925; // 4
+const static uint64_t SH_FLD_MAX_CRD_TO_CQ = 7926; // 6
+const static uint64_t SH_FLD_MAX_CRD_TO_CQ_LEN = 7927; // 6
+const static uint64_t SH_FLD_MAX_CRD_TO_PC = 7928; // 6
+const static uint64_t SH_FLD_MAX_CRD_TO_PC_LEN = 7929; // 6
+const static uint64_t SH_FLD_MAX_CYCLE_SAMPLE = 7930; // 12
+const static uint64_t SH_FLD_MAX_CYCLE_SAMPLE_LEN = 7931; // 12
+const static uint64_t SH_FLD_MAX_ENTRIES_IN_MODIFIED = 7932; // 2
+const static uint64_t SH_FLD_MAX_ENTRIES_IN_MODIFIED_LEN = 7933; // 2
+const static uint64_t SH_FLD_MAX_GRP_POLL_BCST_0_4 = 7934; // 1
+const static uint64_t SH_FLD_MAX_GRP_POLL_BCST_0_4_LEN = 7935; // 1
+const static uint64_t SH_FLD_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS = 7936; // 2
+const static uint64_t SH_FLD_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS_LEN = 7937; // 2
+const static uint64_t SH_FLD_MAX_OUTSTANDING = 7938; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_CI_LOAD = 7939; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_CI_LOAD_LEN = 7940; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_CI_STORE = 7941; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_CI_STORE_LEN = 7942; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_EOI = 7943; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_EOI_LEN = 7944; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_EQD_FETCH = 7945; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_EQD_FETCH_LEN = 7946; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_EQD_WRITE = 7947; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_EQD_WRITE_LEN = 7948; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_EQP = 7949; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_EQP_LEN = 7950; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_ISB_FETCH = 7951; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_ISB_FETCH_LEN = 7952; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_ISB_WRITE = 7953; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_ISB_WRITE_LEN = 7954; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_IVE_FETCH = 7955; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_IVE_FETCH_LEN = 7956; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_LEN = 7957; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_SBC_LOOKUP = 7958; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_SBC_LOOKUP_LEN = 7959; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_SOFT_EOI = 7960; // 1
+const static uint64_t SH_FLD_MAX_OUTSTANDING_SOFT_EOI_LEN = 7961; // 1
+const static uint64_t SH_FLD_MAX_PROMOTE_LEVEL_A_N = 7962; // 96
+const static uint64_t SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN = 7963; // 96
+const static uint64_t SH_FLD_MAX_PTAG_IN_USE = 7964; // 3
+const static uint64_t SH_FLD_MAX_PTAG_IN_USE_LEN = 7965; // 3
+const static uint64_t SH_FLD_MAX_UNLOCK_IN_FIFO = 7966; // 3
+const static uint64_t SH_FLD_MAX_UNLOCK_IN_FIFO_LEN = 7967; // 3
+const static uint64_t SH_FLD_MB00_SPATTN = 7968; // 4
+const static uint64_t SH_FLD_MB01_SPATTN = 7969; // 4
+const static uint64_t SH_FLD_MB10_SPATTN = 7970; // 4
+const static uint64_t SH_FLD_MB11_SPATTN = 7971; // 4
+const static uint64_t SH_FLD_MB20_SPATTN = 7972; // 4
+const static uint64_t SH_FLD_MB21_SPATTN = 7973; // 4
+const static uint64_t SH_FLD_MB30_SPATTN = 7974; // 4
+const static uint64_t SH_FLD_MB31_SPATTN = 7975; // 4
+const static uint64_t SH_FLD_MB40_SPATTN = 7976; // 4
+const static uint64_t SH_FLD_MB41_SPATTN = 7977; // 4
+const static uint64_t SH_FLD_MB50_SPATTN = 7978; // 4
+const static uint64_t SH_FLD_MB51_SPATTN = 7979; // 4
+const static uint64_t SH_FLD_MB60_SPATTN = 7980; // 2
+const static uint64_t SH_FLD_MB61_SPATTN = 7981; // 2
+const static uint64_t SH_FLD_MB70_SPATTN = 7982; // 2
+const static uint64_t SH_FLD_MB71_SPATTN = 7983; // 2
+const static uint64_t SH_FLD_MBABS0_PE = 7984; // 2
+const static uint64_t SH_FLD_MBASE = 7985; // 12
+const static uint64_t SH_FLD_MBASE_LEN = 7986; // 12
+const static uint64_t SH_FLD_MBA_INJQ_CFG_RDTAG_ERR_INJ = 7987; // 8
+const static uint64_t SH_FLD_MBA_INJQ_CFG_RRQ_POP_ERR_INJ = 7988; // 8
+const static uint64_t SH_FLD_MBA_INJQ_CFG_WRD_BUFFER_CE_INJ = 7989; // 8
+const static uint64_t SH_FLD_MBA_INJQ_CFG_WRD_BUFFER_UE_INJ = 7990; // 8
+const static uint64_t SH_FLD_MBA_INJQ_CFG_WRD_BUFF_INJ_MODE = 7991; // 8
+const static uint64_t SH_FLD_MBA_INJQ_CFG_WR_ECC_ERR_INJ = 7992; // 8
+const static uint64_t SH_FLD_MBA_INJQ_CFG_WR_ECC_INJ_MODE = 7993; // 8
+const static uint64_t SH_FLD_MBA_NONRECOVERABLE_ERROR = 7994; // 16
+const static uint64_t SH_FLD_MBA_RECOVERABLE_ERROR = 7995; // 16
+const static uint64_t SH_FLD_MBA_WRD_MODE_CFG_CRC_MODE_EN = 7996; // 8
+const static uint64_t SH_FLD_MBA_WRD_MODE_CFG_CRC_MODE_X8 = 7997; // 8
+const static uint64_t SH_FLD_MBA_WRD_MODE_CFG_MAINT_ECC_CHK_DISABLE = 7998; // 8
+const static uint64_t SH_FLD_MBA_WRD_MODE_CFG_WRD_ECC_CHK_DISABLE = 7999; // 8
+const static uint64_t SH_FLD_MBA_WRD_MODE_CFG_WRD_ECC_COR_DISABLE = 8000; // 8
+const static uint64_t SH_FLD_MBA_WRD_MODE_RESERVED_4 = 8001; // 8
+const static uint64_t SH_FLD_MBMACAQ_PE = 8002; // 2
+const static uint64_t SH_FLD_MBMCCQ_PE = 8003; // 2
+const static uint64_t SH_FLD_MBMCTQ_PE = 8004; // 2
+const static uint64_t SH_FLD_MBOX0 = 8005; // 1
+const static uint64_t SH_FLD_MBOX0_LEN = 8006; // 1
+const static uint64_t SH_FLD_MBOX1 = 8007; // 1
+const static uint64_t SH_FLD_MBOX1_LEN = 8008; // 1
+const static uint64_t SH_FLD_MBOX2 = 8009; // 1
+const static uint64_t SH_FLD_MBOX2_LEN = 8010; // 1
+const static uint64_t SH_FLD_MBOX3 = 8011; // 1
+const static uint64_t SH_FLD_MBOX3_LEN = 8012; // 1
+const static uint64_t SH_FLD_MBOX4 = 8013; // 1
+const static uint64_t SH_FLD_MBOX4_LEN = 8014; // 1
+const static uint64_t SH_FLD_MBOX5 = 8015; // 1
+const static uint64_t SH_FLD_MBOX5_LEN = 8016; // 1
+const static uint64_t SH_FLD_MBOX6 = 8017; // 1
+const static uint64_t SH_FLD_MBOX6_LEN = 8018; // 1
+const static uint64_t SH_FLD_MBOX7 = 8019; // 1
+const static uint64_t SH_FLD_MBOX7_LEN = 8020; // 1
+const static uint64_t SH_FLD_MBRCEICRQ_DATAPATH_PARITY_ERROR_INJECT = 8021; // 8
+const static uint64_t SH_FLD_MBR_DIS = 8022; // 2
+const static uint64_t SH_FLD_MBR_DIS_LEN = 8023; // 2
+const static uint64_t SH_FLD_MBSECCQ_DATA_GENERATOR_META_ENABLE = 8024; // 8
+const static uint64_t SH_FLD_MBSECCQ_DATA_GENERATOR_OVERRIDE = 8025; // 8
+const static uint64_t SH_FLD_MBSECCQ_DATA_INVERSION = 8026; // 8
+const static uint64_t SH_FLD_MBSECCQ_DATA_INVERSION_LEN = 8027; // 8
+const static uint64_t SH_FLD_MBSECCQ_DELAY_NONBYPASS = 8028; // 8
+const static uint64_t SH_FLD_MBSECCQ_DELAY_VALID_1X = 8029; // 8
+const static uint64_t SH_FLD_MBSECCQ_DISABLE_MARK_STORE_WRITE = 8030; // 8
+const static uint64_t SH_FLD_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT =
+    8031; // 8
+const static uint64_t SH_FLD_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT = 8032; // 8
+const static uint64_t SH_FLD_MBSECCQ_DISABLE_UE_RETRY = 8033; // 8
+const static uint64_t SH_FLD_MBSECCQ_ECC_SCHEDULER_DELAY = 8034; // 8
+const static uint64_t SH_FLD_MBSECCQ_ECC_SCHEDULER_DELAY_LEN = 8035; // 8
+const static uint64_t SH_FLD_MBSECCQ_ENABLE_HOST_ATTENTION = 8036; // 8
+const static uint64_t SH_FLD_MBSECCQ_ENABLE_SPECIAL_ATTENTION = 8037; // 8
+const static uint64_t SH_FLD_MBSECCQ_EXIT_OVERRIDE = 8038; // 8
+const static uint64_t SH_FLD_MBSECCQ_EXIT_OVERRIDE_LEN = 8039; // 8
+const static uint64_t SH_FLD_MBSECCQ_INJECT_8B_ECC_ERROR = 8040; // 8
+const static uint64_t SH_FLD_MBSECCQ_INJECT_8B_ECC_ERROR_LEN = 8041; // 8
+const static uint64_t SH_FLD_MBSECCQ_INT_RESET_KEEPER = 8042; // 8
+const static uint64_t SH_FLD_MBSECCQ_ITAG_METADATA_ENABLE = 8043; // 8
+const static uint64_t SH_FLD_MBSECCQ_NEST_VAL_TO_DATA_DELAY = 8044; // 8
+const static uint64_t SH_FLD_MBSECCQ_NEST_VAL_TO_DATA_DELAY_LEN = 8045; // 8
+const static uint64_t SH_FLD_MBSECCQ_READ_POINTER_DELAY = 8046; // 8
+const static uint64_t SH_FLD_MBSECCQ_READ_POINTER_DELAY_LEN = 8047; // 8
+const static uint64_t SH_FLD_MBSECCQ_RESERVED_10 = 8048; // 8
+const static uint64_t SH_FLD_MBSECCQ_RESERVED_12_14 = 8049; // 8
+const static uint64_t SH_FLD_MBSECCQ_RESERVED_12_14_LEN = 8050; // 8
+const static uint64_t SH_FLD_MBSECCQ_RESERVED_16 = 8051; // 8
+const static uint64_t SH_FLD_MBSECCQ_RESERVED_2 = 8052; // 8
+const static uint64_t SH_FLD_MBSECCQ_RESERVED_22_23 = 8053; // 8
+const static uint64_t SH_FLD_MBSECCQ_RESERVED_22_23_LEN = 8054; // 8
+const static uint64_t SH_FLD_MBSECCQ_RESERVED_3 = 8055; // 8
+const static uint64_t SH_FLD_MBSECCQ_RESERVED_4 = 8056; // 8
+const static uint64_t SH_FLD_MBSECCQ_RESERVED_40_47 = 8057; // 8
+const static uint64_t SH_FLD_MBSECCQ_RESERVED_40_47_LEN = 8058; // 8
+const static uint64_t SH_FLD_MBSECCQ_RESERVED_51 = 8059; // 8
+const static uint64_t SH_FLD_MBSECCQ_RESERVED_7_8 = 8060; // 8
+const static uint64_t SH_FLD_MBSECCQ_RESERVED_7_8_LEN = 8061; // 8
+const static uint64_t SH_FLD_MBSECCQ_USE_ADDRESS_HASH = 8062; // 8
+const static uint64_t SH_FLD_MBSECCQ_VAL_TO_DATA_DELAY = 8063; // 8
+const static uint64_t SH_FLD_MBSECCQ_VAL_TO_DATA_DELAY_LEN = 8064; // 8
+const static uint64_t SH_FLD_MBSPAQ_PE = 8065; // 2
+const static uint64_t SH_FLD_MBSPA_BIT_0_MODE = 8066; // 2
+const static uint64_t SH_FLD_MBS_MCBIST_SCOM_PE = 8067; // 2
+const static uint64_t SH_FLD_MB_BAD_ADDR = 8068; // 2
+const static uint64_t SH_FLD_MB_BAD_WRITE = 8069; // 2
+const static uint64_t SH_FLD_MB_CORRUPT = 8070; // 2
+const static uint64_t SH_FLD_MB_LINK_DOWN = 8071; // 2
+const static uint64_t SH_FLD_MB_LINK_ID = 8072; // 2
+const static uint64_t SH_FLD_MB_LINK_ID_LEN = 8073; // 2
+const static uint64_t SH_FLD_MB_RESET = 8074; // 2
+const static uint64_t SH_FLD_MB_SENT = 8075; // 2
+const static uint64_t SH_FLD_MB_SPARE = 8076; // 2
+const static uint64_t SH_FLD_MB_SPARE_LEN = 8077; // 2
+const static uint64_t SH_FLD_MB_VALID = 8078; // 2
+const static uint64_t SH_FLD_MB_WR_NOT_RD = 8079; // 2
+const static uint64_t SH_FLD_MCA_DBG_SEL_IN = 8080; // 8
+const static uint64_t SH_FLD_MCA_DBG_SEL_WRT = 8081; // 8
+const static uint64_t SH_FLD_MCBAGEN_PE = 8082; // 2
+const static uint64_t SH_FLD_MCBCNTL_PORT_SEL = 8083; // 2
+const static uint64_t SH_FLD_MCBCNTL_PORT_SEL_LEN = 8084; // 2
+const static uint64_t SH_FLD_MCBDGEN_PE = 8085; // 2
+const static uint64_t SH_FLD_MCBIST_BRODCAST_OUT_OF_SYNC = 8086; // 10
+const static uint64_t SH_FLD_MCBIST_CCS_SUBTEST_DONE = 8087; // 10
+const static uint64_t SH_FLD_MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR = 8088; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST = 8089; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_PAUSE_AFTER_CCS_SUBTEST = 8090; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_REF_WAIT_TIME = 8091; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_REF_WAIT_TIME_LEN = 8092; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_RAND_MODE = 8093; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_REV_MODE = 8094; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_SEL = 8095; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_SEL_LEN = 8096; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST00_COMPL_1ST_CMD = 8097; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST00_COMPL_2ND_CMD = 8098; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST00_COMPL_3RD_CMD = 8099; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST00_DATA_MODE = 8100; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST00_DATA_MODE_LEN = 8101; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST00_DONE = 8102; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST00_ECC_MODE = 8103; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST00_OP_TYPE = 8104; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST00_OP_TYPE_LEN = 8105; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_RAND_MODE = 8106; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_REV_MODE = 8107; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_SEL = 8108; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_SEL_LEN = 8109; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST01_COMPL_1ST_CMD = 8110; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST01_COMPL_2ND_CMD = 8111; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST01_COMPL_3RD_CMD = 8112; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST01_DATA_MODE = 8113; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST01_DATA_MODE_LEN = 8114; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST01_DONE = 8115; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST01_ECC_MODE = 8116; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST01_OP_TYPE = 8117; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST01_OP_TYPE_LEN = 8118; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_RAND_MODE = 8119; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_REV_MODE = 8120; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_SEL = 8121; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_SEL_LEN = 8122; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST02_COMPL_1ST_CMD = 8123; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST02_COMPL_2ND_CMD = 8124; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST02_COMPL_3RD_CMD = 8125; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST02_DATA_MODE = 8126; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST02_DATA_MODE_LEN = 8127; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST02_DONE = 8128; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST02_ECC_MODE = 8129; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST02_OP_TYPE = 8130; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST02_OP_TYPE_LEN = 8131; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_RAND_MODE = 8132; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_REV_MODE = 8133; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_SEL = 8134; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_SEL_LEN = 8135; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST03_COMPL_1ST_CMD = 8136; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST03_COMPL_2ND_CMD = 8137; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST03_COMPL_3RD_CMD = 8138; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST03_DATA_MODE = 8139; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST03_DATA_MODE_LEN = 8140; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST03_DONE = 8141; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST03_ECC_MODE = 8142; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST03_OP_TYPE = 8143; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST03_OP_TYPE_LEN = 8144; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_RAND_MODE = 8145; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_REV_MODE = 8146; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_SEL = 8147; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_SEL_LEN = 8148; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST04_COMPL_1ST_CMD = 8149; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST04_COMPL_2ND_CMD = 8150; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST04_COMPL_3RD_CMD = 8151; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST04_DATA_MODE = 8152; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST04_DATA_MODE_LEN = 8153; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST04_DONE = 8154; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST04_ECC_MODE = 8155; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST04_OP_TYPE = 8156; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST04_OP_TYPE_LEN = 8157; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_RAND_MODE = 8158; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_REV_MODE = 8159; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_SEL = 8160; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_SEL_LEN = 8161; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST05_COMPL_1ST_CMD = 8162; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST05_COMPL_2ND_CMD = 8163; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST05_COMPL_3RD_CMD = 8164; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST05_DATA_MODE = 8165; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST05_DATA_MODE_LEN = 8166; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST05_DONE = 8167; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST05_ECC_MODE = 8168; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST05_OP_TYPE = 8169; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST05_OP_TYPE_LEN = 8170; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_RAND_MODE = 8171; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_REV_MODE = 8172; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_SEL = 8173; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_SEL_LEN = 8174; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST06_COMPL_1ST_CMD = 8175; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST06_COMPL_2ND_CMD = 8176; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST06_COMPL_3RD_CMD = 8177; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST06_DATA_MODE = 8178; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST06_DATA_MODE_LEN = 8179; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST06_DONE = 8180; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST06_ECC_MODE = 8181; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST06_OP_TYPE = 8182; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST06_OP_TYPE_LEN = 8183; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_RAND_MODE = 8184; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_REV_MODE = 8185; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_SEL = 8186; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_SEL_LEN = 8187; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST07_COMPL_1ST_CMD = 8188; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST07_COMPL_2ND_CMD = 8189; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST07_COMPL_3RD_CMD = 8190; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST07_DATA_MODE = 8191; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST07_DATA_MODE_LEN = 8192; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST07_DONE = 8193; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST07_ECC_MODE = 8194; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST07_OP_TYPE = 8195; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST07_OP_TYPE_LEN = 8196; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_RAND_MODE = 8197; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_REV_MODE = 8198; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_SEL = 8199; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_SEL_LEN = 8200; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST08_COMPL_1ST_CMD = 8201; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST08_COMPL_2ND_CMD = 8202; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST08_COMPL_3RD_CMD = 8203; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST08_DATA_MODE = 8204; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST08_DATA_MODE_LEN = 8205; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST08_DONE = 8206; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST08_ECC_MODE = 8207; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST08_OP_TYPE = 8208; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST08_OP_TYPE_LEN = 8209; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_RAND_MODE = 8210; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_REV_MODE = 8211; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_SEL = 8212; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_SEL_LEN = 8213; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST09_COMPL_1ST_CMD = 8214; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST09_COMPL_2ND_CMD = 8215; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST09_COMPL_3RD_CMD = 8216; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST09_DATA_MODE = 8217; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST09_DATA_MODE_LEN = 8218; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST09_DONE = 8219; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST09_ECC_MODE = 8220; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST09_OP_TYPE = 8221; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST09_OP_TYPE_LEN = 8222; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_RAND_MODE = 8223; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_REV_MODE = 8224; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_SEL = 8225; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_SEL_LEN = 8226; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST10_COMPL_1ST_CMD = 8227; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST10_COMPL_2ND_CMD = 8228; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST10_COMPL_3RD_CMD = 8229; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST10_DATA_MODE = 8230; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST10_DATA_MODE_LEN = 8231; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST10_DONE = 8232; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST10_ECC_MODE = 8233; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST10_OP_TYPE = 8234; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST10_OP_TYPE_LEN = 8235; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_RAND_MODE = 8236; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_REV_MODE = 8237; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_SEL = 8238; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_SEL_LEN = 8239; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST11_COMPL_1ST_CMD = 8240; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST11_COMPL_2ND_CMD = 8241; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST11_COMPL_3RD_CMD = 8242; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST11_DATA_MODE = 8243; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST11_DATA_MODE_LEN = 8244; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST11_DONE = 8245; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST11_ECC_MODE = 8246; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST11_OP_TYPE = 8247; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST11_OP_TYPE_LEN = 8248; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_RAND_MODE = 8249; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_REV_MODE = 8250; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_SEL = 8251; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_SEL_LEN = 8252; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST12_COMPL_1ST_CMD = 8253; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST12_COMPL_2ND_CMD = 8254; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST12_COMPL_3RD_CMD = 8255; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST12_DATA_MODE = 8256; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST12_DATA_MODE_LEN = 8257; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST12_DONE = 8258; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST12_ECC_MODE = 8259; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST12_OP_TYPE = 8260; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST12_OP_TYPE_LEN = 8261; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_RAND_MODE = 8262; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_REV_MODE = 8263; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_SEL = 8264; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_SEL_LEN = 8265; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST13_COMPL_1ST_CMD = 8266; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST13_COMPL_2ND_CMD = 8267; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST13_COMPL_3RD_CMD = 8268; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST13_DATA_MODE = 8269; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST13_DATA_MODE_LEN = 8270; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST13_DONE = 8271; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST13_ECC_MODE = 8272; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST13_OP_TYPE = 8273; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST13_OP_TYPE_LEN = 8274; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_RAND_MODE = 8275; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_REV_MODE = 8276; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_SEL = 8277; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_SEL_LEN = 8278; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST14_COMPL_1ST_CMD = 8279; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST14_COMPL_2ND_CMD = 8280; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST14_COMPL_3RD_CMD = 8281; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST14_DATA_MODE = 8282; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST14_DATA_MODE_LEN = 8283; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST14_DONE = 8284; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST14_ECC_MODE = 8285; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST14_OP_TYPE = 8286; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST14_OP_TYPE_LEN = 8287; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_RAND_MODE = 8288; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_REV_MODE = 8289; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_SEL = 8290; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_SEL_LEN = 8291; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST15_COMPL_1ST_CMD = 8292; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST15_COMPL_2ND_CMD = 8293; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST15_COMPL_3RD_CMD = 8294; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST15_DATA_MODE = 8295; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST15_DATA_MODE_LEN = 8296; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST15_DONE = 8297; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST15_ECC_MODE = 8298; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST15_OP_TYPE = 8299; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST15_OP_TYPE_LEN = 8300; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_RAND_MODE = 8301; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_REV_MODE = 8302; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_SEL = 8303; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_SEL_LEN = 8304; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST16_COMPL_1ST_CMD = 8305; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST16_COMPL_2ND_CMD = 8306; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST16_COMPL_3RD_CMD = 8307; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST16_DATA_MODE = 8308; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST16_DATA_MODE_LEN = 8309; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST16_DONE = 8310; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST16_ECC_MODE = 8311; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST16_OP_TYPE = 8312; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST16_OP_TYPE_LEN = 8313; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_RAND_MODE = 8314; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_REV_MODE = 8315; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_SEL = 8316; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_SEL_LEN = 8317; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST17_COMPL_1ST_CMD = 8318; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST17_COMPL_2ND_CMD = 8319; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST17_COMPL_3RD_CMD = 8320; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST17_DATA_MODE = 8321; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST17_DATA_MODE_LEN = 8322; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST17_DONE = 8323; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST17_ECC_MODE = 8324; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST17_OP_TYPE = 8325; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST17_OP_TYPE_LEN = 8326; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_RAND_MODE = 8327; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_REV_MODE = 8328; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_SEL = 8329; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_SEL_LEN = 8330; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST18_COMPL_1ST_CMD = 8331; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST18_COMPL_2ND_CMD = 8332; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST18_COMPL_3RD_CMD = 8333; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST18_DATA_MODE = 8334; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST18_DATA_MODE_LEN = 8335; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST18_DONE = 8336; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST18_ECC_MODE = 8337; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST18_OP_TYPE = 8338; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST18_OP_TYPE_LEN = 8339; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_RAND_MODE = 8340; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_REV_MODE = 8341; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_SEL = 8342; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_SEL_LEN = 8343; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST19_COMPL_1ST_CMD = 8344; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST19_COMPL_2ND_CMD = 8345; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST19_COMPL_3RD_CMD = 8346; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST19_DATA_MODE = 8347; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST19_DATA_MODE_LEN = 8348; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST19_DONE = 8349; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST19_ECC_MODE = 8350; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST19_OP_TYPE = 8351; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST19_OP_TYPE_LEN = 8352; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_RAND_MODE = 8353; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_REV_MODE = 8354; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_SEL = 8355; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_SEL_LEN = 8356; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST20_COMPL_1ST_CMD = 8357; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST20_COMPL_2ND_CMD = 8358; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST20_COMPL_3RD_CMD = 8359; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST20_DATA_MODE = 8360; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST20_DATA_MODE_LEN = 8361; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST20_DONE = 8362; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST20_ECC_MODE = 8363; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST20_OP_TYPE = 8364; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST20_OP_TYPE_LEN = 8365; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_RAND_MODE = 8366; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_REV_MODE = 8367; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_SEL = 8368; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_SEL_LEN = 8369; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST21_COMPL_1ST_CMD = 8370; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST21_COMPL_2ND_CMD = 8371; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST21_COMPL_3RD_CMD = 8372; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST21_DATA_MODE = 8373; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST21_DATA_MODE_LEN = 8374; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST21_DONE = 8375; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST21_ECC_MODE = 8376; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST21_OP_TYPE = 8377; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST21_OP_TYPE_LEN = 8378; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_RAND_MODE = 8379; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_REV_MODE = 8380; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_SEL = 8381; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_SEL_LEN = 8382; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST22_COMPL_1ST_CMD = 8383; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST22_COMPL_2ND_CMD = 8384; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST22_COMPL_3RD_CMD = 8385; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST22_DATA_MODE = 8386; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST22_DATA_MODE_LEN = 8387; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST22_DONE = 8388; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST22_ECC_MODE = 8389; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST22_OP_TYPE = 8390; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST22_OP_TYPE_LEN = 8391; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_RAND_MODE = 8392; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_REV_MODE = 8393; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_SEL = 8394; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_SEL_LEN = 8395; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST23_COMPL_1ST_CMD = 8396; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST23_COMPL_2ND_CMD = 8397; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST23_COMPL_3RD_CMD = 8398; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST23_DATA_MODE = 8399; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST23_DATA_MODE_LEN = 8400; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST23_DONE = 8401; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST23_ECC_MODE = 8402; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST23_OP_TYPE = 8403; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST23_OP_TYPE_LEN = 8404; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_RAND_MODE = 8405; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_REV_MODE = 8406; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_SEL = 8407; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_SEL_LEN = 8408; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST24_COMPL_1ST_CMD = 8409; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST24_COMPL_2ND_CMD = 8410; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST24_COMPL_3RD_CMD = 8411; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST24_DATA_MODE = 8412; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST24_DATA_MODE_LEN = 8413; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST24_DONE = 8414; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST24_ECC_MODE = 8415; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST24_OP_TYPE = 8416; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST24_OP_TYPE_LEN = 8417; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_RAND_MODE = 8418; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_REV_MODE = 8419; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_SEL = 8420; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_SEL_LEN = 8421; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST25_COMPL_1ST_CMD = 8422; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST25_COMPL_2ND_CMD = 8423; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST25_COMPL_3RD_CMD = 8424; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST25_DATA_MODE = 8425; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST25_DATA_MODE_LEN = 8426; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST25_DONE = 8427; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST25_ECC_MODE = 8428; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST25_OP_TYPE = 8429; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST25_OP_TYPE_LEN = 8430; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_RAND_MODE = 8431; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_REV_MODE = 8432; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_SEL = 8433; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_SEL_LEN = 8434; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST26_COMPL_1ST_CMD = 8435; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST26_COMPL_2ND_CMD = 8436; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST26_COMPL_3RD_CMD = 8437; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST26_DATA_MODE = 8438; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST26_DATA_MODE_LEN = 8439; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST26_DONE = 8440; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST26_ECC_MODE = 8441; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST26_OP_TYPE = 8442; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST26_OP_TYPE_LEN = 8443; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_RAND_MODE = 8444; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_REV_MODE = 8445; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_SEL = 8446; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_SEL_LEN = 8447; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST27_COMPL_1ST_CMD = 8448; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST27_COMPL_2ND_CMD = 8449; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST27_COMPL_3RD_CMD = 8450; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST27_DATA_MODE = 8451; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST27_DATA_MODE_LEN = 8452; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST27_DONE = 8453; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST27_ECC_MODE = 8454; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST27_OP_TYPE = 8455; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST27_OP_TYPE_LEN = 8456; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_RAND_MODE = 8457; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_REV_MODE = 8458; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_SEL = 8459; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_SEL_LEN = 8460; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST28_COMPL_1ST_CMD = 8461; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST28_COMPL_2ND_CMD = 8462; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST28_COMPL_3RD_CMD = 8463; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST28_DATA_MODE = 8464; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST28_DATA_MODE_LEN = 8465; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST28_DONE = 8466; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST28_ECC_MODE = 8467; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST28_OP_TYPE = 8468; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST28_OP_TYPE_LEN = 8469; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_RAND_MODE = 8470; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_REV_MODE = 8471; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_SEL = 8472; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_SEL_LEN = 8473; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST29_COMPL_1ST_CMD = 8474; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST29_COMPL_2ND_CMD = 8475; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST29_COMPL_3RD_CMD = 8476; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST29_DATA_MODE = 8477; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST29_DATA_MODE_LEN = 8478; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST29_DONE = 8479; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST29_ECC_MODE = 8480; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST29_OP_TYPE = 8481; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST29_OP_TYPE_LEN = 8482; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_RAND_MODE = 8483; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_REV_MODE = 8484; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_SEL = 8485; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_SEL_LEN = 8486; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST30_COMPL_1ST_CMD = 8487; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST30_COMPL_2ND_CMD = 8488; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST30_COMPL_3RD_CMD = 8489; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST30_DATA_MODE = 8490; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST30_DATA_MODE_LEN = 8491; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST30_DONE = 8492; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST30_ECC_MODE = 8493; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST30_OP_TYPE = 8494; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST30_OP_TYPE_LEN = 8495; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_RAND_MODE = 8496; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_REV_MODE = 8497; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_SEL = 8498; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_SEL_LEN = 8499; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST31_COMPL_1ST_CMD = 8500; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST31_COMPL_2ND_CMD = 8501; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST31_COMPL_3RD_CMD = 8502; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST31_DATA_MODE = 8503; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST31_DATA_MODE_LEN = 8504; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST31_DONE = 8505; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST31_ECC_MODE = 8506; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST31_OP_TYPE = 8507; // 2
+const static uint64_t SH_FLD_MCBIST_CFG_TEST31_OP_TYPE_LEN = 8508; // 2
+const static uint64_t SH_FLD_MCBIST_DATA_ERROR = 8509; // 10
+const static uint64_t SH_FLD_MCBIST_DONE = 8510; // 4
+const static uint64_t SH_FLD_MCBIST_HALF_COMPARE_MASK = 8511; // 8
+const static uint64_t SH_FLD_MCBIST_HALF_COMPARE_MASK_LEN = 8512; // 8
+const static uint64_t SH_FLD_MCBIST_MASK_COVERAGE_SELECTOR = 8513; // 8
+const static uint64_t SH_FLD_MCBIST_PROGRAM_COMPLETE = 8514; // 10
+const static uint64_t SH_FLD_MCBIST_TRAP_CE_ENABLE = 8515; // 8
+const static uint64_t SH_FLD_MCBIST_TRAP_MPE_ENABLE = 8516; // 8
+const static uint64_t SH_FLD_MCBIST_TRAP_NONSTOP = 8517; // 8
+const static uint64_t SH_FLD_MCBIST_TRAP_UE_ENABLE = 8518; // 8
+const static uint64_t SH_FLD_MCB_CNTLQ_PE = 8519; // 2
+const static uint64_t SH_FLD_MCB_FIR_CCS_ERR = 8520; // 2
+const static uint64_t SH_FLD_MCB_FIR_MCBAGEN_ERR = 8521; // 2
+const static uint64_t SH_FLD_MCB_FIR_MCBFSM_ERR = 8522; // 2
+const static uint64_t SH_FLD_MCD_CHICKEN_SWITCH = 8523; // 2
+const static uint64_t SH_FLD_MCE_SYMBOL0_COUNT = 8524; // 2
+const static uint64_t SH_FLD_MCE_SYMBOL0_COUNT_LEN = 8525; // 2
+const static uint64_t SH_FLD_MCE_SYMBOL1_COUNT = 8526; // 2
+const static uint64_t SH_FLD_MCE_SYMBOL1_COUNT_LEN = 8527; // 2
+const static uint64_t SH_FLD_MCE_SYMBOL2_COUNT = 8528; // 2
+const static uint64_t SH_FLD_MCE_SYMBOL2_COUNT_LEN = 8529; // 2
+const static uint64_t SH_FLD_MCE_SYMBOL3_COUNT = 8530; // 2
+const static uint64_t SH_FLD_MCE_SYMBOL3_COUNT_LEN = 8531; // 2
+const static uint64_t SH_FLD_MCMODE0_64B_WR_IS_PWRT = 8532; // 4
+const static uint64_t SH_FLD_MCPERF1_DISABLE_FASTPATH_QOS = 8533; // 4
+const static uint64_t SH_FLD_MCS_RESET_KEEPER = 8534; // 4
+const static uint64_t SH_FLD_MCS_WAT = 8535; // 4
+const static uint64_t SH_FLD_MC_CHANNELS_PER_GROUP = 8536; // 4
+const static uint64_t SH_FLD_MC_CHANNELS_PER_GROUP_LEN = 8537; // 4
+const static uint64_t SH_FLD_MC_FP_MATE_CMD_ERR0 = 8538; // 12
+const static uint64_t SH_FLD_MC_FP_MATE_CMD_ERR1 = 8539; // 12
+const static uint64_t SH_FLD_MC_INTERNAL_NONRECOVERABLE_ERROR = 8540; // 4
+const static uint64_t SH_FLD_MC_INTERNAL_RECOVERABLE_ERROR = 8541; // 4
+const static uint64_t SH_FLD_MC_TC_0_FIR_HOST_ATTN = 8542; // 2
+const static uint64_t SH_FLD_MC_TC_1_FIR_HOST_ATTN = 8543; // 2
+const static uint64_t SH_FLD_MC_TC_2_FIR_HOST_ATTN = 8544; // 2
+const static uint64_t SH_FLD_MC_TC_3_FIR_HOST_ATTN = 8545; // 2
+const static uint64_t SH_FLD_MC_TC_4_FIR_HOST_ATTN = 8546; // 2
+const static uint64_t SH_FLD_MC_TC_5_FIR_HOST_ATTN = 8547; // 2
+const static uint64_t SH_FLD_MC_TC_6_FIR_HOST_ATTN = 8548; // 2
+const static uint64_t SH_FLD_MC_TC_7_FIR_HOST_ATTN = 8549; // 2
+const static uint64_t SH_FLD_MD5_LATENCY_CFG = 8550; // 1
+const static uint64_t SH_FLD_MED_IDLE_COUNT = 8551; // 8
+const static uint64_t SH_FLD_MED_IDLE_COUNT_LEN = 8552; // 8
+const static uint64_t SH_FLD_MED_IDLE_THRESHOLD = 8553; // 8
+const static uint64_t SH_FLD_MED_IDLE_THRESHOLD_LEN = 8554; // 8
+const static uint64_t SH_FLD_MEM = 8555; // 26
+const static uint64_t SH_FLD_MEMCTL_CIC_FAST = 8556; // 8
+const static uint64_t SH_FLD_MEMCTL_CTRN_IGNORE = 8557; // 8
+const static uint64_t SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP = 8558; // 4
+const static uint64_t SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN = 8559; // 4
+const static uint64_t SH_FLD_MEMORY_TYPE = 8560; // 8
+const static uint64_t SH_FLD_MEMORY_TYPE_LEN = 8561; // 8
+const static uint64_t SH_FLD_MEM_ADDR = 8562; // 18
+const static uint64_t SH_FLD_MEM_ADDR_LEN = 8563; // 18
+const static uint64_t SH_FLD_MEM_BUSY = 8564; // 18
+const static uint64_t SH_FLD_MEM_BYTE_ENABLE = 8565; // 18
+const static uint64_t SH_FLD_MEM_BYTE_ENABLE_LEN = 8566; // 18
+const static uint64_t SH_FLD_MEM_DATAOP_PENDING = 8567; // 18
+const static uint64_t SH_FLD_MEM_ERROR = 8568; // 18
+const static uint64_t SH_FLD_MEM_ERROR_LEN = 8569; // 18
+const static uint64_t SH_FLD_MEM_HIGH_PRIORITY = 8570; // 4
+const static uint64_t SH_FLD_MEM_HIGH_PRIORITY_LEN = 8571; // 4
+const static uint64_t SH_FLD_MEM_IFETCH_PENDING = 8572; // 18
+const static uint64_t SH_FLD_MEM_IMPRECISE_ERROR_PENDING = 8573; // 18
+const static uint64_t SH_FLD_MEM_LEN = 8574; // 26
+const static uint64_t SH_FLD_MEM_LINE_MODE = 8575; // 18
+const static uint64_t SH_FLD_MEM_LOW_PRIORITY = 8576; // 4
+const static uint64_t SH_FLD_MEM_LOW_PRIORITY_LEN = 8577; // 4
+const static uint64_t SH_FLD_MEM_R_NW = 8578; // 18
+const static uint64_t SH_FLD_MEM_SIZE = 8579; // 6
+const static uint64_t SH_FLD_MEM_SIZE_LEN = 8580; // 6
+const static uint64_t SH_FLD_MERGE_CAPACITY_LIMIT = 8581; // 8
+const static uint64_t SH_FLD_MERGE_CAPACITY_LIMIT_LEN = 8582; // 8
+const static uint64_t SH_FLD_MGR_CREDIT = 8583; // 3
+const static uint64_t SH_FLD_MGR_CREDIT_LEN = 8584; // 3
+const static uint64_t SH_FLD_MIB_GPIO = 8585; // 13
+const static uint64_t SH_FLD_MIB_GPIO_LEN = 8586; // 13
+const static uint64_t SH_FLD_MID_CARE_MASK = 8587; // 4
+const static uint64_t SH_FLD_MID_CARE_MASK_LEN = 8588; // 4
+const static uint64_t SH_FLD_MID_MATCH_VALUE = 8589; // 4
+const static uint64_t SH_FLD_MID_MATCH_VALUE_LEN = 8590; // 4
+const static uint64_t SH_FLD_MINCYCLECNT = 8591; // 3
+const static uint64_t SH_FLD_MINCYCLECNT_LEN = 8592; // 3
+const static uint64_t SH_FLD_MINIKERF = 8593; // 2
+const static uint64_t SH_FLD_MINIKERF_LEN = 8594; // 2
+const static uint64_t SH_FLD_MIN_CYCLE_SAMPLE = 8595; // 12
+const static uint64_t SH_FLD_MIN_CYCLE_SAMPLE_LEN = 8596; // 12
+const static uint64_t SH_FLD_MIN_EYE_HEIGHT = 8597; // 6
+const static uint64_t SH_FLD_MIN_EYE_HEIGHT_LEN = 8598; // 6
+const static uint64_t SH_FLD_MIN_EYE_WIDTH = 8599; // 6
+const static uint64_t SH_FLD_MIN_EYE_WIDTH_LEN = 8600; // 6
+const static uint64_t SH_FLD_MIRROR_ACTION_OCCURRED = 8601; // 4
+const static uint64_t SH_FLD_MISC = 8602; // 2
+const static uint64_t SH_FLD_MISC_CFG = 8603; // 6
+const static uint64_t SH_FLD_MISC_CFG_LEN = 8604; // 6
+const static uint64_t SH_FLD_MISC_CTL_4VS64 = 8605; // 1
+const static uint64_t SH_FLD_MISC_CTL_ACCEPT_PASTE = 8606; // 1
+const static uint64_t SH_FLD_MISC_CTL_CAM_LOCATION = 8607; // 1
+const static uint64_t SH_FLD_MISC_CTL_CAM_LOCATION_LEN = 8608; // 1
+const static uint64_t SH_FLD_MISC_CTL_CQ_IS_IDLE = 8609; // 1
+const static uint64_t SH_FLD_MISC_CTL_EG_IS_IDLE = 8610; // 1
+const static uint64_t SH_FLD_MISC_CTL_ENABLE_WRMON = 8611; // 1
+const static uint64_t SH_FLD_MISC_CTL_INVALIDATE_CAM_ALL = 8612; // 1
+const static uint64_t SH_FLD_MISC_CTL_INVALIDATE_CAM_LOC = 8613; // 1
+const static uint64_t SH_FLD_MISC_CTL_IN_IS_IDLE = 8614; // 1
+const static uint64_t SH_FLD_MISC_CTL_RG_IS_IDLE = 8615; // 1
+const static uint64_t SH_FLD_MISC_CTL_WC_IS_IDLE = 8616; // 1
+const static uint64_t SH_FLD_MISC_LEN = 8617; // 2
+const static uint64_t SH_FLD_MISC_MACH_ERROR_MASK = 8618; // 12
+const static uint64_t SH_FLD_MISC_MACH_ERROR_MASK_LEN = 8619; // 12
+const static uint64_t SH_FLD_MISC_RESYNC_OSC_FROM = 8620; // 1
+const static uint64_t SH_FLD_MISR_A_VAL = 8621; // 43
+const static uint64_t SH_FLD_MISR_A_VAL_LEN = 8622; // 43
+const static uint64_t SH_FLD_MISR_B_VAL = 8623; // 43
+const static uint64_t SH_FLD_MISR_B_VAL_LEN = 8624; // 43
+const static uint64_t SH_FLD_MISR_INIT_WAIT = 8625; // 43
+const static uint64_t SH_FLD_MISR_INIT_WAIT_LEN = 8626; // 43
+const static uint64_t SH_FLD_MISR_MODE = 8627; // 43
+const static uint64_t SH_FLD_MMIOSD = 8628; // 1
+const static uint64_t SH_FLD_MMIO_BAR_PE = 8629; // 2
+const static uint64_t SH_FLD_MMIO_CTL_ACTYPE = 8630; // 1
+const static uint64_t SH_FLD_MMIO_CTL_COMP = 8631; // 1
+const static uint64_t SH_FLD_MMIO_CTL_INIT = 8632; // 1
+const static uint64_t SH_FLD_MMIO_CTL_OFFSET = 8633; // 1
+const static uint64_t SH_FLD_MMIO_CTL_OFFSET_LEN = 8634; // 1
+const static uint64_t SH_FLD_MMIO_CTL_OPTYPE = 8635; // 1
+const static uint64_t SH_FLD_MMIO_CTL_UNUSED = 8636; // 1
+const static uint64_t SH_FLD_MMIO_CTL_UNUSED_LEN = 8637; // 1
+const static uint64_t SH_FLD_MMIO_CTL_WINID = 8638; // 1
+const static uint64_t SH_FLD_MMIO_CTL_WINID_LEN = 8639; // 1
+const static uint64_t SH_FLD_MMIO_HYP_RD_ADDR_ERR = 8640; // 2
+const static uint64_t SH_FLD_MMIO_HYP_WR_ADDR_ERR = 8641; // 2
+const static uint64_t SH_FLD_MMIO_NON8B_HYP_ERR = 8642; // 2
+const static uint64_t SH_FLD_MMIO_NON8B_OS_ERR = 8643; // 2
+const static uint64_t SH_FLD_MMIO_OS_RD_ADDR_ERR = 8644; // 2
+const static uint64_t SH_FLD_MMIO_OS_WR_ADDR_ERR = 8645; // 2
+const static uint64_t SH_FLD_MMR = 8646; // 1
+const static uint64_t SH_FLD_MMR_LEN = 8647; // 1
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_00 = 8648; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_00_LEN = 8649; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_01 = 8650; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_01_LEN = 8651; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_02 = 8652; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_02_LEN = 8653; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_03 = 8654; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_03_LEN = 8655; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_04 = 8656; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_04_LEN = 8657; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_05 = 8658; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_05_LEN = 8659; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_06 = 8660; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_06_LEN = 8661; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_07 = 8662; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_07_LEN = 8663; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_08 = 8664; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_08_LEN = 8665; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_09 = 8666; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_09_LEN = 8667; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_10 = 8668; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_10_LEN = 8669; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_11 = 8670; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_11_LEN = 8671; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_12 = 8672; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_12_LEN = 8673; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_13 = 8674; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_13_LEN = 8675; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_14 = 8676; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_14_LEN = 8677; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_15 = 8678; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_15_LEN = 8679; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_16 = 8680; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_16_LEN = 8681; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_17 = 8682; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_17_LEN = 8683; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_18 = 8684; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_18_LEN = 8685; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_19 = 8686; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_19_LEN = 8687; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_20 = 8688; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_20_LEN = 8689; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_21 = 8690; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_21_LEN = 8691; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_22 = 8692; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_22_LEN = 8693; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_23 = 8694; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_23_LEN = 8695; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_24 = 8696; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_24_LEN = 8697; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_25 = 8698; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_25_LEN = 8699; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_26 = 8700; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_26_LEN = 8701; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_27 = 8702; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_27_LEN = 8703; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_28 = 8704; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_28_LEN = 8705; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_29 = 8706; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_29_LEN = 8707; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_30 = 8708; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_30_LEN = 8709; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_31 = 8710; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_31_LEN = 8711; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_32 = 8712; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_32_LEN = 8713; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_33 = 8714; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_33_LEN = 8715; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_34 = 8716; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_34_LEN = 8717; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_35 = 8718; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_35_LEN = 8719; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_36 = 8720; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_36_LEN = 8721; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_37 = 8722; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_37_LEN = 8723; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_38 = 8724; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_38_LEN = 8725; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_39 = 8726; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_39_LEN = 8727; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_40 = 8728; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_40_LEN = 8729; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_41 = 8730; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_41_LEN = 8731; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_42 = 8732; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_42_LEN = 8733; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_43 = 8734; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_43_LEN = 8735; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_44 = 8736; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_44_LEN = 8737; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_45 = 8738; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_45_LEN = 8739; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_46 = 8740; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_46_LEN = 8741; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_47 = 8742; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_47_LEN = 8743; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_48 = 8744; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_48_LEN = 8745; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_49 = 8746; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_49_LEN = 8747; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_50 = 8748; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_50_LEN = 8749; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_51 = 8750; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_51_LEN = 8751; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_52 = 8752; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_52_LEN = 8753; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_53 = 8754; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_53_LEN = 8755; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_54 = 8756; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_54_LEN = 8757; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_55 = 8758; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_55_LEN = 8759; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_56 = 8760; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_56_LEN = 8761; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_57 = 8762; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_57_LEN = 8763; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_58 = 8764; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_58_LEN = 8765; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_59 = 8766; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_59_LEN = 8767; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_60 = 8768; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_60_LEN = 8769; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_61 = 8770; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_61_LEN = 8771; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_62 = 8772; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_62_LEN = 8773; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_63 = 8774; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_63_LEN = 8775; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_64 = 8776; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_64_LEN = 8777; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_65 = 8778; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_65_LEN = 8779; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_66 = 8780; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_66_LEN = 8781; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_67 = 8782; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_67_LEN = 8783; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_68 = 8784; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_68_LEN = 8785; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_69 = 8786; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_69_LEN = 8787; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_70 = 8788; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_70_LEN = 8789; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_71 = 8790; // 2
+const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_71_LEN = 8791; // 2
+const static uint64_t SH_FLD_MODE = 8792; // 151
+const static uint64_t SH_FLD_MODE_128K_VP = 8793; // 1
+const static uint64_t SH_FLD_MODE_LEN = 8794; // 149
+const static uint64_t SH_FLD_MODE_REGISTER_0_VALUE = 8795; // 64
+const static uint64_t SH_FLD_MODE_REGISTER_0_VALUE_LEN = 8796; // 64
+const static uint64_t SH_FLD_MODE_REGISTER_1_VALUE = 8797; // 64
+const static uint64_t SH_FLD_MODE_REGISTER_1_VALUE_LEN = 8798; // 64
+const static uint64_t SH_FLD_MODE_REGISTER_2_VALUE = 8799; // 64
+const static uint64_t SH_FLD_MODE_REGISTER_2_VALUE_LEN = 8800; // 64
+const static uint64_t SH_FLD_MODE_REGISTER_3_VALUE = 8801; // 64
+const static uint64_t SH_FLD_MODE_REGISTER_3_VALUE_LEN = 8802; // 64
+const static uint64_t SH_FLD_MODE_SEL = 8803; // 12
+const static uint64_t SH_FLD_MON = 8804; // 12
+const static uint64_t SH_FLD_MON_LEN = 8805; // 12
+const static uint64_t SH_FLD_MOVE_TO_TB_CORE_ADDRESS = 8806; // 1
+const static uint64_t SH_FLD_MOVE_TO_TB_CORE_ADDRESS_ENABLE = 8807; // 1
+const static uint64_t SH_FLD_MOVE_TO_TB_CORE_ADDRESS_LEN = 8808; // 1
+const static uint64_t SH_FLD_MOVE_TO_TB_CORE_ID = 8809; // 1
+const static uint64_t SH_FLD_MOVE_TO_TB_CORE_ID_LEN = 8810; // 1
+const static uint64_t SH_FLD_MOVE_TO_TB_ON_2X_SYNC_ENABLE = 8811; // 1
+const static uint64_t SH_FLD_MPR_PATTERN_BIT = 8812; // 8
+const static uint64_t SH_FLD_MPSS_DIS = 8813; // 1
+const static uint64_t SH_FLD_MPW1 = 8814; // 43
+const static uint64_t SH_FLD_MPW2 = 8815; // 43
+const static uint64_t SH_FLD_MPW3 = 8816; // 43
+const static uint64_t SH_FLD_MRANK_SCRUBED = 8817; // 2
+const static uint64_t SH_FLD_MRANK_SCRUBED_LEN = 8818; // 2
+const static uint64_t SH_FLD_MRG_BBRD_NBUF = 8819; // 3
+const static uint64_t SH_FLD_MRG_BBRD_NBUF_LEN = 8820; // 3
+const static uint64_t SH_FLD_MRG_CR_DIS = 8821; // 3
+const static uint64_t SH_FLD_MRG_CTLW_CR_DIS = 8822; // 3
+const static uint64_t SH_FLD_MRG_IBRD_NBUF = 8823; // 3
+const static uint64_t SH_FLD_MRG_IBRD_NBUF_LEN = 8824; // 3
+const static uint64_t SH_FLD_MRG_IBWR_NBUF = 8825; // 3
+const static uint64_t SH_FLD_MRG_IBWR_NBUF_LEN = 8826; // 3
+const static uint64_t SH_FLD_MRG_OBRD_NBUF = 8827; // 3
+const static uint64_t SH_FLD_MRG_OBRD_NBUF_LEN = 8828; // 3
+const static uint64_t SH_FLD_MRG_PBTX_NBUF = 8829; // 3
+const static uint64_t SH_FLD_MRG_PBTX_NBUF_LEN = 8830; // 3
+const static uint64_t SH_FLD_MRG_RDBF_NBUF = 8831; // 3
+const static uint64_t SH_FLD_MRG_RDBF_NBUF_LEN = 8832; // 3
+const static uint64_t SH_FLD_MRS_CMD_DQ_OFF = 8833; // 8
+const static uint64_t SH_FLD_MRS_CMD_DQ_OFF_LEN = 8834; // 8
+const static uint64_t SH_FLD_MRS_CMD_DQ_ON = 8835; // 8
+const static uint64_t SH_FLD_MRS_CMD_DQ_ON_LEN = 8836; // 8
+const static uint64_t SH_FLD_MR_MASK_EN = 8837; // 8
+const static uint64_t SH_FLD_MR_MASK_EN_LEN = 8838; // 8
+const static uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_1 = 8839; // 1
+const static uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_1_LEN = 8840; // 1
+const static uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_2 = 8841; // 1
+const static uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_2_LEN = 8842; // 1
+const static uint64_t SH_FLD_MSADES_ILLEGAL_OPERATION_ATTEMPTED_1 = 8843; // 1
+const static uint64_t SH_FLD_MSADES_ILLEGAL_OPERATION_ATTEMPTED_2 = 8844; // 1
+const static uint64_t SH_FLD_MSADES_LBUS_B_RAM_PARITY_DETECTED_1 = 8845; // 1
+const static uint64_t SH_FLD_MSADES_LBUS_B_RAM_PARITY_DETECTED_2 = 8846; // 1
+const static uint64_t SH_FLD_MSADES_READ_EMPTY_PIB_1 = 8847; // 1
+const static uint64_t SH_FLD_MSADES_READ_EMPTY_PIB_2 = 8848; // 1
+const static uint64_t SH_FLD_MSADES_UNUSED_15_12 = 8849; // 1
+const static uint64_t SH_FLD_MSADES_UNUSED_15_12_LEN = 8850; // 1
+const static uint64_t SH_FLD_MSADES_UNUSED_31_28 = 8851; // 1
+const static uint64_t SH_FLD_MSADES_UNUSED_31_28_LEN = 8852; // 1
+const static uint64_t SH_FLD_MSADES_WRITE_FULL_PIB_1 = 8853; // 1
+const static uint64_t SH_FLD_MSADES_WRITE_FULL_PIB_2 = 8854; // 1
+const static uint64_t SH_FLD_MSADI_PIB_ERROR_1 = 8855; // 1
+const static uint64_t SH_FLD_MSADI_PIB_ERROR_2 = 8856; // 1
+const static uint64_t SH_FLD_MSADI_PIB_PENDING_1 = 8857; // 1
+const static uint64_t SH_FLD_MSADI_PIB_PENDING_2 = 8858; // 1
+const static uint64_t SH_FLD_MSADI_UNUSED_31_11 = 8859; // 4
+const static uint64_t SH_FLD_MSADI_UNUSED_31_11_LEN = 8860; // 4
+const static uint64_t SH_FLD_MSADI_UNUSED_7_3 = 8861; // 1
+const static uint64_t SH_FLD_MSADI_UNUSED_7_3_LEN = 8862; // 1
+const static uint64_t SH_FLD_MSADI_XUP_1 = 8863; // 1
+const static uint64_t SH_FLD_MSADI_XUP_2 = 8864; // 1
+const static uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_1 = 8865; // 1
+const static uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_1_LEN = 8866; // 1
+const static uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_2 = 8867; // 1
+const static uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_2_LEN = 8868; // 1
+const static uint64_t SH_FLD_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_1 = 8869; // 1
+const static uint64_t SH_FLD_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_2 = 8870; // 1
+const static uint64_t SH_FLD_MSBDES_PIB_A_RAM_PARITY_DETECTED_1 = 8871; // 1
+const static uint64_t SH_FLD_MSBDES_PIB_A_RAM_PARITY_DETECTED_2 = 8872; // 1
+const static uint64_t SH_FLD_MSBDES_READ_EMPTY_PIB_A_1 = 8873; // 1
+const static uint64_t SH_FLD_MSBDES_READ_EMPTY_PIB_A_2 = 8874; // 1
+const static uint64_t SH_FLD_MSBDES_UNUSED_17_12 = 8875; // 1
+const static uint64_t SH_FLD_MSBDES_UNUSED_17_12_LEN = 8876; // 1
+const static uint64_t SH_FLD_MSBDES_UNUSED_1_0 = 8877; // 2
+const static uint64_t SH_FLD_MSBDES_UNUSED_1_0_LEN = 8878; // 2
+const static uint64_t SH_FLD_MSBDES_UNUSED_31_28 = 8879; // 1
+const static uint64_t SH_FLD_MSBDES_UNUSED_31_28_LEN = 8880; // 1
+const static uint64_t SH_FLD_MSBDES_WRITE_FULL_PIB_A_1 = 8881; // 1
+const static uint64_t SH_FLD_MSBDES_WRITE_FULL_PIB_A_2 = 8882; // 1
+const static uint64_t SH_FLD_MSBDIM1_ENABLE_ABORT = 8883; // 1
+const static uint64_t SH_FLD_MSBDIM1_ENABLE_ABORT_2 = 8884; // 1
+const static uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_ERROR = 8885; // 1
+const static uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_ERROR_2 = 8886; // 1
+const static uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_PENDING = 8887; // 1
+const static uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_PENDING_2 = 8888; // 1
+const static uint64_t SH_FLD_MSBDIM1_ENABLE_XDN = 8889; // 1
+const static uint64_t SH_FLD_MSBDIM1_ENABLE_XDN_2 = 8890; // 1
+const static uint64_t SH_FLD_MSBDI_LBUS_ERROR_1 = 8891; // 1
+const static uint64_t SH_FLD_MSBDI_LBUS_ERROR_2 = 8892; // 1
+const static uint64_t SH_FLD_MSBDI_LBUS_PENDING_1 = 8893; // 1
+const static uint64_t SH_FLD_MSBDI_LBUS_PENDING_2 = 8894; // 1
+const static uint64_t SH_FLD_MSBDI_XDN_1 = 8895; // 1
+const static uint64_t SH_FLD_MSBDI_XDN_2 = 8896; // 1
+const static uint64_t SH_FLD_MSBSWAP = 8897; // 4
+const static uint64_t SH_FLD_MSG_ADDR_ERR = 8898; // 12
+const static uint64_t SH_FLD_MSK = 8899; // 4
+const static uint64_t SH_FLD_MSK_LEN = 8900; // 4
+const static uint64_t SH_FLD_MSM_CURR_STATE_0 = 8901; // 1
+const static uint64_t SH_FLD_MSM_CURR_STATE_0_LEN = 8902; // 1
+const static uint64_t SH_FLD_MSM_CURR_STATE_1 = 8903; // 1
+const static uint64_t SH_FLD_MSM_CURR_STATE_1_LEN = 8904; // 1
+const static uint64_t SH_FLD_MSM_CURR_STATE_2 = 8905; // 1
+const static uint64_t SH_FLD_MSM_CURR_STATE_2_LEN = 8906; // 1
+const static uint64_t SH_FLD_MSM_CURR_STATE_3 = 8907; // 1
+const static uint64_t SH_FLD_MSM_CURR_STATE_3_LEN = 8908; // 1
+const static uint64_t SH_FLD_MST_DIS_ABUSPAREN = 8909; // 1
+const static uint64_t SH_FLD_MST_DIS_BEPAREN = 8910; // 1
+const static uint64_t SH_FLD_MST_DIS_RDDBUSPAR = 8911; // 1
+const static uint64_t SH_FLD_MST_DIS_WRDBUSPAREN = 8912; // 1
+const static uint64_t SH_FLD_MST_SPARE = 8913; // 1
+const static uint64_t SH_FLD_MS_GROUP_CHIP = 8914; // 2
+const static uint64_t SH_FLD_MS_GROUP_CHIP_LEN = 8915; // 2
+const static uint64_t SH_FLD_MULTICAST1 = 8916; // 43
+const static uint64_t SH_FLD_MULTICAST1_LEN = 8917; // 43
+const static uint64_t SH_FLD_MULTICAST2 = 8918; // 43
+const static uint64_t SH_FLD_MULTICAST2_LEN = 8919; // 43
+const static uint64_t SH_FLD_MULTICAST3 = 8920; // 43
+const static uint64_t SH_FLD_MULTICAST3_LEN = 8921; // 43
+const static uint64_t SH_FLD_MULTICAST4 = 8922; // 43
+const static uint64_t SH_FLD_MULTICAST4_LEN = 8923; // 43
+const static uint64_t SH_FLD_MULTICAST_COMPARE_REGISTER = 8924; // 2
+const static uint64_t SH_FLD_MULTICAST_COMPARE_REGISTER_LEN = 8925; // 2
+const static uint64_t SH_FLD_MULTICAST_COMPARE_VALUE_REGISTER = 8926; // 1
+const static uint64_t SH_FLD_MULTICAST_COMPARE_VALUE_REGISTER_LEN = 8927; // 1
+const static uint64_t SH_FLD_MULTIPLE_BAR = 8928; // 4
+const static uint64_t SH_FLD_MULTIPLE_DIR_ERRORS_DETECTED = 8929; // 12
+const static uint64_t SH_FLD_MULTIPLE_REQ = 8930; // 8
+const static uint64_t SH_FLD_MULTIPLE_REQ_SOURCE = 8931; // 8
+const static uint64_t SH_FLD_MULTIPLE_REQ_SOURCE_LEN = 8932; // 8
+const static uint64_t SH_FLD_MULT_REQ_ERR_MASK = 8933; // 8
+const static uint64_t SH_FLD_MUOP_ERROR_1 = 8934; // 4
+const static uint64_t SH_FLD_MUOP_ERROR_2 = 8935; // 4
+const static uint64_t SH_FLD_MUOP_ERROR_3 = 8936; // 4
+const static uint64_t SH_FLD_MUXEN = 8937; // 4
+const static uint64_t SH_FLD_MUXSEL = 8938; // 4
+const static uint64_t SH_FLD_MUXSEL_LEN = 8939; // 4
+const static uint64_t SH_FLD_MUX_SELECT = 8940; // 2
+const static uint64_t SH_FLD_MUX_SELECT_LEN = 8941; // 2
+const static uint64_t SH_FLD_M_0_STEP_ALIGN_FSM_STATE = 8942; // 1
+const static uint64_t SH_FLD_M_0_STEP_ALIGN_FSM_STATE_LEN = 8943; // 1
+const static uint64_t SH_FLD_M_1_STEP_ALIGN_FSM_STATE = 8944; // 1
+const static uint64_t SH_FLD_M_1_STEP_ALIGN_FSM_STATE_LEN = 8945; // 1
+const static uint64_t SH_FLD_M_CPS_ENABLE = 8946; // 1
+const static uint64_t SH_FLD_M_PATH_0_OSC_NOT_VALID = 8947; // 1
+const static uint64_t SH_FLD_M_PATH_0_PARITY = 8948; // 4
+const static uint64_t SH_FLD_M_PATH_0_STEP_ALIGN_THRESHOLD_ENABLE = 8949; // 1
+const static uint64_t SH_FLD_M_PATH_0_STEP_ALIGN_VALID_SWITCH = 8950; // 1
+const static uint64_t SH_FLD_M_PATH_0_STEP_CHECK = 8951; // 4
+const static uint64_t SH_FLD_M_PATH_0_STEP_CHECK_VALID = 8952; // 1
+const static uint64_t SH_FLD_M_PATH_0_STEP_CREATE_THRESHOLD_ENABLE = 8953; // 1
+const static uint64_t SH_FLD_M_PATH_0_SYNC_CREATE_COUNTER_ENABLE = 8954; // 1
+const static uint64_t SH_FLD_M_PATH_1_OSC_NOT_VALID = 8955; // 1
+const static uint64_t SH_FLD_M_PATH_1_PARITY = 8956; // 4
+const static uint64_t SH_FLD_M_PATH_1_STEP_ALIGN_THRESHOLD_ENABLE = 8957; // 1
+const static uint64_t SH_FLD_M_PATH_1_STEP_ALIGN_VALID_SWITCH = 8958; // 1
+const static uint64_t SH_FLD_M_PATH_1_STEP_CHECK = 8959; // 4
+const static uint64_t SH_FLD_M_PATH_1_STEP_CHECK_VALID = 8960; // 1
+const static uint64_t SH_FLD_M_PATH_1_STEP_CREATE_THRESHOLD_ENABLE = 8961; // 1
+const static uint64_t SH_FLD_M_PATH_1_SYNC_CREATE_COUNTER_ENABLE = 8962; // 1
+const static uint64_t SH_FLD_M_PATH_CLOCK_OFF_ENABLE = 8963; // 1
+const static uint64_t SH_FLD_M_PATH_SELECT = 8964; // 1
+const static uint64_t SH_FLD_M_PATH_SWITCH_TRIGGER = 8965; // 1
+const static uint64_t SH_FLD_NACK_RECEIVED_ERROR_0 = 8966; // 2
+const static uint64_t SH_FLD_NACK_RECEIVED_ERROR_1 = 8967; // 2
+const static uint64_t SH_FLD_NACK_RECEIVED_ERROR_2 = 8968; // 2
+const static uint64_t SH_FLD_NACK_RECEIVED_ERROR_3 = 8969; // 2
+const static uint64_t SH_FLD_NB_CLEAN_SLOT = 8970; // 6
+const static uint64_t SH_FLD_NB_CLEAN_SLOT_LEN = 8971; // 6
+const static uint64_t SH_FLD_NB_WRITE_SLOT = 8972; // 6
+const static uint64_t SH_FLD_NB_WRITE_SLOT_LEN = 8973; // 6
+const static uint64_t SH_FLD_NCU_POWERBUS_DATA_TIMEOUT = 8974; // 12
+const static uint64_t SH_FLD_NCU_PURGE = 8975; // 12
+const static uint64_t SH_FLD_NCU_PURGE_ABORT = 8976; // 12
+const static uint64_t SH_FLD_NCU_PURGE_DONE = 8977; // 24
+const static uint64_t SH_FLD_NCU_TLBIE_QUIESCE = 8978; // 12
+const static uint64_t SH_FLD_NDL_PRI_PARITY_ENA = 8979; // 6
+const static uint64_t SH_FLD_NDL_RX_PARITY_ENA = 8980; // 6
+const static uint64_t SH_FLD_NDL_TX_PARITY_ENA = 8981; // 6
+const static uint64_t SH_FLD_NEAR_NODAL_EPSILON = 8982; // 8
+const static uint64_t SH_FLD_NEAR_NODAL_EPSILON_LEN = 8983; // 8
+const static uint64_t SH_FLD_NEST_DBG_SEL_IN = 8984; // 8
+const static uint64_t SH_FLD_NEST_DBG_SEL_WRT = 8985; // 8
+const static uint64_t SH_FLD_NEXT_RANK = 8986; // 8
+const static uint64_t SH_FLD_NEXT_RANK_LEN = 8987; // 8
+const static uint64_t SH_FLD_NEXT_RANK_PAIR = 8988; // 8
+const static uint64_t SH_FLD_NEXT_RANK_PAIR_LEN = 8989; // 8
+const static uint64_t SH_FLD_NFIRACTION0 = 8990; // 9
+const static uint64_t SH_FLD_NFIRACTION0_LEN = 8991; // 9
+const static uint64_t SH_FLD_NFIRACTION1 = 8992; // 9
+const static uint64_t SH_FLD_NFIRACTION1_LEN = 8993; // 9
+const static uint64_t SH_FLD_NMMU_LOCAL_XSTOP = 8994; // 1
+const static uint64_t SH_FLD_NONBAR_PE = 8995; // 9
+const static uint64_t SH_FLD_NONBAR_PE_MASK = 8996; // 9
+const static uint64_t SH_FLD_NONRD_ARE_ERRORS = 8997; // 9
+const static uint64_t SH_FLD_NONRD_ARE_ERRORS_MASK = 8998; // 9
+const static uint64_t SH_FLD_NONSLS_CNTR_TAP_PTS = 8999; // 4
+const static uint64_t SH_FLD_NONSLS_CNTR_TAP_PTS_LEN = 9000; // 4
+const static uint64_t SH_FLD_NONZERO_CSB_CC = 9001; // 1
+const static uint64_t SH_FLD_NOTIFY_FAILED_ERR = 9002; // 2
+const static uint64_t SH_FLD_NOT_USED_0 = 9003; // 1
+const static uint64_t SH_FLD_NOT_USED_0_LEN = 9004; // 1
+const static uint64_t SH_FLD_NOT_USED_1 = 9005; // 1
+const static uint64_t SH_FLD_NOT_USED_1_LEN = 9006; // 1
+const static uint64_t SH_FLD_NOT_USED_2 = 9007; // 1
+const static uint64_t SH_FLD_NOT_USED_2_LEN = 9008; // 1
+const static uint64_t SH_FLD_NOT_USED_3 = 9009; // 1
+const static uint64_t SH_FLD_NOT_USED_3_LEN = 9010; // 1
+const static uint64_t SH_FLD_NO_WAIT_ON_CLK_CMD = 9011; // 43
+const static uint64_t SH_FLD_NR_OF_FRAMES = 9012; // 1
+const static uint64_t SH_FLD_NSEG_MAIN_EN = 9013; // 6
+const static uint64_t SH_FLD_NSEG_MAIN_EN_LEN = 9014; // 6
+const static uint64_t SH_FLD_NSEG_MARGINPD_EN = 9015; // 6
+const static uint64_t SH_FLD_NSEG_MARGINPD_EN_LEN = 9016; // 6
+const static uint64_t SH_FLD_NSEG_MARGINPU_EN = 9017; // 6
+const static uint64_t SH_FLD_NSEG_MARGINPU_EN_LEN = 9018; // 6
+const static uint64_t SH_FLD_NSEG_POST_EN = 9019; // 2
+const static uint64_t SH_FLD_NSEG_POST_EN_LEN = 9020; // 2
+const static uint64_t SH_FLD_NSEG_POST_SEL = 9021; // 2
+const static uint64_t SH_FLD_NSEG_POST_SEL_LEN = 9022; // 2
+const static uint64_t SH_FLD_NSEG_PRE_EN = 9023; // 6
+const static uint64_t SH_FLD_NSEG_PRE_EN_LEN = 9024; // 6
+const static uint64_t SH_FLD_NSEG_PRE_SEL = 9025; // 6
+const static uint64_t SH_FLD_NSEG_PRE_SEL_LEN = 9026; // 6
+const static uint64_t SH_FLD_NSL_FILL_COUNT = 9027; // 43
+const static uint64_t SH_FLD_NSL_FILL_COUNT_LEN = 9028; // 43
+const static uint64_t SH_FLD_NTLR_PAUSE_THRESH = 9029; // 3
+const static uint64_t SH_FLD_NTLR_PAUSE_THRESH_LEN = 9030; // 3
+const static uint64_t SH_FLD_NTLW_PAUSE_THRESH = 9031; // 3
+const static uint64_t SH_FLD_NTLW_PAUSE_THRESH_LEN = 9032; // 3
+const static uint64_t SH_FLD_NTTM_MODE = 9033; // 2
+const static uint64_t SH_FLD_NTTM_RW_DATA_DLY = 9034; // 2
+const static uint64_t SH_FLD_NTTM_RW_DATA_DLY_LEN = 9035; // 2
+const static uint64_t SH_FLD_NULL_MSR_LP = 9036; // 40
+const static uint64_t SH_FLD_NULL_MSR_SIBRC = 9037; // 40
+const static uint64_t SH_FLD_NULL_MSR_SIBRC_LEN = 9038; // 40
+const static uint64_t SH_FLD_NULL_MSR_WE = 9039; // 40
+const static uint64_t SH_FLD_NUM_BLOCKS = 9040; // 12
+const static uint64_t SH_FLD_NUM_BLOCKS_LEN = 9041; // 12
+const static uint64_t SH_FLD_NUM_CL_ACTIVE = 9042; // 8
+const static uint64_t SH_FLD_NUM_CL_ACTIVE_LEN = 9043; // 8
+const static uint64_t SH_FLD_NUM_HA_RSVD = 9044; // 8
+const static uint64_t SH_FLD_NUM_HA_RSVD_LEN = 9045; // 8
+const static uint64_t SH_FLD_NUM_HA_RSVD_SEL = 9046; // 8
+const static uint64_t SH_FLD_NUM_HA_RSVD_SEL_LEN = 9047; // 8
+const static uint64_t SH_FLD_NUM_HPC_RD_RSVD = 9048; // 8
+const static uint64_t SH_FLD_NUM_HPC_RD_RSVD_LEN = 9049; // 8
+const static uint64_t SH_FLD_NUM_HTM_RSVD = 9050; // 8
+const static uint64_t SH_FLD_NUM_HTM_RSVD_LEN = 9051; // 8
+const static uint64_t SH_FLD_NUM_HTM_RSVD_SEL = 9052; // 8
+const static uint64_t SH_FLD_NUM_HTM_RSVD_SEL_LEN = 9053; // 8
+const static uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD = 9054; // 8
+const static uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD_LEN = 9055; // 8
+const static uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD_SEL = 9056; // 8
+const static uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD_SEL_LEN = 9057; // 8
+const static uint64_t SH_FLD_NUM_VALID_SAMPLES = 9058; // 8
+const static uint64_t SH_FLD_NUM_VALID_SAMPLES_LEN = 9059; // 8
+const static uint64_t SH_FLD_NXCQ_ERAT_ARRAY_ACTION = 9060; // 1
+const static uint64_t SH_FLD_NXCQ_ERAT_ARRAY_ENABLE = 9061; // 1
+const static uint64_t SH_FLD_NXCQ_ERAT_ARRAY_SELECT = 9062; // 1
+const static uint64_t SH_FLD_NXCQ_ERAT_ARRAY_SELECT_LEN = 9063; // 1
+const static uint64_t SH_FLD_NXCQ_ERAT_ARRAY_TYPE = 9064; // 1
+const static uint64_t SH_FLD_NXCQ_INJECT_MODE = 9065; // 2
+const static uint64_t SH_FLD_NXCQ_INJECT_MODE_LEN = 9066; // 2
+const static uint64_t SH_FLD_NXCQ_INJECT_TYPE = 9067; // 2
+const static uint64_t SH_FLD_NXCQ_INJECT_TYPE_LEN = 9068; // 2
+const static uint64_t SH_FLD_NXCQ_PBCQ_ARRAY = 9069; // 2
+const static uint64_t SH_FLD_NXCQ_PBCQ_ARRAY_LEN = 9070; // 2
+const static uint64_t SH_FLD_NXCQ_PBCQ_INJECT_ENABLE = 9071; // 2
+const static uint64_t SH_FLD_NXCQ_RNG_INJECT_ACTION = 9072; // 1
+const static uint64_t SH_FLD_NXCQ_RNG_INJECT_ENABLE = 9073; // 1
+const static uint64_t SH_FLD_NXCQ_TRACE_CNTL = 9074; // 2
+const static uint64_t SH_FLD_NXCQ_TRACE_CNTL_LEN = 9075; // 2
+const static uint64_t SH_FLD_NXWR_CFG = 9076; // 2
+const static uint64_t SH_FLD_NXWR_CFG_LEN = 9077; // 2
+const static uint64_t SH_FLD_NXWR_DISABLE_CP = 9078; // 2
+const static uint64_t SH_FLD_NX_FREEZE_MODES = 9079; // 1
+const static uint64_t SH_FLD_NX_FREEZE_MODES_LEN = 9080; // 1
+const static uint64_t SH_FLD_O = 9081; // 1
+const static uint64_t SH_FLD_O2SCMD_A_N_RESERVED_0 = 9082; // 4
+const static uint64_t SH_FLD_O2SCTRL1_A_N_RESERVED_1 = 9083; // 4
+const static uint64_t SH_FLD_O2SCTRL1_A_N_RESERVED_14_16 = 9084; // 4
+const static uint64_t SH_FLD_O2SCTRL1_A_N_RESERVED_14_16_LEN = 9085; // 4
+const static uint64_t SH_FLD_O2SST_A_N_RESERVED_1_4 = 9086; // 4
+const static uint64_t SH_FLD_O2SST_A_N_RESERVED_1_4_LEN = 9087; // 4
+const static uint64_t SH_FLD_O2SST_A_N_RESERVED_6 = 9088; // 4
+const static uint64_t SH_FLD_O2S_BRIDGE_ENABLE_A_N = 9089; // 4
+const static uint64_t SH_FLD_O2S_CLEAR_STICKY_BITS_A_N = 9090; // 4
+const static uint64_t SH_FLD_O2S_CLOCK_DIVIDER_A_N = 9091; // 4
+const static uint64_t SH_FLD_O2S_CLOCK_DIVIDER_A_N_LEN = 9092; // 4
+const static uint64_t SH_FLD_O2S_CPHA_A_N = 9093; // 4
+const static uint64_t SH_FLD_O2S_CPOL_A_N = 9094; // 4
+const static uint64_t SH_FLD_O2S_FRAME_SIZE_A_N = 9095; // 4
+const static uint64_t SH_FLD_O2S_FRAME_SIZE_A_N_LEN = 9096; // 4
+const static uint64_t SH_FLD_O2S_FSM_ERR_A_N = 9097; // 4
+const static uint64_t SH_FLD_O2S_INTER_FRAME_DELAY_A_N = 9098; // 4
+const static uint64_t SH_FLD_O2S_INTER_FRAME_DELAY_A_N_LEN = 9099; // 4
+const static uint64_t SH_FLD_O2S_IN_COUNT1_A_N = 9100; // 4
+const static uint64_t SH_FLD_O2S_IN_COUNT1_A_N_LEN = 9101; // 4
+const static uint64_t SH_FLD_O2S_IN_COUNT2_A_N = 9102; // 4
+const static uint64_t SH_FLD_O2S_IN_COUNT2_A_N_LEN = 9103; // 4
+const static uint64_t SH_FLD_O2S_IN_DELAY1_A_N = 9104; // 4
+const static uint64_t SH_FLD_O2S_IN_DELAY1_A_N_LEN = 9105; // 4
+const static uint64_t SH_FLD_O2S_IN_DELAY2_A_N = 9106; // 4
+const static uint64_t SH_FLD_O2S_IN_DELAY2_A_N_LEN = 9107; // 4
+const static uint64_t SH_FLD_O2S_NR_OF_FRAMES_A_N = 9108; // 4
+const static uint64_t SH_FLD_O2S_ONGOING_A_N = 9109; // 4
+const static uint64_t SH_FLD_O2S_OUT_COUNT1_A_N = 9110; // 4
+const static uint64_t SH_FLD_O2S_OUT_COUNT1_A_N_LEN = 9111; // 4
+const static uint64_t SH_FLD_O2S_OUT_COUNT2_A_N = 9112; // 4
+const static uint64_t SH_FLD_O2S_OUT_COUNT2_A_N_LEN = 9113; // 4
+const static uint64_t SH_FLD_O2S_RDATA_A_N = 9114; // 4
+const static uint64_t SH_FLD_O2S_RDATA_A_N_LEN = 9115; // 4
+const static uint64_t SH_FLD_O2S_WDATA_A_N = 9116; // 4
+const static uint64_t SH_FLD_O2S_WDATA_A_N_LEN = 9117; // 4
+const static uint64_t SH_FLD_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N = 9118; // 4
+const static uint64_t SH_FLD_OBWR_MASK = 9119; // 3
+const static uint64_t SH_FLD_OBWR_MASK_LEN = 9120; // 3
+const static uint64_t SH_FLD_OCC_ACTION_SET = 9121; // 1
+const static uint64_t SH_FLD_OCC_ACTION_SET_LEN = 9122; // 1
+const static uint64_t SH_FLD_OCC_ERROR = 9123; // 1
+const static uint64_t SH_FLD_OCC_FLAGS = 9124; // 1
+const static uint64_t SH_FLD_OCC_FLAGS_LEN = 9125; // 1
+const static uint64_t SH_FLD_OCC_HEARTBEAT_COUNT = 9126; // 7
+const static uint64_t SH_FLD_OCC_HEARTBEAT_COUNT_LEN = 9127; // 7
+const static uint64_t SH_FLD_OCC_HEARTBEAT_EN = 9128; // 1
+const static uint64_t SH_FLD_OCC_HEARTBEAT_ENABLE = 9129; // 6
+const static uint64_t SH_FLD_OCC_HEARTBEAT_LOSS = 9130; // 6
+const static uint64_t SH_FLD_OCC_HEARTBEAT_LOST = 9131; // 12
+const static uint64_t SH_FLD_OCC_INTERRUPT_VALUE = 9132; // 1
+const static uint64_t SH_FLD_OCC_INTERRUPT_VALUE_LEN = 9133; // 1
+const static uint64_t SH_FLD_OCC_MALF_ALERT = 9134; // 1
+const static uint64_t SH_FLD_OCC_PRIORITY = 9135; // 1
+const static uint64_t SH_FLD_OCC_PRIORITY_LEN = 9136; // 1
+const static uint64_t SH_FLD_OCC_SCRATCH_N = 9137; // 3
+const static uint64_t SH_FLD_OCC_SCRATCH_N_LEN = 9138; // 3
+const static uint64_t SH_FLD_OCC_SERVER_NUMBER = 9139; // 1
+const static uint64_t SH_FLD_OCC_SERVER_NUMBER_LEN = 9140; // 1
+const static uint64_t SH_FLD_OCC_SPCL_TIMEOUT_ADDR = 9141; // 1
+const static uint64_t SH_FLD_OCC_SPCL_TIMEOUT_ADDR_LEN = 9142; // 1
+const static uint64_t SH_FLD_OCC_SPECIAL_WKUP = 9143; // 30
+const static uint64_t SH_FLD_OCC_STRM0_PULL = 9144; // 1
+const static uint64_t SH_FLD_OCC_STRM0_PUSH = 9145; // 1
+const static uint64_t SH_FLD_OCC_STRM1_PULL = 9146; // 1
+const static uint64_t SH_FLD_OCC_STRM1_PUSH = 9147; // 1
+const static uint64_t SH_FLD_OCC_STRM2_PULL = 9148; // 1
+const static uint64_t SH_FLD_OCC_STRM2_PUSH = 9149; // 1
+const static uint64_t SH_FLD_OCC_STRM3_PULL = 9150; // 1
+const static uint64_t SH_FLD_OCC_STRM3_PUSH = 9151; // 1
+const static uint64_t SH_FLD_OCC_TIMER0 = 9152; // 1
+const static uint64_t SH_FLD_OCC_TIMER1 = 9153; // 1
+const static uint64_t SH_FLD_OCC_TRACE_MUX_SEL = 9154; // 1
+const static uint64_t SH_FLD_OCC_TRACE_MUX_SEL_LEN = 9155; // 1
+const static uint64_t SH_FLD_OCICFG_RESERVED_20 = 9156; // 1
+const static uint64_t SH_FLD_OCICFG_RESERVED_23 = 9157; // 1
+const static uint64_t SH_FLD_OCISLV_FAIRNESS_MASK = 9158; // 1
+const static uint64_t SH_FLD_OCISLV_FAIRNESS_MASK_LEN = 9159; // 1
+const static uint64_t SH_FLD_OCISLV_REREQ_HANG_DIV = 9160; // 1
+const static uint64_t SH_FLD_OCISLV_REREQ_HANG_DIV_LEN = 9161; // 1
+const static uint64_t SH_FLD_OCI_APAR_ERR = 9162; // 1
+const static uint64_t SH_FLD_OCI_APAR_ERR_MASK = 9163; // 1
+const static uint64_t SH_FLD_OCI_ARB_RESET = 9164; // 1
+const static uint64_t SH_FLD_OCI_BAD_REG_ADDR = 9165; // 1
+const static uint64_t SH_FLD_OCI_BAD_REG_ADDR_MASK = 9166; // 1
+const static uint64_t SH_FLD_OCI_ERR_INJ_CE_UE = 9167; // 1
+const static uint64_t SH_FLD_OCI_ERR_INJ_DCU = 9168; // 1
+const static uint64_t SH_FLD_OCI_ERR_INJ_ICU = 9169; // 1
+const static uint64_t SH_FLD_OCI_ERR_INJ_SINGL_CONT = 9170; // 1
+const static uint64_t SH_FLD_OCI_HI_BUS_MODE = 9171; // 1
+const static uint64_t SH_FLD_OCI_M0_FLCK = 9172; // 1
+const static uint64_t SH_FLD_OCI_M0_OEAR_LOCK = 9173; // 1
+const static uint64_t SH_FLD_OCI_M0_RW_STATUS = 9174; // 1
+const static uint64_t SH_FLD_OCI_M0_TIMEOUT_ERROR = 9175; // 1
+const static uint64_t SH_FLD_OCI_M1_FLCK = 9176; // 1
+const static uint64_t SH_FLD_OCI_M1_OEAR_LOCK = 9177; // 1
+const static uint64_t SH_FLD_OCI_M1_RW_STATUS = 9178; // 1
+const static uint64_t SH_FLD_OCI_M1_TIMEOUT_ERROR = 9179; // 1
+const static uint64_t SH_FLD_OCI_M2_FLCK = 9180; // 1
+const static uint64_t SH_FLD_OCI_M2_OEAR_LOCK = 9181; // 1
+const static uint64_t SH_FLD_OCI_M2_RW_STATUS = 9182; // 1
+const static uint64_t SH_FLD_OCI_M2_TIMEOUT_ERROR = 9183; // 1
+const static uint64_t SH_FLD_OCI_M3_FLCK = 9184; // 1
+const static uint64_t SH_FLD_OCI_M3_OEAR_LOCK = 9185; // 1
+const static uint64_t SH_FLD_OCI_M3_RW_STATUS = 9186; // 1
+const static uint64_t SH_FLD_OCI_M3_TIMEOUT_ERROR = 9187; // 1
+const static uint64_t SH_FLD_OCI_M4_FLCK = 9188; // 1
+const static uint64_t SH_FLD_OCI_M4_OEAR_LOCK = 9189; // 1
+const static uint64_t SH_FLD_OCI_M4_RW_STATUS = 9190; // 1
+const static uint64_t SH_FLD_OCI_M4_TIMEOUT_ERROR = 9191; // 1
+const static uint64_t SH_FLD_OCI_M5_FLCK = 9192; // 1
+const static uint64_t SH_FLD_OCI_M5_OEAR_LOCK = 9193; // 1
+const static uint64_t SH_FLD_OCI_M5_RW_STATUS = 9194; // 1
+const static uint64_t SH_FLD_OCI_M5_TIMEOUT_ERROR = 9195; // 1
+const static uint64_t SH_FLD_OCI_M6_FLCK = 9196; // 1
+const static uint64_t SH_FLD_OCI_M6_OEAR_LOCK = 9197; // 1
+const static uint64_t SH_FLD_OCI_M6_RW_STATUS = 9198; // 1
+const static uint64_t SH_FLD_OCI_M6_TIMEOUT_ERROR = 9199; // 1
+const static uint64_t SH_FLD_OCI_M7_FLCK = 9200; // 1
+const static uint64_t SH_FLD_OCI_M7_OEAR_LOCK = 9201; // 1
+const static uint64_t SH_FLD_OCI_M7_RW_STATUS = 9202; // 1
+const static uint64_t SH_FLD_OCI_M7_TIMEOUT_ERROR = 9203; // 1
+const static uint64_t SH_FLD_OCI_MARKER_SPACE = 9204; // 1
+const static uint64_t SH_FLD_OCI_MARKER_SPACE_LEN = 9205; // 1
+const static uint64_t SH_FLD_OCI_PRIORITY_MODE = 9206; // 1
+const static uint64_t SH_FLD_OCI_PRIORITY_ORDER = 9207; // 1
+const static uint64_t SH_FLD_OCI_PRIORITY_ORDER_LEN = 9208; // 1
+const static uint64_t SH_FLD_OCI_READ_DATA_PARITY = 9209; // 4
+const static uint64_t SH_FLD_OCI_READ_PIPELINE_CONTROL = 9210; // 1
+const static uint64_t SH_FLD_OCI_READ_PIPELINE_CONTROL_LEN = 9211; // 1
+const static uint64_t SH_FLD_OCI_REGION = 9212; // 4
+const static uint64_t SH_FLD_OCI_REGION_LEN = 9213; // 4
+const static uint64_t SH_FLD_OCI_SLAVE_ERROR = 9214; // 4
+const static uint64_t SH_FLD_OCI_SLAVE_INIT = 9215; // 1
+const static uint64_t SH_FLD_OCI_SLAVE_INIT_MASK = 9216; // 1
+const static uint64_t SH_FLD_OCI_TIMEOUT = 9217; // 4
+const static uint64_t SH_FLD_OCI_TIMEOUT_ADDR = 9218; // 1
+const static uint64_t SH_FLD_OCI_TIMEOUT_ADDR_LEN = 9219; // 1
+const static uint64_t SH_FLD_OCI_TRACE_MUX_SEL = 9220; // 1
+const static uint64_t SH_FLD_OCI_TRACE_MUX_SEL_LEN = 9221; // 1
+const static uint64_t SH_FLD_OCI_WRITE_PIPELINE_CONTROL = 9222; // 1
+const static uint64_t SH_FLD_OCI_WRPAR_ERR = 9223; // 1
+const static uint64_t SH_FLD_OCI_WRPAR_ERR_MASK = 9224; // 1
+const static uint64_t SH_FLD_OCR_DBG_HALT = 9225; // 1
+const static uint64_t SH_FLD_OFFSET = 9226; // 9
+const static uint64_t SH_FLD_OFFSET_LEN = 9227; // 9
+const static uint64_t SH_FLD_OFF_INIT_CFG = 9228; // 6
+const static uint64_t SH_FLD_OFF_INIT_CFG_LEN = 9229; // 6
+const static uint64_t SH_FLD_OFF_INIT_TIMEOUT = 9230; // 6
+const static uint64_t SH_FLD_OFF_INIT_TIMEOUT_LEN = 9231; // 6
+const static uint64_t SH_FLD_OFF_RECAL_CFG = 9232; // 6
+const static uint64_t SH_FLD_OFF_RECAL_CFG_LEN = 9233; // 6
+const static uint64_t SH_FLD_OFF_RECAL_TIMEOUT = 9234; // 6
+const static uint64_t SH_FLD_OFF_RECAL_TIMEOUT_LEN = 9235; // 6
+const static uint64_t SH_FLD_OJCFG_DBG_HALT = 9236; // 1
+const static uint64_t SH_FLD_OJCFG_JTAG_SRC_SEL = 9237; // 1
+const static uint64_t SH_FLD_OJCFG_JTAG_TRST_B = 9238; // 1
+const static uint64_t SH_FLD_OJCFG_RUN_TCK = 9239; // 1
+const static uint64_t SH_FLD_OJCFG_TCK_WIDTH = 9240; // 1
+const static uint64_t SH_FLD_OJCFG_TCK_WIDTH_LEN = 9241; // 1
+const static uint64_t SH_FLD_OJIC_DO_DR = 9242; // 1
+const static uint64_t SH_FLD_OJIC_DO_IR = 9243; // 1
+const static uint64_t SH_FLD_OJIC_DO_TAP_RESET = 9244; // 1
+const static uint64_t SH_FLD_OJIC_JTAG_INSTR = 9245; // 1
+const static uint64_t SH_FLD_OJIC_JTAG_INSTR_LEN = 9246; // 1
+const static uint64_t SH_FLD_OJIC_WR_VALID = 9247; // 1
+const static uint64_t SH_FLD_OJSTAT_FSM_ERROR = 9248; // 1
+const static uint64_t SH_FLD_OJSTAT_INPROG_WR_ERR = 9249; // 1
+const static uint64_t SH_FLD_OJSTAT_IR_DR_EQ0_ERR = 9250; // 1
+const static uint64_t SH_FLD_OJSTAT_JTAG_INPROG = 9251; // 1
+const static uint64_t SH_FLD_OJSTAT_RUN_TCK_EQ0_ERR = 9252; // 1
+const static uint64_t SH_FLD_OJSTAT_SRC_SEL_EQ1_ERR = 9253; // 1
+const static uint64_t SH_FLD_OJSTAT_TRST_B_EQ0_ERR = 9254; // 1
+const static uint64_t SH_FLD_ONE_PPC = 9255; // 24
+const static uint64_t SH_FLD_ONGOING = 9256; // 1
+const static uint64_t SH_FLD_ONL = 9257; // 96
+const static uint64_t SH_FLD_OOB_MUX = 9258; // 1
+const static uint64_t SH_FLD_OPB_ERROR = 9259; // 4
+const static uint64_t SH_FLD_OPB_MASTER_HANG_TIMEOUT = 9260; // 4
+const static uint64_t SH_FLD_OPB_PARITY_ERROR = 9261; // 3
+const static uint64_t SH_FLD_OPB_TIMEOUT = 9262; // 4
+const static uint64_t SH_FLD_OPCG_IP = 9263; // 43
+const static uint64_t SH_FLD_OPCODE = 9264; // 1
+const static uint64_t SH_FLD_OPCODE_LEN = 9265; // 1
+const static uint64_t SH_FLD_OPER = 9266; // 1
+const static uint64_t SH_FLD_OPER_LEN = 9267; // 1
+const static uint64_t SH_FLD_OPTION_PIB_RESET = 9268; // 1
+const static uint64_t SH_FLD_OSCILLATOR = 9269; // 1
+const static uint64_t SH_FLD_OSCILLATOR_LEN = 9270; // 1
+const static uint64_t SH_FLD_OSCSWITCH_CNTL0_DC = 9271; // 1
+const static uint64_t SH_FLD_OSCSWITCH_CNTL0_DC_LEN = 9272; // 1
+const static uint64_t SH_FLD_OSCSWITCH_CNTL1_DC = 9273; // 1
+const static uint64_t SH_FLD_OSCSWITCH_CNTL1_DC_LEN = 9274; // 1
+const static uint64_t SH_FLD_OSCSWITCH_INTERRUPT = 9275; // 4
+const static uint64_t SH_FLD_OS_STATUS_DISABLE_A_N = 9276; // 96
+const static uint64_t SH_FLD_OTHER_SCOM_SAT = 9277; // 1
+const static uint64_t SH_FLD_OTHR_SPECIAL_WKUP = 9278; // 30
+const static uint64_t SH_FLD_OTP = 9279; // 1
+const static uint64_t SH_FLD_OTP_LEN = 9280; // 1
+const static uint64_t SH_FLD_OUT = 9281; // 1
+const static uint64_t SH_FLD_OUTER_LOOP_CNT = 9282; // 8
+const static uint64_t SH_FLD_OUTER_LOOP_CNT_LEN = 9283; // 8
+const static uint64_t SH_FLD_OUTWR_INRD_ECC_CE = 9284; // 1
+const static uint64_t SH_FLD_OUTWR_INRD_ECC_SUE = 9285; // 1
+const static uint64_t SH_FLD_OUTWR_INRD_ECC_UE = 9286; // 1
+const static uint64_t SH_FLD_OUT_COUNT1 = 9287; // 1
+const static uint64_t SH_FLD_OUT_COUNT1_LEN = 9288; // 1
+const static uint64_t SH_FLD_OUT_COUNT2 = 9289; // 1
+const static uint64_t SH_FLD_OUT_COUNT2_LEN = 9290; // 1
+const static uint64_t SH_FLD_OUT_LEN = 9291; // 1
+const static uint64_t SH_FLD_OVERFLOW_ERR = 9292; // 43
+const static uint64_t SH_FLD_OVERFLOW_MASK = 9293; // 43
+const static uint64_t SH_FLD_OVERRIDE = 9294; // 8
+const static uint64_t SH_FLD_OVERRIDE_EN = 9295; // 24
+const static uint64_t SH_FLD_OVERRIDE_PBINIT_ERR_CMD = 9296; // 1
+const static uint64_t SH_FLD_OVERRIDE_PBINIT_HTM_CMD = 9297; // 1
+const static uint64_t SH_FLD_OVERRIDE_PBINIT_TOD_CMD = 9298; // 1
+const static uint64_t SH_FLD_OVERRIDE_PBINIT_TRACE_CMD = 9299; // 1
+const static uint64_t SH_FLD_OVERRIDE_PBINIT_XSCOM_CMD = 9300; // 1
+const static uint64_t SH_FLD_OVERRUN = 9301; // 8
+const static uint64_t SH_FLD_OVER_OR_UNDERRUN_ERR = 9302; // 1
+const static uint64_t SH_FLD_OWN_ID_THIS_SLAVE = 9303; // 2
+const static uint64_t SH_FLD_OWN_ID_THIS_SLAVE_LEN = 9304; // 2
+const static uint64_t SH_FLD_P0_IS_IDLE = 9305; // 3
+const static uint64_t SH_FLD_P1_IS_IDLE = 9306; // 3
+const static uint64_t SH_FLD_PACE = 9307; // 2
+const static uint64_t SH_FLD_PACE_LEN = 9308; // 2
+const static uint64_t SH_FLD_PACE_RATE = 9309; // 1
+const static uint64_t SH_FLD_PACE_RATE_LEN = 9310; // 1
+const static uint64_t SH_FLD_PACING_ALLOW = 9311; // 1
+const static uint64_t SH_FLD_PACING_ALLOW_0 = 9312; // 1
+const static uint64_t SH_FLD_PACING_ALLOW_1 = 9313; // 1
+const static uint64_t SH_FLD_PACING_ALLOW_2 = 9314; // 1
+const static uint64_t SH_FLD_PACING_ALLOW_3 = 9315; // 1
+const static uint64_t SH_FLD_PAGE_OFFSET_CFG = 9316; // 1
+const static uint64_t SH_FLD_PAGE_OFFSET_CFG_LEN = 9317; // 1
+const static uint64_t SH_FLD_PAGE_SIZE_64K = 9318; // 1
+const static uint64_t SH_FLD_PAGE_SIZE_64K_IC = 9319; // 1
+const static uint64_t SH_FLD_PAGE_SIZE_64K_PC = 9320; // 1
+const static uint64_t SH_FLD_PAGE_SIZE_64K_TM = 9321; // 1
+const static uint64_t SH_FLD_PAGE_SIZE_64K_VC = 9322; // 1
+const static uint64_t SH_FLD_PAIR0_QUA = 9323; // 8
+const static uint64_t SH_FLD_PAIR0_QUA_LEN = 9324; // 8
+const static uint64_t SH_FLD_PAIR0_QUA_V = 9325; // 8
+const static uint64_t SH_FLD_PAIR0_TER = 9326; // 8
+const static uint64_t SH_FLD_PAIR0_TER_LEN = 9327; // 8
+const static uint64_t SH_FLD_PAIR0_TER_V = 9328; // 8
+const static uint64_t SH_FLD_PAIR1_PRI = 9329; // 8
+const static uint64_t SH_FLD_PAIR1_PRI_LEN = 9330; // 8
+const static uint64_t SH_FLD_PAIR1_PRI_V = 9331; // 8
+const static uint64_t SH_FLD_PAIR1_QUA = 9332; // 8
+const static uint64_t SH_FLD_PAIR1_QUA_LEN = 9333; // 8
+const static uint64_t SH_FLD_PAIR1_QUA_V = 9334; // 8
+const static uint64_t SH_FLD_PAIR1_SEC = 9335; // 8
+const static uint64_t SH_FLD_PAIR1_SEC_LEN = 9336; // 8
+const static uint64_t SH_FLD_PAIR1_SEC_V = 9337; // 8
+const static uint64_t SH_FLD_PAIR1_TER = 9338; // 8
+const static uint64_t SH_FLD_PAIR1_TER_LEN = 9339; // 8
+const static uint64_t SH_FLD_PAIR1_TER_V = 9340; // 8
+const static uint64_t SH_FLD_PAIR2_PRI = 9341; // 8
+const static uint64_t SH_FLD_PAIR2_PRI_LEN = 9342; // 8
+const static uint64_t SH_FLD_PAIR2_PRI_V = 9343; // 8
+const static uint64_t SH_FLD_PAIR2_QUA = 9344; // 8
+const static uint64_t SH_FLD_PAIR2_QUA_LEN = 9345; // 8
+const static uint64_t SH_FLD_PAIR2_QUA_V = 9346; // 8
+const static uint64_t SH_FLD_PAIR2_SEC = 9347; // 8
+const static uint64_t SH_FLD_PAIR2_SEC_LEN = 9348; // 8
+const static uint64_t SH_FLD_PAIR2_SEC_V = 9349; // 8
+const static uint64_t SH_FLD_PAIR2_TER = 9350; // 8
+const static uint64_t SH_FLD_PAIR2_TER_LEN = 9351; // 8
+const static uint64_t SH_FLD_PAIR2_TER_V = 9352; // 8
+const static uint64_t SH_FLD_PAIR3_PRI = 9353; // 8
+const static uint64_t SH_FLD_PAIR3_PRI_LEN = 9354; // 8
+const static uint64_t SH_FLD_PAIR3_PRI_V = 9355; // 8
+const static uint64_t SH_FLD_PAIR3_SEC = 9356; // 8
+const static uint64_t SH_FLD_PAIR3_SEC_LEN = 9357; // 8
+const static uint64_t SH_FLD_PAIR3_SEC_V = 9358; // 8
+const static uint64_t SH_FLD_PARANOIA_TEST_ENABLE_CHANGE = 9359; // 43
+const static uint64_t SH_FLD_PARANOIA_VITL_CLKOFF_CHANGE = 9360; // 43
+const static uint64_t SH_FLD_PARITY = 9361; // 45
+const static uint64_t SH_FLD_PARITY_CHECK = 9362; // 1
+const static uint64_t SH_FLD_PARITY_ERR = 9363; // 3
+const static uint64_t SH_FLD_PARITY_ERR2 = 9364; // 2
+const static uint64_t SH_FLD_PARITY_ERROR = 9365; // 51
+const static uint64_t SH_FLD_PARITY_ERROR_SUE_ENA = 9366; // 6
+const static uint64_t SH_FLD_PARITY_ERR_MASK2 = 9367; // 1
+const static uint64_t SH_FLD_PARSER00_ATTN = 9368; // 4
+const static uint64_t SH_FLD_PARSER01_ATTN = 9369; // 4
+const static uint64_t SH_FLD_PARSER02_ATTN = 9370; // 4
+const static uint64_t SH_FLD_PARSER03_ATTN = 9371; // 4
+const static uint64_t SH_FLD_PARSER04_ATTN = 9372; // 4
+const static uint64_t SH_FLD_PARSER05_ATTN = 9373; // 4
+const static uint64_t SH_FLD_PARSER06_ATTN = 9374; // 2
+const static uint64_t SH_FLD_PARSER07_ATTN = 9375; // 2
+const static uint64_t SH_FLD_PART_0 = 9376; // 2
+const static uint64_t SH_FLD_PART_0_LEN = 9377; // 2
+const static uint64_t SH_FLD_PART_1 = 9378; // 2
+const static uint64_t SH_FLD_PART_10 = 9379; // 2
+const static uint64_t SH_FLD_PART_10_LEN = 9380; // 2
+const static uint64_t SH_FLD_PART_11 = 9381; // 2
+const static uint64_t SH_FLD_PART_11_LEN = 9382; // 2
+const static uint64_t SH_FLD_PART_12 = 9383; // 2
+const static uint64_t SH_FLD_PART_12_LEN = 9384; // 2
+const static uint64_t SH_FLD_PART_13 = 9385; // 2
+const static uint64_t SH_FLD_PART_13_LEN = 9386; // 2
+const static uint64_t SH_FLD_PART_14 = 9387; // 2
+const static uint64_t SH_FLD_PART_14_LEN = 9388; // 2
+const static uint64_t SH_FLD_PART_15 = 9389; // 2
+const static uint64_t SH_FLD_PART_15_LEN = 9390; // 2
+const static uint64_t SH_FLD_PART_16 = 9391; // 2
+const static uint64_t SH_FLD_PART_16_LEN = 9392; // 2
+const static uint64_t SH_FLD_PART_17 = 9393; // 2
+const static uint64_t SH_FLD_PART_17_LEN = 9394; // 2
+const static uint64_t SH_FLD_PART_18 = 9395; // 2
+const static uint64_t SH_FLD_PART_18_LEN = 9396; // 2
+const static uint64_t SH_FLD_PART_19 = 9397; // 2
+const static uint64_t SH_FLD_PART_19_LEN = 9398; // 2
+const static uint64_t SH_FLD_PART_1_LEN = 9399; // 2
+const static uint64_t SH_FLD_PART_2 = 9400; // 2
+const static uint64_t SH_FLD_PART_20 = 9401; // 2
+const static uint64_t SH_FLD_PART_20_LEN = 9402; // 2
+const static uint64_t SH_FLD_PART_21 = 9403; // 2
+const static uint64_t SH_FLD_PART_21_LEN = 9404; // 2
+const static uint64_t SH_FLD_PART_22 = 9405; // 2
+const static uint64_t SH_FLD_PART_22_LEN = 9406; // 2
+const static uint64_t SH_FLD_PART_23 = 9407; // 2
+const static uint64_t SH_FLD_PART_23_LEN = 9408; // 2
+const static uint64_t SH_FLD_PART_24 = 9409; // 2
+const static uint64_t SH_FLD_PART_24_LEN = 9410; // 2
+const static uint64_t SH_FLD_PART_25 = 9411; // 2
+const static uint64_t SH_FLD_PART_25_LEN = 9412; // 2
+const static uint64_t SH_FLD_PART_26 = 9413; // 2
+const static uint64_t SH_FLD_PART_26_LEN = 9414; // 2
+const static uint64_t SH_FLD_PART_27 = 9415; // 2
+const static uint64_t SH_FLD_PART_27_LEN = 9416; // 2
+const static uint64_t SH_FLD_PART_28 = 9417; // 2
+const static uint64_t SH_FLD_PART_28_LEN = 9418; // 2
+const static uint64_t SH_FLD_PART_29 = 9419; // 2
+const static uint64_t SH_FLD_PART_29_LEN = 9420; // 2
+const static uint64_t SH_FLD_PART_2_LEN = 9421; // 2
+const static uint64_t SH_FLD_PART_3 = 9422; // 2
+const static uint64_t SH_FLD_PART_30 = 9423; // 2
+const static uint64_t SH_FLD_PART_30_LEN = 9424; // 2
+const static uint64_t SH_FLD_PART_31 = 9425; // 2
+const static uint64_t SH_FLD_PART_31_LEN = 9426; // 2
+const static uint64_t SH_FLD_PART_32 = 9427; // 2
+const static uint64_t SH_FLD_PART_32_LEN = 9428; // 2
+const static uint64_t SH_FLD_PART_33 = 9429; // 2
+const static uint64_t SH_FLD_PART_33_LEN = 9430; // 2
+const static uint64_t SH_FLD_PART_34 = 9431; // 2
+const static uint64_t SH_FLD_PART_34_LEN = 9432; // 2
+const static uint64_t SH_FLD_PART_35 = 9433; // 2
+const static uint64_t SH_FLD_PART_35_LEN = 9434; // 2
+const static uint64_t SH_FLD_PART_36 = 9435; // 2
+const static uint64_t SH_FLD_PART_36_LEN = 9436; // 2
+const static uint64_t SH_FLD_PART_37 = 9437; // 2
+const static uint64_t SH_FLD_PART_37_LEN = 9438; // 2
+const static uint64_t SH_FLD_PART_38 = 9439; // 2
+const static uint64_t SH_FLD_PART_38_LEN = 9440; // 2
+const static uint64_t SH_FLD_PART_39 = 9441; // 2
+const static uint64_t SH_FLD_PART_39_LEN = 9442; // 2
+const static uint64_t SH_FLD_PART_3_LEN = 9443; // 2
+const static uint64_t SH_FLD_PART_4 = 9444; // 2
+const static uint64_t SH_FLD_PART_40 = 9445; // 2
+const static uint64_t SH_FLD_PART_40_LEN = 9446; // 2
+const static uint64_t SH_FLD_PART_41 = 9447; // 2
+const static uint64_t SH_FLD_PART_41_LEN = 9448; // 2
+const static uint64_t SH_FLD_PART_42 = 9449; // 2
+const static uint64_t SH_FLD_PART_42_LEN = 9450; // 2
+const static uint64_t SH_FLD_PART_43 = 9451; // 2
+const static uint64_t SH_FLD_PART_43_LEN = 9452; // 2
+const static uint64_t SH_FLD_PART_44 = 9453; // 2
+const static uint64_t SH_FLD_PART_44_LEN = 9454; // 2
+const static uint64_t SH_FLD_PART_45 = 9455; // 2
+const static uint64_t SH_FLD_PART_45_LEN = 9456; // 2
+const static uint64_t SH_FLD_PART_46 = 9457; // 2
+const static uint64_t SH_FLD_PART_46_LEN = 9458; // 2
+const static uint64_t SH_FLD_PART_47 = 9459; // 2
+const static uint64_t SH_FLD_PART_47_LEN = 9460; // 2
+const static uint64_t SH_FLD_PART_48 = 9461; // 2
+const static uint64_t SH_FLD_PART_48_LEN = 9462; // 2
+const static uint64_t SH_FLD_PART_49 = 9463; // 2
+const static uint64_t SH_FLD_PART_49_LEN = 9464; // 2
+const static uint64_t SH_FLD_PART_4_LEN = 9465; // 2
+const static uint64_t SH_FLD_PART_5 = 9466; // 2
+const static uint64_t SH_FLD_PART_50 = 9467; // 2
+const static uint64_t SH_FLD_PART_50_LEN = 9468; // 2
+const static uint64_t SH_FLD_PART_51 = 9469; // 2
+const static uint64_t SH_FLD_PART_51_LEN = 9470; // 2
+const static uint64_t SH_FLD_PART_52 = 9471; // 2
+const static uint64_t SH_FLD_PART_52_LEN = 9472; // 2
+const static uint64_t SH_FLD_PART_53 = 9473; // 2
+const static uint64_t SH_FLD_PART_53_LEN = 9474; // 2
+const static uint64_t SH_FLD_PART_54 = 9475; // 2
+const static uint64_t SH_FLD_PART_54_LEN = 9476; // 2
+const static uint64_t SH_FLD_PART_55 = 9477; // 2
+const static uint64_t SH_FLD_PART_55_LEN = 9478; // 2
+const static uint64_t SH_FLD_PART_56 = 9479; // 2
+const static uint64_t SH_FLD_PART_56_LEN = 9480; // 2
+const static uint64_t SH_FLD_PART_57 = 9481; // 2
+const static uint64_t SH_FLD_PART_57_LEN = 9482; // 2
+const static uint64_t SH_FLD_PART_58 = 9483; // 2
+const static uint64_t SH_FLD_PART_58_LEN = 9484; // 2
+const static uint64_t SH_FLD_PART_59 = 9485; // 2
+const static uint64_t SH_FLD_PART_59_LEN = 9486; // 2
+const static uint64_t SH_FLD_PART_5_LEN = 9487; // 2
+const static uint64_t SH_FLD_PART_6 = 9488; // 2
+const static uint64_t SH_FLD_PART_60 = 9489; // 2
+const static uint64_t SH_FLD_PART_60_LEN = 9490; // 2
+const static uint64_t SH_FLD_PART_61 = 9491; // 2
+const static uint64_t SH_FLD_PART_61_LEN = 9492; // 2
+const static uint64_t SH_FLD_PART_62 = 9493; // 2
+const static uint64_t SH_FLD_PART_62_LEN = 9494; // 2
+const static uint64_t SH_FLD_PART_63 = 9495; // 2
+const static uint64_t SH_FLD_PART_63_LEN = 9496; // 2
+const static uint64_t SH_FLD_PART_6_LEN = 9497; // 2
+const static uint64_t SH_FLD_PART_7 = 9498; // 2
+const static uint64_t SH_FLD_PART_7_LEN = 9499; // 2
+const static uint64_t SH_FLD_PART_8 = 9500; // 2
+const static uint64_t SH_FLD_PART_8_LEN = 9501; // 2
+const static uint64_t SH_FLD_PART_9 = 9502; // 2
+const static uint64_t SH_FLD_PART_9_LEN = 9503; // 2
+const static uint64_t SH_FLD_PAR_17_MASK = 9504; // 8
+const static uint64_t SH_FLD_PAR_INVERT = 9505; // 8
+const static uint64_t SH_FLD_PASS_CQ_INT_PMU_DATA_HI = 9506; // 1
+const static uint64_t SH_FLD_PASS_CQ_INT_PMU_DATA_LO = 9507; // 1
+const static uint64_t SH_FLD_PASS_CQ_INT_TRACE_DATA_HI = 9508; // 1
+const static uint64_t SH_FLD_PASS_CQ_INT_TRACE_DATA_LO = 9509; // 1
+const static uint64_t SH_FLD_PASS_CQ_INT_TRACE_TRIG_01 = 9510; // 1
+const static uint64_t SH_FLD_PASS_CQ_INT_TRACE_TRIG_23 = 9511; // 1
+const static uint64_t SH_FLD_PASS_WC_INT_PMU_DATA_HI = 9512; // 1
+const static uint64_t SH_FLD_PASS_WC_INT_PMU_DATA_LO = 9513; // 1
+const static uint64_t SH_FLD_PASS_WC_INT_TRACE_DATA_HI = 9514; // 1
+const static uint64_t SH_FLD_PASS_WC_INT_TRACE_DATA_LO = 9515; // 1
+const static uint64_t SH_FLD_PASS_WC_INT_TRACE_TRIG_01 = 9516; // 1
+const static uint64_t SH_FLD_PASS_WC_INT_TRACE_TRIG_23 = 9517; // 1
+const static uint64_t SH_FLD_PASTE_ADDR_ALIGN = 9518; // 1
+const static uint64_t SH_FLD_PASTE_REJECT = 9519; // 1
+const static uint64_t SH_FLD_PATTERNA = 9520; // 90
+const static uint64_t SH_FLD_PATTERNA_LEN = 9521; // 90
+const static uint64_t SH_FLD_PATTERNB = 9522; // 90
+const static uint64_t SH_FLD_PATTERNB_LEN = 9523; // 90
+const static uint64_t SH_FLD_PATTERNC = 9524; // 90
+const static uint64_t SH_FLD_PATTERNC_LEN = 9525; // 90
+const static uint64_t SH_FLD_PATTERND = 9526; // 90
+const static uint64_t SH_FLD_PATTERND_LEN = 9527; // 90
+const static uint64_t SH_FLD_PATTERN_CHECK_EN = 9528; // 1
+const static uint64_t SH_FLD_PATTERN_SEL = 9529; // 2
+const static uint64_t SH_FLD_PATTERN_SEL_LEN = 9530; // 2
+const static uint64_t SH_FLD_PAYLOAD = 9531; // 1
+const static uint64_t SH_FLD_PAYLOAD_LEN = 9532; // 1
+const static uint64_t SH_FLD_PB = 9533; // 4
+const static uint64_t SH_FLD_PBASE = 9534; // 4
+const static uint64_t SH_FLD_PBASE_LEN = 9535; // 4
+const static uint64_t SH_FLD_PBAX_EN = 9536; // 1
+const static uint64_t SH_FLD_PBAX_OCC_PUSH0 = 9537; // 1
+const static uint64_t SH_FLD_PBAX_OCC_PUSH1 = 9538; // 1
+const static uint64_t SH_FLD_PBAX_OCC_SEND_ATTN = 9539; // 1
+const static uint64_t SH_FLD_PBA_BCDE_ATTN = 9540; // 1
+const static uint64_t SH_FLD_PBA_BCUE_ATTN = 9541; // 1
+const static uint64_t SH_FLD_PBA_ERROR = 9542; // 1
+const static uint64_t SH_FLD_PBA_REGION = 9543; // 1
+const static uint64_t SH_FLD_PBA_REGION_LEN = 9544; // 1
+const static uint64_t SH_FLD_PBCFG_0_EPSILON = 9545; // 1
+const static uint64_t SH_FLD_PBCFG_0_EPSILON_LEN = 9546; // 1
+const static uint64_t SH_FLD_PBCFG_0_HANG_NX_MAX_CNT = 9547; // 1
+const static uint64_t SH_FLD_PBCFG_0_HANG_NX_MAX_CNT_LEN = 9548; // 1
+const static uint64_t SH_FLD_PBCFG_0_HANG_POLL_MAX_CNT = 9549; // 1
+const static uint64_t SH_FLD_PBCFG_0_HANG_POLL_MAX_CNT_LEN = 9550; // 1
+const static uint64_t SH_FLD_PBCFG_0_UNUSED1 = 9551; // 1
+const static uint64_t SH_FLD_PBCFG_0_UNUSED1_LEN = 9552; // 1
+const static uint64_t SH_FLD_PBCFG_0_UNUSED2 = 9553; // 1
+const static uint64_t SH_FLD_PBCFG_0_UNUSED2_LEN = 9554; // 1
+const static uint64_t SH_FLD_PBCFG_0_UNUSED3 = 9555; // 1
+const static uint64_t SH_FLD_PBCFG_0_UNUSED3_LEN = 9556; // 1
+const static uint64_t SH_FLD_PBCFG_1_UNUSED1 = 9557; // 1
+const static uint64_t SH_FLD_PBCFG_1_UNUSED1_LEN = 9558; // 1
+const static uint64_t SH_FLD_PBCFG_1_UNUSED2 = 9559; // 1
+const static uint64_t SH_FLD_PBCFG_1_UNUSED2_LEN = 9560; // 1
+const static uint64_t SH_FLD_PBCQ_CNTRL_LOGIC_ERR = 9561; // 1
+const static uint64_t SH_FLD_PBDATA_HANG = 9562; // 1
+const static uint64_t SH_FLD_PBEXCA0_CMD_REQ_ERR0 = 9563; // 12
+const static uint64_t SH_FLD_PBEXCA0_CMD_REQ_ERR1 = 9564; // 12
+const static uint64_t SH_FLD_PBEXCA0_CMD_REQ_ERR2 = 9565; // 12
+const static uint64_t SH_FLD_PBEXCA1_CMD_REQ_ERR0 = 9566; // 12
+const static uint64_t SH_FLD_PBEXCA1_CMD_REQ_ERR1 = 9567; // 12
+const static uint64_t SH_FLD_PBEXCA1_CMD_REQ_ERR2 = 9568; // 12
+const static uint64_t SH_FLD_PBI_IDLE = 9569; // 1
+const static uint64_t SH_FLD_PBI_INTERNAL_HANG = 9570; // 2
+const static uint64_t SH_FLD_PBI_PE = 9571; // 2
+const static uint64_t SH_FLD_PBI_WRITE_IDLE = 9572; // 2
+const static uint64_t SH_FLD_PBREQ_BCE_MAX_PRIORITY = 9573; // 1
+const static uint64_t SH_FLD_PBREQ_DATA_HANG_DIV = 9574; // 1
+const static uint64_t SH_FLD_PBREQ_DATA_HANG_DIV_LEN = 9575; // 1
+const static uint64_t SH_FLD_PBREQ_DROP_PRIORITY_MASK = 9576; // 1
+const static uint64_t SH_FLD_PBREQ_DROP_PRIORITY_MASK_LEN = 9577; // 1
+const static uint64_t SH_FLD_PBREQ_EVENT_MUX = 9578; // 1
+const static uint64_t SH_FLD_PBREQ_EVENT_MUX_LEN = 9579; // 1
+const static uint64_t SH_FLD_PBREQ_EXIT_HANG_DIV = 9580; // 1
+const static uint64_t SH_FLD_PBREQ_EXIT_HANG_DIV_LEN = 9581; // 1
+const static uint64_t SH_FLD_PBREQ_EXIT_ON_HANG = 9582; // 1
+const static uint64_t SH_FLD_PBREQ_EXIT_ON_HANG_PBAX = 9583; // 1
+const static uint64_t SH_FLD_PBREQ_OPER_HANG_DIV = 9584; // 1
+const static uint64_t SH_FLD_PBREQ_OPER_HANG_DIV_LEN = 9585; // 1
+const static uint64_t SH_FLD_PBREQ_SLVFW_MAX_PRIORITY = 9586; // 1
+const static uint64_t SH_FLD_PBRX_MASK = 9587; // 3
+const static uint64_t SH_FLD_PBRX_MASK_LEN = 9588; // 3
+const static uint64_t SH_FLD_PBTX_AMO_IGNORE_XUE = 9589; // 3
+const static uint64_t SH_FLD_PBTX_DELAY_BDONE = 9590; // 3
+const static uint64_t SH_FLD_PBTX_FLIP_IMIN_BIG = 9591; // 3
+const static uint64_t SH_FLD_PBTX_FLIP_IMIN_LITTLE = 9592; // 3
+const static uint64_t SH_FLD_PBTX_REDUCE_RTAG = 9593; // 3
+const static uint64_t SH_FLD_PBUNSUPPORTEDCMD = 9594; // 9
+const static uint64_t SH_FLD_PBUNSUPPORTEDCMD_MASK = 9595; // 9
+const static uint64_t SH_FLD_PBUNSUPPORTEDSIZE = 9596; // 9
+const static uint64_t SH_FLD_PBUNSUPPORTEDSIZE_MASK = 9597; // 9
+const static uint64_t SH_FLD_PBUS_CMD_HANG = 9598; // 2
+const static uint64_t SH_FLD_PBUS_DATA_HANG = 9599; // 1
+const static uint64_t SH_FLD_PBUS_ECC_CE = 9600; // 2
+const static uint64_t SH_FLD_PBUS_ECC_SUE = 9601; // 2
+const static uint64_t SH_FLD_PBUS_ECC_UE = 9602; // 2
+const static uint64_t SH_FLD_PBUS_LINK_ABORT = 9603; // 2
+const static uint64_t SH_FLD_PBUS_LOAD_LINK_ERR = 9604; // 2
+const static uint64_t SH_FLD_PBUS_MISC_HW = 9605; // 2
+const static uint64_t SH_FLD_PBUS_READ_ARE = 9606; // 2
+const static uint64_t SH_FLD_PBUS_STORE_LINK_ERR = 9607; // 2
+const static uint64_t SH_FLD_PBUS_WRITE_ARE = 9608; // 2
+const static uint64_t SH_FLD_PB_ACKDEAD_FW_RD = 9609; // 1
+const static uint64_t SH_FLD_PB_ACKDEAD_FW_RD_MASK = 9610; // 1
+const static uint64_t SH_FLD_PB_ACKDEAD_FW_WR = 9611; // 1
+const static uint64_t SH_FLD_PB_ACKDEAD_FW_WR_MASK = 9612; // 1
+const static uint64_t SH_FLD_PB_BADCRESP = 9613; // 1
+const static uint64_t SH_FLD_PB_BADCRESP_MASK = 9614; // 1
+const static uint64_t SH_FLD_PB_CE_FW = 9615; // 1
+const static uint64_t SH_FLD_PB_CE_FW_MASK = 9616; // 1
+const static uint64_t SH_FLD_PB_CMD_ERR = 9617; // 12
+const static uint64_t SH_FLD_PB_DATA_ERR = 9618; // 12
+const static uint64_t SH_FLD_PB_DATA_HANG_ERRORS = 9619; // 9
+const static uint64_t SH_FLD_PB_DATA_HANG_ERRORS_MASK = 9620; // 9
+const static uint64_t SH_FLD_PB_DATA_TIME_OUT = 9621; // 4
+const static uint64_t SH_FLD_PB_ECC_CE = 9622; // 1
+const static uint64_t SH_FLD_PB_ECC_ERR_CE = 9623; // 4
+const static uint64_t SH_FLD_PB_ECC_ERR_SUE = 9624; // 4
+const static uint64_t SH_FLD_PB_ECC_ERR_UE = 9625; // 4
+const static uint64_t SH_FLD_PB_ECC_SUE = 9626; // 1
+const static uint64_t SH_FLD_PB_ECC_UE = 9627; // 1
+const static uint64_t SH_FLD_PB_EN = 9628; // 4
+const static uint64_t SH_FLD_PB_FORF0_BAR = 9629; // 1
+const static uint64_t SH_FLD_PB_FORF0_BAR_EN = 9630; // 1
+const static uint64_t SH_FLD_PB_FORF0_BAR_LEN = 9631; // 1
+const static uint64_t SH_FLD_PB_FORF0_MASK = 9632; // 1
+const static uint64_t SH_FLD_PB_FORF0_MASK_LEN = 9633; // 1
+const static uint64_t SH_FLD_PB_FORF1_BAR = 9634; // 1
+const static uint64_t SH_FLD_PB_FORF1_BAR_EN = 9635; // 1
+const static uint64_t SH_FLD_PB_FORF1_BAR_LEN = 9636; // 1
+const static uint64_t SH_FLD_PB_FORF1_MASK = 9637; // 1
+const static uint64_t SH_FLD_PB_FORF1_MASK_LEN = 9638; // 1
+const static uint64_t SH_FLD_PB_FORL0_BAR = 9639; // 1
+const static uint64_t SH_FLD_PB_FORL0_BAR_EN = 9640; // 1
+const static uint64_t SH_FLD_PB_FORL0_BAR_LEN = 9641; // 1
+const static uint64_t SH_FLD_PB_FORL0_MASK = 9642; // 1
+const static uint64_t SH_FLD_PB_FORL0_MASK_LEN = 9643; // 1
+const static uint64_t SH_FLD_PB_FORL1_BAR = 9644; // 1
+const static uint64_t SH_FLD_PB_FORL1_BAR_EN = 9645; // 1
+const static uint64_t SH_FLD_PB_FORL1_BAR_LEN = 9646; // 1
+const static uint64_t SH_FLD_PB_FORL1_MASK = 9647; // 1
+const static uint64_t SH_FLD_PB_FORL1_MASK_LEN = 9648; // 1
+const static uint64_t SH_FLD_PB_HANG_ERRORS = 9649; // 9
+const static uint64_t SH_FLD_PB_HANG_ERRORS_MASK = 9650; // 9
+const static uint64_t SH_FLD_PB_INTERFACE_PE = 9651; // 9
+const static uint64_t SH_FLD_PB_INTERFACE_PE_MASK = 9652; // 9
+const static uint64_t SH_FLD_PB_LEN = 9653; // 4
+const static uint64_t SH_FLD_PB_MASK0 = 9654; // 2
+const static uint64_t SH_FLD_PB_MASK0_LEN = 9655; // 2
+const static uint64_t SH_FLD_PB_MASK1 = 9656; // 2
+const static uint64_t SH_FLD_PB_MASK1_LEN = 9657; // 2
+const static uint64_t SH_FLD_PB_NOCI_EVENT_SEL = 9658; // 1
+const static uint64_t SH_FLD_PB_OFFSET = 9659; // 2
+const static uint64_t SH_FLD_PB_OFFSET_LEN = 9660; // 2
+const static uint64_t SH_FLD_PB_OPERTO = 9661; // 1
+const static uint64_t SH_FLD_PB_OPERTO_MASK = 9662; // 1
+const static uint64_t SH_FLD_PB_OP_HANG_ERR = 9663; // 1
+const static uint64_t SH_FLD_PB_PARITY_ERR = 9664; // 1
+const static uint64_t SH_FLD_PB_PARITY_ERROR = 9665; // 4
+const static uint64_t SH_FLD_PB_PARITY_ERR_MASK = 9666; // 1
+const static uint64_t SH_FLD_PB_PURGE_DONE_LVL = 9667; // 6
+const static uint64_t SH_FLD_PB_PURGE_PLS = 9668; // 6
+const static uint64_t SH_FLD_PB_RDADRERR_FW = 9669; // 1
+const static uint64_t SH_FLD_PB_RDADRERR_FW_MASK = 9670; // 1
+const static uint64_t SH_FLD_PB_RDDATATO_FW = 9671; // 1
+const static uint64_t SH_FLD_PB_RDDATATO_FW_MASK = 9672; // 1
+const static uint64_t SH_FLD_PB_STOP = 9673; // 1
+const static uint64_t SH_FLD_PB_SUE_FW = 9674; // 1
+const static uint64_t SH_FLD_PB_SUE_FW_MASK = 9675; // 1
+const static uint64_t SH_FLD_PB_TO_PEC_CE = 9676; // 9
+const static uint64_t SH_FLD_PB_TO_PEC_CE_MASK = 9677; // 9
+const static uint64_t SH_FLD_PB_TO_PEC_SUE = 9678; // 9
+const static uint64_t SH_FLD_PB_TO_PEC_SUE_MASK = 9679; // 9
+const static uint64_t SH_FLD_PB_TO_PEC_UE = 9680; // 9
+const static uint64_t SH_FLD_PB_TO_PEC_UE_MASK = 9681; // 9
+const static uint64_t SH_FLD_PB_UE_FW = 9682; // 1
+const static uint64_t SH_FLD_PB_UE_FW_MASK = 9683; // 1
+const static uint64_t SH_FLD_PB_UNEXPCRESP = 9684; // 1
+const static uint64_t SH_FLD_PB_UNEXPCRESP_MASK = 9685; // 1
+const static uint64_t SH_FLD_PB_UNEXPDATA = 9686; // 1
+const static uint64_t SH_FLD_PB_UNEXPDATA_MASK = 9687; // 1
+const static uint64_t SH_FLD_PB_WRADRERR_FW = 9688; // 1
+const static uint64_t SH_FLD_PB_WRADRERR_FW_MASK = 9689; // 1
+const static uint64_t SH_FLD_PB_XLAT_DATA_SUE = 9690; // 1
+const static uint64_t SH_FLD_PB_XLAT_DATA_UE = 9691; // 1
+const static uint64_t SH_FLD_PCB = 9692; // 3
+const static uint64_t SH_FLD_PCBMUX_GRANT_C0 = 9693; // 12
+const static uint64_t SH_FLD_PCBMUX_GRANT_C1 = 9694; // 12
+const static uint64_t SH_FLD_PCBMUX_REQ_C0 = 9695; // 12
+const static uint64_t SH_FLD_PCBMUX_REQ_C1 = 9696; // 12
+const static uint64_t SH_FLD_PCBQ_N_INFO = 9697; // 24
+const static uint64_t SH_FLD_PCBQ_N_INFO_LEN = 9698; // 24
+const static uint64_t SH_FLD_PCB_EP_RESET = 9699; // 43
+const static uint64_t SH_FLD_PCB_ERROR = 9700; // 43
+const static uint64_t SH_FLD_PCB_FSM = 9701; // 43
+const static uint64_t SH_FLD_PCB_IDLE = 9702; // 43
+const static uint64_t SH_FLD_PCB_INTERFACE = 9703; // 43
+const static uint64_t SH_FLD_PCB_INTERRUPT_PROTOCOL = 9704; // 30
+const static uint64_t SH_FLD_PCB_INTR_TYPE_A_CORE_N = 9705; // 144
+const static uint64_t SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN = 9706; // 144
+const static uint64_t SH_FLD_PCB_INTR_TYPE_A_QUAD_N = 9707; // 12
+const static uint64_t SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN = 9708; // 6
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_0 = 9709; // 8
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_1 = 9710; // 8
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_10 = 9711; // 6
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_11 = 9712; // 6
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_12 = 9713; // 6
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_13 = 9714; // 6
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_14 = 9715; // 6
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_15 = 9716; // 6
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_16 = 9717; // 6
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_17 = 9718; // 6
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_18 = 9719; // 6
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_19 = 9720; // 6
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_2 = 9721; // 8
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_20 = 9722; // 6
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_21 = 9723; // 6
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_22 = 9724; // 6
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_23 = 9725; // 6
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_3 = 9726; // 8
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_4 = 9727; // 8
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_5 = 9728; // 8
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_6 = 9729; // 6
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_7 = 9730; // 6
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_8 = 9731; // 6
+const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_9 = 9732; // 6
+const static uint64_t SH_FLD_PCB_LEN = 9733; // 2
+const static uint64_t SH_FLD_PCB_MASK = 9734; // 43
+const static uint64_t SH_FLD_PCB_REQUEST_SINCE_RESET = 9735; // 43
+const static uint64_t SH_FLD_PCB_RESET_DC = 9736; // 1
+const static uint64_t SH_FLD_PCB_TMP = 9737; // 1
+const static uint64_t SH_FLD_PCB_TMP_LEN = 9738; // 1
+const static uint64_t SH_FLD_PCC_CORE_INTF_QUIESCE_C0 = 9739; // 12
+const static uint64_t SH_FLD_PCC_CORE_INTF_QUIESCE_C1 = 9740; // 12
+const static uint64_t SH_FLD_PCI_CLOCK_ERROR = 9741; // 9
+const static uint64_t SH_FLD_PCI_CLOCK_ERROR_MASK = 9742; // 9
+const static uint64_t SH_FLD_PCI_HANG_ERROR = 9743; // 9
+const static uint64_t SH_FLD_PCI_HANG_ERROR_MASK = 9744; // 9
+const static uint64_t SH_FLD_PCLKDIFSEL = 9745; // 10
+const static uint64_t SH_FLD_PCLKSEL = 9746; // 14
+const static uint64_t SH_FLD_PCLKSEL_LEN = 9747; // 14
+const static uint64_t SH_FLD_PC_BLOCK_INTERRUPTS_C0 = 9748; // 12
+const static uint64_t SH_FLD_PC_BLOCK_INTERRUPTS_C1 = 9749; // 12
+const static uint64_t SH_FLD_PC_CAL_PCFSM_1HOT = 9750; // 8
+const static uint64_t SH_FLD_PC_CAL_REFFSM_1HOT = 9751; // 8
+const static uint64_t SH_FLD_PC_ENTRY_ACK_C0 = 9752; // 12
+const static uint64_t SH_FLD_PC_ENTRY_ACK_C1 = 9753; // 12
+const static uint64_t SH_FLD_PC_ERR_STATUS0 = 9754; // 8
+const static uint64_t SH_FLD_PC_ERR_STATUS0_LEN = 9755; // 8
+const static uint64_t SH_FLD_PC_FUSED_CORE_MODE = 9756; // 24
+const static uint64_t SH_FLD_PC_INIT_CAL_ERR = 9757; // 8
+const static uint64_t SH_FLD_PC_INIT_CAL_ERR_LEN = 9758; // 8
+const static uint64_t SH_FLD_PC_INSTR_RUNNING_C0 = 9759; // 12
+const static uint64_t SH_FLD_PC_INSTR_RUNNING_C1 = 9760; // 12
+const static uint64_t SH_FLD_PC_INTR_PENDING_C0 = 9761; // 24
+const static uint64_t SH_FLD_PC_INTR_PENDING_C1 = 9762; // 24
+const static uint64_t SH_FLD_PC_NON_HV_RUNNING_C0 = 9763; // 12
+const static uint64_t SH_FLD_PC_NON_HV_RUNNING_C0_LEN = 9764; // 12
+const static uint64_t SH_FLD_PC_NON_HV_RUNNING_C1 = 9765; // 12
+const static uint64_t SH_FLD_PC_NON_HV_RUNNING_C1_LEN = 9766; // 12
+const static uint64_t SH_FLD_PC_PE = 9767; // 8
+const static uint64_t SH_FLD_PC_PM_STATE_ACTIVE_C0 = 9768; // 24
+const static uint64_t SH_FLD_PC_PM_STATE_ACTIVE_C1 = 9769; // 24
+const static uint64_t SH_FLD_PC_PRIORITY_LIMIT_0_3 = 9770; // 1
+const static uint64_t SH_FLD_PC_PRIORITY_LIMIT_0_3_LEN = 9771; // 1
+const static uint64_t SH_FLD_PC_SLICE_EN_ENC = 9772; // 1
+const static uint64_t SH_FLD_PC_SLICE_EN_ENC_LEN = 9773; // 1
+const static uint64_t SH_FLD_PC_TC_AVP_OUT = 9774; // 24
+const static uint64_t SH_FLD_PC_TC_VALID_NOT_HV_MODE = 9775; // 24
+const static uint64_t SH_FLD_PC_TEST = 9776; // 1
+const static uint64_t SH_FLD_PC_UNMASKED_ATTN_C0 = 9777; // 12
+const static uint64_t SH_FLD_PC_UNMASKED_ATTN_C1 = 9778; // 12
+const static uint64_t SH_FLD_PC_WAKEUP_C0 = 9779; // 12
+const static uint64_t SH_FLD_PC_WAKEUP_C1 = 9780; // 12
+const static uint64_t SH_FLD_PDWN = 9781; // 2
+const static uint64_t SH_FLD_PDWNPLL = 9782; // 6
+const static uint64_t SH_FLD_PDWNT = 9783; // 3
+const static uint64_t SH_FLD_PDWN_LITE = 9784; // 140
+const static uint64_t SH_FLD_PDWN_LITE_DISABLE = 9785; // 8
+const static uint64_t SH_FLD_PE = 9786; // 21
+const static uint64_t SH_FLD_PEAK_INIT_CFG = 9787; // 6
+const static uint64_t SH_FLD_PEAK_INIT_CFG_LEN = 9788; // 6
+const static uint64_t SH_FLD_PEAK_INIT_TIMEOUT = 9789; // 6
+const static uint64_t SH_FLD_PEAK_INIT_TIMEOUT_LEN = 9790; // 6
+const static uint64_t SH_FLD_PEAK_RECAL_CFG = 9791; // 6
+const static uint64_t SH_FLD_PEAK_RECAL_CFG_LEN = 9792; // 6
+const static uint64_t SH_FLD_PEAK_RECAL_TIMEOUT = 9793; // 6
+const static uint64_t SH_FLD_PEAK_RECAL_TIMEOUT_LEN = 9794; // 6
+const static uint64_t SH_FLD_PEAK_TUNE = 9795; // 4
+const static uint64_t SH_FLD_PECE_C_N_T0 = 9796; // 24
+const static uint64_t SH_FLD_PECE_C_N_T0_LEN = 9797; // 24
+const static uint64_t SH_FLD_PECE_C_N_T1 = 9798; // 24
+const static uint64_t SH_FLD_PECE_C_N_T1_LEN = 9799; // 24
+const static uint64_t SH_FLD_PECE_C_N_T2 = 9800; // 24
+const static uint64_t SH_FLD_PECE_C_N_T2_LEN = 9801; // 24
+const static uint64_t SH_FLD_PECE_C_N_T3 = 9802; // 24
+const static uint64_t SH_FLD_PECE_C_N_T3_LEN = 9803; // 24
+const static uint64_t SH_FLD_PECE_DECR = 9804; // 96
+const static uint64_t SH_FLD_PECE_DHDES = 9805; // 96
+const static uint64_t SH_FLD_PECE_DPDES = 9806; // 96
+const static uint64_t SH_FLD_PECE_HMAINT = 9807; // 96
+const static uint64_t SH_FLD_PECE_HYPV = 9808; // 96
+const static uint64_t SH_FLD_PECE_INTR_DISABLED = 9809; // 24
+const static uint64_t SH_FLD_PECE_OS_EXT = 9810; // 96
+const static uint64_t SH_FLD_PEC_SCOM_ERR = 9811; // 9
+const static uint64_t SH_FLD_PEC_SCOM_ERR_MASK = 9812; // 9
+const static uint64_t SH_FLD_PEEK_DATA1_0 = 9813; // 12
+const static uint64_t SH_FLD_PEEK_DATA1_0_LEN = 9814; // 12
+const static uint64_t SH_FLD_PEEK_DATA1_1 = 9815; // 12
+const static uint64_t SH_FLD_PEEK_DATA1_1_LEN = 9816; // 12
+const static uint64_t SH_FLD_PEEK_DATA1_2 = 9817; // 12
+const static uint64_t SH_FLD_PEEK_DATA1_2_LEN = 9818; // 12
+const static uint64_t SH_FLD_PEEK_DATA1_3 = 9819; // 12
+const static uint64_t SH_FLD_PEEK_DATA1_3_LEN = 9820; // 12
+const static uint64_t SH_FLD_PENDING_SOURCE = 9821; // 30
+const static uint64_t SH_FLD_PENDING_SOURCE_LEN = 9822; // 30
+const static uint64_t SH_FLD_PERFORM_RDCLK_ALIGN = 9823; // 8
+const static uint64_t SH_FLD_PERIODIC = 9824; // 56
+const static uint64_t SH_FLD_PERIODIC_CAL_REQ_EN = 9825; // 8
+const static uint64_t SH_FLD_PERIODIC_LEN = 9826; // 56
+const static uint64_t SH_FLD_PERSIST = 9827; // 8
+const static uint64_t SH_FLD_PERSIST_LEN = 9828; // 8
+const static uint64_t SH_FLD_PERV = 9829; // 215
+const static uint64_t SH_FLD_PERVASIVE_CAPT = 9830; // 6
+const static uint64_t SH_FLD_PER_ABORT = 9831; // 8
+const static uint64_t SH_FLD_PER_DUTY_CYCLE_SW = 9832; // 8
+const static uint64_t SH_FLD_PER_REPEAT_COUNT = 9833; // 8
+const static uint64_t SH_FLD_PER_REPEAT_COUNT_LEN = 9834; // 8
+const static uint64_t SH_FLD_PE_ADR_BAR_MODE = 9835; // 3
+const static uint64_t SH_FLD_PE_BLOCK_CQPB_PB_INIT = 9836; // 3
+const static uint64_t SH_FLD_PE_CAPP = 9837; // 3
+const static uint64_t SH_FLD_PE_CAPP_256 = 9838; // 3
+const static uint64_t SH_FLD_PE_CAPP_DMA = 9839; // 3
+const static uint64_t SH_FLD_PE_CAPP_EN = 9840; // 3
+const static uint64_t SH_FLD_PE_CAPP_LEN = 9841; // 3
+const static uint64_t SH_FLD_PE_CAPP_P8_MODE = 9842; // 3
+const static uint64_t SH_FLD_PE_CHANNEL_STREAMING_EN = 9843; // 3
+const static uint64_t SH_FLD_PE_CQ_ECC_INJECT_ENABLE = 9844; // 3
+const static uint64_t SH_FLD_PE_CQ_PAR_INJECT_ENABLE = 9845; // 3
+const static uint64_t SH_FLD_PE_CQ_REGISTER_ARRAY = 9846; // 3
+const static uint64_t SH_FLD_PE_CQ_REGISTER_ARRAY_LEN = 9847; // 3
+const static uint64_t SH_FLD_PE_CQ_SRAM_ARRAY = 9848; // 3
+const static uint64_t SH_FLD_PE_CQ_SRAM_ARRAY_LEN = 9849; // 3
+const static uint64_t SH_FLD_PE_DISABLE_CQ_TCE_ARBITRATION = 9850; // 3
+const static uint64_t SH_FLD_PE_DISABLE_INJ_ON_RESEND = 9851; // 3
+const static uint64_t SH_FLD_PE_DISABLE_INTWR_SCOPE_GROUP = 9852; // 3
+const static uint64_t SH_FLD_PE_DISABLE_INTWR_SCOPE_NODE = 9853; // 3
+const static uint64_t SH_FLD_PE_DISABLE_INTWR_VG = 9854; // 3
+const static uint64_t SH_FLD_PE_DISABLE_MC_PREFETCH = 9855; // 3
+const static uint64_t SH_FLD_PE_DISABLE_OOO_MODE = 9856; // 3
+const static uint64_t SH_FLD_PE_DISABLE_PCI_CLK_CHECK = 9857; // 3
+const static uint64_t SH_FLD_PE_DISABLE_RD_SCOPE_GROUP = 9858; // 3
+const static uint64_t SH_FLD_PE_DISABLE_RD_SCOPE_NODAL = 9859; // 3
+const static uint64_t SH_FLD_PE_DISABLE_RD_SCOPE_RNNN = 9860; // 3
+const static uint64_t SH_FLD_PE_DISABLE_RD_VG = 9861; // 3
+const static uint64_t SH_FLD_PE_DISABLE_TCE_ARBITRATION = 9862; // 3
+const static uint64_t SH_FLD_PE_DISABLE_TCE_SCOPE_GROUP = 9863; // 3
+const static uint64_t SH_FLD_PE_DISABLE_TCE_SCOPE_NODAL = 9864; // 3
+const static uint64_t SH_FLD_PE_DISABLE_TCE_SCOPE_RNNN = 9865; // 3
+const static uint64_t SH_FLD_PE_DISABLE_TCE_VG = 9866; // 3
+const static uint64_t SH_FLD_PE_DISABLE_WR_SCOPE_GROUP = 9867; // 3
+const static uint64_t SH_FLD_PE_DISABLE_WR_VG = 9868; // 3
+const static uint64_t SH_FLD_PE_DROPPACECOUNT = 9869; // 3
+const static uint64_t SH_FLD_PE_DROPPACECOUNT_LEN = 9870; // 3
+const static uint64_t SH_FLD_PE_DROPPACEINC = 9871; // 3
+const static uint64_t SH_FLD_PE_DROPPACEINC_LEN = 9872; // 3
+const static uint64_t SH_FLD_PE_DROPPRIORITYMASK = 9873; // 3
+const static uint64_t SH_FLD_PE_DROPPRIORITYMASK_LEN = 9874; // 3
+const static uint64_t SH_FLD_PE_ECC_INJECT_TYPE = 9875; // 3
+const static uint64_t SH_FLD_PE_ECC_INJECT_TYPE_LEN = 9876; // 3
+const static uint64_t SH_FLD_PE_EINJ_STACK = 9877; // 3
+const static uint64_t SH_FLD_PE_EINJ_STACK_LEN = 9878; // 3
+const static uint64_t SH_FLD_PE_ENABLENESTTRACE = 9879; // 3
+const static uint64_t SH_FLD_PE_ENABLE_CTAG_DROP_PRIORITY = 9880; // 3
+const static uint64_t SH_FLD_PE_ENABLE_DMAR_IOPACING = 9881; // 3
+const static uint64_t SH_FLD_PE_ENABLE_DMAW_IOPACING = 9882; // 3
+const static uint64_t SH_FLD_PE_ENABLE_ENH_FLOW = 9883; // 3
+const static uint64_t SH_FLD_PE_ENABLE_IO_CMD_PACING = 9884; // 3
+const static uint64_t SH_FLD_PE_ENABLE_NEW_FLOW_CACHE_INJECT = 9885; // 3
+const static uint64_t SH_FLD_PE_ENABLE_RD_SKIP_GROUP = 9886; // 3
+const static uint64_t SH_FLD_PE_ENABLE_TCE_SKIP_GROUP = 9887; // 3
+const static uint64_t SH_FLD_PE_ENHANCED_PEER2PEER_MODDE = 9888; // 9
+const static uint64_t SH_FLD_PE_ETU_RESET = 9889; // 9
+const static uint64_t SH_FLD_PE_FORCE_DISABLED_CTAG_TO_FOLLOW_FLOW = 9890; // 3
+const static uint64_t SH_FLD_PE_HANG_SM_ON_ARE = 9891; // 3
+const static uint64_t SH_FLD_PE_IGNORE_SFSTAT = 9892; // 3
+const static uint64_t SH_FLD_PE_INBOUND_ACTIVE = 9893; // 9
+const static uint64_t SH_FLD_PE_ISMB_ERROR_INJECT = 9894; // 3
+const static uint64_t SH_FLD_PE_ISMB_ERROR_INJECT_LEN = 9895; // 3
+const static uint64_t SH_FLD_PE_LEN = 9896; // 21
+const static uint64_t SH_FLD_PE_LSI_BAR = 9897; // 9
+const static uint64_t SH_FLD_PE_LSI_BAR_EN = 9898; // 9
+const static uint64_t SH_FLD_PE_LSI_BAR_LEN = 9899; // 9
+const static uint64_t SH_FLD_PE_MMIO_BAR0 = 9900; // 9
+const static uint64_t SH_FLD_PE_MMIO_BAR0_EN = 9901; // 9
+const static uint64_t SH_FLD_PE_MMIO_BAR0_LEN = 9902; // 9
+const static uint64_t SH_FLD_PE_MMIO_BAR1 = 9903; // 9
+const static uint64_t SH_FLD_PE_MMIO_BAR1_EN = 9904; // 9
+const static uint64_t SH_FLD_PE_MMIO_BAR1_LEN = 9905; // 9
+const static uint64_t SH_FLD_PE_MMIO_MASK0 = 9906; // 9
+const static uint64_t SH_FLD_PE_MMIO_MASK0_LEN = 9907; // 9
+const static uint64_t SH_FLD_PE_MMIO_MASK1 = 9908; // 9
+const static uint64_t SH_FLD_PE_MMIO_MASK1_LEN = 9909; // 9
+const static uint64_t SH_FLD_PE_MSI_BAR = 9910; // 9
+const static uint64_t SH_FLD_PE_MSI_BAR_EN = 9911; // 9
+const static uint64_t SH_FLD_PE_MSI_BAR_LEN = 9912; // 9
+const static uint64_t SH_FLD_PE_NESTTRACESEL = 9913; // 3
+const static uint64_t SH_FLD_PE_NESTTRACESEL_LEN = 9914; // 3
+const static uint64_t SH_FLD_PE_OSMB_DATASTART_MODE = 9915; // 3
+const static uint64_t SH_FLD_PE_OSMB_DATASTART_MODE_LEN = 9916; // 3
+const static uint64_t SH_FLD_PE_OSMB_EARLYEMPTY_MODE = 9917; // 3
+const static uint64_t SH_FLD_PE_OSMB_EARLYEMPTY_MODE_LEN = 9918; // 3
+const static uint64_t SH_FLD_PE_OSMB_EARLY_START = 9919; // 3
+const static uint64_t SH_FLD_PE_OSMB_EARLY_START_LEN = 9920; // 3
+const static uint64_t SH_FLD_PE_OSMB_HOL_BLK_CNT = 9921; // 3
+const static uint64_t SH_FLD_PE_OSMB_HOL_BLK_CNT_LEN = 9922; // 3
+const static uint64_t SH_FLD_PE_OUTBOUND_ACTIVE = 9923; // 9
+const static uint64_t SH_FLD_PE_PCIE_CLK_TRACE_EN = 9924; // 3
+const static uint64_t SH_FLD_PE_PCI_CLK_TRACE_SEL = 9925; // 3
+const static uint64_t SH_FLD_PE_PCI_CLK_TRACE_SEL_LEN = 9926; // 3
+const static uint64_t SH_FLD_PE_PEER2PEER_MODDE = 9927; // 9
+const static uint64_t SH_FLD_PE_PERFMON_EN = 9928; // 3
+const static uint64_t SH_FLD_PE_PERFMON_EN_LEN = 9929; // 3
+const static uint64_t SH_FLD_PE_PERFMON_READ_TYPE = 9930; // 3
+const static uint64_t SH_FLD_PE_PERFMON_READ_TYPE_LEN = 9931; // 3
+const static uint64_t SH_FLD_PE_PHB_BAR = 9932; // 9
+const static uint64_t SH_FLD_PE_PHB_BAR_EN = 9933; // 9
+const static uint64_t SH_FLD_PE_PHB_BAR_LEN = 9934; // 9
+const static uint64_t SH_FLD_PE_PMON_MUX_BYTE0 = 9935; // 3
+const static uint64_t SH_FLD_PE_PMON_MUX_BYTE0_LEN = 9936; // 3
+const static uint64_t SH_FLD_PE_PMON_MUX_BYTE1 = 9937; // 3
+const static uint64_t SH_FLD_PE_PMON_MUX_BYTE1_LEN = 9938; // 3
+const static uint64_t SH_FLD_PE_PMON_MUX_BYTE2 = 9939; // 3
+const static uint64_t SH_FLD_PE_PMON_MUX_BYTE2_LEN = 9940; // 3
+const static uint64_t SH_FLD_PE_PMON_MUX_BYTE3 = 9941; // 3
+const static uint64_t SH_FLD_PE_PMON_MUX_BYTE3_LEN = 9942; // 3
+const static uint64_t SH_FLD_PE_QFIFO_HOLD_MODE = 9943; // 3
+const static uint64_t SH_FLD_PE_QFIFO_HOLD_MODE_LEN = 9944; // 3
+const static uint64_t SH_FLD_PE_RD_TIMEOUT_MASK = 9945; // 3
+const static uint64_t SH_FLD_PE_RD_TIMEOUT_MASK_LEN = 9946; // 3
+const static uint64_t SH_FLD_PE_RD_WRITE_ORDERING = 9947; // 3
+const static uint64_t SH_FLD_PE_RD_WRITE_ORDERING_LEN = 9948; // 3
+const static uint64_t SH_FLD_PE_RTYDROPDIVIDER = 9949; // 3
+const static uint64_t SH_FLD_PE_RTYDROPDIVIDER_LEN = 9950; // 3
+const static uint64_t SH_FLD_PE_SELECT_ETU_TRACE = 9951; // 3
+const static uint64_t SH_FLD_PE_STQ_ALLOCATION = 9952; // 3
+const static uint64_t SH_FLD_PE_TX_RESP_HWM = 9953; // 3
+const static uint64_t SH_FLD_PE_TX_RESP_HWM_LEN = 9954; // 3
+const static uint64_t SH_FLD_PE_TX_RESP_LWM = 9955; // 3
+const static uint64_t SH_FLD_PE_TX_RESP_LWM_LEN = 9956; // 3
+const static uint64_t SH_FLD_PE_WR_CACHE_INJECT_MODE = 9957; // 3
+const static uint64_t SH_FLD_PE_WR_CACHE_INJECT_MODE_LEN = 9958; // 3
+const static uint64_t SH_FLD_PE_WR_STRICT_ORDER_MODE = 9959; // 3
+const static uint64_t SH_FLD_PE_WR_TIMEOUT_MASK = 9960; // 3
+const static uint64_t SH_FLD_PE_WR_TIMEOUT_MASK_LEN = 9961; // 3
+const static uint64_t SH_FLD_PFD360SEL = 9962; // 4
+const static uint64_t SH_FLD_PF_DROP_CNT_THRESH = 9963; // 4
+const static uint64_t SH_FLD_PF_DROP_CNT_THRESH_LEN = 9964; // 4
+const static uint64_t SH_FLD_PF_DROP_VALUE0 = 9965; // 8
+const static uint64_t SH_FLD_PF_DROP_VALUE0_LEN = 9966; // 8
+const static uint64_t SH_FLD_PF_DROP_VALUE1 = 9967; // 8
+const static uint64_t SH_FLD_PF_DROP_VALUE1_LEN = 9968; // 8
+const static uint64_t SH_FLD_PF_DROP_VALUE2 = 9969; // 8
+const static uint64_t SH_FLD_PF_DROP_VALUE2_LEN = 9970; // 8
+const static uint64_t SH_FLD_PF_DROP_VALUE3 = 9971; // 8
+const static uint64_t SH_FLD_PF_DROP_VALUE3_LEN = 9972; // 8
+const static uint64_t SH_FLD_PF_MACHINE_HANG_ERR = 9973; // 12
+const static uint64_t SH_FLD_PF_MACHINE_W4DT_HANG_ERR = 9974; // 12
+const static uint64_t SH_FLD_PF_UNSOLICITED_CRESP_ERR = 9975; // 12
+const static uint64_t SH_FLD_PF_UNSOLICITED_CRESP_ERR_LEN = 9976; // 12
+const static uint64_t SH_FLD_PF_UNSOLICITED_DATA_ERR = 9977; // 12
+const static uint64_t SH_FLD_PGMIGR1_BAR = 9978; // 1
+const static uint64_t SH_FLD_PGMIGR1_BAR_LEN = 9979; // 1
+const static uint64_t SH_FLD_PGMIGR1_PGSZ = 9980; // 1
+const static uint64_t SH_FLD_PGMIGR1_PGSZ_LEN = 9981; // 1
+const static uint64_t SH_FLD_PGMIGR1_VAL = 9982; // 1
+const static uint64_t SH_FLD_PGMIGR2_BAR = 9983; // 1
+const static uint64_t SH_FLD_PGMIGR2_BAR_LEN = 9984; // 1
+const static uint64_t SH_FLD_PGMIGR2_PGSZ = 9985; // 1
+const static uint64_t SH_FLD_PGMIGR2_PGSZ_LEN = 9986; // 1
+const static uint64_t SH_FLD_PGMIGR2_VAL = 9987; // 1
+const static uint64_t SH_FLD_PGMIGR3_BAR = 9988; // 1
+const static uint64_t SH_FLD_PGMIGR3_BAR_LEN = 9989; // 1
+const static uint64_t SH_FLD_PGMIGR3_PGSZ = 9990; // 1
+const static uint64_t SH_FLD_PGMIGR3_PGSZ_LEN = 9991; // 1
+const static uint64_t SH_FLD_PGMIGR3_VAL = 9992; // 1
+const static uint64_t SH_FLD_PGMIGR4_BAR = 9993; // 1
+const static uint64_t SH_FLD_PGMIGR4_BAR_LEN = 9994; // 1
+const static uint64_t SH_FLD_PGMIGR4_PGSZ = 9995; // 1
+const static uint64_t SH_FLD_PGMIGR4_PGSZ_LEN = 9996; // 1
+const static uint64_t SH_FLD_PGMIGR4_VAL = 9997; // 1
+const static uint64_t SH_FLD_PGMIGR5_BAR = 9998; // 1
+const static uint64_t SH_FLD_PGMIGR5_BAR_LEN = 9999; // 1
+const static uint64_t SH_FLD_PGMIGR5_PGSZ = 10000; // 1
+const static uint64_t SH_FLD_PGMIGR5_PGSZ_LEN = 10001; // 1
+const static uint64_t SH_FLD_PGMIGR5_VAL = 10002; // 1
+const static uint64_t SH_FLD_PGMIGR6_BAR = 10003; // 1
+const static uint64_t SH_FLD_PGMIGR6_BAR_LEN = 10004; // 1
+const static uint64_t SH_FLD_PGMIGR6_PGSZ = 10005; // 1
+const static uint64_t SH_FLD_PGMIGR6_PGSZ_LEN = 10006; // 1
+const static uint64_t SH_FLD_PGMIGR6_VAL = 10007; // 1
+const static uint64_t SH_FLD_PGMIGR7_BAR = 10008; // 1
+const static uint64_t SH_FLD_PGMIGR7_BAR_LEN = 10009; // 1
+const static uint64_t SH_FLD_PGMIGR7_PGSZ = 10010; // 1
+const static uint64_t SH_FLD_PGMIGR7_PGSZ_LEN = 10011; // 1
+const static uint64_t SH_FLD_PGMIGR7_VAL = 10012; // 1
+const static uint64_t SH_FLD_PGOOD_TIMEOUT_SEL = 10013; // 4
+const static uint64_t SH_FLD_PGOOD_TIMEOUT_SEL_LEN = 10014; // 4
+const static uint64_t SH_FLD_PG_MIG_DISABLED_ERR = 10015; // 2
+const static uint64_t SH_FLD_PG_MIG_SIZE_MISMATCH_ERR = 10016; // 2
+const static uint64_t SH_FLD_PHASEFB = 10017; // 4
+const static uint64_t SH_FLD_PHASEFB_LEN = 10018; // 4
+const static uint64_t SH_FLD_PHBCSR_SPARE = 10019; // 1
+const static uint64_t SH_FLD_PHB_FILTER_CNTL = 10020; // 2
+const static uint64_t SH_FLD_PHB_FILTER_CNTL_LEN = 10021; // 2
+const static uint64_t SH_FLD_PHB_LINK_DOWN = 10022; // 4
+const static uint64_t SH_FLD_PHYP_SCOPE = 10023; // 1
+const static uint64_t SH_FLD_PHYTOP_CLK_GATE = 10024; // 8
+const static uint64_t SH_FLD_PIB2PCB_DC = 10025; // 1
+const static uint64_t SH_FLD_PIBI2CM_PIB_SLAVE_ID = 10026; // 1
+const static uint64_t SH_FLD_PIBI2CM_PIB_SLAVE_ID_LEN = 10027; // 1
+const static uint64_t SH_FLD_PIB_0 = 10028; // 2
+const static uint64_t SH_FLD_PIB_0_LEN = 10029; // 2
+const static uint64_t SH_FLD_PIB_1 = 10030; // 2
+const static uint64_t SH_FLD_PIB_1_LEN = 10031; // 2
+const static uint64_t SH_FLD_PIB_2 = 10032; // 2
+const static uint64_t SH_FLD_PIB_2_LEN = 10033; // 2
+const static uint64_t SH_FLD_PIB_3 = 10034; // 2
+const static uint64_t SH_FLD_PIB_3_LEN = 10035; // 2
+const static uint64_t SH_FLD_PIB_ABORT = 10036; // 2
+const static uint64_t SH_FLD_PIB_ADDR = 10037; // 19
+const static uint64_t SH_FLD_PIB_ADDR_LEN = 10038; // 19
+const static uint64_t SH_FLD_PIB_ADDR_P = 10039; // 1
+const static uint64_t SH_FLD_PIB_ADDR_P_ERR = 10040; // 1
+const static uint64_t SH_FLD_PIB_BUSY = 10041; // 18
+const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_0 = 10042; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_0_LEN = 10043; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_1 = 10044; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_1_LEN = 10045; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_2 = 10046; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_2_LEN = 10047; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_3 = 10048; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_3_LEN = 10049; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_0 = 10050; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_1 = 10051; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_2 = 10052; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_3 = 10053; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_0 = 10054; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_1 = 10055; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_2 = 10056; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_3 = 10057; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_0 = 10058; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_1 = 10059; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_2 = 10060; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_3 = 10061; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_0 = 10062; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_1 = 10063; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_2 = 10064; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_3 = 10065; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_0 = 10066; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_1 = 10067; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_2 = 10068; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_3 = 10069; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_0 = 10070; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_0_LEN = 10071; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_1 = 10072; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_1_LEN = 10073; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_2 = 10074; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_2_LEN = 10075; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_3 = 10076; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_3_LEN = 10077; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_0 = 10078; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_0_LEN = 10079; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_1 = 10080; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_1_LEN = 10081; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_2 = 10082; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_2_LEN = 10083; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_3 = 10084; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_3_LEN = 10085; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_0 = 10086; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_0_LEN = 10087; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_1 = 10088; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_1_LEN = 10089; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_2 = 10090; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_2_LEN = 10091; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_3 = 10092; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_3_LEN = 10093; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_0 = 10094; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_0_LEN = 10095; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_1 = 10096; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_1_LEN = 10097; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_2 = 10098; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_2_LEN = 10099; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_3 = 10100; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_3_LEN = 10101; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_0 = 10102; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_0_LEN = 10103; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_1 = 10104; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_1_LEN = 10105; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_2 = 10106; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_2_LEN = 10107; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_3 = 10108; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_3_LEN = 10109; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_0 = 10110; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_0_LEN = 10111; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_1 = 10112; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_1_LEN = 10113; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_2 = 10114; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_2_LEN = 10115; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_3 = 10116; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_3_LEN = 10117; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_0 = 10118; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_0_LEN = 10119; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_1 = 10120; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_1_LEN = 10121; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_2 = 10122; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_2_LEN = 10123; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_3 = 10124; // 1
+const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_3_LEN = 10125; // 1
+const static uint64_t SH_FLD_PIB_COMPONENT_BUSY = 10126; // 1
+const static uint64_t SH_FLD_PIB_DATA0TO7_0 = 10127; // 1
+const static uint64_t SH_FLD_PIB_DATA0TO7_0_LEN = 10128; // 1
+const static uint64_t SH_FLD_PIB_DATA0TO7_1 = 10129; // 1
+const static uint64_t SH_FLD_PIB_DATA0TO7_1_LEN = 10130; // 1
+const static uint64_t SH_FLD_PIB_DATA0TO7_2 = 10131; // 1
+const static uint64_t SH_FLD_PIB_DATA0TO7_2_LEN = 10132; // 1
+const static uint64_t SH_FLD_PIB_DATA0TO7_3 = 10133; // 1
+const static uint64_t SH_FLD_PIB_DATA0TO7_3_LEN = 10134; // 1
+const static uint64_t SH_FLD_PIB_DATAOP_PENDING = 10135; // 18
+const static uint64_t SH_FLD_PIB_DATA_P = 10136; // 1
+const static uint64_t SH_FLD_PIB_DATA_P_ERR = 10137; // 1
+const static uint64_t SH_FLD_PIB_ERROR_CODE = 10138; // 1
+const static uint64_t SH_FLD_PIB_ERROR_CODE_LEN = 10139; // 1
+const static uint64_t SH_FLD_PIB_FSM_STATE = 10140; // 1
+const static uint64_t SH_FLD_PIB_FSM_STATE_LEN = 10141; // 1
+const static uint64_t SH_FLD_PIB_HANG = 10142; // 1
+const static uint64_t SH_FLD_PIB_IFETCH_PENDING = 10143; // 18
+const static uint64_t SH_FLD_PIB_IMPRECISE_ERROR_PENDING = 10144; // 18
+const static uint64_t SH_FLD_PIB_MASTER_REQUEST = 10145; // 4
+const static uint64_t SH_FLD_PIB_MASTER_RSP_INFO = 10146; // 4
+const static uint64_t SH_FLD_PIB_MASTER_RSP_INFO_LEN = 10147; // 4
+const static uint64_t SH_FLD_PIB_RESET = 10148; // 1
+const static uint64_t SH_FLD_PIB_RESET_DURING_PIB_ACCESS = 10149; // 4
+const static uint64_t SH_FLD_PIB_RESPONSE_INFO = 10150; // 1
+const static uint64_t SH_FLD_PIB_RESPONSE_INFO_LEN = 10151; // 1
+const static uint64_t SH_FLD_PIB_RSP_INFO = 10152; // 18
+const static uint64_t SH_FLD_PIB_RSP_INFO_LEN = 10153; // 18
+const static uint64_t SH_FLD_PIB_R_NW = 10154; // 18
+const static uint64_t SH_FLD_PIB_SLAVE_ADDR_INVALID = 10155; // 4
+const static uint64_t SH_FLD_PIB_SLAVE_ADDR_PARITY = 10156; // 4
+const static uint64_t SH_FLD_PIB_SLAVE_DATA_PARITY = 10157; // 4
+const static uint64_t SH_FLD_PIB_SLAVE_READ_INVALID = 10158; // 4
+const static uint64_t SH_FLD_PIB_SLAVE_WRITE_INVALID = 10159; // 4
+const static uint64_t SH_FLD_PID = 10160; // 9
+const static uint64_t SH_FLD_PID_LEN = 10161; // 9
+const static uint64_t SH_FLD_PID_MASK = 10162; // 1
+const static uint64_t SH_FLD_PID_MASK_LEN = 10163; // 1
+const static uint64_t SH_FLD_PIPELINE_ENABLE = 10164; // 1
+const static uint64_t SH_FLD_PIPE_COUNTER = 10165; // 1
+const static uint64_t SH_FLD_PIPE_COUNTER_LEN = 10166; // 1
+const static uint64_t SH_FLD_PIPE_MARGIN = 10167; // 48
+const static uint64_t SH_FLD_PIPE_SEL = 10168; // 120
+const static uint64_t SH_FLD_PIPE_SEL_LEN = 10169; // 48
+const static uint64_t SH_FLD_PLBARB_LOCKERR = 10170; // 1
+const static uint64_t SH_FLD_PLLCVHOLD = 10171; // 6
+const static uint64_t SH_FLD_PLLFMAX = 10172; // 6
+const static uint64_t SH_FLD_PLLFMIN = 10173; // 6
+const static uint64_t SH_FLD_PLLLOCK = 10174; // 4
+const static uint64_t SH_FLD_PLLLOCK_0_FILTER_PLL_NEST = 10175; // 1
+const static uint64_t SH_FLD_PLLLOCK_1_FILTER_PLL_MC = 10176; // 1
+const static uint64_t SH_FLD_PLLLOCK_2_XBUS = 10177; // 1
+const static uint64_t SH_FLD_PLLLOCK_3_NEST = 10178; // 1
+const static uint64_t SH_FLD_PLLREFSEL = 10179; // 3
+const static uint64_t SH_FLD_PLLREFSEL_LEN = 10180; // 3
+const static uint64_t SH_FLD_PLLRESET = 10181; // 6
+const static uint64_t SH_FLD_PLL_BYPASS = 10182; // 43
+const static uint64_t SH_FLD_PLL_CLKIN_SEL = 10183; // 43
+const static uint64_t SH_FLD_PLL_DESTOUT = 10184; // 43
+const static uint64_t SH_FLD_PLL_LOCK_TIMEOUT_SEL = 10185; // 4
+const static uint64_t SH_FLD_PLL_LOCK_TIMEOUT_SEL_LEN = 10186; // 4
+const static uint64_t SH_FLD_PLL_REFCLKSEL_SCOM_EN = 10187; // 4
+const static uint64_t SH_FLD_PLL_RESET = 10188; // 51
+const static uint64_t SH_FLD_PLL_TEST_EN = 10189; // 43
+const static uint64_t SH_FLD_PLL_UNLOCK = 10190; // 43
+const static uint64_t SH_FLD_PLL_UNLOCK_LEN = 10191; // 43
+const static uint64_t SH_FLD_PL_ERR = 10192; // 6
+const static uint64_t SH_FLD_PL_FIR_ERR = 10193; // 6
+const static uint64_t SH_FLD_PM03_L23_EVENT_TID_SEL_EN = 10194; // 12
+const static uint64_t SH_FLD_PM03_L23_EVENT_TID_SEL_NUM = 10195; // 12
+const static uint64_t SH_FLD_PM03_L23_EVENT_TID_SEL_NUM_LEN = 10196; // 12
+const static uint64_t SH_FLD_PM03_SMT_ROTATION_DIS = 10197; // 12
+const static uint64_t SH_FLD_PM07_TID_ROTATE_PLSS_RATE = 10198; // 12
+const static uint64_t SH_FLD_PM07_TID_ROTATE_PLSS_RATE_LEN = 10199; // 12
+const static uint64_t SH_FLD_PM47_L23_EVENT_TID_SEL_EN = 10200; // 12
+const static uint64_t SH_FLD_PM47_L23_EVENT_TID_SEL_NUM = 10201; // 12
+const static uint64_t SH_FLD_PM47_L23_EVENT_TID_SEL_NUM_LEN = 10202; // 12
+const static uint64_t SH_FLD_PM47_SMT_ROTATION_DIS = 10203; // 12
+const static uint64_t SH_FLD_PMCM_THRESHOLD = 10204; // 24
+const static uint64_t SH_FLD_PMCM_THRESHOLD_LEN = 10205; // 24
+const static uint64_t SH_FLD_PMCR_OVERRIDE_EN = 10206; // 12
+const static uint64_t SH_FLD_PMCR_UPDATE_C0 = 10207; // 12
+const static uint64_t SH_FLD_PMCR_UPDATE_C1 = 10208; // 12
+const static uint64_t SH_FLD_PMC_O2S_0A_ONGOING = 10209; // 1
+const static uint64_t SH_FLD_PMC_O2S_0B_ONGOING = 10210; // 1
+const static uint64_t SH_FLD_PMC_O2S_1A_ONGOING = 10211; // 1
+const static uint64_t SH_FLD_PMC_O2S_1B_ONGOING = 10212; // 1
+const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE0_PENDING = 10213; // 1
+const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE1_PENDING = 10214; // 1
+const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE2_PENDING = 10215; // 1
+const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE3_PENDING = 10216; // 1
+const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE4_PENDING = 10217; // 1
+const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE5_PENDING = 10218; // 1
+const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE6_PENDING = 10219; // 1
+const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE7_PENDING = 10220; // 1
+const static uint64_t SH_FLD_PMISC_CRESP_ADDR_ERR = 10221; // 24
+const static uint64_t SH_FLD_PMON_GROUP_SELECT = 10222; // 2
+const static uint64_t SH_FLD_PMON_GROUP_SELECT_LEN = 10223; // 2
+const static uint64_t SH_FLD_PMON_MUX_BYTE0 = 10224; // 1
+const static uint64_t SH_FLD_PMON_MUX_BYTE0_LEN = 10225; // 1
+const static uint64_t SH_FLD_PMON_MUX_BYTE1 = 10226; // 1
+const static uint64_t SH_FLD_PMON_MUX_BYTE1_LEN = 10227; // 1
+const static uint64_t SH_FLD_PMON_MUX_BYTE2 = 10228; // 1
+const static uint64_t SH_FLD_PMON_MUX_BYTE2_LEN = 10229; // 1
+const static uint64_t SH_FLD_PMON_MUX_BYTE3 = 10230; // 1
+const static uint64_t SH_FLD_PMON_MUX_BYTE3_LEN = 10231; // 1
+const static uint64_t SH_FLD_PMSR_OVERRIDE_EN = 10232; // 12
+const static uint64_t SH_FLD_PMU0145_EVENT0_MODE = 10233; // 2
+const static uint64_t SH_FLD_PMU0145_EVENT0_MODE_LEN = 10234; // 2
+const static uint64_t SH_FLD_PMU0145_EVENT1_MODE = 10235; // 2
+const static uint64_t SH_FLD_PMU0145_EVENT1_MODE_LEN = 10236; // 2
+const static uint64_t SH_FLD_PMU0145_EVENT2_MODE = 10237; // 2
+const static uint64_t SH_FLD_PMU0145_EVENT2_MODE_LEN = 10238; // 2
+const static uint64_t SH_FLD_PMU0145_EVENT3_MODE = 10239; // 2
+const static uint64_t SH_FLD_PMU0145_EVENT3_MODE_LEN = 10240; // 2
+const static uint64_t SH_FLD_PMU01_LINK_SELECT = 10241; // 2
+const static uint64_t SH_FLD_PMU0_ENABLE = 10242; // 2
+const static uint64_t SH_FLD_PMU0_SIZE = 10243; // 2
+const static uint64_t SH_FLD_PMU0_SIZE_LEN = 10244; // 2
+const static uint64_t SH_FLD_PMU1_ENABLE = 10245; // 2
+const static uint64_t SH_FLD_PMU1_SIZE = 10246; // 2
+const static uint64_t SH_FLD_PMU1_SIZE_LEN = 10247; // 2
+const static uint64_t SH_FLD_PMU2367_EVENT0_MODE = 10248; // 2
+const static uint64_t SH_FLD_PMU2367_EVENT0_MODE_LEN = 10249; // 2
+const static uint64_t SH_FLD_PMU2367_EVENT1_MODE = 10250; // 2
+const static uint64_t SH_FLD_PMU2367_EVENT1_MODE_LEN = 10251; // 2
+const static uint64_t SH_FLD_PMU2367_EVENT2_MODE = 10252; // 2
+const static uint64_t SH_FLD_PMU2367_EVENT2_MODE_LEN = 10253; // 2
+const static uint64_t SH_FLD_PMU2367_EVENT3_MODE = 10254; // 2
+const static uint64_t SH_FLD_PMU2367_EVENT3_MODE_LEN = 10255; // 2
+const static uint64_t SH_FLD_PMU23_LINK_SELECT = 10256; // 2
+const static uint64_t SH_FLD_PMU2_ENABLE = 10257; // 2
+const static uint64_t SH_FLD_PMU2_SIZE = 10258; // 2
+const static uint64_t SH_FLD_PMU2_SIZE_LEN = 10259; // 2
+const static uint64_t SH_FLD_PMU3_ENABLE = 10260; // 2
+const static uint64_t SH_FLD_PMU3_SIZE = 10261; // 2
+const static uint64_t SH_FLD_PMU3_SIZE_LEN = 10262; // 2
+const static uint64_t SH_FLD_PMU45_LINK_SELECT = 10263; // 2
+const static uint64_t SH_FLD_PMU4_ENABLE = 10264; // 2
+const static uint64_t SH_FLD_PMU5_ENABLE = 10265; // 2
+const static uint64_t SH_FLD_PMU67_LINK_SELECT = 10266; // 2
+const static uint64_t SH_FLD_PMU6_ENABLE = 10267; // 2
+const static uint64_t SH_FLD_PMU7_ENABLE = 10268; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER0_BIT_PAIR_SELECT = 10269; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER0_BIT_PAIR_SELECT_LEN = 10270; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER0_ENABLE = 10271; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER0_EVENT_SELECT = 10272; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER0_EVENT_SELECT_LEN = 10273; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER0_POSEDGE_SELECT = 10274; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER1_BIT_PAIR_SELECT = 10275; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER1_BIT_PAIR_SELECT_LEN = 10276; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER1_ENABLE = 10277; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER1_EVENT_SELECT = 10278; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER1_EVENT_SELECT_LEN = 10279; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER1_POSEDGE_SELECT = 10280; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER2_BIT_PAIR_SELECT = 10281; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER2_BIT_PAIR_SELECT_LEN = 10282; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER2_ENABLE = 10283; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER2_EVENT_SELECT = 10284; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER2_EVENT_SELECT_LEN = 10285; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER2_POSEDGE_SELECT = 10286; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER3_BIT_PAIR_SELECT = 10287; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER3_BIT_PAIR_SELECT_LEN = 10288; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER3_ENABLE = 10289; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER3_EVENT_SELECT = 10290; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER3_EVENT_SELECT_LEN = 10291; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER3_POSEDGE_SELECT = 10292; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER_FREEZE_MODE = 10293; // 2
+const static uint64_t SH_FLD_PMUA_COUNTER_RESET_MODE = 10294; // 2
+const static uint64_t SH_FLD_PMUA_PORT_SELECT = 10295; // 2
+const static uint64_t SH_FLD_PMUA_PORT_SELECT_LEN = 10296; // 2
+const static uint64_t SH_FLD_PMUA_PRESCALER_SELECT = 10297; // 2
+const static uint64_t SH_FLD_PMUA_PRESCALER_SELECT_LEN = 10298; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER0_BIT_PAIR_SELECT = 10299; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER0_BIT_PAIR_SELECT_LEN = 10300; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER0_ENABLE = 10301; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER0_EVENT_SELECT = 10302; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER0_EVENT_SELECT_LEN = 10303; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER0_POSEDGE_SELECT = 10304; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER1_BIT_PAIR_SELECT = 10305; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER1_BIT_PAIR_SELECT_LEN = 10306; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER1_ENABLE = 10307; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER1_EVENT_SELECT = 10308; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER1_EVENT_SELECT_LEN = 10309; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER1_POSEDGE_SELECT = 10310; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER2_BIT_PAIR_SELECT = 10311; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER2_BIT_PAIR_SELECT_LEN = 10312; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER2_ENABLE = 10313; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER2_EVENT_SELECT = 10314; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER2_EVENT_SELECT_LEN = 10315; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER2_POSEDGE_SELECT = 10316; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER3_BIT_PAIR_SELECT = 10317; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER3_BIT_PAIR_SELECT_LEN = 10318; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER3_ENABLE = 10319; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER3_EVENT_SELECT = 10320; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER3_EVENT_SELECT_LEN = 10321; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER3_POSEDGE_SELECT = 10322; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER_FREEZE_MODE = 10323; // 2
+const static uint64_t SH_FLD_PMUB_COUNTER_RESET_MODE = 10324; // 2
+const static uint64_t SH_FLD_PMUB_PORT_SELECT = 10325; // 2
+const static uint64_t SH_FLD_PMUB_PORT_SELECT_LEN = 10326; // 2
+const static uint64_t SH_FLD_PMUB_PRESCALER_SELECT = 10327; // 2
+const static uint64_t SH_FLD_PMUB_PRESCALER_SELECT_LEN = 10328; // 2
+const static uint64_t SH_FLD_PMULET_FREEZE_MODE = 10329; // 2
+const static uint64_t SH_FLD_PMULET_RESET_MODE = 10330; // 2
+const static uint64_t SH_FLD_PMU_BUS_ENABLE = 10331; // 2
+const static uint64_t SH_FLD_PMU_BUS_ENABLE_LEN = 10332; // 2
+const static uint64_t SH_FLD_PMU_ENABLE = 10333; // 2
+const static uint64_t SH_FLD_PMU_SELECT_HIGH = 10334; // 2
+const static uint64_t SH_FLD_PMU_SELECT_HIGH_LEN = 10335; // 2
+const static uint64_t SH_FLD_PMU_SELECT_LOW = 10336; // 2
+const static uint64_t SH_FLD_PMU_SELECT_LOW_LEN = 10337; // 2
+const static uint64_t SH_FLD_PM_ERROR = 10338; // 6
+const static uint64_t SH_FLD_PM_STATE_ACTIVE_C0 = 10339; // 12
+const static uint64_t SH_FLD_PM_STATE_ACTIVE_C1 = 10340; // 12
+const static uint64_t SH_FLD_PM_STATE_ALL_HV_C0 = 10341; // 12
+const static uint64_t SH_FLD_PM_STATE_ALL_HV_C1 = 10342; // 12
+const static uint64_t SH_FLD_PM_STATE_C0 = 10343; // 12
+const static uint64_t SH_FLD_PM_STATE_C0_LEN = 10344; // 12
+const static uint64_t SH_FLD_PM_STATE_C1 = 10345; // 12
+const static uint64_t SH_FLD_PM_STATE_C1_LEN = 10346; // 12
+const static uint64_t SH_FLD_POCKET_RATE1 = 10347; // 12
+const static uint64_t SH_FLD_POCKET_RATE1_LEN = 10348; // 12
+const static uint64_t SH_FLD_POCKET_RATE2 = 10349; // 12
+const static uint64_t SH_FLD_POCKET_RATE2_LEN = 10350; // 12
+const static uint64_t SH_FLD_POCKET_RATE3 = 10351; // 12
+const static uint64_t SH_FLD_POCKET_RATE3_LEN = 10352; // 12
+const static uint64_t SH_FLD_POD0 = 10353; // 38
+const static uint64_t SH_FLD_POD0_LEN = 10354; // 38
+const static uint64_t SH_FLD_POD1 = 10355; // 38
+const static uint64_t SH_FLD_POD10 = 10356; // 38
+const static uint64_t SH_FLD_POD10_LEN = 10357; // 38
+const static uint64_t SH_FLD_POD1_LEN = 10358; // 38
+const static uint64_t SH_FLD_POD2 = 10359; // 38
+const static uint64_t SH_FLD_POD2_LEN = 10360; // 38
+const static uint64_t SH_FLD_POD3 = 10361; // 38
+const static uint64_t SH_FLD_POD3_LEN = 10362; // 38
+const static uint64_t SH_FLD_POD4 = 10363; // 38
+const static uint64_t SH_FLD_POD4_LEN = 10364; // 38
+const static uint64_t SH_FLD_POD5 = 10365; // 38
+const static uint64_t SH_FLD_POD5_LEN = 10366; // 38
+const static uint64_t SH_FLD_POD6 = 10367; // 38
+const static uint64_t SH_FLD_POD6_LEN = 10368; // 38
+const static uint64_t SH_FLD_POD7 = 10369; // 38
+const static uint64_t SH_FLD_POD7_LEN = 10370; // 38
+const static uint64_t SH_FLD_POD8 = 10371; // 38
+const static uint64_t SH_FLD_POD8_LEN = 10372; // 38
+const static uint64_t SH_FLD_POD9 = 10373; // 38
+const static uint64_t SH_FLD_POD9_LEN = 10374; // 38
+const static uint64_t SH_FLD_POINTER = 10375; // 2
+const static uint64_t SH_FLD_POINTER_LEN = 10376; // 2
+const static uint64_t SH_FLD_POLLING_TIMEOUT_SEL = 10377; // 6
+const static uint64_t SH_FLD_POLLING_TIMEOUT_SEL_LEN = 10378; // 6
+const static uint64_t SH_FLD_POLL_BCST_RTY_MON = 10379; // 1
+const static uint64_t SH_FLD_POLL_DONE = 10380; // 1
+const static uint64_t SH_FLD_POOL = 10381; // 1
+const static uint64_t SH_FLD_POOL_LEN = 10382; // 1
+const static uint64_t SH_FLD_PORT0_ERROR_CODE = 10383; // 3
+const static uint64_t SH_FLD_PORT0_ERROR_CODE_0 = 10384; // 1
+const static uint64_t SH_FLD_PORT0_ERROR_CODE_0_LEN = 10385; // 1
+const static uint64_t SH_FLD_PORT0_ERROR_CODE_1 = 10386; // 2
+const static uint64_t SH_FLD_PORT0_ERROR_CODE_1_LEN = 10387; // 2
+const static uint64_t SH_FLD_PORT0_ERROR_CODE_2 = 10388; // 3
+const static uint64_t SH_FLD_PORT0_ERROR_CODE_2_LEN = 10389; // 3
+const static uint64_t SH_FLD_PORT0_ERROR_CODE_LEN = 10390; // 3
+const static uint64_t SH_FLD_PORT1_ERROR_CODE = 10391; // 3
+const static uint64_t SH_FLD_PORT1_ERROR_CODE_0 = 10392; // 1
+const static uint64_t SH_FLD_PORT1_ERROR_CODE_0_LEN = 10393; // 1
+const static uint64_t SH_FLD_PORT1_ERROR_CODE_1 = 10394; // 2
+const static uint64_t SH_FLD_PORT1_ERROR_CODE_1_LEN = 10395; // 2
+const static uint64_t SH_FLD_PORT1_ERROR_CODE_2 = 10396; // 3
+const static uint64_t SH_FLD_PORT1_ERROR_CODE_2_LEN = 10397; // 3
+const static uint64_t SH_FLD_PORT1_ERROR_CODE_LEN = 10398; // 3
+const static uint64_t SH_FLD_PORT2_ERROR_CODE = 10399; // 3
+const static uint64_t SH_FLD_PORT2_ERROR_CODE_0 = 10400; // 1
+const static uint64_t SH_FLD_PORT2_ERROR_CODE_0_LEN = 10401; // 1
+const static uint64_t SH_FLD_PORT2_ERROR_CODE_1 = 10402; // 2
+const static uint64_t SH_FLD_PORT2_ERROR_CODE_1_LEN = 10403; // 2
+const static uint64_t SH_FLD_PORT2_ERROR_CODE_2 = 10404; // 3
+const static uint64_t SH_FLD_PORT2_ERROR_CODE_2_LEN = 10405; // 3
+const static uint64_t SH_FLD_PORT2_ERROR_CODE_LEN = 10406; // 3
+const static uint64_t SH_FLD_PORT3_ERROR_CODE = 10407; // 3
+const static uint64_t SH_FLD_PORT3_ERROR_CODE_0 = 10408; // 1
+const static uint64_t SH_FLD_PORT3_ERROR_CODE_0_LEN = 10409; // 1
+const static uint64_t SH_FLD_PORT3_ERROR_CODE_1 = 10410; // 2
+const static uint64_t SH_FLD_PORT3_ERROR_CODE_1_LEN = 10411; // 2
+const static uint64_t SH_FLD_PORT3_ERROR_CODE_2 = 10412; // 3
+const static uint64_t SH_FLD_PORT3_ERROR_CODE_2_LEN = 10413; // 3
+const static uint64_t SH_FLD_PORT3_ERROR_CODE_LEN = 10414; // 3
+const static uint64_t SH_FLD_PORT4_ERROR_CODE = 10415; // 3
+const static uint64_t SH_FLD_PORT4_ERROR_CODE_0 = 10416; // 1
+const static uint64_t SH_FLD_PORT4_ERROR_CODE_0_LEN = 10417; // 1
+const static uint64_t SH_FLD_PORT4_ERROR_CODE_1 = 10418; // 2
+const static uint64_t SH_FLD_PORT4_ERROR_CODE_1_LEN = 10419; // 2
+const static uint64_t SH_FLD_PORT4_ERROR_CODE_2 = 10420; // 3
+const static uint64_t SH_FLD_PORT4_ERROR_CODE_2_LEN = 10421; // 3
+const static uint64_t SH_FLD_PORT4_ERROR_CODE_LEN = 10422; // 3
+const static uint64_t SH_FLD_PORT5_ERROR_CODE = 10423; // 3
+const static uint64_t SH_FLD_PORT5_ERROR_CODE_0 = 10424; // 1
+const static uint64_t SH_FLD_PORT5_ERROR_CODE_0_LEN = 10425; // 1
+const static uint64_t SH_FLD_PORT5_ERROR_CODE_1 = 10426; // 2
+const static uint64_t SH_FLD_PORT5_ERROR_CODE_1_LEN = 10427; // 2
+const static uint64_t SH_FLD_PORT5_ERROR_CODE_2 = 10428; // 3
+const static uint64_t SH_FLD_PORT5_ERROR_CODE_2_LEN = 10429; // 3
+const static uint64_t SH_FLD_PORT5_ERROR_CODE_LEN = 10430; // 3
+const static uint64_t SH_FLD_PORT6_ERROR_CODE = 10431; // 3
+const static uint64_t SH_FLD_PORT6_ERROR_CODE_0 = 10432; // 1
+const static uint64_t SH_FLD_PORT6_ERROR_CODE_0_LEN = 10433; // 1
+const static uint64_t SH_FLD_PORT6_ERROR_CODE_1 = 10434; // 2
+const static uint64_t SH_FLD_PORT6_ERROR_CODE_1_LEN = 10435; // 2
+const static uint64_t SH_FLD_PORT6_ERROR_CODE_2 = 10436; // 3
+const static uint64_t SH_FLD_PORT6_ERROR_CODE_2_LEN = 10437; // 3
+const static uint64_t SH_FLD_PORT6_ERROR_CODE_LEN = 10438; // 3
+const static uint64_t SH_FLD_PORT7_ERROR_CODE = 10439; // 3
+const static uint64_t SH_FLD_PORT7_ERROR_CODE_0 = 10440; // 1
+const static uint64_t SH_FLD_PORT7_ERROR_CODE_0_LEN = 10441; // 1
+const static uint64_t SH_FLD_PORT7_ERROR_CODE_1 = 10442; // 2
+const static uint64_t SH_FLD_PORT7_ERROR_CODE_1_LEN = 10443; // 2
+const static uint64_t SH_FLD_PORT7_ERROR_CODE_2 = 10444; // 3
+const static uint64_t SH_FLD_PORT7_ERROR_CODE_2_LEN = 10445; // 3
+const static uint64_t SH_FLD_PORT7_ERROR_CODE_LEN = 10446; // 3
+const static uint64_t SH_FLD_PORTA_CE_ERR = 10447; // 2
+const static uint64_t SH_FLD_PORTA_CNTL_TRAP_SUBTST_NUM = 10448; // 2
+const static uint64_t SH_FLD_PORTA_CNTL_TRAP_SUBTST_NUM_LEN = 10449; // 2
+const static uint64_t SH_FLD_PORTA_ERR_LOG_PTR = 10450; // 2
+const static uint64_t SH_FLD_PORTA_ERR_LOG_PTR_LEN = 10451; // 2
+const static uint64_t SH_FLD_PORTA_ERR_TRAP_OVERFLOW = 10452; // 2
+const static uint64_t SH_FLD_PORTA_UE_ERR = 10453; // 2
+const static uint64_t SH_FLD_PORT_0_ENABLE = 10454; // 1
+const static uint64_t SH_FLD_PORT_0_MAINLINE_AUE_ADDR_TRAP = 10455; // 2
+const static uint64_t SH_FLD_PORT_0_MAINLINE_AUE_ADDR_TRAP_LEN = 10456; // 2
+const static uint64_t SH_FLD_PORT_0_MAINLINE_MPE_ADDR_TRAP = 10457; // 2
+const static uint64_t SH_FLD_PORT_0_MAINLINE_MPE_ADDR_TRAP_LEN = 10458; // 2
+const static uint64_t SH_FLD_PORT_0_MAINLINE_MPE_ON_RCE = 10459; // 2
+const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_ADDR_TRAP = 10460; // 2
+const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_ADDR_TRAP_LEN = 10461; // 2
+const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_GALOIS_FIELD = 10462; // 2
+const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_GALOIS_FIELD_LEN = 10463; // 2
+const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_IS_TCE = 10464; // 2
+const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD = 10465; // 2
+const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD_LEN =
+    10466; // 2
+const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_ON_RCE = 10467; // 2
+const static uint64_t SH_FLD_PORT_0_MAINLINE_RCE_ADDR_TRAP = 10468; // 2
+const static uint64_t SH_FLD_PORT_0_MAINLINE_RCE_ADDR_TRAP_LEN = 10469; // 2
+const static uint64_t SH_FLD_PORT_0_MAINLINE_TCE_GALOIS_FIELD = 10470; // 2
+const static uint64_t SH_FLD_PORT_0_MAINLINE_TCE_GALOIS_FIELD_LEN = 10471; // 2
+const static uint64_t SH_FLD_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD = 10472; // 2
+const static uint64_t SH_FLD_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD_LEN =
+    10473; // 2
+const static uint64_t SH_FLD_PORT_0_MAINLINE_UE_ADDR_TRAP = 10474; // 2
+const static uint64_t SH_FLD_PORT_0_MAINLINE_UE_ADDR_TRAP_LEN = 10475; // 2
+const static uint64_t SH_FLD_PORT_1_ENABLE = 10476; // 2
+const static uint64_t SH_FLD_PORT_1_MAINLINE_AUE_ADDR_TRAP = 10477; // 2
+const static uint64_t SH_FLD_PORT_1_MAINLINE_AUE_ADDR_TRAP_LEN = 10478; // 2
+const static uint64_t SH_FLD_PORT_1_MAINLINE_MPE_ADDR_TRAP = 10479; // 2
+const static uint64_t SH_FLD_PORT_1_MAINLINE_MPE_ADDR_TRAP_LEN = 10480; // 2
+const static uint64_t SH_FLD_PORT_1_MAINLINE_MPE_ON_RCE = 10481; // 2
+const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_ADDR_TRAP = 10482; // 2
+const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_ADDR_TRAP_LEN = 10483; // 2
+const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_GALOIS_FIELD = 10484; // 2
+const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_GALOIS_FIELD_LEN = 10485; // 2
+const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_IS_TCE = 10486; // 2
+const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD = 10487; // 2
+const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD_LEN =
+    10488; // 2
+const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_ON_RCE = 10489; // 2
+const static uint64_t SH_FLD_PORT_1_MAINLINE_RCE_ADDR_TRAP = 10490; // 2
+const static uint64_t SH_FLD_PORT_1_MAINLINE_RCE_ADDR_TRAP_LEN = 10491; // 2
+const static uint64_t SH_FLD_PORT_1_MAINLINE_TCE_GALOIS_FIELD = 10492; // 2
+const static uint64_t SH_FLD_PORT_1_MAINLINE_TCE_GALOIS_FIELD_LEN = 10493; // 2
+const static uint64_t SH_FLD_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD = 10494; // 2
+const static uint64_t SH_FLD_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD_LEN =
+    10495; // 2
+const static uint64_t SH_FLD_PORT_1_MAINLINE_UE_ADDR_TRAP = 10496; // 2
+const static uint64_t SH_FLD_PORT_1_MAINLINE_UE_ADDR_TRAP_LEN = 10497; // 2
+const static uint64_t SH_FLD_PORT_2_ENABLE = 10498; // 3
+const static uint64_t SH_FLD_PORT_2_MAINLINE_AUE_ADDR_TRAP = 10499; // 2
+const static uint64_t SH_FLD_PORT_2_MAINLINE_AUE_ADDR_TRAP_LEN = 10500; // 2
+const static uint64_t SH_FLD_PORT_2_MAINLINE_MPE_ADDR_TRAP = 10501; // 2
+const static uint64_t SH_FLD_PORT_2_MAINLINE_MPE_ADDR_TRAP_LEN = 10502; // 2
+const static uint64_t SH_FLD_PORT_2_MAINLINE_MPE_ON_RCE = 10503; // 2
+const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_ADDR_TRAP = 10504; // 2
+const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_ADDR_TRAP_LEN = 10505; // 2
+const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_GALOIS_FIELD = 10506; // 2
+const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_GALOIS_FIELD_LEN = 10507; // 2
+const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_IS_TCE = 10508; // 2
+const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD = 10509; // 2
+const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD_LEN =
+    10510; // 2
+const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_ON_RCE = 10511; // 2
+const static uint64_t SH_FLD_PORT_2_MAINLINE_RCE_ADDR_TRAP = 10512; // 2
+const static uint64_t SH_FLD_PORT_2_MAINLINE_RCE_ADDR_TRAP_LEN = 10513; // 2
+const static uint64_t SH_FLD_PORT_2_MAINLINE_TCE_GALOIS_FIELD = 10514; // 2
+const static uint64_t SH_FLD_PORT_2_MAINLINE_TCE_GALOIS_FIELD_LEN = 10515; // 2
+const static uint64_t SH_FLD_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD = 10516; // 2
+const static uint64_t SH_FLD_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD_LEN =
+    10517; // 2
+const static uint64_t SH_FLD_PORT_2_MAINLINE_UE_ADDR_TRAP = 10518; // 2
+const static uint64_t SH_FLD_PORT_2_MAINLINE_UE_ADDR_TRAP_LEN = 10519; // 2
+const static uint64_t SH_FLD_PORT_3_ENABLE = 10520; // 3
+const static uint64_t SH_FLD_PORT_3_MAINLINE_AUE_ADDR_TRAP = 10521; // 2
+const static uint64_t SH_FLD_PORT_3_MAINLINE_AUE_ADDR_TRAP_LEN = 10522; // 2
+const static uint64_t SH_FLD_PORT_3_MAINLINE_MPE_ADDR_TRAP = 10523; // 2
+const static uint64_t SH_FLD_PORT_3_MAINLINE_MPE_ADDR_TRAP_LEN = 10524; // 2
+const static uint64_t SH_FLD_PORT_3_MAINLINE_MPE_ON_RCE = 10525; // 2
+const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_ADDR_TRAP = 10526; // 2
+const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_ADDR_TRAP_LEN = 10527; // 2
+const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_GALOIS_FIELD = 10528; // 2
+const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_GALOIS_FIELD_LEN = 10529; // 2
+const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_IS_TCE = 10530; // 2
+const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD = 10531; // 2
+const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD_LEN =
+    10532; // 2
+const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_ON_RCE = 10533; // 2
+const static uint64_t SH_FLD_PORT_3_MAINLINE_RCE_ADDR_TRAP = 10534; // 2
+const static uint64_t SH_FLD_PORT_3_MAINLINE_RCE_ADDR_TRAP_LEN = 10535; // 2
+const static uint64_t SH_FLD_PORT_3_MAINLINE_TCE_GALOIS_FIELD = 10536; // 2
+const static uint64_t SH_FLD_PORT_3_MAINLINE_TCE_GALOIS_FIELD_LEN = 10537; // 2
+const static uint64_t SH_FLD_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD = 10538; // 2
+const static uint64_t SH_FLD_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD_LEN =
+    10539; // 2
+const static uint64_t SH_FLD_PORT_3_MAINLINE_UE_ADDR_TRAP = 10540; // 2
+const static uint64_t SH_FLD_PORT_3_MAINLINE_UE_ADDR_TRAP_LEN = 10541; // 2
+const static uint64_t SH_FLD_PORT_4_ENABLE = 10542; // 3
+const static uint64_t SH_FLD_PORT_5_ENABLE = 10543; // 3
+const static uint64_t SH_FLD_PORT_6_ENABLE = 10544; // 3
+const static uint64_t SH_FLD_PORT_7_ENABLE = 10545; // 3
+const static uint64_t SH_FLD_PORT_ENABLE = 10546; // 3
+const static uint64_t SH_FLD_PORT_ERROR_RESET = 10547; // 1
+const static uint64_t SH_FLD_PORT_ERROR_RESET_1 = 10548; // 2
+const static uint64_t SH_FLD_PORT_ERROR_RESET_2 = 10549; // 3
+const static uint64_t SH_FLD_PORT_ERROR_RESET_3 = 10550; // 3
+const static uint64_t SH_FLD_PORT_ERROR_RESET_4 = 10551; // 3
+const static uint64_t SH_FLD_PORT_ERROR_RESET_5 = 10552; // 3
+const static uint64_t SH_FLD_PORT_ERROR_RESET_6 = 10553; // 3
+const static uint64_t SH_FLD_PORT_ERROR_RESET_7 = 10554; // 3
+const static uint64_t SH_FLD_PORT_GENERAL_RESET = 10555; // 1
+const static uint64_t SH_FLD_PORT_GENERAL_RESET_1 = 10556; // 2
+const static uint64_t SH_FLD_PORT_GENERAL_RESET_2 = 10557; // 3
+const static uint64_t SH_FLD_PORT_GENERAL_RESET_3 = 10558; // 3
+const static uint64_t SH_FLD_PORT_GENERAL_RESET_4 = 10559; // 3
+const static uint64_t SH_FLD_PORT_GENERAL_RESET_5 = 10560; // 3
+const static uint64_t SH_FLD_PORT_GENERAL_RESET_6 = 10561; // 3
+const static uint64_t SH_FLD_PORT_GENERAL_RESET_7 = 10562; // 3
+const static uint64_t SH_FLD_PORT_NUMBER = 10563; // 1
+const static uint64_t SH_FLD_PORT_NUMBER_0 = 10564; // 1
+const static uint64_t SH_FLD_PORT_NUMBER_0_LEN = 10565; // 1
+const static uint64_t SH_FLD_PORT_NUMBER_1 = 10566; // 1
+const static uint64_t SH_FLD_PORT_NUMBER_1_LEN = 10567; // 1
+const static uint64_t SH_FLD_PORT_NUMBER_2 = 10568; // 1
+const static uint64_t SH_FLD_PORT_NUMBER_2_LEN = 10569; // 1
+const static uint64_t SH_FLD_PORT_NUMBER_3 = 10570; // 1
+const static uint64_t SH_FLD_PORT_NUMBER_3_LEN = 10571; // 1
+const static uint64_t SH_FLD_PORT_NUMBER_LEN = 10572; // 1
+const static uint64_t SH_FLD_PORT_SEL = 10573; // 1
+const static uint64_t SH_FLD_PORT_SEL_LEN = 10574; // 1
+const static uint64_t SH_FLD_POWDN_DLY = 10575; // 30
+const static uint64_t SH_FLD_POWDN_DLY_LEN = 10576; // 30
+const static uint64_t SH_FLD_POWERBUS_DATA_HANG_ERROR = 10577; // 4
+const static uint64_t SH_FLD_POWERBUS_HANG_ERROR = 10578; // 4
+const static uint64_t SH_FLD_POWERBUS_INTERFACE_PE = 10579; // 4
+const static uint64_t SH_FLD_POWERBUS_MISC_ERROR = 10580; // 4
+const static uint64_t SH_FLD_POWERBUS_PROTOCOL_ERROR = 10581; // 4
+const static uint64_t SH_FLD_POWER_MANAGEMENT_INTERRUPT = 10582; // 1
+const static uint64_t SH_FLD_POWER_SAVING_LIMIT_A_N = 10583; // 96
+const static uint64_t SH_FLD_POWER_SAVING_LIMIT_A_N_LEN = 10584; // 96
+const static uint64_t SH_FLD_POWER_UP_CNTR_REF = 10585; // 1
+const static uint64_t SH_FLD_POWER_UP_CNTR_REF_LEN = 10586; // 1
+const static uint64_t SH_FLD_POWUP_DLY = 10587; // 30
+const static uint64_t SH_FLD_POWUP_DLY_LEN = 10588; // 30
+const static uint64_t SH_FLD_PPC405_HALT = 10589; // 1
+const static uint64_t SH_FLD_PPE_BREAKPOINT_ERROR = 10590; // 12
+const static uint64_t SH_FLD_PPE_DEBUG_TRIGGER = 10591; // 12
+const static uint64_t SH_FLD_PPE_EXTERNAL_ERROR = 10592; // 12
+const static uint64_t SH_FLD_PPE_HALTED = 10593; // 12
+const static uint64_t SH_FLD_PPE_INTERNAL_ERROR = 10594; // 12
+const static uint64_t SH_FLD_PPE_PROGRESS_ERROR = 10595; // 12
+const static uint64_t SH_FLD_PPE_RD_ACK_DEAD = 10596; // 12
+const static uint64_t SH_FLD_PPE_RD_CRESP_ADDR_ERR = 10597; // 24
+const static uint64_t SH_FLD_PPE_RD_FOREIGN0_ACK_DEAD = 10598; // 12
+const static uint64_t SH_FLD_PPE_RD_FOREIGN1_ACK_DEAD = 10599; // 12
+const static uint64_t SH_FLD_PPE_WATCHDOG = 10600; // 12
+const static uint64_t SH_FLD_PPE_WR_ACK_DEAD = 10601; // 12
+const static uint64_t SH_FLD_PPE_WR_CRESP_ADDR_ERR = 10602; // 24
+const static uint64_t SH_FLD_PPE_WR_FOREIGN0_ACK_DEAD = 10603; // 12
+const static uint64_t SH_FLD_PPE_WR_FOREIGN1_ACK_DEAD = 10604; // 12
+const static uint64_t SH_FLD_PPE_XIRAMEDR_EDR = 10605; // 4
+const static uint64_t SH_FLD_PPE_XIRAMEDR_EDR_LEN = 10606; // 4
+const static uint64_t SH_FLD_PPE_XIRAMGA_IR = 10607; // 4
+const static uint64_t SH_FLD_PPE_XIRAMGA_IR_LEN = 10608; // 4
+const static uint64_t SH_FLD_PPE_XIRAMRA_SPRG0 = 10609; // 4
+const static uint64_t SH_FLD_PPE_XIRAMRA_SPRG0_LEN = 10610; // 4
+const static uint64_t SH_FLD_PPE_XIXCR_XCR = 10611; // 4
+const static uint64_t SH_FLD_PPE_XIXCR_XCR_LEN = 10612; // 4
+const static uint64_t SH_FLD_PPM_SPARE_OUT_C0 = 10613; // 12
+const static uint64_t SH_FLD_PPM_SPARE_OUT_C1 = 10614; // 12
+const static uint64_t SH_FLD_PPM_WRITE_DISABLE = 10615; // 24
+const static uint64_t SH_FLD_PPM_WRITE_OVERRIDE = 10616; // 24
+const static uint64_t SH_FLD_PRBS_CHECK_SYNC = 10617; // 72
+const static uint64_t SH_FLD_PRBS_SCRAMBLE_MODE = 10618; // 144
+const static uint64_t SH_FLD_PRBS_SCRAMBLE_MODE_LEN = 10619; // 144
+const static uint64_t SH_FLD_PRBS_SEED_DDC = 10620; // 72
+const static uint64_t SH_FLD_PRBS_SEED_MODE = 10621; // 76
+const static uint64_t SH_FLD_PRBS_SEED_VALUE_0_15 = 10622; // 140
+const static uint64_t SH_FLD_PRBS_SEED_VALUE_0_15_LEN = 10623; // 140
+const static uint64_t SH_FLD_PRBS_SEED_VALUE_16_22 = 10624; // 140
+const static uint64_t SH_FLD_PRBS_SEED_VALUE_16_22_LEN = 10625; // 140
+const static uint64_t SH_FLD_PRBS_SLS_EXPECT = 10626; // 4
+const static uint64_t SH_FLD_PRBS_SLS_EXPECT_LEN = 10627; // 4
+const static uint64_t SH_FLD_PRBS_SYNC_MODE = 10628; // 72
+const static uint64_t SH_FLD_PRBS_TEST_DATA = 10629; // 120
+const static uint64_t SH_FLD_PRBS_TEST_DATA_LEN = 10630; // 120
+const static uint64_t SH_FLD_PRECISE_DIR_FLUSH_FAILED = 10631; // 2
+const static uint64_t SH_FLD_PRECISE_DIR_SIZE = 10632; // 2
+const static uint64_t SH_FLD_PRECISE_DIR_SIZE_LEN = 10633; // 2
+const static uint64_t SH_FLD_PRECLUDE = 10634; // 1
+const static uint64_t SH_FLD_PREFETCH = 10635; // 6
+const static uint64_t SH_FLD_PREFETCH_CHANNEL_CNT = 10636; // 1
+const static uint64_t SH_FLD_PREFETCH_CHANNEL_CNT_LEN = 10637; // 1
+const static uint64_t SH_FLD_PREFETCH_DISABLE = 10638; // 6
+const static uint64_t SH_FLD_PREFETCH_DISTANCE = 10639; // 6
+const static uint64_t SH_FLD_PREFETCH_DISTANCE_LEN = 10640; // 6
+const static uint64_t SH_FLD_PREFETCH_LIMIT = 10641; // 8
+const static uint64_t SH_FLD_PREFETCH_LIMIT_LEN = 10642; // 8
+const static uint64_t SH_FLD_PREF_DEPTH = 10643; // 1
+const static uint64_t SH_FLD_PREF_DEPTH_LEN = 10644; // 1
+const static uint64_t SH_FLD_PREF_THRSH0 = 10645; // 1
+const static uint64_t SH_FLD_PREF_THRSH0_LEN = 10646; // 1
+const static uint64_t SH_FLD_PREF_THRSH1 = 10647; // 1
+const static uint64_t SH_FLD_PREF_THRSH1_LEN = 10648; // 1
+const static uint64_t SH_FLD_PREF_THRSH2 = 10649; // 1
+const static uint64_t SH_FLD_PREF_THRSH2_LEN = 10650; // 1
+const static uint64_t SH_FLD_PREF_THRSH3 = 10651; // 1
+const static uint64_t SH_FLD_PREF_THRSH3_LEN = 10652; // 1
+const static uint64_t SH_FLD_PREF_TIMEOUT = 10653; // 1
+const static uint64_t SH_FLD_PREF_TIMEOUT_LEN = 10654; // 1
+const static uint64_t SH_FLD_PRESCALAR_SEL0 = 10655; // 2
+const static uint64_t SH_FLD_PRESCALAR_SEL0_LEN = 10656; // 2
+const static uint64_t SH_FLD_PRESCALAR_SEL1 = 10657; // 2
+const static uint64_t SH_FLD_PRESCALAR_SEL1_LEN = 10658; // 2
+const static uint64_t SH_FLD_PRESCALAR_SEL2 = 10659; // 2
+const static uint64_t SH_FLD_PRESCALAR_SEL2_LEN = 10660; // 2
+const static uint64_t SH_FLD_PRESCALAR_SEL3 = 10661; // 2
+const static uint64_t SH_FLD_PRESCALAR_SEL3_LEN = 10662; // 2
+const static uint64_t SH_FLD_PRESCALER_SEL = 10663; // 1
+const static uint64_t SH_FLD_PRESCALER_SEL_LEN = 10664; // 1
+const static uint64_t SH_FLD_PRESP_RTY_OTHER = 10665; // 2
+const static uint64_t SH_FLD_PREVENT_SBE_START = 10666; // 1
+const static uint64_t SH_FLD_PRGM_ADDR = 10667; // 1
+const static uint64_t SH_FLD_PRGM_ADDR_LEN = 10668; // 1
+const static uint64_t SH_FLD_PRGSM_BUSY = 10669; // 24
+const static uint64_t SH_FLD_PRGSM_BUSY_ON_THIS = 10670; // 24
+const static uint64_t SH_FLD_PRG_BIT_LOCATION = 10671; // 1
+const static uint64_t SH_FLD_PRG_BIT_LOCATION_LEN = 10672; // 1
+const static uint64_t SH_FLD_PRI = 10673; // 8
+const static uint64_t SH_FLD_PRIORITY = 10674; // 18
+const static uint64_t SH_FLD_PRIORITY_ENABLE = 10675; // 6
+const static uint64_t SH_FLD_PRIORITY_LEN = 10676; // 6
+const static uint64_t SH_FLD_PRIORITY_LIMIT_0_3 = 10677; // 1
+const static uint64_t SH_FLD_PRIORITY_LIMIT_0_3_LEN = 10678; // 1
+const static uint64_t SH_FLD_PRIORITY_LPID = 10679; // 6
+const static uint64_t SH_FLD_PRIORITY_LPID_LEN = 10680; // 6
+const static uint64_t SH_FLD_PRIORITY_PID = 10681; // 6
+const static uint64_t SH_FLD_PRIORITY_PID_LEN = 10682; // 6
+const static uint64_t SH_FLD_PRIORITY_PRIMAX = 10683; // 3
+const static uint64_t SH_FLD_PRIORITY_PRIMAX_LEN = 10684; // 3
+const static uint64_t SH_FLD_PRIORITY_QUEUED = 10685; // 6
+const static uint64_t SH_FLD_PRIORITY_QUEUED_LEN = 10686; // 6
+const static uint64_t SH_FLD_PRIORITY_READ_OFFSET = 10687; // 6
+const static uint64_t SH_FLD_PRIORITY_READ_OFFSET_LEN = 10688; // 6
+const static uint64_t SH_FLD_PRIORITY_SIZE = 10689; // 6
+const static uint64_t SH_FLD_PRIORITY_SIZE_LEN = 10690; // 6
+const static uint64_t SH_FLD_PRIORITY_TID = 10691; // 6
+const static uint64_t SH_FLD_PRIORITY_TID_LEN = 10692; // 6
+const static uint64_t SH_FLD_PRI_I_PATH_STEP_CHECK_ENABLE = 10693; // 1
+const static uint64_t SH_FLD_PRI_LEN = 10694; // 8
+const static uint64_t SH_FLD_PRI_M_PATH_0_STEP_CHECK_ENABLE = 10695; // 1
+const static uint64_t SH_FLD_PRI_M_PATH_1_STEP_CHECK_ENABLE = 10696; // 1
+const static uint64_t SH_FLD_PRI_M_PATH_SELECT = 10697; // 2
+const static uint64_t SH_FLD_PRI_M_S_DRAWER_SELECT = 10698; // 2
+const static uint64_t SH_FLD_PRI_M_S_SELECT = 10699; // 2
+const static uint64_t SH_FLD_PRI_SEC_SELECT = 10700; // 1
+const static uint64_t SH_FLD_PRI_SEC_SELECT_LEN = 10701; // 1
+const static uint64_t SH_FLD_PRI_SELECT = 10702; // 1
+const static uint64_t SH_FLD_PRI_S_PATH_0_STEP_CHECK_ENABLE = 10703; // 1
+const static uint64_t SH_FLD_PRI_S_PATH_1_STEP_CHECK_ENABLE = 10704; // 1
+const static uint64_t SH_FLD_PRI_S_PATH_SELECT = 10705; // 1
+const static uint64_t SH_FLD_PRI_V = 10706; // 8
+const static uint64_t SH_FLD_PROBE_0_TOGGLE_ENABLE = 10707; // 1
+const static uint64_t SH_FLD_PROBE_1_TOGGLE_ENABLE = 10708; // 1
+const static uint64_t SH_FLD_PROBE_2_TOGGLE_ENABLE = 10709; // 1
+const static uint64_t SH_FLD_PROBE_3_TOGGLE_ENABLE = 10710; // 1
+const static uint64_t SH_FLD_PROC_RCVY_AGAIN = 10711; // 96
+const static uint64_t SH_FLD_PROC_RCVY_DONE = 10712; // 96
+const static uint64_t SH_FLD_PROGRAM_ENABLE = 10713; // 1
+const static uint64_t SH_FLD_PROG_REQ_DELAY = 10714; // 1
+const static uint64_t SH_FLD_PROG_REQ_DELAY_LEN = 10715; // 1
+const static uint64_t SH_FLD_PROTECTION_CHECK = 10716; // 1
+const static uint64_t SH_FLD_PROTOCOL = 10717; // 8
+const static uint64_t SH_FLD_PROTOCOL_ERROR = 10718; // 43
+const static uint64_t SH_FLD_PROTOCOL_LEN = 10719; // 8
+const static uint64_t SH_FLD_PROT_EX_SPARE0 = 10720; // 1
+const static uint64_t SH_FLD_PROT_EX_SPARE1 = 10721; // 1
+const static uint64_t SH_FLD_PROT_TP_SPARE0 = 10722; // 1
+const static uint64_t SH_FLD_PROT_TP_SPARE1 = 10723; // 1
+const static uint64_t SH_FLD_PROT_TP_SPARE2 = 10724; // 1
+const static uint64_t SH_FLD_PRPG_A_VAL = 10725; // 43
+const static uint64_t SH_FLD_PRPG_A_VAL_LEN = 10726; // 43
+const static uint64_t SH_FLD_PRPG_B_VAL = 10727; // 43
+const static uint64_t SH_FLD_PRPG_B_VAL_LEN = 10728; // 43
+const static uint64_t SH_FLD_PRPG_MODE = 10729; // 43
+const static uint64_t SH_FLD_PRPG_VALUE = 10730; // 43
+const static uint64_t SH_FLD_PRPG_VALUE_LEN = 10731; // 43
+const static uint64_t SH_FLD_PRPG_WEIGHTING = 10732; // 43
+const static uint64_t SH_FLD_PRPG_WEIGHTING_LEN = 10733; // 43
+const static uint64_t SH_FLD_PR_BUMP_SL_1UI = 10734; // 120
+const static uint64_t SH_FLD_PR_BUMP_SR_1UI = 10735; // 120
+const static uint64_t SH_FLD_PR_BUMP_TO_CENTER = 10736; // 72
+const static uint64_t SH_FLD_PR_BUMP_TO_EDGE_A = 10737; // 120
+const static uint64_t SH_FLD_PR_BUMP_TO_EDGE_B = 10738; // 48
+const static uint64_t SH_FLD_PR_DATA_A_OFFSET = 10739; // 120
+const static uint64_t SH_FLD_PR_DATA_A_OFFSET_LEN = 10740; // 120
+const static uint64_t SH_FLD_PR_DATA_B_OFFSET = 10741; // 120
+const static uint64_t SH_FLD_PR_DATA_B_OFFSET_LEN = 10742; // 120
+const static uint64_t SH_FLD_PR_DDC_A = 10743; // 120
+const static uint64_t SH_FLD_PR_DDC_B = 10744; // 48
+const static uint64_t SH_FLD_PR_EDGE_TRACK_CNTL = 10745; // 120
+const static uint64_t SH_FLD_PR_EDGE_TRACK_CNTL_LEN = 10746; // 120
+const static uint64_t SH_FLD_PR_FW_INERTIA_AMT = 10747; // 48
+const static uint64_t SH_FLD_PR_FW_INERTIA_AMT_LEN = 10748; // 48
+const static uint64_t SH_FLD_PR_FW_OFF = 10749; // 48
+const static uint64_t SH_FLD_PR_HALFRATE_MODE = 10750; // 120
+const static uint64_t SH_FLD_PR_INVALID_LOCK_BUMP_SIZE = 10751; // 120
+const static uint64_t SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN = 10752; // 120
+const static uint64_t SH_FLD_PR_INVALID_LOCK_FILTER_EN = 10753; // 120
+const static uint64_t SH_FLD_PR_IQ_RES_SEL = 10754; // 120
+const static uint64_t SH_FLD_PR_IQ_RES_SEL_LEN = 10755; // 120
+const static uint64_t SH_FLD_PR_LOCK_DONE = 10756; // 120
+const static uint64_t SH_FLD_PR_PHASE_STEP = 10757; // 120
+const static uint64_t SH_FLD_PR_PHASE_STEP_LEN = 10758; // 120
+const static uint64_t SH_FLD_PR_RESET = 10759; // 48
+const static uint64_t SH_FLD_PR_TRACE_DDC_SM = 10760; // 120
+const static uint64_t SH_FLD_PR_TRACE_DDC_SM_LEN = 10761; // 120
+const static uint64_t SH_FLD_PR_TRACE_DDC_STOP = 10762; // 120
+const static uint64_t SH_FLD_PR_TRACE_WOBBLE_SM = 10763; // 120
+const static uint64_t SH_FLD_PR_TRACE_WOBBLE_SM_LEN = 10764; // 120
+const static uint64_t SH_FLD_PR_TRACE_WOBBLE_STOP = 10765; // 120
+const static uint64_t SH_FLD_PR_USE_DFE_CLOCK_A = 10766; // 120
+const static uint64_t SH_FLD_PR_USE_DFE_CLOCK_B = 10767; // 48
+const static uint64_t SH_FLD_PR_WOBBLE_A = 10768; // 120
+const static uint64_t SH_FLD_PR_WOBBLE_B = 10769; // 48
+const static uint64_t SH_FLD_PR_WOBBLE_EDGE = 10770; // 48
+const static uint64_t SH_FLD_PSCR_OVERRIDE_EN = 10771; // 12
+const static uint64_t SH_FLD_PSEG_MAIN_EN = 10772; // 6
+const static uint64_t SH_FLD_PSEG_MAIN_EN_LEN = 10773; // 6
+const static uint64_t SH_FLD_PSEG_MARGINPD_EN = 10774; // 6
+const static uint64_t SH_FLD_PSEG_MARGINPD_EN_LEN = 10775; // 6
+const static uint64_t SH_FLD_PSEG_MARGINPU_EN = 10776; // 6
+const static uint64_t SH_FLD_PSEG_MARGINPU_EN_LEN = 10777; // 6
+const static uint64_t SH_FLD_PSEG_POST_EN = 10778; // 2
+const static uint64_t SH_FLD_PSEG_POST_EN_LEN = 10779; // 2
+const static uint64_t SH_FLD_PSEG_POST_SEL = 10780; // 2
+const static uint64_t SH_FLD_PSEG_POST_SEL_LEN = 10781; // 2
+const static uint64_t SH_FLD_PSEG_PRE_EN = 10782; // 6
+const static uint64_t SH_FLD_PSEG_PRE_EN_LEN = 10783; // 6
+const static uint64_t SH_FLD_PSEG_PRE_SEL = 10784; // 6
+const static uint64_t SH_FLD_PSEG_PRE_SEL_LEN = 10785; // 6
+const static uint64_t SH_FLD_PSIFSP_ACK_TIMEOUT = 10786; // 1
+const static uint64_t SH_FLD_PSIFSP_DMAR_OUTSTANDING = 10787; // 1
+const static uint64_t SH_FLD_PSIFSP_DMA_ADDR_ERR = 10788; // 1
+const static uint64_t SH_FLD_PSIFSP_DMA_ERR = 10789; // 1
+const static uint64_t SH_FLD_PSIFSP_INT_BUSY = 10790; // 1
+const static uint64_t SH_FLD_PSIFSP_INV_OP = 10791; // 1
+const static uint64_t SH_FLD_PSIFSP_LOAD_OUTSTANDING = 10792; // 1
+const static uint64_t SH_FLD_PSIFSP_MMIO_ADDR_ERR = 10793; // 1
+const static uint64_t SH_FLD_PSIFSP_MMIO_LENGTH_ERR = 10794; // 1
+const static uint64_t SH_FLD_PSIFSP_MMIO_LOAD_TIMEOUT = 10795; // 1
+const static uint64_t SH_FLD_PSIFSP_MMIO_TYPE_ERR = 10796; // 1
+const static uint64_t SH_FLD_PSIFSP_PAGE_FAULT = 10797; // 1
+const static uint64_t SH_FLD_PSIFSP_PERR = 10798; // 1
+const static uint64_t SH_FLD_PSIFSP_TCE_EXTENT_ERR = 10799; // 1
+const static uint64_t SH_FLD_PSIHB2FSP_INJ_CONST = 10800; // 1
+const static uint64_t SH_FLD_PSIHB2FSP_INJ_ERR_BITS = 10801; // 1
+const static uint64_t SH_FLD_PSIHB2FSP_INJ_ERR_BITS_LEN = 10802; // 1
+const static uint64_t SH_FLD_PSIHB2FSP_INJ_ONCE = 10803; // 1
+const static uint64_t SH_FLD_PSIHB2PB_INJ_CONST = 10804; // 1
+const static uint64_t SH_FLD_PSIHB2PB_INJ_ERR_BITS = 10805; // 1
+const static uint64_t SH_FLD_PSIHB2PB_INJ_ERR_BITS_LEN = 10806; // 1
+const static uint64_t SH_FLD_PSIHB2PB_INJ_ONCE = 10807; // 1
+const static uint64_t SH_FLD_PSIHBC_RESET = 10808; // 1
+const static uint64_t SH_FLD_PSIRFACC_C_RXDATA_RDY_ERR = 10809; // 1
+const static uint64_t SH_FLD_PSIRFACC_RADDR_PCK = 10810; // 1
+const static uint64_t SH_FLD_PSIRFACC_RCTRL_PCK = 10811; // 1
+const static uint64_t SH_FLD_PSIRFACC_RDL_FSM_PCK = 10812; // 1
+const static uint64_t SH_FLD_PSIRFACC_RFSM_PCK = 10813; // 1
+const static uint64_t SH_FLD_PSIRFACC_RLINK_STATE_LT_02 = 10814; // 1
+const static uint64_t SH_FLD_PSIRFACC_RXSC_PCK = 10815; // 1
+const static uint64_t SH_FLD_PSIRFACC_TADDR_PCK = 10816; // 1
+const static uint64_t SH_FLD_PSIRFACC_TCTRL_PCK = 10817; // 1
+const static uint64_t SH_FLD_PSIRFACC_TDL_CMD_CTRL_PCK = 10818; // 1
+const static uint64_t SH_FLD_PSIRFACC_TDL_FSM_PCK = 10819; // 1
+const static uint64_t SH_FLD_PSIRFACC_TDL_RETRY_ERR = 10820; // 1
+const static uint64_t SH_FLD_PSIRFACC_TDL_RSP_CTRL_PCK = 10821; // 1
+const static uint64_t SH_FLD_PSIRFACC_TFSM_PCK = 10822; // 1
+const static uint64_t SH_FLD_PSIRFACC_TXSC_PCK = 10823; // 1
+const static uint64_t SH_FLD_PSIRXBFF_DATAO_PCK = 10824; // 1
+const static uint64_t SH_FLD_PSIRXBFF_DATA_PCK = 10825; // 1
+const static uint64_t SH_FLD_PSIRXBFF_RFC_PCK = 10826; // 1
+const static uint64_t SH_FLD_PSIRXEI_SHIFT_PCK = 10827; // 1
+const static uint64_t SH_FLD_PSIRXEI_TRANSMIT_PCK = 10828; // 1
+const static uint64_t SH_FLD_PSIRXINS_DATA_PCK = 10829; // 1
+const static uint64_t SH_FLD_PSIRXINS_OVERRUN = 10830; // 1
+const static uint64_t SH_FLD_PSIRXINS_RFGSHIFT_PCK = 10831; // 1
+const static uint64_t SH_FLD_PSIRXINS_RZRTMP_PCK = 10832; // 1
+const static uint64_t SH_FLD_PSIRXLC_CE_RF = 10833; // 1
+const static uint64_t SH_FLD_PSIRXLC_DATA_BUFF_PCK = 10834; // 1
+const static uint64_t SH_FLD_PSIRXLC_DATA_GXST1_PCK_2N = 10835; // 1
+const static uint64_t SH_FLD_PSIRXLC_DATA_PCK = 10836; // 1
+const static uint64_t SH_FLD_PSIRXLC_FSM_PCK = 10837; // 1
+const static uint64_t SH_FLD_PSIRXLC_RADDR_PCK = 10838; // 1
+const static uint64_t SH_FLD_PSIRXLC_RCTRL_PCK = 10839; // 1
+const static uint64_t SH_FLD_PSIRXLC_UE_RF = 10840; // 1
+const static uint64_t SH_FLD_PSITXBFF_DATA_PCK = 10841; // 1
+const static uint64_t SH_FLD_PSITXBFF_TDO_PCK = 10842; // 1
+const static uint64_t SH_FLD_PSITXBFF_TFC_PCK = 10843; // 1
+const static uint64_t SH_FLD_PSITXEI_SHIFT_PCK = 10844; // 1
+const static uint64_t SH_FLD_PSITXEI_TRANSMIT_PCK = 10845; // 1
+const static uint64_t SH_FLD_PSITXINS_DATA_PCK = 10846; // 1
+const static uint64_t SH_FLD_PSITXINS_PARITY = 10847; // 1
+const static uint64_t SH_FLD_PSITXINS_TZRTMP_PCK = 10848; // 1
+const static uint64_t SH_FLD_PSITXINS_UNDERRUN = 10849; // 1
+const static uint64_t SH_FLD_PSITXLC_CE_GX_2N = 10850; // 1
+const static uint64_t SH_FLD_PSITXLC_CE_RF = 10851; // 1
+const static uint64_t SH_FLD_PSITXLC_DATA_BUFF_PCK = 10852; // 1
+const static uint64_t SH_FLD_PSITXLC_DATA_GXST2_PCK_2N = 10853; // 1
+const static uint64_t SH_FLD_PSITXLC_DATA_GXST3_PCK_2N = 10854; // 1
+const static uint64_t SH_FLD_PSITXLC_FSM_PCK = 10855; // 1
+const static uint64_t SH_FLD_PSITXLC_TADDR_PCK = 10856; // 1
+const static uint64_t SH_FLD_PSITXLC_TCTRL_PCK = 10857; // 1
+const static uint64_t SH_FLD_PSITXLC_TDO_PCK = 10858; // 1
+const static uint64_t SH_FLD_PSITXLC_UE_GX_2N = 10859; // 1
+const static uint64_t SH_FLD_PSITXLC_UE_RF = 10860; // 1
+const static uint64_t SH_FLD_PSI_ALERT1 = 10861; // 1
+const static uint64_t SH_FLD_PSI_ALERT2 = 10862; // 1
+const static uint64_t SH_FLD_PSI_LINK_ENABLE = 10863; // 1
+const static uint64_t SH_FLD_PSI_LINK_INACTIVE_TRANS = 10864; // 1
+const static uint64_t SH_FLD_PSI_RESERVED0 = 10865; // 2
+const static uint64_t SH_FLD_PSI_RESERVED1 = 10866; // 2
+const static uint64_t SH_FLD_PSI_RESERVED2 = 10867; // 2
+const static uint64_t SH_FLD_PSI_RESERVED3 = 10868; // 2
+const static uint64_t SH_FLD_PSI_RESERVED4 = 10869; // 2
+const static uint64_t SH_FLD_PSI_UE = 10870; // 1
+const static uint64_t SH_FLD_PSI_XMIT_ERROR = 10871; // 1
+const static uint64_t SH_FLD_PSL_CMD_SUE = 10872; // 4
+const static uint64_t SH_FLD_PSL_CMD_UE = 10873; // 4
+const static uint64_t SH_FLD_PSL_CREDIT_TIMEOUT_ERR = 10874; // 2
+const static uint64_t SH_FLD_PSSBRIDGE_ONGOING = 10875; // 1
+const static uint64_t SH_FLD_PSS_HAM = 10876; // 3
+const static uint64_t SH_FLD_PSS_HAM_CORE_INTERRUPT_MASK = 10877; // 1
+const static uint64_t SH_FLD_PSTATE_A_THRESHOLD = 10878; // 24
+const static uint64_t SH_FLD_PSTATE_A_THRESHOLD_LEN = 10879; // 24
+const static uint64_t SH_FLD_PSTATE_B_THRESHOLD = 10880; // 24
+const static uint64_t SH_FLD_PSTATE_B_THRESHOLD_LEN = 10881; // 24
+const static uint64_t SH_FLD_PTCR = 10882; // 1
+const static uint64_t SH_FLD_PTCR_LEN = 10883; // 1
+const static uint64_t SH_FLD_PULL_EMPTY = 10884; // 4
+const static uint64_t SH_FLD_PULL_ENABLE = 10885; // 4
+const static uint64_t SH_FLD_PULL_FULL = 10886; // 4
+const static uint64_t SH_FLD_PULL_INTR_ACTION_0_1 = 10887; // 4
+const static uint64_t SH_FLD_PULL_INTR_ACTION_0_1_LEN = 10888; // 4
+const static uint64_t SH_FLD_PULL_LENGTH = 10889; // 4
+const static uint64_t SH_FLD_PULL_LENGTH_LEN = 10890; // 4
+const static uint64_t SH_FLD_PULL_READ_PTR = 10891; // 4
+const static uint64_t SH_FLD_PULL_READ_PTR_LEN = 10892; // 4
+const static uint64_t SH_FLD_PULL_READ_UNDERFLOW = 10893; // 4
+const static uint64_t SH_FLD_PULL_READ_UNDERFLOW_EN = 10894; // 4
+const static uint64_t SH_FLD_PULL_REGION = 10895; // 4
+const static uint64_t SH_FLD_PULL_REGION_LEN = 10896; // 4
+const static uint64_t SH_FLD_PULL_START = 10897; // 4
+const static uint64_t SH_FLD_PULL_START_LEN = 10898; // 4
+const static uint64_t SH_FLD_PULL_WRITE_OVERFLOW = 10899; // 4
+const static uint64_t SH_FLD_PULL_WRITE_PTR = 10900; // 4
+const static uint64_t SH_FLD_PULL_WRITE_PTR_LEN = 10901; // 4
+const static uint64_t SH_FLD_PULSE1_CNTR = 10902; // 1
+const static uint64_t SH_FLD_PULSE1_CNTR_LEN = 10903; // 1
+const static uint64_t SH_FLD_PULSE2_CNTR = 10904; // 1
+const static uint64_t SH_FLD_PULSE2_CNTR_LEN = 10905; // 1
+const static uint64_t SH_FLD_PULSE_DELAY = 10906; // 43
+const static uint64_t SH_FLD_PULSE_DELAY_LEN = 10907; // 43
+const static uint64_t SH_FLD_PUMP_MODE = 10908; // 1
+const static uint64_t SH_FLD_PUP_LITE_WAIT_SEL = 10909; // 4
+const static uint64_t SH_FLD_PUP_LITE_WAIT_SEL_LEN = 10910; // 4
+const static uint64_t SH_FLD_PUSH_EMPTY = 10911; // 6
+const static uint64_t SH_FLD_PUSH_ENABLE = 10912; // 6
+const static uint64_t SH_FLD_PUSH_FULL = 10913; // 6
+const static uint64_t SH_FLD_PUSH_INTR_ACTION_0_1 = 10914; // 6
+const static uint64_t SH_FLD_PUSH_INTR_ACTION_0_1_LEN = 10915; // 6
+const static uint64_t SH_FLD_PUSH_LENGTH = 10916; // 6
+const static uint64_t SH_FLD_PUSH_LENGTH_LEN = 10917; // 6
+const static uint64_t SH_FLD_PUSH_READ_PTR = 10918; // 6
+const static uint64_t SH_FLD_PUSH_READ_PTR_LEN = 10919; // 6
+const static uint64_t SH_FLD_PUSH_READ_UNDERFLOW = 10920; // 4
+const static uint64_t SH_FLD_PUSH_REGION = 10921; // 4
+const static uint64_t SH_FLD_PUSH_REGION_LEN = 10922; // 4
+const static uint64_t SH_FLD_PUSH_START = 10923; // 6
+const static uint64_t SH_FLD_PUSH_START_LEN = 10924; // 6
+const static uint64_t SH_FLD_PUSH_WRITE_OVERFLOW = 10925; // 4
+const static uint64_t SH_FLD_PUSH_WRITE_OVERFLOW_EN = 10926; // 4
+const static uint64_t SH_FLD_PUSH_WRITE_PTR = 10927; // 6
+const static uint64_t SH_FLD_PUSH_WRITE_PTR_LEN = 10928; // 6
+const static uint64_t SH_FLD_PU_BIT_ENABLES = 10929; // 1
+const static uint64_t SH_FLD_PU_BIT_ENABLES_LEN = 10930; // 1
+const static uint64_t SH_FLD_PU_COUNTS = 10931; // 8
+const static uint64_t SH_FLD_PU_COUNTS_LEN = 10932; // 8
+const static uint64_t SH_FLD_PVREF_ERROR_EN = 10933; // 1
+const static uint64_t SH_FLD_PVREF_ERROR_EN_LEN = 10934; // 1
+const static uint64_t SH_FLD_PVREF_ERROR_FINE = 10935; // 1
+const static uint64_t SH_FLD_PVREF_ERROR_GROSS = 10936; // 1
+const static uint64_t SH_FLD_PVREF_FAIL = 10937; // 12
+const static uint64_t SH_FLD_PVTN = 10938; // 16
+const static uint64_t SH_FLD_PVTNL_ENC = 10939; // 1
+const static uint64_t SH_FLD_PVTNL_ENC_LEN = 10940; // 1
+const static uint64_t SH_FLD_PVTN_LEN = 10941; // 16
+const static uint64_t SH_FLD_PVTP = 10942; // 16
+const static uint64_t SH_FLD_PVTPL_ENC = 10943; // 1
+const static uint64_t SH_FLD_PVTPL_ENC_LEN = 10944; // 1
+const static uint64_t SH_FLD_PVTP_LEN = 10945; // 16
+const static uint64_t SH_FLD_QPPM_ONGOING = 10946; // 24
+const static uint64_t SH_FLD_QPPM_RDATA = 10947; // 24
+const static uint64_t SH_FLD_QPPM_RDATA_LEN = 10948; // 24
+const static uint64_t SH_FLD_QPPM_REG = 10949; // 24
+const static uint64_t SH_FLD_QPPM_REG_LEN = 10950; // 24
+const static uint64_t SH_FLD_QPPM_RNW = 10951; // 24
+const static uint64_t SH_FLD_QPPM_STATUS = 10952; // 24
+const static uint64_t SH_FLD_QPPM_STATUS_LEN = 10953; // 24
+const static uint64_t SH_FLD_QPPM_WDATA = 10954; // 24
+const static uint64_t SH_FLD_QPPM_WDATA_LEN = 10955; // 24
+const static uint64_t SH_FLD_QUA = 10956; // 8
+const static uint64_t SH_FLD_QUAD_CHECKSTOP = 10957; // 12
+const static uint64_t SH_FLD_QUAD_CLK_SB_OVERRIDE = 10958; // 24
+const static uint64_t SH_FLD_QUAD_CLK_SW_OVERRIDE = 10959; // 24
+const static uint64_t SH_FLD_QUAD_SEL = 10960; // 6
+const static uint64_t SH_FLD_QUAD_SEL_LEN = 10961; // 6
+const static uint64_t SH_FLD_QUAD_STOPPED = 10962; // 1
+const static uint64_t SH_FLD_QUAD_STOPPED_LEN = 10963; // 1
+const static uint64_t SH_FLD_QUA_LEN = 10964; // 8
+const static uint64_t SH_FLD_QUA_V = 10965; // 8
+const static uint64_t SH_FLD_QUEUED_RD_EN = 10966; // 12
+const static uint64_t SH_FLD_QUEUED_WR_EN = 10967; // 12
+const static uint64_t SH_FLD_QUEUE_DISABLE = 10968; // 6
+const static uint64_t SH_FLD_QUEUE_NOT_EMPTY = 10969; // 6
+const static uint64_t SH_FLD_QUIESCED = 10970; // 1
+const static uint64_t SH_FLD_QUIESCE_ACHEIVED = 10971; // 1
+const static uint64_t SH_FLD_QUIESCE_FAILED = 10972; // 1
+const static uint64_t SH_FLD_QUIESCE_PB = 10973; // 1
+const static uint64_t SH_FLD_QUIESCE_REQUEST = 10974; // 1
+const static uint64_t SH_FLD_R0_COUNT = 10975; // 12
+const static uint64_t SH_FLD_R0_COUNT_LEN = 10976; // 12
+const static uint64_t SH_FLD_R15_BIT_MAP = 10977; // 8
+const static uint64_t SH_FLD_R15_BIT_MAP_LEN = 10978; // 8
+const static uint64_t SH_FLD_R16_BIT_MAP = 10979; // 8
+const static uint64_t SH_FLD_R16_BIT_MAP_LEN = 10980; // 8
+const static uint64_t SH_FLD_R17_BIT_MAP = 10981; // 8
+const static uint64_t SH_FLD_R17_BIT_MAP_LEN = 10982; // 8
+const static uint64_t SH_FLD_R1_COUNT = 10983; // 12
+const static uint64_t SH_FLD_R1_COUNT_LEN = 10984; // 12
+const static uint64_t SH_FLD_R2_COUNT = 10985; // 12
+const static uint64_t SH_FLD_R2_COUNT_LEN = 10986; // 12
+const static uint64_t SH_FLD_RAM_OVERRIDE = 10987; // 24
+const static uint64_t SH_FLD_RAND_ADDR_ALL_ADDR_MODE_EN = 10988; // 2
+const static uint64_t SH_FLD_RAND_EVENT = 10989; // 1
+const static uint64_t SH_FLD_RAND_EVENT_LEN = 10990; // 1
+const static uint64_t SH_FLD_RANGE = 10991; // 1
+const static uint64_t SH_FLD_RANGE_LEN = 10992; // 1
+const static uint64_t SH_FLD_RANK = 10993; // 8
+const static uint64_t SH_FLD_RANK_LEN = 10994; // 8
+const static uint64_t SH_FLD_RANK_OVERRIDE = 10995; // 8
+const static uint64_t SH_FLD_RANK_OVERRIDE_VALUE = 10996; // 8
+const static uint64_t SH_FLD_RANK_OVERRIDE_VALUE_LEN = 10997; // 8
+const static uint64_t SH_FLD_RANK_PAIR = 10998; // 8
+const static uint64_t SH_FLD_RANK_PAIR_LEN = 10999; // 8
+const static uint64_t SH_FLD_RANK_SM_1HOT = 11000; // 8
+const static uint64_t SH_FLD_RATE = 11001; // 14
+const static uint64_t SH_FLD_RATE_LEN = 11002; // 14
+const static uint64_t SH_FLD_RC = 11003; // 8
+const static uint64_t SH_FLD_RCDAT_RD_PARITY_ERR = 11004; // 12
+const static uint64_t SH_FLD_RCD_PARITY_ERROR = 11005; // 16
+const static uint64_t SH_FLD_RCE_COUNT = 11006; // 2
+const static uint64_t SH_FLD_RCE_COUNT_LEN = 11007; // 2
+const static uint64_t SH_FLD_RCE_ETE_ATTN = 11008; // 14
+const static uint64_t SH_FLD_RCMD0_ADDR_PARITY_ERROR = 11009; // 2
+const static uint64_t SH_FLD_RCMD0_ADDR_PERR = 11010; // 1
+const static uint64_t SH_FLD_RCMD0_TTAG_PERR = 11011; // 1
+const static uint64_t SH_FLD_RCMD1_ADDR_PARITY_ERROR = 11012; // 2
+const static uint64_t SH_FLD_RCMD1_ADDR_PERR = 11013; // 1
+const static uint64_t SH_FLD_RCMD1_TTAG_PERR = 11014; // 1
+const static uint64_t SH_FLD_RCMD2_ADDR_PARITY_ERROR = 11015; // 2
+const static uint64_t SH_FLD_RCMD2_ADDR_PERR = 11016; // 1
+const static uint64_t SH_FLD_RCMD2_TTAG_PERR = 11017; // 1
+const static uint64_t SH_FLD_RCMD3_ADDR_PARITY_ERROR = 11018; // 2
+const static uint64_t SH_FLD_RCMD3_ADDR_PERR = 11019; // 1
+const static uint64_t SH_FLD_RCMD3_TTAG_PERR = 11020; // 1
+const static uint64_t SH_FLD_RCMD_ADDR_P_ERR = 11021; // 12
+const static uint64_t SH_FLD_RCMD_ADDR_P_ERR_LEN = 11022; // 12
+const static uint64_t SH_FLD_RCMD_TTAG_P_ERR = 11023; // 12
+const static uint64_t SH_FLD_RCMD_TTAG_P_ERR_LEN = 11024; // 12
+const static uint64_t SH_FLD_RCV_BRDCST_GROUP = 11025; // 1
+const static uint64_t SH_FLD_RCV_BRDCST_GROUP_LEN = 11026; // 1
+const static uint64_t SH_FLD_RCV_CAPTURE = 11027; // 1
+const static uint64_t SH_FLD_RCV_CAPTURE_LEN = 11028; // 1
+const static uint64_t SH_FLD_RCV_CHIPID = 11029; // 1
+const static uint64_t SH_FLD_RCV_CHIPID_LEN = 11030; // 1
+const static uint64_t SH_FLD_RCV_DATATO_DIV = 11031; // 1
+const static uint64_t SH_FLD_RCV_DATATO_DIV_LEN = 11032; // 1
+const static uint64_t SH_FLD_RCV_ERROR = 11033; // 1
+const static uint64_t SH_FLD_RCV_GROUPID = 11034; // 1
+const static uint64_t SH_FLD_RCV_GROUPID_LEN = 11035; // 1
+const static uint64_t SH_FLD_RCV_IN_PROGRESS = 11036; // 1
+const static uint64_t SH_FLD_RCV_PB_OP_HANG_ERR = 11037; // 1
+const static uint64_t SH_FLD_RCV_RESERVATION_SET = 11038; // 1
+const static uint64_t SH_FLD_RCV_RESET = 11039; // 1
+const static uint64_t SH_FLD_RCV_TOD_STATE = 11040; // 1
+const static uint64_t SH_FLD_RCV_TOD_STATE_LEN = 11041; // 1
+const static uint64_t SH_FLD_RCV_TTAG_PARITY_ERR = 11042; // 1
+const static uint64_t SH_FLD_RCV_WRITE_IN_PROGRESS = 11043; // 1
+const static uint64_t SH_FLD_RC_ADDR_PAR = 11044; // 1
+const static uint64_t SH_FLD_RC_ENABLE_BER_TEST = 11045; // 6
+const static uint64_t SH_FLD_RC_ENABLE_CM_COARSE_CAL = 11046; // 6
+const static uint64_t SH_FLD_RC_ENABLE_CM_FINE_CAL = 11047; // 4
+const static uint64_t SH_FLD_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 11048; // 6
+const static uint64_t SH_FLD_RC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 11049; // 6
+const static uint64_t SH_FLD_RC_ENABLE_CTLE_COARSE_CAL = 11050; // 6
+const static uint64_t SH_FLD_RC_ENABLE_CTLE_EDGE_OFFSET_CAL = 11051; // 2
+const static uint64_t SH_FLD_RC_ENABLE_CTLE_EDGE_TRACK_ONLY = 11052; // 4
+const static uint64_t SH_FLD_RC_ENABLE_DAC_H1_CAL = 11053; // 6
+const static uint64_t SH_FLD_RC_ENABLE_DAC_H1_TO_A_CAL = 11054; // 4
+const static uint64_t SH_FLD_RC_ENABLE_DDC = 11055; // 6
+const static uint64_t SH_FLD_RC_ENABLE_DFE_H1_CAL = 11056; // 6
+const static uint64_t SH_FLD_RC_ENABLE_DFE_H2_H12_CAL = 11057; // 4
+const static uint64_t SH_FLD_RC_ENABLE_DFE_H2_H12_SUBSTEP = 11058; // 4
+const static uint64_t SH_FLD_RC_ENABLE_DFE_H2_H12_SUBSTEP_LEN = 11059; // 4
+const static uint64_t SH_FLD_RC_ENABLE_DFE_VOLTAGE_MODE = 11060; // 4
+const static uint64_t SH_FLD_RC_ENABLE_H1AP_TWEAK = 11061; // 6
+const static uint64_t SH_FLD_RC_ENABLE_INTEG_LATCH_OFFSET_CAL = 11062; // 6
+const static uint64_t SH_FLD_RC_ENABLE_RESULT_CHECK = 11063; // 6
+const static uint64_t SH_FLD_RC_ENABLE_VGA_CAL = 11064; // 6
+const static uint64_t SH_FLD_RC_ENABLE_VGA_EDGE_OFFSET_CAL = 11065; // 2
+const static uint64_t SH_FLD_RC_LOAD_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV =
+    11066; // 12
+const static uint64_t SH_FLD_RC_LOAD_RECIVED_PB_CRESP_ADR_ERR = 11067; // 12
+const static uint64_t SH_FLD_RC_LOAD_RECIVED_PB_CRESP_ADR_ERR_FOR_HYP =
+    11068; // 12
+const static uint64_t SH_FLD_RC_MASK = 11069; // 8
+const static uint64_t SH_FLD_RC_POWBUS_DATA_CE_ERR_FROM_F2CHK = 11070; // 12
+const static uint64_t SH_FLD_RC_POWBUS_DATA_SUE_ERR_FROM_F2CHK = 11071; // 12
+const static uint64_t SH_FLD_RC_POWBUS_DATA_UE_ERR_FROM_F2CHK = 11072; // 12
+const static uint64_t SH_FLD_RC_POWERBUS_DATA_TIMEOUT = 11073; // 12
+const static uint64_t SH_FLD_RC_SLOWDOWN_TIMEOUT_SEL = 11074; // 6
+const static uint64_t SH_FLD_RC_SLOWDOWN_TIMEOUT_SEL_LEN = 11075; // 6
+const static uint64_t SH_FLD_RC_STORE_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV =
+    11076; // 12
+const static uint64_t SH_FLD_RC_STORE_RECIVED_PB_CRESP_ADR_ERR = 11077; // 12
+const static uint64_t SH_FLD_RC_TTAG_PAR = 11078; // 1
+const static uint64_t SH_FLD_RDADDR_ARB_BAD_HAND = 11079; // 2
+const static uint64_t SH_FLD_RDATA = 11080; // 1
+const static uint64_t SH_FLD_RDATA_LEN = 11081; // 1
+const static uint64_t SH_FLD_RDBUFF_ALLOC = 11082; // 2
+const static uint64_t SH_FLD_RDBUFF_ALLOC_LEN = 11083; // 2
+const static uint64_t SH_FLD_RDCLK_ALIGN = 11084; // 8
+const static uint64_t SH_FLD_RDCMP = 11085; // 2
+const static uint64_t SH_FLD_RDCMP_LEN = 11086; // 2
+const static uint64_t SH_FLD_RDIV = 11087; // 14
+const static uint64_t SH_FLD_RDIV_LEN = 11088; // 10
+const static uint64_t SH_FLD_RDQ_FSM_PERR = 11089; // 1
+const static uint64_t SH_FLD_RDQ_OVERFLOW = 11090; // 1
+const static uint64_t SH_FLD_RDWR_ACCESS_EN = 11091; // 2
+const static uint64_t SH_FLD_RDWR_ADDR = 11092; // 2
+const static uint64_t SH_FLD_RDWR_ADDR_LEN = 11093; // 2
+const static uint64_t SH_FLD_RDWR_OP_BUSY = 11094; // 1
+const static uint64_t SH_FLD_RDWR_RDWR_DATA = 11095; // 2
+const static uint64_t SH_FLD_RDWR_RDWR_DATA_LEN = 11096; // 2
+const static uint64_t SH_FLD_RDWR_READ_STATUS = 11097; // 2
+const static uint64_t SH_FLD_RDWR_REQ_PEND = 11098; // 2
+const static uint64_t SH_FLD_RDWR_UPDATE_ERROR = 11099; // 2
+const static uint64_t SH_FLD_RDWR_WRITE_MODE = 11100; // 2
+const static uint64_t SH_FLD_RDWR_WRITE_STATUS = 11101; // 2
+const static uint64_t SH_FLD_RDWR_WR_ENABLE = 11102; // 2
+const static uint64_t SH_FLD_RD_ADDR_0_7 = 11103; // 1
+const static uint64_t SH_FLD_RD_ADDR_0_7_LEN = 11104; // 1
+const static uint64_t SH_FLD_RD_ARE_ERRORS = 11105; // 9
+const static uint64_t SH_FLD_RD_ARE_ERRORS_MASK = 11106; // 9
+const static uint64_t SH_FLD_RD_CNTL = 11107; // 8
+const static uint64_t SH_FLD_RD_CNTL_MASK = 11108; // 8
+const static uint64_t SH_FLD_RD_DATA_COUNT = 11109; // 1
+const static uint64_t SH_FLD_RD_DATA_COUNT_LEN = 11110; // 1
+const static uint64_t SH_FLD_RD_DATA_PARITY_ERROR = 11111; // 3
+const static uint64_t SH_FLD_RD_GO_M_QOS = 11112; // 2
+const static uint64_t SH_FLD_RD_MACHINE_HANG_ERR = 11113; // 12
+const static uint64_t SH_FLD_RD_RST_INTRPT_FACES = 11114; // 1
+const static uint64_t SH_FLD_RD_RST_INTRPT_PIB = 11115; // 1
+const static uint64_t SH_FLD_RD_SCOPE = 11116; // 24
+const static uint64_t SH_FLD_RD_SCOPE_LEN = 11117; // 24
+const static uint64_t SH_FLD_RD_SLVNUM = 11118; // 6
+const static uint64_t SH_FLD_RD_SLVNUM_LEN = 11119; // 6
+const static uint64_t SH_FLD_READ_BUFFER_OVERFLOW_ERROR = 11120; // 8
+const static uint64_t SH_FLD_READ_COMPARE_REQUIRED = 11121; // 64
+const static uint64_t SH_FLD_READ_CONTINUE_0 = 11122; // 1
+const static uint64_t SH_FLD_READ_CONTINUE_1 = 11123; // 1
+const static uint64_t SH_FLD_READ_CONTINUE_2 = 11124; // 1
+const static uint64_t SH_FLD_READ_CONTINUE_3 = 11125; // 1
+const static uint64_t SH_FLD_READ_COUNT = 11126; // 8
+const static uint64_t SH_FLD_READ_COUNT_LEN = 11127; // 8
+const static uint64_t SH_FLD_READ_CRD_POOL = 11128; // 1
+const static uint64_t SH_FLD_READ_CRD_POOL_LEN = 11129; // 1
+const static uint64_t SH_FLD_READ_CTR = 11130; // 8
+const static uint64_t SH_FLD_READ_ENABLE = 11131; // 129
+const static uint64_t SH_FLD_READ_EPSILON_MODE = 11132; // 2
+const static uint64_t SH_FLD_READ_EPSILON_TIER0 = 11133; // 2
+const static uint64_t SH_FLD_READ_EPSILON_TIER0_LEN = 11134; // 2
+const static uint64_t SH_FLD_READ_EPSILON_TIER1 = 11135; // 2
+const static uint64_t SH_FLD_READ_EPSILON_TIER1_LEN = 11136; // 2
+const static uint64_t SH_FLD_READ_EPSILON_TIER2 = 11137; // 2
+const static uint64_t SH_FLD_READ_EPSILON_TIER2_LEN = 11138; // 2
+const static uint64_t SH_FLD_READ_INVALID_FACES = 11139; // 1
+const static uint64_t SH_FLD_READ_INVALID_PIB = 11140; // 1
+const static uint64_t SH_FLD_READ_LATENCY_OFFSET = 11141; // 8
+const static uint64_t SH_FLD_READ_LATENCY_OFFSET_LEN = 11142; // 8
+const static uint64_t SH_FLD_READ_NOT_WRITE_0 = 11143; // 1
+const static uint64_t SH_FLD_READ_NOT_WRITE_1 = 11144; // 1
+const static uint64_t SH_FLD_READ_NOT_WRITE_2 = 11145; // 1
+const static uint64_t SH_FLD_READ_NOT_WRITE_3 = 11146; // 1
+const static uint64_t SH_FLD_READ_NVLD = 11147; // 1
+const static uint64_t SH_FLD_READ_OR_WRITE_DATA = 11148; // 64
+const static uint64_t SH_FLD_READ_OR_WRITE_DATA_LEN = 11149; // 64
+const static uint64_t SH_FLD_READ_PREFETCH_CTL = 11150; // 4
+const static uint64_t SH_FLD_READ_PREFETCH_CTL_LEN = 11151; // 4
+const static uint64_t SH_FLD_READ_RAMP_PERF_TRESHOLD = 11152; // 4
+const static uint64_t SH_FLD_READ_RAMP_PERF_TRESHOLD_LEN = 11153; // 4
+const static uint64_t SH_FLD_READ_RESPONSE_DELAY_ENABLE = 11154; // 2
+const static uint64_t SH_FLD_READ_RST_INTERRUPT_FACES = 11155; // 1
+const static uint64_t SH_FLD_READ_RST_INTERRUPT_PIB = 11156; // 1
+const static uint64_t SH_FLD_READ_SPECULATION_DISABLE_THRESHOLD = 11157; // 4
+const static uint64_t SH_FLD_READ_SPECULATION_DISABLE_THRESHOLD_LEN =
+    11158; // 4
+const static uint64_t SH_FLD_READ_TTYPE = 11159; // 4
+const static uint64_t SH_FLD_RECAL_ABORT_DL_MASK = 11160; // 2
+const static uint64_t SH_FLD_RECAL_ABORT_VEC_0_15 = 11161; // 2
+const static uint64_t SH_FLD_RECAL_ABORT_VEC_0_15_LEN = 11162; // 2
+const static uint64_t SH_FLD_RECAL_ABORT_VEC_16_23 = 11163; // 2
+const static uint64_t SH_FLD_RECAL_ABORT_VEC_16_23_LEN = 11164; // 2
+const static uint64_t SH_FLD_RECAL_ERROR = 11165; // 8
+const static uint64_t SH_FLD_RECAL_MAX_SPARES_EXCEEDED = 11166; // 8
+const static uint64_t SH_FLD_RECAL_SPARE_DEPLOYED = 11167; // 8
+const static uint64_t SH_FLD_RECEIVED = 11168; // 1
+const static uint64_t SH_FLD_RECEIVED_ERROR = 11169; // 1
+const static uint64_t SH_FLD_RECEIVER_MODE = 11170; // 3
+const static uint64_t SH_FLD_RECEIVER_MODE_LEN = 11171; // 3
+const static uint64_t SH_FLD_RECEIVE_ACKNOWLEDGE_REGISTER = 11172; // 1
+const static uint64_t SH_FLD_RECEIVE_ACKNOWLEDGE_REGISTER_LEN = 11173; // 1
+const static uint64_t SH_FLD_RECOVERABLE_ERROR = 11174; // 2
+const static uint64_t SH_FLD_RECOVERY_FAILED = 11175; // 6
+const static uint64_t SH_FLD_RECOVERY_HANG_DETECTED = 11176; // 2
+const static uint64_t SH_FLD_REC_PB_SM_ERROR_ERR = 11177; // 2
+const static uint64_t SH_FLD_REC_SM_ERROR_ERR = 11178; // 2
+const static uint64_t SH_FLD_REC_UPDATE_ERROR = 11179; // 2
+const static uint64_t SH_FLD_REDIS_PRIORITY = 11180; // 1
+const static uint64_t SH_FLD_REDIS_PRIORITY_LEN = 11181; // 1
+const static uint64_t SH_FLD_REDIS_RSD = 11182; // 1
+const static uint64_t SH_FLD_REDIS_RSD_LEN = 11183; // 1
+const static uint64_t SH_FLD_REFCLKSEL = 11184; // 4
+const static uint64_t SH_FLD_REFCLK_0_TERM_DIS_DC = 11185; // 1
+const static uint64_t SH_FLD_REFCLK_1_TERM_DIS_DC = 11186; // 1
+const static uint64_t SH_FLD_REFISINK = 11187; // 3
+const static uint64_t SH_FLD_REFISINK_LEN = 11188; // 3
+const static uint64_t SH_FLD_REFISRC = 11189; // 3
+const static uint64_t SH_FLD_REFISRC_LEN = 11190; // 3
+const static uint64_t SH_FLD_REFRESH_ALL_RANKS = 11191; // 8
+const static uint64_t SH_FLD_REFRESH_BLOCK_CONFIG = 11192; // 8
+const static uint64_t SH_FLD_REFRESH_BLOCK_CONFIG_LEN = 11193; // 8
+const static uint64_t SH_FLD_REFRESH_CONTROL = 11194; // 8
+const static uint64_t SH_FLD_REFRESH_CONTROL_LEN = 11195; // 8
+const static uint64_t SH_FLD_REFRESH_COUNT = 11196; // 8
+const static uint64_t SH_FLD_REFRESH_COUNT_LEN = 11197; // 8
+const static uint64_t SH_FLD_REFRESH_INTERVAL = 11198; // 8
+const static uint64_t SH_FLD_REFRESH_INTERVAL_LEN = 11199; // 8
+const static uint64_t SH_FLD_REFRESH_ONLY_SUBTEST_EN = 11200; // 2
+const static uint64_t SH_FLD_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL = 11201; // 2
+const static uint64_t SH_FLD_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL_LEN = 11202; // 2
+const static uint64_t SH_FLD_REFRESH_OVERRUN = 11203; // 16
+const static uint64_t SH_FLD_REFVREG = 11204; // 3
+const static uint64_t SH_FLD_REFVREG_LEN = 11205; // 3
+const static uint64_t SH_FLD_REG = 11206; // 19
+const static uint64_t SH_FLD_REGF = 11207; // 43
+const static uint64_t SH_FLD_REGION = 11208; // 72
+const static uint64_t SH_FLD_REGION_LEN = 11209; // 72
+const static uint64_t SH_FLD_REGISTER = 11210; // 3
+const static uint64_t SH_FLD_REGISTER_ARRAY_PE = 11211; // 9
+const static uint64_t SH_FLD_REGISTER_ARRAY_PE_MASK = 11212; // 9
+const static uint64_t SH_FLD_REGISTER_LEN = 11213; // 3
+const static uint64_t SH_FLD_REGISTER_PE = 11214; // 4
+const static uint64_t SH_FLD_REGISTER_VALID = 11215; // 4
+const static uint64_t SH_FLD_REGS = 11216; // 1
+const static uint64_t SH_FLD_REGSEL = 11217; // 3
+const static uint64_t SH_FLD_REGSEL_LEN = 11218; // 3
+const static uint64_t SH_FLD_REGS_LEN = 11219; // 1
+const static uint64_t SH_FLD_REGULAR_WKUP_ACTIVE = 11220; // 30
+const static uint64_t SH_FLD_REGULAR_WKUP_PRESENT = 11221; // 30
+const static uint64_t SH_FLD_REGULAR_WKUP_REQUESTED = 11222; // 30
+const static uint64_t SH_FLD_REG_ADDR_LEN = 11223; // 1
+const static uint64_t SH_FLD_REG_ADDR_LEN_0 = 11224; // 1
+const static uint64_t SH_FLD_REG_ADDR_LEN_0_LEN = 11225; // 1
+const static uint64_t SH_FLD_REG_ADDR_LEN_1 = 11226; // 1
+const static uint64_t SH_FLD_REG_ADDR_LEN_1_LEN = 11227; // 1
+const static uint64_t SH_FLD_REG_ADDR_LEN_2 = 11228; // 1
+const static uint64_t SH_FLD_REG_ADDR_LEN_2_LEN = 11229; // 1
+const static uint64_t SH_FLD_REG_ADDR_LEN_3 = 11230; // 1
+const static uint64_t SH_FLD_REG_ADDR_LEN_3_LEN = 11231; // 1
+const static uint64_t SH_FLD_REG_ADDR_LEN_LEN = 11232; // 1
+const static uint64_t SH_FLD_REG_ENABLE = 11233; // 1
+const static uint64_t SH_FLD_REG_FIFO_SIZE_EQ_1 = 11234; // 1
+const static uint64_t SH_FLD_REG_LEN = 11235; // 19
+const static uint64_t SH_FLD_REG_UNUSED = 11236; // 1
+const static uint64_t SH_FLD_REG_UNUSED_LEN = 11237; // 1
+const static uint64_t SH_FLD_REG_WAKEUP_C0 = 11238; // 24
+const static uint64_t SH_FLD_REG_WAKEUP_C1 = 11239; // 24
+const static uint64_t SH_FLD_REG_WKUP_OVERRIDE = 11240; // 30
+const static uint64_t SH_FLD_REINIT_CREDITS = 11241; // 1
+const static uint64_t SH_FLD_REJECTED_PASTE_CMD = 11242; // 2
+const static uint64_t SH_FLD_REL_ASYNC_PARITY_ERROR = 11243; // 8
+const static uint64_t SH_FLD_REL_ASYNC_SEQUENCE_ERROR = 11244; // 8
+const static uint64_t SH_FLD_REL_MERGE_ASYNC_PARITY_ERROR = 11245; // 8
+const static uint64_t SH_FLD_REL_MERGE_ASYNC_SEQUENCE_ERROR = 11246; // 8
+const static uint64_t SH_FLD_REMAINING_WORDS = 11247; // 1
+const static uint64_t SH_FLD_REMAINING_WORDS_LEN = 11248; // 1
+const static uint64_t SH_FLD_REMAP_DEST = 11249; // 1
+const static uint64_t SH_FLD_REMAP_DEST_LEN = 11250; // 1
+const static uint64_t SH_FLD_REMAP_SOURCE = 11251; // 1
+const static uint64_t SH_FLD_REMAP_SOURCE_LEN = 11252; // 1
+const static uint64_t SH_FLD_REMOTE_NODAL_EPSILON = 11253; // 8
+const static uint64_t SH_FLD_REMOTE_NODAL_EPSILON_LEN = 11254; // 8
+const static uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION = 11255; // 1
+const static uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR =
+    11256; // 1
+const static uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR_LEN =
+    11257; // 1
+const static uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_LEN = 11258; // 1
+const static uint64_t SH_FLD_REMOTE_SYNC_CHECK_M_CPS_DISABLE = 11259; // 1
+const static uint64_t SH_FLD_REMOTE_SYNC_DISABLE = 11260; // 1
+const static uint64_t SH_FLD_REMOTE_SYNC_ERROR_DISABLE = 11261; // 1
+const static uint64_t SH_FLD_REMOTE_SYNC_MISS_COUNT_MAX = 11262; // 1
+const static uint64_t SH_FLD_REMOTE_SYNC_MISS_COUNT_MAX_LEN = 11263; // 1
+const static uint64_t SH_FLD_REPAIR_DONE = 11264; // 4
+const static uint64_t SH_FLD_REPAIR_FAILED = 11265; // 4
+const static uint64_t SH_FLD_REPEAT_CMD_CNT = 11266; // 64
+const static uint64_t SH_FLD_REPEAT_CMD_CNT_LEN = 11267; // 64
+const static uint64_t SH_FLD_REPR = 11268; // 43
+const static uint64_t SH_FLD_REPTEST_ENABLE = 11269; // 1
+const static uint64_t SH_FLD_REPTEST_MATCH_TH = 11270; // 1
+const static uint64_t SH_FLD_REPTEST_MATCH_TH_LEN = 11271; // 1
+const static uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG0 = 11272; // 1
+const static uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG0_LEN = 11273; // 1
+const static uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG1 = 11274; // 1
+const static uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG1_LEN = 11275; // 1
+const static uint64_t SH_FLD_REPTEST_SOFT_FAIL_TH = 11276; // 1
+const static uint64_t SH_FLD_REPTEST_SOFT_FAIL_TH_LEN = 11277; // 1
+const static uint64_t SH_FLD_REQ = 11278; // 43
+const static uint64_t SH_FLD_REQUEST = 11279; // 1
+const static uint64_t SH_FLD_REQUEST_LEN = 11280; // 1
+const static uint64_t SH_FLD_REQ_INTR_PAYLOAD = 11281; // 30
+const static uint64_t SH_FLD_REQ_INTR_PAYLOAD_LEN = 11282; // 30
+const static uint64_t SH_FLD_REQ_INTR_TYPE = 11283; // 30
+const static uint64_t SH_FLD_REQ_INTR_TYPE_LEN = 11284; // 30
+const static uint64_t SH_FLD_REQ_RESET_FR_SBE = 11285; // 1
+const static uint64_t SH_FLD_REQ_RESET_FR_SP = 11286; // 1
+const static uint64_t SH_FLD_REQ_STOP_LEVEL = 11287; // 30
+const static uint64_t SH_FLD_REQ_STOP_LEVEL_FSP = 11288; // 30
+const static uint64_t SH_FLD_REQ_STOP_LEVEL_FSP_LEN = 11289; // 30
+const static uint64_t SH_FLD_REQ_STOP_LEVEL_HYP = 11290; // 30
+const static uint64_t SH_FLD_REQ_STOP_LEVEL_HYP_LEN = 11291; // 30
+const static uint64_t SH_FLD_REQ_STOP_LEVEL_LEN = 11292; // 30
+const static uint64_t SH_FLD_REQ_STOP_LEVEL_OCC = 11293; // 30
+const static uint64_t SH_FLD_REQ_STOP_LEVEL_OCC_LEN = 11294; // 30
+const static uint64_t SH_FLD_REQ_STOP_LEVEL_OTR = 11295; // 30
+const static uint64_t SH_FLD_REQ_STOP_LEVEL_OTR_LEN = 11296; // 30
+const static uint64_t SH_FLD_RESCLK_DIS = 11297; // 43
+const static uint64_t SH_FLD_RESEND_COUNTER = 11298; // 1
+const static uint64_t SH_FLD_RESEND_COUNTER_LEN = 11299; // 1
+const static uint64_t SH_FLD_RESERVATION_EN = 11300; // 1
+const static uint64_t SH_FLD_RESERVED = 11301; // 102
+const static uint64_t SH_FLD_RESERVED1 = 11302; // 194
+const static uint64_t SH_FLD_RESERVED12 = 11303; // 4
+const static uint64_t SH_FLD_RESERVED13 = 11304; // 4
+const static uint64_t SH_FLD_RESERVED17 = 11305; // 4
+const static uint64_t SH_FLD_RESERVED18 = 11306; // 4
+const static uint64_t SH_FLD_RESERVED19 = 11307; // 4
+const static uint64_t SH_FLD_RESERVED19_23 = 11308; // 4
+const static uint64_t SH_FLD_RESERVED19_23_LEN = 11309; // 4
+const static uint64_t SH_FLD_RESERVED1_2 = 11310; // 4
+const static uint64_t SH_FLD_RESERVED1_2_LEN = 11311; // 4
+const static uint64_t SH_FLD_RESERVED1_LEN = 11312; // 110
+const static uint64_t SH_FLD_RESERVED2 = 11313; // 60
+const static uint64_t SH_FLD_RESERVED20 = 11314; // 4
+const static uint64_t SH_FLD_RESERVED21 = 11315; // 4
+const static uint64_t SH_FLD_RESERVED22 = 11316; // 4
+const static uint64_t SH_FLD_RESERVED23 = 11317; // 4
+const static uint64_t SH_FLD_RESERVED25 = 11318; // 4
+const static uint64_t SH_FLD_RESERVED26 = 11319; // 12
+const static uint64_t SH_FLD_RESERVED2_LEN = 11320; // 6
+const static uint64_t SH_FLD_RESERVED3 = 11321; // 18
+const static uint64_t SH_FLD_RESERVED3_LEN = 11322; // 12
+const static uint64_t SH_FLD_RESERVED4 = 11323; // 6
+const static uint64_t SH_FLD_RESERVED46_48 = 11324; // 4
+const static uint64_t SH_FLD_RESERVED46_48_LEN = 11325; // 4
+const static uint64_t SH_FLD_RESERVED4_LEN = 11326; // 6
+const static uint64_t SH_FLD_RESERVED515 = 11327; // 4
+const static uint64_t SH_FLD_RESERVED515_LEN = 11328; // 4
+const static uint64_t SH_FLD_RESERVED6 = 11329; // 1
+const static uint64_t SH_FLD_RESERVED61_63 = 11330; // 4
+const static uint64_t SH_FLD_RESERVED61_63_LEN = 11331; // 4
+const static uint64_t SH_FLD_RESERVED_0 = 11332; // 6
+const static uint64_t SH_FLD_RESERVED_00 = 11333; // 1
+const static uint64_t SH_FLD_RESERVED_02 = 11334; // 1
+const static uint64_t SH_FLD_RESERVED_03 = 11335; // 1
+const static uint64_t SH_FLD_RESERVED_0_1 = 11336; // 20
+const static uint64_t SH_FLD_RESERVED_0_11 = 11337; // 6
+const static uint64_t SH_FLD_RESERVED_0_11_LEN = 11338; // 6
+const static uint64_t SH_FLD_RESERVED_0_17 = 11339; // 2
+const static uint64_t SH_FLD_RESERVED_0_17_LEN = 11340; // 2
+const static uint64_t SH_FLD_RESERVED_0_1_LEN = 11341; // 20
+const static uint64_t SH_FLD_RESERVED_0_20 = 11342; // 5
+const static uint64_t SH_FLD_RESERVED_0_20_LEN = 11343; // 5
+const static uint64_t SH_FLD_RESERVED_0_3 = 11344; // 1
+const static uint64_t SH_FLD_RESERVED_0_31 = 11345; // 2
+const static uint64_t SH_FLD_RESERVED_0_31_LEN = 11346; // 2
+const static uint64_t SH_FLD_RESERVED_0_32 = 11347; // 1
+const static uint64_t SH_FLD_RESERVED_0_32_LEN = 11348; // 1
+const static uint64_t SH_FLD_RESERVED_0_3_LEN = 11349; // 1
+const static uint64_t SH_FLD_RESERVED_0_7 = 11350; // 24
+const static uint64_t SH_FLD_RESERVED_0_7_LEN = 11351; // 24
+const static uint64_t SH_FLD_RESERVED_1 = 11352; // 12
+const static uint64_t SH_FLD_RESERVED_10 = 11353; // 2
+const static uint64_t SH_FLD_RESERVED_10_11 = 11354; // 30
+const static uint64_t SH_FLD_RESERVED_10_11_LEN = 11355; // 30
+const static uint64_t SH_FLD_RESERVED_10_LEN = 11356; // 1
+const static uint64_t SH_FLD_RESERVED_11 = 11357; // 18
+const static uint64_t SH_FLD_RESERVED_11A = 11358; // 43
+const static uint64_t SH_FLD_RESERVED_11_12 = 11359; // 4
+const static uint64_t SH_FLD_RESERVED_11_12_LEN = 11360; // 4
+const static uint64_t SH_FLD_RESERVED_11_14 = 11361; // 34
+const static uint64_t SH_FLD_RESERVED_11_14_LEN = 11362; // 34
+const static uint64_t SH_FLD_RESERVED_11_23 = 11363; // 2
+const static uint64_t SH_FLD_RESERVED_11_23_LEN = 11364; // 2
+const static uint64_t SH_FLD_RESERVED_11_LEN = 11365; // 1
+const static uint64_t SH_FLD_RESERVED_12 = 11366; // 17
+const static uint64_t SH_FLD_RESERVED_12_13 = 11367; // 8
+const static uint64_t SH_FLD_RESERVED_12_13_LEN = 11368; // 8
+const static uint64_t SH_FLD_RESERVED_12_15 = 11369; // 1
+const static uint64_t SH_FLD_RESERVED_12_15_LEN = 11370; // 1
+const static uint64_t SH_FLD_RESERVED_12_23 = 11371; // 1
+const static uint64_t SH_FLD_RESERVED_12_23_LEN = 11372; // 1
+const static uint64_t SH_FLD_RESERVED_12_31 = 11373; // 2
+const static uint64_t SH_FLD_RESERVED_12_31_LEN = 11374; // 2
+const static uint64_t SH_FLD_RESERVED_13 = 11375; // 17
+const static uint64_t SH_FLD_RESERVED_13_49 = 11376; // 2
+const static uint64_t SH_FLD_RESERVED_13_49_LEN = 11377; // 2
+const static uint64_t SH_FLD_RESERVED_13_LEN = 11378; // 1
+const static uint64_t SH_FLD_RESERVED_14 = 11379; // 1
+const static uint64_t SH_FLD_RESERVED_14C = 11380; // 43
+const static uint64_t SH_FLD_RESERVED_14_LEN = 11381; // 1
+const static uint64_t SH_FLD_RESERVED_15 = 11382; // 12
+const static uint64_t SH_FLD_RESERVED_15C = 11383; // 43
+const static uint64_t SH_FLD_RESERVED_15_24 = 11384; // 2
+const static uint64_t SH_FLD_RESERVED_15_24_LEN = 11385; // 2
+const static uint64_t SH_FLD_RESERVED_16 = 11386; // 13
+const static uint64_t SH_FLD_RESERVED_16_17 = 11387; // 12
+const static uint64_t SH_FLD_RESERVED_16_17_LEN = 11388; // 12
+const static uint64_t SH_FLD_RESERVED_16_18 = 11389; // 30
+const static uint64_t SH_FLD_RESERVED_16_18_LEN = 11390; // 30
+const static uint64_t SH_FLD_RESERVED_16_26 = 11391; // 2
+const static uint64_t SH_FLD_RESERVED_16_26_LEN = 11392; // 2
+const static uint64_t SH_FLD_RESERVED_16_LEN = 11393; // 1
+const static uint64_t SH_FLD_RESERVED_17 = 11394; // 11
+const static uint64_t SH_FLD_RESERVED_17_19 = 11395; // 6
+const static uint64_t SH_FLD_RESERVED_17_19_LEN = 11396; // 6
+const static uint64_t SH_FLD_RESERVED_17_20 = 11397; // 6
+const static uint64_t SH_FLD_RESERVED_17_20_LEN = 11398; // 6
+const static uint64_t SH_FLD_RESERVED_17_63 = 11399; // 2
+const static uint64_t SH_FLD_RESERVED_17_63_LEN = 11400; // 2
+const static uint64_t SH_FLD_RESERVED_17_LEN = 11401; // 1
+const static uint64_t SH_FLD_RESERVED_18A = 11402; // 43
+const static uint64_t SH_FLD_RESERVED_18_23 = 11403; // 10
+const static uint64_t SH_FLD_RESERVED_18_23_LEN = 11404; // 10
+const static uint64_t SH_FLD_RESERVED_18_31 = 11405; // 1
+const static uint64_t SH_FLD_RESERVED_18_31_LEN = 11406; // 1
+const static uint64_t SH_FLD_RESERVED_19 = 11407; // 1
+const static uint64_t SH_FLD_RESERVED_19A = 11408; // 43
+const static uint64_t SH_FLD_RESERVED_19_31 = 11409; // 10
+const static uint64_t SH_FLD_RESERVED_19_31_LEN = 11410; // 10
+const static uint64_t SH_FLD_RESERVED_1_12 = 11411; // 4
+const static uint64_t SH_FLD_RESERVED_1_12_LEN = 11412; // 4
+const static uint64_t SH_FLD_RESERVED_1_5 = 11413; // 1
+const static uint64_t SH_FLD_RESERVED_1_5_LEN = 11414; // 1
+const static uint64_t SH_FLD_RESERVED_1_7 = 11415; // 1
+const static uint64_t SH_FLD_RESERVED_1_7_LEN = 11416; // 1
+const static uint64_t SH_FLD_RESERVED_2 = 11417; // 2
+const static uint64_t SH_FLD_RESERVED_20 = 11418; // 1
+const static uint64_t SH_FLD_RESERVED_20_22 = 11419; // 1
+const static uint64_t SH_FLD_RESERVED_20_22_LEN = 11420; // 1
+const static uint64_t SH_FLD_RESERVED_20_23 = 11421; // 12
+const static uint64_t SH_FLD_RESERVED_20_23_LEN = 11422; // 12
+const static uint64_t SH_FLD_RESERVED_20_31 = 11423; // 2
+const static uint64_t SH_FLD_RESERVED_20_31_LEN = 11424; // 2
+const static uint64_t SH_FLD_RESERVED_20_LEN = 11425; // 1
+const static uint64_t SH_FLD_RESERVED_21 = 11426; // 8
+const static uint64_t SH_FLD_RESERVED_22C = 11427; // 43
+const static uint64_t SH_FLD_RESERVED_23 = 11428; // 4
+const static uint64_t SH_FLD_RESERVED_23C = 11429; // 43
+const static uint64_t SH_FLD_RESERVED_23_26 = 11430; // 8
+const static uint64_t SH_FLD_RESERVED_23_26_LEN = 11431; // 8
+const static uint64_t SH_FLD_RESERVED_23_63 = 11432; // 2
+const static uint64_t SH_FLD_RESERVED_23_63_LEN = 11433; // 2
+const static uint64_t SH_FLD_RESERVED_24 = 11434; // 5
+const static uint64_t SH_FLD_RESERVED_24_25 = 11435; // 2
+const static uint64_t SH_FLD_RESERVED_24_25_LEN = 11436; // 2
+const static uint64_t SH_FLD_RESERVED_24_29 = 11437; // 1
+const static uint64_t SH_FLD_RESERVED_24_29_LEN = 11438; // 1
+const static uint64_t SH_FLD_RESERVED_24_31 = 11439; // 1
+const static uint64_t SH_FLD_RESERVED_24_31_LEN = 11440; // 1
+const static uint64_t SH_FLD_RESERVED_24_LEN = 11441; // 1
+const static uint64_t SH_FLD_RESERVED_25 = 11442; // 11
+const static uint64_t SH_FLD_RESERVED_25_26 = 11443; // 3
+const static uint64_t SH_FLD_RESERVED_25_26_LEN = 11444; // 3
+const static uint64_t SH_FLD_RESERVED_27_63 = 11445; // 2
+const static uint64_t SH_FLD_RESERVED_27_63_LEN = 11446; // 2
+const static uint64_t SH_FLD_RESERVED_28 = 11447; // 3
+const static uint64_t SH_FLD_RESERVED_28_29 = 11448; // 6
+const static uint64_t SH_FLD_RESERVED_28_29_LEN = 11449; // 6
+const static uint64_t SH_FLD_RESERVED_28_31 = 11450; // 68
+const static uint64_t SH_FLD_RESERVED_28_31_LEN = 11451; // 68
+const static uint64_t SH_FLD_RESERVED_28_LEN = 11452; // 2
+const static uint64_t SH_FLD_RESERVED_2E = 11453; // 43
+const static uint64_t SH_FLD_RESERVED_2_11 = 11454; // 24
+const static uint64_t SH_FLD_RESERVED_2_11_LEN = 11455; // 24
+const static uint64_t SH_FLD_RESERVED_2_3 = 11456; // 3
+const static uint64_t SH_FLD_RESERVED_2_3_LEN = 11457; // 3
+const static uint64_t SH_FLD_RESERVED_3 = 11458; // 34
+const static uint64_t SH_FLD_RESERVED_30 = 11459; // 1
+const static uint64_t SH_FLD_RESERVED_30C = 11460; // 43
+const static uint64_t SH_FLD_RESERVED_31 = 11461; // 3
+const static uint64_t SH_FLD_RESERVED_31C = 11462; // 43
+const static uint64_t SH_FLD_RESERVED_31_LEN = 11463; // 2
+const static uint64_t SH_FLD_RESERVED_32 = 11464; // 26
+const static uint64_t SH_FLD_RESERVED_32_33 = 11465; // 4
+const static uint64_t SH_FLD_RESERVED_32_33_LEN = 11466; // 4
+const static uint64_t SH_FLD_RESERVED_32_34 = 11467; // 7
+const static uint64_t SH_FLD_RESERVED_32_34_LEN = 11468; // 7
+const static uint64_t SH_FLD_RESERVED_32_35 = 11469; // 2
+const static uint64_t SH_FLD_RESERVED_32_35_LEN = 11470; // 2
+const static uint64_t SH_FLD_RESERVED_32_39 = 11471; // 3
+const static uint64_t SH_FLD_RESERVED_32_39_LEN = 11472; // 3
+const static uint64_t SH_FLD_RESERVED_32_40 = 11473; // 10
+const static uint64_t SH_FLD_RESERVED_32_40_LEN = 11474; // 10
+const static uint64_t SH_FLD_RESERVED_32_43 = 11475; // 1
+const static uint64_t SH_FLD_RESERVED_32_43_LEN = 11476; // 1
+const static uint64_t SH_FLD_RESERVED_32_63 = 11477; // 8
+const static uint64_t SH_FLD_RESERVED_32_63_LEN = 11478; // 8
+const static uint64_t SH_FLD_RESERVED_33A = 11479; // 43
+const static uint64_t SH_FLD_RESERVED_33_63 = 11480; // 2
+const static uint64_t SH_FLD_RESERVED_33_63_LEN = 11481; // 2
+const static uint64_t SH_FLD_RESERVED_34 = 11482; // 1
+const static uint64_t SH_FLD_RESERVED_34A = 11483; // 43
+const static uint64_t SH_FLD_RESERVED_35 = 11484; // 1
+const static uint64_t SH_FLD_RESERVED_35A = 11485; // 43
+const static uint64_t SH_FLD_RESERVED_36_37 = 11486; // 8
+const static uint64_t SH_FLD_RESERVED_36_37_LEN = 11487; // 8
+const static uint64_t SH_FLD_RESERVED_36_39 = 11488; // 12
+const static uint64_t SH_FLD_RESERVED_36_39_LEN = 11489; // 12
+const static uint64_t SH_FLD_RESERVED_37 = 11490; // 1
+const static uint64_t SH_FLD_RESERVED_37_51 = 11491; // 1
+const static uint64_t SH_FLD_RESERVED_37_51_LEN = 11492; // 1
+const static uint64_t SH_FLD_RESERVED_37_56 = 11493; // 8
+const static uint64_t SH_FLD_RESERVED_37_56_LEN = 11494; // 8
+const static uint64_t SH_FLD_RESERVED_38 = 11495; // 1
+const static uint64_t SH_FLD_RESERVED_38A = 11496; // 43
+const static uint64_t SH_FLD_RESERVED_38_39 = 11497; // 24
+const static uint64_t SH_FLD_RESERVED_38_39_LEN = 11498; // 24
+const static uint64_t SH_FLD_RESERVED_38_41 = 11499; // 2
+const static uint64_t SH_FLD_RESERVED_38_41_LEN = 11500; // 2
+const static uint64_t SH_FLD_RESERVED_38_63 = 11501; // 2
+const static uint64_t SH_FLD_RESERVED_38_63_LEN = 11502; // 2
+const static uint64_t SH_FLD_RESERVED_39 = 11503; // 12
+const static uint64_t SH_FLD_RESERVED_39A = 11504; // 43
+const static uint64_t SH_FLD_RESERVED_39_47 = 11505; // 64
+const static uint64_t SH_FLD_RESERVED_39_47_LEN = 11506; // 64
+const static uint64_t SH_FLD_RESERVED_3E = 11507; // 43
+const static uint64_t SH_FLD_RESERVED_4 = 11508; // 14
+const static uint64_t SH_FLD_RESERVED_40 = 11509; // 35
+const static uint64_t SH_FLD_RESERVED_40_41 = 11510; // 7
+const static uint64_t SH_FLD_RESERVED_40_41_LEN = 11511; // 7
+const static uint64_t SH_FLD_RESERVED_40_42 = 11512; // 1
+const static uint64_t SH_FLD_RESERVED_40_42_LEN = 11513; // 1
+const static uint64_t SH_FLD_RESERVED_40_47 = 11514; // 1
+const static uint64_t SH_FLD_RESERVED_40_47_LEN = 11515; // 1
+const static uint64_t SH_FLD_RESERVED_41 = 11516; // 2
+const static uint64_t SH_FLD_RESERVED_41_42 = 11517; // 10
+const static uint64_t SH_FLD_RESERVED_41_42_LEN = 11518; // 10
+const static uint64_t SH_FLD_RESERVED_41_43 = 11519; // 1
+const static uint64_t SH_FLD_RESERVED_41_43_LEN = 11520; // 1
+const static uint64_t SH_FLD_RESERVED_41_63 = 11521; // 8
+const static uint64_t SH_FLD_RESERVED_41_63_LEN = 11522; // 8
+const static uint64_t SH_FLD_RESERVED_42 = 11523; // 2
+const static uint64_t SH_FLD_RESERVED_42A = 11524; // 43
+const static uint64_t SH_FLD_RESERVED_42_43 = 11525; // 12
+const static uint64_t SH_FLD_RESERVED_42_43_LEN = 11526; // 12
+const static uint64_t SH_FLD_RESERVED_43 = 11527; // 2
+const static uint64_t SH_FLD_RESERVED_43A = 11528; // 43
+const static uint64_t SH_FLD_RESERVED_43C = 11529; // 43
+const static uint64_t SH_FLD_RESERVED_43_44 = 11530; // 2
+const static uint64_t SH_FLD_RESERVED_43_44_LEN = 11531; // 2
+const static uint64_t SH_FLD_RESERVED_44 = 11532; // 9
+const static uint64_t SH_FLD_RESERVED_44_47 = 11533; // 1
+const static uint64_t SH_FLD_RESERVED_44_47_LEN = 11534; // 1
+const static uint64_t SH_FLD_RESERVED_45 = 11535; // 1
+const static uint64_t SH_FLD_RESERVED_45_63 = 11536; // 1
+const static uint64_t SH_FLD_RESERVED_45_63_LEN = 11537; // 1
+const static uint64_t SH_FLD_RESERVED_46 = 11538; // 1
+const static uint64_t SH_FLD_RESERVED_47 = 11539; // 1
+const static uint64_t SH_FLD_RESERVED_47_48 = 11540; // 2
+const static uint64_t SH_FLD_RESERVED_47_48_LEN = 11541; // 2
+const static uint64_t SH_FLD_RESERVED_48 = 11542; // 26
+const static uint64_t SH_FLD_RESERVED_48_49 = 11543; // 1
+const static uint64_t SH_FLD_RESERVED_48_49_LEN = 11544; // 1
+const static uint64_t SH_FLD_RESERVED_48_50 = 11545; // 2
+const static uint64_t SH_FLD_RESERVED_48_50_LEN = 11546; // 2
+const static uint64_t SH_FLD_RESERVED_48_55 = 11547; // 1
+const static uint64_t SH_FLD_RESERVED_48_55_LEN = 11548; // 1
+const static uint64_t SH_FLD_RESERVED_48_63 = 11549; // 10
+const static uint64_t SH_FLD_RESERVED_48_63_LEN = 11550; // 10
+const static uint64_t SH_FLD_RESERVED_49_63 = 11551; // 8
+const static uint64_t SH_FLD_RESERVED_49_63_LEN = 11552; // 8
+const static uint64_t SH_FLD_RESERVED_4_5 = 11553; // 12
+const static uint64_t SH_FLD_RESERVED_4_5_LEN = 11554; // 12
+const static uint64_t SH_FLD_RESERVED_4_7 = 11555; // 33
+const static uint64_t SH_FLD_RESERVED_4_7_LEN = 11556; // 33
+const static uint64_t SH_FLD_RESERVED_4_LEN = 11557; // 1
+const static uint64_t SH_FLD_RESERVED_5 = 11558; // 1
+const static uint64_t SH_FLD_RESERVED_50 = 11559; // 4
+const static uint64_t SH_FLD_RESERVED_50_51 = 11560; // 1
+const static uint64_t SH_FLD_RESERVED_50_51_LEN = 11561; // 1
+const static uint64_t SH_FLD_RESERVED_51 = 11562; // 8
+const static uint64_t SH_FLD_RESERVED_51_63 = 11563; // 1
+const static uint64_t SH_FLD_RESERVED_51_63_LEN = 11564; // 1
+const static uint64_t SH_FLD_RESERVED_52 = 11565; // 38
+const static uint64_t SH_FLD_RESERVED_52_55 = 11566; // 64
+const static uint64_t SH_FLD_RESERVED_52_55_LEN = 11567; // 64
+const static uint64_t SH_FLD_RESERVED_52_56 = 11568; // 8
+const static uint64_t SH_FLD_RESERVED_52_56_LEN = 11569; // 8
+const static uint64_t SH_FLD_RESERVED_53 = 11570; // 8
+const static uint64_t SH_FLD_RESERVED_53_55 = 11571; // 6
+const static uint64_t SH_FLD_RESERVED_53_55_LEN = 11572; // 6
+const static uint64_t SH_FLD_RESERVED_53_59 = 11573; // 2
+const static uint64_t SH_FLD_RESERVED_53_59_LEN = 11574; // 2
+const static uint64_t SH_FLD_RESERVED_53_63 = 11575; // 1
+const static uint64_t SH_FLD_RESERVED_53_63_LEN = 11576; // 1
+const static uint64_t SH_FLD_RESERVED_54_63 = 11577; // 8
+const static uint64_t SH_FLD_RESERVED_54_63_LEN = 11578; // 8
+const static uint64_t SH_FLD_RESERVED_55_63 = 11579; // 8
+const static uint64_t SH_FLD_RESERVED_55_63_LEN = 11580; // 8
+const static uint64_t SH_FLD_RESERVED_56 = 11581; // 40
+const static uint64_t SH_FLD_RESERVED_56_57 = 11582; // 1
+const static uint64_t SH_FLD_RESERVED_56_57_LEN = 11583; // 1
+const static uint64_t SH_FLD_RESERVED_56_58 = 11584; // 4
+const static uint64_t SH_FLD_RESERVED_56_58_LEN = 11585; // 4
+const static uint64_t SH_FLD_RESERVED_56_59 = 11586; // 1
+const static uint64_t SH_FLD_RESERVED_56_59_LEN = 11587; // 1
+const static uint64_t SH_FLD_RESERVED_56_63 = 11588; // 17
+const static uint64_t SH_FLD_RESERVED_56_63_LEN = 11589; // 17
+const static uint64_t SH_FLD_RESERVED_57 = 11590; // 24
+const static uint64_t SH_FLD_RESERVED_57_58 = 11591; // 1
+const static uint64_t SH_FLD_RESERVED_57_58_LEN = 11592; // 1
+const static uint64_t SH_FLD_RESERVED_57_59 = 11593; // 2
+const static uint64_t SH_FLD_RESERVED_57_59_LEN = 11594; // 2
+const static uint64_t SH_FLD_RESERVED_57_63 = 11595; // 8
+const static uint64_t SH_FLD_RESERVED_57_63_LEN = 11596; // 8
+const static uint64_t SH_FLD_RESERVED_58_63 = 11597; // 24
+const static uint64_t SH_FLD_RESERVED_58_63_LEN = 11598; // 24
+const static uint64_t SH_FLD_RESERVED_59 = 11599; // 1
+const static uint64_t SH_FLD_RESERVED_5_15 = 11600; // 1
+const static uint64_t SH_FLD_RESERVED_5_15_LEN = 11601; // 1
+const static uint64_t SH_FLD_RESERVED_5_7 = 11602; // 30
+const static uint64_t SH_FLD_RESERVED_5_7_LEN = 11603; // 30
+const static uint64_t SH_FLD_RESERVED_5_LEN = 11604; // 1
+const static uint64_t SH_FLD_RESERVED_6 = 11605; // 2
+const static uint64_t SH_FLD_RESERVED_60 = 11606; // 24
+const static uint64_t SH_FLD_RESERVED_60_63 = 11607; // 7
+const static uint64_t SH_FLD_RESERVED_60_63_LEN = 11608; // 7
+const static uint64_t SH_FLD_RESERVED_61 = 11609; // 24
+const static uint64_t SH_FLD_RESERVED_61_63 = 11610; // 16
+const static uint64_t SH_FLD_RESERVED_61_63_LEN = 11611; // 16
+const static uint64_t SH_FLD_RESERVED_62 = 11612; // 5
+const static uint64_t SH_FLD_RESERVED_62_63 = 11613; // 8
+const static uint64_t SH_FLD_RESERVED_62_63_LEN = 11614; // 8
+const static uint64_t SH_FLD_RESERVED_63 = 11615; // 12
+const static uint64_t SH_FLD_RESERVED_6C = 11616; // 43
+const static uint64_t SH_FLD_RESERVED_6E = 11617; // 43
+const static uint64_t SH_FLD_RESERVED_6_14 = 11618; // 2
+const static uint64_t SH_FLD_RESERVED_6_14_LEN = 11619; // 2
+const static uint64_t SH_FLD_RESERVED_6_7 = 11620; // 26
+const static uint64_t SH_FLD_RESERVED_6_7_LEN = 11621; // 26
+const static uint64_t SH_FLD_RESERVED_7 = 11622; // 2
+const static uint64_t SH_FLD_RESERVED_7C = 11623; // 43
+const static uint64_t SH_FLD_RESERVED_7_8 = 11624; // 2
+const static uint64_t SH_FLD_RESERVED_7_8_LEN = 11625; // 2
+const static uint64_t SH_FLD_RESERVED_7_9 = 11626; // 8
+const static uint64_t SH_FLD_RESERVED_7_9_LEN = 11627; // 8
+const static uint64_t SH_FLD_RESERVED_7_LEN = 11628; // 1
+const static uint64_t SH_FLD_RESERVED_8 = 11629; // 5
+const static uint64_t SH_FLD_RESERVED_8_10 = 11630; // 30
+const static uint64_t SH_FLD_RESERVED_8_10_LEN = 11631; // 30
+const static uint64_t SH_FLD_RESERVED_8_11 = 11632; // 12
+const static uint64_t SH_FLD_RESERVED_8_11_LEN = 11633; // 12
+const static uint64_t SH_FLD_RESERVED_8_37 = 11634; // 2
+const static uint64_t SH_FLD_RESERVED_8_37_LEN = 11635; // 2
+const static uint64_t SH_FLD_RESERVED_8_9 = 11636; // 1
+const static uint64_t SH_FLD_RESERVED_8_9_LEN = 11637; // 1
+const static uint64_t SH_FLD_RESERVED_8_LEN = 11638; // 1
+const static uint64_t SH_FLD_RESERVED_9 = 11639; // 27
+const static uint64_t SH_FLD_RESERVED_9_27 = 11640; // 1
+const static uint64_t SH_FLD_RESERVED_9_27_LEN = 11641; // 1
+const static uint64_t SH_FLD_RESERVED_CERR_24 = 11642; // 8
+const static uint64_t SH_FLD_RESERVED_CERR_25 = 11643; // 8
+const static uint64_t SH_FLD_RESERVED_FOR_ADDRESS = 11644; // 1
+const static uint64_t SH_FLD_RESERVED_FOR_ADDRESS_LEN = 11645; // 1
+const static uint64_t SH_FLD_RESERVED_FOR_CONFIGS = 11646; // 1
+const static uint64_t SH_FLD_RESERVED_FOR_CONFIGS_LEN = 11647; // 1
+const static uint64_t SH_FLD_RESERVED_FOR_ERRS = 11648; // 1
+const static uint64_t SH_FLD_RESERVED_FOR_ERRS_LEN = 11649; // 1
+const static uint64_t SH_FLD_RESERVED_ID_55C = 11650; // 43
+const static uint64_t SH_FLD_RESERVED_ID_61C = 11651; // 43
+const static uint64_t SH_FLD_RESERVED_ID_62C = 11652; // 43
+const static uint64_t SH_FLD_RESERVED_ID_63C = 11653; // 43
+const static uint64_t SH_FLD_RESERVED_LEN = 11654; // 47
+const static uint64_t SH_FLD_RESERVED_TEST_CONTROL_35C = 11655; // 43
+const static uint64_t SH_FLD_RESERVED_TEST_CONTROL_36C = 11656; // 43
+const static uint64_t SH_FLD_RESERVED_TEST_CONTROL_37C = 11657; // 43
+const static uint64_t SH_FLD_RESERVED_TEST_CONTROL_38C = 11658; // 43
+const static uint64_t SH_FLD_RESERVED_TEST_CONTROL_39C = 11659; // 43
+const static uint64_t SH_FLD_RESERVE_39_52 = 11660; // 2
+const static uint64_t SH_FLD_RESERVE_39_52_LEN = 11661; // 2
+const static uint64_t SH_FLD_RESET = 11662; // 27
+const static uint64_t SH_FLD_RESET_0_7 = 11663; // 1
+const static uint64_t SH_FLD_RESET_0_7_LEN = 11664; // 1
+const static uint64_t SH_FLD_RESET_EP = 11665; // 43
+const static uint64_t SH_FLD_RESET_ERROR_LOGS = 11666; // 2
+const static uint64_t SH_FLD_RESET_ERR_RPT = 11667; // 8
+const static uint64_t SH_FLD_RESET_IMPRECISE_QERR = 11668; // 12
+const static uint64_t SH_FLD_RESET_KEEPER = 11669; // 18
+const static uint64_t SH_FLD_RESET_LEN = 11670; // 2
+const static uint64_t SH_FLD_RESET_ON_PARITY = 11671; // 1
+const static uint64_t SH_FLD_RESET_PIB = 11672; // 1
+const static uint64_t SH_FLD_RESET_RECOVER = 11673; // 8
+const static uint64_t SH_FLD_RESET_STAB = 11674; // 8
+const static uint64_t SH_FLD_RESET_STATE_INDICATOR = 11675; // 30
+const static uint64_t SH_FLD_RESET_TOD_STATE = 11676; // 1
+const static uint64_t SH_FLD_RESET_TRAP_CNFG = 11677; // 2
+const static uint64_t SH_FLD_RESET_TRIG_SEL = 11678; // 43
+const static uint64_t SH_FLD_RESET_TRIG_SEL_LEN = 11679; // 43
+const static uint64_t SH_FLD_RESET_ZCAL = 11680; // 8
+const static uint64_t SH_FLD_RESID_FE_LEN_0 = 11681; // 1
+const static uint64_t SH_FLD_RESID_FE_LEN_0_LEN = 11682; // 1
+const static uint64_t SH_FLD_RESID_FE_LEN_1 = 11683; // 1
+const static uint64_t SH_FLD_RESID_FE_LEN_1_LEN = 11684; // 1
+const static uint64_t SH_FLD_RESID_FE_LEN_2 = 11685; // 1
+const static uint64_t SH_FLD_RESID_FE_LEN_2_LEN = 11686; // 1
+const static uint64_t SH_FLD_RESID_FE_LEN_3 = 11687; // 1
+const static uint64_t SH_FLD_RESID_FE_LEN_3_LEN = 11688; // 1
+const static uint64_t SH_FLD_RESP_PKT_RCV = 11689; // 2
+const static uint64_t SH_FLD_RESSEL = 11690; // 4
+const static uint64_t SH_FLD_RESULT = 11691; // 1
+const static uint64_t SH_FLD_RESULT_AVAILABLE = 11692; // 2
+const static uint64_t SH_FLD_RESULT_LEN = 11693; // 1
+const static uint64_t SH_FLD_RESUME_FROM_PAUSE = 11694; // 2
+const static uint64_t SH_FLD_RETRAIN_PERCAL_SW = 11695; // 8
+const static uint64_t SH_FLD_RETRY_COUNTER = 11696; // 1
+const static uint64_t SH_FLD_RETRY_COUNTER_LEN = 11697; // 1
+const static uint64_t SH_FLD_RETRY_LPC_LFSR_SELECT = 11698; // 4
+const static uint64_t SH_FLD_RETRY_LPC_LFSR_SELECT_LEN = 11699; // 4
+const static uint64_t SH_FLD_RETRY_VALUE = 11700; // 1
+const static uint64_t SH_FLD_RETRY_VALUE_LEN = 11701; // 1
+const static uint64_t SH_FLD_RETURNQ_ERR = 11702; // 4
+const static uint64_t SH_FLD_RG_CERR_BITS = 11703; // 1
+const static uint64_t SH_FLD_RG_CERR_BITS_LEN = 11704; // 1
+const static uint64_t SH_FLD_RG_CERR_RESET = 11705; // 1
+const static uint64_t SH_FLD_RG_ECC_CE_ERROR = 11706; // 2
+const static uint64_t SH_FLD_RG_ECC_SUE_ERROR = 11707; // 2
+const static uint64_t SH_FLD_RG_ECC_UE_ERROR = 11708; // 2
+const static uint64_t SH_FLD_RG_LOGIC_HW_ERROR = 11709; // 2
+const static uint64_t SH_FLD_RG_TRACE_GROUP_SEL_HI = 11710; // 1
+const static uint64_t SH_FLD_RG_TRACE_GROUP_SEL_HI_LEN = 11711; // 1
+const static uint64_t SH_FLD_RG_TRACE_GROUP_SEL_LO = 11712; // 1
+const static uint64_t SH_FLD_RG_TRACE_GROUP_SEL_LO_LEN = 11713; // 1
+const static uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_01 = 11714; // 1
+const static uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_01_LEN = 11715; // 1
+const static uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_23 = 11716; // 1
+const static uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_23_LEN = 11717; // 1
+const static uint64_t SH_FLD_RI_N = 11718; // 43
+const static uint64_t SH_FLD_RMA_BAR = 11719; // 1
+const static uint64_t SH_FLD_RMA_BAR_LEN = 11720; // 1
+const static uint64_t SH_FLD_RMA_BAR_MASK = 11721; // 1
+const static uint64_t SH_FLD_RMA_BAR_MASK_LEN = 11722; // 1
+const static uint64_t SH_FLD_RND_BACKOFF_ENABLE = 11723; // 2
+const static uint64_t SH_FLD_RNG0_BIST_FAIL = 11724; // 1
+const static uint64_t SH_FLD_RNG0_FAIL = 11725; // 1
+const static uint64_t SH_FLD_RNG0_INJ_CONTINOUS_ERROR = 11726; // 1
+const static uint64_t SH_FLD_RNG1_BIST_FAIL = 11727; // 1
+const static uint64_t SH_FLD_RNG1_FAIL = 11728; // 1
+const static uint64_t SH_FLD_RNG1_INJ_CONTINOUS_ERROR = 11729; // 1
+const static uint64_t SH_FLD_RNG_CNTRL_LOGIC_ERR = 11730; // 1
+const static uint64_t SH_FLD_RNG_FIRST_FAIL = 11731; // 1
+const static uint64_t SH_FLD_RNG_SECOND_FAIL = 11732; // 1
+const static uint64_t SH_FLD_RNW = 11733; // 15
+const static uint64_t SH_FLD_RPT = 11734; // 2
+const static uint64_t SH_FLD_RPT_LEN = 11735; // 2
+const static uint64_t SH_FLD_RRDM_DLY = 11736; // 8
+const static uint64_t SH_FLD_RRDM_DLY_LEN = 11737; // 8
+const static uint64_t SH_FLD_RRN_BYPASS_ENABLE = 11738; // 1
+const static uint64_t SH_FLD_RRN_DATA = 11739; // 1
+const static uint64_t SH_FLD_RRN_DATA_LEN = 11740; // 1
+const static uint64_t SH_FLD_RROP_DLY = 11741; // 8
+const static uint64_t SH_FLD_RROP_DLY_LEN = 11742; // 8
+const static uint64_t SH_FLD_RRQ_CAPACITY_LIMIT = 11743; // 4
+const static uint64_t SH_FLD_RRQ_CAPACITY_LIMIT_LEN = 11744; // 4
+const static uint64_t SH_FLD_RRQ_HANG = 11745; // 8
+const static uint64_t SH_FLD_RRQ_PE = 11746; // 8
+const static uint64_t SH_FLD_RRSBG_DLY = 11747; // 8
+const static uint64_t SH_FLD_RRSBG_DLY_LEN = 11748; // 8
+const static uint64_t SH_FLD_RRSMDR_DLY = 11749; // 8
+const static uint64_t SH_FLD_RRSMDR_DLY_LEN = 11750; // 8
+const static uint64_t SH_FLD_RRSMSR_DLY = 11751; // 8
+const static uint64_t SH_FLD_RRSMSR_DLY_LEN = 11752; // 8
+const static uint64_t SH_FLD_RSD_CRD_AT_MACRO = 11753; // 1
+const static uint64_t SH_FLD_RSD_CRD_AT_MACRO_LEN = 11754; // 1
+const static uint64_t SH_FLD_RSD_CRD_DMA_READ = 11755; // 1
+const static uint64_t SH_FLD_RSD_CRD_DMA_READ_LEN = 11756; // 1
+const static uint64_t SH_FLD_RSD_CRD_DMA_WRITE = 11757; // 1
+const static uint64_t SH_FLD_RSD_CRD_DMA_WRITE_LEN = 11758; // 1
+const static uint64_t SH_FLD_RSD_CRD_EQC_DOING_CI_LOAD = 11759; // 1
+const static uint64_t SH_FLD_RSD_CRD_EQC_DOING_CI_LOAD_LEN = 11760; // 1
+const static uint64_t SH_FLD_RSD_CRD_EQ_POST = 11761; // 1
+const static uint64_t SH_FLD_RSD_CRD_EQ_POST_LEN = 11762; // 1
+const static uint64_t SH_FLD_RSD_CRD_TRIG_FWD_1 = 11763; // 1
+const static uint64_t SH_FLD_RSD_CRD_TRIG_FWD_1_LEN = 11764; // 1
+const static uint64_t SH_FLD_RSD_CRD_TRIG_FWD_2 = 11765; // 1
+const static uint64_t SH_FLD_RSD_CRD_TRIG_FWD_2_LEN = 11766; // 1
+const static uint64_t SH_FLD_RSEL = 11767; // 10
+const static uint64_t SH_FLD_RSEL_LEN = 11768; // 10
+const static uint64_t SH_FLD_RSP_AE_ALWAYS = 11769; // 6
+const static uint64_t SH_FLD_RSP_CTL_CRED_SINGLE_ENA = 11770; // 6
+const static uint64_t SH_FLD_RSV17 = 11771; // 2
+const static uint64_t SH_FLD_RSV18 = 11772; // 2
+const static uint64_t SH_FLD_RSV19 = 11773; // 2
+const static uint64_t SH_FLD_RSV26 = 11774; // 2
+const static uint64_t SH_FLD_RSV27 = 11775; // 2
+const static uint64_t SH_FLD_RSV34 = 11776; // 2
+const static uint64_t SH_FLD_RSV35 = 11777; // 2
+const static uint64_t SH_FLD_RSV6 = 11778; // 2
+const static uint64_t SH_FLD_RSV7 = 11779; // 2
+const static uint64_t SH_FLD_RSVD0 = 11780; // 1
+const static uint64_t SH_FLD_RTAGFLUSH_FAILED = 11781; // 2
+const static uint64_t SH_FLD_RTAG_PARITY = 11782; // 1
+const static uint64_t SH_FLD_RTAG_PERR = 11783; // 1
+const static uint64_t SH_FLD_RTIM_THOLD_FORCE = 11784; // 43
+const static uint64_t SH_FLD_RTY_COUNT = 11785; // 2
+const static uint64_t SH_FLD_RTY_COUNT_LEN = 11786; // 2
+const static uint64_t SH_FLD_RUNNING = 11787; // 92
+const static uint64_t SH_FLD_RUNN_MODE = 11788; // 43
+const static uint64_t SH_FLD_RUN_CHIPLET_SCAN0 = 11789; // 43
+const static uint64_t SH_FLD_RUN_CHIPLET_SCAN0_NO_PLL = 11790; // 43
+const static uint64_t SH_FLD_RUN_DYN_RECAL_TIMER = 11791; // 4
+const static uint64_t SH_FLD_RUN_LANE_DL_MASK = 11792; // 2
+const static uint64_t SH_FLD_RUN_LANE_VEC_0_15 = 11793; // 2
+const static uint64_t SH_FLD_RUN_LANE_VEC_0_15_LEN = 11794; // 2
+const static uint64_t SH_FLD_RUN_LANE_VEC_16_23 = 11795; // 2
+const static uint64_t SH_FLD_RUN_LANE_VEC_16_23_LEN = 11796; // 2
+const static uint64_t SH_FLD_RUN_ON_CAPTURE_DR = 11797; // 43
+const static uint64_t SH_FLD_RUN_ON_UPDATE_DR = 11798; // 43
+const static uint64_t SH_FLD_RUN_SCAN0 = 11799; // 43
+const static uint64_t SH_FLD_RUN_STATE_MASK = 11800; // 43
+const static uint64_t SH_FLD_RUN_STOP_HYP = 11801; // 30
+const static uint64_t SH_FLD_RUN_STOP_OCC = 11802; // 30
+const static uint64_t SH_FLD_RUN_STOP_OTR = 11803; // 30
+const static uint64_t SH_FLD_RUN_TCK = 11804; // 1
+const static uint64_t SH_FLD_RUN_TCK_EQ0_ERR = 11805; // 1
+const static uint64_t SH_FLD_RWDM_DLY = 11806; // 8
+const static uint64_t SH_FLD_RWDM_DLY_LEN = 11807; // 8
+const static uint64_t SH_FLD_RWSMDR_DLY = 11808; // 8
+const static uint64_t SH_FLD_RWSMDR_DLY_LEN = 11809; // 8
+const static uint64_t SH_FLD_RWSMSR_DLY = 11810; // 8
+const static uint64_t SH_FLD_RWSMSR_DLY_LEN = 11811; // 8
+const static uint64_t SH_FLD_RXAERR = 11812; // 6
+const static uint64_t SH_FLD_RXBERR = 11813; // 6
+const static uint64_t SH_FLD_RXCAL = 11814; // 116
+const static uint64_t SH_FLD_RXCERR = 11815; // 6
+const static uint64_t SH_FLD_RXDERR = 11816; // 6
+const static uint64_t SH_FLD_RXEERR = 11817; // 6
+const static uint64_t SH_FLD_RXFERR = 11818; // 6
+const static uint64_t SH_FLD_RXGERR = 11819; // 6
+const static uint64_t SH_FLD_RXHERR = 11820; // 6
+const static uint64_t SH_FLD_RXIERR = 11821; // 6
+const static uint64_t SH_FLD_RXJERR = 11822; // 6
+const static uint64_t SH_FLD_RXKERR = 11823; // 6
+const static uint64_t SH_FLD_RXLERR = 11824; // 6
+const static uint64_t SH_FLD_RXMERR = 11825; // 6
+const static uint64_t SH_FLD_RXNERR = 11826; // 6
+const static uint64_t SH_FLD_RXOERR = 11827; // 6
+const static uint64_t SH_FLD_RXPERR = 11828; // 6
+const static uint64_t SH_FLD_RX_BUS_WIDTH = 11829; // 4
+const static uint64_t SH_FLD_RX_BUS_WIDTH_LEN = 11830; // 4
+const static uint64_t SH_FLD_RX_PCB_DATA_P = 11831; // 1
+const static uint64_t SH_FLD_RX_PCB_DATA_P_ERR = 11832; // 1
+const static uint64_t SH_FLD_RX_SELECT = 11833; // 4
+const static uint64_t SH_FLD_RX_SELECT_LEN = 11834; // 4
+const static uint64_t SH_FLD_RX_TTYPE_0 = 11835; // 4
+const static uint64_t SH_FLD_RX_TTYPE_1 = 11836; // 4
+const static uint64_t SH_FLD_RX_TTYPE_1_ON_STEP_ENABLE = 11837; // 1
+const static uint64_t SH_FLD_RX_TTYPE_2 = 11838; // 4
+const static uint64_t SH_FLD_RX_TTYPE_3 = 11839; // 4
+const static uint64_t SH_FLD_RX_TTYPE_4 = 11840; // 4
+const static uint64_t SH_FLD_RX_TTYPE_4_DATA_PARITY = 11841; // 4
+const static uint64_t SH_FLD_RX_TTYPE_5 = 11842; // 4
+const static uint64_t SH_FLD_RX_TTYPE_INVALID = 11843; // 4
+const static uint64_t SH_FLD_S0_BIT_MAP = 11844; // 8
+const static uint64_t SH_FLD_S0_BIT_MAP_LEN = 11845; // 8
+const static uint64_t SH_FLD_S1_BIT_MAP = 11846; // 8
+const static uint64_t SH_FLD_S1_BIT_MAP_LEN = 11847; // 8
+const static uint64_t SH_FLD_S2_BIT_MAP = 11848; // 8
+const static uint64_t SH_FLD_S2_BIT_MAP_LEN = 11849; // 8
+const static uint64_t SH_FLD_SAFE_REFRESH_MODE = 11850; // 8
+const static uint64_t SH_FLD_SAFE_REFRESH_MODE_CLR = 11851; // 8
+const static uint64_t SH_FLD_SAMPLED_SMD_PIN = 11852; // 1
+const static uint64_t SH_FLD_SAMPLE_GUTS = 11853; // 43
+const static uint64_t SH_FLD_SAMPLE_GUTS_LEN = 11854; // 43
+const static uint64_t SH_FLD_SAMPLE_PULSE_CNT = 11855; // 43
+const static uint64_t SH_FLD_SAMPLE_PULSE_CNT_LEN = 11856; // 43
+const static uint64_t SH_FLD_SAMPLE_VALID = 11857; // 12
+const static uint64_t SH_FLD_SAMPTEST_ENABLE = 11858; // 1
+const static uint64_t SH_FLD_SAMPTEST_MATCH_TH_MAX = 11859; // 1
+const static uint64_t SH_FLD_SAMPTEST_MATCH_TH_MAX_LEN = 11860; // 1
+const static uint64_t SH_FLD_SAMPTEST_MATCH_TH_MIN = 11861; // 1
+const static uint64_t SH_FLD_SAMPTEST_MATCH_TH_MIN_LEN = 11862; // 1
+const static uint64_t SH_FLD_SAMPTEST_RRN_ENABLE = 11863; // 1
+const static uint64_t SH_FLD_SAMPTEST_WINDOW_SIZE = 11864; // 1
+const static uint64_t SH_FLD_SAMPTEST_WINDOW_SIZE_LEN = 11865; // 1
+const static uint64_t SH_FLD_SBASE = 11866; // 12
+const static uint64_t SH_FLD_SBASE_LEN = 11867; // 12
+const static uint64_t SH_FLD_SBC_DMA = 11868; // 1
+const static uint64_t SH_FLD_SBC_DMA_LEN = 11869; // 1
+const static uint64_t SH_FLD_SBC_EOI = 11870; // 1
+const static uint64_t SH_FLD_SBC_EOI_LEN = 11871; // 1
+const static uint64_t SH_FLD_SBC_LOOKUP = 11872; // 1
+const static uint64_t SH_FLD_SBC_LOOKUP_LEN = 11873; // 1
+const static uint64_t SH_FLD_SBEFIFO_DATA = 11874; // 5
+const static uint64_t SH_FLD_SBEFIFO_RESET = 11875; // 5
+const static uint64_t SH_FLD_SB_STRENGTH = 11876; // 43
+const static uint64_t SH_FLD_SB_STRENGTH_LEN = 11877; // 43
+const static uint64_t SH_FLD_SCAN0_MODE = 11878; // 43
+const static uint64_t SH_FLD_SCAN_CLK_USE_EVEN = 11879; // 43
+const static uint64_t SH_FLD_SCAN_COUNT = 11880; // 43
+const static uint64_t SH_FLD_SCAN_COUNT_LEN = 11881; // 43
+const static uint64_t SH_FLD_SCAN_INIT_VERSION_PARITY_MASK = 11882; // 43
+const static uint64_t SH_FLD_SCAN_RATIO = 11883; // 43
+const static uint64_t SH_FLD_SCAN_RATIO_LEN = 11884; // 43
+const static uint64_t SH_FLD_SCOMFIR_ERR_DUP = 11885; // 1
+const static uint64_t SH_FLD_SCOM_CMD_REG_INJ = 11886; // 2
+const static uint64_t SH_FLD_SCOM_CMD_REG_INJ_MODE = 11887; // 2
+const static uint64_t SH_FLD_SCOM_ERR = 11888; // 6
+const static uint64_t SH_FLD_SCOM_ERR1 = 11889; // 48
+const static uint64_t SH_FLD_SCOM_ERR2 = 11890; // 52
+const static uint64_t SH_FLD_SCOM_ERROR = 11891; // 8
+const static uint64_t SH_FLD_SCOM_ERR_DUP = 11892; // 2
+const static uint64_t SH_FLD_SCOM_FATAL_REG_PE = 11893; // 10
+const static uint64_t SH_FLD_SCOM_FIR_HMI = 11894; // 96
+const static uint64_t SH_FLD_SCOM_LINK01_RESET_KEEPER = 11895; // 2
+const static uint64_t SH_FLD_SCOM_LINK23_RESET_KEEPER = 11896; // 2
+const static uint64_t SH_FLD_SCOM_LINK45_RESET_KEEPER = 11897; // 2
+const static uint64_t SH_FLD_SCOM_LINK67_RESET_KEEPER = 11898; // 1
+const static uint64_t SH_FLD_SCOM_PARITY_CLASS_RECOVERABLE = 11899; // 8
+const static uint64_t SH_FLD_SCOM_PARITY_CLASS_STATUS = 11900; // 8
+const static uint64_t SH_FLD_SCOM_PARITY_CLASS_UNRECOVERABLE = 11901; // 8
+const static uint64_t SH_FLD_SCOM_PARITY_ERR = 11902; // 3
+const static uint64_t SH_FLD_SCOM_PARITY_ERR2 = 11903; // 3
+const static uint64_t SH_FLD_SCOM_PE = 11904; // 3
+const static uint64_t SH_FLD_SCOM_PERR0 = 11905; // 6
+const static uint64_t SH_FLD_SCOM_PERR1 = 11906; // 6
+const static uint64_t SH_FLD_SCOM_PE_DUP = 11907; // 3
+const static uint64_t SH_FLD_SCOM_RECOVERABLE_REG_PE = 11908; // 10
+const static uint64_t SH_FLD_SCOPE_ATTN_BAR = 11909; // 1
+const static uint64_t SH_FLD_SCOPE_ATTN_BAR_LEN = 11910; // 1
+const static uint64_t SH_FLD_SCOPE_CONTROL = 11911; // 6
+const static uint64_t SH_FLD_SCOPE_CONTROL_LEN = 11912; // 6
+const static uint64_t SH_FLD_SCOPE_MODE = 11913; // 48
+const static uint64_t SH_FLD_SCOPE_MODE_LEN = 11914; // 48
+const static uint64_t SH_FLD_SCPTGT_LFSR_MODE = 11915; // 2
+const static uint64_t SH_FLD_SCPTGT_LFSR_MODE_LEN = 11916; // 2
+const static uint64_t SH_FLD_SCRATCH_ATOMIC_DATA = 11917; // 24
+const static uint64_t SH_FLD_SCRATCH_ATOMIC_DATA_LEN = 11918; // 24
+const static uint64_t SH_FLD_SCRATCH_N = 11919; // 4
+const static uint64_t SH_FLD_SCRATCH_N_LEN = 11920; // 4
+const static uint64_t SH_FLD_SEC = 11921; // 8
+const static uint64_t SH_FLD_SECURE_ACCESS = 11922; // 1
+const static uint64_t SH_FLD_SECURE_ACCESS_BIT = 11923; // 1
+const static uint64_t SH_FLD_SECURE_ACCESS_VIOLATION = 11924; // 1
+const static uint64_t SH_FLD_SECURE_DEBUG = 11925; // 1
+const static uint64_t SH_FLD_SECURE_DEBUG_MODE = 11926; // 1
+const static uint64_t SH_FLD_SECURE_ERR = 11927; // 2
+const static uint64_t SH_FLD_SECURE_MODE = 11928; // 1
+const static uint64_t SH_FLD_SECURE_SCOM_ERROR = 11929; // 4
+const static uint64_t SH_FLD_SECURITY_DEBUG_MODE = 11930; // 43
+const static uint64_t SH_FLD_SEC_I_PATH_STEP_CHECK_ENABLE = 11931; // 1
+const static uint64_t SH_FLD_SEC_LEN = 11932; // 8
+const static uint64_t SH_FLD_SEC_M_PATH_0_STEP_CHECK_ENABLE = 11933; // 1
+const static uint64_t SH_FLD_SEC_M_PATH_1_STEP_CHECK_ENABLE = 11934; // 1
+const static uint64_t SH_FLD_SEC_M_PATH_SELECT = 11935; // 2
+const static uint64_t SH_FLD_SEC_M_S_DRAWER_SELECT = 11936; // 2
+const static uint64_t SH_FLD_SEC_M_S_SELECT = 11937; // 2
+const static uint64_t SH_FLD_SEC_SELECT = 11938; // 1
+const static uint64_t SH_FLD_SEC_S_PATH_0_STEP_CHECK_ENABLE = 11939; // 1
+const static uint64_t SH_FLD_SEC_S_PATH_1_STEP_CHECK_ENABLE = 11940; // 1
+const static uint64_t SH_FLD_SEC_S_PATH_SELECT = 11941; // 1
+const static uint64_t SH_FLD_SEC_V = 11942; // 8
+const static uint64_t SH_FLD_SEC_WBRD_DEBUG_0_SELECT = 11943; // 8
+const static uint64_t SH_FLD_SEC_WBRD_DEBUG_1_SELECT = 11944; // 8
+const static uint64_t SH_FLD_SEEPROM_UPDATE_LOCK = 11945; // 1
+const static uint64_t SH_FLD_SEG_TEST_CLK_STATUS = 11946; // 4
+const static uint64_t SH_FLD_SEG_TEST_CLK_STATUS_LEN = 11947; // 4
+const static uint64_t SH_FLD_SEG_TEST_LEAKAGE_CTRL = 11948; // 6
+const static uint64_t SH_FLD_SEG_TEST_MODE = 11949; // 6
+const static uint64_t SH_FLD_SEG_TEST_MODE_LEN = 11950; // 6
+const static uint64_t SH_FLD_SEG_TEST_STATUS = 11951; // 116
+const static uint64_t SH_FLD_SEG_TEST_STATUS_LEN = 11952; // 116
+const static uint64_t SH_FLD_SEIDBAR = 11953; // 1
+const static uint64_t SH_FLD_SEIDBAR_LEN = 11954; // 1
+const static uint64_t SH_FLD_SEL = 11955; // 10
+const static uint64_t SH_FLD_SELD2SPR = 11956; // 10
+const static uint64_t SH_FLD_SELECT = 11957; // 2
+const static uint64_t SH_FLD_SELECT_LEN = 11958; // 2
+const static uint64_t SH_FLD_SELECT_REGISTER_FSP2PIB = 11959; // 1
+const static uint64_t SH_FLD_SELECT_REGISTER_FSP2PIB_LEN = 11960; // 1
+const static uint64_t SH_FLD_SELFBOOT_DONE = 11961; // 1
+const static uint64_t SH_FLD_SELFBOOT_ENGINE_ATTENTION = 11962; // 1
+const static uint64_t SH_FLD_SELF_BUSY_0 = 11963; // 2
+const static uint64_t SH_FLD_SELF_BUSY_1 = 11964; // 2
+const static uint64_t SH_FLD_SELF_BUSY_2 = 11965; // 2
+const static uint64_t SH_FLD_SELF_BUSY_3 = 11966; // 2
+const static uint64_t SH_FLD_SELPFDPW = 11967; // 10
+const static uint64_t SH_FLD_SELPREFB = 11968; // 10
+const static uint64_t SH_FLD_SELPRESPE = 11969; // 10
+const static uint64_t SH_FLD_SEL_03_NPU_NOT = 11970; // 1
+const static uint64_t SH_FLD_SEL_04_NPU_NOT = 11971; // 1
+const static uint64_t SH_FLD_SEL_05_NPU_NOT = 11972; // 1
+const static uint64_t SH_FLD_SEL_0_2 = 11973; // 16
+const static uint64_t SH_FLD_SEL_0_2_LEN = 11974; // 16
+const static uint64_t SH_FLD_SEL_1_3 = 11975; // 16
+const static uint64_t SH_FLD_SEL_1_3_LEN = 11976; // 16
+const static uint64_t SH_FLD_SEL_LEN = 11977; // 10
+const static uint64_t SH_FLD_SEL_RG_PMU_DATA_HI = 11978; // 1
+const static uint64_t SH_FLD_SEL_RG_PMU_DATA_HI_LEN = 11979; // 1
+const static uint64_t SH_FLD_SEL_RG_PMU_DATA_LO = 11980; // 1
+const static uint64_t SH_FLD_SEL_RG_PMU_DATA_LO_LEN = 11981; // 1
+const static uint64_t SH_FLD_SEL_RG_TRACE_DATA_HI = 11982; // 1
+const static uint64_t SH_FLD_SEL_RG_TRACE_DATA_HI_LEN = 11983; // 1
+const static uint64_t SH_FLD_SEL_RG_TRACE_DATA_LO = 11984; // 1
+const static uint64_t SH_FLD_SEL_RG_TRACE_DATA_LO_LEN = 11985; // 1
+const static uint64_t SH_FLD_SEL_RG_TRIGGERS_01 = 11986; // 1
+const static uint64_t SH_FLD_SEL_RG_TRIGGERS_01_LEN = 11987; // 1
+const static uint64_t SH_FLD_SEL_RG_TRIGGERS_23 = 11988; // 1
+const static uint64_t SH_FLD_SEL_RG_TRIGGERS_23_LEN = 11989; // 1
+const static uint64_t SH_FLD_SEL_THOLD_ARY = 11990; // 43
+const static uint64_t SH_FLD_SEL_THOLD_NSL = 11991; // 43
+const static uint64_t SH_FLD_SEL_THOLD_SL = 11992; // 43
+const static uint64_t SH_FLD_SEL_TYPE_0_2 = 11993; // 16
+const static uint64_t SH_FLD_SEL_TYPE_1_3 = 11994; // 16
+const static uint64_t SH_FLD_SEND_DELAY_CYCLES = 11995; // 2
+const static uint64_t SH_FLD_SEND_DELAY_CYCLES_LEN = 11996; // 2
+const static uint64_t SH_FLD_SEND_PACKET_TIMER_VALUE = 11997; // 2
+const static uint64_t SH_FLD_SEND_PACKET_TIMER_VALUE_LEN = 11998; // 2
+const static uint64_t SH_FLD_SEQ = 11999; // 8
+const static uint64_t SH_FLD_SEQ_01 = 12000; // 43
+const static uint64_t SH_FLD_SEQ_01_LEN = 12001; // 43
+const static uint64_t SH_FLD_SEQ_02 = 12002; // 43
+const static uint64_t SH_FLD_SEQ_02_LEN = 12003; // 43
+const static uint64_t SH_FLD_SEQ_03 = 12004; // 43
+const static uint64_t SH_FLD_SEQ_03_LEN = 12005; // 43
+const static uint64_t SH_FLD_SEQ_04 = 12006; // 43
+const static uint64_t SH_FLD_SEQ_04_LEN = 12007; // 43
+const static uint64_t SH_FLD_SEQ_05 = 12008; // 43
+const static uint64_t SH_FLD_SEQ_05_LEN = 12009; // 43
+const static uint64_t SH_FLD_SEQ_06 = 12010; // 43
+const static uint64_t SH_FLD_SEQ_06_LEN = 12011; // 43
+const static uint64_t SH_FLD_SEQ_07 = 12012; // 43
+const static uint64_t SH_FLD_SEQ_07EVEN = 12013; // 43
+const static uint64_t SH_FLD_SEQ_07EVEN_LEN = 12014; // 43
+const static uint64_t SH_FLD_SEQ_07ODD = 12015; // 43
+const static uint64_t SH_FLD_SEQ_07ODD_LEN = 12016; // 43
+const static uint64_t SH_FLD_SEQ_07_LEN = 12017; // 43
+const static uint64_t SH_FLD_SEQ_08 = 12018; // 43
+const static uint64_t SH_FLD_SEQ_08EVEN = 12019; // 43
+const static uint64_t SH_FLD_SEQ_08EVEN_LEN = 12020; // 43
+const static uint64_t SH_FLD_SEQ_08ODD = 12021; // 43
+const static uint64_t SH_FLD_SEQ_08ODD_LEN = 12022; // 43
+const static uint64_t SH_FLD_SEQ_08_LEN = 12023; // 43
+const static uint64_t SH_FLD_SEQ_09 = 12024; // 43
+const static uint64_t SH_FLD_SEQ_09EVEN = 12025; // 43
+const static uint64_t SH_FLD_SEQ_09EVEN_LEN = 12026; // 43
+const static uint64_t SH_FLD_SEQ_09ODD = 12027; // 43
+const static uint64_t SH_FLD_SEQ_09ODD_LEN = 12028; // 43
+const static uint64_t SH_FLD_SEQ_09_LEN = 12029; // 43
+const static uint64_t SH_FLD_SEQ_10 = 12030; // 43
+const static uint64_t SH_FLD_SEQ_10EVEN = 12031; // 43
+const static uint64_t SH_FLD_SEQ_10EVEN_LEN = 12032; // 43
+const static uint64_t SH_FLD_SEQ_10ODD = 12033; // 43
+const static uint64_t SH_FLD_SEQ_10ODD_LEN = 12034; // 43
+const static uint64_t SH_FLD_SEQ_10_LEN = 12035; // 43
+const static uint64_t SH_FLD_SEQ_11 = 12036; // 43
+const static uint64_t SH_FLD_SEQ_11EVEN = 12037; // 43
+const static uint64_t SH_FLD_SEQ_11EVEN_LEN = 12038; // 43
+const static uint64_t SH_FLD_SEQ_11ODD = 12039; // 43
+const static uint64_t SH_FLD_SEQ_11ODD_LEN = 12040; // 43
+const static uint64_t SH_FLD_SEQ_11_LEN = 12041; // 43
+const static uint64_t SH_FLD_SEQ_12 = 12042; // 43
+const static uint64_t SH_FLD_SEQ_12EVEN = 12043; // 43
+const static uint64_t SH_FLD_SEQ_12EVEN_LEN = 12044; // 43
+const static uint64_t SH_FLD_SEQ_12ODD = 12045; // 43
+const static uint64_t SH_FLD_SEQ_12ODD_LEN = 12046; // 43
+const static uint64_t SH_FLD_SEQ_12_LEN = 12047; // 43
+const static uint64_t SH_FLD_SEQ_13_01EVEN = 12048; // 43
+const static uint64_t SH_FLD_SEQ_13_01EVEN_LEN = 12049; // 43
+const static uint64_t SH_FLD_SEQ_14_01ODD = 12050; // 43
+const static uint64_t SH_FLD_SEQ_14_01ODD_LEN = 12051; // 43
+const static uint64_t SH_FLD_SEQ_15_02EVEN = 12052; // 43
+const static uint64_t SH_FLD_SEQ_15_02EVEN_LEN = 12053; // 43
+const static uint64_t SH_FLD_SEQ_16_02ODD = 12054; // 43
+const static uint64_t SH_FLD_SEQ_16_02ODD_LEN = 12055; // 43
+const static uint64_t SH_FLD_SEQ_17_03EVEN = 12056; // 43
+const static uint64_t SH_FLD_SEQ_17_03EVEN_LEN = 12057; // 43
+const static uint64_t SH_FLD_SEQ_18_03ODD = 12058; // 43
+const static uint64_t SH_FLD_SEQ_18_03ODD_LEN = 12059; // 43
+const static uint64_t SH_FLD_SEQ_19_04EVEN = 12060; // 43
+const static uint64_t SH_FLD_SEQ_19_04EVEN_LEN = 12061; // 43
+const static uint64_t SH_FLD_SEQ_20_04ODD = 12062; // 43
+const static uint64_t SH_FLD_SEQ_20_04ODD_LEN = 12063; // 43
+const static uint64_t SH_FLD_SEQ_21_05EVEN = 12064; // 43
+const static uint64_t SH_FLD_SEQ_21_05EVEN_LEN = 12065; // 43
+const static uint64_t SH_FLD_SEQ_22_05ODD = 12066; // 43
+const static uint64_t SH_FLD_SEQ_22_05ODD_LEN = 12067; // 43
+const static uint64_t SH_FLD_SEQ_23_06EVEN = 12068; // 43
+const static uint64_t SH_FLD_SEQ_23_06EVEN_LEN = 12069; // 43
+const static uint64_t SH_FLD_SEQ_24_06ODD = 12070; // 43
+const static uint64_t SH_FLD_SEQ_24_06ODD_LEN = 12071; // 43
+const static uint64_t SH_FLD_SEQ_MASK = 12072; // 8
+const static uint64_t SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK = 12073; // 43
+const static uint64_t SH_FLD_SERVO_CHG_CFG = 12074; // 6
+const static uint64_t SH_FLD_SERVO_CHG_CFG_LEN = 12075; // 6
+const static uint64_t SH_FLD_SERVO_DONE = 12076; // 6
+const static uint64_t SH_FLD_SERVO_OP = 12077; // 6
+const static uint64_t SH_FLD_SERVO_OP_LEN = 12078; // 6
+const static uint64_t SH_FLD_SERVO_RECAL_IP = 12079; // 4
+const static uint64_t SH_FLD_SERVO_RESULT = 12080; // 6
+const static uint64_t SH_FLD_SERVO_RESULT_LEN = 12081; // 6
+const static uint64_t SH_FLD_SERVO_THRESH1 = 12082; // 6
+const static uint64_t SH_FLD_SERVO_THRESH1_LEN = 12083; // 6
+const static uint64_t SH_FLD_SERVO_THRESH2 = 12084; // 6
+const static uint64_t SH_FLD_SERVO_THRESH2_LEN = 12085; // 6
+const static uint64_t SH_FLD_SET = 12086; // 6
+const static uint64_t SH_FLD_SET_CMDS = 12087; // 2
+const static uint64_t SH_FLD_SET_CMDS_EN = 12088; // 2
+const static uint64_t SH_FLD_SET_CMDS_LEN = 12089; // 2
+const static uint64_t SH_FLD_SET_ECC_INJECT_ERR = 12090; // 12
+const static uint64_t SH_FLD_SET_INDEX = 12091; // 2
+const static uint64_t SH_FLD_SET_INDEX_LEN = 12092; // 2
+const static uint64_t SH_FLD_SET_LEN = 12093; // 6
+const static uint64_t SH_FLD_SF_INCREMENT_MODE = 12094; // 2
+const static uint64_t SH_FLD_SGB_BYTE_VALID = 12095; // 18
+const static uint64_t SH_FLD_SGB_BYTE_VALID_LEN = 12096; // 18
+const static uint64_t SH_FLD_SGB_FLUSH_PENDING = 12097; // 18
+const static uint64_t SH_FLD_SG_HIGH_DURING_FILL = 12098; // 43
+const static uint64_t SH_FLD_SHADOW_ANALOGTUNE = 12099; // 14
+const static uint64_t SH_FLD_SHADOW_ANALOGTUNE_LEN = 12100; // 14
+const static uint64_t SH_FLD_SHADOW_ATSTSEL = 12101; // 14
+const static uint64_t SH_FLD_SHADOW_ATSTSEL_LEN = 12102; // 14
+const static uint64_t SH_FLD_SHADOW_BANDSEL = 12103; // 14
+const static uint64_t SH_FLD_SHADOW_BANDSEL_LEN = 12104; // 14
+const static uint64_t SH_FLD_SHADOW_BGOFFSET = 12105; // 14
+const static uint64_t SH_FLD_SHADOW_BGOFFSET_LEN = 12106; // 14
+const static uint64_t SH_FLD_SHADOW_BYPASSN = 12107; // 10
+const static uint64_t SH_FLD_SHADOW_CALRECAL = 12108; // 10
+const static uint64_t SH_FLD_SHADOW_CALREQ = 12109; // 10
+const static uint64_t SH_FLD_SHADOW_CAPSEL = 12110; // 4
+const static uint64_t SH_FLD_SHADOW_CCALBANDSEL = 12111; // 10
+const static uint64_t SH_FLD_SHADOW_CCALBANDSEL_LEN = 12112; // 10
+const static uint64_t SH_FLD_SHADOW_CCALCOMP = 12113; // 10
+const static uint64_t SH_FLD_SHADOW_CCALCVHOLD = 12114; // 10
+const static uint64_t SH_FLD_SHADOW_CCALERR = 12115; // 10
+const static uint64_t SH_FLD_SHADOW_CCALFMAX = 12116; // 10
+const static uint64_t SH_FLD_SHADOW_CCALFMIN = 12117; // 10
+const static uint64_t SH_FLD_SHADOW_CCALLOAD = 12118; // 10
+const static uint64_t SH_FLD_SHADOW_CCALMETH = 12119; // 10
+const static uint64_t SH_FLD_SHADOW_CMLEN = 12120; // 10
+const static uint64_t SH_FLD_SHADOW_CPISEL = 12121; // 14
+const static uint64_t SH_FLD_SHADOW_CPISEL_LEN = 12122; // 14
+const static uint64_t SH_FLD_SHADOW_CSEL = 12123; // 10
+const static uint64_t SH_FLD_SHADOW_CSEL_LEN = 12124; // 10
+const static uint64_t SH_FLD_SHADOW_DIVSELB = 12125; // 10
+const static uint64_t SH_FLD_SHADOW_DIVSELB_LEN = 12126; // 10
+const static uint64_t SH_FLD_SHADOW_DIVSELFB = 12127; // 4
+const static uint64_t SH_FLD_SHADOW_DIVSELFB_LEN = 12128; // 4
+const static uint64_t SH_FLD_SHADOW_EN = 12129; // 10
+const static uint64_t SH_FLD_SHADOW_ENABLE = 12130; // 10
+const static uint64_t SH_FLD_SHADOW_FILTDIVSEL = 12131; // 3
+const static uint64_t SH_FLD_SHADOW_FILTDIVSEL_LEN = 12132; // 3
+const static uint64_t SH_FLD_SHADOW_FRAC1 = 12133; // 3
+const static uint64_t SH_FLD_SHADOW_FRAC1_LEN = 12134; // 3
+const static uint64_t SH_FLD_SHADOW_FRAC2 = 12135; // 3
+const static uint64_t SH_FLD_SHADOW_FRAC2_LEN = 12136; // 3
+const static uint64_t SH_FLD_SHADOW_ITUNE = 12137; // 4
+const static uint64_t SH_FLD_SHADOW_ITUNE_LEN = 12138; // 4
+const static uint64_t SH_FLD_SHADOW_LOCK = 12139; // 10
+const static uint64_t SH_FLD_SHADOW_MUXEN = 12140; // 4
+const static uint64_t SH_FLD_SHADOW_MUXSEL = 12141; // 4
+const static uint64_t SH_FLD_SHADOW_MUXSEL_LEN = 12142; // 4
+const static uint64_t SH_FLD_SHADOW_PCLKDIFSEL = 12143; // 10
+const static uint64_t SH_FLD_SHADOW_PCLKSEL = 12144; // 14
+const static uint64_t SH_FLD_SHADOW_PCLKSEL_LEN = 12145; // 14
+const static uint64_t SH_FLD_SHADOW_PFD360SEL = 12146; // 4
+const static uint64_t SH_FLD_SHADOW_PHASEFB = 12147; // 4
+const static uint64_t SH_FLD_SHADOW_PHASEFB_LEN = 12148; // 4
+const static uint64_t SH_FLD_SHADOW_PLLLOCK = 12149; // 4
+const static uint64_t SH_FLD_SHADOW_RDIV = 12150; // 14
+const static uint64_t SH_FLD_SHADOW_RDIV_LEN = 12151; // 10
+const static uint64_t SH_FLD_SHADOW_REFCLKSEL = 12152; // 4
+const static uint64_t SH_FLD_SHADOW_RESET = 12153; // 10
+const static uint64_t SH_FLD_SHADOW_RESSEL = 12154; // 4
+const static uint64_t SH_FLD_SHADOW_RSEL = 12155; // 10
+const static uint64_t SH_FLD_SHADOW_RSEL_LEN = 12156; // 10
+const static uint64_t SH_FLD_SHADOW_SEL = 12157; // 10
+const static uint64_t SH_FLD_SHADOW_SELD2SPR = 12158; // 10
+const static uint64_t SH_FLD_SHADOW_SELPFDPW = 12159; // 10
+const static uint64_t SH_FLD_SHADOW_SELPREFB = 12160; // 10
+const static uint64_t SH_FLD_SHADOW_SELPRESPE = 12161; // 10
+const static uint64_t SH_FLD_SHADOW_SEL_LEN = 12162; // 10
+const static uint64_t SH_FLD_SHADOW_SPARE = 12163; // 14
+const static uint64_t SH_FLD_SHADOW_SPARE_LEN = 12164; // 10
+const static uint64_t SH_FLD_SHADOW_SPEDIV = 12165; // 10
+const static uint64_t SH_FLD_SHADOW_SPEDIV_LEN = 12166; // 10
+const static uint64_t SH_FLD_SHADOW_SSCGEN = 12167; // 3
+const static uint64_t SH_FLD_SHADOW_SYNCEN = 12168; // 7
+const static uint64_t SH_FLD_SHADOW_THREEPHAS = 12169; // 3
+const static uint64_t SH_FLD_SHADOW_UNUSED23_63 = 12170; // 7
+const static uint64_t SH_FLD_SHADOW_UNUSED23_63_LEN = 12171; // 7
+const static uint64_t SH_FLD_SHADOW_UNUSED4 = 12172; // 7
+const static uint64_t SH_FLD_SHADOW_UNUSED5 = 12173; // 7
+const static uint64_t SH_FLD_SHADOW_UNUSED63 = 12174; // 3
+const static uint64_t SH_FLD_SHADOW_VCORANGE = 12175; // 10
+const static uint64_t SH_FLD_SHADOW_VCORANGE_LEN = 12176; // 10
+const static uint64_t SH_FLD_SHADOW_VCOSEL = 12177; // 10
+const static uint64_t SH_FLD_SHADOW_VREGBYPASS = 12178; // 4
+const static uint64_t SH_FLD_SHADOW_VREGENABLE_N = 12179; // 4
+const static uint64_t SH_FLD_SHADOW_VSEL = 12180; // 10
+const static uint64_t SH_FLD_SHADOW_VSEL_LEN = 12181; // 10
+const static uint64_t SH_FLD_SHA_LATENCY_CFG = 12182; // 1
+const static uint64_t SH_FLD_SHIFTER_PARITY_MASK = 12183; // 43
+const static uint64_t SH_FLD_SHIFTER_VALID_MASK = 12184; // 43
+const static uint64_t SH_FLD_SINGLE_BIT_MPR_RP0 = 12185; // 8
+const static uint64_t SH_FLD_SINGLE_BIT_MPR_RP1 = 12186; // 8
+const static uint64_t SH_FLD_SINGLE_BIT_MPR_RP2 = 12187; // 8
+const static uint64_t SH_FLD_SINGLE_BIT_MPR_RP3 = 12188; // 8
+const static uint64_t SH_FLD_SINGLE_OUTSTANDING_CMD = 12189; // 1
+const static uint64_t SH_FLD_SIR_CERR = 12190; // 8
+const static uint64_t SH_FLD_SIZE = 12191; // 33
+const static uint64_t SH_FLD_SIZE_LEN = 12192; // 33
+const static uint64_t SH_FLD_SKIP_G = 12193; // 3
+const static uint64_t SH_FLD_SKITTER0 = 12194; // 43
+const static uint64_t SH_FLD_SKITTER0_LEN = 12195; // 43
+const static uint64_t SH_FLD_SKITTER_FORCEREG_PARITY_MASK = 12196; // 43
+const static uint64_t SH_FLD_SKITTER_MODEREG_PARITY_MASK = 12197; // 43
+const static uint64_t SH_FLD_SLAVE10_ERROR_CODE = 12198; // 1
+const static uint64_t SH_FLD_SLAVE10_ERROR_CODE_LEN = 12199; // 1
+const static uint64_t SH_FLD_SLAVE10_RESPONSE_BIT = 12200; // 1
+const static uint64_t SH_FLD_SLAVE11_ERROR_CODE = 12201; // 1
+const static uint64_t SH_FLD_SLAVE11_ERROR_CODE_LEN = 12202; // 1
+const static uint64_t SH_FLD_SLAVE11_RESPONSE_BIT = 12203; // 1
+const static uint64_t SH_FLD_SLAVE12_ERROR_CODE = 12204; // 1
+const static uint64_t SH_FLD_SLAVE12_ERROR_CODE_LEN = 12205; // 1
+const static uint64_t SH_FLD_SLAVE12_RESPONSE_BIT = 12206; // 1
+const static uint64_t SH_FLD_SLAVE13_ERROR_CODE = 12207; // 1
+const static uint64_t SH_FLD_SLAVE13_ERROR_CODE_LEN = 12208; // 1
+const static uint64_t SH_FLD_SLAVE13_RESPONSE_BIT = 12209; // 1
+const static uint64_t SH_FLD_SLAVE14_ERROR_CODE = 12210; // 1
+const static uint64_t SH_FLD_SLAVE14_ERROR_CODE_LEN = 12211; // 1
+const static uint64_t SH_FLD_SLAVE14_RESPONSE_BIT = 12212; // 1
+const static uint64_t SH_FLD_SLAVE15_ERROR_CODE = 12213; // 1
+const static uint64_t SH_FLD_SLAVE15_ERROR_CODE_LEN = 12214; // 1
+const static uint64_t SH_FLD_SLAVE15_RESPONSE_BIT = 12215; // 1
+const static uint64_t SH_FLD_SLAVE16_ERROR_CODE = 12216; // 1
+const static uint64_t SH_FLD_SLAVE16_ERROR_CODE_LEN = 12217; // 1
+const static uint64_t SH_FLD_SLAVE16_RESPONSE_BIT = 12218; // 1
+const static uint64_t SH_FLD_SLAVE17_ERROR_CODE = 12219; // 1
+const static uint64_t SH_FLD_SLAVE17_ERROR_CODE_LEN = 12220; // 1
+const static uint64_t SH_FLD_SLAVE17_RESPONSE_BIT = 12221; // 1
+const static uint64_t SH_FLD_SLAVE18_ERROR_CODE = 12222; // 1
+const static uint64_t SH_FLD_SLAVE18_ERROR_CODE_LEN = 12223; // 1
+const static uint64_t SH_FLD_SLAVE18_RESPONSE_BIT = 12224; // 1
+const static uint64_t SH_FLD_SLAVE19_ERROR_CODE = 12225; // 1
+const static uint64_t SH_FLD_SLAVE19_ERROR_CODE_LEN = 12226; // 1
+const static uint64_t SH_FLD_SLAVE19_RESPONSE_BIT = 12227; // 1
+const static uint64_t SH_FLD_SLAVE1_ERROR_CODE = 12228; // 1
+const static uint64_t SH_FLD_SLAVE1_ERROR_CODE_LEN = 12229; // 1
+const static uint64_t SH_FLD_SLAVE1_RESPONSE_BIT = 12230; // 1
+const static uint64_t SH_FLD_SLAVE20_ERROR_CODE = 12231; // 1
+const static uint64_t SH_FLD_SLAVE20_ERROR_CODE_LEN = 12232; // 1
+const static uint64_t SH_FLD_SLAVE20_RESPONSE_BIT = 12233; // 1
+const static uint64_t SH_FLD_SLAVE21_ERROR_CODE = 12234; // 1
+const static uint64_t SH_FLD_SLAVE21_ERROR_CODE_LEN = 12235; // 1
+const static uint64_t SH_FLD_SLAVE21_RESPONSE_BIT = 12236; // 1
+const static uint64_t SH_FLD_SLAVE22_ERROR_CODE = 12237; // 1
+const static uint64_t SH_FLD_SLAVE22_ERROR_CODE_LEN = 12238; // 1
+const static uint64_t SH_FLD_SLAVE22_RESPONSE_BIT = 12239; // 1
+const static uint64_t SH_FLD_SLAVE23_ERROR_CODE = 12240; // 1
+const static uint64_t SH_FLD_SLAVE23_ERROR_CODE_LEN = 12241; // 1
+const static uint64_t SH_FLD_SLAVE23_RESPONSE_BIT = 12242; // 1
+const static uint64_t SH_FLD_SLAVE24_ERROR_CODE = 12243; // 1
+const static uint64_t SH_FLD_SLAVE24_ERROR_CODE_LEN = 12244; // 1
+const static uint64_t SH_FLD_SLAVE24_RESPONSE_BIT = 12245; // 1
+const static uint64_t SH_FLD_SLAVE25_ERROR_CODE = 12246; // 1
+const static uint64_t SH_FLD_SLAVE25_ERROR_CODE_LEN = 12247; // 1
+const static uint64_t SH_FLD_SLAVE25_RESPONSE_BIT = 12248; // 1
+const static uint64_t SH_FLD_SLAVE26_ERROR_CODE = 12249; // 1
+const static uint64_t SH_FLD_SLAVE26_ERROR_CODE_LEN = 12250; // 1
+const static uint64_t SH_FLD_SLAVE26_RESPONSE_BIT = 12251; // 1
+const static uint64_t SH_FLD_SLAVE27_ERROR_CODE = 12252; // 1
+const static uint64_t SH_FLD_SLAVE27_ERROR_CODE_LEN = 12253; // 1
+const static uint64_t SH_FLD_SLAVE27_RESPONSE_BIT = 12254; // 1
+const static uint64_t SH_FLD_SLAVE28_ERROR_CODE = 12255; // 1
+const static uint64_t SH_FLD_SLAVE28_ERROR_CODE_LEN = 12256; // 1
+const static uint64_t SH_FLD_SLAVE28_RESPONSE_BIT = 12257; // 1
+const static uint64_t SH_FLD_SLAVE29_ERROR_CODE = 12258; // 1
+const static uint64_t SH_FLD_SLAVE29_ERROR_CODE_LEN = 12259; // 1
+const static uint64_t SH_FLD_SLAVE29_RESPONSE_BIT = 12260; // 1
+const static uint64_t SH_FLD_SLAVE2_ERROR_CODE = 12261; // 1
+const static uint64_t SH_FLD_SLAVE2_ERROR_CODE_LEN = 12262; // 1
+const static uint64_t SH_FLD_SLAVE2_RESPONSE_BIT = 12263; // 1
+const static uint64_t SH_FLD_SLAVE30_ERROR_CODE = 12264; // 1
+const static uint64_t SH_FLD_SLAVE30_ERROR_CODE_LEN = 12265; // 1
+const static uint64_t SH_FLD_SLAVE30_RESPONSE_BIT = 12266; // 1
+const static uint64_t SH_FLD_SLAVE31_ERROR_CODE = 12267; // 1
+const static uint64_t SH_FLD_SLAVE31_ERROR_CODE_LEN = 12268; // 1
+const static uint64_t SH_FLD_SLAVE31_RESPONSE_BIT = 12269; // 1
+const static uint64_t SH_FLD_SLAVE32_ERROR_CODE = 12270; // 1
+const static uint64_t SH_FLD_SLAVE32_ERROR_CODE_LEN = 12271; // 1
+const static uint64_t SH_FLD_SLAVE32_RESPONSE_BIT = 12272; // 1
+const static uint64_t SH_FLD_SLAVE33_ERROR_CODE = 12273; // 1
+const static uint64_t SH_FLD_SLAVE33_ERROR_CODE_LEN = 12274; // 1
+const static uint64_t SH_FLD_SLAVE33_RESPONSE_BIT = 12275; // 1
+const static uint64_t SH_FLD_SLAVE34_ERROR_CODE = 12276; // 1
+const static uint64_t SH_FLD_SLAVE34_ERROR_CODE_LEN = 12277; // 1
+const static uint64_t SH_FLD_SLAVE34_RESPONSE_BIT = 12278; // 1
+const static uint64_t SH_FLD_SLAVE35_ERROR_CODE = 12279; // 1
+const static uint64_t SH_FLD_SLAVE35_ERROR_CODE_LEN = 12280; // 1
+const static uint64_t SH_FLD_SLAVE35_RESPONSE_BIT = 12281; // 1
+const static uint64_t SH_FLD_SLAVE36_ERROR_CODE = 12282; // 1
+const static uint64_t SH_FLD_SLAVE36_ERROR_CODE_LEN = 12283; // 1
+const static uint64_t SH_FLD_SLAVE36_RESPONSE_BIT = 12284; // 1
+const static uint64_t SH_FLD_SLAVE37_ERROR_CODE = 12285; // 1
+const static uint64_t SH_FLD_SLAVE37_ERROR_CODE_LEN = 12286; // 1
+const static uint64_t SH_FLD_SLAVE37_RESPONSE_BIT = 12287; // 1
+const static uint64_t SH_FLD_SLAVE38_ERROR_CODE = 12288; // 1
+const static uint64_t SH_FLD_SLAVE38_ERROR_CODE_LEN = 12289; // 1
+const static uint64_t SH_FLD_SLAVE38_RESPONSE_BIT = 12290; // 1
+const static uint64_t SH_FLD_SLAVE39_ERROR_CODE = 12291; // 1
+const static uint64_t SH_FLD_SLAVE39_ERROR_CODE_LEN = 12292; // 1
+const static uint64_t SH_FLD_SLAVE39_RESPONSE_BIT = 12293; // 1
+const static uint64_t SH_FLD_SLAVE3_ERROR_CODE = 12294; // 1
+const static uint64_t SH_FLD_SLAVE3_ERROR_CODE_LEN = 12295; // 1
+const static uint64_t SH_FLD_SLAVE3_RESPONSE_BIT = 12296; // 1
+const static uint64_t SH_FLD_SLAVE40_ERROR_CODE = 12297; // 1
+const static uint64_t SH_FLD_SLAVE40_ERROR_CODE_LEN = 12298; // 1
+const static uint64_t SH_FLD_SLAVE40_RESPONSE_BIT = 12299; // 1
+const static uint64_t SH_FLD_SLAVE41_ERROR_CODE = 12300; // 1
+const static uint64_t SH_FLD_SLAVE41_ERROR_CODE_LEN = 12301; // 1
+const static uint64_t SH_FLD_SLAVE41_RESPONSE_BIT = 12302; // 1
+const static uint64_t SH_FLD_SLAVE42_ERROR_CODE = 12303; // 1
+const static uint64_t SH_FLD_SLAVE42_ERROR_CODE_LEN = 12304; // 1
+const static uint64_t SH_FLD_SLAVE42_RESPONSE_BIT = 12305; // 1
+const static uint64_t SH_FLD_SLAVE43_ERROR_CODE = 12306; // 1
+const static uint64_t SH_FLD_SLAVE43_ERROR_CODE_LEN = 12307; // 1
+const static uint64_t SH_FLD_SLAVE43_RESPONSE_BIT = 12308; // 1
+const static uint64_t SH_FLD_SLAVE44_ERROR_CODE = 12309; // 1
+const static uint64_t SH_FLD_SLAVE44_ERROR_CODE_LEN = 12310; // 1
+const static uint64_t SH_FLD_SLAVE44_RESPONSE_BIT = 12311; // 1
+const static uint64_t SH_FLD_SLAVE45_ERROR_CODE = 12312; // 1
+const static uint64_t SH_FLD_SLAVE45_ERROR_CODE_LEN = 12313; // 1
+const static uint64_t SH_FLD_SLAVE45_RESPONSE_BIT = 12314; // 1
+const static uint64_t SH_FLD_SLAVE46_ERROR_CODE = 12315; // 1
+const static uint64_t SH_FLD_SLAVE46_ERROR_CODE_LEN = 12316; // 1
+const static uint64_t SH_FLD_SLAVE46_RESPONSE_BIT = 12317; // 1
+const static uint64_t SH_FLD_SLAVE47_ERROR_CODE = 12318; // 1
+const static uint64_t SH_FLD_SLAVE47_ERROR_CODE_LEN = 12319; // 1
+const static uint64_t SH_FLD_SLAVE47_RESPONSE_BIT = 12320; // 1
+const static uint64_t SH_FLD_SLAVE48_ERROR_CODE = 12321; // 1
+const static uint64_t SH_FLD_SLAVE48_ERROR_CODE_LEN = 12322; // 1
+const static uint64_t SH_FLD_SLAVE48_RESPONSE_BIT = 12323; // 1
+const static uint64_t SH_FLD_SLAVE49_ERROR_CODE = 12324; // 1
+const static uint64_t SH_FLD_SLAVE49_ERROR_CODE_LEN = 12325; // 1
+const static uint64_t SH_FLD_SLAVE49_RESPONSE_BIT = 12326; // 1
+const static uint64_t SH_FLD_SLAVE4_ERROR_CODE = 12327; // 1
+const static uint64_t SH_FLD_SLAVE4_ERROR_CODE_LEN = 12328; // 1
+const static uint64_t SH_FLD_SLAVE4_RESPONSE_BIT = 12329; // 1
+const static uint64_t SH_FLD_SLAVE50_ERROR_CODE = 12330; // 1
+const static uint64_t SH_FLD_SLAVE50_ERROR_CODE_LEN = 12331; // 1
+const static uint64_t SH_FLD_SLAVE50_RESPONSE_BIT = 12332; // 1
+const static uint64_t SH_FLD_SLAVE51_ERROR_CODE = 12333; // 1
+const static uint64_t SH_FLD_SLAVE51_ERROR_CODE_LEN = 12334; // 1
+const static uint64_t SH_FLD_SLAVE51_RESPONSE_BIT = 12335; // 1
+const static uint64_t SH_FLD_SLAVE52_ERROR_CODE = 12336; // 1
+const static uint64_t SH_FLD_SLAVE52_ERROR_CODE_LEN = 12337; // 1
+const static uint64_t SH_FLD_SLAVE52_RESPONSE_BIT = 12338; // 1
+const static uint64_t SH_FLD_SLAVE53_ERROR_CODE = 12339; // 1
+const static uint64_t SH_FLD_SLAVE53_ERROR_CODE_LEN = 12340; // 1
+const static uint64_t SH_FLD_SLAVE53_RESPONSE_BIT = 12341; // 1
+const static uint64_t SH_FLD_SLAVE54_ERROR_CODE = 12342; // 1
+const static uint64_t SH_FLD_SLAVE54_ERROR_CODE_LEN = 12343; // 1
+const static uint64_t SH_FLD_SLAVE54_RESPONSE_BIT = 12344; // 1
+const static uint64_t SH_FLD_SLAVE55_ERROR_CODE = 12345; // 1
+const static uint64_t SH_FLD_SLAVE55_ERROR_CODE_LEN = 12346; // 1
+const static uint64_t SH_FLD_SLAVE55_RESPONSE_BIT = 12347; // 1
+const static uint64_t SH_FLD_SLAVE56_ERROR_CODE = 12348; // 1
+const static uint64_t SH_FLD_SLAVE56_ERROR_CODE_LEN = 12349; // 1
+const static uint64_t SH_FLD_SLAVE56_RESPONSE_BIT = 12350; // 1
+const static uint64_t SH_FLD_SLAVE57_ERROR_CODE = 12351; // 1
+const static uint64_t SH_FLD_SLAVE57_ERROR_CODE_LEN = 12352; // 1
+const static uint64_t SH_FLD_SLAVE57_RESPONSE_BIT = 12353; // 1
+const static uint64_t SH_FLD_SLAVE58_ERROR_CODE = 12354; // 1
+const static uint64_t SH_FLD_SLAVE58_ERROR_CODE_LEN = 12355; // 1
+const static uint64_t SH_FLD_SLAVE58_RESPONSE_BIT = 12356; // 1
+const static uint64_t SH_FLD_SLAVE59_ERROR_CODE = 12357; // 1
+const static uint64_t SH_FLD_SLAVE59_ERROR_CODE_LEN = 12358; // 1
+const static uint64_t SH_FLD_SLAVE59_RESPONSE_BIT = 12359; // 1
+const static uint64_t SH_FLD_SLAVE5_ERROR_CODE = 12360; // 1
+const static uint64_t SH_FLD_SLAVE5_ERROR_CODE_LEN = 12361; // 1
+const static uint64_t SH_FLD_SLAVE5_RESPONSE_BIT = 12362; // 1
+const static uint64_t SH_FLD_SLAVE60_ERROR_CODE = 12363; // 1
+const static uint64_t SH_FLD_SLAVE60_ERROR_CODE_LEN = 12364; // 1
+const static uint64_t SH_FLD_SLAVE60_RESPONSE_BIT = 12365; // 1
+const static uint64_t SH_FLD_SLAVE61_ERROR_CODE = 12366; // 1
+const static uint64_t SH_FLD_SLAVE61_ERROR_CODE_LEN = 12367; // 1
+const static uint64_t SH_FLD_SLAVE61_RESPONSE_BIT = 12368; // 1
+const static uint64_t SH_FLD_SLAVE62_ERROR_CODE = 12369; // 1
+const static uint64_t SH_FLD_SLAVE62_ERROR_CODE_LEN = 12370; // 1
+const static uint64_t SH_FLD_SLAVE62_RESPONSE_BIT = 12371; // 1
+const static uint64_t SH_FLD_SLAVE63_ERROR_CODE = 12372; // 1
+const static uint64_t SH_FLD_SLAVE63_ERROR_CODE_LEN = 12373; // 1
+const static uint64_t SH_FLD_SLAVE63_RESPONSE_BIT = 12374; // 1
+const static uint64_t SH_FLD_SLAVE6_ERROR_CODE = 12375; // 1
+const static uint64_t SH_FLD_SLAVE6_ERROR_CODE_LEN = 12376; // 1
+const static uint64_t SH_FLD_SLAVE6_RESPONSE_BIT = 12377; // 1
+const static uint64_t SH_FLD_SLAVE7_ERROR_CODE = 12378; // 1
+const static uint64_t SH_FLD_SLAVE7_ERROR_CODE_LEN = 12379; // 1
+const static uint64_t SH_FLD_SLAVE7_RESPONSE_BIT = 12380; // 1
+const static uint64_t SH_FLD_SLAVE8_ERROR_CODE = 12381; // 1
+const static uint64_t SH_FLD_SLAVE8_ERROR_CODE_LEN = 12382; // 1
+const static uint64_t SH_FLD_SLAVE8_RESPONSE_BIT = 12383; // 1
+const static uint64_t SH_FLD_SLAVE9_ERROR_CODE = 12384; // 1
+const static uint64_t SH_FLD_SLAVE9_ERROR_CODE_LEN = 12385; // 1
+const static uint64_t SH_FLD_SLAVE9_RESPONSE_BIT = 12386; // 1
+const static uint64_t SH_FLD_SLAVE_IDLE = 12387; // 1
+const static uint64_t SH_FLD_SLAVE_MODE = 12388; // 43
+const static uint64_t SH_FLD_SLAVE_RESET_TO_405_ENABLE = 12389; // 1
+const static uint64_t SH_FLD_SLBI_GROUP_PUMP_EN = 12390; // 12
+const static uint64_t SH_FLD_SLEWCTL = 12391; // 1
+const static uint64_t SH_FLD_SLEWCTL_LEN = 12392; // 1
+const static uint64_t SH_FLD_SLICE = 12393; // 3
+const static uint64_t SH_FLD_SLICE0_CFG_ECC_CE_ERR = 12394; // 2
+const static uint64_t SH_FLD_SLICE0_CFG_ECC_UE_ERR = 12395; // 2
+const static uint64_t SH_FLD_SLICE1_CFG_ECC_CE_ERR = 12396; // 2
+const static uint64_t SH_FLD_SLICE1_CFG_ECC_UE_ERR = 12397; // 2
+const static uint64_t SH_FLD_SLICE2_CFG_ECC_CE_ERR = 12398; // 2
+const static uint64_t SH_FLD_SLICE2_CFG_ECC_UE_ERR = 12399; // 2
+const static uint64_t SH_FLD_SLICE3_CFG_ECC_CE_ERR = 12400; // 2
+const static uint64_t SH_FLD_SLICE3_CFG_ECC_UE_ERR = 12401; // 2
+const static uint64_t SH_FLD_SLICE_LEN = 12402; // 3
+const static uint64_t SH_FLD_SLOT0_B2_VALID = 12403; // 8
+const static uint64_t SH_FLD_SLOT0_D_VALUE = 12404; // 8
+const static uint64_t SH_FLD_SLOT0_M0_VALID = 12405; // 8
+const static uint64_t SH_FLD_SLOT0_M1_VALID = 12406; // 8
+const static uint64_t SH_FLD_SLOT0_ROW15_VALID = 12407; // 8
+const static uint64_t SH_FLD_SLOT0_ROW16_VALID = 12408; // 8
+const static uint64_t SH_FLD_SLOT0_ROW17_VALID = 12409; // 8
+const static uint64_t SH_FLD_SLOT0_S0_VALID = 12410; // 8
+const static uint64_t SH_FLD_SLOT0_S1_VALID = 12411; // 8
+const static uint64_t SH_FLD_SLOT0_S2_VALID = 12412; // 8
+const static uint64_t SH_FLD_SLOT0_VALID = 12413; // 8
+const static uint64_t SH_FLD_SLOT1_B2_VALID = 12414; // 8
+const static uint64_t SH_FLD_SLOT1_D_VALUE = 12415; // 8
+const static uint64_t SH_FLD_SLOT1_M0_VALID = 12416; // 8
+const static uint64_t SH_FLD_SLOT1_M1_VALID = 12417; // 8
+const static uint64_t SH_FLD_SLOT1_ROW15_VALID = 12418; // 8
+const static uint64_t SH_FLD_SLOT1_ROW16_VALID = 12419; // 8
+const static uint64_t SH_FLD_SLOT1_ROW17_VALID = 12420; // 8
+const static uint64_t SH_FLD_SLOT1_S0_VALID = 12421; // 8
+const static uint64_t SH_FLD_SLOT1_S1_VALID = 12422; // 8
+const static uint64_t SH_FLD_SLOT1_S2_VALID = 12423; // 8
+const static uint64_t SH_FLD_SLOT1_VALID = 12424; // 8
+const static uint64_t SH_FLD_SLOW_CMD_RATE = 12425; // 1
+const static uint64_t SH_FLD_SLS_CMD_GCRMSG = 12426; // 4
+const static uint64_t SH_FLD_SLS_CMD_GCRMSG_LEN = 12427; // 4
+const static uint64_t SH_FLD_SLS_CNTR_TAP_PTS = 12428; // 4
+const static uint64_t SH_FLD_SLS_CNTR_TAP_PTS_LEN = 12429; // 4
+const static uint64_t SH_FLD_SLS_DISABLE = 12430; // 4
+const static uint64_t SH_FLD_SLS_EXCEPTION2_CS = 12431; // 4
+const static uint64_t SH_FLD_SLS_EXTEND_SEL = 12432; // 4
+const static uint64_t SH_FLD_SLS_EXTEND_SEL_LEN = 12433; // 4
+const static uint64_t SH_FLD_SLS_LANE_GCRMSG = 12434; // 4
+const static uint64_t SH_FLD_SLS_LANE_GCRMSG_LEN = 12435; // 4
+const static uint64_t SH_FLD_SLS_LANE_SEL_LG_GCRMSG = 12436; // 4
+const static uint64_t SH_FLD_SLS_LANE_SHDW_GCRMSG = 12437; // 4
+const static uint64_t SH_FLD_SLS_LANE_UNSEL_LG_GCRMSG = 12438; // 4
+const static uint64_t SH_FLD_SLS_LANE_VAL_GCRMSG = 12439; // 4
+const static uint64_t SH_FLD_SLS_RCVY_DISABLE = 12440; // 4
+const static uint64_t SH_FLD_SLS_SCRAMBLE_MODE = 12441; // 4
+const static uint64_t SH_FLD_SLS_SCRAMBLE_MODE_LEN = 12442; // 4
+const static uint64_t SH_FLD_SLS_TIMEOUT_SEL = 12443; // 4
+const static uint64_t SH_FLD_SLS_TIMEOUT_SEL_LEN = 12444; // 4
+const static uint64_t SH_FLD_SLV_DIS_ABUSPAR = 12445; // 1
+const static uint64_t SH_FLD_SLV_DIS_BE = 12446; // 1
+const static uint64_t SH_FLD_SLV_DIS_BEPAR = 12447; // 1
+const static uint64_t SH_FLD_SLV_DIS_RDDBUSPAREN = 12448; // 1
+const static uint64_t SH_FLD_SLV_DIS_SACK = 12449; // 1
+const static uint64_t SH_FLD_SLV_DIS_WRDBUSPAR = 12450; // 1
+const static uint64_t SH_FLD_SLV_EVENT_MUX = 12451; // 1
+const static uint64_t SH_FLD_SLV_EVENT_MUX_LEN = 12452; // 1
+const static uint64_t SH_FLD_SLV_LGL_RPR_REQ_GCRMSG = 12453; // 4
+const static uint64_t SH_FLD_SLV_MV_SLS_RPR_REQ_GCRMSG = 12454; // 4
+const static uint64_t SH_FLD_SLV_MV_SLS_SHDW_REQ_GCRMSG = 12455; // 4
+const static uint64_t SH_FLD_SLV_MV_SLS_SHDW_RPR_REQ_GCRMSG = 12456; // 4
+const static uint64_t SH_FLD_SLV_MV_SLS_UNSHDW_REQ_GCRMSG = 12457; // 4
+const static uint64_t SH_FLD_SLV_MV_SLS_UNSHDW_RPR_REQ_GCRMSG = 12458; // 4
+const static uint64_t SH_FLD_SLV_RECAL_ABORT_ACK_FIN_GCRMSG = 12459; // 4
+const static uint64_t SH_FLD_SLV_RECAL_ABORT_MNOP_FIN_GCRMSG = 12460; // 4
+const static uint64_t SH_FLD_SLV_RECAL_ABORT_SNOP_FIN_GCRMSG = 12461; // 4
+const static uint64_t SH_FLD_SLV_RECAL_DONE_NOP_FIN_GCRMSG = 12462; // 4
+const static uint64_t SH_FLD_SLV_RECAL_FAIL_NOP_FIN_GCRMSG = 12463; // 4
+const static uint64_t SH_FLD_SLV_RECAL_FRESULTS_FIN_GCRMSG = 12464; // 4
+const static uint64_t SH_FLD_SLV_SHDW_DONE_FIN_GCRMSG = 12465; // 4
+const static uint64_t SH_FLD_SLV_SHDW_NOP_FIN_GCRMSG = 12466; // 4
+const static uint64_t SH_FLD_SLV_SHDW_RPR_DONE_FIN_GCRMSG = 12467; // 4
+const static uint64_t SH_FLD_SLV_SHDW_RPR_NOP_FIN_GCRMSG = 12468; // 4
+const static uint64_t SH_FLD_SLV_SPARE = 12469; // 1
+const static uint64_t SH_FLD_SLV_UNSHDW_DONE_FIN_GCRMSG = 12470; // 4
+const static uint64_t SH_FLD_SLV_UNSHDW_NOP_FIN_GCRMSG = 12471; // 4
+const static uint64_t SH_FLD_SLV_UNSHDW_RPR_DONE_FIN_GCRMSG = 12472; // 4
+const static uint64_t SH_FLD_SLV_UNSHDW_RPR_NOP_FIN_GCRMSG = 12473; // 4
+const static uint64_t SH_FLD_SMALL_STEP = 12474; // 8
+const static uint64_t SH_FLD_SMALL_STEP_LEN = 12475; // 8
+const static uint64_t SH_FLD_SM_1HOT_ERR = 12476; // 16
+const static uint64_t SH_FLD_SM_RESET = 12477; // 1
+const static uint64_t SH_FLD_SND_CHIPID = 12478; // 1
+const static uint64_t SH_FLD_SND_CHIPID_LEN = 12479; // 1
+const static uint64_t SH_FLD_SND_CNT = 12480; // 1
+const static uint64_t SH_FLD_SND_CNT_LEN = 12481; // 1
+const static uint64_t SH_FLD_SND_CNT_STATUS = 12482; // 1
+const static uint64_t SH_FLD_SND_CNT_STATUS_LEN = 12483; // 1
+const static uint64_t SH_FLD_SND_ERROR = 12484; // 1
+const static uint64_t SH_FLD_SND_GROUPID = 12485; // 1
+const static uint64_t SH_FLD_SND_GROUPID_LEN = 12486; // 1
+const static uint64_t SH_FLD_SND_IN_PROGRESS = 12487; // 1
+const static uint64_t SH_FLD_SND_PHASE_STATUS = 12488; // 1
+const static uint64_t SH_FLD_SND_PHASE_STATUS_LEN = 12489; // 1
+const static uint64_t SH_FLD_SND_QID = 12490; // 1
+const static uint64_t SH_FLD_SND_RESERVATION = 12491; // 1
+const static uint64_t SH_FLD_SND_RESET = 12492; // 1
+const static uint64_t SH_FLD_SND_RETRY_COUNT = 12493; // 1
+const static uint64_t SH_FLD_SND_RETRY_COUNT_LEN = 12494; // 1
+const static uint64_t SH_FLD_SND_RETRY_COUNT_OVERCOM = 12495; // 1
+const static uint64_t SH_FLD_SND_RETRY_THRESH = 12496; // 1
+const static uint64_t SH_FLD_SND_RETRY_THRESH_LEN = 12497; // 1
+const static uint64_t SH_FLD_SND_RSVTO_DIV = 12498; // 1
+const static uint64_t SH_FLD_SND_RSVTO_DIV_LEN = 12499; // 1
+const static uint64_t SH_FLD_SND_SCOPE = 12500; // 1
+const static uint64_t SH_FLD_SND_SCOPE_LEN = 12501; // 1
+const static uint64_t SH_FLD_SND_SLS_CMD_GCRMSG = 12502; // 4
+const static uint64_t SH_FLD_SND_SLS_CMD_PREV_GCRMSG = 12503; // 4
+const static uint64_t SH_FLD_SND_SLS_USING_REG_SCRAMBLE = 12504; // 4
+const static uint64_t SH_FLD_SND_STOP = 12505; // 1
+const static uint64_t SH_FLD_SND_TYPE = 12506; // 1
+const static uint64_t SH_FLD_SNFSM_ADDR_ERR = 12507; // 12
+const static uint64_t SH_FLD_SNGL_THD_EN = 12508; // 2
+const static uint64_t SH_FLD_SNOOPER_RECOVERABLE_ERROR = 12509; // 4
+const static uint64_t SH_FLD_SNOOPER_SYS_XSTOP_ERROR = 12510; // 4
+const static uint64_t SH_FLD_SNOOP_ARRAY_CE = 12511; // 4
+const static uint64_t SH_FLD_SNOOP_ARRAY_UE = 12512; // 4
+const static uint64_t SH_FLD_SNOOP_DIS = 12513; // 8
+const static uint64_t SH_FLD_SNOP = 12514; // 43
+const static uint64_t SH_FLD_SNOP_FORCE_SG = 12515; // 43
+const static uint64_t SH_FLD_SNOP_LEN = 12516; // 43
+const static uint64_t SH_FLD_SNOP_WAIT = 12517; // 43
+const static uint64_t SH_FLD_SNOP_WAIT_LEN = 12518; // 43
+const static uint64_t SH_FLD_SNS1_UNUSED_0_31 = 12519; // 1
+const static uint64_t SH_FLD_SNS1_UNUSED_0_31_LEN = 12520; // 1
+const static uint64_t SH_FLD_SNS2_UNUSED_0_31 = 12521; // 1
+const static uint64_t SH_FLD_SNS2_UNUSED_0_31_LEN = 12522; // 1
+const static uint64_t SH_FLD_SN_MACHINE_HANG_ERR = 12523; // 12
+const static uint64_t SH_FLD_SN_MSG_MAX_CREDIT = 12524; // 2
+const static uint64_t SH_FLD_SN_MSG_MAX_CREDIT_LEN = 12525; // 2
+const static uint64_t SH_FLD_SN_UNSOLICITED_CRESP_ERR = 12526; // 12
+const static uint64_t SH_FLD_SN_UNSOLICITED_CRESP_ERR_LEN = 12527; // 12
+const static uint64_t SH_FLD_SN_WRT_DBUF_MAX_CREDIT = 12528; // 2
+const static uint64_t SH_FLD_SN_WRT_DBUF_MAX_CREDIT_LEN = 12529; // 2
+const static uint64_t SH_FLD_SOFT_CE_COUNT = 12530; // 2
+const static uint64_t SH_FLD_SOFT_CE_COUNT_LEN = 12531; // 2
+const static uint64_t SH_FLD_SOFT_CE_ETE_ATTN = 12532; // 4
+const static uint64_t SH_FLD_SOFT_MCE_COUNT = 12533; // 2
+const static uint64_t SH_FLD_SOFT_MCE_COUNT_LEN = 12534; // 2
+const static uint64_t SH_FLD_SOFT_NCE_ETE_ATTN = 12535; // 10
+const static uint64_t SH_FLD_SOURCE_SELECT = 12536; // 43
+const static uint64_t SH_FLD_SOURCE_SELECT_LEN = 12537; // 43
+const static uint64_t SH_FLD_SOURCE_SUBUNIT_0_1 = 12538; // 1
+const static uint64_t SH_FLD_SOURCE_SUBUNIT_0_1_LEN = 12539; // 1
+const static uint64_t SH_FLD_SOUTH_CTL_DISABLE_WC_ECC = 12540; // 1
+const static uint64_t SH_FLD_SOUTH_CTL_DISABLE_WC_SCRUB = 12541; // 1
+const static uint64_t SH_FLD_SOUTH_CTL_EG_SINGLE_THREAD = 12542; // 1
+const static uint64_t SH_FLD_SOUTH_CTL_EG_WM_CTX_UPDATE_MODE = 12543; // 1
+const static uint64_t SH_FLD_SPAM_EN = 12544; // 8
+const static uint64_t SH_FLD_SPARE = 12545; // 93
+const static uint64_t SH_FLD_SPARE0 = 12546; // 105
+const static uint64_t SH_FLD_SPARE0_LEN = 12547; // 8
+const static uint64_t SH_FLD_SPARE1 = 12548; // 5
+const static uint64_t SH_FLD_SPARE10 = 12549; // 1
+const static uint64_t SH_FLD_SPARE11 = 12550; // 13
+const static uint64_t SH_FLD_SPARE13 = 12551; // 1
+const static uint64_t SH_FLD_SPARE14 = 12552; // 1
+const static uint64_t SH_FLD_SPARE15 = 12553; // 1
+const static uint64_t SH_FLD_SPARE1_ERR = 12554; // 12
+const static uint64_t SH_FLD_SPARE1_ERR_LEN = 12555; // 12
+const static uint64_t SH_FLD_SPARE2 = 12556; // 4
+const static uint64_t SH_FLD_SPARE2_ERR = 12557; // 12
+const static uint64_t SH_FLD_SPARE2_ERR_LEN = 12558; // 12
+const static uint64_t SH_FLD_SPARE3 = 12559; // 1
+const static uint64_t SH_FLD_SPARE4_TIMEOUT = 12560; // 6
+const static uint64_t SH_FLD_SPARE4_TIMEOUT_LEN = 12561; // 6
+const static uint64_t SH_FLD_SPARE7 = 12562; // 1
+const static uint64_t SH_FLD_SPARE8 = 12563; // 1
+const static uint64_t SH_FLD_SPARE9 = 12564; // 1
+const static uint64_t SH_FLD_SPARES = 12565; // 4
+const static uint64_t SH_FLD_SPARES_LEN = 12566; // 4
+const static uint64_t SH_FLD_SPARE_0 = 12567; // 4
+const static uint64_t SH_FLD_SPARE_0_LEN = 12568; // 4
+const static uint64_t SH_FLD_SPARE_1_3 = 12569; // 1
+const static uint64_t SH_FLD_SPARE_1_3_LEN = 12570; // 1
+const static uint64_t SH_FLD_SPARE_2 = 12571; // 4
+const static uint64_t SH_FLD_SPARE_21_23 = 12572; // 12
+const static uint64_t SH_FLD_SPARE_21_23_LEN = 12573; // 12
+const static uint64_t SH_FLD_SPARE_24_31 = 12574; // 1
+const static uint64_t SH_FLD_SPARE_24_31_LEN = 12575; // 1
+const static uint64_t SH_FLD_SPARE_25_27 = 12576; // 12
+const static uint64_t SH_FLD_SPARE_25_27_LEN = 12577; // 12
+const static uint64_t SH_FLD_SPARE_27_28 = 12578; // 12
+const static uint64_t SH_FLD_SPARE_27_28_LEN = 12579; // 12
+const static uint64_t SH_FLD_SPARE_3 = 12580; // 4
+const static uint64_t SH_FLD_SPARE_31 = 12581; // 2
+const static uint64_t SH_FLD_SPARE_32_33 = 12582; // 12
+const static uint64_t SH_FLD_SPARE_32_33_LEN = 12583; // 12
+const static uint64_t SH_FLD_SPARE_38_39 = 12584; // 12
+const static uint64_t SH_FLD_SPARE_38_39_LEN = 12585; // 12
+const static uint64_t SH_FLD_SPARE_4 = 12586; // 2
+const static uint64_t SH_FLD_SPARE_58 = 12587; // 4
+const static uint64_t SH_FLD_SPARE_59 = 12588; // 4
+const static uint64_t SH_FLD_SPARE_60 = 12589; // 4
+const static uint64_t SH_FLD_SPARE_61 = 12590; // 4
+const static uint64_t SH_FLD_SPARE_63 = 12591; // 3
+const static uint64_t SH_FLD_SPARE_6_7 = 12592; // 24
+const static uint64_t SH_FLD_SPARE_6_7_LEN = 12593; // 24
+const static uint64_t SH_FLD_SPARE_8_11 = 12594; // 6
+const static uint64_t SH_FLD_SPARE_8_11_LEN = 12595; // 6
+const static uint64_t SH_FLD_SPARE_9 = 12596; // 12
+const static uint64_t SH_FLD_SPARE_ATTN1 = 12597; // 4
+const static uint64_t SH_FLD_SPARE_DI_CONTROL = 12598; // 1
+const static uint64_t SH_FLD_SPARE_FENCE_CONTROL = 12599; // 1
+const static uint64_t SH_FLD_SPARE_FIR0 = 12600; // 12
+const static uint64_t SH_FLD_SPARE_LEN = 12601; // 76
+const static uint64_t SH_FLD_SPARE_MODE_0 = 12602; // 116
+const static uint64_t SH_FLD_SPARE_MODE_1 = 12603; // 116
+const static uint64_t SH_FLD_SPARE_MODE_2 = 12604; // 116
+const static uint64_t SH_FLD_SPARE_MODE_3 = 12605; // 116
+const static uint64_t SH_FLD_SPARE_N = 12606; // 2
+const static uint64_t SH_FLD_SPARE_N_LEN = 12607; // 2
+const static uint64_t SH_FLD_SPARE_PIB_CONTROL = 12608; // 1
+const static uint64_t SH_FLD_SPARE_RI_CONTROL = 12609; // 1
+const static uint64_t SH_FLD_SPARE_TANK_PLL_CONTROL = 12610; // 1
+const static uint64_t SH_FLD_SPC_WKUP_OVERRIDE = 12611; // 30
+const static uint64_t SH_FLD_SPECIAL_ATTENTION = 12612; // 1
+const static uint64_t SH_FLD_SPECIAL_WAKEUP_C0 = 12613; // 24
+const static uint64_t SH_FLD_SPECIAL_WAKEUP_C1 = 12614; // 24
+const static uint64_t SH_FLD_SPECIAL_WKUP_ACTIVE = 12615; // 30
+const static uint64_t SH_FLD_SPECIAL_WKUP_ACTIVE_FSP = 12616; // 30
+const static uint64_t SH_FLD_SPECIAL_WKUP_ACTIVE_HYP = 12617; // 30
+const static uint64_t SH_FLD_SPECIAL_WKUP_ACTIVE_OCC = 12618; // 30
+const static uint64_t SH_FLD_SPECIAL_WKUP_ACTIVE_OTR = 12619; // 30
+const static uint64_t SH_FLD_SPECIAL_WKUP_DONE = 12620; // 60
+const static uint64_t SH_FLD_SPECIAL_WKUP_PROTOCOL = 12621; // 30
+const static uint64_t SH_FLD_SPECIAL_WKUP_REQUESTED = 12622; // 30
+const static uint64_t SH_FLD_SPECIFIC_GAP_CONDITION = 12623; // 8
+const static uint64_t SH_FLD_SPECIFIC_GAP_CONDITION_LEN = 12624; // 8
+const static uint64_t SH_FLD_SPECIFIC_GAP_COUNT = 12625; // 8
+const static uint64_t SH_FLD_SPECIFIC_GAP_COUNT_LEN = 12626; // 8
+const static uint64_t SH_FLD_SPECULATIVE_CHECKIN_COUNT = 12627; // 1
+const static uint64_t SH_FLD_SPECULATIVE_CHECKIN_COUNT_LEN = 12628; // 1
+const static uint64_t SH_FLD_SPEC_CILD_G = 12629; // 1
+const static uint64_t SH_FLD_SPEC_HPC_DIR_STATE = 12630; // 2
+const static uint64_t SH_FLD_SPEC_HPC_DIR_STATE_LEN = 12631; // 2
+const static uint64_t SH_FLD_SPEC_READ_FILTER_NO_HASH_MODE = 12632; // 4
+const static uint64_t SH_FLD_SPEDIV = 12633; // 20
+const static uint64_t SH_FLD_SPEDIV_LEN = 12634; // 20
+const static uint64_t SH_FLD_SPIPSS_ERROR = 12635; // 1
+const static uint64_t SH_FLD_SPRC0_SEL = 12636; // 24
+const static uint64_t SH_FLD_SPRC1_SEL = 12637; // 24
+const static uint64_t SH_FLD_SPRC2_SEL = 12638; // 24
+const static uint64_t SH_FLD_SPRC3_SEL = 12639; // 24
+const static uint64_t SH_FLD_SPRC_T0_SEL = 12640; // 24
+const static uint64_t SH_FLD_SPRC_T1_SEL = 12641; // 24
+const static uint64_t SH_FLD_SPRC_T2_SEL = 12642; // 24
+const static uint64_t SH_FLD_SPRC_T3_SEL = 12643; // 24
+const static uint64_t SH_FLD_SPRC_WR_EN = 12644; // 24
+const static uint64_t SH_FLD_SPRG0 = 12645; // 18
+const static uint64_t SH_FLD_SPRG0_LEN = 12646; // 18
+const static uint64_t SH_FLD_SPR_LNS_PDWN_LITE_GCRMSG = 12647; // 4
+const static uint64_t SH_FLD_SR = 12648; // 8
+const static uint64_t SH_FLD_SRAM_ABIST_DONE_DC = 12649; // 43
+const static uint64_t SH_FLD_SRAM_ACCESS_MODE = 12650; // 12
+const static uint64_t SH_FLD_SRAM_ADDRESS = 12651; // 12
+const static uint64_t SH_FLD_SRAM_ADDRESS_LEN = 12652; // 12
+const static uint64_t SH_FLD_SRAM_CE = 12653; // 12
+const static uint64_t SH_FLD_SRAM_DATA = 12654; // 12
+const static uint64_t SH_FLD_SRAM_DATA_LEN = 12655; // 12
+const static uint64_t SH_FLD_SRAM_HIGH_PRIORITY = 12656; // 4
+const static uint64_t SH_FLD_SRAM_HIGH_PRIORITY_LEN = 12657; // 4
+const static uint64_t SH_FLD_SRAM_LOW_PRIORITY = 12658; // 4
+const static uint64_t SH_FLD_SRAM_LOW_PRIORITY_LEN = 12659; // 4
+const static uint64_t SH_FLD_SRAM_SCRUB_ENABLE = 12660; // 12
+const static uint64_t SH_FLD_SRAM_SCRUB_ERR = 12661; // 12
+const static uint64_t SH_FLD_SRAM_SCRUB_INDEX = 12662; // 12
+const static uint64_t SH_FLD_SRAM_SCRUB_INDEX_LEN = 12663; // 12
+const static uint64_t SH_FLD_SRAM_UE = 12664; // 12
+const static uint64_t SH_FLD_SRC_DDE = 12665; // 3
+const static uint64_t SH_FLD_SRC_DDE_LEN = 12666; // 3
+const static uint64_t SH_FLD_SRC_SEL_EQ1_ERR = 12667; // 1
+const static uint64_t SH_FLD_SRT_ERROR = 12668; // 1
+const static uint64_t SH_FLD_SR_FINAL_NOP_TIMEOUT_SEL = 12669; // 4
+const static uint64_t SH_FLD_SR_FINAL_NOP_TIMEOUT_SEL_LEN = 12670; // 4
+const static uint64_t SH_FLD_SR_LEN = 12671; // 8
+const static uint64_t SH_FLD_SSCGEN = 12672; // 3
+const static uint64_t SH_FLD_SS_ENABLE = 12673; // 6
+const static uint64_t SH_FLD_ST2_RESET_PERIOD = 12674; // 1
+const static uint64_t SH_FLD_ST2_RESET_PERIOD_LEN = 12675; // 1
+const static uint64_t SH_FLD_STACK_SCOM_ERR0 = 12676; // 9
+const static uint64_t SH_FLD_STACK_SCOM_ERR0_MASK = 12677; // 9
+const static uint64_t SH_FLD_STACK_SCOM_ERR1 = 12678; // 9
+const static uint64_t SH_FLD_STACK_SCOM_ERR1_MASK = 12679; // 9
+const static uint64_t SH_FLD_STAGGERED_PATTERN = 12680; // 8
+const static uint64_t SH_FLD_START = 12681; // 23
+const static uint64_t SH_FLD_START0 = 12682; // 5
+const static uint64_t SH_FLD_START1 = 12683; // 5
+const static uint64_t SH_FLD_STARTING_ADDRESS = 12684; // 4
+const static uint64_t SH_FLD_STARTING_ADDRESS_LEN = 12685; // 4
+const static uint64_t SH_FLD_STARTS_BIST = 12686; // 43
+const static uint64_t SH_FLD_START_BOOT_SEQUENCER = 12687; // 1
+const static uint64_t SH_FLD_START_DESKEW = 12688; // 4
+const static uint64_t SH_FLD_START_EYE_OPT = 12689; // 4
+const static uint64_t SH_FLD_START_FUNC_MODE = 12690; // 4
+const static uint64_t SH_FLD_START_INIT = 12691; // 8
+const static uint64_t SH_FLD_START_JTAG_CMD = 12692; // 1
+const static uint64_t SH_FLD_START_LANE_ID = 12693; // 8
+const static uint64_t SH_FLD_START_LANE_ID_LEN = 12694; // 8
+const static uint64_t SH_FLD_START_PPE_ADDR = 12695; // 4
+const static uint64_t SH_FLD_START_PPE_ADDR_LEN = 12696; // 4
+const static uint64_t SH_FLD_START_REPAIR = 12697; // 4
+const static uint64_t SH_FLD_START_RESTART_VECTOR0 = 12698; // 1
+const static uint64_t SH_FLD_START_RESTART_VECTOR1 = 12699; // 1
+const static uint64_t SH_FLD_START_SEEPROM_ADDRESS = 12700; // 4
+const static uint64_t SH_FLD_START_SEEPROM_ADDRESS_LEN = 12701; // 4
+const static uint64_t SH_FLD_START_WIRETEST = 12702; // 4
+const static uint64_t SH_FLD_START_WR_ADDR = 12703; // 2
+const static uint64_t SH_FLD_START_WR_ADDR_LEN = 12704; // 2
+const static uint64_t SH_FLD_STAT = 12705; // 2
+const static uint64_t SH_FLD_STATE = 12706; // 44
+const static uint64_t SH_FLD_STATE_LEN = 12707; // 43
+const static uint64_t SH_FLD_STATE_LOSS_ENABLE_A_N = 12708; // 96
+const static uint64_t SH_FLD_STATE_MACHINE_TRANSITION_DELAY = 12709; // 1
+const static uint64_t SH_FLD_STATE_MACHINE_TRANSITION_DELAY_LEN = 12710; // 1
+const static uint64_t SH_FLD_STATIC_MAX_SPARES_EXCEEDED = 12711; // 8
+const static uint64_t SH_FLD_STATIC_SPARE_DEPLOYED = 12712; // 8
+const static uint64_t SH_FLD_STATUS = 12713; // 3
+const static uint64_t SH_FLD_STATUS_INVALID_CRESP = 12714; // 2
+const static uint64_t SH_FLD_STATUS_PARITY_ERROR = 12715; // 2
+const static uint64_t SH_FLD_STATUS_PERV = 12716; // 129
+const static uint64_t SH_FLD_STATUS_REC_DROPPED_Q = 12717; // 26
+const static uint64_t SH_FLD_STATUS_REG = 12718; // 1
+const static uint64_t SH_FLD_STATUS_REG_LEN = 12719; // 1
+const static uint64_t SH_FLD_STATUS_SCOM_ERROR = 12720; // 26
+const static uint64_t SH_FLD_STATUS_TRIG_DROPPED_Q = 12721; // 26
+const static uint64_t SH_FLD_STATUS_UNIT1 = 12722; // 129
+const static uint64_t SH_FLD_STATUS_UNIT10 = 12723; // 129
+const static uint64_t SH_FLD_STATUS_UNIT2 = 12724; // 129
+const static uint64_t SH_FLD_STATUS_UNIT3 = 12725; // 129
+const static uint64_t SH_FLD_STATUS_UNIT4 = 12726; // 129
+const static uint64_t SH_FLD_STATUS_UNIT5 = 12727; // 129
+const static uint64_t SH_FLD_STATUS_UNIT6 = 12728; // 129
+const static uint64_t SH_FLD_STATUS_UNIT7 = 12729; // 129
+const static uint64_t SH_FLD_STATUS_UNIT8 = 12730; // 129
+const static uint64_t SH_FLD_STATUS_UNIT9 = 12731; // 129
+const static uint64_t SH_FLD_STATUS_UNUSED = 12732; // 24
+const static uint64_t SH_FLD_STATUS_UNUSED_LEN = 12733; // 24
+const static uint64_t SH_FLD_STAT_LEN = 12734; // 2
+const static uint64_t SH_FLD_STC_MAX_Q_DEPTH = 12735; // 1
+const static uint64_t SH_FLD_STC_MAX_Q_DEPTH_LEN = 12736; // 1
+const static uint64_t SH_FLD_STEP_CHECK_CONSTANT_CPS_ENABLE = 12737; // 1
+const static uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION = 12738; // 1
+const static uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR = 12739; // 3
+const static uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN = 12740; // 3
+const static uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION_LEN = 12741; // 1
+const static uint64_t SH_FLD_STEP_CHECK_ENABLE_CHICKEN_SWITCH = 12742; // 1
+const static uint64_t SH_FLD_STEP_CHECK_STEP_SELECT = 12743; // 1
+const static uint64_t SH_FLD_STEP_CHECK_VALIDITY_COUNT = 12744; // 1
+const static uint64_t SH_FLD_STEP_CHECK_VALIDITY_COUNT_LEN = 12745; // 1
+const static uint64_t SH_FLD_STEP_CREATE_DUAL_EDGE_DISABLE = 12746; // 1
+const static uint64_t SH_FLD_STICKY_CACHE_VDM_DATA = 12747; // 12
+const static uint64_t SH_FLD_STICKY_CACHE_VDM_DATA_LEN = 12748; // 12
+const static uint64_t SH_FLD_STICKY_CORE0_VDM_DATA = 12749; // 12
+const static uint64_t SH_FLD_STICKY_CORE0_VDM_DATA_LEN = 12750; // 12
+const static uint64_t SH_FLD_STICKY_CORE1_VDM_DATA = 12751; // 12
+const static uint64_t SH_FLD_STICKY_CORE1_VDM_DATA_LEN = 12752; // 12
+const static uint64_t SH_FLD_STICKY_CORE2_VDM_DATA = 12753; // 12
+const static uint64_t SH_FLD_STICKY_CORE2_VDM_DATA_LEN = 12754; // 12
+const static uint64_t SH_FLD_STICKY_CORE3_VDM_DATA = 12755; // 12
+const static uint64_t SH_FLD_STICKY_CORE3_VDM_DATA_LEN = 12756; // 12
+const static uint64_t SH_FLD_STICKY_ERROR_INJECT_ENABLE = 12757; // 1
+const static uint64_t SH_FLD_STICKY_VDM_CONTROL_SUMMARY = 12758; // 12
+const static uint64_t SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN = 12759; // 12
+const static uint64_t SH_FLD_STOP = 12760; // 6
+const static uint64_t SH_FLD_STOP1_ACTIVE_ENABLE = 12761; // 12
+const static uint64_t SH_FLD_STOPPED = 12762; // 2
+const static uint64_t SH_FLD_STOP_ACTIVE_MASK = 12763; // 12
+const static uint64_t SH_FLD_STOP_ERROR_0 = 12764; // 2
+const static uint64_t SH_FLD_STOP_ERROR_1 = 12765; // 2
+const static uint64_t SH_FLD_STOP_ERROR_2 = 12766; // 2
+const static uint64_t SH_FLD_STOP_ERROR_3 = 12767; // 2
+const static uint64_t SH_FLD_STOP_ETE_NOW = 12768; // 2
+const static uint64_t SH_FLD_STOP_ETE_RANK_END = 12769; // 2
+const static uint64_t SH_FLD_STOP_GATED = 12770; // 30
+const static uint64_t SH_FLD_STOP_GATED_FSP = 12771; // 30
+const static uint64_t SH_FLD_STOP_MCE = 12772; // 2
+const static uint64_t SH_FLD_STOP_MPE = 12773; // 2
+const static uint64_t SH_FLD_STOP_NCE_HARD = 12774; // 2
+const static uint64_t SH_FLD_STOP_NCE_INTERMITTENT = 12775; // 2
+const static uint64_t SH_FLD_STOP_NCE_SOFT = 12776; // 2
+const static uint64_t SH_FLD_STOP_ON_END_ADDRESS = 12777; // 2
+const static uint64_t SH_FLD_STOP_ON_ERR = 12778; // 2
+const static uint64_t SH_FLD_STOP_OVERRIDE_MODE = 12779; // 12
+const static uint64_t SH_FLD_STOP_REQUEST_LEVEL_A_N = 12780; // 96
+const static uint64_t SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN = 12781; // 96
+const static uint64_t SH_FLD_STOP_RETRYCE = 12782; // 2
+const static uint64_t SH_FLD_STOP_RUNN_ON_XSTOP = 12783; // 43
+const static uint64_t SH_FLD_STOP_SCE = 12784; // 2
+const static uint64_t SH_FLD_STOP_SUE = 12785; // 2
+const static uint64_t SH_FLD_STOP_TRANSITION = 12786; // 30
+const static uint64_t SH_FLD_STOP_TRANSITION_FSP = 12787; // 30
+const static uint64_t SH_FLD_STOP_TRANSITION_FSP_LEN = 12788; // 30
+const static uint64_t SH_FLD_STOP_TRANSITION_HYP = 12789; // 30
+const static uint64_t SH_FLD_STOP_TRANSITION_HYP_LEN = 12790; // 30
+const static uint64_t SH_FLD_STOP_TRANSITION_LEN = 12791; // 30
+const static uint64_t SH_FLD_STOP_TRANSITION_OCC = 12792; // 30
+const static uint64_t SH_FLD_STOP_TRANSITION_OCC_LEN = 12793; // 30
+const static uint64_t SH_FLD_STOP_TRANSITION_OTR = 12794; // 30
+const static uint64_t SH_FLD_STOP_TRANSITION_OTR_LEN = 12795; // 30
+const static uint64_t SH_FLD_STOP_UE = 12796; // 2
+const static uint64_t SH_FLD_STORE_ADDRESS = 12797; // 18
+const static uint64_t SH_FLD_STORE_ADDRESS_LEN = 12798; // 18
+const static uint64_t SH_FLD_STORE_ON_TRIG_MODE = 12799; // 90
+const static uint64_t SH_FLD_STORE_ON_TRIG_MODE_LEN = 12800; // 90
+const static uint64_t SH_FLD_STORE_TIMEOUT = 12801; // 24
+const static uint64_t SH_FLD_STQ_DATA_PARITY_ERR = 12802; // 24
+const static uint64_t SH_FLD_STQ_ERR = 12803; // 12
+const static uint64_t SH_FLD_STQ_ERR_LEN = 12804; // 12
+const static uint64_t SH_FLD_STQ_HW_MAX_0_4 = 12805; // 1
+const static uint64_t SH_FLD_STQ_HW_MAX_0_4_LEN = 12806; // 1
+const static uint64_t SH_FLD_STQ_HW_MIN_0_4 = 12807; // 1
+const static uint64_t SH_FLD_STQ_HW_MIN_0_4_LEN = 12808; // 1
+const static uint64_t SH_FLD_STQ_HYP_MAX_0_4 = 12809; // 1
+const static uint64_t SH_FLD_STQ_HYP_MAX_0_4_LEN = 12810; // 1
+const static uint64_t SH_FLD_STQ_HYP_MIN_0_4 = 12811; // 1
+const static uint64_t SH_FLD_STQ_HYP_MIN_0_4_LEN = 12812; // 1
+const static uint64_t SH_FLD_STQ_INVALID_ST = 12813; // 1
+const static uint64_t SH_FLD_STQ_IPI_MAX_0_4 = 12814; // 1
+const static uint64_t SH_FLD_STQ_IPI_MAX_0_4_LEN = 12815; // 1
+const static uint64_t SH_FLD_STQ_IPI_MIN_0_4 = 12816; // 1
+const static uint64_t SH_FLD_STQ_IPI_MIN_0_4_LEN = 12817; // 1
+const static uint64_t SH_FLD_STQ_OS_MAX_0_4 = 12818; // 1
+const static uint64_t SH_FLD_STQ_OS_MAX_0_4_LEN = 12819; // 1
+const static uint64_t SH_FLD_STQ_OS_MIN_0_4 = 12820; // 1
+const static uint64_t SH_FLD_STQ_OS_MIN_0_4_LEN = 12821; // 1
+const static uint64_t SH_FLD_STQ_RDI_MAX_0_4 = 12822; // 1
+const static uint64_t SH_FLD_STQ_RDI_MAX_0_4_LEN = 12823; // 1
+const static uint64_t SH_FLD_STQ_RDI_MIN_0_4 = 12824; // 1
+const static uint64_t SH_FLD_STQ_RDI_MIN_0_4_LEN = 12825; // 1
+const static uint64_t SH_FLD_STQ_REG_MAX_0_4 = 12826; // 1
+const static uint64_t SH_FLD_STQ_REG_MAX_0_4_LEN = 12827; // 1
+const static uint64_t SH_FLD_STQ_REG_MIN_0_4 = 12828; // 1
+const static uint64_t SH_FLD_STQ_REG_MIN_0_4_LEN = 12829; // 1
+const static uint64_t SH_FLD_STQ_THR_MAX_0_4 = 12830; // 1
+const static uint64_t SH_FLD_STQ_THR_MAX_0_4_LEN = 12831; // 1
+const static uint64_t SH_FLD_STQ_THR_MIN_0_4 = 12832; // 1
+const static uint64_t SH_FLD_STQ_THR_MIN_0_4_LEN = 12833; // 1
+const static uint64_t SH_FLD_STQ_TYPE = 12834; // 12
+const static uint64_t SH_FLD_STQ_TYPE_LEN = 12835; // 12
+const static uint64_t SH_FLD_STQ_VPC_MAX_0_4 = 12836; // 1
+const static uint64_t SH_FLD_STQ_VPC_MAX_0_4_LEN = 12837; // 1
+const static uint64_t SH_FLD_STQ_VPC_MIN_0_4 = 12838; // 1
+const static uint64_t SH_FLD_STQ_VPC_MIN_0_4_LEN = 12839; // 1
+const static uint64_t SH_FLD_STREAM_MODE = 12840; // 4
+const static uint64_t SH_FLD_STREAM_TYPE = 12841; // 4
+const static uint64_t SH_FLD_STRICT_IPI_RULES = 12842; // 1
+const static uint64_t SH_FLD_STRICT_ORDER = 12843; // 1
+const static uint64_t SH_FLD_ST_ACK_DEAD = 12844; // 12
+const static uint64_t SH_FLD_ST_ADDR_ERR = 12845; // 24
+const static uint64_t SH_FLD_ST_CLASS_CMD_ADDR_ERR = 12846; // 4
+const static uint64_t SH_FLD_ST_CLASS_CMD_FOREIGN_LINK_FAIL = 12847; // 4
+const static uint64_t SH_FLD_ST_FOREIGN0_ACK_DEAD = 12848; // 12
+const static uint64_t SH_FLD_ST_FOREIGN1_ACK_DEAD = 12849; // 12
+const static uint64_t SH_FLD_ST_MAX_Q_DEPTH = 12850; // 1
+const static uint64_t SH_FLD_ST_MAX_Q_DEPTH_LEN = 12851; // 1
+const static uint64_t SH_FLD_SUE_DIS_BR = 12852; // 3
+const static uint64_t SH_FLD_SUE_DIS_BR_PERR = 12853; // 3
+const static uint64_t SH_FLD_SUE_DIS_IR = 12854; // 3
+const static uint64_t SH_FLD_SUE_DIS_IR_PERR = 12855; // 3
+const static uint64_t SH_FLD_SUE_DIS_OR = 12856; // 3
+const static uint64_t SH_FLD_SUE_DIS_OR_PERR = 12857; // 3
+const static uint64_t SH_FLD_SUE_DIS_PR = 12858; // 3
+const static uint64_t SH_FLD_SUE_DIS_PT = 12859; // 3
+const static uint64_t SH_FLD_SUMMARY = 12860; // 1
+const static uint64_t SH_FLD_SUOP_ERROR_1 = 12861; // 4
+const static uint64_t SH_FLD_SUOP_ERROR_2 = 12862; // 4
+const static uint64_t SH_FLD_SUOP_ERROR_3 = 12863; // 4
+const static uint64_t SH_FLD_SUPPRESS = 12864; // 301
+const static uint64_t SH_FLD_SUPPRESS_EVEN_CLK = 12865; // 43
+const static uint64_t SH_FLD_SWC_VALUE = 12866; // 1
+const static uint64_t SH_FLD_SWC_VALUE_LEN = 12867; // 1
+const static uint64_t SH_FLD_SWITCHOVER_STATUS = 12868; // 1
+const static uint64_t SH_FLD_SWITCH_SYNC_ERROR_DISABLE = 12869; // 1
+const static uint64_t SH_FLD_SYM_CPB_CHECK_DISABLE = 12870; // 1
+const static uint64_t SH_FLD_SYM_MAX_INRD = 12871; // 1
+const static uint64_t SH_FLD_SYM_MAX_INRD_LEN = 12872; // 1
+const static uint64_t SH_FLD_SYM_MAX_Q_DEPTH = 12873; // 1
+const static uint64_t SH_FLD_SYM_MAX_Q_DEPTH_LEN = 12874; // 1
+const static uint64_t SH_FLD_SYNCEN = 12875; // 7
+const static uint64_t SH_FLD_SYNC_BRK = 12876; // 1
+const static uint64_t SH_FLD_SYNC_BRK_LEN = 12877; // 1
+const static uint64_t SH_FLD_SYNC_CREATE_SPS_SELECT = 12878; // 1
+const static uint64_t SH_FLD_SYNC_CREATE_SPS_SELECT_LEN = 12879; // 1
+const static uint64_t SH_FLD_SYNC_DONE = 12880; // 1
+const static uint64_t SH_FLD_SYNC_DONE_LEN = 12881; // 1
+const static uint64_t SH_FLD_SYNC_FENCE = 12882; // 4
+const static uint64_t SH_FLD_SYNC_GO_CH0 = 12883; // 4
+const static uint64_t SH_FLD_SYNC_GO_CH1 = 12884; // 4
+const static uint64_t SH_FLD_SYNC_MODE = 12885; // 4
+const static uint64_t SH_FLD_SYNC_REPLAY_COUNT = 12886; // 4
+const static uint64_t SH_FLD_SYNC_REPLAY_COUNT_LEN = 12887; // 4
+const static uint64_t SH_FLD_SYNC_RESERVED = 12888; // 4
+const static uint64_t SH_FLD_SYNC_RESERVED_LEN = 12889; // 4
+const static uint64_t SH_FLD_SYNC_RESET = 12890; // 1
+const static uint64_t SH_FLD_SYNC_TIMER_SEL = 12891; // 17
+const static uint64_t SH_FLD_SYNC_TIMER_SEL_LEN = 12892; // 17
+const static uint64_t SH_FLD_SYNC_TYPE = 12893; // 4
+const static uint64_t SH_FLD_SYNC_TYPE_LEN = 12894; // 4
+const static uint64_t SH_FLD_SYN_HI_0_7 = 12895; // 1
+const static uint64_t SH_FLD_SYN_HI_0_7_LEN = 12896; // 1
+const static uint64_t SH_FLD_SYN_LO_0_7 = 12897; // 1
+const static uint64_t SH_FLD_SYN_LO_0_7_LEN = 12898; // 1
+const static uint64_t SH_FLD_SYSCLK_2X_MEMINTCLKO = 12899; // 8
+const static uint64_t SH_FLD_SYSCLK_CLK_GATE = 12900; // 8
+const static uint64_t SH_FLD_SYSCLK_RESET = 12901; // 8
+const static uint64_t SH_FLD_SYSMAP_SM_NOT_LG_SEL = 12902; // 12
+const static uint64_t SH_FLD_SYSTEM = 12903; // 2
+const static uint64_t SH_FLD_SYSTEM_CHECKSTOP = 12904; // 1
+const static uint64_t SH_FLD_SYSTEM_FAST_INIT = 12905; // 43
+const static uint64_t SH_FLD_SYSTEM_LEN = 12906; // 2
+const static uint64_t SH_FLD_SYSTEM_RESET = 12907; // 1
+const static uint64_t SH_FLD_S_PATH_0_PARITY = 12908; // 4
+const static uint64_t SH_FLD_S_PATH_0_STEP_CHECK = 12909; // 4
+const static uint64_t SH_FLD_S_PATH_0_STEP_CHECK_VALID = 12910; // 1
+const static uint64_t SH_FLD_S_PATH_1_PARITY = 12911; // 4
+const static uint64_t SH_FLD_S_PATH_1_STEP_CHECK = 12912; // 4
+const static uint64_t SH_FLD_S_PATH_1_STEP_CHECK_VALID = 12913; // 1
+const static uint64_t SH_FLD_S_PATH_SELECT = 12914; // 1
+const static uint64_t SH_FLD_T0_HONOR_DEBUG_MARKS = 12915; // 24
+const static uint64_t SH_FLD_T0_RUN_Q = 12916; // 24
+const static uint64_t SH_FLD_T1_HONOR_DEBUG_MARKS = 12917; // 24
+const static uint64_t SH_FLD_T1_RUN_Q = 12918; // 24
+const static uint64_t SH_FLD_T2_HONOR_DEBUG_MARKS = 12919; // 24
+const static uint64_t SH_FLD_T2_RUN_Q = 12920; // 24
+const static uint64_t SH_FLD_T3_HONOR_DEBUG_MARKS = 12921; // 24
+const static uint64_t SH_FLD_T3_RUN_Q = 12922; // 24
+const static uint64_t SH_FLD_T4_RUN_Q = 12923; // 24
+const static uint64_t SH_FLD_T5_RUN_Q = 12924; // 24
+const static uint64_t SH_FLD_T6_RUN_Q = 12925; // 24
+const static uint64_t SH_FLD_T7_RUN_Q = 12926; // 24
+const static uint64_t SH_FLD_TABLE_ADDRESS = 12927; // 1
+const static uint64_t SH_FLD_TABLE_ADDRESS_LEN = 12928; // 1
+const static uint64_t SH_FLD_TABLE_DATA = 12929; // 1
+const static uint64_t SH_FLD_TABLE_DATA_LEN = 12930; // 1
+const static uint64_t SH_FLD_TABLE_SELECT = 12931; // 1
+const static uint64_t SH_FLD_TABLE_SELECT_LEN = 12932; // 1
+const static uint64_t SH_FLD_TAG_ECC = 12933; // 8
+const static uint64_t SH_FLD_TAG_ECC_LEN = 12934; // 8
+const static uint64_t SH_FLD_TARGET_DDE = 12935; // 3
+const static uint64_t SH_FLD_TARGET_DDE_LEN = 12936; // 3
+const static uint64_t SH_FLD_TARGET_ID0 = 12937; // 2
+const static uint64_t SH_FLD_TARGET_MIN = 12938; // 2
+const static uint64_t SH_FLD_TARGET_MIN_LEN = 12939; // 2
+const static uint64_t SH_FLD_TARGET_VALID = 12940; // 2
+const static uint64_t SH_FLD_TARGET_VALID_LEN = 12941; // 2
+const static uint64_t SH_FLD_TCBR_TP_PSI_GLB_ERR_0 = 12942; // 4
+const static uint64_t SH_FLD_TCBR_TP_PSI_GLB_ERR_1 = 12943; // 4
+const static uint64_t SH_FLD_TCE_CACHE_1W = 12944; // 1
+const static uint64_t SH_FLD_TCE_CACHE_DISABLE = 12945; // 1
+const static uint64_t SH_FLD_TCK_WIDTH = 12946; // 1
+const static uint64_t SH_FLD_TCK_WIDTH_LEN = 12947; // 1
+const static uint64_t SH_FLD_TCPERV_OCC_PIB_FENCE_DC = 12948; // 1
+const static uint64_t SH_FLD_TC_AMUX_CTRL_DC = 12949; // 43
+const static uint64_t SH_FLD_TC_AMUX_CTRL_DC_LEN = 12950; // 43
+const static uint64_t SH_FLD_TC_BSC_EXTMODE_DC = 12951; // 43
+const static uint64_t SH_FLD_TC_BSC_INTMODE_DC = 12952; // 43
+const static uint64_t SH_FLD_TC_BSC_INV_DC = 12953; // 43
+const static uint64_t SH_FLD_TC_BSC_WRAPSEL_DC = 12954; // 43
+const static uint64_t SH_FLD_TC_DIAG_PORT0_OUT = 12955; // 43
+const static uint64_t SH_FLD_TC_DIAG_PORT1_OUT = 12956; // 43
+const static uint64_t SH_FLD_TC_DPLL_SS_ENABLE_DC = 12957; // 24
+const static uint64_t SH_FLD_TC_EDRAM_ABIST_MODE_DC = 12958; // 43
+const static uint64_t SH_FLD_TC_FENCE0 = 12959; // 43
+const static uint64_t SH_FLD_TC_FENCE1 = 12960; // 43
+const static uint64_t SH_FLD_TC_FENCE2 = 12961; // 43
+const static uint64_t SH_FLD_TC_FUNCTIONAL_FENCE_0 = 12962; // 30
+const static uint64_t SH_FLD_TC_FUNCTIONAL_FENCE_1 = 12963; // 42
+const static uint64_t SH_FLD_TC_FUNCTIONAL_FENCE_10 = 12964; // 43
+const static uint64_t SH_FLD_TC_FUNCTIONAL_FENCE_11 = 12965; // 43
+const static uint64_t SH_FLD_TC_FUNCTIONAL_FENCE_12 = 12966; // 43
+const static uint64_t SH_FLD_TC_FUNCTIONAL_FENCE_13 = 12967; // 43
+const static uint64_t SH_FLD_TC_FUNCTIONAL_FENCE_14 = 12968; // 43
+const static uint64_t SH_FLD_TC_FUNCTIONAL_FENCE_2 = 12969; // 42
+const static uint64_t SH_FLD_TC_FUNCTIONAL_FENCE_3 = 12970; // 43
+const static uint64_t SH_FLD_TC_FUNCTIONAL_FENCE_4 = 12971; // 43
+const static uint64_t SH_FLD_TC_FUNCTIONAL_FENCE_5 = 12972; // 43
+const static uint64_t SH_FLD_TC_FUNCTIONAL_FENCE_6 = 12973; // 43
+const static uint64_t SH_FLD_TC_FUNCTIONAL_FENCE_7 = 12974; // 43
+const static uint64_t SH_FLD_TC_FUNCTIONAL_FENCE_8 = 12975; // 43
+const static uint64_t SH_FLD_TC_FUNCTIONAL_FENCE_9 = 12976; // 43
+const static uint64_t SH_FLD_TC_IOBIST_MODE_DC = 12977; // 43
+const static uint64_t SH_FLD_TC_IOM_DPHY01_PLL_RESET_N = 12978; // 2
+const static uint64_t SH_FLD_TC_IOM_DPHY23_PLL_RESET_N = 12979; // 2
+const static uint64_t SH_FLD_TC_IOP_HSSPCLKOUTEN = 12980; // 3
+const static uint64_t SH_FLD_TC_IOP_HSSPORWREN = 12981; // 3
+const static uint64_t SH_FLD_TC_IOP_SYS_RESET_PCS = 12982; // 3
+const static uint64_t SH_FLD_TC_IOP_SYS_RESET_PMA = 12983; // 3
+const static uint64_t SH_FLD_TC_L3_FENCE_EDRAM = 12984; // 6
+const static uint64_t SH_FLD_TC_MC_FENCE_DC_N = 12985; // 2
+const static uint64_t SH_FLD_TC_NBTI_ACDC_STRESS_SELECT_DC = 12986; // 43
+const static uint64_t SH_FLD_TC_NBTI_HDR_ENABLE_OVR_DC = 12987; // 43
+const static uint64_t SH_FLD_TC_OB_RATIO_DC = 12988; // 2
+const static uint64_t SH_FLD_TC_OB_RATIO_DC_LEN = 12989; // 2
+const static uint64_t SH_FLD_TC_OELCC_ALIGN_FLUSH_DC = 12990; // 43
+const static uint64_t SH_FLD_TC_OELCC_EDGE_DELAYED_DC = 12991; // 43
+const static uint64_t SH_FLD_TC_PBE0_IOVALID_DC = 12992; // 1
+const static uint64_t SH_FLD_TC_PBE1_IOVALID_DC = 12993; // 1
+const static uint64_t SH_FLD_TC_PBE2_IOVALID_DC = 12994; // 1
+const static uint64_t SH_FLD_TC_PBE3_IOVALID_DC = 12995; // 1
+const static uint64_t SH_FLD_TC_PBE4_IOVALID_DC = 12996; // 1
+const static uint64_t SH_FLD_TC_PBE5_IOVALID_DC = 12997; // 1
+const static uint64_t SH_FLD_TC_PBIOO0_IOVALID = 12998; // 2
+const static uint64_t SH_FLD_TC_PBIOO1_IOVALID = 12999; // 2
+const static uint64_t SH_FLD_TC_PCI0_FENCE_EN_DC = 13000; // 1
+const static uint64_t SH_FLD_TC_PCI0_IOVALID = 13001; // 1
+const static uint64_t SH_FLD_TC_PCI0_LANE_CFG_DC = 13002; // 1
+const static uint64_t SH_FLD_TC_PCI0_LANE_CFG_DC_LEN = 13003; // 1
+const static uint64_t SH_FLD_TC_PCI0_RATIO_DC = 13004; // 1
+const static uint64_t SH_FLD_TC_PCI0_RATIO_DC_LEN = 13005; // 1
+const static uint64_t SH_FLD_TC_PCI0_RATIO_OVERRIDE = 13006; // 1
+const static uint64_t SH_FLD_TC_PCI0_SWAP_DC = 13007; // 1
+const static uint64_t SH_FLD_TC_PCI1X_IOVALID = 13008; // 1
+const static uint64_t SH_FLD_TC_PCI1X_IOVALID_LEN = 13009; // 1
+const static uint64_t SH_FLD_TC_PCI1_FENCE_EN_DC = 13010; // 1
+const static uint64_t SH_FLD_TC_PCI1_LANE_CFG_DC = 13011; // 1
+const static uint64_t SH_FLD_TC_PCI1_LANE_CFG_DC_LEN = 13012; // 1
+const static uint64_t SH_FLD_TC_PCI1_PIPE1_RATIO_DC = 13013; // 1
+const static uint64_t SH_FLD_TC_PCI1_PIPE1_RATIO_DC_LEN = 13014; // 1
+const static uint64_t SH_FLD_TC_PCI1_PIPE2_RATIO_DC = 13015; // 1
+const static uint64_t SH_FLD_TC_PCI1_PIPE2_RATIO_DC_LEN = 13016; // 1
+const static uint64_t SH_FLD_TC_PCI1_RATIO_OVERRIDE = 13017; // 1
+const static uint64_t SH_FLD_TC_PCI1_RATIO_OVERRIDE_LEN = 13018; // 1
+const static uint64_t SH_FLD_TC_PCI1_SWAP_DC = 13019; // 1
+const static uint64_t SH_FLD_TC_PCI1_SWAP_DC_LEN = 13020; // 1
+const static uint64_t SH_FLD_TC_PCI2_FENCE_EN_DC = 13021; // 1
+const static uint64_t SH_FLD_TC_PCI2_IOVALID = 13022; // 1
+const static uint64_t SH_FLD_TC_PCI2_IOVALID_LEN = 13023; // 1
+const static uint64_t SH_FLD_TC_PCI2_LANE_CFG_DC = 13024; // 1
+const static uint64_t SH_FLD_TC_PCI2_LANE_CFG_DC_LEN = 13025; // 1
+const static uint64_t SH_FLD_TC_PCI2_PIPE1_RATIO_DC = 13026; // 1
+const static uint64_t SH_FLD_TC_PCI2_PIPE1_RATIO_DC_LEN = 13027; // 1
+const static uint64_t SH_FLD_TC_PCI2_PIPE2_RATIO_DC = 13028; // 1
+const static uint64_t SH_FLD_TC_PCI2_PIPE2_RATIO_DC_LEN = 13029; // 1
+const static uint64_t SH_FLD_TC_PCI2_PIPE3_RATIO_DC = 13030; // 1
+const static uint64_t SH_FLD_TC_PCI2_PIPE3_RATIO_DC_LEN = 13031; // 1
+const static uint64_t SH_FLD_TC_PCI2_RATIO_OVERRIDE = 13032; // 1
+const static uint64_t SH_FLD_TC_PCI2_RATIO_OVERRIDE_LEN = 13033; // 1
+const static uint64_t SH_FLD_TC_PCI2_SWAP_DC = 13034; // 1
+const static uint64_t SH_FLD_TC_PCI2_SWAP_DC_LEN = 13035; // 1
+const static uint64_t SH_FLD_TC_PCIS0_FENCE_EN_DC = 13036; // 1
+const static uint64_t SH_FLD_TC_PCIS1_FENCE_EN_DC = 13037; // 1
+const static uint64_t SH_FLD_TC_PCIS2_FENCE_EN_DC = 13038; // 1
+const static uint64_t SH_FLD_TC_PERV_FENCE_DC = 13039; // 43
+const static uint64_t SH_FLD_TC_PSI_IOVALID_DC = 13040; // 1
+const static uint64_t SH_FLD_TC_PSRO_SEL_DC = 13041; // 43
+const static uint64_t SH_FLD_TC_PSRO_SEL_DC_LEN = 13042; // 43
+const static uint64_t SH_FLD_TC_REFCLK_DRVR_EN_DC = 13043; // 43
+const static uint64_t SH_FLD_TC_REGION10_FENCE_DC = 13044; // 19
+const static uint64_t SH_FLD_TC_REGION1_FENCE_DC = 13045; // 19
+const static uint64_t SH_FLD_TC_REGION2_FENCE_DC = 13046; // 19
+const static uint64_t SH_FLD_TC_REGION3_FENCE_DC = 13047; // 19
+const static uint64_t SH_FLD_TC_REGION4_FENCE_DC = 13048; // 19
+const static uint64_t SH_FLD_TC_REGION5_FENCE_DC = 13049; // 19
+const static uint64_t SH_FLD_TC_REGION6_FENCE_DC = 13050; // 19
+const static uint64_t SH_FLD_TC_REGION7_FENCE_DC = 13051; // 19
+const static uint64_t SH_FLD_TC_REGION8_FENCE_DC = 13052; // 19
+const static uint64_t SH_FLD_TC_REGION9_FENCE_DC = 13053; // 19
+const static uint64_t SH_FLD_TC_REGION_FENCE_DC = 13054; // 24
+const static uint64_t SH_FLD_TC_REGION_FENCE_DC_LEN = 13055; // 24
+const static uint64_t SH_FLD_TC_SKIT_MODE_BIST_DC = 13056; // 43
+const static uint64_t SH_FLD_TC_SRAM_ABIST_MODE_DC = 13057; // 43
+const static uint64_t SH_FLD_TC_START_TEST_DC = 13058; // 43
+const static uint64_t SH_FLD_TC_UNIT_ARY_WRT_THRU_DC = 13059; // 43
+const static uint64_t SH_FLD_TC_UNIT_AVP_MODE = 13060; // 19
+const static uint64_t SH_FLD_TC_UNIT_CHIP_ID_DC = 13061; // 43
+const static uint64_t SH_FLD_TC_UNIT_CHIP_ID_DC_LEN = 13062; // 43
+const static uint64_t SH_FLD_TC_UNIT_CONSTRAIN_SAFESCAN_DC = 13063; // 43
+const static uint64_t SH_FLD_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC = 13064; // 43
+const static uint64_t SH_FLD_TC_UNIT_GROUP_ID_DC = 13065; // 43
+const static uint64_t SH_FLD_TC_UNIT_GROUP_ID_DC_LEN = 13066; // 43
+const static uint64_t SH_FLD_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC = 13067; // 43
+const static uint64_t SH_FLD_TC_UNIT_MULTICYCLE_TEST_FENCE_DC = 13068; // 43
+const static uint64_t SH_FLD_TC_UNIT_RRFA_TEST_ENABLE_DC = 13069; // 43
+const static uint64_t SH_FLD_TC_UNIT_SYNCCLK_MUXSEL_DC = 13070; // 43
+const static uint64_t SH_FLD_TC_UNIT_SYS_ID_DC = 13071; // 43
+const static uint64_t SH_FLD_TC_UNIT_SYS_ID_DC_LEN = 13072; // 43
+const static uint64_t SH_FLD_TC_VITL_FENCE_DC = 13073; // 43
+const static uint64_t SH_FLD_TDR_DAC_CNTL = 13074; // 4
+const static uint64_t SH_FLD_TDR_DAC_CNTL_LEN = 13075; // 4
+const static uint64_t SH_FLD_TDR_PHASE_SEL = 13076; // 4
+const static uint64_t SH_FLD_TDR_PULSE_OFFSET = 13077; // 4
+const static uint64_t SH_FLD_TDR_PULSE_OFFSET_LEN = 13078; // 4
+const static uint64_t SH_FLD_TDR_PULSE_WIDTH = 13079; // 4
+const static uint64_t SH_FLD_TDR_PULSE_WIDTH_LEN = 13080; // 4
+const static uint64_t SH_FLD_TER = 13081; // 8
+const static uint64_t SH_FLD_TERM_ENC = 13082; // 1
+const static uint64_t SH_FLD_TERM_ENC_LEN = 13083; // 1
+const static uint64_t SH_FLD_TERM_TEST = 13084; // 1
+const static uint64_t SH_FLD_TER_LEN = 13085; // 8
+const static uint64_t SH_FLD_TER_V = 13086; // 8
+const static uint64_t SH_FLD_TEST_ENABLE = 13087; // 43
+const static uint64_t SH_FLD_TFAC_ERR = 13088; // 96
+const static uint64_t SH_FLD_TFMR_PARITY_ERR = 13089; // 96
+const static uint64_t SH_FLD_TGT_NODAL_DINC_ERR = 13090; // 12
+const static uint64_t SH_FLD_TGT_NODAL_REQ_DINC_ERR = 13091; // 12
+const static uint64_t SH_FLD_THERM_MODE = 13092; // 43
+const static uint64_t SH_FLD_THERM_MODEREG_PARITY_MASK = 13093; // 43
+const static uint64_t SH_FLD_THERM_MODE_LEN = 13094; // 43
+const static uint64_t SH_FLD_THERM_TRIP = 13095; // 43
+const static uint64_t SH_FLD_THERM_TRIP_LEN = 13096; // 43
+const static uint64_t SH_FLD_THRDID = 13097; // 4
+const static uint64_t SH_FLD_THRDID_LEN = 13098; // 4
+const static uint64_t SH_FLD_THREEPHAS = 13099; // 3
+const static uint64_t SH_FLD_THRESHOLD = 13100; // 1
+const static uint64_t SH_FLD_THRES_ENA = 13101; // 43
+const static uint64_t SH_FLD_THRES_ENA_LEN = 13102; // 43
+const static uint64_t SH_FLD_THRES_OVERFLOW_MASK = 13103; // 43
+const static uint64_t SH_FLD_THRES_STATE_MASK = 13104; // 43
+const static uint64_t SH_FLD_THRES_TRIP_ENA = 13105; // 43
+const static uint64_t SH_FLD_THRES_TRIP_ENA_LEN = 13106; // 43
+const static uint64_t SH_FLD_THRID = 13107; // 1
+const static uint64_t SH_FLD_THRID_LEN = 13108; // 1
+const static uint64_t SH_FLD_THR_ID = 13109; // 1
+const static uint64_t SH_FLD_THR_ID_LEN = 13110; // 1
+const static uint64_t SH_FLD_TID = 13111; // 8
+const static uint64_t SH_FLD_TID_LEN = 13112; // 8
+const static uint64_t SH_FLD_TIER0_VALUE = 13113; // 12
+const static uint64_t SH_FLD_TIER0_VALUE_LEN = 13114; // 12
+const static uint64_t SH_FLD_TIER1_VALUE = 13115; // 24
+const static uint64_t SH_FLD_TIER1_VALUE_LEN = 13116; // 24
+const static uint64_t SH_FLD_TIER2_VALUE = 13117; // 24
+const static uint64_t SH_FLD_TIER2_VALUE_LEN = 13118; // 24
+const static uint64_t SH_FLD_TIME = 13119; // 43
+const static uint64_t SH_FLD_TIMEBASE = 13120; // 330
+const static uint64_t SH_FLD_TIMEBASE_BURST_SEL = 13121; // 2
+const static uint64_t SH_FLD_TIMEBASE_ENABLE = 13122; // 1
+const static uint64_t SH_FLD_TIMEBASE_INTERVAL = 13123; // 2
+const static uint64_t SH_FLD_TIMEBASE_INTERVAL_LEN = 13124; // 2
+const static uint64_t SH_FLD_TIMEBASE_LEN = 13125; // 330
+const static uint64_t SH_FLD_TIMEBASE_SEL = 13126; // 2
+const static uint64_t SH_FLD_TIMEBASE_SEL_LEN = 13127; // 2
+const static uint64_t SH_FLD_TIMEFAC_ERROR_INJ = 13128; // 24
+const static uint64_t SH_FLD_TIMEFAC_ERROR_INJ_LEN = 13129; // 24
+const static uint64_t SH_FLD_TIMEOUT_ACTIVE = 13130; // 2
+const static uint64_t SH_FLD_TIMEOUT_EN = 13131; // 1
+const static uint64_t SH_FLD_TIMEOUT_MASK = 13132; // 43
+const static uint64_t SH_FLD_TIMEOUT_N = 13133; // 2
+const static uint64_t SH_FLD_TIMEOUT_PARITY = 13134; // 43
+const static uint64_t SH_FLD_TIMEOUT_SEL = 13135; // 3
+const static uint64_t SH_FLD_TIMEOUT_SEL_LEN = 13136; // 3
+const static uint64_t SH_FLD_TIMEOUT_VALUE = 13137; // 1
+const static uint64_t SH_FLD_TIMEOUT_VALUE_LEN = 13138; // 1
+const static uint64_t SH_FLD_TIMER = 13139; // 4
+const static uint64_t SH_FLD_TIMER_ENABLE = 13140; // 4
+const static uint64_t SH_FLD_TIMER_EXPIRED_RECOV_ERROR = 13141; // 4
+const static uint64_t SH_FLD_TIMER_EXPIRED_XSTOP_ERROR = 13142; // 4
+const static uint64_t SH_FLD_TIMER_LEN = 13143; // 4
+const static uint64_t SH_FLD_TIMER_N = 13144; // 2
+const static uint64_t SH_FLD_TIMER_N_LEN = 13145; // 2
+const static uint64_t SH_FLD_TIMER_PERIOD_MASK = 13146; // 4
+const static uint64_t SH_FLD_TIMER_PERIOD_MASK_LEN = 13147; // 4
+const static uint64_t SH_FLD_TIMESTAMP_COUNTER_OVERFLOW_ERR = 13148; // 43
+const static uint64_t SH_FLD_TIMESTAMP_COUNTER_VALUE = 13149; // 43
+const static uint64_t SH_FLD_TIMESTAMP_COUNTER_VALUE_LEN = 13150; // 43
+const static uint64_t SH_FLD_TIME_BASE_ERR = 13151; // 4
+const static uint64_t SH_FLD_TLBIE_CNT_THRESH = 13152; // 13
+const static uint64_t SH_FLD_TLBIE_CNT_THRESH_LEN = 13153; // 13
+const static uint64_t SH_FLD_TLBIE_CNT_WT4TX_CORE_EN = 13154; // 12
+const static uint64_t SH_FLD_TLBIE_CONTROL_ERR = 13155; // 24
+const static uint64_t SH_FLD_TLBIE_DEC_RATE = 13156; // 13
+const static uint64_t SH_FLD_TLBIE_DEC_RATE_LEN = 13157; // 13
+const static uint64_t SH_FLD_TLBIE_INC_RATE = 13158; // 13
+const static uint64_t SH_FLD_TLBIE_INC_RATE_LEN = 13159; // 13
+const static uint64_t SH_FLD_TLBIE_MASTER_TIMEOUT = 13160; // 24
+const static uint64_t SH_FLD_TLBIE_PACING_CNT_EN = 13161; // 12
+const static uint64_t SH_FLD_TLBIE_SLBIEG_SW_ERR = 13162; // 12
+const static uint64_t SH_FLD_TLBIE_SNOOP_TIMEOUT = 13163; // 24
+const static uint64_t SH_FLD_TLBIE_STALL_CMPLT_CNT = 13164; // 14
+const static uint64_t SH_FLD_TLBIE_STALL_CMPLT_CNT_LEN = 13165; // 14
+const static uint64_t SH_FLD_TLBIE_STALL_DELAY_CNT = 13166; // 14
+const static uint64_t SH_FLD_TLBIE_STALL_DELAY_CNT_LEN = 13167; // 14
+const static uint64_t SH_FLD_TLBIE_STALL_EN = 13168; // 14
+const static uint64_t SH_FLD_TLBIE_STALL_THRESHOLD = 13169; // 14
+const static uint64_t SH_FLD_TLBIE_STALL_THRESHOLD_LEN = 13170; // 14
+const static uint64_t SH_FLD_TLBIE_SW_ERR = 13171; // 12
+const static uint64_t SH_FLD_TLBI_BAD_OP_ERR = 13172; // 4
+const static uint64_t SH_FLD_TLBI_DATA_POLL_PULSE_DIV = 13173; // 2
+const static uint64_t SH_FLD_TLBI_DATA_POLL_PULSE_DIV_LEN = 13174; // 2
+const static uint64_t SH_FLD_TLBI_FENCE = 13175; // 2
+const static uint64_t SH_FLD_TLBI_GROUP_PUMP_EN = 13176; // 12
+const static uint64_t SH_FLD_TLBI_PSL_DEAD = 13177; // 2
+const static uint64_t SH_FLD_TLBI_SEQ_ERR = 13178; // 4
+const static uint64_t SH_FLD_TLBI_SEQ_NUM_PARITY_ERR = 13179; // 4
+const static uint64_t SH_FLD_TLBI_TIMEOUT = 13180; // 4
+const static uint64_t SH_FLD_TLB_CHK_WAIT_DEC = 13181; // 12
+const static uint64_t SH_FLD_TLB_CHK_WAIT_DEC_LEN = 13182; // 12
+const static uint64_t SH_FLD_TLB_SNOOP_DATA_POLL_PULSE_DIV = 13183; // 12
+const static uint64_t SH_FLD_TLB_SNOOP_DATA_POLL_PULSE_DIV_LEN = 13184; // 12
+const static uint64_t SH_FLD_TLB_STG1_HANG_POLL_PULSE_DIV = 13185; // 12
+const static uint64_t SH_FLD_TLB_STG1_HANG_POLL_PULSE_DIV_LEN = 13186; // 12
+const static uint64_t SH_FLD_TLB_STG2_HANG_POLL_PULSE_DIV = 13187; // 12
+const static uint64_t SH_FLD_TLB_STG2_HANG_POLL_PULSE_DIV_LEN = 13188; // 12
+const static uint64_t SH_FLD_TMOD_CYCLES = 13189; // 8
+const static uint64_t SH_FLD_TMOD_CYCLES_LEN = 13190; // 8
+const static uint64_t SH_FLD_TMRSC_CYCLES = 13191; // 8
+const static uint64_t SH_FLD_TMRSC_CYCLES_LEN = 13192; // 8
+const static uint64_t SH_FLD_TMR_PE = 13193; // 8
+const static uint64_t SH_FLD_TM_CAM_ERR = 13194; // 12
+const static uint64_t SH_FLD_TM_CAM_ERR_LEN = 13195; // 12
+const static uint64_t SH_FLD_TODTLON_OFF_CYCLES = 13196; // 8
+const static uint64_t SH_FLD_TODTLON_OFF_CYCLES_LEN = 13197; // 8
+const static uint64_t SH_FLD_TOD_CMD_OVERRUN = 13198; // 1
+const static uint64_t SH_FLD_TOD_CNTR_REF = 13199; // 1
+const static uint64_t SH_FLD_TOD_CNTR_REF_LEN = 13200; // 1
+const static uint64_t SH_FLD_TOD_HANG_ERR = 13201; // 1
+const static uint64_t SH_FLD_TOO_MANY_BUS_ERRORS = 13202; // 8
+const static uint64_t SH_FLD_TOTAL_FREE_BUF_COUNT = 13203; // 1
+const static uint64_t SH_FLD_TOTAL_FREE_BUF_COUNT_LEN = 13204; // 1
+const static uint64_t SH_FLD_TOTAL_GAP_COUNTS = 13205; // 8
+const static uint64_t SH_FLD_TOTAL_GAP_COUNTS_LEN = 13206; // 8
+const static uint64_t SH_FLD_TPCFSI_OPB_SW0_FENCE_DC = 13207; // 1
+const static uint64_t SH_FLD_TPCFSI_OPB_SW0_FENCE_DC_LEN = 13208; // 1
+const static uint64_t SH_FLD_TPCFSI_OPB_SW1_FENCE_DC = 13209; // 1
+const static uint64_t SH_FLD_TPCFSI_OPB_SW1_FENCE_DC_LEN = 13210; // 1
+const static uint64_t SH_FLD_TPCFSI_OPB_SW_RESET_DC = 13211; // 1
+const static uint64_t SH_FLD_TPFSI_ALTREFCLK_SE1 = 13212; // 1
+const static uint64_t SH_FLD_TPFSI_ALTREFCLK_SEL = 13213; // 1
+const static uint64_t SH_FLD_TPFSI_ARRAY_SET_VBL_TO_VDD_DC = 13214; // 1
+const static uint64_t SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC = 13215; // 1
+const static uint64_t SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC_LEN = 13216; // 1
+const static uint64_t SH_FLD_TPFSI_OSCSW0_PGOOD_N = 13217; // 1
+const static uint64_t SH_FLD_TPFSI_OSCSW1_PGOOD = 13218; // 1
+const static uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ0_DC = 13219; // 1
+const static uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ0_DC_LEN = 13220; // 1
+const static uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ1_DC = 13221; // 1
+const static uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ1_DC_LEN = 13222; // 1
+const static uint64_t SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC = 13223; // 1
+const static uint64_t SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC_LEN = 13224; // 1
+const static uint64_t SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC = 13225; // 1
+const static uint64_t SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC_LEN = 13226; // 1
+const static uint64_t SH_FLD_TPFSI_OSCSW_TWEAK_DC = 13227; // 1
+const static uint64_t SH_FLD_TPFSI_OSCSW_TWEAK_DC_LEN = 13228; // 1
+const static uint64_t SH_FLD_TPFSI_SBE_FENCE_VTLIO_DC = 13229; // 1
+const static uint64_t SH_FLD_TPFSI_TPI2C_BUS_FENCE_DC = 13230; // 1
+const static uint64_t SH_FLD_TPFSI_TP_FENCE_VTLIO_DC = 13231; // 1
+const static uint64_t SH_FLD_TPFSI_TP_LOWFREQTEST_REFCLK_DC = 13232; // 1
+const static uint64_t SH_FLD_TPFSI_TP_PFET_FORCE_OFF_DC = 13233; // 1
+const static uint64_t SH_FLD_TPFSI_TP_PFET_OVERRIDE_ON_DC_N = 13234; // 1
+const static uint64_t SH_FLD_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC = 13235; // 1
+const static uint64_t SH_FLD_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC = 13236; // 1
+const static uint64_t SH_FLD_TPFSI_TP_VSB_DBG_PCB_TYPE_PAR_DIS_DC = 13237; // 1
+const static uint64_t SH_FLD_TPFSI_TP_VSB_PCB_GSD_LATCHED_MODE_DC = 13238; // 1
+const static uint64_t SH_FLD_TP_ARRAY_WRITE_ASSIST_EN_DC = 13239; // 1
+const static uint64_t SH_FLD_TP_CHIPLET_EN_DC = 13240; // 1
+const static uint64_t SH_FLD_TP_CLK_ASYNC_RESET_DC = 13241; // 1
+const static uint64_t SH_FLD_TP_CLK_DIV_BYPASS_EN_DC = 13242; // 1
+const static uint64_t SH_FLD_TP_CLK_PDLY_BYPASS1_EN_DC = 13243; // 1
+const static uint64_t SH_FLD_TP_CLK_PDLY_BYPASS2_EN_DC = 13244; // 1
+const static uint64_t SH_FLD_TP_CLK_PULSE_ENABLE_DC = 13245; // 1
+const static uint64_t SH_FLD_TP_CLK_PULSE_MODE_DC = 13246; // 1
+const static uint64_t SH_FLD_TP_CLK_PULSE_MODE_DC_LEN = 13247; // 1
+const static uint64_t SH_FLD_TP_CPM_CAL_SET = 13248; // 1
+const static uint64_t SH_FLD_TP_DI1_DC_B = 13249; // 1
+const static uint64_t SH_FLD_TP_DI1_DC_N = 13250; // 1
+const static uint64_t SH_FLD_TP_DI2_DC_B = 13251; // 1
+const static uint64_t SH_FLD_TP_DI2_DC_N = 13252; // 1
+const static uint64_t SH_FLD_TP_EDRAM_ENABLE_DC = 13253; // 1
+const static uint64_t SH_FLD_TP_EXSD_FULLSPEED_DC = 13254; // 1
+const static uint64_t SH_FLD_TP_EX_FUSE_FP_THROTTLE_EN_DC = 13255; // 1
+const static uint64_t SH_FLD_TP_EX_FUSE_VMX_CRYPTO_DIS_DC = 13256; // 1
+const static uint64_t SH_FLD_TP_FENCE_EN_DC = 13257; // 1
+const static uint64_t SH_FLD_TP_FENCE_PCB = 13258; // 43
+const static uint64_t SH_FLD_TP_FENCE_PCB_DC = 13259; // 1
+const static uint64_t SH_FLD_TP_FILTPLL_CP_ALT_BYPASS_DC = 13260; // 1
+const static uint64_t SH_FLD_TP_FILTPLL_IO_ALT_BYPASS_DC = 13261; // 1
+const static uint64_t SH_FLD_TP_FILTPLL_PLL_BYPASS1_DC = 13262; // 1
+const static uint64_t SH_FLD_TP_FILTPLL_PLL_RESET1_DC = 13263; // 1
+const static uint64_t SH_FLD_TP_FLUSH_ALIGN_OVERWRITE = 13264; // 1
+const static uint64_t SH_FLD_TP_FLUSH_SCAN_DC_N = 13265; // 1
+const static uint64_t SH_FLD_TP_FSI_CLKIN_SEL_DC = 13266; // 1
+const static uint64_t SH_FLD_TP_FSI_PROBE_SEL_DC = 13267; // 1
+const static uint64_t SH_FLD_TP_FSI_PROBE_SEL_DC_LEN = 13268; // 1
+const static uint64_t SH_FLD_TP_GLBCK_MEM_TESTCLK_SEL_DC = 13269; // 1
+const static uint64_t SH_FLD_TP_GLBCK_VSB_NEST_VREGDLY_SHUTOFF_DC = 13270; // 1
+const static uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC = 13271; // 1
+const static uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC_LEN = 13272; // 1
+const static uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC = 13273; // 1
+const static uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC_LEN = 13274; // 1
+const static uint64_t SH_FLD_TP_GPIO_PIB_TIMEOUT = 13275; // 1
+const static uint64_t SH_FLD_TP_GPIO_PIB_TIMEOUT_LEN = 13276; // 1
+const static uint64_t SH_FLD_TP_IDDQ_DC = 13277; // 1
+const static uint64_t SH_FLD_TP_LVLTRANS_FENCE_DC = 13278; // 1
+const static uint64_t SH_FLD_TP_NX_ALLOW_CRYPTO_DC = 13279; // 1
+const static uint64_t SH_FLD_TP_OSCSWITCH_VSB = 13280; // 1
+const static uint64_t SH_FLD_TP_OSCSWITCH_VSB_LEN = 13281; // 1
+const static uint64_t SH_FLD_TP_PCB_EP_RESET_DC = 13282; // 1
+const static uint64_t SH_FLD_TP_PCB_PM_MUX_SEL_DC = 13283; // 1
+const static uint64_t SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC = 13284; // 1
+const static uint64_t SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC_LEN = 13285; // 1
+const static uint64_t SH_FLD_TP_PIB_TRACE_MODE_DATA_DC = 13286; // 44
+const static uint64_t SH_FLD_TP_PIB_TRACE_MUX_SEL = 13287; // 1
+const static uint64_t SH_FLD_TP_PIB_TRACE_MUX_SEL_LEN = 13288; // 1
+const static uint64_t SH_FLD_TP_PIB_VSB_DISABLE_PARITY_DC = 13289; // 1
+const static uint64_t SH_FLD_TP_PLLBYP_DC = 13290; // 1
+const static uint64_t SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC = 13291; // 1
+const static uint64_t SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC_LEN = 13292; // 1
+const static uint64_t SH_FLD_TP_PLLRST_DC = 13293; // 1
+const static uint64_t SH_FLD_TP_PLL_CLKIN_SEL1_DC = 13294; // 1
+const static uint64_t SH_FLD_TP_PLL_CLKIN_SEL2_DC = 13295; // 1
+const static uint64_t SH_FLD_TP_PLL_CLKIN_SEL3_DC = 13296; // 1
+const static uint64_t SH_FLD_TP_PLL_CLKIN_SEL4_DC = 13297; // 1
+const static uint64_t SH_FLD_TP_PLL_FORCE_OUT_EN_DC = 13298; // 1
+const static uint64_t SH_FLD_TP_PLL_TEST_ENABLE_DC = 13299; // 1
+const static uint64_t SH_FLD_TP_PLL_TEST_EN_DC = 13300; // 1
+const static uint64_t SH_FLD_TP_PROBE0_SEL_DC = 13301; // 1
+const static uint64_t SH_FLD_TP_PROBE0_SEL_DC_LEN = 13302; // 1
+const static uint64_t SH_FLD_TP_PROBE1_SEL_DC = 13303; // 1
+const static uint64_t SH_FLD_TP_PROBE1_SEL_DC_LEN = 13304; // 1
+const static uint64_t SH_FLD_TP_PROBE_DRV_EN_DC = 13305; // 1
+const static uint64_t SH_FLD_TP_PROBE_HIGHDRIVE_DC = 13306; // 1
+const static uint64_t SH_FLD_TP_PROBE_MESH_SEL_DC = 13307; // 1
+const static uint64_t SH_FLD_TP_RESCLK_DIS_DC = 13308; // 1
+const static uint64_t SH_FLD_TP_RI_DC_B = 13309; // 1
+const static uint64_t SH_FLD_TP_RI_DC_N = 13310; // 1
+const static uint64_t SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC = 13311; // 1
+const static uint64_t SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC_LEN = 13312; // 1
+const static uint64_t SH_FLD_TP_SSPLL_PLL_BYPASS0_DC = 13313; // 1
+const static uint64_t SH_FLD_TP_SSPLL_PLL_RESET0_DC = 13314; // 1
+const static uint64_t SH_FLD_TP_TANKPLL_TEST_PLL_BYPASS2_DC = 13315; // 1
+const static uint64_t SH_FLD_TP_TEST_BURNIN_MODE_DC = 13316; // 1
+const static uint64_t SH_FLD_TP_TPFSI_ACK = 13317; // 43
+const static uint64_t SH_FLD_TP_VCS_PFET_ENABLE_ACTUAL = 13318; // 30
+const static uint64_t SH_FLD_TP_VCS_PFET_ENABLE_ACTUAL_LEN = 13319; // 30
+const static uint64_t SH_FLD_TP_VDD_PFET_ENABLE_ACTUAL = 13320; // 30
+const static uint64_t SH_FLD_TP_VDD_PFET_ENABLE_ACTUAL_LEN = 13321; // 30
+const static uint64_t SH_FLD_TP_VITL_ACT_DIS_DC = 13322; // 1
+const static uint64_t SH_FLD_TP_VITL_CLKOFF_DC = 13323; // 1
+const static uint64_t SH_FLD_TP_VITL_DELAY_LCLKR_DC = 13324; // 1
+const static uint64_t SH_FLD_TP_VITL_MPW1_DC_N = 13325; // 1
+const static uint64_t SH_FLD_TP_VITL_MPW2_DC_N = 13326; // 1
+const static uint64_t SH_FLD_TP_VITL_MPW3_DC_N = 13327; // 1
+const static uint64_t SH_FLD_TP_VITL_SCAN_CLK_DC = 13328; // 1
+const static uint64_t SH_FLD_TP_VITL_SCIN_DC = 13329; // 1
+const static uint64_t SH_FLD_TRACE_BUS_BITS_64_87 = 13330; // 1
+const static uint64_t SH_FLD_TRACE_BUS_BITS_64_87_LEN = 13331; // 1
+const static uint64_t SH_FLD_TRACE_BUS_EN = 13332; // 1
+const static uint64_t SH_FLD_TRACE_BUS_SEL_0_1 = 13333; // 1
+const static uint64_t SH_FLD_TRACE_BUS_SEL_0_1_LEN = 13334; // 1
+const static uint64_t SH_FLD_TRACE_BUS_TRIGGER_BITS = 13335; // 1
+const static uint64_t SH_FLD_TRACE_BUS_TRIGGER_BITS_LEN = 13336; // 1
+const static uint64_t SH_FLD_TRACE_DATA_SELECT = 13337; // 1
+const static uint64_t SH_FLD_TRACE_DATA_SELECT_LEN = 13338; // 1
+const static uint64_t SH_FLD_TRACE_DISABLE = 13339; // 1
+const static uint64_t SH_FLD_TRACE_ENABLE = 13340; // 6
+const static uint64_t SH_FLD_TRACE_EVENT = 13341; // 1
+const static uint64_t SH_FLD_TRACE_MUX_SEL = 13342; // 1
+const static uint64_t SH_FLD_TRACE_SEL = 13343; // 1
+const static uint64_t SH_FLD_TRACE_SELECT = 13344; // 2
+const static uint64_t SH_FLD_TRACE_SELECT_LEN = 13345; // 2
+const static uint64_t SH_FLD_TRACE_SEL_0_1 = 13346; // 1
+const static uint64_t SH_FLD_TRACE_SEL_0_1_LEN = 13347; // 1
+const static uint64_t SH_FLD_TRACE_SEL_LEN = 13348; // 1
+const static uint64_t SH_FLD_TRACE_TRIGGER = 13349; // 1
+const static uint64_t SH_FLD_TRACKING_TIMEOUT_SEL = 13350; // 6
+const static uint64_t SH_FLD_TRACKING_TIMEOUT_SEL_LEN = 13351; // 6
+const static uint64_t SH_FLD_TRANSPORT_INFORMATIONAL_ERR = 13352; // 4
+const static uint64_t SH_FLD_TRASH_EN = 13353; // 12
+const static uint64_t SH_FLD_TRCD_CYCLES = 13354; // 8
+const static uint64_t SH_FLD_TRCD_CYCLES_LEN = 13355; // 8
+const static uint64_t SH_FLD_TRC_CMD_OVERRUN = 13356; // 1
+const static uint64_t SH_FLD_TRC_CYCLES = 13357; // 8
+const static uint64_t SH_FLD_TRC_CYCLES_LEN = 13358; // 8
+const static uint64_t SH_FLD_TRC_GRP = 13359; // 6
+const static uint64_t SH_FLD_TRC_GRP_LEN = 13360; // 6
+const static uint64_t SH_FLD_TRC_MODE = 13361; // 6
+const static uint64_t SH_FLD_TRC_MODE_LEN = 13362; // 6
+const static uint64_t SH_FLD_TRFC_CYCLES = 13363; // 8
+const static uint64_t SH_FLD_TRFC_CYCLES_LEN = 13364; // 8
+const static uint64_t SH_FLD_TRIG = 13365; // 17
+const static uint64_t SH_FLD_TRIG0_AND_MASK = 13366; // 90
+const static uint64_t SH_FLD_TRIG0_AND_MASK_LEN = 13367; // 90
+const static uint64_t SH_FLD_TRIG0_NOT_MODE = 13368; // 90
+const static uint64_t SH_FLD_TRIG0_OR_MASK = 13369; // 90
+const static uint64_t SH_FLD_TRIG0_OR_MASK_LEN = 13370; // 90
+const static uint64_t SH_FLD_TRIG1_AND_MASK = 13371; // 90
+const static uint64_t SH_FLD_TRIG1_AND_MASK_LEN = 13372; // 90
+const static uint64_t SH_FLD_TRIG1_NOT_MODE = 13373; // 90
+const static uint64_t SH_FLD_TRIG1_OR_MASK = 13374; // 90
+const static uint64_t SH_FLD_TRIG1_OR_MASK_LEN = 13375; // 90
+const static uint64_t SH_FLD_TRIGGER = 13376; // 31
+const static uint64_t SH_FLD_TRIGGER_OPCG_ON = 13377; // 129
+const static uint64_t SH_FLD_TRIG_FIR_HMI = 13378; // 96
+const static uint64_t SH_FLD_TRIG_OVERIDE = 13379; // 24
+const static uint64_t SH_FLD_TRP_CYCLES = 13380; // 8
+const static uint64_t SH_FLD_TRP_CYCLES_LEN = 13381; // 8
+const static uint64_t SH_FLD_TRRD = 13382; // 8
+const static uint64_t SH_FLD_TRRD_LEN = 13383; // 8
+const static uint64_t SH_FLD_TRRD_SBG = 13384; // 8
+const static uint64_t SH_FLD_TRRD_SBG_LEN = 13385; // 8
+const static uint64_t SH_FLD_TRST_B_EQ0_ERR = 13386; // 1
+const static uint64_t SH_FLD_TRUSTED_PRIORITY = 13387; // 1
+const static uint64_t SH_FLD_TRUSTED_PRIORITY_LEN = 13388; // 1
+const static uint64_t SH_FLD_TRUSTED_SERVER_NUMBER = 13389; // 1
+const static uint64_t SH_FLD_TRUSTED_SERVER_NUMBER_LEN = 13390; // 1
+const static uint64_t SH_FLD_TSIZE = 13391; // 1
+const static uint64_t SH_FLD_TSIZE_4_6 = 13392; // 1
+const static uint64_t SH_FLD_TSIZE_4_6_LEN = 13393; // 1
+const static uint64_t SH_FLD_TSIZE_MASK = 13394; // 8
+const static uint64_t SH_FLD_TSIZE_MASK_LEN = 13395; // 8
+const static uint64_t SH_FLD_TSIZE_MATCH = 13396; // 8
+const static uint64_t SH_FLD_TSIZE_MATCH_LEN = 13397; // 8
+const static uint64_t SH_FLD_TTAG_PARITY_ERROR = 13398; // 2
+const static uint64_t SH_FLD_TTYPE_MATCH = 13399; // 8
+const static uint64_t SH_FLD_TTYPE_MATCH_LEN = 13400; // 8
+const static uint64_t SH_FLD_TTYPE_REPLACE = 13401; // 8
+const static uint64_t SH_FLD_TTYPE_REPLACE_LEN = 13402; // 8
+const static uint64_t SH_FLD_TWLDQSEN_CYCLES = 13403; // 8
+const static uint64_t SH_FLD_TWLDQSEN_CYCLES_LEN = 13404; // 8
+const static uint64_t SH_FLD_TWLO_TWLOE = 13405; // 8
+const static uint64_t SH_FLD_TWLO_TWLOE_LEN = 13406; // 8
+const static uint64_t SH_FLD_TWO_CYCLE_ADDR_EN = 13407; // 8
+const static uint64_t SH_FLD_TWRMRD_CYCLES = 13408; // 8
+const static uint64_t SH_FLD_TWRMRD_CYCLES_LEN = 13409; // 8
+const static uint64_t SH_FLD_TWSM_DIS = 13410; // 1
+const static uint64_t SH_FLD_TWSM_DIS_LEN = 13411; // 1
+const static uint64_t SH_FLD_TXAERR = 13412; // 6
+const static uint64_t SH_FLD_TXBERR = 13413; // 6
+const static uint64_t SH_FLD_TXCERR = 13414; // 6
+const static uint64_t SH_FLD_TXDERR = 13415; // 6
+const static uint64_t SH_FLD_TXEERR = 13416; // 6
+const static uint64_t SH_FLD_TXFERR = 13417; // 6
+const static uint64_t SH_FLD_TXGERR = 13418; // 6
+const static uint64_t SH_FLD_TXHERR = 13419; // 6
+const static uint64_t SH_FLD_TXIERR = 13420; // 6
+const static uint64_t SH_FLD_TXJERR = 13421; // 6
+const static uint64_t SH_FLD_TXKERR = 13422; // 6
+const static uint64_t SH_FLD_TXLERR = 13423; // 6
+const static uint64_t SH_FLD_TXMERR = 13424; // 6
+const static uint64_t SH_FLD_TXNERR = 13425; // 6
+const static uint64_t SH_FLD_TXOERR = 13426; // 6
+const static uint64_t SH_FLD_TXPERR = 13427; // 6
+const static uint64_t SH_FLD_TX_BUS_WIDTH = 13428; // 4
+const static uint64_t SH_FLD_TX_BUS_WIDTH_LEN = 13429; // 4
+const static uint64_t SH_FLD_TX_DATA_ECC_CORR_ENA = 13430; // 6
+const static uint64_t SH_FLD_TX_ECC_DATA_POISON_ENA = 13431; // 6
+const static uint64_t SH_FLD_TX_SLS_DISABLE = 13432; // 4
+const static uint64_t SH_FLD_TX_TRISTATE_CNTL = 13433; // 8
+const static uint64_t SH_FLD_TX_TTYPE_PIB_MST_FSM_STATE_DISABLE = 13434; // 1
+const static uint64_t SH_FLD_TX_TTYPE_PIB_MST_IF_RESET = 13435; // 1
+const static uint64_t SH_FLD_TYPE = 13436; // 108
+const static uint64_t SH_FLD_TYPE_LEN = 13437; // 44
+const static uint64_t SH_FLD_TZQCS_CYCLES = 13438; // 8
+const static uint64_t SH_FLD_TZQCS_CYCLES_LEN = 13439; // 8
+const static uint64_t SH_FLD_TZQINIT_CYCLES = 13440; // 8
+const static uint64_t SH_FLD_TZQINIT_CYCLES_LEN = 13441; // 8
+const static uint64_t SH_FLD_UE1_0_OUT = 13442; // 4
+const static uint64_t SH_FLD_UE1_1_OUT = 13443; // 4
+const static uint64_t SH_FLD_UE1_2_OUT = 13444; // 4
+const static uint64_t SH_FLD_UE1_3_OUT = 13445; // 4
+const static uint64_t SH_FLD_UE1_4_OUT = 13446; // 4
+const static uint64_t SH_FLD_UE1_5_OUT = 13447; // 4
+const static uint64_t SH_FLD_UE1_6_OUT = 13448; // 4
+const static uint64_t SH_FLD_UE1_7_OUT = 13449; // 4
+const static uint64_t SH_FLD_UE2_0_OUT = 13450; // 4
+const static uint64_t SH_FLD_UE2_1_OUT = 13451; // 4
+const static uint64_t SH_FLD_UE2_2_OUT = 13452; // 4
+const static uint64_t SH_FLD_UE2_3_OUT = 13453; // 4
+const static uint64_t SH_FLD_UE2_4_OUT = 13454; // 4
+const static uint64_t SH_FLD_UE2_5_OUT = 13455; // 4
+const static uint64_t SH_FLD_UE2_6_OUT = 13456; // 4
+const static uint64_t SH_FLD_UE2_7_OUT = 13457; // 4
+const static uint64_t SH_FLD_UE_COUNT = 13458; // 2
+const static uint64_t SH_FLD_UE_COUNT_LEN = 13459; // 2
+const static uint64_t SH_FLD_UE_DISABLE = 13460; // 2
+const static uint64_t SH_FLD_UMAC_CRB_SUE = 13461; // 1
+const static uint64_t SH_FLD_UMAC_CRB_UE = 13462; // 1
+const static uint64_t SH_FLD_UMAC_LD_LINK_ERR = 13463; // 1
+const static uint64_t SH_FLD_UMAC_LINK_ABORT = 13464; // 1
+const static uint64_t SH_FLD_UMAC_RD_DISABLE_GROUP = 13465; // 1
+const static uint64_t SH_FLD_UMAC_RD_DISABLE_LN = 13466; // 1
+const static uint64_t SH_FLD_UMAC_RD_DISABLE_NN_RN = 13467; // 1
+const static uint64_t SH_FLD_UMAC_RD_DISABLE_VG_NOT_SYS = 13468; // 1
+const static uint64_t SH_FLD_UMAC_WC_INT_ADDR_UE = 13469; // 1
+const static uint64_t SH_FLD_UMAC_WR_DISABLE_GROUP = 13470; // 1
+const static uint64_t SH_FLD_UMAC_WR_DISABLE_LN = 13471; // 1
+const static uint64_t SH_FLD_UMAC_WR_DISABLE_NN_RN = 13472; // 1
+const static uint64_t SH_FLD_UMAC_WR_DISABLE_VG_NOT_SYS = 13473; // 1
+const static uint64_t SH_FLD_UNCORR_ERROR = 13474; // 1
+const static uint64_t SH_FLD_UNEXPECTEDCRESP = 13475; // 9
+const static uint64_t SH_FLD_UNEXPECTEDCRESP_MASK = 13476; // 9
+const static uint64_t SH_FLD_UNEXPECTED_PB = 13477; // 4
+const static uint64_t SH_FLD_UNEXPECT_DATA = 13478; // 1
+const static uint64_t SH_FLD_UNIT1 = 13479; // 215
+const static uint64_t SH_FLD_UNIT10 = 13480; // 215
+const static uint64_t SH_FLD_UNIT2 = 13481; // 215
+const static uint64_t SH_FLD_UNIT3 = 13482; // 215
+const static uint64_t SH_FLD_UNIT4 = 13483; // 215
+const static uint64_t SH_FLD_UNIT5 = 13484; // 215
+const static uint64_t SH_FLD_UNIT6 = 13485; // 215
+const static uint64_t SH_FLD_UNIT7 = 13486; // 215
+const static uint64_t SH_FLD_UNIT8 = 13487; // 215
+const static uint64_t SH_FLD_UNIT9 = 13488; // 215
+const static uint64_t SH_FLD_UNIT_REGION_CLKCMD_ENABLE = 13489; // 43
+const static uint64_t SH_FLD_UNLOAD_CLK_DISABLE = 13490; // 116
+const static uint64_t SH_FLD_UNLOAD_SEL = 13491; // 116
+const static uint64_t SH_FLD_UNLOAD_SEL_LEN = 13492; // 116
+const static uint64_t SH_FLD_UNSOLICITIEDPBDATA = 13493; // 9
+const static uint64_t SH_FLD_UNSOLICITIEDPBDATA_MASK = 13494; // 9
+const static uint64_t SH_FLD_UNTRUSTED = 13495; // 4
+const static uint64_t SH_FLD_UNTRUSTED_LEN = 13496; // 4
+const static uint64_t SH_FLD_UNUSED = 13497; // 130
+const static uint64_t SH_FLD_UNUSED0 = 13498; // 1
+const static uint64_t SH_FLD_UNUSED1 = 13499; // 45
+const static uint64_t SH_FLD_UNUSED1520 = 13500; // 43
+const static uint64_t SH_FLD_UNUSED1520_LEN = 13501; // 43
+const static uint64_t SH_FLD_UNUSED1_LEN = 13502; // 44
+const static uint64_t SH_FLD_UNUSED2 = 13503; // 47
+const static uint64_t SH_FLD_UNUSED23_63 = 13504; // 7
+const static uint64_t SH_FLD_UNUSED23_63_LEN = 13505; // 7
+const static uint64_t SH_FLD_UNUSED2_LEN = 13506; // 43
+const static uint64_t SH_FLD_UNUSED3 = 13507; // 46
+const static uint64_t SH_FLD_UNUSED4 = 13508; // 7
+const static uint64_t SH_FLD_UNUSED41_63 = 13509; // 43
+const static uint64_t SH_FLD_UNUSED41_63_LEN = 13510; // 43
+const static uint64_t SH_FLD_UNUSED46 = 13511; // 43
+const static uint64_t SH_FLD_UNUSED5 = 13512; // 7
+const static uint64_t SH_FLD_UNUSED63 = 13513; // 3
+const static uint64_t SH_FLD_UNUSED78 = 13514; // 43
+const static uint64_t SH_FLD_UNUSED78_LEN = 13515; // 43
+const static uint64_t SH_FLD_UNUSED919 = 13516; // 43
+const static uint64_t SH_FLD_UNUSED919_LEN = 13517; // 43
+const static uint64_t SH_FLD_UNUSED_0 = 13518; // 44
+const static uint64_t SH_FLD_UNUSED_0_LEN = 13519; // 1
+const static uint64_t SH_FLD_UNUSED_1 = 13520; // 44
+const static uint64_t SH_FLD_UNUSED_16_22 = 13521; // 1
+const static uint64_t SH_FLD_UNUSED_16_22_LEN = 13522; // 1
+const static uint64_t SH_FLD_UNUSED_1_LEN = 13523; // 1
+const static uint64_t SH_FLD_UNUSED_2 = 13524; // 1
+const static uint64_t SH_FLD_UNUSED_26_31 = 13525; // 1
+const static uint64_t SH_FLD_UNUSED_26_31_LEN = 13526; // 1
+const static uint64_t SH_FLD_UNUSED_2_LEN = 13527; // 1
+const static uint64_t SH_FLD_UNUSED_3 = 13528; // 1
+const static uint64_t SH_FLD_UNUSED_39_43 = 13529; // 1
+const static uint64_t SH_FLD_UNUSED_39_43_LEN = 13530; // 1
+const static uint64_t SH_FLD_UNUSED_3_LEN = 13531; // 1
+const static uint64_t SH_FLD_UNUSED_47_51 = 13532; // 1
+const static uint64_t SH_FLD_UNUSED_47_51_LEN = 13533; // 1
+const static uint64_t SH_FLD_UNUSED_4_15 = 13534; // 1
+const static uint64_t SH_FLD_UNUSED_4_15_LEN = 13535; // 1
+const static uint64_t SH_FLD_UNUSED_53 = 13536; // 1
+const static uint64_t SH_FLD_UNUSED_8_14 = 13537; // 1
+const static uint64_t SH_FLD_UNUSED_8_14_LEN = 13538; // 1
+const static uint64_t SH_FLD_UNUSED_LEN = 13539; // 87
+const static uint64_t SH_FLD_UPSTREAM = 13540; // 4
+const static uint64_t SH_FLD_USERDEF_CFG = 13541; // 6
+const static uint64_t SH_FLD_USERDEF_CFG_LEN = 13542; // 6
+const static uint64_t SH_FLD_USERDEF_TIMEOUT = 13543; // 6
+const static uint64_t SH_FLD_USERDEF_TIMEOUT_LEN = 13544; // 6
+const static uint64_t SH_FLD_USER_FILTER_MASK = 13545; // 6
+const static uint64_t SH_FLD_USER_FILTER_MASK_LEN = 13546; // 6
+const static uint64_t SH_FLD_USE_ARY_CLK_DURING_FILL = 13547; // 43
+const static uint64_t SH_FLD_USE_FOR_SCAN = 13548; // 43
+const static uint64_t SH_FLD_USE_OSC_OBSERVATION = 13549; // 1
+const static uint64_t SH_FLD_USE_OSC_OBSERVATION_LEN = 13550; // 1
+const static uint64_t SH_FLD_USE_PECE = 13551; // 24
+const static uint64_t SH_FLD_USE_PECE_LEN = 13552; // 24
+const static uint64_t SH_FLD_USE_SLS_AS_SPR = 13553; // 4
+const static uint64_t SH_FLD_USE_TB_STEP_SYNC = 13554; // 1
+const static uint64_t SH_FLD_USE_TB_SYNC_MECHANISM = 13555; // 1
+const static uint64_t SH_FLD_USE_WATCH_TO_READ_CTRL_ARY = 13556; // 1
+const static uint64_t SH_FLD_VALID = 13557; // 44
+const static uint64_t SH_FLD_VALID_ENTRY = 13558; // 1
+const static uint64_t SH_FLD_VALUE = 13559; // 50
+const static uint64_t SH_FLD_VALUES0 = 13560; // 16
+const static uint64_t SH_FLD_VALUES0_LEN = 13561; // 16
+const static uint64_t SH_FLD_VALUES1 = 13562; // 16
+const static uint64_t SH_FLD_VALUES1_LEN = 13563; // 16
+const static uint64_t SH_FLD_VALUES2 = 13564; // 16
+const static uint64_t SH_FLD_VALUES2_LEN = 13565; // 16
+const static uint64_t SH_FLD_VALUES3 = 13566; // 16
+const static uint64_t SH_FLD_VALUES3_LEN = 13567; // 16
+const static uint64_t SH_FLD_VALUES4 = 13568; // 16
+const static uint64_t SH_FLD_VALUES4_LEN = 13569; // 16
+const static uint64_t SH_FLD_VALUES5 = 13570; // 16
+const static uint64_t SH_FLD_VALUES5_LEN = 13571; // 16
+const static uint64_t SH_FLD_VALUES6 = 13572; // 16
+const static uint64_t SH_FLD_VALUES6_LEN = 13573; // 16
+const static uint64_t SH_FLD_VALUES7 = 13574; // 16
+const static uint64_t SH_FLD_VALUES7_LEN = 13575; // 16
+const static uint64_t SH_FLD_VALUE_LEN = 13576; // 50
+const static uint64_t SH_FLD_VAS_LOCAL_XSTOP = 13577; // 1
+const static uint64_t SH_FLD_VBGENDOC = 13578; // 3
+const static uint64_t SH_FLD_VBGENDOC_LEN = 13579; // 3
+const static uint64_t SH_FLD_VCC_REG_PD = 13580; // 8
+const static uint64_t SH_FLD_VCORANGE = 13581; // 10
+const static uint64_t SH_FLD_VCORANGE_LEN = 13582; // 10
+const static uint64_t SH_FLD_VCOSEL = 13583; // 16
+const static uint64_t SH_FLD_VCS_PFETS_DISABLED_SENSE = 13584; // 30
+const static uint64_t SH_FLD_VCS_PFETS_ENABLED_SENSE = 13585; // 30
+const static uint64_t SH_FLD_VCS_PFET_ENABLE_VALUE = 13586; // 30
+const static uint64_t SH_FLD_VCS_PFET_ENABLE_VALUE_LEN = 13587; // 30
+const static uint64_t SH_FLD_VCS_PFET_FORCE_STATE = 13588; // 30
+const static uint64_t SH_FLD_VCS_PFET_FORCE_STATE_LEN = 13589; // 30
+const static uint64_t SH_FLD_VCS_PFET_SEL_OVERRIDE = 13590; // 30
+const static uint64_t SH_FLD_VCS_PFET_SEL_VALUE = 13591; // 30
+const static uint64_t SH_FLD_VCS_PFET_SEL_VALUE_LEN = 13592; // 30
+const static uint64_t SH_FLD_VCS_PFET_VAL_OVERRIDE = 13593; // 30
+const static uint64_t SH_FLD_VCS_PG_SEL = 13594; // 30
+const static uint64_t SH_FLD_VCS_PG_SEL_LEN = 13595; // 30
+const static uint64_t SH_FLD_VCS_PG_STATE = 13596; // 30
+const static uint64_t SH_FLD_VCS_PG_STATE_LEN = 13597; // 30
+const static uint64_t SH_FLD_VCS_VOFF_SEL = 13598; // 30
+const static uint64_t SH_FLD_VCS_VOFF_SEL_LEN = 13599; // 30
+const static uint64_t SH_FLD_VC_PRIORITY_LIMIT_0_3 = 13600; // 1
+const static uint64_t SH_FLD_VC_PRIORITY_LIMIT_0_3_LEN = 13601; // 1
+const static uint64_t SH_FLD_VDD2VIO_LVL_FENCE_DC = 13602; // 1
+const static uint64_t SH_FLD_VDD_NEST_OBSERVE = 13603; // 1
+const static uint64_t SH_FLD_VDD_PFETS_DISABLED_SENSE = 13604; // 30
+const static uint64_t SH_FLD_VDD_PFETS_ENABLED_SENSE = 13605; // 30
+const static uint64_t SH_FLD_VDD_PFET_ENABLE_VALUE = 13606; // 30
+const static uint64_t SH_FLD_VDD_PFET_ENABLE_VALUE_LEN = 13607; // 30
+const static uint64_t SH_FLD_VDD_PFET_FORCE_STATE = 13608; // 30
+const static uint64_t SH_FLD_VDD_PFET_FORCE_STATE_LEN = 13609; // 30
+const static uint64_t SH_FLD_VDD_PFET_REGULATION_FINGER_EN = 13610; // 30
+const static uint64_t SH_FLD_VDD_PFET_REGULATION_FINGER_VALUE = 13611; // 30
+const static uint64_t SH_FLD_VDD_PFET_SEL_OVERRIDE = 13612; // 30
+const static uint64_t SH_FLD_VDD_PFET_SEL_VALUE = 13613; // 30
+const static uint64_t SH_FLD_VDD_PFET_SEL_VALUE_LEN = 13614; // 30
+const static uint64_t SH_FLD_VDD_PFET_VAL_OVERRIDE = 13615; // 30
+const static uint64_t SH_FLD_VDD_PG_SEL = 13616; // 30
+const static uint64_t SH_FLD_VDD_PG_SEL_LEN = 13617; // 30
+const static uint64_t SH_FLD_VDD_PG_STATE = 13618; // 30
+const static uint64_t SH_FLD_VDD_PG_STATE_LEN = 13619; // 30
+const static uint64_t SH_FLD_VDD_VOFF_SEL = 13620; // 30
+const static uint64_t SH_FLD_VDD_VOFF_SEL_LEN = 13621; // 30
+const static uint64_t SH_FLD_VDM_DISABLE = 13622; // 30
+const static uint64_t SH_FLD_VDM_DROOP_LARGE = 13623; // 6
+const static uint64_t SH_FLD_VDM_DROOP_LARGE_LEN = 13624; // 6
+const static uint64_t SH_FLD_VDM_DROOP_SMALL = 13625; // 6
+const static uint64_t SH_FLD_VDM_DROOP_SMALL_LEN = 13626; // 6
+const static uint64_t SH_FLD_VDM_DROOP_XTREME = 13627; // 6
+const static uint64_t SH_FLD_VDM_DROOP_XTREME_LEN = 13628; // 6
+const static uint64_t SH_FLD_VDM_LARGE_DROOP_CTR = 13629; // 12
+const static uint64_t SH_FLD_VDM_LARGE_DROOP_CTR_LEN = 13630; // 12
+const static uint64_t SH_FLD_VDM_LCL_SAMPLE_EN = 13631; // 12
+const static uint64_t SH_FLD_VDM_NO_DROOP_CTR = 13632; // 12
+const static uint64_t SH_FLD_VDM_NO_DROOP_CTR_LEN = 13633; // 12
+const static uint64_t SH_FLD_VDM_OVERVOLT_CTR = 13634; // 12
+const static uint64_t SH_FLD_VDM_OVERVOLT_CTR_LEN = 13635; // 12
+const static uint64_t SH_FLD_VDM_POWERON = 13636; // 36
+const static uint64_t SH_FLD_VDM_SMALL_DROOP_CTR = 13637; // 12
+const static uint64_t SH_FLD_VDM_SMALL_DROOP_CTR_LEN = 13638; // 12
+const static uint64_t SH_FLD_VDM_VID_COMPARE = 13639; // 6
+const static uint64_t SH_FLD_VDM_VID_COMPARE_LEN = 13640; // 6
+const static uint64_t SH_FLD_VECTOR_GROUP_EPSILON = 13641; // 8
+const static uint64_t SH_FLD_VECTOR_GROUP_EPSILON_LEN = 13642; // 8
+const static uint64_t SH_FLD_VG_COUNT = 13643; // 2
+const static uint64_t SH_FLD_VG_COUNT_LEN = 13644; // 2
+const static uint64_t SH_FLD_VG_TARGE = 13645; // 1
+const static uint64_t SH_FLD_VG_TARGET_SEL = 13646; // 24
+const static uint64_t SH_FLD_VG_TARGE_LEN = 13647; // 1
+const static uint64_t SH_FLD_VITAL_SCAN = 13648; // 43
+const static uint64_t SH_FLD_VITAL_SCAN_IN = 13649; // 43
+const static uint64_t SH_FLD_VITAL_THOLD = 13650; // 43
+const static uint64_t SH_FLD_VITL = 13651; // 43
+const static uint64_t SH_FLD_VITL_CLKOFF = 13652; // 43
+const static uint64_t SH_FLD_VLD = 13653; // 4
+const static uint64_t SH_FLD_VOFF_CFG = 13654; // 6
+const static uint64_t SH_FLD_VOFF_CFG_LEN = 13655; // 6
+const static uint64_t SH_FLD_VOLT_MODEREG_PARITY_MASK = 13656; // 43
+const static uint64_t SH_FLD_VPROTH_CTL = 13657; // 8
+const static uint64_t SH_FLD_VPROTH_CTL_LEN = 13658; // 8
+const static uint64_t SH_FLD_VREF = 13659; // 1
+const static uint64_t SH_FLD_VREFDQ0D = 13660; // 8
+const static uint64_t SH_FLD_VREFDQ0DSGN = 13661; // 8
+const static uint64_t SH_FLD_VREFDQ0D_LEN = 13662; // 8
+const static uint64_t SH_FLD_VREFDQ1D = 13663; // 8
+const static uint64_t SH_FLD_VREFDQ1DSGN = 13664; // 8
+const static uint64_t SH_FLD_VREFDQ1D_LEN = 13665; // 8
+const static uint64_t SH_FLD_VREFTUNE = 13666; // 3
+const static uint64_t SH_FLD_VREFTUNE_LEN = 13667; // 3
+const static uint64_t SH_FLD_VREF_LEN = 13668; // 1
+const static uint64_t SH_FLD_VREGBYP = 13669; // 6
+const static uint64_t SH_FLD_VREGBYPASS = 13670; // 4
+const static uint64_t SH_FLD_VREGENABLE_N = 13671; // 4
+const static uint64_t SH_FLD_VSEL = 13672; // 10
+const static uint64_t SH_FLD_VSEL_LEN = 13673; // 10
+const static uint64_t SH_FLD_VST_TYPE = 13674; // 1
+const static uint64_t SH_FLD_VST_TYPE_LEN = 13675; // 1
+const static uint64_t SH_FLD_VTARGET = 13676; // 4
+const static uint64_t SH_FLD_VTARGET_LEN = 13677; // 4
+const static uint64_t SH_FLD_V_TARG = 13678; // 1
+const static uint64_t SH_FLD_V_TARG_LEN = 13679; // 1
+const static uint64_t SH_FLD_W0_COUNT = 13680; // 12
+const static uint64_t SH_FLD_W0_COUNT_LEN = 13681; // 12
+const static uint64_t SH_FLD_W1_COUNT = 13682; // 12
+const static uint64_t SH_FLD_W1_COUNT_LEN = 13683; // 12
+const static uint64_t SH_FLD_WAITING = 13684; // 2
+const static uint64_t SH_FLD_WAIT_ALLWAYS = 13685; // 129
+const static uint64_t SH_FLD_WAIT_CYCLES = 13686; // 172
+const static uint64_t SH_FLD_WAIT_CYCLES_LEN = 13687; // 172
+const static uint64_t SH_FLD_WAKEUP_PULSE = 13688; // 1
+const static uint64_t SH_FLD_WAKEUP_PULSE_LEN = 13689; // 1
+const static uint64_t SH_FLD_WANT_CACHE_DISABLE = 13690; // 3
+const static uint64_t SH_FLD_WANT_INVALIDATE = 13691; // 2
+const static uint64_t SH_FLD_WARB_INVALID_CASE_ERROR = 13692; // 2
+const static uint64_t SH_FLD_WARM_START_COMPLETED = 13693; // 2
+const static uint64_t SH_FLD_WATCHDOG_SEL = 13694; // 17
+const static uint64_t SH_FLD_WATCHDOG_SEL_LEN = 13695; // 17
+const static uint64_t SH_FLD_WATERMARK_REG = 13696; // 1
+const static uint64_t SH_FLD_WATERMARK_REG_0 = 13697; // 1
+const static uint64_t SH_FLD_WATERMARK_REG_0_LEN = 13698; // 1
+const static uint64_t SH_FLD_WATERMARK_REG_1 = 13699; // 1
+const static uint64_t SH_FLD_WATERMARK_REG_1_LEN = 13700; // 1
+const static uint64_t SH_FLD_WATERMARK_REG_2 = 13701; // 1
+const static uint64_t SH_FLD_WATERMARK_REG_2_LEN = 13702; // 1
+const static uint64_t SH_FLD_WATERMARK_REG_3 = 13703; // 1
+const static uint64_t SH_FLD_WATERMARK_REG_3_LEN = 13704; // 1
+const static uint64_t SH_FLD_WATERMARK_REG_LEN = 13705; // 1
+const static uint64_t SH_FLD_WAT_DEBUG_ATTN = 13706; // 14
+const static uint64_t SH_FLD_WAT_ERROR = 13707; // 16
+const static uint64_t SH_FLD_WBMGR_DBG_0_SELECT = 13708; // 8
+const static uint64_t SH_FLD_WBMGR_DBG_1_SELECT = 13709; // 8
+const static uint64_t SH_FLD_WBRD_DEBUG_0_SELECT = 13710; // 8
+const static uint64_t SH_FLD_WBRD_DEBUG_1_SELECT = 13711; // 8
+const static uint64_t SH_FLD_WC = 13712; // 8
+const static uint64_t SH_FLD_WC_BS_BAR = 13713; // 1
+const static uint64_t SH_FLD_WC_BS_BAR_LEN = 13714; // 1
+const static uint64_t SH_FLD_WC_CERR_BITS = 13715; // 1
+const static uint64_t SH_FLD_WC_CERR_BITS_LEN = 13716; // 1
+const static uint64_t SH_FLD_WC_CERR_RESET = 13717; // 1
+const static uint64_t SH_FLD_WC_ECC_CE_ERROR = 13718; // 2
+const static uint64_t SH_FLD_WC_ECC_SUE_ERROR = 13719; // 2
+const static uint64_t SH_FLD_WC_ECC_UE_ERROR = 13720; // 2
+const static uint64_t SH_FLD_WC_LOGIC_HW_ERROR = 13721; // 2
+const static uint64_t SH_FLD_WC_MASK = 13722; // 8
+const static uint64_t SH_FLD_WC_TRACE_GROUP_SEL_HI = 13723; // 1
+const static uint64_t SH_FLD_WC_TRACE_GROUP_SEL_HI_LEN = 13724; // 1
+const static uint64_t SH_FLD_WC_TRACE_GROUP_SEL_LO = 13725; // 1
+const static uint64_t SH_FLD_WC_TRACE_GROUP_SEL_LO_LEN = 13726; // 1
+const static uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_01 = 13727; // 1
+const static uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_01_LEN = 13728; // 1
+const static uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_23 = 13729; // 1
+const static uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_23_LEN = 13730; // 1
+const static uint64_t SH_FLD_WDATA = 13731; // 1
+const static uint64_t SH_FLD_WDATA_LEN = 13732; // 1
+const static uint64_t SH_FLD_WDF_ASYNC_INTERFACE_ERROR = 13733; // 8
+const static uint64_t SH_FLD_WDF_MISC_REGISTER_PARITY_ERROR = 13734; // 8
+const static uint64_t SH_FLD_WDF_OVERRUN_ERROR_0 = 13735; // 8
+const static uint64_t SH_FLD_WDF_OVERRUN_ERROR_1 = 13736; // 8
+const static uint64_t SH_FLD_WDF_SCOM_SEQUENCE_ERROR = 13737; // 8
+const static uint64_t SH_FLD_WDF_STATE_MACHINE_ERROR = 13738; // 8
+const static uint64_t SH_FLD_WIRETEST_DONE = 13739; // 4
+const static uint64_t SH_FLD_WIRETEST_FAILED = 13740; // 4
+const static uint64_t SH_FLD_WITH_ADDRESS_0 = 13741; // 1
+const static uint64_t SH_FLD_WITH_ADDRESS_1 = 13742; // 1
+const static uint64_t SH_FLD_WITH_ADDRESS_2 = 13743; // 1
+const static uint64_t SH_FLD_WITH_ADDRESS_3 = 13744; // 1
+const static uint64_t SH_FLD_WITH_START_0 = 13745; // 1
+const static uint64_t SH_FLD_WITH_START_1 = 13746; // 1
+const static uint64_t SH_FLD_WITH_START_2 = 13747; // 1
+const static uint64_t SH_FLD_WITH_START_3 = 13748; // 1
+const static uint64_t SH_FLD_WITH_STOP_0 = 13749; // 1
+const static uint64_t SH_FLD_WITH_STOP_1 = 13750; // 1
+const static uint64_t SH_FLD_WITH_STOP_2 = 13751; // 1
+const static uint64_t SH_FLD_WITH_STOP_3 = 13752; // 1
+const static uint64_t SH_FLD_WI_MACHINE_HANG_ERR = 13753; // 12
+const static uint64_t SH_FLD_WI_MACHINE_W4DT_HANG_ERR = 13754; // 12
+const static uint64_t SH_FLD_WI_UNSOLICITED_DATA_ERR = 13755; // 12
+const static uint64_t SH_FLD_WKUP_NOTIFY_SELECT = 13756; // 24
+const static uint64_t SH_FLD_WKUP_OVERRIDE_EN = 13757; // 30
+const static uint64_t SH_FLD_WL_ONE_DQS_PULSE = 13758; // 8
+const static uint64_t SH_FLD_WM_MULTIHIT_ERR = 13759; // 2
+const static uint64_t SH_FLD_WM_WIN_NOT_OPEN_ERR = 13760; // 2
+const static uint64_t SH_FLD_WOF = 13761; // 6
+const static uint64_t SH_FLD_WOF_COUNTER = 13762; // 1
+const static uint64_t SH_FLD_WOF_COUNTER_LEN = 13763; // 1
+const static uint64_t SH_FLD_WOF_LEN = 13764; // 6
+const static uint64_t SH_FLD_WOF_LOW_ORDER_STEP_COUNTER_PARITY = 13765; // 4
+const static uint64_t SH_FLD_WORD = 13766; // 8
+const static uint64_t SH_FLD_WORD_LEN = 13767; // 8
+const static uint64_t SH_FLD_WRAP = 13768; // 1
+const static uint64_t SH_FLD_WRAP_0 = 13769; // 1
+const static uint64_t SH_FLD_WRAP_1 = 13770; // 1
+const static uint64_t SH_FLD_WRAP_2 = 13771; // 1
+const static uint64_t SH_FLD_WRAP_3 = 13772; // 1
+const static uint64_t SH_FLD_WRCMP = 13773; // 2
+const static uint64_t SH_FLD_WRCMP_LEN = 13774; // 2
+const static uint64_t SH_FLD_WRCNTL_DBG_SELECT = 13775; // 8
+const static uint64_t SH_FLD_WRDM_DLY = 13776; // 8
+const static uint64_t SH_FLD_WRDM_DLY_LEN = 13777; // 8
+const static uint64_t SH_FLD_WRD_CAW2_UE_CE_DETECT = 13778; // 2
+const static uint64_t SH_FLD_WRITE = 13779; // 3
+const static uint64_t SH_FLD_WRITE_CMD = 13780; // 1
+const static uint64_t SH_FLD_WRITE_COUNT = 13781; // 8
+const static uint64_t SH_FLD_WRITE_COUNTER = 13782; // 1
+const static uint64_t SH_FLD_WRITE_COUNTER_LEN = 13783; // 1
+const static uint64_t SH_FLD_WRITE_COUNT_LEN = 13784; // 8
+const static uint64_t SH_FLD_WRITE_CRD_POOL = 13785; // 1
+const static uint64_t SH_FLD_WRITE_CRD_POOL_LEN = 13786; // 1
+const static uint64_t SH_FLD_WRITE_CTR = 13787; // 8
+const static uint64_t SH_FLD_WRITE_ENABLE = 13788; // 129
+const static uint64_t SH_FLD_WRITE_INVALID_FACES = 13789; // 1
+const static uint64_t SH_FLD_WRITE_INVALID_PIB = 13790; // 1
+const static uint64_t SH_FLD_WRITE_LATENCY_OFFSET = 13791; // 8
+const static uint64_t SH_FLD_WRITE_LATENCY_OFFSET_LEN = 13792; // 8
+const static uint64_t SH_FLD_WRITE_NOT_READ = 13793; // 3
+const static uint64_t SH_FLD_WRITE_NVLD = 13794; // 1
+const static uint64_t SH_FLD_WRITE_ON_RUN = 13795; // 90
+const static uint64_t SH_FLD_WRITE_RMW_CE = 13796; // 8
+const static uint64_t SH_FLD_WRITE_RMW_SUE = 13797; // 8
+const static uint64_t SH_FLD_WRITE_RMW_UE = 13798; // 8
+const static uint64_t SH_FLD_WRITE_RST_INTERRUPT_FACES = 13799; // 1
+const static uint64_t SH_FLD_WRITE_RST_INTERRUPT_PIB = 13800; // 1
+const static uint64_t SH_FLD_WRITE_TSIZE = 13801; // 4
+const static uint64_t SH_FLD_WRITE_TSIZE_LEN = 13802; // 4
+const static uint64_t SH_FLD_WRITE_TTYPE = 13803; // 4
+const static uint64_t SH_FLD_WRITE_TTYPE_LEN = 13804; // 4
+const static uint64_t SH_FLD_WRITE_WHILE_BRIDGE_BUSY_ERR = 13805; // 1
+const static uint64_t SH_FLD_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN = 13806; // 1
+const static uint64_t SH_FLD_WRMON_BAR0_BA = 13807; // 1
+const static uint64_t SH_FLD_WRMON_BAR0_BA_LEN = 13808; // 1
+const static uint64_t SH_FLD_WRMON_BAR0_SIZE = 13809; // 1
+const static uint64_t SH_FLD_WRMON_BAR0_SIZE_LEN = 13810; // 1
+const static uint64_t SH_FLD_WRMON_BAR1_BA = 13811; // 1
+const static uint64_t SH_FLD_WRMON_BAR1_BA_LEN = 13812; // 1
+const static uint64_t SH_FLD_WRMON_BAR1_SIZE = 13813; // 1
+const static uint64_t SH_FLD_WRMON_BAR1_SIZE_LEN = 13814; // 1
+const static uint64_t SH_FLD_WRMON_BAR2_BA = 13815; // 1
+const static uint64_t SH_FLD_WRMON_BAR2_BA_LEN = 13816; // 1
+const static uint64_t SH_FLD_WRMON_BAR2_SIZE = 13817; // 1
+const static uint64_t SH_FLD_WRMON_BAR2_SIZE_LEN = 13818; // 1
+const static uint64_t SH_FLD_WRMON_BAR3_BA = 13819; // 1
+const static uint64_t SH_FLD_WRMON_BAR3_BA_LEN = 13820; // 1
+const static uint64_t SH_FLD_WRMON_BAR3_SIZE = 13821; // 1
+const static uint64_t SH_FLD_WRMON_BAR3_SIZE_LEN = 13822; // 1
+const static uint64_t SH_FLD_WRMON_BAR4_BA = 13823; // 1
+const static uint64_t SH_FLD_WRMON_BAR4_BA_LEN = 13824; // 1
+const static uint64_t SH_FLD_WRMON_BAR4_SIZE = 13825; // 1
+const static uint64_t SH_FLD_WRMON_BAR4_SIZE_LEN = 13826; // 1
+const static uint64_t SH_FLD_WRMON_BAR5_BA = 13827; // 1
+const static uint64_t SH_FLD_WRMON_BAR5_BA_LEN = 13828; // 1
+const static uint64_t SH_FLD_WRMON_BAR5_SIZE = 13829; // 1
+const static uint64_t SH_FLD_WRMON_BAR5_SIZE_LEN = 13830; // 1
+const static uint64_t SH_FLD_WRMON_BAR6_BA = 13831; // 1
+const static uint64_t SH_FLD_WRMON_BAR6_BA_LEN = 13832; // 1
+const static uint64_t SH_FLD_WRMON_BAR6_SIZE = 13833; // 1
+const static uint64_t SH_FLD_WRMON_BAR6_SIZE_LEN = 13834; // 1
+const static uint64_t SH_FLD_WRMON_BAR7_BA = 13835; // 1
+const static uint64_t SH_FLD_WRMON_BAR7_BA_LEN = 13836; // 1
+const static uint64_t SH_FLD_WRMON_BAR7_SIZE = 13837; // 1
+const static uint64_t SH_FLD_WRMON_BAR7_SIZE_LEN = 13838; // 1
+const static uint64_t SH_FLD_WRMON_CMP0_ENADTTYPE = 13839; // 1
+const static uint64_t SH_FLD_WRMON_CMP0_TSIZE = 13840; // 1
+const static uint64_t SH_FLD_WRMON_CMP0_TSIZEMSK = 13841; // 1
+const static uint64_t SH_FLD_WRMON_CMP0_TSIZEMSK_LEN = 13842; // 1
+const static uint64_t SH_FLD_WRMON_CMP0_TSIZE_LEN = 13843; // 1
+const static uint64_t SH_FLD_WRMON_CMP0_TTYPE = 13844; // 1
+const static uint64_t SH_FLD_WRMON_CMP0_TTYPEDIS = 13845; // 1
+const static uint64_t SH_FLD_WRMON_CMP0_TTYPEDIS_LEN = 13846; // 1
+const static uint64_t SH_FLD_WRMON_CMP0_TTYPEMSK = 13847; // 1
+const static uint64_t SH_FLD_WRMON_CMP0_TTYPEMSK_LEN = 13848; // 1
+const static uint64_t SH_FLD_WRMON_CMP0_TTYPE_LEN = 13849; // 1
+const static uint64_t SH_FLD_WRMON_CMP0_VAL = 13850; // 1
+const static uint64_t SH_FLD_WRMON_CMP1_ENADTTYPE = 13851; // 1
+const static uint64_t SH_FLD_WRMON_CMP1_TSIZE = 13852; // 1
+const static uint64_t SH_FLD_WRMON_CMP1_TSIZEMSK = 13853; // 1
+const static uint64_t SH_FLD_WRMON_CMP1_TSIZEMSK_LEN = 13854; // 1
+const static uint64_t SH_FLD_WRMON_CMP1_TSIZE_LEN = 13855; // 1
+const static uint64_t SH_FLD_WRMON_CMP1_TTYPE = 13856; // 1
+const static uint64_t SH_FLD_WRMON_CMP1_TTYPEDIS = 13857; // 1
+const static uint64_t SH_FLD_WRMON_CMP1_TTYPEDIS_LEN = 13858; // 1
+const static uint64_t SH_FLD_WRMON_CMP1_TTYPEMSK = 13859; // 1
+const static uint64_t SH_FLD_WRMON_CMP1_TTYPEMSK_LEN = 13860; // 1
+const static uint64_t SH_FLD_WRMON_CMP1_TTYPE_LEN = 13861; // 1
+const static uint64_t SH_FLD_WRMON_CMP1_VAL = 13862; // 1
+const static uint64_t SH_FLD_WRMON_CMP2_ENADTTYPE = 13863; // 1
+const static uint64_t SH_FLD_WRMON_CMP2_TSIZE = 13864; // 1
+const static uint64_t SH_FLD_WRMON_CMP2_TSIZEMSK = 13865; // 1
+const static uint64_t SH_FLD_WRMON_CMP2_TSIZEMSK_LEN = 13866; // 1
+const static uint64_t SH_FLD_WRMON_CMP2_TSIZE_LEN = 13867; // 1
+const static uint64_t SH_FLD_WRMON_CMP2_TTYPE = 13868; // 1
+const static uint64_t SH_FLD_WRMON_CMP2_TTYPEDIS = 13869; // 1
+const static uint64_t SH_FLD_WRMON_CMP2_TTYPEDIS_LEN = 13870; // 1
+const static uint64_t SH_FLD_WRMON_CMP2_TTYPEMSK = 13871; // 1
+const static uint64_t SH_FLD_WRMON_CMP2_TTYPEMSK_LEN = 13872; // 1
+const static uint64_t SH_FLD_WRMON_CMP2_TTYPE_LEN = 13873; // 1
+const static uint64_t SH_FLD_WRMON_CMP2_VAL = 13874; // 1
+const static uint64_t SH_FLD_WRMON_CMP3_ENADTTYPE = 13875; // 1
+const static uint64_t SH_FLD_WRMON_CMP3_TSIZE = 13876; // 1
+const static uint64_t SH_FLD_WRMON_CMP3_TSIZEMSK = 13877; // 1
+const static uint64_t SH_FLD_WRMON_CMP3_TSIZEMSK_LEN = 13878; // 1
+const static uint64_t SH_FLD_WRMON_CMP3_TSIZE_LEN = 13879; // 1
+const static uint64_t SH_FLD_WRMON_CMP3_TTYPE = 13880; // 1
+const static uint64_t SH_FLD_WRMON_CMP3_TTYPEDIS = 13881; // 1
+const static uint64_t SH_FLD_WRMON_CMP3_TTYPEDIS_LEN = 13882; // 1
+const static uint64_t SH_FLD_WRMON_CMP3_TTYPEMSK = 13883; // 1
+const static uint64_t SH_FLD_WRMON_CMP3_TTYPEMSK_LEN = 13884; // 1
+const static uint64_t SH_FLD_WRMON_CMP3_TTYPE_LEN = 13885; // 1
+const static uint64_t SH_FLD_WRMON_CMP3_VAL = 13886; // 1
+const static uint64_t SH_FLD_WRMON_CMP4_ENADTTYPE = 13887; // 1
+const static uint64_t SH_FLD_WRMON_CMP4_TSIZE = 13888; // 1
+const static uint64_t SH_FLD_WRMON_CMP4_TSIZEMSK = 13889; // 1
+const static uint64_t SH_FLD_WRMON_CMP4_TSIZEMSK_LEN = 13890; // 1
+const static uint64_t SH_FLD_WRMON_CMP4_TSIZE_LEN = 13891; // 1
+const static uint64_t SH_FLD_WRMON_CMP4_TTYPE = 13892; // 1
+const static uint64_t SH_FLD_WRMON_CMP4_TTYPEDIS = 13893; // 1
+const static uint64_t SH_FLD_WRMON_CMP4_TTYPEDIS_LEN = 13894; // 1
+const static uint64_t SH_FLD_WRMON_CMP4_TTYPEMSK = 13895; // 1
+const static uint64_t SH_FLD_WRMON_CMP4_TTYPEMSK_LEN = 13896; // 1
+const static uint64_t SH_FLD_WRMON_CMP4_TTYPE_LEN = 13897; // 1
+const static uint64_t SH_FLD_WRMON_CMP4_VAL = 13898; // 1
+const static uint64_t SH_FLD_WRMON_CMP5_ENADTTYPE = 13899; // 1
+const static uint64_t SH_FLD_WRMON_CMP5_TSIZE = 13900; // 1
+const static uint64_t SH_FLD_WRMON_CMP5_TSIZEMSK = 13901; // 1
+const static uint64_t SH_FLD_WRMON_CMP5_TSIZEMSK_LEN = 13902; // 1
+const static uint64_t SH_FLD_WRMON_CMP5_TSIZE_LEN = 13903; // 1
+const static uint64_t SH_FLD_WRMON_CMP5_TTYPE = 13904; // 1
+const static uint64_t SH_FLD_WRMON_CMP5_TTYPEDIS = 13905; // 1
+const static uint64_t SH_FLD_WRMON_CMP5_TTYPEDIS_LEN = 13906; // 1
+const static uint64_t SH_FLD_WRMON_CMP5_TTYPEMSK = 13907; // 1
+const static uint64_t SH_FLD_WRMON_CMP5_TTYPEMSK_LEN = 13908; // 1
+const static uint64_t SH_FLD_WRMON_CMP5_TTYPE_LEN = 13909; // 1
+const static uint64_t SH_FLD_WRMON_CMP5_VAL = 13910; // 1
+const static uint64_t SH_FLD_WRMON_CMP6_ENADTTYPE = 13911; // 1
+const static uint64_t SH_FLD_WRMON_CMP6_TSIZE = 13912; // 1
+const static uint64_t SH_FLD_WRMON_CMP6_TSIZEMSK = 13913; // 1
+const static uint64_t SH_FLD_WRMON_CMP6_TSIZEMSK_LEN = 13914; // 1
+const static uint64_t SH_FLD_WRMON_CMP6_TSIZE_LEN = 13915; // 1
+const static uint64_t SH_FLD_WRMON_CMP6_TTYPE = 13916; // 1
+const static uint64_t SH_FLD_WRMON_CMP6_TTYPEDIS = 13917; // 1
+const static uint64_t SH_FLD_WRMON_CMP6_TTYPEDIS_LEN = 13918; // 1
+const static uint64_t SH_FLD_WRMON_CMP6_TTYPEMSK = 13919; // 1
+const static uint64_t SH_FLD_WRMON_CMP6_TTYPEMSK_LEN = 13920; // 1
+const static uint64_t SH_FLD_WRMON_CMP6_TTYPE_LEN = 13921; // 1
+const static uint64_t SH_FLD_WRMON_CMP6_VAL = 13922; // 1
+const static uint64_t SH_FLD_WRMON_CMP7_ENADTTYPE = 13923; // 1
+const static uint64_t SH_FLD_WRMON_CMP7_TSIZE = 13924; // 1
+const static uint64_t SH_FLD_WRMON_CMP7_TSIZEMSK = 13925; // 1
+const static uint64_t SH_FLD_WRMON_CMP7_TSIZEMSK_LEN = 13926; // 1
+const static uint64_t SH_FLD_WRMON_CMP7_TSIZE_LEN = 13927; // 1
+const static uint64_t SH_FLD_WRMON_CMP7_TTYPE = 13928; // 1
+const static uint64_t SH_FLD_WRMON_CMP7_TTYPEDIS = 13929; // 1
+const static uint64_t SH_FLD_WRMON_CMP7_TTYPEDIS_LEN = 13930; // 1
+const static uint64_t SH_FLD_WRMON_CMP7_TTYPEMSK = 13931; // 1
+const static uint64_t SH_FLD_WRMON_CMP7_TTYPEMSK_LEN = 13932; // 1
+const static uint64_t SH_FLD_WRMON_CMP7_TTYPE_LEN = 13933; // 1
+const static uint64_t SH_FLD_WRMON_CMP7_VAL = 13934; // 1
+const static uint64_t SH_FLD_WRMON_WID0 = 13935; // 1
+const static uint64_t SH_FLD_WRMON_WID0_LEN = 13936; // 1
+const static uint64_t SH_FLD_WRMON_WID1 = 13937; // 1
+const static uint64_t SH_FLD_WRMON_WID1_LEN = 13938; // 1
+const static uint64_t SH_FLD_WRMON_WID2 = 13939; // 1
+const static uint64_t SH_FLD_WRMON_WID2_LEN = 13940; // 1
+const static uint64_t SH_FLD_WRMON_WID3 = 13941; // 1
+const static uint64_t SH_FLD_WRMON_WID3_LEN = 13942; // 1
+const static uint64_t SH_FLD_WRMON_WID4 = 13943; // 1
+const static uint64_t SH_FLD_WRMON_WID4_LEN = 13944; // 1
+const static uint64_t SH_FLD_WRMON_WID5 = 13945; // 1
+const static uint64_t SH_FLD_WRMON_WID5_LEN = 13946; // 1
+const static uint64_t SH_FLD_WRMON_WID6 = 13947; // 1
+const static uint64_t SH_FLD_WRMON_WID6_LEN = 13948; // 1
+const static uint64_t SH_FLD_WRMON_WID7 = 13949; // 1
+const static uint64_t SH_FLD_WRMON_WID7_LEN = 13950; // 1
+const static uint64_t SH_FLD_WRQ_CAPACITY_LIMIT = 13951; // 4
+const static uint64_t SH_FLD_WRQ_CAPACITY_LIMIT_LEN = 13952; // 4
+const static uint64_t SH_FLD_WRQ_FSM_PERR = 13953; // 1
+const static uint64_t SH_FLD_WRQ_HANG = 13954; // 8
+const static uint64_t SH_FLD_WRQ_OVERFLOW = 13955; // 1
+const static uint64_t SH_FLD_WRQ_PE = 13956; // 8
+const static uint64_t SH_FLD_WRQ_RRQ_HANG_ERR = 13957; // 16
+const static uint64_t SH_FLD_WRSBG_DLY = 13958; // 8
+const static uint64_t SH_FLD_WRSBG_DLY_LEN = 13959; // 8
+const static uint64_t SH_FLD_WRSMDR_DLY = 13960; // 8
+const static uint64_t SH_FLD_WRSMDR_DLY_LEN = 13961; // 8
+const static uint64_t SH_FLD_WRSMSR_DLY = 13962; // 8
+const static uint64_t SH_FLD_WRSMSR_DLY_LEN = 13963; // 8
+const static uint64_t SH_FLD_WRTO_AMO_COLLISION_RULES = 13964; // 8
+const static uint64_t SH_FLD_WRTO_AMO_COLLISION_RULES_LEN = 13965; // 8
+const static uint64_t SH_FLD_WRT_MISC_REGISTER_PARITY_ERROR = 13966; // 8
+const static uint64_t SH_FLD_WRT_RST_INTRPT_FACES = 13967; // 1
+const static uint64_t SH_FLD_WRT_RST_INTRPT_PIB = 13968; // 1
+const static uint64_t SH_FLD_WRT_SCOM_SEQUENCE_ERROR = 13969; // 8
+const static uint64_t SH_FLD_WR_BUFFER_STATUS = 13970; // 2
+const static uint64_t SH_FLD_WR_BUFFER_STATUS_LEN = 13971; // 2
+const static uint64_t SH_FLD_WR_BYTE_COUNT = 13972; // 2
+const static uint64_t SH_FLD_WR_BYTE_COUNT_LEN = 13973; // 2
+const static uint64_t SH_FLD_WR_CNTL = 13974; // 8
+const static uint64_t SH_FLD_WR_CNTL_MASK = 13975; // 8
+const static uint64_t SH_FLD_WR_DATA_PARITY_ERROR = 13976; // 3
+const static uint64_t SH_FLD_WR_EPSILON_VALUE = 13977; // 2
+const static uint64_t SH_FLD_WR_EPSILON_VALUE_LEN = 13978; // 2
+const static uint64_t SH_FLD_WR_FIFO_STAB = 13979; // 8
+const static uint64_t SH_FLD_WR_GATHER_TIMEOUT = 13980; // 4
+const static uint64_t SH_FLD_WR_GATHER_TIMEOUT_LEN = 13981; // 4
+const static uint64_t SH_FLD_WR_LEVEL = 13982; // 8
+const static uint64_t SH_FLD_WR_MON_NOT_DISABLED_ERR = 13983; // 2
+const static uint64_t SH_FLD_WR_PAR_ERR = 13984; // 8
+const static uint64_t SH_FLD_WR_PAR_ERR_MASK = 13985; // 8
+const static uint64_t SH_FLD_WR_PRE_DLY = 13986; // 8
+const static uint64_t SH_FLD_WR_PRE_DLY_LEN = 13987; // 8
+const static uint64_t SH_FLD_WR_RSVD_LOWER_OR_STATIC_LIMIT = 13988; // 8
+const static uint64_t SH_FLD_WR_RSVD_LOWER_OR_STATIC_LIMIT_LEN = 13989; // 8
+const static uint64_t SH_FLD_WR_RSVD_UPPER_LIMIT = 13990; // 8
+const static uint64_t SH_FLD_WR_RSVD_UPPER_LIMIT_LEN = 13991; // 8
+const static uint64_t SH_FLD_WR_SCOPE = 13992; // 24
+const static uint64_t SH_FLD_WR_SLVNUM = 13993; // 2
+const static uint64_t SH_FLD_WR_SLVNUM_LEN = 13994; // 2
+const static uint64_t SH_FLD_WR_SPLIT_UT0_ENA = 13995; // 6
+const static uint64_t SH_FLD_WR_SPLIT_UT1_ENA = 13996; // 6
+const static uint64_t SH_FLD_WR_VALID = 13997; // 1
+const static uint64_t SH_FLD_WT4CR_TIER0_EPS_VAL = 13998; // 12
+const static uint64_t SH_FLD_WT4CR_TIER0_EPS_VAL_LEN = 13999; // 12
+const static uint64_t SH_FLD_WT4CR_TIER1_EPS_VAL = 14000; // 24
+const static uint64_t SH_FLD_WT4CR_TIER1_EPS_VAL_LEN = 14001; // 24
+const static uint64_t SH_FLD_WT4CR_TIER2_EPS_VAL = 14002; // 24
+const static uint64_t SH_FLD_WT4CR_TIER2_EPS_VAL_LEN = 14003; // 24
+const static uint64_t SH_FLD_WTL_SM_STATUS = 14004; // 4
+const static uint64_t SH_FLD_WTL_SM_STATUS_LEN = 14005; // 4
+const static uint64_t SH_FLD_WTL_TEST_CLOCK = 14006; // 4
+const static uint64_t SH_FLD_WTL_TEST_DATA = 14007; // 4
+const static uint64_t SH_FLD_WTR_MAX_BAD_LANES = 14008; // 4
+const static uint64_t SH_FLD_WTR_MAX_BAD_LANES_LEN = 14009; // 4
+const static uint64_t SH_FLD_WT_ALL_DONE_GCRMSG = 14010; // 4
+const static uint64_t SH_FLD_WT_BS_CLOCK_EN_BYP = 14011; // 4
+const static uint64_t SH_FLD_WT_BS_DATA_EN_BYP = 14012; // 4
+const static uint64_t SH_FLD_WT_CHECK_COUNT = 14013; // 4
+const static uint64_t SH_FLD_WT_CHECK_COUNT_LEN = 14014; // 4
+const static uint64_t SH_FLD_WT_CLK_LANE_BAD_CODE = 14015; // 4
+const static uint64_t SH_FLD_WT_CLK_LANE_BAD_CODE_LEN = 14016; // 4
+const static uint64_t SH_FLD_WT_CLK_LANE_INVERTED = 14017; // 4
+const static uint64_t SH_FLD_WT_CU_BYP_PLL_LOCK = 14018; // 4
+const static uint64_t SH_FLD_WT_CU_PLL_PGOOD = 14019; // 4
+const static uint64_t SH_FLD_WT_CU_PLL_PGOODDLY = 14020; // 4
+const static uint64_t SH_FLD_WT_CU_PLL_PGOODDLY_LEN = 14021; // 4
+const static uint64_t SH_FLD_WT_CU_PLL_RESET = 14022; // 4
+const static uint64_t SH_FLD_WT_EN_ALL_CLK_SEGS_GCRMSG = 14023; // 4
+const static uint64_t SH_FLD_WT_EN_ALL_DATA_SEGS_GCRMSG = 14024; // 4
+const static uint64_t SH_FLD_WT_LANE_BAD_CODE = 14025; // 96
+const static uint64_t SH_FLD_WT_LANE_BAD_CODE_LEN = 14026; // 96
+const static uint64_t SH_FLD_WT_LANE_DISABLED = 14027; // 96
+const static uint64_t SH_FLD_WT_PATTERN_LENGTH = 14028; // 8
+const static uint64_t SH_FLD_WT_PATTERN_LENGTH_LEN = 14029; // 8
+const static uint64_t SH_FLD_WT_PLL_REFCLKSEL = 14030; // 4
+const static uint64_t SH_FLD_WT_PREV_DONE_GCRMSG = 14031; // 4
+const static uint64_t SH_FLD_WT_TIMEOUT_SEL = 14032; // 4
+const static uint64_t SH_FLD_WT_TIMEOUT_SEL_LEN = 14033; // 4
+const static uint64_t SH_FLD_WWDM_DLY = 14034; // 8
+const static uint64_t SH_FLD_WWDM_DLY_LEN = 14035; // 8
+const static uint64_t SH_FLD_WWOP_DLY = 14036; // 8
+const static uint64_t SH_FLD_WWOP_DLY_LEN = 14037; // 8
+const static uint64_t SH_FLD_WWSMDR_DLY = 14038; // 8
+const static uint64_t SH_FLD_WWSMDR_DLY_LEN = 14039; // 8
+const static uint64_t SH_FLD_WWSMSR_DLY = 14040; // 8
+const static uint64_t SH_FLD_WWSMSR_DLY_LEN = 14041; // 8
+const static uint64_t SH_FLD_X0_TX_ENABLE = 14042; // 4
+const static uint64_t SH_FLD_X0_TX_SELECT = 14043; // 4
+const static uint64_t SH_FLD_X0_TX_SELECT_LEN = 14044; // 4
+const static uint64_t SH_FLD_X1_TX_ENABLE = 14045; // 4
+const static uint64_t SH_FLD_X1_TX_SELECT = 14046; // 4
+const static uint64_t SH_FLD_X1_TX_SELECT_LEN = 14047; // 4
+const static uint64_t SH_FLD_X2_TX_ENABLE = 14048; // 4
+const static uint64_t SH_FLD_X2_TX_SELECT = 14049; // 4
+const static uint64_t SH_FLD_X2_TX_SELECT_LEN = 14050; // 4
+const static uint64_t SH_FLD_X3_TX_ENABLE = 14051; // 4
+const static uint64_t SH_FLD_X3_TX_SELECT = 14052; // 4
+const static uint64_t SH_FLD_X3_TX_SELECT_LEN = 14053; // 4
+const static uint64_t SH_FLD_X4_TX_ENABLE = 14054; // 4
+const static uint64_t SH_FLD_X4_TX_SELECT = 14055; // 4
+const static uint64_t SH_FLD_X4_TX_SELECT_LEN = 14056; // 4
+const static uint64_t SH_FLD_X5_TX_ENABLE = 14057; // 4
+const static uint64_t SH_FLD_X5_TX_SELECT = 14058; // 4
+const static uint64_t SH_FLD_X5_TX_SELECT_LEN = 14059; // 4
+const static uint64_t SH_FLD_X6_TX_ENABLE = 14060; // 4
+const static uint64_t SH_FLD_X6_TX_SELECT = 14061; // 4
+const static uint64_t SH_FLD_X6_TX_SELECT_LEN = 14062; // 4
+const static uint64_t SH_FLD_X7_TX_ENABLE = 14063; // 4
+const static uint64_t SH_FLD_X7_TX_SELECT = 14064; // 4
+const static uint64_t SH_FLD_X7_TX_SELECT_LEN = 14065; // 4
+const static uint64_t SH_FLD_XCR = 14066; // 18
+const static uint64_t SH_FLD_XCR_LEN = 14067; // 18
+const static uint64_t SH_FLD_XIMEM_MEM_IFETCH_PENDING = 14068; // 18
+const static uint64_t SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 14069; // 18
+const static uint64_t SH_FLD_XIRAMGA_IR = 14070; // 18
+const static uint64_t SH_FLD_XIRAMGA_IR_LEN = 14071; // 18
+const static uint64_t SH_FLD_XIRAMRA_SPRG0 = 14072; // 36
+const static uint64_t SH_FLD_XIRAMRA_SPRG0_LEN = 14073; // 36
+const static uint64_t SH_FLD_XISIB_PIB_IFETCH_PENDING = 14074; // 18
+const static uint64_t SH_FLD_XIXCR_XCR = 14075; // 18
+const static uint64_t SH_FLD_XIXCR_XCR_LEN = 14076; // 18
+const static uint64_t SH_FLD_XLATE_TO_ADDR_ID_ENABLE = 14077; // 2
+const static uint64_t SH_FLD_XPT_POWERBUS_CE = 14078; // 4
+const static uint64_t SH_FLD_XPT_POWERBUS_SUE = 14079; // 4
+const static uint64_t SH_FLD_XPT_POWERBUS_UE = 14080; // 4
+const static uint64_t SH_FLD_XPT_RECOVERABLE_ERROR = 14081; // 4
+const static uint64_t SH_FLD_XPT_SYS_XSTOP_ERROR = 14082; // 4
+const static uint64_t SH_FLD_XSCOM_DONE = 14083; // 96
+const static uint64_t SH_FLD_XSCOM_FAIL = 14084; // 96
+const static uint64_t SH_FLD_XSCOM_STATUS = 14085; // 96
+const static uint64_t SH_FLD_XSCOM_STATUS_LEN = 14086; // 96
+const static uint64_t SH_FLD_XSC_CMD_OVERRUN = 14087; // 1
+const static uint64_t SH_FLD_XSTOP = 14088; // 5
+const static uint64_t SH_FLD_XSTOP_GATE = 14089; // 1
+const static uint64_t SH_FLD_Z = 14090; // 1
+const static uint64_t SH_FLD_ZCAL = 14091; // 4
+const static uint64_t SH_FLD_ZCAL_CYA_DATA_INV = 14092; // 4
+const static uint64_t SH_FLD_ZCAL_LEN = 14093; // 4
+const static uint64_t SH_FLD_ZCAL_N = 14094; // 4
+const static uint64_t SH_FLD_ZCAL_NOT_CONT = 14095; // 8
+const static uint64_t SH_FLD_ZCAL_N_LEN = 14096; // 4
+const static uint64_t SH_FLD_ZCAL_P = 14097; // 4
+const static uint64_t SH_FLD_ZCAL_P_LEN = 14098; // 4
+const static uint64_t SH_FLD_ZCAL_RANGE_CHECK = 14099; // 4
+const static uint64_t SH_FLD_ZCAL_SM_MAX_VAL = 14100; // 4
+const static uint64_t SH_FLD_ZCAL_SM_MAX_VAL_LEN = 14101; // 4
+const static uint64_t SH_FLD_ZCAL_SM_MIN_VAL = 14102; // 4
+const static uint64_t SH_FLD_ZCAL_SM_MIN_VAL_LEN = 14103; // 4
+const static uint64_t SH_FLD_ZCAL_SWO_CAL_SEGS = 14104; // 4
+const static uint64_t SH_FLD_ZCAL_SWO_CMP_INV = 14105; // 4
+const static uint64_t SH_FLD_ZCAL_SWO_CMP_OFFSET = 14106; // 4
+const static uint64_t SH_FLD_ZCAL_SWO_CMP_RESET = 14107; // 4
+const static uint64_t SH_FLD_ZCAL_SWO_EN = 14108; // 4
+const static uint64_t SH_FLD_ZCAL_SWO_POWERDOWN = 14109; // 4
+const static uint64_t SH_FLD_ZCAL_SWO_TCOIL = 14110; // 4
+const static uint64_t SH_FLD_ZCAL_TEST_CLK_DIV = 14111; // 4
+const static uint64_t SH_FLD_ZCAL_TEST_OVR_1R = 14112; // 4
+const static uint64_t SH_FLD_ZCAL_TEST_OVR_2R = 14113; // 4
+const static uint64_t SH_FLD_ZCAL_TEST_OVR_4X_SEG = 14114; // 4
+
+#endif
diff --git a/src/ppe/importtemp/fapi2/include/array.H b/src/ppe/importtemp/fapi2/include/array.H
new file mode 100644
index 0000000..a5d0a25
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/array.H
@@ -0,0 +1,174 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/array.H $                    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file array.H
+ * @brief definitions for fapi2 arrays
+ */
+
+#ifndef __FAPI2_ARRAY__
+#define __FAPI2_ARRAY__
+
+#include <stdint.h>
+#include <utility>
+#include <assert.h>
+#include <string.h>
+
+namespace fapi2
+{
+    ///
+    /// @brief Class representing a FAPI2 array
+    /// FAPI2 arrays are defined to be very lightweight but support
+    /// c++ container operations (iterators, bounds checking, assignment, etc.)
+    /// To avoid the code-bloat associated with std::vector templates,
+    /// fapi2::array is presently limited to 64-bit elements.
+    ///
+    /// To construct an array, you can either pass in an existing chunk
+    /// of memory, or let the container allocate memory for you:
+    ///    fapi2::array foo(3, &PIB_MEM_BLOCK);
+    /// creates an array 3 x uit64_t in size, located at &PIB_MEM_BLOCK.
+    /// The memory pointed to by the address passed in is untouched
+    /// during creation. This allows for a light-weight overlay on top
+    /// of existing memory. It also means you need to initialize the space
+    /// yourself.
+    ///    fapi2_array foo(3);
+    /// creates an array 3 x uint64_t in size, and that memory will be
+    /// allocated by the constructor and initiaized to 0's.
+    ///
+    ///
+    class array
+    {
+    public:
+
+        typedef uint64_t element_type;
+        typedef element_type* iterator;
+        typedef const element_type* const_iterator;
+
+        ///
+        /// @brief Create an array
+        /// @param[in] the size of the array
+        /// @param[in] a pointer to memory of appropriate size
+        ///   defaults to nullptr which causes the platform to
+        ///   allocate memory of size * element_type
+        /// @warning fapi2::arrays, like arrays, can not be re-sized after
+        /// creation.
+        ///
+        array(const uint32_t i_size, element_type* i_data = nullptr);
+
+        ///
+        /// @brief Destroy an array
+        ///
+        ~array(void);
+
+        ///
+        /// @brief operator[]
+        /// @param[in] the index of the element
+        /// @return a reference to the element in question.
+        /// @note array[0] = 0 works as well as foo = array[0]
+        ///
+        element_type& operator[](const uint32_t i_index);
+
+        ///
+        /// @brief operator=()
+        /// @param[in] the other array
+        /// @return a reference to this, after the assignement
+        ///
+        array& operator=(const array& i_other);
+
+        ///
+        /// @brief move operator=()
+        /// @note To use: new_array = std::move(old_array). old_array will be
+        /// destroyed and no copy will be made (moved)
+        ///
+        array& operator=(array&& i_other);
+
+        ///
+        /// @brief operator==()
+        ///
+        bool operator==(const array& i_other);
+
+        ///
+        /// @brief operator!=()
+        ///
+        __attribute__ ((always_inline))
+        bool operator!=(const array& i_other)
+            { return ! operator==(i_other); }
+
+        ///
+        /// @brief Return an iterator the to beginning of the array
+        /// @return An iterator to the beginning of the array
+        ///
+        __attribute__ ((always_inline))
+        iterator begin(void)
+            { return iv_data; }
+
+        ///
+        /// @brief Return an iterator the to end of the array
+        /// @return An iterator to the end of the array
+        ///
+        __attribute__ ((always_inline))
+        iterator end(void)
+            { return iv_data + size(); }
+
+        ///
+        /// @brief Return a const_iterator the to beginning of the array
+        /// @return A const_iterator to the beginning of the array
+        ///
+        __attribute__ ((always_inline))
+        const_iterator begin(void) const
+            { return iv_data; }
+
+        ///
+        /// @brief Return a const_iterator the to end of the array
+        /// @return A const_iterator to the end the array
+        ///
+        __attribute__ ((always_inline))
+        const_iterator end(void) const
+            { return iv_data + size(); }
+
+    private:
+
+        enum
+        {
+            // Bit in iv_size representing whether we delete in the dtor
+            delete_bit = 0x80000000,
+
+            // The resulting size limit
+            size_limit = 0x7FFFFFFF,
+        };
+
+        __attribute__ ((always_inline))
+        uint32_t size(void)
+        { return (iv_size & ~delete_bit); }
+
+        __attribute__ ((always_inline))
+        uint32_t size(void) const
+        { return (iv_size & ~delete_bit); }
+
+        uint32_t      iv_size;
+        element_type* iv_data;
+    };
+}
+
+#endif
diff --git a/src/ppe/importtemp/fapi2/include/buffer.H b/src/ppe/importtemp/fapi2/include/buffer.H
new file mode 100644
index 0000000..c0d86bc
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/buffer.H
@@ -0,0 +1,684 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/buffer.H $                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file buffer.H
+ * @brief definitions for fapi2 variable integral buffers
+ */
+
+#ifndef __FAPI2_INTEGRAL_BUFFER__
+#define __FAPI2_INTEGRAL_BUFFER__
+
+#include <buffer_parameters.H>
+#include <buffer_traits.H>
+#include <return_code.H>
+
+namespace fapi2
+{
+    /// @brief Class representing a FAPI buffer<T>
+    /// @tparam T, the integral type of the buffer (uint16_t, uint64_t, etc.)
+    template <typename T, typename TT = bufferTraits<T> >
+    class buffer
+    {
+    public:
+        /// Shortcut typedef to get to our traits class
+        typedef typename TT::bits_type bits_type;
+
+        ///
+        /// @brief Integral buffer assignment constructor
+        /// @param[in] i_value initial value of the buffer
+        /// Meaningless for variable types and thus protected.
+        ///
+        inline buffer(T i_value = 0):
+            iv_data(i_value)
+            {
+            }
+
+        ~buffer(void) = default;
+
+#if !defined(DOXYGEN) && defined(FAPI2_DEBUG)
+        /// @brief Print the contents of the buffer to stdout
+        inline void print(void) const
+        { TT::print(iv_data); }
+#endif
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return The contents of the buffer
+        ///
+        inline operator T() const { return iv_data; }
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return The contents of the buffer
+        ///
+        inline operator T&() { return iv_data; }
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return The contents of the buffer
+        ///
+        inline T& operator()(void) { return iv_data; }
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return Reference to the contents of the buffer
+        ///
+        inline const T& operator()(void) const { return iv_data; }
+
+        /// @name Buffer Manipulation Functions
+        ///@{
+
+        ///
+        /// @brief Set an OT of data in buffer
+        /// @param[in] i_value sizeof(OT) bits of data
+        /// @param[in] i_offset Start OT (start word, for example) in buffer
+        ///            - defaults to 0 (will by default write the left most element)
+        /// @return FAPI2_RC_SUCCESS on success, FAPI2_RC_OVERFLOW otherwise
+        /// @note This is is only available for integral types. To set a
+        ///    variable_buffer into a variable_buffer, use insert()
+        ///
+        template< typename OT>
+        inline fapi2::ReturnCode set(OT i_value, const bits_type i_offset = 0)
+        {
+            // Compile time check to make sure OT is integral
+            static_assert( std::is_integral<OT>::value,
+                           "Input must be an integral type" );
+
+            const uint32_t length = TT:: template size<OT>(iv_data);
+            static const bits_type bits_in_value = parameterTraits<OT>::bit_length();
+            const bits_type bit_length = TT::bit_length(iv_data);
+
+            if (i_offset + bits_in_value >= bit_length)
+            {
+                return FAPI2_RC_OVERFLOW;
+            }
+
+            // Create mask if part of this byte is not in the valid part of the buffer,
+            // Shift it left by the amount of unused bits,
+            // Clear the unused bits
+            if (((i_offset + 1) == length) && (bit_length % bits_in_value)) {
+                i_value &= parameterTraits<OT>::mask() << ((bits_in_value * length) - bit_length);
+            }
+
+            parameterTraits<OT>::template write_element<typename TT::unit_type>(TT::get_address(iv_data), i_value, i_offset);
+            return FAPI2_RC_SUCCESS;
+        }
+
+        /// @name Bit/Word Manipulation Functions
+        ///@{
+
+        ///
+        /// @brief Return the length of the buffer in bits
+        /// @return Length in bits
+        ///
+        inline constexpr uint32_t getBitLength(void) const
+            { return TT::bit_length(iv_data); }
+
+        ///
+        /// @brief Return the length of the buffer in OT units
+        /// @return Length in OT units rounded up
+        /// @tparam OT the type to get the length of. For example, if one
+        /// wanted the length in double words, OT would be uint64_t
+        /// (getLength<uint64_t>().) Similarly, to get the length in words,
+        /// getLength<uin32_t>().
+        ///
+        template< typename OT >
+        inline constexpr uint32_t getLength(void) const
+        {
+            return TT::template size<OT>(iv_data);
+        }
+
+        ///
+        /// @brief Templated setBit for integral types
+        /// @tparam B the bit number to set.
+        /// @tparam C the count of bits to set, defaults to 1
+        /// @return buffer& Useful for method chaining
+        /// @note 0 is left-most
+        /// @note Example: fapi2::buffer<uint64_t>().setBit<3>();
+        ///
+        template< bits_type B, bits_type C = 1 >
+        inline buffer& setBit(void)
+        {
+            static_assert((B >= 0) &&
+                          ((B + C - 1) < TT::bits_per_unit()), "failed range check");
+
+            // This would be a candidate for a fast_mask (see variable_buffer) but
+            // we'd need tables for all the integral types which maybe we need to
+            // do ...
+            iv_data |= (T(~0) >> (TT::bits_per_unit() - C)) << (TT::bits_per_unit() - B - C);
+            return *this;
+        }
+
+        ///
+        /// @brief Set a bit in the buffer
+        /// @param[in] i_bit the bit number to set.
+        /// @param[in] i_count the count of bits to set, defaults to 1
+        /// @note 0 is left-most
+        /// @return FAPI2_RC_SUCCESS if OK
+        ///
+        inline fapi2::ReturnCode setBit(const bits_type& i_bit, const bits_type& i_count = 1)
+        {
+            if ((i_count + i_bit - 1) >= TT::bits_per_unit())
+            {
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            iv_data |= (T(~0) >> (TT::bits_per_unit() - i_count)) << (TT::bits_per_unit() - i_bit - i_count);
+
+            return FAPI2_RC_SUCCESS;
+        }
+
+        ///
+        /// @brief Clear a bit in buffer
+        /// @tparam B Bit in buffer to clear.
+        /// @tparam C the count of bits to clear, defaults to 1
+        /// @return buffer& Useful for method chaining
+        /// @note Asserting that all the parameters are known at
+        /// compile time so this can be templated only. If that is not
+        /// the case we can add a function parameter version.
+        ///
+        template< bits_type B, bits_type C = 1>
+        inline buffer& clearBit(void)
+        {
+            static_assert((B >= 0) &&
+                          ((B + C - 1)< TT::bits_per_unit()), "failed range check");
+
+            iv_data &= buffer<T>().setBit<B, C>().invert();
+            return *this;
+        }
+
+        ///
+        /// @brief Clear a bit in the buffer
+        /// @param[in] i_bit the bit number to clear.
+        /// @param[in] i_count the count of bits to clear, defaults to 1
+        /// @note 0 is left-most
+        /// @return FAPI2_RC_SUCCESS if OK
+        ///
+        inline fapi2::ReturnCode clearBit(const bits_type& i_bit, const bits_type& i_count = 1)
+        {
+            if ((i_count + i_bit - 1) >= TT::bits_per_unit())
+            {
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            fapi2::buffer<T> l_scratch;
+
+            if (l_scratch.setBit(i_bit, i_count) != FAPI2_RC_SUCCESS)
+            {
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            iv_data &= l_scratch.invert();
+
+            return FAPI2_RC_SUCCESS;
+        }
+
+        ///
+        /// @brief Write a bit in buffer to a given value
+        /// @tparam B Bit in buffer to write
+        /// @tparam C the count of bits to write, defaults to 1
+        /// @return buffer& Useful for method chaining
+        /// @note Asserting that all the parameters are known at
+        /// compile time so this can be templated only. If that is not
+        /// the case we can add a function parameter version.
+        ///
+        template< bits_type B, bits_type C = 1 >
+        inline buffer& writeBit(const bool i_value)
+        {
+            static_assert((B >= 0) &&
+                          ((B + C - 1)< TT::bits_per_unit()), "failed range check");
+
+            (i_value == 0) ? clearBit<B, C>() : setBit<B, C>();
+            return *this;
+        }
+
+
+        ///
+        /// @brief Invert bit
+        /// @tparam B Bit in buffer to invert.
+        /// @tparam C the count of bits to flip, defaults to 1
+        /// @return buffer& Useful for method chaining
+        /// @note Asserting that all the parameters are known at
+        /// compile time so this can be templated only. If that is not
+        /// the case we can add a function parameter version.
+        ///
+        template< bits_type B, bits_type C = 1 >
+        inline buffer& flipBit(void)
+        {
+            static_assert((B >= 0) &&
+                          ((B + C - 1) < TT::bits_per_unit()), "failed range check");
+
+            iv_data ^= buffer<T>().setBit<B, C>();
+            return *this;
+        }
+
+        ///
+        /// @brief Get the value of a bit in the buffer
+        /// @tparam B Bit in buffer to get.
+        /// @tparam C the count of bits to get, defaults to 1
+        /// @return true if *any* bit is on, false if *every* bit is off
+        ///
+        template< bits_type B, bits_type C = 1>
+        inline bool getBit(void) const
+            {
+                return buffer<T>().setBit<B, C>() & iv_data;
+            }
+
+        ///
+        /// @brief Set and entire buffer to X's
+        /// @tparam X {0,1} depending if you want to clear (0)
+        /// or fill (1) a buffer
+        /// @return buffer_base&, Useful for method chaining
+        ///
+        template< uint8_t X >
+        inline buffer& flush(void)
+            {
+                static_assert( (X == 1) || (X == 0), "bad argument to flush" );
+                (0 == X) ? TT::clear(iv_data) : TT::set(iv_data);
+                return *this;
+            }
+
+        ///
+        /// @brief Invert entire buffer
+        /// @return buffer_base&, Useful for method chaining
+        ///
+        inline buffer& invert(void)
+            { TT::invert(iv_data); return *this; }
+
+        ///
+        /// @brief Bit reverse entire buffer
+        /// @return buffer_base&, Useful for method chaining
+        ///
+        inline buffer& reverse(void)
+            { TT::reverse(iv_data); return *this; }
+
+
+        ///@}
+
+        /// @name Buffer Manipulation Functions
+        ///@{
+
+        ///
+        /// @brief Get a pointer to the buffer bits
+        /// @return Pointer to the buffer itself
+        ///
+        inline T* pointer(void) { return &iv_data; }
+
+        // Note: Many (all?) of these are not needed and the compiler complains
+        // as the cast to T yields a better operator. There are here mainly for
+        // documenation purposes.
+
+        ///
+        /// @brief operator>>()
+        ///
+#ifdef DOXYGEN
+        inline buffer<T>& operator>>(bits_type i_shiftnum);
+#endif
+
+        ///
+        /// @brief operator<<()
+        ///
+#ifdef DOXYGEN
+        inline buffer<T>& operator<<(bits_type i_shiftnum);
+#endif
+
+        ///
+        /// @brief operator+()
+        ///
+#ifdef DOXYGEN
+        inline buffer<T>& operator+(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator+=()
+        ///
+#ifdef DOXYGEN
+        inline buffer<T>& operator+=(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator|=()
+        ///
+#ifdef DOXYGEN
+        inline buffer<T>& operator|=(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator&=()
+        ///
+#ifdef DOXYGEN
+        inline buffer<T>& operator&=(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator|()
+        ///
+#ifdef DOXYGEN
+        inline buffer<T>& operator|(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator&()
+        ///
+#ifdef DOXYGEN
+        inline buffer<T>& operator&(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator^=()
+        ///
+#ifdef DOXYGEN
+        inline buffer<T>& operator^=(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator~()
+        ///
+#ifdef DOXYGEN
+        inline buffer<T>& operator~(const T& rhs) const;
+#endif
+
+        ///
+        /// @brief operator==()
+        ///
+#ifdef DOXYGEN
+        inline bool operator==(const T& rhs) const;
+#endif
+
+        ///
+        /// @brief operator!=()
+        ///
+#ifdef DOXYGEN
+        inline bool operator!=(const T& rhs) const;
+#endif
+
+        ///
+        /// @brief Copy part of a OT into the DataBuffer
+        /// @tparam TS Start bit to insert into (target start)
+        /// @tparam L Length of bits to insert
+        /// @tparam SS Start bit in source - defaults to bit 0
+        /// @tparam OT the type of the incoming (origin) data
+        /// @param[in] i_datain OT value to copy into DataBuffer
+        ///    - data is taken left aligned
+        /// @return buffer& Useful for method chaining
+        ///
+        template<bits_type TS, bits_type L, bits_type SS = 0, typename OT>
+        inline buffer& insert(const OT i_datain)
+        {
+            const bits_type target_length = parameterTraits<T>::bit_length();
+            const bits_type source_length = parameterTraits<OT>::bit_length();
+
+            // Error if input data don't make sense
+            static_assert((TS + L) <= target_length,
+                          "insert(): (Target Start + Len) is out of bounds");
+            static_assert((SS + L) <= source_length,
+                          "insert(): (Source Start + Len) is out of bounds");
+            static_assert(TS < target_length,
+                          "insert(): Target Start is out of bounds");
+            static_assert(SS < source_length,
+                          "insert(): Source Start is out of bounds");
+
+            // Normalize the input to 2 64 bit integers and adjust the starts accordingly
+            uint64_t source = static_cast<uint64_t>(i_datain);
+            const uint64_t target = static_cast<uint64_t>(iv_data);
+
+            const bits_type source_start = parameterTraits<uint64_t>::bit_length() - (source_length - SS);
+            const bits_type target_start = parameterTraits<uint64_t>::bit_length() - (target_length - TS);
+
+            // Get mask value for Target buffer
+            // Note: Need "& 0UL" because bit shift left for Target buffer doesn't roll off
+            uint64_t mask = ((~0UL << (parameterTraits<uint64_t>::bit_length() - L)) & ~0UL) >> target_start;
+
+            // Align the source to the target. Make things signed so we know which way to shift.
+            int32_t shift = source_start - target_start;
+            if (shift > 0)
+            {
+                source <<= shift;
+            }
+            else
+            {
+                shift = target_start - source_start;
+                source >>= shift;
+            }
+
+            iv_data = ((target & ~mask) | (source & mask));
+            return *this;
+        }
+
+        ///
+        /// @brief Copy part of a OT into the DataBuffer
+        /// @tparam OT the type of the incoming (origin) data
+        /// @param[in] i_datain OT value to copy into DataBuffer
+        ///    - data is taken left aligned
+        /// @param[in] Start bit to insert into (target start)
+        /// @param[in] Length of bits to insert
+        /// @param[in] Start bit in source - defaults to bit 0
+
+        /// @return FAPI2_RC_SUCCESS if successful
+        ///
+        template<typename OT>
+        fapi2::ReturnCode insert(const OT i_datain, const bits_type i_targetStart,
+                                 const bits_type i_len, const bits_type i_sourceStart = 0)
+        {
+            const bits_type target_length = parameterTraits<T>::bit_length();
+            const bits_type source_length = parameterTraits<OT>::bit_length();
+
+            // Error if input data don't make sense
+            if ((i_targetStart + i_len) > target_length)
+            {
+                FAPI_ERR("insert(): (Target Start + Len) is out of bounds");
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            if ((i_sourceStart + i_len) > source_length)
+            {
+                FAPI_ERR("insert(): (Source Start + Len) is out of bounds");
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            if (i_targetStart >= target_length)
+            {
+                FAPI_ERR("insert(): Target Start is out of bounds");
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            if (i_sourceStart >= source_length)
+            {
+                FAPI_ERR("insert(): Source Start is out of bounds");
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            // Normalize the input to 2 64 bit integers and adjust the starts accordingly
+            uint64_t source = static_cast<uint64_t>(i_datain);
+            const uint64_t target = static_cast<uint64_t>(iv_data);
+
+            const bits_type source_start = parameterTraits<uint64_t>::bit_length() - (source_length - i_sourceStart);
+            const bits_type target_start = parameterTraits<uint64_t>::bit_length() - (target_length - i_targetStart);
+
+            // Get mask value for Target buffer
+            // Note: Need "& 0UL" because bit shift left for Target buffer doesn't roll off
+            uint64_t mask = ((~0UL << (parameterTraits<uint64_t>::bit_length() - i_len)) & ~0UL) >> target_start;
+
+            // Align the source to the target. Make things signed so we know which way to shift.
+            int32_t shift = source_start - target_start;
+            if (shift > 0)
+            {
+                source <<= shift;
+            }
+            else
+            {
+                shift = target_start - source_start;
+                source >>= shift;
+            }
+
+            iv_data = ((target & ~mask) | (source & mask));
+            return FAPI2_RC_SUCCESS;
+        }
+
+        ///
+        /// @brief Copy in a right aligned value
+        /// @tparam SB Start bit to insert into
+        /// @tparam L Length of bits to insert
+        /// @tparam OT the type of the incoming (origin) data
+        /// @param[in] i_datain OT value to copy into DataBuffer
+        ///    - data is taken right aligned
+        /// @return buffer& Useful for method chaining
+        /// @note Data is assumed to be aligned on the word boundary of L
+        ///
+        template<bits_type TS, bits_type L, typename OT>
+        inline buffer& insertFromRight(const OT i_datain)
+        {
+            // Error if input data don't make sense
+            static_assert(L <= parameterTraits<OT>::bit_length(),
+                          "insertFromRight(): Len > input buffer");
+            static_assert(TS < parameterTraits<T>::bit_length(),
+                          "insertFromRight(): Target Start is out of bounds");
+            static_assert((TS + L) <= parameterTraits<T>::bit_length(),
+                          "InsertFromRight(): (Target Start + Len) is out of bounds");
+
+            this->insert<TS, L, parameterTraits<OT>::bit_length() - L>(i_datain);
+            return *this;
+        }
+
+        ///
+        /// @brief Copy in a right aligned value
+        /// @tparam OT the type of the incoming (origin) data
+        /// @param[in] i_datain OT value to copy into DataBuffer
+        ///    - data is taken right aligned
+        /// @param[in] Start bit to insert into
+        /// @param[in] Length of bits to insert
+        /// @return FAPi2_RC_SUCCESS if no error
+        /// @note Data is assumed to be aligned on the word boundary of L
+        ///
+        template<typename OT>
+        fapi2::ReturnCode insertFromRight(const OT i_datain, const bits_type i_targetStart,
+                                          const bits_type i_len)
+        {
+            // Error if input data don't make sense
+            if ((i_targetStart + i_len) > parameterTraits<T>::bit_length())
+            {
+                FAPI_ERR("insertFromRight(): (Target Start + Len) is out of bounds");
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            if (i_targetStart >= parameterTraits<T>::bit_length())
+            {
+                FAPI_ERR("insertFromRight(): Target Start is out of bounds");
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            if (i_len > parameterTraits<OT>::bit_length())
+            {
+                FAPI_ERR("insertFromRight(): Len > input buffer");
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            return this->insert(i_datain, i_targetStart, i_len, parameterTraits<OT>::bit_length() - i_len);
+        }
+
+        ///
+        /// @brief Copy data from this buffer into an OT
+        /// @tparam SS Start bit in source
+        /// @tparam L Length of bits to insert
+        /// @tparam TS Start bit to insert into (target start)
+        /// @tparam OT the type of the outgoing (target)
+        /// @param[out] o_out OT to copy into - data is placed left aligned
+        /// @return buffer& Useful for method chaining
+        ///
+        template<bits_type SS, bits_type L, bits_type TS = 0, typename OT>
+        inline buffer& extract(OT& o_out)
+        {
+            // Extraction is just an insert into o_out
+
+            buffer<OT> out(o_out);
+            out.insert<TS, L, SS>(iv_data);
+            o_out = out;
+            return *this;
+        }
+
+        ///
+        /// @brief Copy data from this buffer into an OT
+        /// @tparam OT the type of the outgoing (target)
+        /// @param[out] o_out OT to copy into - data is placed left aligned
+        /// @param[in] Start bit in source
+        /// @param[in] Length of bits to extract
+        /// @param[in] Start bit to insert into (target start)
+        /// @return FAPI2_RC_SUCCESS if ok
+        ///
+        template<typename OT>
+        fapi2::ReturnCode extract(OT& o_out, const bits_type i_sourceStart,
+                                  const bits_type i_len, const bits_type i_targetStart = 0)
+        {
+            // Extraction is just an insert into o_out
+
+            buffer<OT> out(o_out);
+            if (out.insert(iv_data, i_targetStart, i_len, i_sourceStart) != FAPI2_RC_SUCCESS)
+            {
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            o_out = out;
+            return FAPI2_RC_SUCCESS;
+        }
+
+        ///
+        /// @brief Copy data from this buffer into an OT and right justify
+        /// @tparam SS Start bit to insert into (source start)
+        /// @tparam L Length of bits to extract
+        /// @tparam OT the type of the outgoing (target)
+        /// @param[out] o_out OT to copy into - data is placed right aligned
+        /// @return buffer& Useful for method chaining
+        ///
+        template<bits_type SS, bits_type L, typename OT>
+        inline buffer& extractToRight(OT& o_out)
+        {
+            extract<SS, L, parameterTraits<OT>::bit_length() - L>(o_out);
+            return *this;
+        }
+
+        ///
+        /// @brief Copy data from this buffer into an OT and right justify
+        /// @tparam OT the type of the outgoing (target)
+        /// @param[out] o_out OT to copy into - data is placed right aligned
+        /// @param[in] Start bit to insert into (source start)
+        /// @param[in] Length of bits to insert
+        /// @return FAPI2_RC_SUCCESS if ok
+        ///
+        template<typename OT>
+        fapi2::ReturnCode extractToRight(OT& o_out, const bits_type i_sourceStart,
+                                         const bits_type i_len)
+        {
+            return extract(o_out, i_sourceStart, i_len, parameterTraits<OT>::bit_length() - i_len);
+        }
+
+        ///@}
+
+    private:
+        /// The contents of the buffer
+        T iv_data;
+    };
+}
+
+#endif
diff --git a/src/ppe/importtemp/fapi2/include/buffer_parameters.H b/src/ppe/importtemp/fapi2/include/buffer_parameters.H
new file mode 100644
index 0000000..f4dbf27
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/buffer_parameters.H
@@ -0,0 +1,70 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/buffer_parameters.H $        */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file buffer_parameters.H
+ * @brief definitions for fapi2 buffer parameter types
+ */
+
+#ifndef __FAPI2_BUFFER_PARAM__
+#define __FAPI2_BUFFER_PARAM__
+
+#include <stdint.h>
+
+namespace fapi2
+{
+    /// @cond
+    /// @brief Traits of buffer parameters - things passed in
+    /// @tparam T is the type of i_value (typically an integral type)
+    template<typename T>
+    class parameterTraits
+    {
+    public:
+        // Why constexpr functions? Enums are hard to do math on, and
+        // static const doesn't work without -O1 (or greater.) That might
+        // be a bug in g++ but this works just the same.
+        constexpr static T mask(void)
+            { return T(~0); }
+
+        constexpr static uint32_t byte_length(void)
+            { return sizeof(T); }
+
+        constexpr static uint32_t bit_length(void)
+            { return sizeof(T) * 8; }
+
+        template<typename U>
+        inline static void write_element(void* i_data, T i_value, uint32_t i_offset)
+        {
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+            T* ptr = (T*)i_data + (i_offset ^ ((sizeof(U) / sizeof(T)) - 1));
+#else
+            T* ptr = (T*)i_data + i_offset;
+#endif
+            *ptr = i_value;
+        }
+    };
+    /// @endcond
+}
+
+#endif
diff --git a/src/ppe/importtemp/fapi2/include/buffer_traits.H b/src/ppe/importtemp/fapi2/include/buffer_traits.H
new file mode 100644
index 0000000..795cb8c
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/buffer_traits.H
@@ -0,0 +1,240 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/buffer_traits.H $            */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file buffer_traits.H
+ * @brief trait definitions for fapi2 buffer base class
+ */
+
+#ifndef __FAPI2_BUFFER_TRAITS__
+#define __FAPI2_BUFFER_TRAITS__
+
+#include <stdint.h>
+#include <vector>
+#include <algorithm>
+#include <buffer_parameters.H>
+
+#ifdef FAPI2_DEBUG
+#include <iostream>
+#endif
+
+#include <iterator>
+
+namespace fapi2
+{
+    /// @cond
+    /// Types representing a container of bits. Used to create
+    /// variable_buffer. container_unit must remain 32-bits
+    /// for now - there will be a lot of code to change if it
+    /// changes. There are assertions helping to enforce this
+    /// in places in the code.
+    typedef uint32_t container_unit;
+    typedef std::vector<container_unit> bits_container;
+
+    /// @brief Traits of buffers
+    // In general, we try to give buffers traits reflecting integral types. If
+    // this fails, the compiler will let someone know.
+    ///
+    /// @tparam T is the type of iv_data (std::vector, etc)
+    /// @tparam B is the type of the bit-specifier, typically uint32_t
+    template<typename T, typename B = uint32_t>
+    class bufferTraits
+    {
+    public:
+
+#if !defined(DOXYGEN) && defined(FAPI2_DEBUG)
+        ///
+        /// @brief Print a container of bits
+        /// @param[in] i_data the container of bits
+        ///
+        static inline void print(const T& i_data)
+        {
+            // convert to uint64_t to prevent uint8_t from being
+            // printed as a char.
+            std::cout << "\tdata is "
+                      << std::hex
+                      << static_cast<uint64_t>(i_data)
+                      << std::dec << std::endl;
+        }
+#endif
+
+        ///
+        /// @brief Return the size of the buffer in E units
+        /// @tparam E, the element size.
+        /// @param[in] io_buffer the buffer which to size
+        /// @return The size of the buffer in E's rounded up
+        ///
+        template<typename E>
+        constexpr static B size(const T& i_buffer)
+            {
+                return (bit_length(i_buffer) +
+                        (parameterTraits<E>::bit_length() - 1)) /
+                    parameterTraits<E>::bit_length();
+            }
+
+        ///
+        /// @brief Return the size of the buffer itself
+        /// @param[in] io_buffer the buffer which to size
+        /// @return The size of the buffer in bits (not units)
+        ///
+        constexpr static B bit_length(const T&)
+            { return sizeof(T) * 8; }
+
+        ///
+        /// @brief Clear the buffer
+        /// @param[in,out] io_buffer the buffer which to clear
+        ///
+        static inline void clear(T& io_buffer)
+            { io_buffer = static_cast<T>(0); }
+
+        ///
+        /// @brief Set the buffer
+        /// @param[in,out] io_buffer the buffer which to set
+        ///
+        static inline void set(T& io_buffer)
+            { io_buffer = static_cast<T>(~0); }
+
+        ///
+        /// @brief Invert the buffer
+        /// @param[in,out] io_buffer the buffer which to invert
+        ///
+        static inline void invert(T& io_buffer)
+            { io_buffer = ~io_buffer; }
+
+        ///
+        /// @brief Reverse the buffer
+        /// @param[in,out] io_buffer the buffer which to reverse
+        ///
+        static inline void reverse(T& io_buffer)
+            {
+                io_buffer =
+                    ((io_buffer & 0xAAAAAAAAAAAAAAAA) >> 1) |
+                    ((io_buffer & 0x5555555555555555) << 1);
+            }
+
+        ///
+        /// @brief Get the address of the buffer as an array
+        /// @param[in] i_buffer the buffer which to invert
+        /// @return The address of the first element of the buffer
+        ///
+        static inline void* get_address(T& i_buffer)
+            { return (void*)&i_buffer; }
+
+        typedef B bits_type;
+        typedef T unit_type;
+        constexpr static uint32_t bits_per_unit(void)
+            { return sizeof(unit_type) * 8; }
+    };
+
+    //
+    //
+    /// @brief Traits for buffers which are a container of bits
+    //
+    //
+    template<>
+    class bufferTraits<bits_container, uint32_t>
+    {
+    public:
+#if !defined(DOXYGEN) && defined(FAPI2_DEBUG)
+        ///
+        /// @brief Print a container of bits
+        /// @param[in] i_data the container of bits
+        ///
+        static inline void print(const bits_container& i_data)
+        {
+            std::cout << "\tdata is " << std::hex;
+            std::copy(i_data.begin(), i_data.end(),
+                      std::ostream_iterator<container_unit>(std::cout, " "));
+            std::cout << std::dec << std::endl;
+        }
+#endif
+
+        ///
+        /// @brief Return the size of the buffer in E units
+        /// @tparam E, the element size.
+        /// @param[in] io_buffer the buffer which to size
+        /// @return The size of the buffer in E's rounded up
+        ///
+        template<typename E>
+        constexpr static uint32_t size(const bits_container& i_buffer)
+            {
+                return (bit_length(i_buffer) +
+                        (parameterTraits<E>::bit_length() - 1)) /
+                    parameterTraits<E>::bit_length();
+            }
+
+        ///
+        /// @brief Return the size of the buffer itself
+        /// @param[in,out] io_buffer the buffer which to size
+        /// @return The size of the buffer in bits (not units)
+        ///
+        static inline uint32_t bit_length(const bits_container& i_buffer)
+            { return i_buffer.size() * sizeof(container_unit) * 8; }
+
+        ///
+        /// @brief Clear the buffer
+        /// @param[in,out] io_buffer the buffer which to clear
+        ///
+        static inline void clear(bits_container& io_buffer)
+            { io_buffer.assign(io_buffer.size(), 0); }
+
+        ///
+        /// @brief Set the buffer
+        /// @param[in,out] io_buffer the buffer which to set
+        ///
+        static inline void set(bits_container& io_buffer)
+            { io_buffer.assign(io_buffer.size(), ~0); }
+
+        ///
+        /// @brief Invert the buffer
+        /// @param[in,out] io_buffer the buffer which to invert
+        ///
+        static inline void invert(bits_container& io_buffer)
+            {
+                std::transform(io_buffer.begin(), io_buffer.end(),
+                               io_buffer.begin(),
+                               [](container_unit u) { return ~u; });
+            }
+
+        ///
+        /// @brief Get the address of the buffer as an array
+        /// @param[in] i_buffer the buffer which to invert
+        /// @return The address of the first element of the buffer
+        ///
+        static inline void* get_address(bits_container& i_buffer)
+            {
+                return (void*)&(i_buffer[0]);
+            }
+
+        typedef uint32_t bits_type;
+        typedef container_unit unit_type;
+        constexpr static uint32_t bits_per_unit(void)
+            { return sizeof(unit_type) * 8; }
+    };
+    /// @endcond
+}
+
+
+
+#endif
diff --git a/src/ppe/importtemp/fapi2/include/collect_reg_ffdc.H b/src/ppe/importtemp/fapi2/include/collect_reg_ffdc.H
new file mode 100644
index 0000000..8f5f5d6
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/collect_reg_ffdc.H
@@ -0,0 +1,80 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/collect_reg_ffdc.H $         */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ *  @file collect_reg_ffdc.H
+ *
+ *  @brief Defines the collectRegFfdc function that collects chip or
+ *         chiplet register FFDC data. This is called automatically by
+ *         FAPI_SET_HWP_ERROR (when a HWP creates an error) and
+ *         FAPI_ADD_INFO_TO_HWP_ERROR (when an FFDC HWP adds error information
+ *         to an existing error) if the error XML contains a
+ *         <collectRegisterFfdc> element. This function should not be called
+ *         directly by any user code. The function implementation is
+ *         automatically generated from FAPI Error XML files.
+ */
+
+#ifndef FAPI2_COLLECT_REG_FFDC_H_
+#define FAPI2_COLLECT_REG_FFDC_H_
+
+#include <target.H>
+#include <return_code.H>
+#include <ffdc.H>
+#include <hwp_error_info.H>
+
+namespace fapi2
+{
+
+    ///
+    /// @brief Collects Register FFDC from a chip or chiplet
+    ///
+    /// @warning This should only be called by FAPI during FAPI_SET_HWP_ERROR or
+    /// FAPI_ADD_INFO_TO_HWP_ERROR
+    ///
+    /// @param[in]  i_target      Pointer to Target to collect FFDC from (ffdc_t.ptr())
+    /// @param[in]  i_ffdcId      FFDC Identifier
+    /// @param[out] o_rc          Reference to ReturnCode that FFDC is added to
+    /// @param[in]  i_child       Specifies type of i_target's chiplet to collect
+    ///                           FFDC from.  If this parameter is TARGET_TYPE_NONE
+    ///                           (default value), then register FFDC is collected
+    ///                           from i_target, else, register FFDC is collected
+    ///                           from all functional child chiplets i_target of
+    ///                           the specified type
+    /// @param[in]  i_presChild   When specified, register FFDC will be collected
+    ///                           from i_target's registers based on present chiplets
+    ///                           of this type.
+    /// @param[in]  i_childOffsetMult  Specifies the chiplet position offset multiplier.
+    ///                           This is used in calculating the scom register
+    ///                           addresses when collecting register FFDC based on
+    ///                           present child chiplets.
+    ///
+    void collectRegFfdc(const fapi2::ffdc_t& i_target,
+                        const fapi2::HwpFfdcId i_ffdcId,
+                        fapi2::ReturnCode & o_rc,
+                        const TargetType i_child = TARGET_TYPE_NONE,
+                        const TargetType i_presChild = TARGET_TYPE_NONE,
+                        uint32_t i_childOffsetMult = 0);
+}
+
+#endif
diff --git a/src/ppe/importtemp/fapi2/include/error_info.H b/src/ppe/importtemp/fapi2/include/error_info.H
new file mode 100644
index 0000000..8ad3aa5
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/error_info.H
@@ -0,0 +1,652 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/error_info.H $               */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file error_info.H
+/// @brief Defines the Error Information structures and classes
+///
+
+#ifndef FAPI2_ERRORINFO_H_
+#define FAPI2_ERRORINFO_H_
+
+#include <stdint.h>
+#include <memory>
+#include <vector>
+#include <target.H>
+#include <error_info_defs.H>
+
+namespace fapi2
+{
+    // forward fapi2::Assert()
+    extern void Assert(bool);
+
+    ///
+    /// @class ErrorInfoFfdc
+    ///
+    /// This class contains a copy of some FFDC data
+    ///
+    class ErrorInfoFfdc
+    {
+    public:
+        ///
+        /// @brief Constructor
+        ///
+        /// @param[in] i_ffdcId FFDC Identifier (used to decode FFDC)
+        /// @param[in] i_pFfdc  Pointer to the FFDC to copy
+        /// @param[in] i_size   Size of the FFDC to copy
+        ///
+        ErrorInfoFfdc(const uint32_t i_ffdcId,
+                      const void*    i_pFfdc,
+                      const uint32_t i_size);
+
+        ///
+        /// @brief Get a pointer to the FfdcData
+        ///
+        /// @param[out] o_size Reference to uint32_t that is filled in with
+        /// the FFDC size
+        ///
+        /// @return void *. Pointer to the FFDC
+        ///
+        inline const void* getData(uint32_t & o_size) const
+            {
+                o_size = iv_size;
+                return iv_pFfdc.get();
+            }
+
+        ///
+        /// @brief Get a pointer to the FfdcData
+        /// @return void *. Pointer to the FFDC
+        ///
+        inline void* getData(void) const
+            { return iv_pFfdc.get(); }
+
+        ///
+        /// @brief Get the FFDC Identifier
+        ///
+        /// @return uint32_t The FFDC Identifier
+        ///
+        inline uint32_t getFfdcId(void)
+            { return iv_ffdcId; }
+
+#ifdef FAPI_CUSTOM_MALLOC
+        ///
+        /// @brief Overload new operator to use platform-specific allocator
+        ///
+        /// @param[in] i_sz  Size of memory to allocate in bytes
+        ///
+        /// @return  Pointer to allocated memory
+        ///
+        static void* operator new(size_t i_sz);
+
+        ///
+        /// @brief Overload delete operator to use platform-specific deallocator
+        ///
+        /// @param[in] i_ptr Pointer to memory previously allocated with new
+        ///
+        static void operator delete(void* i_ptr);
+#endif
+
+    private:
+
+        // FFDC Identifier
+        uint32_t iv_ffdcId;
+
+        // Pointer to the FFDC
+        std::shared_ptr<uint8_t> iv_pFfdc;
+
+        // Size of the FFDC
+        uint32_t iv_size;
+
+        // Disabled
+        ErrorInfoFfdc(const ErrorInfoFfdc &) = delete;
+        ErrorInfoFfdc & operator=(const ErrorInfoFfdc &) = delete;
+    };
+
+    ///
+    /// @struct ErrorInfoHwCallout
+    ///
+    /// This struct contains hardware to callout
+    ///
+    struct ErrorInfoHwCallout
+    {
+        ///
+        /// @brief Constructor.
+        ///
+        /// @param[in] i_hw              Hardware to callout
+        /// @param[in] i_calloutPriority Priority of callout
+        /// @param[in] i_refTarget       Reference to reference target
+        ///
+        ErrorInfoHwCallout(
+            const HwCallouts::HwCallout i_hw,
+            const CalloutPriorities::CalloutPriority i_calloutPriority,
+            const Target<TARGET_TYPE_ALL> & i_refTarget);
+
+#ifdef FAPI_CUSTOM_MALLOC
+        ///
+        /// @brief Overload new operator to use platform-specific allocator
+        ///
+        /// @param[in] i_sz  Size of memory to allocate in bytes
+        ///
+        /// @return  Pointer to allocated memory
+        ///
+        static void* operator new(size_t i_sz);
+
+        ///
+        /// @brief Overload delete operator to use platform-specific deallocator
+        ///
+        /// @param[in] i_ptr Pointer to memory previously allocated with new
+        ///
+        static void operator delete(void* i_ptr);
+#endif
+
+        // The hw to callout
+        HwCallouts::HwCallout iv_hw;
+
+        // The callout priority
+        CalloutPriorities::CalloutPriority iv_calloutPriority;
+
+        // The reference target (needed for some HW callouts to identify what to
+        // callout). The target handle is NULL if there is no reference target.
+        Target<TARGET_TYPE_ALL> iv_refTarget;
+    };
+
+    ///
+    /// @struct ErrorInfoProcedureCallout
+    ///
+    /// This struct contains a procedure to callout
+    ///
+    struct ErrorInfoProcedureCallout
+    {
+        ///
+        /// @brief Constructor.
+        ///
+        /// @param[in] i_procedure        Procedure to callout
+        /// @param[in] i_calloutPriority  Priority of callout
+        ///
+        ErrorInfoProcedureCallout(
+            const ProcedureCallouts::ProcedureCallout i_procedure,
+            const CalloutPriorities::CalloutPriority i_calloutPriority);
+
+#ifdef FAPI_CUSTOM_MALLOC
+        ///
+        /// @brief Overload new operator to use platform-specific allocator
+        ///
+        /// @param[in] i_sz  Size of memory to allocate in bytes
+        ///
+        /// @return  Pointer to allocated memory
+        ///
+        static void* operator new(size_t i_sz);
+
+        ///
+        /// @brief Overload delete operator to use platform-specific deallocator
+        ///
+        /// @param[in] i_ptr Pointer to memory previously allocated with new
+        ///
+        static void operator delete(void* i_ptr);
+#endif
+
+        // The procedure to callout
+        ProcedureCallouts::ProcedureCallout iv_procedure;
+
+        // The callout priority
+        CalloutPriorities::CalloutPriority iv_calloutPriority;
+    };
+
+    ///
+    /// @struct ErrorInfoBusCallout
+    ///
+    /// This struct contains a bus to callout
+    ///
+    struct ErrorInfoBusCallout
+    {
+        ///
+        /// @brief Constructor.
+        ///
+        /// @param[in] i_target1          Reference to target on one end of the bus
+        /// @param[in] i_target2          Reference to target on other end of the bus
+        /// @param[in] i_calloutPriority  Priority of callout
+        ///
+        ErrorInfoBusCallout(
+            const Target<TARGET_TYPE_ALL> & i_target1,
+            const Target<TARGET_TYPE_ALL> & i_target2,
+            const CalloutPriorities::CalloutPriority i_calloutPriority);
+
+#ifdef FAPI_CUSTOM_MALLOC
+        ///
+        /// @brief Overload new operator to use platform-specific allocator
+        ///
+        /// @param[in] i_sz  Size of memory to allocate in bytes
+        ///
+        /// @return  Pointer to allocated memory
+        ///
+        static void* operator new(size_t i_sz);
+
+        ///
+        /// @brief Overload delete operator to use platform-specific deallocator
+        ///
+        /// @param[in] i_ptr Pointer to memory previously allocated with new
+        ///
+        static void operator delete(void* i_ptr);
+#endif
+
+        // The targets on each end of the bus to callout
+        Target<TARGET_TYPE_ALL> iv_target1;
+        Target<TARGET_TYPE_ALL> iv_target2;
+
+        // The callout priority
+        CalloutPriorities::CalloutPriority iv_calloutPriority;
+    };
+
+    ///
+    /// @struct ErrorInfoCDG
+    ///
+    /// This struct contains a target to callout/deconfigure/GARD
+    ///
+    struct ErrorInfoCDG
+    {
+        ///
+        /// @brief Constructor.
+        ///
+        /// @param[in] i_target      Reference to the target to c/d/g
+        /// @param[in] i_callout     True if Target should be called out
+        /// @param[in] i_deconfigure True if Target should be deconfigured
+        /// @param[in] i_gard        True if Target should be GARDed
+        /// @param[in] i_priority    The priority of any callout
+        ///
+        ErrorInfoCDG(const Target<TARGET_TYPE_ALL> & i_target,
+                     const bool i_callout,
+                     const bool i_deconfigure,
+                     const bool i_gard,
+                     const CalloutPriorities::CalloutPriority i_priority);
+
+#ifdef FAPI_CUSTOM_MALLOC
+        ///
+        /// @brief Overload new operator to use platform-specific allocator
+        ///
+        /// @param[in] i_sz  Size of memory to allocate in bytes
+        ///
+        /// @return  Pointer to allocated memory
+        ///
+        static void* operator new(size_t i_sz);
+
+        ///
+        /// @brief Overload delete operator to use platform-specific deallocator
+        ///
+        /// @param[in] i_ptr Pointer to memory previously allocated with new
+        ///
+        static void operator delete(void* i_ptr);
+#endif
+
+        // The target to callout/deconfigure/GARD
+        Target<TARGET_TYPE_ALL> iv_target;
+
+        // Callout Information
+        bool iv_callout;
+        CalloutPriorities::CalloutPriority iv_calloutPriority;
+
+        // Deconfigure Information
+        bool iv_deconfigure;
+
+        // GARD Information
+        bool iv_gard;
+    };
+
+    ///
+    /// @struct ErrorInfoChildrenCDG
+    ///
+    /// This struct contains children targets to callout/deconfigure/GARD
+    ///
+    /// Children by containment can be CDG (chiplets belonging to a parent chip)
+    /// e.g.
+    /// - PROC_CHIP -> EX_CHIPLET
+    /// - MEMBUF_CHIP -> MBA_CHIPLET
+    /// Children by affinity can be CDG.
+    ///   Any from PROC_CHIP->MCS_CHIPLET->MEMBUF_CHIP->MBA_CHIPLET->DIMM e.g.
+    ///   - PROC_CHIP->MEMBUF_CHIP
+    ///   - MEMBUF_CHIP->DIMM
+    ///   - MBA_CHIPLET->DIMM
+    /// Port and Number criteria can be applied to the child target as
+    /// detailed in the constructor
+    ///
+    struct ErrorInfoChildrenCDG
+    {
+        ///
+        /// @brief Constructor.
+        ///
+        /// @param[in] i_parent      Reference to the parent target
+        /// @oaram[in] i_childType   Child target type to c/d/g
+        /// @param[in] i_callout     True if Target should be called out
+        /// @param[in] i_deconfigure True if Target should be deconfigured
+        /// @param[in] i_gard        True if Target should be GARDed
+        /// @param[in] i_priority    The priority of any callout
+        /// @param[in] i_childPort   Child Port
+        ///                            For DIMM children, the MBA port number
+        /// @param[in] i_childNum    Child Number
+        ///                            For DIMM children, the dimm socket number
+        ///                            For Chip children, the chip position
+        ///                            For Chiplet children, the chiplet unit pos
+        ///
+        ErrorInfoChildrenCDG(const Target<TARGET_TYPE_ALL> & i_parentChip,
+                             const TargetType i_childType,
+                             const bool i_callout,
+                             const bool i_deconfigure,
+                             const bool i_gard,
+                             const CalloutPriorities::CalloutPriority i_priority,
+                             const uint8_t i_childPort, const uint8_t i_childNum);
+
+#ifdef FAPI_CUSTOM_MALLOC
+        ///
+        /// @brief Overload new operator to use platform-specific allocator
+        ///
+        /// @param[in] i_sz  Size of memory to allocate in bytes
+        ///
+        /// @return  Pointer to allocated memory
+        ///
+        static void* operator new(size_t i_sz);
+
+        ///
+        /// @brief Overload delete operator to use platform-specific deallocator
+        ///
+        /// @param[in] i_ptr Pointer to memory previously allocated with new
+        ///
+        static void operator delete(void* i_ptr);
+#endif
+
+        // The parent chip
+        Target<TARGET_TYPE_ALL> iv_parent;
+
+        // The child target types to c/d/g
+        TargetType iv_childType;
+
+        // Callout Information
+        bool iv_callout;
+        CalloutPriorities::CalloutPriority iv_calloutPriority;
+
+        // Deconfigure Information
+        bool iv_deconfigure;
+
+        // GARD Information
+        bool iv_gard;
+
+        // Child Port
+        static const uint8_t ALL_CHILD_PORTS = 0xff;
+        uint8_t iv_childPort;
+
+        // Child Number
+        static const uint8_t ALL_CHILD_NUMBERS = 0xff;
+        uint8_t iv_childNumber;
+    };
+
+    ///
+    /// @struct ErrorInfoCollectTrace
+    ///
+    /// This struct contains trace ID to add to the error log
+    ///
+    struct ErrorInfoCollectTrace
+    {
+        ///
+        /// @brief Constructor.
+        ///
+        /// @param[in] i_trace
+        ///
+        ErrorInfoCollectTrace(CollectTraces::CollectTrace i_traceId);
+
+
+#ifdef FAPI_CUSTOM_MALLOC
+        ///
+        /// @brief Overload new operator to use platform-specific allocator
+        ///
+        /// @param[in] i_sz  Size of memory to allocate in bytes
+        ///
+        /// @return  Pointer to allocated memory
+        ///
+        static void* operator new(size_t i_sz);
+
+        ///
+        /// @brief Overload delete operator to use platform-specific deallocator
+        ///
+        /// @param[in] i_ptr Pointer to memory previously allocated with new
+        ///
+        static void operator delete(void* i_ptr);
+#endif
+
+        // trace
+        CollectTraces::CollectTrace iv_eiTraceId;
+    };
+
+   ///
+   /// @struct ErrorInfo
+   ///
+   /// This struct defines the error information associated with a fapi2::ffdc
+   /// Users are allowed to access the data directly
+   ///
+    struct ErrorInfo
+    {
+
+#ifdef FAPI_CUSTOM_MALLOC
+        ///
+        /// @brief Overload new operator to use platform-specific allocator
+        ///
+        /// @param[in] i_sz  Size of memory to allocate in bytes
+        ///
+        /// @return  Pointer to allocated memory
+        ///
+        static void* operator new(size_t i_sz);
+
+        ///
+        /// @brief Overload delete operator to use platform-specific deallocator
+        ///
+        /// @param[in] i_ptr Pointer to memory previously allocated with new
+        ///
+        static void operator delete(void* i_ptr);
+#endif
+
+        // Vector of FFDC Data
+        std::vector<std::shared_ptr<ErrorInfoFfdc> > iv_ffdcs;
+
+        // Vector of Hardware to callout
+        std::vector<std::shared_ptr<ErrorInfoHwCallout> > iv_hwCallouts;
+
+        // Vector of procedures to callout
+        std::vector<std::shared_ptr<ErrorInfoProcedureCallout> >
+          iv_procedureCallouts;
+
+        // Vector of buses to callout
+        std::vector<std::shared_ptr<ErrorInfoBusCallout> > iv_busCallouts;
+
+        // Vector of targets to callout/deconfigure/GARD
+        std::vector<std::shared_ptr<ErrorInfoCDG> > iv_CDGs;
+
+        // Vector of children targets to callout/deconfigure/GARD
+        std::vector<std::shared_ptr<ErrorInfoChildrenCDG> > iv_childrenCDGs;
+
+        // Vector of traces to collect
+        std::vector<std::shared_ptr<ErrorInfoCollectTrace> > iv_traces;
+    };
+
+    ///
+    /// @brief Structure representing a single ErrorInfo entry.
+    ///
+    /// An array of these is passed to the addErrorInfo function when a HWP
+    /// generates an error by calling the FAPI_SET_HWP_ERROR macro
+    // Why aren't these inherited classes? Saves on allocation overhead.
+    // We create an array of ErrorInfoEntries as automatics when we start
+    // FFDC collection. If we did this as inherited classes it would either
+    // be allocating and deallocating or we'd need to allocate an array of
+    // the largest and map each struct in to it. That's messy to do without
+    // unions (that's what they're for) so we do it like this. The inherited
+    // model would result in a jump table anyway, so we're basically doing
+    // all of that by hand to avoid the mess.
+    //
+    struct ErrorInfoEntryFfdc
+    {
+        uint8_t  iv_ffdcObjIndex;
+        uint16_t iv_ffdcSize;
+        uint32_t iv_ffdcId;
+        void addErrorInfo(std::shared_ptr<ErrorInfo> i_info,
+                          const void* const* i_object) const;
+    };
+
+    ///
+    /// @brief Structure representing a hardware callout
+    ///
+    struct ErrorInfoEntryHwCallout
+    {
+        uint8_t iv_hw;
+        uint8_t iv_calloutPriority;
+        uint8_t iv_refObjIndex;
+        void addErrorInfo(std::shared_ptr<ErrorInfo> i_info,
+                          const void* const* i_object) const;
+    };
+
+    ///
+    /// @brief Structure representing a procedure callout
+    ///
+    struct ErrorInfoEntryProcCallout
+    {
+        uint8_t iv_procedure;
+        uint8_t iv_calloutPriority;
+        void addErrorInfo(std::shared_ptr<ErrorInfo> i_info,
+                          const void* const* i_object) const;
+
+        ErrorInfoEntryProcCallout(uint8_t i_procedure, uint8_t i_calloutPriority):
+            iv_procedure(i_procedure),
+            iv_calloutPriority(i_calloutPriority)
+            {}
+
+        ErrorInfoEntryProcCallout(void) = default;
+    };
+
+    ///
+    /// @brief Structure representing a bus callout
+    ///
+    struct ErrorInfoEntryBusCallout
+    {
+        uint8_t iv_endpoint1ObjIndex;
+        uint8_t iv_endpoint2ObjIndex;
+        uint8_t iv_calloutPriority;
+        void addErrorInfo(std::shared_ptr<ErrorInfo> i_info,
+                          const void* const* i_object) const;
+    };
+
+    ///
+    /// @brief Structure representing a target callout
+    ///
+    struct ErrorInfoEntryTargetCDG
+    {
+        uint8_t iv_targetObjIndex;
+        uint8_t iv_callout;
+        uint8_t iv_deconfigure;
+        uint8_t iv_gard;
+        uint8_t iv_calloutPriority;
+        void addErrorInfo(std::shared_ptr<ErrorInfo> i_info,
+                          const void* const* i_object) const;
+    };
+
+    ///
+    /// @brief Structure representing a child callout
+    ///
+    struct ErrorInfoEntryChildrenCDG
+    {
+        uint8_t  iv_parentObjIndex;
+        uint8_t  iv_callout;
+        uint8_t  iv_deconfigure;
+        uint32_t iv_childType;
+        uint8_t  iv_childPort;
+        uint8_t  iv_childNumber;
+        uint8_t  iv_gard;
+        uint8_t  iv_calloutPriority;
+        void addErrorInfo(std::shared_ptr<ErrorInfo> i_info,
+                          const void* const* i_object) const;
+    };
+
+    ///
+    /// @brief Structure representing collected trace information
+    ///
+    struct ErrorInfoEntryCollectTrace
+    {
+        uint32_t  iv_eieTraceId;
+        void addErrorInfo(std::shared_ptr<ErrorInfo> i_info,
+                          const void* const* i_object) const;
+    };
+
+    ///
+    /// @brief Union of all the error info types
+    ///
+    struct ErrorInfoEntry
+    {
+        uint8_t iv_type; // Value from ErrorInfoType
+        union
+        {
+            ErrorInfoEntryFfdc ffdc;
+            ErrorInfoEntryHwCallout hw_callout;
+            ErrorInfoEntryProcCallout proc_callout;
+            ErrorInfoEntryBusCallout bus_callout;
+            ErrorInfoEntryTargetCDG target_cdg;
+            ErrorInfoEntryChildrenCDG children_cdg;
+            ErrorInfoEntryCollectTrace collect_trace;
+        };
+
+        ///
+        /// @brief Add error information to the FFDC object
+        /// @param[in] i_info a shared pointer to the error info
+        /// @param[in] i_object the list of ffdc objects being collected
+        ///
+        void addErrorInfo(std::shared_ptr<ErrorInfo> i_info,
+                          const void* const* i_object) const
+            {
+                // "unhandled error info type");
+                fapi2::Assert(iv_type < EI_LAST_TYPE);
+
+                switch(iv_type)
+                {
+                case EI_TYPE_FFDC:
+                    ffdc.addErrorInfo(i_info, i_object);
+                    break;
+                case EI_TYPE_HW_CALLOUT:
+                    hw_callout.addErrorInfo(i_info, i_object);
+                    break;
+                case EI_TYPE_PROCEDURE_CALLOUT:
+                    proc_callout.addErrorInfo(i_info, i_object);
+                    break;
+                case EI_TYPE_BUS_CALLOUT:
+                    bus_callout.addErrorInfo(i_info, i_object);
+                    break;
+                case EI_TYPE_CDG:
+                    target_cdg.addErrorInfo(i_info, i_object);
+                    break;
+                case EI_TYPE_CHILDREN_CDG:
+                    children_cdg.addErrorInfo(i_info, i_object);
+                    break;
+                case EI_TYPE_COLLECT_TRACE:
+                    collect_trace.addErrorInfo(i_info, i_object);
+                    break;
+                };
+                return;
+            }
+    };
+}
+
+#endif // FAPI2_ERRORINFO_H_
diff --git a/src/ppe/importtemp/fapi2/include/error_info_defs.H b/src/ppe/importtemp/fapi2/include/error_info_defs.H
new file mode 100644
index 0000000..18bfe92
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/error_info_defs.H
@@ -0,0 +1,249 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/error_info_defs.H $          */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file error_info_defs.H
+/// @brief Defines to support the Error Information class
+///
+
+#ifndef FAPI2_ERRORINFO_DEFS_H_
+#define FAPI2_ERRORINFO_DEFS_H_
+
+#include <stdint.h>
+#include <target.H>
+//#include <variable_buffer.H>
+
+//#include <iostream>
+
+namespace fapi2
+{
+    ///
+    /// @brief Type to hold the ffdc element in the ffdc class
+    /// Needed so that the size can be squirled away before the
+    /// macro is called.
+    ///
+    class ffdc_t
+    {
+    public:
+        ffdc_t(void)
+            {}
+
+        operator const void*() const { return iv_value.first; }
+        operator uint8_t() const
+            { return *(reinterpret_cast<const uint8_t*>(iv_value.first)); }
+
+        int16_t size(void) const { return iv_value.second; }
+        int16_t& size(void) { return iv_value.second; }
+
+        const void* ptr(void) const { return iv_value.first; }
+        const void*& ptr(void) { return iv_value.first; }
+
+    private:
+        std::pair<const void*, int16_t> iv_value;
+    };
+
+    ///
+    /// @brief Enumeration of ErrorInfo FFDC sizes that are used to indicate a
+    ///        special type that cannot simply be memcopied
+    enum ErrorInfoFfdcSize
+    {
+        EI_FFDC_SIZE_BUF    = 0xffff,   // fapi2::buffer<T>
+        EI_FFDC_SIZE_TARGET = 0xfffe,   // fapi2::Target
+        EI_FFDC_SIZE_VBUF   = 0xfffd,   // fapi2::variable_buffer
+        EI_FFDC_MAX_SIZE    = 0x1000,   // Limit regular FFDC capture to 4kb
+    };
+
+    ///
+    /// @brief Enumeration of error log severity.
+    ///
+    enum errlSeverity_t
+    {
+        FAPI2_ERRL_SEV_UNDEFINED     = 0x00, /// Used internally by ffdc mechanism
+        FAPI2_ERRL_SEV_RECOVERED     = 0x10, /// Not seen by customer
+        FAPI2_ERRL_SEV_PREDICTIVE    = 0x20, /// Error recovered but customer will see
+        FAPI2_ERRL_SEV_UNRECOVERABLE = 0x40  /// Unrecoverable, general
+    };
+
+    ///
+    /// @brief Enumeration of ErrorInfo types
+    ///
+    enum ErrorInfoType
+    {
+        EI_TYPE_FFDC              = 0,
+        EI_TYPE_HW_CALLOUT        = 1,
+        EI_TYPE_PROCEDURE_CALLOUT = 2,
+        EI_TYPE_BUS_CALLOUT       = 3,
+        EI_TYPE_CDG               = 4, // Target Callout/Deconfig/GARD
+        EI_TYPE_CHILDREN_CDG      = 5, // Children Callout/Deconfig/GARD
+        EI_TYPE_COLLECT_TRACE     = 6,
+        EI_LAST_TYPE              = EI_TYPE_COLLECT_TRACE + 1,
+    };
+
+    ///
+    /// @enum HwCallout
+    ///
+    /// This enumeration defines the possible Hardware Callouts that are not
+    /// represented by fapi2::Targets
+    ///
+    /// Note that platform code may depend on the enum values starting at 0 and
+    /// incrementing in order to efficiently convert to a platform callout value
+    /// so do not reorder without consulting all platforms
+    ///
+    namespace HwCallouts
+    {
+        enum HwCallout
+        {
+            // Where indicated, a HW Callout in FAPI Error XML must include a
+            // reference target that is used to identify the HW. e.g. for
+            // TOD_CLOCK, the proc chip that the clock is attached to must be
+            // specified
+            TOD_CLOCK           = 0, // Include proc-chip ref (or child chiplet)
+            MEM_REF_CLOCK       = 1, // Include membuf-chip ref (or child chiplet)
+            PROC_REF_CLOCK      = 2, // Include proc-chip ref (or child chiplet)
+            PCI_REF_CLOCK       = 3, // Include proc-chip ref (or child chiplet)
+            FLASH_CONTROLLER_PART      = 4,
+            PNOR_PART                  = 5,
+            SBE_SEEPROM_PART           = 6,
+            VPD_PART                   = 7,
+            LPC_SLAVE_PART             = 8,
+            GPIO_EXPANDER_PART         = 9,
+            SPIVID_SLAVE_PART          = 10,
+        };
+    }
+
+    ///
+    /// @enum ProcedureCallout
+    ///
+    /// This enumeration defines the possible Procedure Callouts
+    /// These instruct the customer/customer-engineer what to do
+    ///
+    /// Note that platform code may depend on the enum values starting at 0 and
+    /// incrementing in order to efficiently convert to a platform callout value
+    /// so do not reorder without consulting all platforms
+    ///
+    namespace ProcedureCallouts
+    {
+        enum ProcedureCallout
+        {
+            CODE                  = 0, // Code problem
+            LVL_SUPPORT           = 1, // Call next level of support
+            MEMORY_PLUGGING_ERROR = 2, // DIMM Plugging error
+            BUS_CALLOUT           = 3, // Bus Called Out
+        };
+    }
+
+    ///
+    /// @enum CalloutPriority
+    ///
+    /// This enumeration defines the possible Procedure and Target callout priorities
+    ///
+    /// Note that platform code may depend on the enum values starting at 0 and
+    /// incrementing in order to efficiently convert to a platform priority value
+    /// so do not reorder without consulting all platforms
+    ///
+    namespace CalloutPriorities
+    {
+        enum CalloutPriority
+        {
+            LOW = 0,
+            MEDIUM = 1,
+            HIGH   = 2,
+        };
+    }
+
+    ///
+    /// @enum Collect Trace
+    ///
+    /// This enumeration defines the possible firmware traces to collect
+    ///
+    namespace CollectTraces
+    {
+        const uint32_t TRACE_SIZE = 256; // limit collected trace size
+        enum CollectTrace
+        {
+            FSI              = 1,
+            SCOM             = 2,
+            SCAN             = 3,
+            MBOX             = 4,
+        };
+    }
+
+    ///
+    /// @brief Get FFDC Size
+    ///
+    /// This is called by the FAPI_SET_HWP_ERROR macro to find out the size of
+    /// FFDC data. If the data is of a special type that is handled differently
+    /// than types that are simply memcopied then it is handled by a template
+    /// specialization.
+    /// If this function template is instantiated with a pointer, the compile
+    /// will fail.
+    ///
+    /// @return uint16_t. Size of the FFDC data
+    ///
+    template<typename T>
+    inline uint16_t getErrorInfoFfdcSize(const T &)
+    {
+        static_assert(sizeof(T) <= EI_FFDC_MAX_SIZE,
+                      "FFDC too large to capture");
+        return sizeof(T);
+    }
+
+    ///
+    /// @brief Compile error if caller tries to get the FFDC size of a pointer
+    ///
+    template<typename T>
+    inline uint16_t getErrorInfoFfdcSize(const T*)
+    {
+        static_assert(std::is_pointer<T>::value,
+                      "pointer passed to getErrorInfoFfdcSize");
+        return 0;
+    }
+
+    ///
+    /// @brief Get FFDC Size specialization for fapi2::Target
+    ///
+    template<fapi2::TargetType T>
+    inline uint16_t getErrorInfoFfdcSize(const fapi2::Target<T>&)
+    {
+        return EI_FFDC_SIZE_TARGET;
+    }
+
+    // Comment out this code temporarily for compilation
+#if 0
+    ///
+    /// @brief Get FFDC Size specialization for variable buffers
+    ///
+    template<>
+    inline uint16_t getErrorInfoFfdcSize(const fapi2::variable_buffer& i_thing)
+    {
+        // Limit a variable buffer to 4kb bytes, and we can memcpy the storage.
+        return std::min(static_cast<uint32_t>(EI_FFDC_MAX_SIZE),
+                        i_thing.getLength<uint8_t>());
+    }
+#endif
+
+};
+
+#endif // FAPI2_ERRORINFO_DEFS_H_
diff --git a/src/ppe/importtemp/fapi2/include/error_scope.H b/src/ppe/importtemp/fapi2/include/error_scope.H
new file mode 100644
index 0000000..9af1474
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/error_scope.H
@@ -0,0 +1,37 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/error_scope.H $              */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file error_scope.H
+ * @brief platform specializations which create a scope for automatic error handling
+ */
+
+#ifndef __FAPI2_ERROR_SCOPE__
+#define __FAPI2_ERROR_SCOPE__
+
+#include <plat_error_scope.H>
+#include <fapi2_error_scope.H>
+
+
+#endif
diff --git a/src/ppe/importtemp/fapi2/include/fapi2.H b/src/ppe/importtemp/fapi2/include/fapi2.H
new file mode 100644
index 0000000..4d91e9b
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/fapi2.H
@@ -0,0 +1,53 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/fapi2.H $                    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file fapi2.H
+/// @brief top level header for fapi2
+///
+
+#ifndef __FAPI2_TOP_LEVEL__
+#define __FAPI2_TOP_LEVEL__
+
+#include <target.H>
+#include <return_code.H>
+#include <buffer.H>
+#include <hw_access.H>
+#include <utils.H>
+#include <plat_trace.H>
+
+// In turn includes the needed generated headers (hwp_ffd_classes, etc.)
+#include <error_scope.H>
+#include <set_sbe_error.H>      // Generated file
+
+#include <hwp_executor.H>
+
+#include <mvpd_access.H>
+
+// Block of headers not currently in fapi2
+#ifdef FAPI2_MISSING_HEADERS
+    #include <mbvpdAccess.H>
+#endif
+
+#endif // __FAPI2_TOP_LEVEL__
diff --git a/src/ppe/importtemp/fapi2/include/fapi2_attribute_service.H b/src/ppe/importtemp/fapi2/include/fapi2_attribute_service.H
new file mode 100644
index 0000000..f2a9df4
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/fapi2_attribute_service.H
@@ -0,0 +1,151 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/fapi2_attribute_service.H $  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file src/include/usr/hwpf/fapi2/fapi2_attribute_service.H
+///
+/// @brief Defines the FAPI_ATTR_GET and FAPI_ATTR_SET macros that a user
+/// calls to get/set attributes and a check function that the macros use to
+/// verify correct usage
+///
+
+#ifndef FAPI2ATTRIBUTESERVICE_H_
+#define FAPI2ATTRIBUTESERVICE_H_
+#include <stdint.h>
+#include <attribute_ids.H>
+#include <target.H>
+#include <target_types.H>
+#include <plat_attribute_service.H>
+
+/// @brief Macros called by user to get/set attributes for FAPI2 targets
+///
+/// Code must have a reference to a FAPI2 Target and an attribute ID (from
+/// XML file):
+///   fapi2::ReturnCode l_rc;
+///   fapi2::Target<target type>& l_target = ????;
+///          Ex: Target<TARGET_TYPE_PROC_CHIP>& l_target = ????;
+///
+/// To get a copy of an integer attribute and set the attribute
+///   uint64_t l_val = 0;
+///   l_rc = FAPI_ATTR_GET(<ID>, l_target, l_val);
+///   l_rc = FAPI_ATTR_SET(<ID>, l_target, l_val);
+///
+/// To get a copy of an integer array attribute and set the attribute
+///   uint32_t l_pVal[4] = {0};
+///   l_rc = FAPI_ATTR_GET(<ID>, l_target, l_pVal);
+///   l_rc = FAPI_ATTR_SET(<ID>, l_target, l_pVal);
+///
+/// A priveleged attribute is one that a HWP should not generally access,
+/// examples include ATTR_NAME and ATTR_EC, where usage can lead to a non
+/// data-driven design. A privileged attribute can be accessed with
+/// FAPI_ATTR_GET_PRIVILEGED and FAPI_ATTR_SET_PRIVILEGED
+///
+/// The non-PRIVILEGED macros first call a template function (compiler will
+/// optimize out) that will cause a compile failure if the attribute is
+/// privileged, they then call a PRIVILEGED macro to get/set the attribute
+///
+/// The PRIVILEGED macros call a template function (compiler will optimize out)
+/// that will cause a compile failure if the ID is not valid or VAL is not the
+/// correct type.
+//
+
+#define FAPI_ATTR_GET(ID, TARGET, VAL) \
+    (fapi2::failIfPrivileged<ID##_Privileged>(), \
+     fapi2::Target<ID##_TargetType>(TARGET), \
+     fapi2::checkIdType<ID##_Type>(ID, VAL), \
+     ID##_GETMACRO(ID, TARGET, VAL))
+
+#define FAPI_ATTR_SET(ID, TARGET, VAL) \
+    (fapi2::failIfPrivileged<ID##_Privileged>(), \
+     fapi2::Target<ID##_TargetType>(TARGET), \
+     fapi2::checkIdType<ID##_Type>(ID, VAL), \
+     ID##_SETMACRO(ID, TARGET, VAL))
+
+#define FAPI_ATTR_GET_PRIVILEGED(ID, TARGET, VAL) \
+    (fapi2::checkIdType<ID##_Type>(ID, VAL), \
+     ID##_GETMACRO(ID, TARGET, VAL))
+
+#define FAPI_ATTR_SET_PRIVILEGED(ID, TARGET, VAL) \
+    (fapi2::checkIdType<ID##_Type>(ID, VAL), \
+     ID##_SETMACRO(ID, TARGET, VAL))
+
+namespace fapi2
+{
+
+///
+/// @brief Get an InitFile attribute for FAPI2
+///
+/// This function gets a copy of an attribute. In the case of an array attribute,
+/// The value in the specified index is retrieved. This should be used by the
+/// InitFile HWP only, that HWP processes a binary InitFile and therefore needs
+/// to read a variable ID of a variable data type. Standard HWPs should use the
+/// FAPI2_ATTR_GET macro which automatically checks the type for correct usage.
+///
+/// If there are ever attributes with more than 4 dimensions then this function
+/// will need to be updated.
+///
+/// @Tparam K template parameter, passed in target.
+/// @param[in]  i_id          AttributeID
+/// @param[in]  i_target      Reference to fapi2::Target (can be NULL for system)
+/// @param[out] o_val         Reference to uint64_t where attribute value is set
+/// @param[in]  i_arrayIndex1 If array attribute then index1
+/// @param[in]  i_arrayIndex2 If at least 2D array attribute then index2
+/// @param[in]  i_arrayIndex3 If at least 3D array attribute then index3
+/// @param[in]  i_arrayIndex4 If at least 4D array attribute then index4
+///
+/// @return ReturnCode. Zero if success
+///
+template< TargetType K >
+ReturnCode getInitFileAttr(const AttributeId i_id,
+                           const Target<K>& i_target,
+                           uint64_t & o_val,
+                           const uint32_t i_arrayIndex1 = 0,
+                           const uint32_t i_arrayIndex2 = 0,
+                           const uint32_t i_arrayIndex3 = 0,
+                           const uint32_t i_arrayIndex4 = 0);
+
+/**
+ * @brief Check the ID and TYPE
+ *
+ * This is called by FAPI code to check at compile time that a FAPI attribute
+ * access is using the correct data type and a valid AttributeId
+ */
+template<typename T> inline void checkIdType(AttributeId, T &) {}
+
+/**
+ * @brief Fail if attribute privileged
+ *
+ * This is called by FAPI code to check at compile time that a standard FAPI
+ * attribute access (FAPI_ATTR_GET) is not accessing a privileged attribute
+ */
+class ErrorAccessingPrivilegedAttribute;
+template<const bool PRIVILEGED> void failIfPrivileged()
+{
+   ErrorAccessingPrivilegedAttribute();
+}
+template <> inline void failIfPrivileged<false>() {}
+
+}
+
+#endif // FAPI2ATTRIBUTESERVICE_H_
diff --git a/src/ppe/importtemp/fapi2/include/fapi2_chip_ec_feature.H b/src/ppe/importtemp/fapi2/include/fapi2_chip_ec_feature.H
new file mode 100644
index 0000000..f4d2d95
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/fapi2_chip_ec_feature.H
@@ -0,0 +1,63 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/fapi2_chip_ec_feature.H $    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file src/include/usr/hwpf/fapi2/fapi2_chip_ec_feature.H
+///
+/// @brief Defines the queryChipEcFeature function that allows HWPs to
+///        query if a particular chip has a feature determined by its EC level.
+///        Chip EC features are specified in attribute XML files and the
+///        queryChipEcFeature function implementation is auto-generated.
+///        HWPs should not call this function directly, but should access the
+///        corresponding HWPF attribute using FAPI_ATTR_GET
+///
+
+#ifndef FAPI2CHIPECFEATURE_H_
+#define FAPI2CHIPECFEATURE_H_
+
+#include <stdint.h>
+#include <target.H>
+#include <return_code.H>
+
+namespace fapi2
+{
+
+///
+/// @brief Queries if a Chip has a particular feature
+///
+/// This should only be called by FAPI during the processing of a FAPI_ATTR_GET
+/// for a Chip EC Feature attribute
+///
+/// @param[in]  i_id         Attribute ID of the Chip EC Feature
+/// @param[in]  i_target     Reference to chip target
+/// @param[out] o_hasFeature Set to 1 if chip has feature else 0
+/// @return ReturnCode. Zero on success, else platform specified error
+///
+template< TargetType K >
+ReturnCode queryChipEcFeature(AttributeId i_id,
+                              const Target<K>& i_target,
+                              uint8_t & o_hasFeature);
+}
+
+#endif
diff --git a/src/ppe/importtemp/fapi2/include/fapi2_error_scope.H b/src/ppe/importtemp/fapi2/include/fapi2_error_scope.H
new file mode 100644
index 0000000..9ba9a98
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/fapi2_error_scope.H
@@ -0,0 +1,79 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/fapi2_error_scope.H $        */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file fapi2_error_scope.H
+ * @brief common definitions which create a scope for automatic error handling
+ */
+
+#ifndef __FAPI2_COMMON_ERROR_SCOPE__
+#define __FAPI2_COMMON_ERROR_SCOPE__
+
+#include <stdint.h>
+#include <plat_error_scope.H>
+#include <return_code.H>
+#include <hwp_ffdc_classes.H>
+
+/// @cond
+#define FAPI_VA_NARGS_IMPL(_1, _2, _3, _4, _5, N, ...) N
+#define FAPI_VA_NARGS(...) FAPI_VA_NARGS_IMPL(__VA_ARGS__, 5, 4, 3, 2, 1)
+
+#define FAPI_TRY_IMPL2(count, ...) FAPI_TRY ## count (__VA_ARGS__)
+#define FAPI_TRY_IMPL(count, ...) FAPI_TRY_IMPL2(count, __VA_ARGS__)
+
+#define FAPI_TRY_NO_TRACE( __operation__ ) PLAT_FAPI_TRY_NO_TRACE( __operation__ )
+#define FAPI_TRY_TRACE( __operation__, ... ) PLAT_FAPI_TRY_TRACE( __operation__, __VA_ARGS__ )
+
+#define FAPI_TRY1 FAPI_TRY_NO_TRACE
+#define FAPI_TRY2 FAPI_TRY_TRACE
+#define FAPI_TRY3 FAPI_TRY_TRACE
+#define FAPI_TRY4 FAPI_TRY_TRACE
+#define FAPI_TRY5 FAPI_TRY_TRACE
+/// @endcond
+
+///
+/// @brief Wrapper to check an operation for an error state
+/// and jump to the label cleam_up if there is an error.
+/// @param[in] __operation__ an operation which returns a fapi::ReturnCode
+/// @param[in] ... vararg format/agruments for trace output (optional)
+/// @note This implementation does not support PIB error masks or
+/// FSP operational states.
+///
+#ifdef DOXYGEN
+#define FAPI_TRY(__operation__, ...) FAPI_TRY_IMPL
+#else
+#define FAPI_TRY(...) FAPI_TRY_IMPL(FAPI_VA_NARGS(__VA_ARGS__), __VA_ARGS__)
+#endif
+
+///
+/// @brief Assert a conditional is true.
+/// If it is not, the FFDC gathering function is called and the
+/// trace is output as a FAPI error trace.
+/// @param[in] __conditional__ the condition to assert
+/// @param[in] __ffdc__ the FFDC gathering function
+/// @param[in] ... varargs, as input to FAPI_ERR
+///
+#define FAPI_ASSERT( __conditional__, __ffdc__, ... ) PLAT_FAPI_ASSERT( __conditional__, __ffdc__, __VA_ARGS__ )
+
+#endif
diff --git a/src/ppe/importtemp/fapi2/include/fapi2_hw_access.H b/src/ppe/importtemp/fapi2/include/fapi2_hw_access.H
new file mode 100644
index 0000000..1c27dd0
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/fapi2_hw_access.H
@@ -0,0 +1,464 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/fapi2_hw_access.H $          */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file fapi2_hw_access.H
+/// @brief Common file that defines the hardware access functions that
+/// platform code must implement.
+///
+
+#ifndef _FAPI2_COMMON_HWACCESS_H_
+#define _FAPI2_COMMON_HWACCESS_H_
+
+#ifdef FAPI_SUPPORT_SPY_AS_ENUM
+#include <spy_ids.H>
+typedef uint64_t spyId_t;
+#endif
+
+#include <stdint.h>
+#include <thread>
+#include <buffer.H>
+
+// variable_buffer isn't supported on PPE
+#ifndef __PPE__
+#include <variable_buffer.H>
+#endif
+
+#include <return_code.H>
+#include <target.H>
+#include <hw_access_def.H>
+#include <plat_hw_access.H>
+
+#ifdef FAPI_SUPPORT_MULTI_SCOM
+#include <multi_scom.H>
+#endif
+
+namespace fapi2
+{
+    //--------------------------------------------------------------------------
+    // PIB Error Functions
+    //--------------------------------------------------------------------------
+
+    /// @brief Sets the PIB error mask - platform dependant
+    /// @param[in]  i_mask     The new error mask
+    inline void setPIBErrorMask(uint8_t i_mask);
+
+    /// @brief Gets the PIB error mask - platform dependant
+    /// @return uint8_t The current PIB error mask
+    inline uint8_t getPIBErrorMask(void);
+
+    //--------------------------------------------------------------------------
+    // Operational Mode Error Functions
+    //--------------------------------------------------------------------------
+
+    /// @brief Sets the operational mode
+    /// @param[in]  i_mode     The new mode
+    inline void setOpMode(const OpModes i_mode);
+
+    /// @brief Gets the operational mode
+    /// @return the operational mode
+    inline OpModes getOpMode(void);
+
+    //--------------------------------------------------------------------------
+    // HW Communication Functions
+    //--------------------------------------------------------------------------
+
+    /// @brief Reads a SCOM register from a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target     HW target to operate on.
+    /// @param[in]  i_address    SCOM register address to read from.
+    /// @param[out] o_data       Buffer that holds data read from HW target.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode getScom(const Target<K>& i_target, const uint64_t i_address,
+                              buffer<uint64_t>& o_data);
+
+    /// @brief Writes a SCOM register on a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target     HW target to operate on.
+    /// @param[in] i_address    SCOM register address to write to.
+    /// @param[in] i_data       Buffer that holds data to write into address.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode putScom(const Target<K>& i_target, const uint64_t i_address,
+                              const buffer<uint64_t> i_data);
+
+    /// @brief Writes a SCOM register under mask on a chip
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target     HW target to operate on.
+    /// @param[in] i_address    SCOM register address to write to.
+    /// @param[in] i_data       Buffer that holds data to write into address.
+    /// @param[in] i_mask       Buffer that holds the mask value.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode putScomUnderMask(const Target<K>& i_target,
+                                       const uint64_t i_address,
+                                       const buffer<uint64_t> i_data,
+                                       const buffer<uint64_t> i_mask);
+
+    /// @brief Reads a CFAM register from a chip.
+    ///        CFAM register is 32-bit wide.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target  HW target to operate on.
+    /// @param[in]  i_address CFAM register address to read from.
+    /// @param[out] o_data    Buffer that holds data read from HW target.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode getCfamRegister(const Target<K>& i_target,
+                                      const uint32_t i_address,
+                                      buffer<uint32_t>& o_data);
+
+    /// @brief Writes a CFAM register on a chip.
+    ///        CFAM register is 32-bit wide.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target  HW target to operate on.
+    /// @param[in] i_address CFAM register address to write to.
+    /// @param[in] i_data    Buffer that holds data to write into address.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode putCfamRegister(const Target<K>& i_target,
+                                      const uint32_t i_address,
+                                      const buffer<uint32_t> i_data);
+
+    /// @brief Read-modify-write a CFAM register on a chip.
+    ///        CFAM register is 32-bit wide.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target     HW target to operate on.
+    /// @param[in] i_address    CFAM register address to modify.
+    /// @param[in] i_data       Buffer that holds data to be modified.
+    /// @param[in] i_modifyMode The modify mode (or/and/xor).
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode modifyCfamRegister(const Target<K>& i_target,
+                                         const uint32_t i_address,
+                                         const buffer<uint32_t> i_data,
+                                         const ChipOpModifyMode i_modifyMode);
+
+    // variable_buffer isn't supported on PPE
+#ifndef __PPE__
+    /// @brief Reads a ring from a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target   Target to operate on.
+    /// @param[in]  i_address  Ring address to read from.
+    /// @param[out] o_data     Buffer that holds data read from HW target.
+    /// @param[in]  i_ringMode Ring operation mode.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode getRing(const Target<K>& i_target,
+                              const scanRingId_t i_address,
+                              variable_buffer& o_data,
+                              const RingMode i_ringMode = 0);
+
+    /// @brief Writes a ring to a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target   Target to operate on.
+    /// @param[in] i_address  Ring address to write to.
+    /// @param[in] i_data     Buffer that contains RS4 compressed ring data
+    ///                       to write into address
+    /// @param[in] i_ringMode Ring operation mode.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode putRing(const Target<K>& i_target,
+                              const scanRingId_t i_address,
+                              const variable_buffer& i_data,
+                              const RingMode i_ringMode = 0);
+
+
+    /// @brief Read-modify-write a ring on a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target     Target to operate on.
+    /// @param[in] i_address    Ring address to modify.
+    /// @param[in] i_data       Buffer that contains RS4 compressed ring data
+    ///                         to be modified.
+    /// @param[in] i_modifyMode The modify mode (or/and/xor)
+    /// @param[in] i_ringMode   Ring operation mode.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode modifyRing(const Target<K>& i_target,
+                                 const scanRingId_t i_address,
+                                 const variable_buffer& i_data,
+                                 const ChipOpModifyMode i_modifyMode,
+                                 const RingMode i_ringMode = 0);
+#endif
+
+#ifdef FAPI_SUPPORT_MULTI_SCOM
+    /// @brief Performs a multiple SCOM operation
+    ///        This interface performs multiple SCOM operations on a chip in the
+    ///        order specified by the input MultiScom object.
+    ///        See fapiMultiScom.H for details of how to populate the MultiScom
+    ///        object with SCOM operations.
+    ///
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]     i_target Target to operate on.
+    /// @param[in,out] io_multiScomObj Reference to a MultiScom object,
+    ///                                pre-populated with SingleScomInfo entries
+    ///                                to perform multiple SCOMs on input target
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note   This is a synchronous interface and would return after all the
+    ///         SCOM operations are completed or on the first failed operation
+    ///
+    /// @note   SCOMs will be performed in the order they were added to the
+    ///         input MultiScom object
+    ///
+    /// @note   In case of errors, the platform code is responsible to collect
+    ///         and add all the required error info and FFDC into the error data
+    ///         for debugging
+    ///
+    /// @note   If the SCOM operations added are specific to a processor chip,
+    ///         then the FSI Shift Engine configured in scatter-gather DMA mode
+    ///         extension would be used to execute the SCOM operations in a
+    ///         performance optimize mode. In this mode, the special
+    ///         SCOM_BULK_READ_MODE and SCOM_BULK_WRITE_MODE operations are
+    ///         supported that allow a large bulk of SCOM access (in multiple of
+    ///         64 bits) for targets that support auto-increment. The
+    ///         SCOM_WRITE_UNDER_MASK operation is not supported in this mode
+    ///
+    /// @note   If the SCOM operations added are specific to a memory buffer
+    ///         chip, then the regular SCOM engine is used to execute the SCOM
+    ///         operations. SCOM_WRITE_UNDER_MASK operation is supported in
+    ///         this mode, but the special SCOM_BULK_READ_MODE and
+    ///         SCOM_BULK_WRITE_MODE operations are not supported due to
+    ///         hardware limitations.
+    ///
+    template< TargetType K >
+    fapi2::ReturnCode multiScom (const Target<K>& i_target,
+                                 MultiScom&  io_multiScomObj);
+#endif
+
+    // --------------------------------------------------------------------------
+    // NOTE:
+    // Implement platform Spy access functions if platform supports them.
+    // --------------------------------------------------------------------------
+
+    // variable_buffer isn't supported on PPE
+#ifndef __PPE__
+    /// @brief Reads a spy from a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target   Target to operate on.
+    /// @param[in]  i_spyId    Id of the spy whose data to be read.
+    /// @param[out] o_data     Buffer that holds data read from HW target.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note:  The string version is only supported for cronus.
+    ///
+    ///         The fapi design to support both FSP and cronus use of get and
+    ///         put spy functions is dependant on the SPY names being expanded
+    ///         to resemble a valid C identifier. This design places some
+    ///         restrictions on the SPY names which can be used.
+    ///
+    ///         1. if the spy name contains a # procedure writers should replace
+    ///         it with an __P__ for example -
+    ///
+    ///         ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+    ///         becomes
+    ///         ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS
+    ///
+    ///         2. if the spy name has a number following a "." it must have an
+    ///         underscore prepended to the number.
+    ///
+    ///         EH.TPCHIP.2KX100_ARY_CLK_EDGES_DLY
+    ///         becomes
+    ///         EH.TPCHIP._2KX100_ARY_CLK_EDGES_DLY
+    ///
+    ///         Example SPY name:
+    ///         The hardware procedure should call the function like:
+    ///
+    ///          ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+    ///
+    ///          fapi2::ReturnCode rc = fapiGetSpy( targ,
+    ///                  ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS, data );
+    ///
+    /// @note The ID is not in quotes the fapi code will handle adding
+    ///       the quotes for the cronus environment
+#if defined(FAPI_SUPPORT_SPY_AS_ENUM) || defined(DOXYGEN)
+
+#define FAPI_GET_SPY(TARGET, ID, DATA) fapi2::getSpy(TARGET, FAPI_SPY_NAMES::ID.value, DATA)
+
+    template< TargetType K >
+    inline ReturnCode getSpy(const Target<K>& i_target,
+                             const spyId_t i_spyId,
+                             variable_buffer& o_data);
+#endif
+
+#if defined(FAPI_SUPPORT_SPY_AS_STRING) || defined(DOXYGEN)
+
+#define FAPI_GET_SPY(TARGET, ID, DATA) fapi2::getSpy(TARGET, #ID, DATA)
+
+    template< TargetType K >
+    inline ReturnCode getSpy(const Target<K>& i_target,
+                             const char * const i_spyId,
+                             variable_buffer& o_data);
+#endif
+
+    /// @brief Writes a spy on a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target   Target to operate on.
+    /// @param[in]  i_spyId    Id of the spy to write data to.
+    /// @param[out] i_data     Buffer that holds data to write into spy.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note:  The string version is only supported for cronus.
+    ///
+    ///         The fapi design to support both FSP and cronus use of get and
+    ///         put spy functions is dependent on the SPY names being expanded
+    ///         to resemble a valid C identifier. This design places some
+    ///         restrictions on the SPY names which can be used.
+    ///
+    ///         1. if the spy name contains a # procedure writers should replace
+    ///         is with an __P__ for example -
+    ///
+    ///         ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+    ///         becomes
+    ///         ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS
+    ///
+    ///         2. if the spy name has a number following a "." it must have an
+    ///         underscore prepended to the number.
+    ///
+    ///         EH.TPCHIP.2KX100_ARY_CLK_EDGES_DLY
+    ///         becomes
+    ///         EH.TPCHIP._2KX100_ARY_CLK_EDGES_DLY
+    ///
+    ///         Example SPY name:
+    ///         The hardware procedure should call the function like:
+    ///
+    ///          ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+    ///
+    ///          fapi2::ReturnCode rc = fapiPutSpy( targ,
+    ///                  ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS, data );
+    ///
+    /// @note The ID is not in quotes the fapi code will handle adding
+    ///         the quotes for the cronus environment
+    ///
+#if defined(FAPI_SUPPORT_SPY_AS_ENUM) || defined(DOXYGEN)
+
+#define FAPI_PUT_SPY(TARGET, ID, DATA) fapi2::putSpy(TARGET, FAPI_SPY_NAMES::ID.value, DATA)
+
+    template< TargetType K >
+    inline ReturnCode putSpy(const Target<K>& i_target,
+                             const spyId_t i_spyId,
+                             variable_buffer& i_data);
+#endif
+
+#if defined(FAPI_SUPPORT_SPY_AS_STRING) || defined(DOXYGEN)
+
+#define FAPI_PUT_SPY(TARGET, ID, DATA) fapi2::putSpy(TARGET, #ID, DATA)
+
+    template< TargetType K >
+    inline ReturnCode putSpy(const Target<K>& i_target,
+                             const char* const i_spyId,
+                             variable_buffer& i_data);
+#endif
+
+    /// @brief Writes spy data into a buffer holding ring data image
+    ///        This API is used by L2/L3 repair to put column repair data
+    ///        into a ring buffer image.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target Target to operate on.
+    /// @param[in]  i_spyId  Id of the spy.
+    /// @param[in]  i_data   Buffer that holds spy data to write into ring
+    ///                      image.
+    /// @param[out] o_data   Buffer that holds updated ring image.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note:  The string version is only supported for cronus.
+    ///
+    ///         The fapi design to support both FSP and cronus use of get and
+    ///         put spy functions is dependent on the SPY names being expanded
+    ///         to resemble a valid C identifier. This design places some
+    ///         restrictions on the SPY names which can be used.
+    ///
+    ///         See fapiPutSpy for details on spy id specifics.
+    ///
+#if defined(FAPI_SUPPORT_SPY_AS_ENUM) || defined(DOXYGEN)
+
+#define FAPI_PUT_SPY_IMAGE(TARGET, ID, DATA1, DATA2)                    \
+    fapi2::putSpyImage(TARGET, FAPI_SPY_NAMES::ID.value,                \
+                       DATA1, DATA2)
+
+    template< TargetType K >
+    inline ReturnCode putSpyImage(const Target<K>& i_target,
+                                  const spyId_t i_spyId,
+                                  const variable_buffer& i_data,
+                                  variable_buffer& o_imageData);
+#endif
+
+#if defined(FAPI_SUPPORT_SPY_AS_STRING) || defined(DOXYGEN)
+
+#define FAPI_PUT_SPY_IMAGE(TARGET, ID, DATA1, DATA2) \
+    fapi2::putSpyImage(TARGET, #ID, DATA1,DATA2)
+
+    template< TargetType K >
+    inline ReturnCode putSpyImage(const Target<K>& i_target,
+                                  const char* const i_spyId,
+                                  const variable_buffer& i_data,
+                                  variable_buffer& o_imageData);
+#endif
+
+    /// @brief Reads spy data from a ring image buffer
+    /// @param[in]   i_target      Target to operate on
+    /// @param[in]   i_spyId       The spy's id
+    /// @param[out]  o_data        Buffer that holds data read from ring image.
+    /// @param[in]   i_imageData   Buffer that holds ring image to read data
+    ///                            from.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note:  The string version is only supported for cronus.
+    ///
+    ///         The fapi design to support both FSP and cronus use of get and
+    ///         put spy functions is dependent on the SPY names being expanded
+    ///         to resemble a valid C identifier. This design places some
+    ///         restrictions on the SPY names which can be used.
+    ///
+    ///         See fapiPutSpy for details on spy id specifics.
+    ///
+#if defined(FAPI_SUPPORT_SPY_AS_ENUM) || defined(DOXYGEN)
+
+#define FAPI_GET_SPY_IMAGE(TARGET, ID, DATA1, DATA2)    \
+    fapi2:getSpyImage(TARGET, FAPI_SPY_NAMES::ID.value, \
+                      DATA1, DATA2)
+
+    template< TargetType K >
+    inline ReturnCode getSpyImage(const Target<K>& i_target,
+                                  const spyId_t i_spyId,
+                                  variable_buffer& o_data,
+                                  const variable_buffer& i_imageData);
+#endif
+
+#if defined(FAPI_SUPPORT_SPY_AS_STRING) || defined(DOXYGEN)
+
+#define FAPI_GET_SPY_IMAGE(TARGET, ID, DATA1, DATA2) \
+    fapi2::getSpyImage(TARGET, #ID, DATA1,DATA2)
+
+    template< TargetType K >
+    inline ReturnCode getSpyImage(const Target<K>& i_target,
+                                  const char * const i_spyId,
+                                  variable_buffer& o_data,
+                                  const variable_buffer& i_imageData);
+#endif
+
+#endif // PPE
+};
+
+#endif // _FAPI2_HWACCESS_H_
diff --git a/src/ppe/importtemp/fapi2/include/fapi2_hwp_executor.H b/src/ppe/importtemp/fapi2/include/fapi2_hwp_executor.H
new file mode 100644
index 0000000..617d38b
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/fapi2_hwp_executor.H
@@ -0,0 +1,48 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/fapi2_hwp_executor.H $       */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file fapi2_hwp_executor.H
+///
+/// @brief Defines the FAPI2 HWP Executor Macro.
+///
+/// The FAPI2 HWP Executor macro is called when a PLAT invoker function or a HWP
+/// wants to execute a HWP.
+///
+
+#ifndef FAPI2HWPEXECUTOR_H_
+#define FAPI2HWPEXECUTOR_H_
+
+#include <hwp_executor.H>
+
+/**
+ * @brief HWP Executor macro
+ *
+ * This macro calls a PLAT macro which will do any platform specific work to
+ * execute the HWP (e.g. dlopening a shared library)
+ */
+#define FAPI_EXEC_HWP(RC, FUNC, _args_...) \
+    FAPI_PLAT_EXEC_HWP(RC, FUNC, ##_args_)
+
+#endif // FAPI2HWPEXECUTOR_H_
diff --git a/src/ppe/importtemp/fapi2/include/fapi2_target.H b/src/ppe/importtemp/fapi2/include/fapi2_target.H
new file mode 100644
index 0000000..e753676
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/fapi2_target.H
@@ -0,0 +1,457 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/fapi2_target.H $             */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file fapi2_target.H
+/// @brief Common definitions for fapi2 targets
+///
+
+#ifndef __FAPI2_COMMON_TARGET__
+#define __FAPI2_COMMON_TARGET__
+
+#include <stdint.h>
+#include <vector>
+#include <target_types.H>
+#include <target_states.H>
+#include <plat_target.H>
+
+namespace fapi2
+{
+    ///
+    /// @brief Class representing a FAPI2 Target
+    /// @tparam K the type (Kind) of target
+    /// @tparam V the type of the target's Value
+    /// @remark TargetLite targets are uint64_t, Targets
+    /// are uintptr_t (void*).
+    ///
+    /// Assuming there are representations of a processor,
+    /// a membuf and a system here are some examples:
+    /// @code
+    /// #define PROCESSOR_CHIP_A 0xFFFF0000
+    /// #define MEMBUF_CHIP_B    0x0000FFFF
+    /// #define SYSTEM_C         0x0000AAAA
+    /// @endcode
+    ///
+    /// * To define a target:
+    /// @code
+    /// fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> A(PROCESSOR_CHIP_A);
+    /// fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> C(SYSTEM_C);
+    /// fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP> B(MEMBUF_CHIP_B);
+    /// @endcode
+    ///
+    /// * Functions which take composite target types
+    /// @code
+    /// void takesProcOrMembuf(
+    /// const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP |
+    ///                     fapi2::TARGET_TYPE_MEMBUF_CHIP>& V );
+    ///
+    /// void takesAny(const fapi2::Target<fapi2::TARGET_TYPE_ALL>& V );
+    ///
+    /// @endcode
+    ///
+    /// * Traversing the target "tree"
+    /// @code
+    /// fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> A(PROCESSOR_CHIP_A);
+    ///
+    /// // Get A's parent
+    /// A.getParent<fapi2::TARGET_TYPE_SYSTEM>();
+    ///
+    /// // Get the 0x53'd core
+    /// fapi2::getTarget<fapi2::TARGET_TYPE_CORE>(0x53);
+    ///
+    /// // Get all *my* present/functional children which are cores
+    /// A.getChildren<fapi2::TARGET_TYPE_CORE>();
+    ///
+    /// // Get all of the the cores relative to my base target
+    /// fapi2::getChildren<fapi2::TARGET_TYPE_CORE>();
+    /// @endcode
+    ///
+    /// * Invalid casts
+    /// @code
+    /// // Can't cast to a specialized target
+    /// fapi2::Target<fapi2::TARGET_TYPE_NONE> D(MEMBUF_CHIP_B);
+    /// takesProcOrMembuf( D );
+    ///
+    /// // Not one of the shared types
+    /// fapi2::Target<fapi2::TARGET_TYPE_ABUS_ENDPOINT> E;
+    /// takesProcOrMembuf( E );
+    /// @endcode
+    template<TargetType K, typename V = plat_target_handle_t>
+    class Target
+    {
+    public:
+
+        ///
+        /// @brief Create a Target, with a value
+        /// @param[in] Value the value (i.e., specific element this
+        /// target represents, or pointer)
+        /// @note Platforms can mangle the value and K to get a
+        /// single uint64_t in value which represents all the information
+        /// they might need. value( K | V ), for example
+        ///
+        Target(V Value = 0):
+            iv_handle(Value)
+        {}
+
+        ///
+        /// @brief Assignment Operator.
+        /// @param[in] i_right Reference to Target to assign from.
+        /// @return Reference to 'this' Target
+        ///
+        Target& operator=(const Target& i_right);
+
+        ///
+        /// @brief Equality Comparison Operator
+        /// @param[in] i_right Reference to Target to compare.
+        /// @return bool. True if equal.
+        /// @note Platforms need to define this so that the physical
+        /// targets are determined to be equivilent rather than just the handles
+        ///
+        bool operator==(const Target& i_right) const;
+
+        ///
+        /// @brief Inquality Comparison Operator
+        /// @param[in] i_right Reference to Target to compare.
+        /// @return bool. True if not equal.
+        /// @note Platforms need to define this so that the physical
+        /// targets are determined to be equivilent rather than just the handles
+        ///
+        bool operator!=(const Target& i_right) const;
+
+        ///
+        /// @brief Get the handle.
+        /// @return V The target's handle, or value
+        ///
+        V get(void) const
+            { return iv_handle; }
+
+        ///
+        /// @brief Get the handle as a V
+        /// @return V The target's handle, or value
+        ///
+        inline operator V() const { return iv_handle; }
+
+        ///
+        /// @brief Get a target's value
+        /// @return V The target's handle, or value
+        ///
+        inline V& operator()(void) { return iv_handle; }
+
+        ///
+        /// @brief Get the target type
+        /// @return The type of target represented by this target
+        ///
+        inline TargetType getType(void) const { return iv_type; }
+
+        ///
+        /// @brief Get this target's immediate parent
+        /// @tparam T The type of the parent
+        /// @return Target<T> a target representing the parent
+        ///
+        template< TargetType T >
+        inline Target<T> getParent(void) const;
+
+        ///
+        /// @brief Is this target a chip?
+        /// @return Return true if this target is a chip, false otherwise
+        ///
+        inline constexpr bool isChip(void) const
+        {
+           return ( (K == TARGET_TYPE_PROC_CHIP) ||
+                    (K == TARGET_TYPE_MEMBUF_CHIP) );
+        }
+
+        ///
+        /// @brief Is this target a chiplet?
+        /// @return Return true if this target is a chiplet, false otherwise
+        ///
+        inline constexpr bool isChiplet(void) const
+        {
+           return ( (K == TARGET_TYPE_EX) ||
+                    (K == TARGET_TYPE_MBA) ||
+                    (K == TARGET_TYPE_MCS) ||
+                    (K == TARGET_TYPE_XBUS) ||
+                    (K == TARGET_TYPE_ABUS) ||
+                    (K == TARGET_TYPE_L4) ||
+                    (K == TARGET_TYPE_CORE) ||
+                    (K == TARGET_TYPE_EQ) ||
+                    (K == TARGET_TYPE_MCA) ||
+                    (K == TARGET_TYPE_MCBIST) ||
+                    (K == TARGET_TYPE_MI) ||
+                    (K == TARGET_TYPE_DMI) ||
+                    (K == TARGET_TYPE_OBUS) ||
+                    (K == TARGET_TYPE_NV) ||
+                    (K == TARGET_TYPE_SBE) ||
+                    (K == TARGET_TYPE_PPE) ||
+                    (K == TARGET_TYPE_PERV) ||
+                    (K == TARGET_TYPE_PEC) ||
+                    (K == TARGET_TYPE_PHB) );
+        }
+
+        ///
+        /// @brief Get this target's children
+        /// @tparam T The type of the parent
+        /// @param[in] i_state The desired TargetState of the children
+        /// @return std::vector<Target<T> > a vector of present/functional
+        /// children
+        /// @warning The children of EX's (cores) are expected to be returned
+        /// in order. That is, core 0 is std::vector[0].
+        ///
+        template< TargetType T>
+        inline std::vector<Target<T> >
+        getChildren(const TargetState i_state = TARGET_STATE_FUNCTIONAL) const;
+
+        ///
+        /// @brief Get the target at the other end of a bus - dimm included
+        /// @tparam T The type of the parent
+        /// @param[in] i_state The desired TargetState of the children
+        /// @return Target<T> a target representing the thing on the other end
+        /// @note Can be easily changed to a vector if needed
+        ///
+        template<TargetType T>
+        inline Target<T>
+        getOtherEnd(const TargetState i_state = TARGET_STATE_FUNCTIONAL) const;
+
+        ///
+        /// @brief Copy from a Target<O> to a Target<K>
+        /// @tparam O the target type of the other
+        ///
+        template<TargetType O>
+        inline Target( const Target<O>& Other ):
+            Target<K, V>(Other.get())
+        {
+            // In case of recursion depth failure, use -ftemplate-depth=
+            static_assert( (K & O) != 0,
+                           "unable to cast Target, no shared types");
+
+            static_assert( bitCount<K>::count >= bitCount<O>::count,
+                           "unable to cast to specialized Target");
+        }
+
+    private:
+        // Don't use enums here as it makes it hard to assign
+        // in the platform target cast constructor.
+        static const TargetType iv_type = K;
+        V iv_handle;
+
+    };
+
+    // EX threads map to CORE threads:
+    // t0 / t2 / t4 / t6 fused = t0 / t1 / t2 / t3 normal (c0)
+    // t1 / t3 / t5 / t7 fused = t0 / t1 / t2 / t3 normal (c1)
+    // So when splitting the EX, we need to map from EX threads
+    // to CORE threads.
+
+    ///
+    /// @brief Given a normal core thread id, translate this to
+    /// a fused core thread id. (normal to fused)
+    /// @param[in] the ordinal number of the normal core this thread belongs to
+    /// @param[in] a normal core thread id - 0, ..., 3
+    /// @return the fused core thread id
+    ///
+    inline uint8_t thread_id_n2f(const uint8_t i_ordinal, const uint8_t i_thread_id)
+    {
+        return (i_thread_id << 1) | i_ordinal;
+    }
+
+    ///
+    /// @brief Given a fused core thread id, translate this to
+    /// a normal core thread id. (fused to normal)
+    /// @param[in] a fused core thread id - 0, ..., 7
+    /// @return the normal core thread id
+    ///
+    inline uint8_t thread_id_f2n(const uint8_t i_thread_id)
+    {
+        return i_thread_id >> 1;
+    }
+
+    ///
+    /// @brief Given a normal core thread id, translate this to a
+    /// normal core bitset.
+    /// @param[in] a normal core thread id - 0, ..., 3
+    /// @return the normal core bitset
+    /// @note to got from a fused core id to a normal core bitset,
+    /// translate from a fused core thread id first.
+    ///
+    inline uint8_t thread_id2bitset(const uint8_t i_thread_id)
+    {
+        // 0xff means "set all bits"
+        static const uint8_t all_threads  = 0xff;
+        static const uint8_t all_normal_threads_bitset = 0x0f;
+
+        if (i_thread_id == all_threads)
+        {
+            return all_normal_threads_bitset;
+        }
+
+        // A thread_id is really just bit index.
+        return (1 << (4 - i_thread_id - 1));
+    }
+
+    ///
+    /// @brief Given a bitset of normal core thread ids, translate this to
+    /// a bit mask of fused core thread id. (normal to fused)
+    /// @param[in] the ordinal number of the normal core this thread belongs to
+    /// @param[in] a normal core thread bitset - b0000, ..., b1111
+    /// @return the corresponding fused core bitset
+    ///
+    inline uint8_t thread_bitset_n2f(const uint8_t i_ordinal, const uint8_t i_threads)
+    {
+        // Since we only have 4 bits I think this is better than a shift-type solution
+        // for interleaving bits
+        static uint8_t core_map[] = {
+            0b00000000, // b0000
+            0b00000010, // b0001
+            0b00001000, // b0010
+            0b00001010, // b0011
+            0b00100000, // b0100
+            0b00100010, // b0101
+            0b00101000, // b0110
+            0b00101010, // b0111
+            0b10000000, // b1000
+            0b10000010, // b1001
+            0b10001000, // b1010
+            0b10001010, // b1011
+            0b10100000, // b1100
+            0b10100010, // b1101
+            0b10101000, // b1110
+            0b10101010, // b1111
+        };
+
+        return core_map[i_threads] >> i_ordinal;
+    }
+
+    ///
+    /// @brief Given a fused core thread bitset, translate this to
+    /// a normal core thread bitset. (fused to normal)
+    /// @param[in] the ordinal number of the normal core this thread belongs to
+    /// @param[in] a fused core thread bitset - b00000000, ..., b11111111
+    /// @return the corresponding normal core bitset
+    ///
+    inline uint8_t thread_bitset_f2n(const uint8_t i_ordinal, const uint8_t i_threads)
+    {
+        uint8_t normal_set = 0;
+
+        // core 0 is the left-most bit in the pair
+        uint8_t pair_mask = (i_ordinal == 0) ? 0x2 : 0x1;
+
+        // For each bit which can be set in the normal core bit_set ...
+        for( auto i = 0; i <= 3; ++i )
+        {
+            // ... grab the two fused bits which represent it ...
+            // ... and mask off the bit in the pair which represents this normal core ...
+            // (the << 1 shifts the masks over as we walk the pairs of bits)
+            uint8_t bits = (((3 << (i << 1)) & i_threads) & (pair_mask << (i << 1)));
+
+            // ... if either bit is set, set the corresponding bit in
+            // the normal core bitset.
+            normal_set |= (bits != 0) << i;
+        }
+        return normal_set;
+    }
+
+    ///
+    /// @brief Return the string interpretation of this target
+    /// @tparam T The type of the target
+    /// @param[in] i_target Target<T>
+    /// @param[in] i_buffer buffer to write in to
+    /// @param[in] i_bsize size of the buffer
+    /// @return void
+    /// @post The contents of the buffer is replaced with the string
+    /// representation of the target
+    ///
+    template< TargetType T >
+    inline void toString(const Target<T>& i_target, char* i_buffer, size_t i_bsize);
+
+    ///
+    /// @brief Return the string interpretation of this target
+    /// @tparam T The type of the target
+    /// @tparam B The type of the buffer
+    /// @param[in] A pointer to the Target<T>
+    /// @param[in] i_buffer buffer to write in to
+    /// @param[in] i_bsize size of the buffer
+    /// @return void
+    /// @post The contents of the buffer is replaced with the string
+    /// representation of the target
+    ///
+    template< TargetType T >
+    inline void toString(const Target<T>* i_target, char* i_buffer, size_t i_bsize);
+
+    ///
+    /// @brief Get an enumerated target of a specific type
+    /// @tparam T The type of the target
+    /// @param[in] Ordinal representing the ordinal number of
+    /// the desired target
+    /// @return Target<T> the target requested
+    ///
+    template<TargetType T>
+    inline Target<T> getTarget(uint64_t Ordinal);
+
+    // Why has the been removed? For starters, the API name
+    // is probably wrong as it's already been confused with
+    // Target::getChildren(). And if I'm going to change it
+    // I really want to see if we need it. I'm still not
+    // clear on whether we're alloing this traversal or not.
+#if 0
+    ///
+    /// @brief Get the base target's children
+    /// @tparam T The type of the target
+    /// @return std::vector<Target<T> > a vector of present/functional
+    /// children
+    ///
+    template<TargetType T>
+    inline std::vector<Target<T> > getChildren()
+    {
+        // For testing
+        return {Target<T>(), Target<T>()};
+    }
+#endif
+
+    ///
+    /// @brief Return the string interpretation of this target
+    /// @tparam T The type of the target
+    /// @tparam B The type of the buffer
+    /// @param[in] i_target Target<T>
+    /// @param[in] i_buffer buffer
+    /// @return void
+    /// @post The contents of the buffer is replaced with the string
+    /// representation of the target
+    ///
+    template<TargetType T, typename B>
+    inline void toString(const Target<T>& i_target, B& i_buffer);
+
+    ///
+    /// @brief Check if the target is of a type, or in a type subset.
+    /// @tparam K the TargetType to check
+    /// @tparam T TargetType or TargetType composite to check against
+    /// @return True, iff K is a proper T
+    ///
+    template< TargetType K, TargetType T >
+    inline constexpr bool is_same(void)
+    { return (K & T) != 0; }
+
+
+}
+
+#endif
diff --git a/src/ppe/importtemp/fapi2/include/ffdc.H b/src/ppe/importtemp/fapi2/include/ffdc.H
new file mode 100644
index 0000000..b05a311
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/ffdc.H
@@ -0,0 +1,192 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/ffdc.H $                     */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ *  @file ffdc.H
+ *  @brief Defines the FirstFailureData class
+ */
+
+#ifndef FAPI2_FFDC_H_
+#define FAPI2_FFDC_H_
+
+#include <memory>
+#include <hwp_return_codes.H>
+#include <plat_trace.H>
+#include <error_info.H>
+#include <target.H>
+
+using fapi2::TARGET_TYPE_ALL;
+
+namespace fapi2
+{
+    ///
+    /// @brief Check the type of a variable
+    ///
+    /// This function can be called to check that a variable type is as expected
+    /// @note This mechanism will allow for cast ctor's which other static type
+    /// checking might not.
+    ///
+    template<typename T>
+    inline
+    void checkType(const T &) {}
+
+    class ReturnCode;
+
+    ///
+    /// @class FirstFailureData
+    ///
+    /// This class provides storage and methods for creating and manipulating
+    /// FFDC.
+    /// It is not needed on all platforms - platforms which need this class have
+    /// specified this by forcing their fapi2::ReturnCode to be a subclass of
+    /// this class.
+    ///
+    template< class R = fapi2::ReturnCode >
+    class FirstFailureData
+    {
+    public:
+
+        ///
+        /// @brief Default constructor.
+        /// @note We don't create our error info be default. It will be created
+        /// when its needed in the setHwpError() method. Note that dereferencing
+        /// the error info without will create a problem.
+        ///
+        FirstFailureData(void):
+            iv_info( nullptr )
+            {}
+
+        ///
+        /// @brief Copy Constructor
+        ///
+        /// @param[in] i_right Reference to FirstFailureData to copy
+        /// @note Generates default copy constructor - no deep pointer
+        /// copies necessary.
+        ///
+        FirstFailureData(const FirstFailureData & i_right) = default;
+
+        ///
+        /// @brief Destructor
+        ///
+        ~FirstFailureData(void) = default;
+
+        ///
+        /// @brief Assignment Operator.
+        ///
+        /// @param[in] i_right Reference to FirstFailureData to assign from.
+        /// @return Reference to 'this' FirstFailureData
+        ///
+        FirstFailureData & operator=(const FirstFailureData & i_right) = default;
+
+        ///
+        /// @brief Sets a HWP error. Sets the rcValue to the supplied value (from
+        ///      the HwpFirstFailureData enumeration) and deletes any
+        /// associated data.
+        ///
+        /// HWP code must call the FAPI_SET_HWP_ERROR macro rather than this
+        /// function
+        /// directly to generate an error so that any error information is
+        /// automatically added to the FirstFailureData
+        ///
+        /// @param[in] i_rcValue Error value to set
+        ///
+        inline void _setHwpError(const fapi2::HwpReturnCode i_rcValue)
+            {
+                FAPI_ERR("_setHwpError: Creating HWP error 0x%x", i_rcValue);
+                static_cast<R*>(this)->operator=(i_rcValue);
+
+                // Forget about any associated data (this is a new error)
+                iv_info.reset(new ErrorInfo());
+            }
+
+        ///
+        /// @brief Get a pointer to any PlatData. FirstFailureData is still
+        ///        responsible for deletion of the data. The caller must not
+        ///        delete
+        ///
+        /// This is called by PLAT. The expected use-case is to get a pointer to
+        /// a platform error log. The data pointer should be used immediately in
+        /// the same thread.
+        ///
+        /// @return void *. Pointer to any PlatData. If NULL then no data
+        ///
+        void* getData(void) const;
+
+        ///
+        /// @brief Get a pointer to any PlatData and release ownership from
+        ///      FirstFailureData. The caller is responsible for deletion.
+        ///
+        /// This is called by PLAT. The expected use-case is to retrieve a
+        /// platform error log.
+        ///
+        /// @return void*. Pointer to any PlatData. If NULL then no data
+        ///
+        void* releaseData(void);
+
+        ///
+        /// @brief Add ErrorInfo
+        ///
+        /// This is called by the FAPI_SET_HWP_ERROR and macro to add ErrorInfo
+        /// to the FirstFailureData when a HWP generates an error. The function
+        /// is designed to add all the ErrorInfo at once rather than the
+        /// FAPI_SET_HWP_ERROR macro making multiple function calls to add each
+        /// piece of ErrorInfo individually in order to minimize code size
+        ///
+        /// @param[in] i_pObjects Pointer to array of const pointers to const
+        ///     objects that are referred to by ErrorInfoEntry objects
+        /// @param[in] i_pEntries Pointer to array of ErrorInfoEntry objects
+        ///     defining the ErrorInfo that needs to be added
+        /// @param[in] i_count    Number of ErrorInfoEntry entries
+        ///
+        void addErrorInfo(const void* const * i_pObjects,
+                          const ErrorInfoEntry* i_pEntries,
+                          const uint8_t i_count);
+
+        ///
+        /// @brief Get a pointer to any ErrorInfo
+        ///
+        /// This is called by PLAT to find information about an error
+        ///
+        /// @return ErrorInfo *. Pointer to any ErrorInfo. If NULL then no info
+        ///
+        inline const fapi2::ErrorInfo* getErrorInfo(void) const
+            { return iv_info.get(); }
+
+        ///
+        /// @brief Forgets about any associated data (PlatData and ErrorInfo)
+        ///
+        /// If this is the only FirstFailureData pointing to the data then the
+        /// data is deleted
+        ///
+        inline void forgetData(void)
+            { iv_info = nullptr; }
+
+    private:
+
+        // Pointer to the data
+        std::shared_ptr<ErrorInfo> iv_info;
+    };
+
+}
+#endif // FAPI2_FFDC_H_
diff --git a/src/ppe/importtemp/fapi2/include/hw_access.H b/src/ppe/importtemp/fapi2/include/hw_access.H
new file mode 100644
index 0000000..3545633
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/hw_access.H
@@ -0,0 +1,582 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/hw_access.H $                */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+/// @file hw_access.H
+///
+/// @brief Hardware access functions that needs to be specialized for
+/// platform implementation.
+///
+
+#ifndef _FAPI2_HWACCESS_H_
+#define _FAPI2_HWACCESS_H_
+
+    // variable_buffer isn't supported on PPE
+#ifndef __PPE__
+#include <variable_buffer.H>
+#endif
+
+#include <plat_hw_access.H>
+#include <fapi2_hw_access.H>
+
+namespace fapi2
+{
+    //--------------------------------------------------------------------------
+    // PIB Error Functions
+    //--------------------------------------------------------------------------
+
+    /// @brief Sets the PIB error mask - platform dependant
+    /// @param[in]  i_mask     The new error mask
+    // note: this can be moved  to a C file if desired
+    inline void setPIBErrorMask(uint8_t i_mask)
+    {
+        // Keeps the compiler from complaining about the unused i_mask
+        static_cast<void>(i_mask);
+
+        return;
+    }
+
+    /// @brief Gets the PIB error mask - platform dependant
+    /// @return uint8_t The current PIB error mask
+    // note: this can be moved  to a C file if desired
+    inline uint8_t getPIBErrorMask(void)
+    {
+        return 0;
+    }
+
+    //--------------------------------------------------------------------------
+    // Operational Mode Error Functions
+    //--------------------------------------------------------------------------
+
+    /// @brief Sets the operational mode
+    /// @param[in]  i_mode     The new mode
+    // note: this can be moved  to a C file if desired
+    inline void setOpMode(const OpModes i_mode)
+    {
+        // Keeps the compiler from complaining about the unused i_mode
+        static_cast<void>(i_mode);
+
+        // No-op for now. Should set thread-local operational mode
+        return;
+    }
+
+    /// @brief Gets the operational mode
+    /// @return the operational mode
+    // note: this can be moved  to a C file if desired
+    inline OpModes getOpMode(void)
+    {
+        // No-op for now. Should read thread-local operational mode
+        return NORMAL;
+    }
+
+    //------------------------------------------------------------------------------
+    // HW Communication Functions to be implemented at the platform layer.
+    //------------------------------------------------------------------------------
+
+    ///
+    /// @brief Platform-level implementation of getScom()
+    /// @Tparam K template parameter, passed in target.
+    /// @param[in]  i_target   HW target to operate on.
+    /// @param[in]  i_address  SCOM register address to read from.
+    /// @param[out] o_date     Buffer that holds data read from HW target.
+    /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    template< TargetType K >
+    inline ReturnCode getScom(const Target<K>& i_target,
+                              const uint64_t i_address,
+                              buffer<uint64_t>& o_data)
+    {
+        o_data = 0x0000FEEDFACE0000;
+        std::cout << std::hex << "   getScom "
+                  << "target: {" << i_target.getType() << ","
+                  << uint64_t(i_target) << "}; "
+                  << "address: " << i_address << "; "
+                  << "output data: " << uint64_t(o_data)
+                  << std::dec << std::endl;
+
+        return FAPI2_RC_SUCCESS;
+    }
+
+    /// @brief Platform-level implementation of putScom()
+    /// @Tparam K template parameter, passed in target.
+    /// @param[in] i_target     HW target to operate on.
+    /// @param[in] i_address    SCOM register address to write to.
+    /// @param[in] i_data       Buffer that holds data to write into address.
+    /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode putScom(const Target<K>& i_target,
+                              const uint64_t i_address,
+                              const buffer<uint64_t> i_data)
+    {
+        std::cout << std::hex << "   putScom "
+                  << "target: {" << i_target.getType() << ","
+                  << uint64_t(i_target) << "}; "
+                  << "address: " << i_address << "; "
+                  << "input data: " << uint64_t(i_data)
+                  << std::dec << std::endl;
+        return FAPI2_RC_SUCCESS;
+    }
+
+    /// @brief Platform-level implementation of putScomUnderMask()
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target     HW target to operate on.
+    /// @param[in] i_address    SCOM register address to write to.
+    /// @param[in] i_data       Buffer that holds data to write into address.
+    /// @param[in] i_mask       Buffer that holds the mask value.
+    /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode putScomUnderMask(const Target<K>& i_target,
+                                       const uint64_t i_address,
+                                       const buffer<uint64_t> i_data,
+                                       const buffer<uint64_t> i_mask)
+    {
+        std::cout << std::hex << "   putScomUnderMask "
+                  << "target: {" << i_target.getType() << ","
+                  << uint64_t(i_target) << "}; "
+                  << "address: " << i_address << "; "
+                  << "input data: " << uint64_t(i_data) << "; "
+                  << "input mask: " << uint64_t(i_mask)
+                  << std::dec << std::endl;
+        return FAPI2_RC_SUCCESS;
+    }
+
+    ///
+    /// @brief Platform-level implementation called by getCfamRegister()
+    /// Hardware procedures writers will not call this function.
+    /// @Tparam K template parameter, passed in target.
+    /// @param[in]  i_target   HW target to operate on.
+    /// @param[in]  i_address  CFAM address to read from.
+    /// @param[out] o_data     32-bit buffer that holds data read from HW target.
+    /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    template< TargetType K >
+    inline ReturnCode getCfamRegister(const Target<K>& i_target,
+                                      const uint32_t i_address,
+                                      buffer<uint32_t>& o_data)
+    {
+        o_data = 0xFEED0CFA;
+        std::cout << std::hex << "   getCfamRegister "
+                  << "target: {" << i_target.getType() << ","
+                  << uint64_t(i_target) << "}; "
+                  << "address: " << i_address << "; "
+                  << "output data: " << uint32_t(o_data)
+                  << std::dec << std::endl;
+        return FAPI2_RC_SUCCESS;
+    }
+
+    ///
+    /// @brief Platform-level implementation of putCfamRegister()
+    /// Hardware procedures writers will not call this function.
+    /// @Tparam K template parameter, passed in target.
+    /// @param[in]  i_target   HW target to operate on.
+    /// @param[in]  i_address  CFAM address to write to.
+    /// @param[out] i_data     32-bit buffer that holds data to write into address.
+    /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    template< TargetType K >
+    inline ReturnCode putCfamRegister(const Target<K>& i_target,
+                                      const uint32_t i_address,
+                                      const buffer<uint32_t> i_data)
+    {
+        std::cout << std::hex << "   putCfamRegister "
+                  << "target: {" << i_target.getType() << ","
+                  << uint64_t(i_target) << "}; "
+                  << "address: " << i_address << "; "
+                  << "input data: " << uint32_t(i_data)
+                  << std::dec << std::endl;
+        return FAPI2_RC_SUCCESS;
+    }
+
+
+    ///
+    /// @brief Platform-level implementation of modifyCfamRegister()
+    /// Hardware procedures writers will not call this function.
+    /// @Tparam K template parameter, passed in target.
+    /// @param[in]  i_target     HW target to operate on.
+    /// @param[in]  i_address    CFAM register address to modify.
+    /// @param[out] i_data       32-bit buffer that holds data to modify.
+    /// @param[in]  i_modifyMode The modify mode (or/and/xor).
+    /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    template< TargetType K >
+    inline ReturnCode modifyCfamRegister(const Target<K>& i_target,
+                                         const uint32_t i_address,
+                                         const buffer<uint32_t> i_data,
+                                         const fapi2::ChipOpModifyMode i_modifyMode)
+    {
+        std::cout << std::hex << "   modifyCfamRegister "
+                  << "target: {" << i_target.getType() << ","
+                  << uint64_t(i_target) << "}; "
+                  << "address: " << i_address << "; "
+                  << "input modifying data: " << uint32_t(i_data) << "; "
+                  << "input ChipOpModifyMode: " << i_modifyMode
+                  << std::dec << std::endl;
+        return FAPI2_RC_SUCCESS;
+    }
+
+    // variable_buffer isn't supported on PPE
+#ifndef __PPE__
+    ///
+    /// @brief Platform-level implementation of getRing()
+    /// Hardware procedures writers will not call this function.
+    /// @Tparam K template parameter, passed in target.
+    /// @param[in]  i_target   HW target to operate on.
+    /// @param[in]  i_address  Ring address to read from.
+    /// @param[out] o_data     Buffer that holds ring data read from HW target.
+    /// @param[in]  i_ringMode Ring operation mode.
+    /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    template< TargetType K >
+    inline ReturnCode getRing(const Target<K>& i_target,
+                              const scanRingId_t i_address,
+                              variable_buffer& o_data,
+                              const RingMode i_ringMode)
+    {
+        o_data.setBit(0);
+        o_data.setBit(3);
+        std::cout << std::hex << "   getRing "
+                  << "target: {" << i_target.getType() << ","
+                  << uint64_t(i_target) << "}; "
+                  << "ring address: " << i_address << "; "
+                  << "ring mode: " << i_ringMode << "; "
+                  << "first element of output data: " << o_data()[0]
+                  << std::endl;
+
+        return FAPI2_RC_SUCCESS;
+    }
+
+    /// @brief Platform-level implementation  of putRing()
+    /// Hardware procedures writers will not call this function.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target   Target to operate on.
+    /// @param[in] i_address  Ring address to write to.
+    /// @param[in] i_data     Buffer that contains RS4 compressed ring data
+    ///                       to write into address
+    /// @param[in] i_ringMode Ring operation mode.
+    /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode putRing(const Target<K>& i_target,
+                              const scanRingId_t i_address,
+                              const variable_buffer& i_data,
+                              const RingMode i_ringMode)
+    {
+        std::cout << std::hex << "   putRing "
+                  << "target: {" << i_target.getType() << ","
+                  << uint64_t(i_target) << "}; "
+                  << "address: " << i_address << "; "
+                  << "ring mode: " << i_ringMode << "; "
+                  << "first element of the input data: " << i_data()[0]
+                  << std::endl;
+
+        return FAPI2_RC_SUCCESS;
+    }
+
+    /// @brief Platform-level implementation of modifyRing()
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target     Target to operate on.
+    /// @param[in] i_address    Ring address to modify.
+    /// @param[in] i_data       Buffer that contains RS4 compressed ring data
+    ///                         to be modified.
+    /// @param[in] i_modifyMode The modify mode (or/and/xor)
+    /// @param[in] i_ringMode   Ring operation mode.
+    /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode modifyRing(const Target<K>& i_target,
+                                 const scanRingId_t i_address,
+                                 const variable_buffer& i_data,
+                                 const ChipOpModifyMode i_modifyMode,
+                                 const RingMode i_ringMode)
+    {
+        std::cout << std::hex << "   modifyRing "
+                  << "target: {" << i_target.getType() << ","
+                  << uint64_t(i_target) << "}; "
+                  << "address: " << i_address << "; "
+                  << "input ChipOpModifyMode: " << i_modifyMode << "; "
+                  << "ring mode: " << i_ringMode << "; "
+                  << "first element of the input data: " << i_data()[0]
+                  << std::endl;
+
+        return FAPI2_RC_SUCCESS;
+    }
+#endif
+
+#ifdef FAPI_SUPPORT_MULTI_SCOM
+    /// @brief Performs a multiple SCOM operation
+    ///        This interface performs multiple SCOM operations on a chip in the
+    ///        order specified by the input MultiScom object.
+    ///        See fapiMultiScom.H for details of how to populate the MultiScom
+    ///        object with SCOM operations.
+    ///
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]     i_target Target to operate on.
+    /// @param[in,out] io_multiScomObj Reference to a MultiScom object,
+    ///                                pre-populated with SingleScomInfo entries
+    ///                                to perform multiple SCOMs on input target
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note   This is a synchronous interface and would return after all the
+    ///         SCOM operations are completed or on the first failed operation
+    ///
+    /// @note   SCOMs will be performed in the order they were added to the
+    ///         input MultiScom object
+    ///
+    /// @note   In case of errors, the platform code is responsible to collect
+    ///         and add all the required error info and FFDC into the error data
+    ///         for debugging
+    ///
+    /// @note   If the SCOM operations added are specific to a processor chip,
+    ///         then the FSI Shift Engine configured in scatter-gather DMA mode
+    ///         extension would be used to execute the SCOM operations in a
+    ///         performance optimize mode. In this mode, the special
+    ///         SCOM_BULK_READ_MODE and SCOM_BULK_WRITE_MODE operations are
+    ///         supported that allow a large bulk of SCOM access (in multiple of
+    ///         64 bits) for targets that support auto-increment. The
+    ///         SCOM_WRITE_UNDER_MASK operation is not supported in this mode
+    ///
+    /// @note   If the SCOM operations added are specific to a memory buffer
+    ///         chip, then the regular SCOM engine is used to execute the SCOM
+    ///         operations. SCOM_WRITE_UNDER_MASK operation is supported in
+    ///         this mode, but the special SCOM_BULK_READ_MODE and
+    ///         SCOM_BULK_WRITE_MODE operations are not supported due to
+    ///         hardware limitations.
+    ///
+    template< TargetType K >
+    fapi2::ReturnCode multiScom (const Target<K>& i_target,
+                                 MultiScom&  io_multiScomObj)
+    {
+    }
+#endif
+
+    // --------------------------------------------------------------------------
+    // NOTE:
+    // Implement platform Spy access functions if platform supports them.
+    // --------------------------------------------------------------------------
+
+    // variable_buffer isn't supported on PPE
+#ifndef __PPE__
+    /// @brief Reads a spy from a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target   Target to operate on.
+    /// @param[in]  i_spyId    Id of the spy whose data to be read.
+    /// @param[out] o_data     Buffer that holds data read from HW target.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note:  The string version is only supported for cronus.
+    ///
+    ///         The fapi design to support both FSP and cronus use of get and
+    ///         put spy functions is dependant on the SPY names being expanded
+    ///         to resemble a valid C identifier. This design places some
+    ///         restrictions on the SPY names which can be used.
+    ///
+    ///         1. if the spy name contains a # procedure writers should replace
+    ///         it with an __P__ for example -
+    ///
+    ///         ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+    ///         becomes
+    ///         ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS
+    ///
+    ///         2. if the spy name has a number following a "." it must have an
+    ///         underscore prepended to the number.
+    ///
+    ///         EH.TPCHIP.2KX100_ARY_CLK_EDGES_DLY
+    ///         becomes
+    ///         EH.TPCHIP._2KX100_ARY_CLK_EDGES_DLY
+    ///
+    ///         Example SPY name:
+    ///         The hardware procedure should call the function like:
+    ///
+    ///          ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+    ///
+    ///          fapi2::ReturnCode rc = fapiGetSpy( targ,
+    ///                  ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS, data );
+    ///
+    /// @note The ID is not in quotes the fapi code will handle adding
+    ///       the quotes for the cronus environment
+    ///
+#ifdef FAPI_SUPPORT_SPY_AS_ENUM
+    template< TargetType K >
+    inline ReturnCode getSpy(const Target<K>& i_target,
+                             const spyId_t i_spyId,
+                             variable_buffer& o_data)
+    {
+        static_assert(K == 0, "implement getSpy (string)");
+        return ~FAPI2_RC_SUCCESS;
+    }
+#endif
+#ifdef FAPI_SUPPORT_SPY_AS_STRING
+    template< TargetType K >
+    inline ReturnCode getSpy(const Target<K>& i_target,
+                             const char * const i_spyId,
+                             variable_buffer& o_data)
+    {
+        static_assert(K == 0, "implement getSpy (string)");
+        return ~FAPI2_RC_SUCCESS;
+    }
+#endif
+    /// @brief Writes a spy on a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target   Target to operate on.
+    /// @param[in]  i_spyId    Id of the spy to write data to.
+    /// @param[out] i_data     Buffer that holds data to write into spy.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note:  The string version is only supported for cronus.
+    ///
+    ///         The fapi design to support both FSP and cronus use of get and
+    ///         put spy functions is dependent on the SPY names being expanded
+    ///         to resemble a valid C identifier. This design places some
+    ///         restrictions on the SPY names which can be used.
+    ///
+    ///         1. if the spy name contains a # procedure writers should replace
+    ///         is with an __P__ for example -
+    ///
+    ///         ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+    ///         becomes
+    ///         ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS
+    ///
+    ///         2. if the spy name has a number following a "." it must have an
+    ///         underscore prepended to the number.
+    ///
+    ///         EH.TPCHIP.2KX100_ARY_CLK_EDGES_DLY
+    ///         becomes
+    ///         EH.TPCHIP._2KX100_ARY_CLK_EDGES_DLY
+    ///
+    ///         Example SPY name:
+    ///         The hardware procedure should call the function like:
+    ///
+    ///          ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+    ///
+    ///          fapi2::ReturnCode rc = fapiPutSpy( targ,
+    ///                  ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS, data );
+    ///
+    /// @note The ID is not in quotes the fapi code will handle adding
+    ///         the quotes for the cronus environment
+    ///
+#ifdef FAPI_SUPPORT_SPY_AS_ENUM
+    template< TargetType K >
+    inline ReturnCode putSpy(const Target<K>& i_target,
+                             const spyId_t i_spyId,
+                             variable_buffer& i_data)
+    {
+        static_assert(K == 0, "implement putSpy (enum)");
+        return ~FAPI2_RC_SUCCESS;
+    }
+#endif
+#ifdef FAPI_SUPPORT_SPY_AS_STRING
+    template< TargetType K >
+    inline ReturnCode putSpy(const Target<K>& i_target,
+                             const char* const i_spyId,
+                             variable_buffer& i_data)
+    {
+        static_assert(K == 0, "implement putSpy (string)");
+        return ~FAPI2_RC_SUCCESS;
+    }
+#endif
+    /// @brief Writes spy data into a buffer holding ring data image
+    ///        This API is used by L2/L3 repair to put column repair data
+    ///        into a ring buffer image.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target Target to operate on.
+    /// @param[in]  i_spyId  Id of the spy.
+    /// @param[in]  i_data   Buffer that holds spy data to write into ring
+    ///                      image.
+    /// @param[out] o_data   Buffer that holds updated ring image.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note:  The string version is only supported for cronus.
+    ///
+    ///         The fapi design to support both FSP and cronus use of get and
+    ///         put spy functions is dependent on the SPY names being expanded
+    ///         to resemble a valid C identifier. This design places some
+    ///         restrictions on the SPY names which can be used.
+    ///
+    ///         See fapiPutSpy for details on spy id specifics.
+    ///
+#ifdef FAPI_SUPPORT_SPY_AS_ENUM
+    template< TargetType K >
+    inline ReturnCode putSpyImage(const Target<K>& i_target,
+                                  const spyId_t i_spyId,
+                                  const variable_buffer& i_data,
+                                  variable_buffer& o_imageData)
+    {
+        static_assert(K == 0, "implement putSpyImage (enum)");
+        return ~FAPI2_RC_SUCCESS;
+    }
+#endif
+#ifdef FAPI_SUPPORT_SPY_AS_STRING
+    template< TargetType K >
+    inline ReturnCode putSpyImage(const Target<K>& i_target,
+                                  const char* const i_spyId,
+                                  const variable_buffer& i_data,
+                                  variable_buffer& o_imageData)
+    {
+        static_assert(K == 0, "implement putSpyImage (string)");
+        return ~FAPI2_RC_SUCCESS;
+    }
+#endif
+    /// @brief Reads spy data from a ring image buffer
+    /// @param[in]   i_target      Target to operate on
+    /// @param[in]   i_spyId       The spy's id
+    /// @param[out]  o_data        Buffer that holds data read from ring image.
+    /// @param[in]   i_imageData   Buffer that holds ring image to read data
+    ///                            from.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note:  The string version is only supported for cronus.
+    ///
+    ///         The fapi design to support both FSP and cronus use of get and
+    ///         put spy functions is dependent on the SPY names being expanded
+    ///         to resemble a valid C identifier. This design places some
+    ///         restrictions on the SPY names which can be used.
+    ///
+    ///         See fapiPutSpy for details on spy id specifics.
+    ///
+#ifdef FAPI_SUPPORT_SPY_AS_ENUM
+    template< TargetType K >
+    inline ReturnCode getSpyImage(const Target<K>& i_target,
+                                  const spyId_t i_spyId,
+                                  variable_buffer& o_data,
+                                  const variable_buffer& i_imageData)
+    {
+        static_assert(K == 0, "implement getSpyImage (enum)");
+        return ~FAPI2_RC_SUCCESS;
+    }
+#endif
+#ifdef FAPI_SUPPORT_SPY_AS_STRING
+    template< TargetType K >
+    inline ReturnCode getSpyImage(const Target<K>& i_target,
+                                  const char * const i_spyId,
+                                  variable_buffer& o_data,
+                                  const variable_buffer& i_imageData)
+    {
+        static_assert(K == 0, "implement getSpyImage (string)");
+        return ~FAPI2_RC_SUCCESS;
+    }
+#endif
+
+#endif // PPE
+
+};
+
+#endif // _FAPI2_HWACCESS_H_
diff --git a/src/ppe/importtemp/fapi2/include/hw_access_def.H b/src/ppe/importtemp/fapi2/include/hw_access_def.H
new file mode 100644
index 0000000..1832a60
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/hw_access_def.H
@@ -0,0 +1,77 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/hw_access_def.H $            */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file hw_access_def.H
+/// @brief Hardware access definitions
+///
+
+#ifndef FAPI2_HWACCESSDEF_H_
+#define FAPI2_HWACCESSDEF_H_
+
+#include <stdint.h>
+
+/// @cond
+typedef uint64_t spyId_t;
+typedef uint64_t scanRingId_t;
+/// @endcond
+
+namespace fapi2
+{
+    ///
+    /// @enum fapi2::ChipOpModifyMode
+    /// @brief Enumeration of modify modes used in HW access modify operations
+    ///
+    enum ChipOpModifyMode
+    {
+        CHIP_OP_MODIFY_MODE_OR = 1,  ///< Modify or mode
+        CHIP_OP_MODIFY_MODE_AND = 2, ///< Modify and mode
+        CHIP_OP_MODIFY_MODE_XOR = 3, ///< Modify xor mode
+    };
+
+    ///
+    /// @enum fapi2::RingMode
+    /// @brief Enumeration of Ring access operation modes
+    ///        This is a bitmap to allow the user to specify multiple modes.
+    ///
+    enum RingMode
+    {
+        RING_MODE_SET_PULSE       = 0x00000001, ///< Set pulse
+        RING_MODE_NO_HEADER_CHECK = 0x00000002, ///< Dont' check header
+        // FUTURE_MODE            = 0x00000004,
+        // FUTURE_MODE            = 0x00000008,
+    };
+
+    /// @enum OpModes operational Mode Error Functions
+    enum OpModes
+    {
+        // These are bit-masks in case they need to be or'd together
+        NORMAL           = 0x00,
+        IGNORE_HW_ERROR  = 0x01,
+        DO_NOT_DO_WAKEUP = 0x02,
+    };
+
+}
+
+#endif
diff --git a/src/ppe/importtemp/fapi2/include/mvpd_access.H b/src/ppe/importtemp/fapi2/include/mvpd_access.H
new file mode 100644
index 0000000..390d1ff
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/mvpd_access.H
@@ -0,0 +1,165 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/mvpd_access.H $              */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file mvpd_access.H
+///
+/// @brief Defines the Module VPD functions that platform must implement
+///
+
+#ifndef _FAPI2_MVPDACCESS_H_
+#define _FAPI2_MVPDACCESS_H_
+
+#include <stdint.h>
+#include <return_code.H>
+#include <target.H>
+
+namespace fapi2
+{
+enum MvpdRecord
+{
+    MVPD_RECORD_CRP0 = 0x00,
+    MVPD_RECORD_CP00 = 0x01,
+    MVPD_RECORD_VINI = 0x02,
+    MVPD_RECORD_LRP0 = 0x03,
+    MVPD_RECORD_LRP1 = 0x04,
+    MVPD_RECORD_LRP2 = 0x05,
+    MVPD_RECORD_LRP3 = 0x06,
+    MVPD_RECORD_LRP4 = 0x07,
+    MVPD_RECORD_LRP5 = 0x08,
+    MVPD_RECORD_LRP6 = 0x09,
+    MVPD_RECORD_LRP7 = 0x0a,
+    MVPD_RECORD_LRP8 = 0x0b,
+    MVPD_RECORD_LRP9 = 0x0c,
+    MVPD_RECORD_LRPA = 0x0d,
+    MVPD_RECORD_LRPB = 0x0e,
+    MVPD_RECORD_LRPC = 0x0f,
+    MVPD_RECORD_LRPD = 0x10,
+    MVPD_RECORD_LRPE = 0x11,
+    MVPD_RECORD_LWP0 = 0x12,
+    MVPD_RECORD_LWP1 = 0x13,
+    MVPD_RECORD_LWP2 = 0x14,
+    MVPD_RECORD_LWP3 = 0x15,
+    MVPD_RECORD_LWP4 = 0x16,
+    MVPD_RECORD_LWP5 = 0x17,
+    MVPD_RECORD_LWP6 = 0x18,
+    MVPD_RECORD_LWP7 = 0x19,
+    MVPD_RECORD_LWP8 = 0x1a,
+    MVPD_RECORD_LWP9 = 0x1b,
+    MVPD_RECORD_LWPA = 0x1c,
+    MVPD_RECORD_LWPB = 0x1d,
+    MVPD_RECORD_LWPC = 0x1e,
+    MVPD_RECORD_LWPD = 0x1f,
+    MVPD_RECORD_LWPE = 0x20,
+    MVPD_RECORD_VWML = 0x21,
+    MVPD_RECORD_MER0 = 0x22,
+};
+
+enum MvpdKeyword
+{
+    MVPD_KEYWORD_VD  = 0x00,
+    MVPD_KEYWORD_ED  = 0x01,
+    MVPD_KEYWORD_TE  = 0x02,
+    MVPD_KEYWORD_DD  = 0x03,
+    MVPD_KEYWORD_PDP = 0x04,
+    MVPD_KEYWORD_ST  = 0x05,
+    MVPD_KEYWORD_DN  = 0x06,
+    MVPD_KEYWORD_PG  = 0x07,
+    MVPD_KEYWORD_PK  = 0x08,
+    MVPD_KEYWORD_PDR = 0x09,
+    MVPD_KEYWORD_PDV = 0x0a,
+    MVPD_KEYWORD_PDH = 0x0b,
+    MVPD_KEYWORD_SB  = 0x0c,
+    MVPD_KEYWORD_DR  = 0x0d,
+    MVPD_KEYWORD_VZ  = 0x0e,
+    MVPD_KEYWORD_CC  = 0x0f,
+    MVPD_KEYWORD_CE  = 0x10,
+    MVPD_KEYWORD_FN  = 0x11,
+    MVPD_KEYWORD_PN  = 0x12,
+    MVPD_KEYWORD_SN  = 0x13,
+    MVPD_KEYWORD_PR  = 0x14,
+    MVPD_KEYWORD_HE  = 0x15,
+    MVPD_KEYWORD_CT  = 0x16,
+    MVPD_KEYWORD_HW  = 0x17,
+    MVPD_KEYWORD_PDM = 0x18,
+    MVPD_KEYWORD_IN  = 0x19,
+    MVPD_KEYWORD_PD2 = 0x1a,
+    MVPD_KEYWORD_PD3 = 0x1b,
+    MVPD_KEYWORD_OC  = 0x1c,
+    MVPD_KEYWORD_FO  = 0x1d,
+    MVPD_KEYWORD_PDI = 0x1e,
+    MVPD_KEYWORD_PDG = 0x1f,
+    MVPD_KEYWORD_MK  = 0x20,
+    MVPD_KEYWORD_PB  = 0x21,
+    MVPD_KEYWORD_CH  = 0x22,
+    MVPD_KEYWORD_IQ  = 0x23,
+};
+
+///
+/// @brief Get Module VPD field.
+///
+/// A Module VPD field is specified using a record and keyword enumerator
+///
+/// Suggested way to call this routine is to call it once with a NULL buffer
+/// pointer to to retrieve the size of the record, then allocate the proper
+/// size of the buffer and call again.
+///
+/// @param[in] i_record     Record enumerator
+/// @param[in] i_keyword    Keyword enumerator
+/// @param[in] i_target     Reference to processor chip target for the record
+/// @param[in] i_pBuffer    Pointer to buffer where record will be stored. If
+///                         NULL then the size of record will be stored in
+///                         io_fieldSize
+/// @param[in,out] io_fieldSize Size of i_pBuffer in bytes
+///
+/// @return fapi2::ReturnCode. FAPI_RC_SUCCESS, or failure value.
+///
+ReturnCode getMvpdField(const MvpdRecord i_record,
+                        const MvpdKeyword i_keyword,
+                        const Target<TARGET_TYPE_PROC_CHIP> &i_target,
+                        uint8_t * const i_pBuffer,
+                        uint32_t &io_fieldSize);
+
+///
+/// @brief Set Module VPD field.
+///
+/// A Module VPD field is specified using a record and keyword enumerator
+///
+/// @param[in] i_record     Record enumerator
+/// @param[in] i_keyword    Keyword enumerator
+/// @param[in] i_target     Reference to processor chip target for the record
+/// @param[in] i_pBuffer    Pointer to buffer where data to set is stored
+/// @param[in] i_fieldSize  Size of i_pBuffer in bytes
+///
+/// @return fapi2::ReturnCode. FAPI_RC_SUCCESS, or failure value.
+///
+ReturnCode setMvpdField(const MvpdRecord i_record,
+                        const MvpdKeyword i_keyword,
+                        const Target<TARGET_TYPE_PROC_CHIP> &i_target,
+                        const uint8_t * const i_pBuffer,
+                        const uint32_t i_fieldSize);
+}
+
+#endif
diff --git a/src/ppe/importtemp/fapi2/include/plat_error_scope.H b/src/ppe/importtemp/fapi2/include/plat_error_scope.H
new file mode 100644
index 0000000..517b890
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/plat_error_scope.H
@@ -0,0 +1,64 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/plat_error_scope.H $         */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file plat_error_scope.H
+ * @brief platform definitions which create a scope for automatic error handling
+ */
+
+#ifndef __FAPI2_PLAT_ERROR_SCOPE__
+#define __FAPI2_PLAT_ERROR_SCOPE__
+
+/// @cond
+#define PLAT_FAPI_TRY_NO_TRACE( __operation__ )                         \
+    if ((fapi2::current_err = (__operation__)) != fapi2::FAPI2_RC_SUCCESS) \
+    {                                                                   \
+        goto fapi_try_exit;                                             \
+    }
+
+#define PLAT_FAPI_TRY_TRACE( __operation__, ... )                       \
+    if ((fapi2::current_err = (__operation__)) != fapi2::FAPI2_RC_SUCCESS) \
+    {                                                                   \
+        FAPI_ERR(__VA_ARGS__);                                          \
+        goto fapi_try_exit;                                             \
+    }
+
+///
+/// @brief Assert a conditional is true.
+/// If it is not, the FFDC gathering function is called and the
+/// trace is output as a FAPI error trace.
+/// @param[in] __conditional__ the condition to assert
+/// @param[in] __ffdc__ the FFDC gathering function
+/// @param[in] ... varargs, as input to FAPI_ERR
+///
+#define PLAT_FAPI_ASSERT( __conditional__, __ffdc__, ... )      \
+    if (! (__conditional__))                                    \
+    {                                                           \
+        (__ffdc__).execute();                                   \
+        FAPI_ERR(__VA_ARGS__);                                  \
+        goto fapi_try_exit;                                     \
+    }
+/// @endcond
+
+#endif
diff --git a/src/ppe/importtemp/fapi2/include/plat_hw_access.H b/src/ppe/importtemp/fapi2/include/plat_hw_access.H
new file mode 100644
index 0000000..b472990
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/plat_hw_access.H
@@ -0,0 +1,39 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/plat_hw_access.H $           */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+/// @file plat_hw_access.H
+///
+/// @brief Platform hardware-access definitions
+///
+
+#ifndef _FAPI2_PLAT_HWACCESS_H_
+#define _FAPI2_PLAT_HWACCESS_H_
+
+namespace fapi2
+{
+
+}
+
+#endif // _FAPI2_PLAT_HWACCESS_H_
diff --git a/src/ppe/importtemp/fapi2/include/plat_target.H b/src/ppe/importtemp/fapi2/include/plat_target.H
new file mode 100644
index 0000000..46dfa60
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/plat_target.H
@@ -0,0 +1,43 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/plat_target.H $              */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file plat_target.H
+ * @brief platform definitions for fapi2 targets
+ */
+
+#ifndef __FAPI2_PLAT_TARGET__
+#define __FAPI2_PLAT_TARGET__
+
+//
+// Define what a platform handle looks like. For Hostboot,
+// for example, this might be a void*. For the SBE, this
+// will be a uint64_t ...
+//
+namespace fapi2
+{
+    typedef uint64_t plat_target_handle_t;
+}
+
+#endif
diff --git a/src/ppe/importtemp/fapi2/include/plat_trace.H b/src/ppe/importtemp/fapi2/include/plat_trace.H
new file mode 100644
index 0000000..937d6ac
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/plat_trace.H
@@ -0,0 +1,70 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/plat_trace.H $               */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ *  @file plat_trace.H
+ *  @brief Defines the FAPI2 trace macros.
+ *
+ *  Note that platform code must provide the implementation.
+ *
+ *  FAPI has provided a default implementation. Platform code must
+ *  provide an alternate implementation if needed.
+ */
+
+#ifndef FAPI2_PLATTRACE_H_
+#define FAPI2_PLATTRACE_H_
+
+#include <stdio.h>
+#include <stdint.h>
+
+// Why not a #define, why is this in the fapi2 namespace?
+// To prevent problems with Cronus and the fapi1 definitions.
+namespace fapi2
+{
+    static const uint32_t MAX_ECMD_STRING_LEN = 64;
+};
+
+// Information traces (go into fast trace buffer that can wrap often)
+#define FAPI_TRACE(_id_, _fmt_, _args_...)                              \
+    printf("%s: %s:%d ", _id_, __func__, __LINE__);                     \
+    printf(_fmt_, ##_args_);                                            \
+    printf("\n")
+
+#define FAPI_INF(_fmt_, _args_...) FAPI_TRACE("inf", _fmt_, ##_args_)
+
+// Important traces (go into slow trace buffer that should not wrap often)
+#define FAPI_IMP(_fmt_, _args_...) FAPI_TRACE("imp", _fmt_, ##_args_)
+
+// Error traces (go into slow trace buffer that should not wrap often)
+#define FAPI_ERR(_fmt_, _args_...) FAPI_TRACE("err", _fmt_, ##_args_)
+
+// Debug traces (go into fast trace buffer that can wrap often)
+#define FAPI_DBG(_fmt_, _args_...) FAPI_TRACE("dbg", _fmt_, ##_args_)
+
+// Scan traces
+#define FAPI_SCAN(_fmt_, _args_...) FAPI_TRACE("scan", _fmt_, ##_args_)
+
+#define FAPI_MFG(_fmt_, _args_...) FAPI_TRACE("mfg", _fmt_, ##_args_)
+
+#endif // FAPI2_PLATTRACE_H_
diff --git a/src/ppe/importtemp/fapi2/include/return_code.H b/src/ppe/importtemp/fapi2/include/return_code.H
new file mode 100644
index 0000000..88aad0c
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/return_code.H
@@ -0,0 +1,120 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/return_code.H $              */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file return_code.H
+ * @brief definitions for fapi2 return codes
+ */
+
+#ifndef __FAPI2_RETURN_CODE__
+#define __FAPI2_RETURN_CODE__
+
+#include <stdint.h>
+
+#ifndef FAPI2_NO_FFDC
+    #include <ffdc.H>
+#endif
+
+namespace fapi2
+{
+///
+/// @brief Class representing a FAPI2 ReturnCode
+///
+// Remove the inheritance relationship with FirstFailureData if
+// the platform doesn't support FFDC.
+#ifdef FAPI2_NO_FFDC
+class ReturnCode
+#else
+class ReturnCode : public FirstFailureData<ReturnCode>
+#endif
+{
+    public:
+
+        ///
+        /// @brief Constructor.
+        /// @param[in] i_rc the rc to set
+        ///
+        ReturnCode(const uint64_t i_rc = FAPI2_RC_SUCCESS):
+            iv_rc(i_rc)
+        {};
+
+        ///
+        /// @brief integral type conversion function. Returns the error code
+        /// @return The error code
+        ///
+        inline operator uint64_t() const
+        {
+            return iv_rc;
+        }
+
+        ///
+        /// @brief Returns true iff iv_rc == SUCCESS
+        /// @return true or false
+        ///
+        inline operator bool() const
+        {
+            return iv_rc != FAPI2_RC_SUCCESS;
+        }
+
+        ///
+        /// @brief Assignement operator
+        ///
+        #ifdef DOXYGEN
+        inline ReturnCode& operator=(const uint64_t& rhs)
+        inline ReturnCode& operator=(const ReturnCodes& rhs)
+        #endif
+
+        inline bool operator==(const uint64_t& rhs) const
+        {
+            return rhs == iv_rc;
+        }
+
+        inline bool operator==(const ReturnCodes& rhs) const
+        {
+            return rhs == iv_rc;
+        }
+
+        inline bool operator!=(const uint64_t& rhs) const
+        {
+            return rhs != iv_rc;
+        }
+
+        inline bool operator!=(const ReturnCodes& rhs) const
+        {
+            return rhs != iv_rc;
+        }
+
+    private:
+        uint64_t iv_rc;
+};
+
+/// This implementation assumes no exception handling and leverages thread-local
+/// storage. For platforms without thread support, a global variable will
+/// suffice for the error state.
+extern thread_local ReturnCode current_err;      /// the current error state
+extern thread_local uint64_t pib_error_mask;     /// the pib mask
+extern thread_local uint64_t operational_state;  /// the operational mode
+}
+
+#endif
diff --git a/src/ppe/importtemp/fapi2/include/return_code_defs.H b/src/ppe/importtemp/fapi2/include/return_code_defs.H
new file mode 100644
index 0000000..7631c2d
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/return_code_defs.H
@@ -0,0 +1,114 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/return_code_defs.H $         */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file return_code.H
+ * @brief definitions for fapi2 return codes
+ */
+
+#ifndef __FAPI2_RETURN_CODE_DEFS_
+#define __FAPI2_RETURN_CODE_DEFS_
+
+#include <stdint.h>
+
+///
+/// @brief Set HWP Error macro
+///
+/// This macro should be used by a HWP to create an error. The ReturnCode's
+/// internal return code is set and any error information in the Error XML file
+/// is added to the ReturnCode
+///
+#define FAPI_SET_HWP_ERROR(RC, ERROR) \
+    RC._setHwpError(fapi2::ERROR); \
+    ERROR##_CALL_FUNCS_TO_COLLECT_FFDC(RC); \
+    ERROR##_CALL_FUNCS_TO_COLLECT_REG_FFDC(RC); \
+    ERROR##_ADD_ERROR_INFO(RC)
+
+///
+/// @brief Add info to HWP Error macro
+///
+/// This macro should be used by an FFDC HWP to add error information from an
+/// Error XML file to an existing error.
+///
+#define FAPI_ADD_INFO_TO_HWP_ERROR(RC, ERROR) \
+    ERROR##_CALL_FUNCS_TO_COLLECT_FFDC(RC); \
+    ERROR##_CALL_FUNCS_TO_COLLECT_REG_FFDC(RC); \
+    ERROR##_ADD_ERROR_INFO(RC)
+
+namespace fapi2
+{
+    ///
+    /// @brief Enumeration of return codes
+    ///
+    enum ReturnCodes
+    {
+        ///< Success
+        FAPI2_RC_SUCCESS = 0,
+
+        // Flag bits indicating which code generated the error.
+        FAPI2_RC_FAPI2_MASK = 0x04000000, ///< FAPI2 mask
+        FAPI2_RC_PLAT_MASK =  0x02000000, ///< Platform mask
+        FAPI2_RC_HWP_MASK =   0x00000000, ///< HWP mask
+
+        //
+        // FAPI generated return codes
+        //
+
+        FAPI2_RC_INVALID_ATTR_GET            = FAPI2_RC_FAPI2_MASK | 0x01,
+        ///< Initfile requested an attribute with an invalid attribute ID
+
+        FAPI2_RC_INVALID_CHIP_EC_FEATURE_GET = FAPI2_RC_FAPI2_MASK | 0x02,
+        ///< HWP requested a chip EC feature with an invalid attribute ID
+
+        FAPI2_RC_INVALID_MULTISCOM_LENGTH    = FAPI2_RC_FAPI2_MASK | 0x03,
+        ///< Invalid multiscom parameters
+
+        FAPI2_RC_INVALID_PARAMETER           = FAPI2_RC_FAPI2_MASK | 0x04,
+        ///< Invalid parameters to a FAPI2 function
+
+        FAPI2_RC_OVERFLOW                    = FAPI2_RC_FAPI2_MASK | 0x05,
+        ///< Overflow condition, typically a buffer operation
+
+        FAPI2_RC_FALSE                       = FAPI2_RC_FAPI2_MASK | 0x06,
+        ///< The logical opposite of SUCCESS. Needed where procedures want
+        ///< a multi-bool type of operation (e.g., true, false, scom error)
+
+        //
+        // PLAT generated return codes. Additional details may be contained in
+        // ReturnCode platData (this can only be looked at by PLAT code)
+        //
+
+        FAPI2_RC_PLAT_ERR_SEE_DATA   = FAPI2_RC_PLAT_MASK | 0x01,
+        ///< Generic platform error
+
+        FAPI2_RC_PLAT_ERR_ADU_LOCKED = FAPI2_RC_PLAT_MASK | 0x02,
+        ///< Operation to AlterDisplay unit failed because it is locked
+
+        FAPI2_RC_PLAT_NOT_SUPPORTED_AT_RUNTIME = FAPI2_RC_PLAT_MASK | 0x03,
+        ///< Operation not supported by HB runtime
+    };
+
+}
+
+#endif
diff --git a/src/ppe/importtemp/fapi2/include/target.H b/src/ppe/importtemp/fapi2/include/target.H
new file mode 100644
index 0000000..0bc3a7e
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/target.H
@@ -0,0 +1,171 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/target.H $                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file target.H
+ * @brief platform specializations for fapi2 targets
+ */
+
+#ifndef __FAPI2_TARGET__
+#define __FAPI2_TARGET__
+
+#include <plat_target.H>
+#include <fapi2_target.H>
+#include <stdio.h>
+
+namespace fapi2
+{
+
+    ///
+    /// @brief Assignment Operator.
+    /// @param[in] i_right Reference to Target to assign from.
+    /// @return Reference to 'this' Target
+    ///
+    template<TargetType K, typename V>
+    Target<K, V>& Target<K, V>::operator=(const Target& i_right)
+    { iv_handle = i_right.iv_handle; return *this; }
+
+    ///
+    /// @brief Equality Comparison Operator
+    /// @param[in] i_right Reference to Target to compare.
+    /// @return bool. True if equal.
+    /// @note Platforms need to define this so that the physical
+    /// targets are determined to be equivilent rather than just the handles
+    ///
+    template<TargetType K, typename V>
+    bool Target<K, V>::operator==(const Target& i_right) const
+    { return i_right.iv_handle == iv_handle; }
+
+    ///
+    /// @brief Inquality Comparison Operator
+    /// @param[in] i_right Reference to Target to compare.
+    /// @return bool. True if not equal.
+    /// @note Platforms need to define this so that the physical
+    /// targets are determined to be equivilent rather than just the handles
+    ///
+    template<TargetType K, typename V>
+    bool Target<K, V>::operator!=(const Target& i_right) const
+    { return i_right.iv_handle != iv_handle; }
+
+    ///
+    /// @brief Get this target's immediate parent
+    /// @tparam T The type of the parent
+    /// @return Target<T> a target representing the parent
+    ///
+    template<TargetType K, typename V>
+    template<TargetType T>
+    inline Target<T> Target<K, V>::getParent(void) const
+    {
+        // For testing
+        return Target<T>(iv_handle);
+    }
+
+    ///
+    /// @brief Get this target's children
+    /// @tparam T The type of the parent
+    /// @param[in] i_state The desired TargetState of the children
+    /// @return std::vector<Target<T> > a vector of present/functional
+    /// children
+    /// @warning The children of EX's (cores) are expected to be returned
+    /// in order. That is, core 0 is std::vector[0].
+    ///
+    template<TargetType K, typename V>
+    template< TargetType T>
+    inline std::vector<Target<T> >
+    Target<K, V>::getChildren(const TargetState i_state) const
+    {
+        // To keep the compiler quiet about unused variables
+        static_cast<void>(i_state);
+        // For testing
+        return {Target<T>(), Target<T>()};
+    }
+
+    ///
+    /// @brief Get the target at the other end of a bus - dimm included
+    /// @tparam T The type of the parent
+    /// @param[in] i_state The desired TargetState of the children
+    /// @return Target<T> a target representing the thing on the other end
+    /// @note Can be easily changed to a vector if needed
+    ///
+    template<TargetType K, typename V>
+    template<TargetType T>
+    inline Target<T>
+    Target<K, V>::getOtherEnd(const TargetState i_state) const
+    {
+        // Implementation note: cast to a composite of
+        // bus types and the compiler will check if this is
+        // a good function at compile time
+        return Target<T>();
+    }
+
+
+    ///
+    /// @brief Return the string interpretation of this target
+    /// @tparam T The type of the target
+    /// @param[in] i_target Target<T>
+    /// @param[in] i_buffer buffer to write in to
+    /// @param[in] i_bsize size of the buffer
+    /// @return void
+    /// @post The contents of the buffer is replaced with the string
+    /// representation of the target
+    ///
+    template< TargetType T >
+    inline void toString(const Target<T>& i_target, char* i_buffer, size_t i_bsize)
+    {
+        snprintf(i_buffer, i_bsize, "Target 0x%lx/0x%x", i_target.get(), T);
+    }
+
+    ///
+    /// @brief Return the string interpretation of this target
+    /// @tparam T The type of the target
+    /// @tparam B The type of the buffer
+    /// @param[in] A pointer to the Target<T>
+    /// @param[in] i_buffer buffer to write in to
+    /// @param[in] i_bsize size of the buffer
+    /// @return void
+    /// @post The contents of the buffer is replaced with the string
+    /// representation of the target
+    ///
+    template< TargetType T >
+    inline void toString(const Target<T>* i_target, char* i_buffer, size_t i_bsize)
+    {
+        snprintf(i_buffer, i_bsize, "Target 0x%lx/0x%x", i_target->get(), T);
+    }
+
+    ///
+    /// @brief Get an enumerated target of a specific type
+    /// @tparam T The type of the target
+    /// @param[in] Ordinal representing the ordinal number of
+    /// the desired target
+    /// @return Target<T> the target requested
+    ///
+    template<TargetType T>
+    inline Target<T> getTarget(uint64_t Ordinal)
+    {
+        // For testing
+        return Target<T>(Ordinal);
+    }
+}
+
+#endif
diff --git a/src/ppe/importtemp/fapi2/include/target_states.H b/src/ppe/importtemp/fapi2/include/target_states.H
new file mode 100644
index 0000000..de2bafc
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/target_states.H
@@ -0,0 +1,45 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/target_states.H $            */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file target_states.H
+ * @brief common state for fapi2 targets
+ */
+
+#ifndef __FAPI2_TARGET_STATES__
+#define __FAPI2_TARGET_STATES__
+
+namespace fapi2
+{
+    ///
+    /// @brief Enumeration of target state values (bitmask values)
+    ///
+    enum TargetState
+    {
+        TARGET_STATE_PRESENT    = 0x00000001,
+        TARGET_STATE_FUNCTIONAL = 0x00000002,
+    };
+}
+
+#endif
diff --git a/src/ppe/importtemp/fapi2/include/target_types.H b/src/ppe/importtemp/fapi2/include/target_types.H
new file mode 100644
index 0000000..25e97d3
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/target_types.H
@@ -0,0 +1,106 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/target_types.H $             */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file target_types.H
+ * @brief definitions for fapi2 target types
+ */
+
+#ifndef __FAPI2_TARGET_TYPES__
+#define __FAPI2_TARGET_TYPES__
+
+/// FAPI namespace
+namespace fapi2
+{
+    ///
+    /// @enum fapi::TargetType
+    /// @brief Types, kinds, of targets
+    /// @note TYPE_NONE is used to represent empty/NULL targets in lists
+    /// or tables. TYPE_ALL is used to pass targets to methods which
+    /// can act generally on any type of target
+    ///
+
+    /// Target Kind
+    enum TargetType
+    {
+        TARGET_TYPE_NONE          = 0x00000000, ///< No type
+        TARGET_TYPE_SYSTEM        = 0x00000001, ///< System type
+        TARGET_TYPE_DIMM          = 0x00000002, ///< DIMM type
+        TARGET_TYPE_PROC_CHIP     = 0x00000004, ///< Processor type
+        TARGET_TYPE_MEMBUF_CHIP   = 0x00000008, ///< Membuf type
+        TARGET_TYPE_EX            = 0x00000010, ///< EX - 2x Core, L2, L3 - can be deconfigured
+        TARGET_TYPE_MBA           = 0x00000020, ///< MBA type
+        TARGET_TYPE_MCS           = 0x00000040, ///< MCS type
+        TARGET_TYPE_XBUS          = 0x00000080, ///< XBUS type
+        TARGET_TYPE_ABUS          = 0x00000100, ///< ABUS type
+        TARGET_TYPE_L4            = 0x00000200, ///< L4 type
+        TARGET_TYPE_CORE          = 0x00000400, ///< Core - 4x threads(?) - can be deconfigured
+        TARGET_TYPE_EQ            = 0x00000800, ///< EQ - 4x core, 2x L2, 2x L3 - can be deconfigured
+        TARGET_TYPE_MCA           = 0x00001000, ///< MCA type
+        TARGET_TYPE_MCBIST        = 0x00002000, ///< MCBIST type
+        TARGET_TYPE_MI            = 0x00004000, ///< MI Memory Interface (Cumulus)
+        TARGET_TYPE_CAPP          = 0x00008000, ///< CAPP target
+        TARGET_TYPE_DMI           = 0x00010000, ///< DMI type
+        TARGET_TYPE_OBUS          = 0x00020000, ///< OBUS type
+        TARGET_TYPE_NV            = 0x00040000, ///< NV bus type
+        TARGET_TYPE_SBE           = 0x00080000, ///< SBE type
+        TARGET_TYPE_PPE           = 0x00100000, ///< PPE type
+        TARGET_TYPE_PERV          = 0x00200000, ///< Pervasive type
+        TARGET_TYPE_PEC           = 0x00400000, ///< PEC type
+        TARGET_TYPE_PHB           = 0x00800000, ///< PHB type
+
+        TARGET_TYPE_ALL           = 0xFFFFFFFF, ///< Any/All types
+
+        // Mappings to target types found in the error xml files
+        TARGET_TYPE_EX_CHIPLET    = TARGET_TYPE_EX,
+        TARGET_TYPE_MBA_CHIPLET   = TARGET_TYPE_MBA,
+        TARGET_TYPE_MCS_CHIPLET   = TARGET_TYPE_MCS,
+        TARGET_TYPE_XBUS_ENDPOINT = TARGET_TYPE_XBUS,
+        TARGET_TYPE_ABUS_ENDPOINT = TARGET_TYPE_ABUS,
+    };
+
+    /// @cond
+    constexpr TargetType operator|(TargetType x, TargetType y)
+    {
+        return static_cast<TargetType>(static_cast<int>(x) |
+                                       static_cast<int>(y));
+    }
+
+    template<uint64_t V>
+    class bitCount {
+    public:
+        // Don't use enums, too hard to compare
+        static const uint8_t count = bitCount<(V >> 1)>::count + (V & 1);
+    };
+
+    template<>
+    class bitCount<0> {
+    public:
+        static const uint8_t count = 0;
+    };
+    /// @endcond
+
+}
+
+#endif
diff --git a/src/ppe/importtemp/fapi2/include/utils.H b/src/ppe/importtemp/fapi2/include/utils.H
new file mode 100644
index 0000000..223569b
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/utils.H
@@ -0,0 +1,97 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/utils.H $                    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file utils.H
+ * @brief Defines common fapi2 utilities
+ */
+
+#ifndef FAPI2_UTILS_H_
+#define FAPI2_UTILS_H_
+
+#include <stdint.h>
+#include <return_code.H>
+#include <error_info_defs.H>
+
+namespace fapi2
+{
+///
+/// @brief Log an error.
+///
+/// @param[in,out] io_rc Reference to ReturnCode (Any references to data and error
+///            target are removed and rc value is set to success after
+///            function ends.)
+/// @param[in] i_sev Fapi error log severity defaulted to unrecoverable
+/// @param[in] i_unitTestError - flag to log error which does not cause a unit
+///                              test to fail.
+///
+/// @note This function is called from the ffdc collection classes and no longer
+/// needs to be called directly.
+/// @note Implemented by platform code
+///
+void logError(
+    fapi2::ReturnCode & io_rc,
+    fapi2::errlSeverity_t i_sev = fapi2::FAPI2_ERRL_SEV_UNRECOVERABLE,
+    bool i_unitTestError = false );
+
+///
+/// @brief Delay this thread. Hostboot will use the nanoseconds parameter
+/// and make a syscall to nanosleep. While in the syscall, the hostboot
+/// kernel will continue to consume CPU cycles as it looks for a runnable
+/// task.  When the delay time expires, the task becomes runnable and will soon
+/// return from the syscall.  Callers of delay() in the hostboot environment
+/// will likely have to know the mHz clock speed they are running on and
+/// compute a non-zero value for i_nanoSeconds.
+///
+/// On the FSP, it was sometimes acceptable to just provide zero for the
+/// sleep delay time, causing the task to yield its time slice. By the
+/// time the calling task could run again, it was pretty certain enough
+/// host cycles had past.  This is probably not acceptable in
+/// the hostboot environment. Callers should calculate and provide a
+/// sleep value in nanoseconds relative to host clock speed.
+///
+/// On FSP when VBU is the target, then the i_simCycles parameter will be
+/// used instead.  The FSP needs to use the simdispatcher client/server
+/// API and issue a command to the awan to advance the simulation the
+/// specified number of cycles.
+///
+/// @param[in] i_nanoSeconds    nanoseconds to sleep
+/// @param[in] i_simCycles      count of Awan cycles to advance
+/// @param[in] i_fixed          Determination, for DFT, if this time is
+///                             fixed or not. Defaults to non-fixed
+///
+/// @return ReturnCode. Zero on success, else platform specified error.
+///
+ReturnCode delay(uint64_t i_nanoSeconds, uint64_t i_simCycles,
+                 bool i_fixed = false);
+
+///
+/// @brief Assert a condition, and halt
+///
+/// @param[in] a boolean representing the assertion
+///
+void Assert(bool i_expression);
+};
+
+#endif // FAPI2_UTILS_H_
diff --git a/src/ppe/importtemp/fapi2/include/variable_buffer.H b/src/ppe/importtemp/fapi2/include/variable_buffer.H
new file mode 100644
index 0000000..579058a
--- /dev/null
+++ b/src/ppe/importtemp/fapi2/include/variable_buffer.H
@@ -0,0 +1,1198 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/importtemp/fapi2/include/variable_buffer.H $          */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file variable_buffer.H
+ * @brief definitions for fapi2 variable length buffers
+ */
+
+#ifndef __FAPI2_VARIABLE_BUFFER__
+#define __FAPI2_VARIABLE_BUFFER__
+
+#include <buffer_parameters.H>
+#include <buffer_traits.H>
+#include <return_code_defs.H>
+#include <cassert>
+
+namespace fapi2
+{
+    /// @brief Get a 32 bit mask quickly
+    // This is one of the main reasons we static_assert in the ctor's
+    // to ensure the unit_type is 32 bits.
+    inline uint32_t fast_mask32(int32_t i_pos, int32_t i_len)
+    {
+        // generates an arbitrary 32-bit mask using two operations, not too shabby
+
+        static const uint32_t l_mask32[] = {
+            0x00000000,
+            0x80000000, 0xC0000000, 0xE0000000, 0xF0000000,
+            0xF8000000, 0xFC000000, 0xFE000000, 0xFF000000,
+            0xFF800000, 0xFFC00000, 0xFFE00000, 0xFFF00000,
+            0xFFF80000, 0xFFFC0000, 0xFFFE0000, 0xFFFF0000,
+            0xFFFF8000, 0xFFFFC000, 0xFFFFE000, 0xFFFFF000,
+            0xFFFFF800, 0xFFFFFC00, 0xFFFFFE00, 0xFFFFFF00,
+            0xFFFFFF80, 0xFFFFFFC0, 0xFFFFFFE0, 0xFFFFFFF0,
+            0xFFFFFFF8, 0xFFFFFFFC, 0xFFFFFFFE, 0xFFFFFFFF,
+        };
+        return l_mask32[i_len] >> i_pos;
+    }
+
+    //
+    // General set a series of bits in the buffer.
+    //
+
+    ///
+    /// @cond
+    /// @brief Internal bit inserting method.
+    /// @tparam unit_type The type of a unit of the arrays
+    /// @tparam bits_type The type of the bit counting values
+    /// @param[in] i_source The incoming data
+    /// @param[in] i_source_length The length in bits of the incoming data
+    /// @param[in] i_target The outgoing data
+    /// @param[in] i_target_length The length in bits of the outgoing data
+    /// @param[in] i_source_start_bit The starting bit location in the
+    ///            incoming data
+    /// @param[in] i_target_start_bit The starting bit position in this
+    /// @param[in] i_length The length, in bits, the user wants copied.
+    ///
+    template<typename unit_type, typename bits_type, typename output_type>
+    inline fapi2::ReturnCodes _insert(const unit_type* i_source,
+                                     bits_type i_source_length,
+                                     output_type* i_target,
+                                     bits_type i_target_length,
+                                     bits_type i_source_start_bit,
+                                     bits_type i_target_start_bit,
+                                     bits_type i_length)
+    {
+        const bits_type bits_per_input_unit = parameterTraits<unit_type>::bit_length();
+        const bits_type bits_per_output_unit =parameterTraits<output_type>::bit_length();
+
+        // targetStart is defaulted to the sizeof(target) - (sizeof(source) - i_source_start_bit)
+        // which makes this act like insert from right
+        if (i_target_start_bit == static_cast<bits_type>(~0))
+        {
+            i_target_start_bit = (i_target_length - (i_source_length - i_source_start_bit));
+        }
+
+        // len defaults to (sizeof(OT) * 8) - i_source_start_bit
+        if (i_length == static_cast<bits_type>(~0))
+        {
+            i_length = i_source_length - i_source_start_bit;
+        }
+
+        // Check for overflow
+        if ((i_length + i_target_start_bit > i_target_length) ||
+            (i_length + i_source_start_bit > i_source_length))
+        {
+            return fapi2::FAPI2_RC_OVERFLOW;
+        }
+
+        do
+        {
+            const bits_type src_idx = i_source_start_bit / bits_per_input_unit;
+            const bits_type trg_idx = i_target_start_bit / bits_per_output_unit;
+
+            // "slop" = unaligned bits
+            const bits_type src_slop = i_source_start_bit % bits_per_input_unit;
+            const bits_type trg_slop = i_target_start_bit % bits_per_output_unit;
+
+            // "cnt" = largest number of bits to be moved each pass
+            bits_type cnt = std::min(i_length, bits_per_input_unit);
+            cnt = std::min(cnt, bits_per_input_unit - src_slop);
+            cnt = std::min(cnt, bits_per_output_unit - trg_slop);
+
+            // generate the source mask only once
+            bits_type mask = fast_mask32(src_slop, cnt);
+
+            // read the source bits only once
+            bits_type src_bits = i_source[src_idx] & mask;
+
+            // "shift" = amount of shifting needed for target alignment
+            int32_t shift = trg_slop - src_slop;
+
+            if (shift < 0)
+            {
+                src_bits <<= -shift;
+                mask <<= -shift;
+            }
+            else
+            {
+                src_bits >>= shift;
+                mask >>= shift;
+            }
+
+            // clear source '0' bits in the target
+            i_target[trg_idx] &= ~mask;
+
+            // set source '1' bits in the target
+            i_target[trg_idx] |= src_bits;
+
+            i_source_start_bit += cnt;
+            i_target_start_bit += cnt;
+
+            i_length -= cnt;
+
+        } while (0 < i_length);
+
+        return fapi2::FAPI2_RC_SUCCESS;
+    }
+    /// @endcond
+
+    /// @brief Class representing a FAPI variable_buffer.
+    /// @remark Variable buffers are buffers which can be variable in length
+    /// (and "odd sized.") These best represent the FAPI 1.X ecmdDataBuffer,
+    /// however they are implemented using the same template techniques
+    /// as the new fapi::buffer.
+    /// @note Variable buffers are not (presently) declared as std::bitset
+    /// as bitsets' size is fixed at runtime. It is not clear if this is
+    /// acceptable for variable_buffers at this time.
+    /// @note Variable buffers are implemented as a std::vecor of uint32_t
+    /// as this keeps simple compatibility with ecmdDataBuffers. Cronus (at
+    //least) need to interwork the two.
+    class variable_buffer
+    {
+
+    public:
+
+        /// Shortcut typedef to get to our traits class
+        typedef typename bufferTraits<bits_container>::bits_type bits_type;
+        /// Shortcut typedef to get to our traits class
+        typedef typename bufferTraits<bits_container>::unit_type unit_type;
+
+        ///
+        /// @brief Variable buffer constructor
+        /// @param[in] i_value number of *bits* (sizeof(uint_type) * 8)
+        /// needed.
+        inline variable_buffer(bits_type i_value = 0):
+            iv_data(_vector_size(i_value)),
+            iv_perceived_bit_length(i_value)
+            {
+                static_assert(std::is_same<unit_type, uint32_t>::value,
+                              "code currently needs unit_type to be a unit32_t");
+            }
+
+        ///
+        /// @brief Variable buffer list constructor
+        /// @param[in] i_value an initializer list to initialize the container.
+        /// @warning Input data is assumed to be right-aligned and must be 32 bits
+        ///
+        inline variable_buffer(const std::initializer_list<unit_type>& i_value):
+            iv_data(i_value),
+            iv_perceived_bit_length(i_value.size() * sizeof(unit_type) * 8)
+            {
+                static_assert(std::is_same<unit_type, uint32_t>::value,
+                              "code currently needs unit_type to be a unit32_t");
+            }
+
+        ///
+        /// @brief Variable buffer copy constructor
+        /// @param[in] i_buffer the buffer to copy from
+        ///
+        inline variable_buffer(const variable_buffer& i_buffer)
+            {
+                iv_perceived_bit_length = i_buffer.iv_perceived_bit_length;
+                iv_data = i_buffer.iv_data;
+            }
+
+        ///
+        /// @brief Variable buffer move constructor
+        /// @param[in] i_buffer the buffer to move
+        ///
+        inline variable_buffer(variable_buffer&& i_buffer)
+            {
+                iv_perceived_bit_length = i_buffer.iv_perceived_bit_length;
+                i_buffer.iv_perceived_bit_length = 0;
+                iv_data = std::move(i_buffer.iv_data);
+            }
+
+        ///
+        /// @brief Variable buffer array constructor
+        /// @param[in] i_value a uint32_t array to initialize the container.
+        /// @param[in] i_length the length of the array in 32-bit words
+        /// @param[in] i_bit_length the length of the resulting buffer in bits.
+        /// @warning This assumes the underlying container of a variable_buffer
+        /// is a uint32_t - which it is.
+        /// @note To use this constructor given an ecmdDataBuffer, you would
+        /// ecmd.memCopyOut( buffer, ... );
+        /// variable_buffer( buffer, ecmd.getCapacity(), ecmd.getBitLength());
+        ///
+        inline variable_buffer(const uint32_t* i_value, const uint32_t i_length,
+                               const uint32_t i_bit_length):
+            iv_perceived_bit_length(i_bit_length)
+            {
+                static_assert(std::is_same<unit_type, uint32_t>::value,
+                              "code currently needs unit_type to be a unit32_t");
+
+                // Copy the array in to our vector.
+                iv_data.insert(iv_data.end(), i_value, &i_value[i_length]);
+            }
+
+
+#if !defined(DOXYGEN) && defined(FAPI2_DEBUG)
+        /// @brief Print the contents of the buffer to stdout
+        inline void print(void) const
+        { bufferTraits<bits_container>::print(iv_data); }
+#endif
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return The contents of the buffer
+        ///
+        inline operator bits_container() const { return iv_data; }
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return The contents of the buffer
+        ///
+        inline operator bits_container&() { return iv_data; }
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return The contents of the buffer
+        ///
+        inline bits_container& operator()(void) { return iv_data; }
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return Reference to the contents of the buffer
+        ///
+        inline const bits_container& operator()(void) const { return iv_data; }
+
+        /// @name Buffer Manipulation Functions
+        ///@{
+
+        ///
+        /// @brief Set an OT of data in buffer
+        /// @param[in] i_value sizeof(OT) bits of data
+        /// @param[in] i_offset Start OT (start word, for example) in buffer
+        ///            - defaults to 0 (will by default write the left most element)
+        /// @return FAPI2_RC_SUCCESS on success, FAPI2_RC_OVERFLOW otherwise
+        ///
+        template< typename OT>
+        inline fapi2::ReturnCodes set(OT i_value, const bits_type i_offset = 0)
+        {
+            // Compile time check to make sure OT is integral
+            static_assert( std::is_integral<OT>::value,
+                           "Input must be an integral type" );
+
+            const uint32_t length = bufferTraits<bits_container>:: template size<OT>(iv_data);
+            static const bits_type bits_in_value = parameterTraits<OT>::bit_length();
+            const bits_type bit_length = bufferTraits<bits_container>::bit_length(iv_data);
+
+            if ((i_offset + bits_in_value) >= iv_perceived_bit_length)
+            {
+                return FAPI2_RC_OVERFLOW;
+            }
+
+            // Create mask if part of this byte is not in the valid part of the buffer,
+            // Shift it left by the amount of unused bits,
+            // Clear the unused bits (doesn't use fastmask as OT isn't always 32 bits)
+            if (((i_offset + 1) == length) && (bit_length % bits_in_value)) {
+                i_value &= parameterTraits<OT>::mask() << ((bits_in_value * length) - bit_length);
+            }
+
+            parameterTraits<OT>::template write_element<unit_type>(bufferTraits<bits_container>::get_address(iv_data), i_value, i_offset);
+            return FAPI2_RC_SUCCESS;
+        }
+
+        ///
+        /// @brief Get an OT of data from buffer
+        /// @tparam OT the type of the data to get
+        /// @param[in] i_offset Start OT (start word, for example) in buffer
+        ///            - defaults to 0 (will by default write the left most element)
+        /// @return OT
+        /// @note uint8_t b = get<uint8_t>(N) <- gets the N'th left byte from the buffer
+        ///
+        template< typename OT>
+        inline OT get(const bits_type i_offset = 0);
+
+        /// @name Bit/Word Manipulation Functions
+        ///@{
+
+        ///
+        /// @brief Return the length of the buffer in bits
+        /// @return Length in bits
+        ///
+        inline uint32_t getBitLength(void) const
+            { return iv_perceived_bit_length; }
+
+        ///
+        /// @brief Return the length of the buffer in OT units
+        /// @return Length in OT units rounded up
+        /// @tparam OT the type to get the length of. For example, if one
+        /// wanted the length in double words, OT would be uint64_t
+        /// (getLength<uint64_t>().) Similarly, to get the length in words,
+        /// getLength<uin32_t>().
+        ///
+        template< typename OT >
+        inline uint32_t getLength(void) const
+        {
+            static const uint32_t bits_in_ot = sizeof(OT) * 8;
+            return (getBitLength() + (bits_in_ot - 1)) / bits_in_ot;
+        }
+
+        ///
+        /// @brief  Set a bit in buffer
+        /// @tparam SB Start bit in buffer to clear.
+        /// @tparam L Number of consecutive bits from start bit to
+        /// clear
+        /// @return FAPI2_RC_SUCCESS on success
+        inline fapi2::ReturnCodes setBit( const bits_type SB, bits_type L = 1)
+        {
+
+            ReturnCodes rc;
+           // make sure we stay within our container
+            assert((L > 0) && ((SB + L) <= this->iv_perceived_bit_length) );
+
+            uint32_t mask   = 0;
+
+            // last bit to check
+            bits_type EB    = SB + L -1;
+
+            // index where first bit to check is located
+            bits_type start_index = SB/bits_per_unit;
+
+            // index where last bit is located
+            bits_type end_index   = EB/bits_per_unit;
+
+            if( start_index == end_index )
+            {
+                // normalize our SB to be within a unit
+                bits_type TempSB = SB - (start_index*bits_per_unit);
+
+                // grab a mask from SB for L number of bits.
+                mask = fast_mask32(TempSB, L);
+
+                iv_data[start_index] |= mask;
+
+                rc = FAPI2_RC_SUCCESS;
+
+            }
+            else
+            {
+                // the bits span more than one internal unit, need to break
+                // it up to process it.
+
+                // make TempSB point to the start of the next unit, adjust the
+                // length and go again, process the bits in the previous index
+                // when we get back.
+                bits_type TempSB = (start_index + 1) * bits_per_unit;
+                bits_type TempL  = EB - TempSB + 1;
+
+                rc = this->setBit( TempSB, TempL );
+
+                if(rc == FAPI2_RC_SUCCESS)
+                {
+                    // now check the bits in the previous index up to the next index.
+                    // normalize our SB to be within a unit
+                    TempSB = SB - (start_index*bits_per_unit);
+
+                    // get a mask for the new SB location to the end of this unit.
+                    mask = fast_mask32(TempSB, L-TempL);
+
+                    // merge theses bits with the others.
+                    iv_data[start_index] |= mask;
+                }
+
+            }
+
+            return rc;
+        }
+
+        ///
+        /// @brief Clear a bit in buffer
+        /// @tparam SB Start bit in buffer to clear.
+        /// @tparam L Number of consecutive bits from start bit to
+        /// clear
+        /// @return FAPI2_RC_SUCCESS on success
+        /// @note Asserting that all the parameters are known at
+        /// compile time so this can be templated only. If that is not
+        /// the case we can add a function parameter version.
+        ///
+        inline fapi2::ReturnCodes clearBit(bits_type SB, bits_type L = 0)
+        {
+            ReturnCodes rc = invert().setBit(SB,L);
+
+            invert();
+
+            return rc;
+        }
+
+        ///
+        /// @brief Invert bit
+        /// @tparam SB Start bit in buffer to invert.
+        /// @tparam L Number of consecutive bits from start bit to
+        /// invert, defaults to 1
+        /// @return FAPI2_RC_SUCCESS on success
+        /// @note Asserting that all the parameters are known at
+        /// compile time so this can be templated only. If that is not
+        /// the case we can add a function parameter version.
+        ///
+        template< bits_type SB, bits_type L = 1 >
+        inline fapi2::ReturnCodes flipBit(void);
+
+        ///
+        /// @brief Get the value of a bit in the buffer
+        /// @tparam B Bit in buffer to get.
+        /// @return true/1 if bit is on, false/0 if bit is off
+        /// @note Asserting that all the parameters are known at
+        /// compile time so this can be templated only. If that is not
+        /// the case we can add a function parameter version.
+        ///
+        template< bits_type B >
+        inline bool getBit(void) const
+        {
+            const bits_type index = B / bits_per_unit;
+            const unit_type mask = unit_type(1) <<
+                ((bits_per_unit - 1) - (B - (index * bits_per_unit)));
+            return iv_data[index] & mask;
+        }
+
+        ///
+        /// @brief Test if multiple bits are set
+        /// @param SB Start bit in buffer to test.
+        /// @param L Number of consecutive bits from start bit to
+        /// test, defaults to 1
+        /// @return true if all bits in range are set - false if any
+        /// bit is clear
+        /// @note Example: fapi2::buffer<uint64_t>().isBitSet(4,3);
+        inline bool isBitSet( bits_type SB, bits_type L = 1 ) const
+        {
+            // make sure we stay within our container
+            assert( ((L > 0) && ((SB + L) <= this->iv_perceived_bit_length)) );
+
+            bool is_set     = false;
+            uint32_t mask   = 0;
+
+            // last bit to check
+            bits_type EB    = SB + L - 1;
+
+            // index where first bit to check is located
+            bits_type start_index = SB/bits_per_unit;
+
+            // index where last bit is located
+            bits_type end_index   = EB/bits_per_unit;
+
+            if( start_index == end_index )
+            {
+                // normalize our SB to be within a unit
+                bits_type TempSB = SB - (start_index*bits_per_unit);
+
+                // grab a mask from SB for L number of bits.
+                mask = fast_mask32(TempSB, L);
+
+                is_set =
+                    (( iv_data[start_index] & mask) == mask ) ? true : false;
+
+            }
+            else
+            {
+                // the bits span more than one internal unit, need to break
+                // it up to process it.
+
+                // make TempSB point to the start of the next unit, adjust the
+                // length and go again, process the bits in the previous index
+                // when we get back.
+                bits_type TempSB = (start_index + 1) * bits_per_unit;
+                bits_type TempL  = EB - TempSB + 1;
+
+                is_set = this->isBitSet( TempSB, TempL );
+
+                // now check the bits in the previous index up to the next index.
+                // normalize our SB to be within a unit
+                TempSB = SB - (start_index*bits_per_unit);
+
+                // get a mask for the new SB location to the end of this unit.
+                mask = fast_mask32(TempSB, L-TempL);
+
+                // test these bits against the others..
+                is_set &=
+                    (( iv_data[start_index] & mask) == mask ) ? true : false;
+
+            }
+
+            return is_set;
+        }
+
+        ///
+        /// @brief Test if multiple bits are clear
+        /// @param SB Start bit in buffer to test.
+        /// @param L Number of consecutive bits from start bit to
+        /// test, defaults to 1
+        /// @return true if bit is clear - false if bit is set
+        ///
+        inline bool isBitClear( bits_type SB, bits_type L =1 ) const
+        {
+            variable_buffer l_buf = *this;
+
+            return l_buf.invert().isBitSet(SB,L);
+        }
+
+        ///
+        /// @brief Count number of bits set in a range
+        /// @tparam SB Start bit in buffer to test.
+        /// @tparam L Number of consecutive bits from start bit to
+        /// test, defaults to 1
+        /// @note Asserting that all the parameters are known at
+        /// compile time so this can be templated only. If that is not
+        /// the case we can add a function parameter version.
+        /// @return Number of bits set in range
+        ///
+        template< bits_type SB, bits_type L = 1 >
+        inline bits_type getNumBitsSet(void) const;
+
+        ///
+        /// @brief Set and entire buffer to X's
+        /// @tparam X {0,1} depending if you want to clear (0)
+        /// or fill (1) a buffer
+        /// @return variable_buffer&, Useful for method chaining
+        ///
+        template< uint8_t X >
+        inline variable_buffer& flush(void)
+            {
+                static_assert( (X == 1) || (X == 0), "bad argument to flush" );
+                (0 == X) ? bufferTraits<bits_container>::clear(iv_data) : bufferTraits<bits_container>::set(iv_data);
+                return *this;
+            }
+
+        ///
+        /// @brief Invert entire buffer
+        /// @return variable_buffer&, Useful for method chaining
+        ///
+        inline variable_buffer& invert(void)
+            { bufferTraits<bits_container>::invert(iv_data); return *this; }
+
+        ///@}
+
+        /// @name Buffer Manipulation Functions
+        ///@{
+
+        ///
+        /// @brief Shift a buffer left a defined number of bits, from a start bit
+        /// @param[in] number of bits to shift
+        /// @param[in] offset from 0 to start shift, defaults to ~0 (see operator<<())
+        /// @note an offset of ~(0) implies "end of the buffer"
+        /// @warning there is no shiftLeftandResize - resizing the buffer is left to
+        /// the caller to alight the operations with integral buffers.
+        /// @return FAPI2_RC_SUCCESS on success
+        ///
+        inline ReturnCodes shiftLeft(bits_type i_shiftNum, bits_type i_offset = ~0);
+
+        ///
+        /// @brief Shift a buffer right a defined number of bits, from a start bit
+        /// @param[in] number of bits to shift
+        /// @param[in] offset from 0 to start shift, defaults to 0 (see operator>>())
+        /// @warning there is no shiftRightandResize - resizing the buffer is left to
+        /// the caller to alight the operations with integral buffers.
+        /// @return FAPI2_RC_SUCCESS on success
+        ///
+        inline ReturnCodes shiftRight(bits_type i_shiftNum, bits_type i_offset = 0);
+
+        ///
+        /// @brief move operator=()
+        /// @note To use: new_buffer = std::move(old_buffer). old_buffer will be
+        /// destroyed and no copy will be made (moved)
+        ///
+        inline variable_buffer& operator=(variable_buffer&& other)
+            {
+                iv_perceived_bit_length = other.iv_perceived_bit_length;
+                other.iv_perceived_bit_length = 0;
+                iv_data = std::move(other.iv_data);
+                return *this;
+            }
+
+        ///
+        /// @brief operator=()
+        ///
+        inline variable_buffer& operator=(const variable_buffer& other)
+            {
+                iv_perceived_bit_length = other.iv_perceived_bit_length;
+                iv_data = other.iv_data;
+                return *this;
+            }
+
+        ///
+        /// @brief operator>>()
+        ///
+        inline variable_buffer& operator>>(bits_type i_shiftnum)
+            {
+                // This is just a right shift from the begining of the buffer
+                // Why void? Well, there's no place to return the return
+                // code and in reality the only problem which can arise
+                // is the offset is out of bounds. But since we're hard-wiring it
+                // to 0, it can't be out of bounds. So there's no real problem
+                // which can arise here.
+                static_cast<void>(shiftRight(i_shiftnum));
+                return *this;
+            }
+
+        ///
+        /// @brief operator<<()
+        ///
+        inline variable_buffer& operator<<(bits_type i_shiftnum)
+            {
+                // This is just a left shift from the end of the buffer
+                // Why void? Well, there's no place to return the return
+                // code and in reality the only problem which can arise
+                // is the offset is out of bounds. But since we're hard-wiring it
+                // to 0, it can't be out of bounds. So there's no real problem
+                // which can arise here.
+                static_cast<void>(shiftLeft(i_shiftnum));
+                return *this;
+            }
+
+
+        ///
+        /// @brief operator+()
+        /// @param[in] A variable_buffer to append to this
+        ///
+        inline variable_buffer& operator+(const variable_buffer& rhs)
+            {
+                iv_perceived_bit_length += rhs.iv_perceived_bit_length;
+                iv_data.insert(iv_data.end(), rhs.iv_data.begin(), rhs.iv_data.end());
+                return *this;
+            }
+
+        ///
+        /// @brief operator+()
+        /// @param[in] A number of bits to add to this buffer
+        ///
+        inline variable_buffer& operator+(const bits_type& rhs)
+            {
+                if (rhs != 0)
+                {
+                    iv_perceived_bit_length += rhs;
+                    iv_data.resize(_vector_size(iv_perceived_bit_length));
+                }
+                return *this;
+            }
+
+        ///
+        /// @brief resize()
+        /// @param[in] Desired resulting size of the buffer, in bits
+        ///
+        inline variable_buffer& resize(const bits_type& rhs)
+            {
+                return operator+(rhs - iv_perceived_bit_length);
+            }
+
+        ///
+        /// @brief operator+=()
+        ///
+#ifdef DOXYGEN
+        inline variable_buffer<T>& operator+=(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator|=()
+        ///
+#ifdef DOXYGEN
+        inline variable_buffer<T>& operator|=(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator&=()
+        ///
+#ifdef DOXYGEN
+        inline variable_buffer<T>& operator&=(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator|()
+        ///
+#ifdef DOXYGEN
+        inline variable_buffer<T>& operator|(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator&()
+        ///
+#ifdef DOXYGEN
+        inline variable_buffer<T>& operator&(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator^=()
+        ///
+#ifdef DOXYGEN
+        inline variable_buffer<T>& operator^=(const T& rhs);
+#endif
+
+        ///
+        /// @brief Get a pointer to the buffer bits
+        /// @return Pointer to the buffer itself
+        ///
+        inline unit_type* pointer(void) { return &(iv_data[0]); }
+
+        ///
+        /// @brief operator!=()
+        ///
+        inline bool operator!=(const variable_buffer& rhs) const
+            { return ! operator==(rhs); }
+
+        ///
+        /// @brief operator==()
+        /// @return true if and only if lhs == rhs
+        ///
+        inline bool operator==(const variable_buffer& rhs) const
+        {
+            if (&iv_data == &rhs.iv_data)
+            {
+                return true;
+            }
+
+            return (iv_data == rhs.iv_data) &&
+                (iv_perceived_bit_length == rhs.iv_perceived_bit_length);
+        }
+
+        ///
+        /// @brief Copy part of an element into the DataBuffer
+        /// @param[in] i_data OT value to copy into DataBuffer
+        /// @param[in] i_targetStart The position in this where the copy starts
+        /// @param[in] i_len How many bits to copy
+        /// @param[in] i_sourceStart The start positon in i_data, defaults to 0
+        /// @return FAPI2_RC_SUCCESS on success, FAPi2_RC_OVERFLOW otherwise
+        ///
+        template<typename OT>
+        inline fapi2::ReturnCodes insert(const OT& i_data,
+                                        bits_type i_targetStart = 0,
+                                        bits_type i_len = ~0,
+                                        bits_type i_sourceStart = 0)
+            {
+                // _insert likes 32-bit sources. So lets make our source 32 bits.
+                uint32_t l_source = static_cast<uint32_t>(i_data);
+                bits_type l_sourceStart = i_sourceStart +
+                    parameterTraits<uint32_t>::bit_length() -
+                        parameterTraits<OT>::bit_length();
+
+                return _insert(&l_source, parameterTraits<uint32_t>::bit_length(),
+                               &(iv_data[0]), getBitLength(),
+                               l_sourceStart, i_targetStart, i_len);
+            }
+
+        ///
+        /// @brief Copy in a right aligned (decimal) element
+        /// @param[in] i_data the incoming data
+        ///    - data is taken right aligned
+        /// @param[in] i_targetStart The starting bit position in this
+        ///            - Defaults to 0
+        /// @param[in] i_len The length, in bits, the user wants copied.
+        ///            - Defaults to all of the bits in the source which fit
+        /// @return FAPI2_RC_SUCCESS on success, FAPI2_RC_OVERFLOW otherwise
+        ///
+        template<typename OT>
+        inline fapi2::ReturnCodes insertFromRight(const OT& i_data,
+                                                 bits_type i_targetStart = 0,
+                                                 bits_type i_len = ~0)
+            {
+                return _insertFromRight(i_data, parameterTraits<OT>::bit_length(),
+                                        i_targetStart, i_len);
+            }
+
+        ///
+        /// @brief Copy data from this buffer into an OT
+        /// @tparam OT the type of the outgoing data
+        /// @param[out] o_out OT to copy into - data is placed left aligned
+        /// @param[in] i_start Start bit to copy from - defaults to 0
+        /// @param[in] i_len Length of bits to copy - defaults to filling o_out
+        /// @return FAPI2_RC_SUCCESS on success
+        /// @warning fapi2::extract() does not extend the argument buffer. The caller
+        /// should adjust the size proir to calling extract() (resize()). This is to
+        /// keep the semantics the same with integral buffers, which can't be resized.
+        ///
+        // Generic extract. Extract is an insert with the arguments reversed.
+        template< typename OT >
+        inline fapi2::ReturnCodes extract(OT& o_out,
+                                         bits_type i_start = 0,
+                                         bits_type i_len = ~0) const
+            {
+                // If thy didn't pass an i_len, assume they want all the data
+                // which will fit.
+                if (i_len == static_cast<bits_type>(~0))
+                {
+                    i_len = std::min(getBitLength(),
+                                     parameterTraits<OT>::bit_length());
+                }
+
+                if (i_len > getBitLength())
+                {
+                    return FAPI2_RC_INVALID_PARAMETER;
+                }
+
+                // _insert likes 32-bit targets. So lets make our target 32 bits.
+                uint32_t l_data = static_cast<uint32_t>(o_out);
+
+                ReturnCodes rc;
+                if ((rc = _insert((container_unit*)&iv_data[0], getBitLength(),
+                                  &l_data,
+                                  parameterTraits<uint32_t>::bit_length(),
+                                  i_start, 0U, i_len)) != FAPI2_RC_SUCCESS)
+                {
+                    return rc;
+                }
+
+                // Shift back to the original bit width.
+                o_out = l_data >> (parameterTraits<uint32_t>::bit_length() -
+                                   parameterTraits<OT>::bit_length());
+                return FAPI2_RC_SUCCESS;
+            }
+
+        ///
+        /// @brief Copy data from this buffer into an OT and right justify
+        /// @tparam OT the type of the outgoing data
+        /// @param[out] o_out OT to copy into - data is placed right aligned
+        /// @param[in] i_start Start bit to copy from - defaults to 0
+        /// @param[in] i_len Length of bits to copy - defaults to filling o_out
+        /// @return FAPI2_RC_SUCCESS on success
+        ///
+        // Extract is an insert with the arguments reversed.
+        template< typename OT >
+        inline fapi2::ReturnCodes extractToRight(OT& o_out,
+                                                bits_type i_start = 0,
+                                                bits_type i_len = ~0) const
+            {
+                // If thy didn't pass an i_len, assume they want all the data
+                // which will fit.
+                if ((i_len == static_cast<bits_type>(~0)) ||
+                    (i_len > parameterTraits<OT>::bit_length()))
+                {
+                    i_len = std::min(getBitLength(),
+                                     parameterTraits<OT>::bit_length());
+                }
+
+                // _insert likes 32-bit targets. So lets make our target 32 bits.
+                uint32_t l_data = static_cast<uint32_t>(o_out);
+
+                ReturnCodes rc;
+                if ((rc = _insert(
+                         reinterpret_cast<const container_unit*>(&iv_data[0]),
+                         getBitLength(),
+                         &l_data,
+                         parameterTraits<uint32_t>::bit_length(),
+                         i_start,
+                         parameterTraits<uint32_t>::bit_length() -
+                         i_len, i_len)) != FAPI2_RC_SUCCESS)
+                {
+                    return rc;
+                }
+
+                o_out = l_data;
+                return FAPI2_RC_SUCCESS;
+            }
+
+        ///@}
+
+    private:
+        // Just shorthand ...
+        static const bits_type bits_per_unit = bufferTraits<bits_container>::bits_per_unit();
+
+        ///@cond
+        ///
+        /// @brief Return the size of the internal vector given a desired bit size
+        /// @param[in] The size in bits
+        /// @return The size in units.
+        ///
+        inline bits_type _vector_size(const bits_type& bits_size)
+            {
+                // If we fit in one unit, we allocate one unit.
+                if (bits_size < parameterTraits<unit_type>::bit_length())
+                {
+                    return 1;
+                }
+
+                // Otherwise, the number of units is calculates - add one if
+                // we cross the unit boundary.
+                else
+                {
+                    bits_type my_size = bits_type(bits_size / 8 / sizeof(unit_type));
+                    my_size += (bits_size % parameterTraits<unit_type>::bit_length() == 0) ? 0 : 1;
+                    return my_size;
+                }
+            }
+        ///@endcond
+
+        /// The contents of the buffer
+        bits_container iv_data;
+
+        // The number of bits the user asked for. The actual size of the
+        // container might be larger.
+        bits_type iv_perceived_bit_length;
+
+        ///
+        /// @brief Internal insertFromRight
+        /// @param[in] i_data, the incoming data
+        /// @param[in] i_data_length The length in bits of the incoming data
+        /// @param[in] i_target_start_bit The starting bit position in this
+        /// @param[in] i_length The length, in bits, the user wants copied.
+        ///
+        template<typename OT>
+        inline fapi2::ReturnCodes _insertFromRight(const OT& i_data,
+                                                  bits_type i_data_length,
+                                                  bits_type i_targetStart,
+                                                  bits_type i_len)
+        {
+            // If they didn't pass in a length, assume they want all the i_data
+            // which will fit.
+            if( i_len == static_cast<bits_type>(~0) )
+            {
+                // The longest the length can be is the length of the data
+                // This is the miniumum of the length of the data or the
+                // number of available bits
+                i_len = std::min(i_data_length, getBitLength() - i_targetStart);
+            }
+
+            // Source start is the length, counted from the right
+            return insert(i_data, i_targetStart, i_len, i_data_length - i_len);
+        }
+
+    };
+
+    // If the source is 64-bits, treat that as 2x32
+    template<>
+    inline fapi2::ReturnCodes variable_buffer::insert(const uint64_t& i_source,
+                                    bits_type i_targetStart,
+                                    bits_type i_len,
+                                    bits_type i_sourceStart)
+    {
+        // _insert wants 32 bit chunks, so lets turn our uint64_t into a
+        // uint32_t array (of 64 bits in length). Looks like a 64 bit
+        // variable_buffer.
+        uint32_t l_source[2] =
+            {static_cast<uint32_t>((i_source & 0xFFFFFFFF00000000) >> 32),
+             static_cast<uint32_t>((i_source & 0x00000000FFFFFFFF))};
+
+        return _insert(l_source, parameterTraits<uint64_t>::bit_length(),
+                       &(iv_data[0]), getBitLength(),
+                       i_sourceStart, i_targetStart, i_len);
+    }
+
+    // Insert another variable_bufer
+    template<>
+    inline fapi2::ReturnCodes variable_buffer::insert(
+        const variable_buffer& i_data,
+        bits_type i_targetStart,
+        bits_type i_len,
+        bits_type i_sourceStart)
+    {
+        return _insert(reinterpret_cast<const unit_type*>(&(i_data()[0])),
+                       i_data.getBitLength(),
+                       &(iv_data[0]), getBitLength(),
+                       i_sourceStart, i_targetStart, i_len);
+    }
+
+    // variable_buffer insert from right
+    template<>
+    inline fapi2::ReturnCodes variable_buffer::insertFromRight(
+        const variable_buffer& i_data,
+        bits_type i_targetStart,
+        bits_type i_len)
+    {
+        const bits_type bit_length_of_source = i_data.getBitLength();
+        return _insertFromRight(i_data, bit_length_of_source,
+                                i_targetStart, i_len);
+    }
+
+    template<>
+    inline fapi2::ReturnCodes variable_buffer::extract(
+        uint64_t& i_data,
+        bits_type i_start,
+        bits_type i_len) const
+    {
+        // If thy didn't pass an i_len, assume they want all the data
+        // which will fit.
+        if ((i_len == static_cast<bits_type>(~0)) ||
+            (i_len > parameterTraits<uint64_t>::bit_length()))
+        {
+            i_len = std::min(getBitLength(),
+                             parameterTraits<uint64_t>::bit_length());
+        }
+
+        // _insert wants 32 bit chunks, so lets turn our uint64_t into a
+        // uint32_t array (of 64 bits in length). Looks like a 64 bit
+        // variable_buffer.
+        uint32_t l_data[2] =
+            {static_cast<uint32_t>((i_data & 0xFFFFFFFF00000000) >> 32),
+             static_cast<uint32_t>((i_data & 0x00000000FFFFFFFF))};
+
+        ReturnCodes rc;
+        if ((rc = _insert((container_unit*)&iv_data[0], getBitLength(),
+                          l_data, parameterTraits<uint64_t>::bit_length(),
+                          i_start, 0U, i_len)) != FAPI2_RC_SUCCESS)
+        {
+            return rc;
+        }
+
+        i_data = static_cast<uint64_t>(l_data[0]) << 32;
+        i_data |= l_data[1];
+
+        return FAPI2_RC_SUCCESS;
+    }
+
+    // Extract in to another variable_bufer
+    template<>
+    inline fapi2::ReturnCodes variable_buffer::extract(
+        variable_buffer& i_data,
+        bits_type i_start,
+        bits_type i_len) const
+    {
+        // If thy didn't pass an i_len, assume they want all the data
+        // which will fit.
+        if (i_len == static_cast<bits_type>(~0))
+        {
+            i_len = i_data.getBitLength();
+        }
+
+        return _insert(reinterpret_cast<const container_unit*>(
+                           &iv_data[0]),
+                       getBitLength(),
+                       &(i_data()[0]), i_data.getBitLength(),
+                       i_start, 0U, i_len);
+    }
+
+    template<>
+    inline fapi2::ReturnCodes variable_buffer::extractToRight(
+        uint64_t& i_data,
+        bits_type i_start,
+        bits_type i_len) const
+    {
+        // If thy didn't pass an i_len, assume they want all the data
+        // which will fit.
+        if ((i_len == static_cast<bits_type>(~0)) ||
+            (i_len > parameterTraits<uint64_t>::bit_length()))
+        {
+            i_len = std::min(getBitLength(),
+                             parameterTraits<uint64_t>::bit_length());
+        }
+
+        // _insert wants 32 bit chunks, so lets turn our uint64_t into a
+        // uint32_t array (of 64 bits in length).
+        uint32_t l_data[2] =
+            {static_cast<uint32_t>((i_data & 0xFFFFFFFF00000000) >> 32),
+             static_cast<uint32_t>((i_data & 0x00000000FFFFFFFF))};
+
+        ReturnCodes rc;
+        if ((rc = _insert(
+                 reinterpret_cast<const container_unit*>(&iv_data[0]),
+                 getBitLength(),
+                 l_data, parameterTraits<uint64_t>::bit_length(),
+                 i_start,
+                 parameterTraits<uint64_t>::bit_length() - i_len, i_len))
+            != FAPI2_RC_SUCCESS)
+        {
+            return rc;
+        }
+
+        i_data = static_cast<uint64_t>(l_data[0]) << 32;
+        i_data |= l_data[1];
+
+        return FAPI2_RC_SUCCESS;
+    }
+
+    inline fapi2::ReturnCodes variable_buffer::shiftLeft(
+        bits_type i_shiftNum,
+        bits_type i_offset)
+    {
+        if (i_offset == 0)
+        {
+            return FAPI2_RC_SUCCESS;
+        }
+
+        if (i_offset == static_cast<bits_type>(~0))
+        {
+            i_offset = getBitLength();
+        }
+
+        else if (i_offset > getBitLength())
+        {
+            return FAPI2_RC_INVALID_PARAMETER;
+        }
+
+        /* To shift the data, extact the piece being shifted and then re-insert it at the new location */
+        variable_buffer shiftData(i_offset);
+        ReturnCodes rc;
+
+        // Get the hunk of data
+        if ((rc = extract(shiftData, 0, i_offset)) != FAPI2_RC_SUCCESS)
+        {
+            return rc;
+        }
+
+        // Clear the hole that was opened
+        if ((rc = clearBit((i_offset - i_shiftNum), i_shiftNum)) != FAPI2_RC_SUCCESS)
+        {
+            return rc;
+        }
+
+        // Stick the data back in
+        rc = insert(shiftData, 0, (shiftData.getBitLength() - i_shiftNum), i_shiftNum);
+
+        return rc;
+    }
+
+    inline fapi2::ReturnCodes variable_buffer::shiftRight(
+        bits_type i_shiftNum,
+        bits_type i_offset)
+    {
+        if (i_offset == getBitLength())
+        {
+            return FAPI2_RC_SUCCESS;
+        }
+
+        if (i_offset > getBitLength())
+        {
+            return FAPI2_RC_INVALID_PARAMETER;
+        }
+
+        /* To shift the data, extact the piece being shifted and then re-insert it at the new location */
+        variable_buffer shiftData(getBitLength() - i_offset);
+        ReturnCodes rc;
+
+        // Get the hunk of data
+        if ((rc = extract(shiftData, i_offset, getBitLength() - i_offset)) != FAPI2_RC_SUCCESS)
+        {
+            return rc;
+        }
+
+        // Clear the hole that was opened
+        if ((rc = clearBit(i_offset, i_shiftNum)) != FAPI2_RC_SUCCESS)
+        {
+            return rc;
+        }
+
+        // Stick the data back in
+        rc = insert(shiftData, (i_offset + i_shiftNum), (shiftData.getBitLength() - i_shiftNum));
+
+        return rc;
+    }
+
+    template< typename OT>
+    inline OT variable_buffer::get(const bits_type i_offset)
+    {
+        // Get is just an extract.
+        OT l_tmp;
+        extract(l_tmp, parameterTraits<OT>::bit_length() * i_offset, parameterTraits<OT>::bit_length());
+        return l_tmp;
+    }
+}
+#endif
diff --git a/src/ppe/importtemp/xml/attribute_info/core_attributes.xml b/src/ppe/importtemp/xml/attribute_info/core_attributes.xml
new file mode 100644
index 0000000..fb56f35
--- /dev/null
+++ b/src/ppe/importtemp/xml/attribute_info/core_attributes.xml
@@ -0,0 +1,61 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/ppe/importtemp/xml/attribute_info/core_attributes.xml $   -->
+<!--                                                                        -->
+<!-- OpenPOWER OnChipController Project                                     -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- $Id: proc_pll_ring_attributes.xml,v 1.17 2014/11/13 20:14:02 szhong Exp $ -->
+<!-- proc_pll_ring_attributes.xml -->
+<attributes>
+  <attribute>
+    <id>ATTR_CORE_REPR_RING</id>
+    <targetType>TARGET_TYPE_CORE</targetType>
+    <description>
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <writeable/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_CORE_TIME_RING</id>
+    <targetType>TARGET_TYPE_CORE</targetType>
+    <description>
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <writeable/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_CORE_GPTR_RING</id>
+    <targetType>TARGET_TYPE_CORE</targetType>
+    <description>
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <writeable/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+</attributes>
diff --git a/src/ppe/importtemp/xml/attribute_info/eq_attributes.xml b/src/ppe/importtemp/xml/attribute_info/eq_attributes.xml
new file mode 100644
index 0000000..5e1a19e
--- /dev/null
+++ b/src/ppe/importtemp/xml/attribute_info/eq_attributes.xml
@@ -0,0 +1,38 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/ppe/importtemp/xml/attribute_info/eq_attributes.xml $     -->
+<!--                                                                        -->
+<!-- OpenPOWER OnChipController Project                                     -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- $Id: proc_pll_ring_attributes.xml,v 1.17 2014/11/13 20:14:02 szhong Exp $ -->
+<!-- proc_pll_ring_attributes.xml -->
+<attributes>
+  <attribute>
+    <id>ATTR_DPLL_RING</id>
+    <targetType>TARGET_TYPE_EQ</targetType>
+    <description>
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+</attributes>
diff --git a/src/ppe/importtemp/xml/attribute_info/ex_attributes.xml b/src/ppe/importtemp/xml/attribute_info/ex_attributes.xml
new file mode 100644
index 0000000..6ca2986
--- /dev/null
+++ b/src/ppe/importtemp/xml/attribute_info/ex_attributes.xml
@@ -0,0 +1,88 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/ppe/importtemp/xml/attribute_info/ex_attributes.xml $     -->
+<!--                                                                        -->
+<!-- OpenPOWER OnChipController Project                                     -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- $Id: proc_pll_ring_attributes.xml,v 1.17 2014/11/13 20:14:02 szhong Exp $ -->
+<!-- proc_pll_ring_attributes.xml -->
+<attributes>
+  <attribute>
+    <id>ATTR_L2_REPR_RING</id>
+    <targetType>TARGET_TYPE_EX</targetType>
+    <description>
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_L2_TIME_RING</id>
+    <targetType>TARGET_TYPE_EX</targetType>
+    <description>
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_L2_GPTR_RING</id>
+    <targetType>TARGET_TYPE_EX</targetType>
+    <description>
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_L3_REPR_RING</id>
+    <targetType>TARGET_TYPE_EX</targetType>
+    <description>
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_L3_TIME_RING</id>
+    <targetType>TARGET_TYPE_EX</targetType>
+    <description>
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_L3_GPTR_RING</id>
+    <targetType>TARGET_TYPE_EX</targetType>
+    <description>
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+</attributes>
diff --git a/src/ppe/importtemp/xml/attribute_info/perv_attributes.xml b/src/ppe/importtemp/xml/attribute_info/perv_attributes.xml
new file mode 100644
index 0000000..67769a5
--- /dev/null
+++ b/src/ppe/importtemp/xml/attribute_info/perv_attributes.xml
@@ -0,0 +1,726 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/ppe/importtemp/xml/attribute_info/perv_attributes.xml $   -->
+<!--                                                                        -->
+<!-- OpenPOWER OnChipController Project                                     -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- $Id: proc_pll_ring_attributes.xml,v 1.17 2014/11/13 20:14:02 szhong Exp $ -->
+<!-- proc_pll_ring_attributes.xml -->
+<attributes>
+  <attribute>
+    <id>ATTR_REPR_RING</id>
+    <targetType>TARGET_TYPE_PERV</targetType>
+    <description>
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_TIME_RING</id>
+    <targetType>TARGET_TYPE_PERV</targetType>
+    <description>
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_GPTR_RING</id>
+    <targetType>TARGET_TYPE_PERV</targetType>
+    <description>
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_PLL_RING</id>
+    <targetType>TARGET_TYPE_PERV</targetType>
+    <description>
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PG_FSI</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+        Partial good mask for FSI chiplet.  A 0 indicates a GOOD subregion.
+        bit 4:  fsi0
+        bit 5:  fsi1
+        bit 6:  fsia
+    </description>
+    <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_PRV</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Pervasive chiplet.  A 0 indicates a GOOD subregion.
+          bit 3:  vital
+          bit 4:  perv
+          bit 5:  net
+          bit 6:  pib
+          bit 7:  occ
+          bit 8:  anperv
+          bit 14: pllnest
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_N0</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Nest0 chiplet.  A 0 indicates a GOOD subregion.
+          bit 3:  vital
+          bit 4:  perv
+          bit 5:  nx
+          bit 6:  cxa0
+          bit 7:  pbioe0
+          bit 8:  pbioe1
+          bit 9:  pbioe2
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_N1</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Nest1 chiplet.  A 0 indicates a GOOD subregion.
+          bit 3:  vital
+          bit 4:  perv
+          bit 5:  mcd
+          bit 6:  va
+          bit 7:  pbioo0
+          bit 8:  pbioo1
+          bit 9:  mcs23
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_N2</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Nest2 chiplet.  A 0 indicates a GOOD subregion.
+          bit 3:  vital
+          bit 4:  perv
+          bit 5:  cxa1
+          bit 6:  pcis0
+          bit 7:  pcis1
+          bit 8:  pcis2
+          bit 9:  iopsi
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_N3</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Nest3 chiplet.  A 0 indicates a GOOD subregion.
+          bit 3:  vital
+          bit 4:  perv
+          bit 5:  pb
+          bit 6:  br
+          bit 7:  npu
+          bit 8:  mm
+          bit 9:  int
+          bit 10: mcs01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_XB</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for XBus chiplet.  A 0 indicates a GOOD subregion.
+          bit 3:  vital
+          bit 4:  perv
+          bit 5:  iox0
+          bit 6:  iox1
+          bit 7:  iox2
+          bit 8:  pbiox0
+          bit 9:  pbiox1
+          bit 10: pbiox2
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+   <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_MC01</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for MC01 chiplet.  A 0 indicates a GOOD subregion.
+          bit 3:  vital
+          bit 4:  perv
+          bit 5:  mca01
+          bit 6:  iom01
+          bit 7:  iom23
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_MC23</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for MC23 chiplet.  A 0 indicates a GOOD subregion.
+          bit 3:  vital
+          bit 4:  perv
+          bit 5:  mca23
+          bit 6:  iom45
+          bit 7:  iom67
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_OB0</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for OBus0 chiplet.  A 0 indicates a GOOD subregion.
+          bit 3:  vital
+          bit 4:  perv
+          bit 5:  pbiooa0
+          bit 6:  ioo0
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_OB1</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for OBus1 chiplet.  A 0 indicates a GOOD subregion.
+          bit 3:  vital
+          bit 4:  perv
+          bit 5:  pbiooa1
+          bit 6:  ioo1
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_OB2</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for OBus2 chiplet.  A 0 indicates a GOOD subregion.
+          bit 3:  vital
+          bit 4:  perv
+          bit 5:  pbiooa2
+          bit 6:  ioo2
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_OB3</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for OBus3 chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          pbiooa3	ioo3
+
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_PCI0</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for PCI0 chiplet.  A 0 indicates a GOOD subregion.
+          bit 3:  vital
+          bit 4:  perv
+          bit 5:  pci00
+          bit 6:  iopci0
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_PCI1</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for PCI1 chiplet.  A 0 indicates a GOOD subregion.
+          bit 3:  vital
+          bit 4:  perv
+          bit 5:  pci11
+          bit 6:  pci12
+          bit 7:  iopci1
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_PCI2</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for PCI2 chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5:  pci23
+          bit 6:  pci24
+          bit 7:  pci25
+          bit 8:  iopci2
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EQ0</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for EQ0 chiplet.  A 0 indicates a GOOD subregion.
+          bit 3:  vital
+          bit 4:  perv
+          bit 5:  eqpb
+          bit 6:  l30
+          bit 7:  l31
+          bit 8:  l20
+          bit 9:  l21
+          bit 10: an
+          bit 13: refr
+          bit 14: dpll
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EQ1</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for EQ1 chiplet.  A 0 indicates a GOOD subregion.
+          bit 3:  vital
+          bit 4:  perv
+          bit 5:  eqpb
+          bit 6:  l30
+          bit 7:  l31
+          bit 8:  l20
+          bit 9:  l21
+          bit 10: an
+          bit 13: refr
+          bit 14: dpll
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EQ2</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for EQ2 chiplet.  A 0 indicates a GOOD subregion.
+          bit 3:  vital
+          bit 4:  perv
+          bit 5:  eqpb
+          bit 6:  l30
+          bit 7:  l31
+          bit 8:  l20
+          bit 9:  l21
+          bit 10: an
+          bit 13: refr
+          bit 14: dpll
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EQ3</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for EQ3 chiplet.  A 0 indicates a GOOD subregion.
+         bit 3: vital
+          bit 4:  perv
+          bit 5:  eqpb
+          bit 6:  l30
+          bit 7:  l31
+          bit 8:  l20
+          bit 9:  l21
+          bit 10: an
+          bit 13: refr
+          bit 14: dpll
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EQ4</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for EQ4 chiplet.  A 0 indicates a GOOD subregion.
+          bit 3:  vital
+          bit 4:  perv
+          bit 5:  eqpb
+          bit 6:  l30
+          bit 7:  l31
+          bit 8:  l20
+          bit 9:  l21
+          bit 10: an
+          bit 13: refr
+          bit 14: dpll
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EQ5</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for EQ5 chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4:  perv
+          bit 5:  eqpb
+          bit 6:  l30
+          bit 7:  l31
+          bit 8:  l20
+          bit 9:  l21
+          bit 10: an
+          bit 13: refr
+          bit 14: dpll
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC00</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC00) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC01</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC01) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC02</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC02) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC03</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC03) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC04</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC04) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC05</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC05) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC06</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC06) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC07</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC07) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC08</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC08) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC09</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC09) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC10</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC10) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC11</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC11) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC12</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC12) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC13</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC13) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC14</id>
+       <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC14) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC15</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC15) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC16</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC16) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC17</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC17) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC18</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC18) chiplet.  A 0 indicates a GOOD subregion.
+         bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC19</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC19) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC20</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC20) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC21</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC21) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC22</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC22) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PG_EC23</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          Partial good mask for Core (EC23) chiplet.  A 0 indicates a GOOD subregion.
+          bit 3: vital
+          bit 4: perv
+          bit 5: c00
+          bit 6: c01
+      </description>
+      <valueType>uint16</valueType>
+  </attribute>
+  <!-- ********************************************************************* -->
+</attributes>
diff --git a/src/ppe/importtemp/xml/attribute_info/pervasive_attributes.xml b/src/ppe/importtemp/xml/attribute_info/pervasive_attributes.xml
new file mode 100644
index 0000000..12a7d07
--- /dev/null
+++ b/src/ppe/importtemp/xml/attribute_info/pervasive_attributes.xml
@@ -0,0 +1,149 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/ppe/importtemp/xml/attribute_info/pervasive_attributes.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER OnChipController Project                                     -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- This is an automatically generated file. -->
+<!-- File: pervasive_attributes.xml. -->
+<!-- XML file specifying attributes used by HW Procedures. Attributes are taken from model pervasive -->
+<!--pervasive_attributes.xml-->
+<attributes>
+<attribute>
+  <id>ATTR_BOOT_FREQ</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+</attribute>
+
+<attribute>
+  <id>ATTR_CHIP_REGIONS_TO_ENABLE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint32</valueType>
+</attribute>
+
+<attribute>
+  <id>ATTR_CHIP_UNIT_POS</id>
+  <targetType>TARGET_TYPE_PERV,TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+</attribute>
+
+<attribute>
+  <id>ATTR_ECID</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint64</valueType>
+</attribute>
+
+<attribute>
+  <id>ATTR_EC_GARD</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+</attribute>
+
+<attribute>
+  <id>ATTR_EQ_GARD</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+</attribute>
+
+<attribute>
+  <id>ATTR_I2C_BUS_DIV_NEST</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+</attribute>
+
+<attribute>
+  <id>ATTR_I2C_BUS_DIV_REF</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+</attribute>
+
+<attribute>
+  <id>ATTR_MC_SYNC_MODE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+</attribute>
+
+<attribute>
+  <id>ATTR_NEST_PLL_BUCKET</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+</attribute>
+
+<attribute>
+  <id>ATTR_PROC_PB_BNDY_DMIPLL_DATA</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+</attribute>
+
+<attribute>
+  <id>ATTR_PROC_PB_BNDY_DMIPLL_FOR_DCCAL_DATA</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+</attribute>
+
+<attribute>
+  <id>ATTR_PROC_PERV_BNDY_PLL_DATA</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+</attribute>
+
+<attribute>
+  <id>ATTR_SBE_SEEPROM_I2C_DEVICE_ADDRESS</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint32</valueType>
+</attribute>
+
+<attribute>
+  <id>ATTR_SBE_SEEPROM_I2C_PORT</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint32</valueType>
+</attribute>
+
+<attribute>
+  <id>ATTR_VCS_BOOT_VOLTAGE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+</attribute>
+
+<attribute>
+  <id>ATTR_VDD_BOOT_VOLTAGE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+</attribute>
+
+</attributes>
diff --git a/src/ppe/importtemp/xml/attribute_info/proc_attributes.xml b/src/ppe/importtemp/xml/attribute_info/proc_attributes.xml
new file mode 100644
index 0000000..08e18bd
--- /dev/null
+++ b/src/ppe/importtemp/xml/attribute_info/proc_attributes.xml
@@ -0,0 +1,175 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/ppe/importtemp/xml/attribute_info/proc_attributes.xml $   -->
+<!--                                                                        -->
+<!-- OpenPOWER OnChipController Project                                     -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- $Id: proc_pll_ring_attributes.xml,v 1.17 2014/11/13 20:14:02 szhong Exp $ -->
+<!-- proc_attributes.xml -->
+<attributes>
+  <attribute>
+    <id>ATTR_SCRATCH_UINT8_1</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_SCRATCH_UINT8_2</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_SCRATCH_UINT32_1</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_SCRATCH_UINT32_2</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_SCRATCH_UINT64_1</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+    </description>
+    <valueType>uint64</valueType>
+    <platInit/>
+    <writeable/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_SCRATCH_UINT64_2</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+    </description>
+    <valueType>uint64</valueType>
+     <enum>VAL_A = 0, VAL_B = 5, VAL_C = 0xffffffffffffffff</enum>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_SIGNED_TEST_8</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+    </description>
+    <valueType>int8</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_SIGNED_TEST_64</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+    </description>
+    <valueType>int64</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_SCRATCH_INT8_1</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+    </description>
+    <valueType>int8</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_SCRATCH_INT8_2</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+    </description>
+    <valueType>int8</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_SCRATCH_INT32_1</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+    </description>
+    <valueType>int32</valueType>
+    <platInit/>
+    <writeable/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_SCRATCH_INT32_2</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+    </description>
+    <valueType>int32</valueType>
+    <platInit/>
+    <writeable/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_SCRATCH_INT64_1</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+    </description>
+    <valueType>int64</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_SCRATCH_INT64_2</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+    </description>
+    <valueType>int64</valueType>
+    <enum>VAL_A = 0, VAL_B = 5, VAL_C = 0xffffffffffffffff</enum>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+</attributes>
diff --git a/src/ppe/importtemp/xml/error_info/.empty b/src/ppe/importtemp/xml/error_info/.empty
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/ppe/importtemp/xml/error_info/.empty
diff --git a/src/ppe/importtemp/xml/p9_ppe_attributes.xml b/src/ppe/importtemp/xml/p9_ppe_attributes.xml
new file mode 100644
index 0000000..fdcc774
--- /dev/null
+++ b/src/ppe/importtemp/xml/p9_ppe_attributes.xml
@@ -0,0 +1,302 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/ppe/importtemp/xml/p9_ppe_attributes.xml $                -->
+<!--                                                                        -->
+<!-- OpenPOWER OnChipController Project                                     -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- $Id: p9_ppe_entryibutes.xml,v 1.11 2013/11/07 21:51:13 rembold Exp $ -->
+<!-- p9_ppe_entryibutes.xml -->
+<entries>
+  <!-- ********************************************************************* -->
+  <entry>
+    <name>ATTR_SCRATCH_UINT8_1</name>
+    <value>0x8</value>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_UINT8_2</name>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_UINT32_1</name>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_UINT32_2</name>
+    <value>0xaffeaffe</value>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_UINT64_1</name>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_UINT64_2</name>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_INT8_1</name>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_INT8_2</name>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_INT32_1</name>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_INT32_2</name>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_INT64_1</name>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_INT64_2</name>
+  </entry>
+  <entry>
+    <name>ATTR_REPR_RING</name>
+    <value>0xcafe</value>
+    <value>0xaffe</value>
+  </entry>
+  <entry>
+    <name>ATTR_TIME_RING</name>
+  </entry>
+  <entry>
+    <name>ATTR_GPTR_RING</name>
+    <value>0xcafe</value>
+    <value>0xaffe</value>
+  </entry>
+  <entry>
+    <name>ATTR_PLL_RING</name>
+  </entry>
+  <entry>
+    <name>ATTR_CORE_REPR_RING</name>
+  </entry>
+  <entry>
+    <name>ATTR_CORE_TIME_RING</name>
+  </entry>
+  <entry>
+    <name>ATTR_CORE_GPTR_RING</name>
+  </entry>
+  <entry>
+    <name>ATTR_L2_REPR_RING</name>
+  </entry>
+  <entry>
+    <name>ATTR_L2_TIME_RING</name>
+    <value>0xcafe</value>
+    <value>0xaffe</value>
+  </entry>
+  <entry>
+    <name>ATTR_L2_GPTR_RING</name>
+  </entry>
+  <entry>
+    <name>ATTR_L3_REPR_RING</name>
+  </entry>
+  <entry>
+    <name>ATTR_L3_TIME_RING</name>
+    <value>0xcafe</value>
+    <value>0xaffe</value>
+  </entry>
+  <entry>
+    <name>ATTR_L3_GPTR_RING</name>
+  </entry>
+  <entry>
+    <name>ATTR_DPLL_RING</name>
+  </entry>
+  <entry>
+    <name>ATTR_PG_FSI</name>
+    <value>0xF1FF</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_PRV</name>
+      <value>0xF07D</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_N0</name>
+      <value>0xF03F</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_N1</name>
+      <value>0xF03F</value>
+  </entry> 
+  <entry>
+      <name>ATTR_PG_N2</name>
+      <value>0xF03F</value>
+  </entry>
+  <entry>
+      <name>ATTR_PG_N3</name>
+      <value>0xF01F</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_XB</name>
+      <value>0xF01D</value>
+  </entry>   
+  <entry>
+      <name>ATTR_PG_MC01</name>
+      <value>0xF0FD</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_MC23</name>
+      <value>0xF0FD</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_OB0</name>
+      <value>0xF1FD</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_OB1</name>
+      <value>0xF1FD</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_OB2</name>
+      <value>0xF1FD</value>
+  </entry> 
+  <entry>
+      <name>ATTR_PG_OB3</name>
+      <value>0xF1FD</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_PCI0</name>
+      <value>0xF1FD</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_PCI1</name>
+      <value>0xF0FD</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_PCI2</name>
+      <value>0xF07D</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EQ0</name>
+      <value>0xF019</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EQ1</name>
+      <value>0xF019</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EQ2</name>
+      <value>0xF019</value>
+  </entry>
+  <entry>
+      <name>ATTR_PG_EQ3</name>
+      <value>0xF019</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EQ4</name>
+      <value>0xF019</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EQ5</name>
+      <value>0xF019</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EC00</name>
+      <value>0xF1FF</value>
+  </entry> 
+  <entry>
+      <name>ATTR_PG_EC01</name>
+      <value>0xF1FF</value>
+  </entry> 
+  <entry>
+      <name>ATTR_PG_EC02</name>
+      <value>0xF1FF</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EC03</name>
+      <value>0xF1FF</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EC04</name>
+      <value>0xF1FF</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EC05</name>
+      <value>0xF1FF</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EC06</name>
+      <value>0xF1FF</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EC07</name>
+      <value>0xF1FF</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EC08</name>
+      <value>0xF1FF</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EC09</name>
+      <value>0xF1FF</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EC10</name>
+      <value>0xF1FF</value>
+  </entry>
+  
+  <entry>
+      <name>ATTR_PG_EC11</name>
+     <value>0xF1FF</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EC12</name>
+      <value>0xF1FF</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EC13</name>
+      <value>0xF1FF</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EC14</name>
+      <value>0xF1FF</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EC15</name>
+      <value>0xF1FF</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EC16</name>
+      <value>0xF1FF</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EC17</name>
+      <value>0xF1FF</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EC18</name>
+      <value>0xF1FF</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EC19</name>
+      <value>0xF1FF</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EC20</name>
+      <value>0xF1FF</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EC21</name>
+      <value>0xF1FF</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EC22</name>
+      <value>0xF1FF</value>
+  </entry>  
+  <entry>
+      <name>ATTR_PG_EC23</name>
+      <value>0xF1FF</value>
+  </entry>
+</entries>
diff --git a/src/ppe/pk/ppe42/ppe42_scom.c b/src/ppe/pk/ppe42/ppe42_scom.c
index 20da4df..220712c 100755
--- a/src/ppe/pk/ppe42/ppe42_scom.c
+++ b/src/ppe/pk/ppe42/ppe42_scom.c
@@ -48,11 +48,11 @@
 #include "ppe42_msr.h"
 
 
-uint32_t putscom_abs(const uint32_t i_address, uint64_t *i_data)
+uint32_t putscom_abs(const uint32_t i_address, uint64_t i_data)
 {
 
     // Perform the Store Virtual Double instruction
-    PPE_STVD(i_address, &i_data);
+    PPE_STVD(i_address, i_data);
 
     // Get the MSR[SIBRC] as the return code   
     uint32_t rc = mfmsr();
@@ -61,11 +61,11 @@ uint32_t putscom_abs(const uint32_t i_address, uint64_t *i_data)
     
 }
 
-uint32_t _putscom( uint32_t i_chiplet_id, uint32_t i_address, uint64_t *i_data)
+uint32_t _putscom( uint32_t i_chiplet_id, uint32_t i_address, uint64_t i_data)
 {
 
     // Perform the Store Virtual Double Index instruction
-    PPE_STVDX(i_chiplet_id, i_address, &i_data);
+    PPE_STVDX(i_chiplet_id, i_address, i_data);
 
     // Get the MSR[SIBRC] as the return code   
     uint32_t rc = mfmsr();
@@ -78,7 +78,7 @@ uint32_t getscom_abs( const uint32_t i_address, uint64_t *o_data)
 {
     
     // Perform the Load Virtual Double instruction
-    PPE_LVD(i_address, &o_data);
+    PPE_LVD(i_address, o_data);
 
     // Get the MSR[SIBRC] as the return code   
     uint32_t rc = mfmsr();
@@ -91,7 +91,7 @@ uint32_t _getscom( const uint32_t i_chiplet_id, const uint32_t i_address, uint64
 {
     
     // Perform the Load Virtual Double Index instruction
-    PPE_LVDX(i_chiplet_id, i_address, &o_data);
+    PPE_LVDX(i_chiplet_id, i_address, o_data);
 
     // Get the MSR[SIBRC] as the return code   
     uint32_t rc = mfmsr();
diff --git a/src/ppe/pk/ppe42/ppe42_scom.h b/src/ppe/pk/ppe42/ppe42_scom.h
index 42bc87a..7368594 100755
--- a/src/ppe/pk/ppe42/ppe42_scom.h
+++ b/src/ppe/pk/ppe42/ppe42_scom.h
@@ -59,9 +59,9 @@ extern "C" {
 asm volatile \
     ( \
     "lvd %[data], 0(%[address]) \n" \
-    :  [data]"=&r"(*_m_data) \
-    :  "[data]"(*_m_data), \
-       [address]"r"(_m_address) \
+    :  [data]"=&r"(_m_data) \
+    :  "[data]"(_m_data), \
+       [address]"b"(_m_address) \
     );
 
 
@@ -70,9 +70,9 @@ asm volatile \
 asm volatile \
     ( \
         "stvd %[data], 0(%[address]) \n" \
-        : [data]"=&r"(*_m_data) \
-        : "[data]"(*_m_data), \
-          [address]"r"(_m_address) \
+        : [data]"=&r"(_m_data) \
+        : "[data]"(_m_data), \
+          [address]"b"(_m_address) \
         : "memory" \
      );
 
@@ -83,7 +83,7 @@ asm volatile \
     "lvdx %[data], %[base], %[offset] \n" \
     :  [data]"=&r"(*_m_data) \
     :  "[data]"(*_m_data), \
-       [base]"r"(_m_base), \
+       [base]"b"(_m_base), \
        [offset]"r"(_m_offset) \
     );
 
@@ -93,9 +93,9 @@ asm volatile \
 asm volatile \
     ( \
         "stvdx %[data], %[base], %[offset] \n" \
-        : [data]"=&r"(*_m_data) \
-        : "[data]"(*_m_data), \
-          [base]"r"(_m_base), \
+        : [data]"=&r"(_m_data) \
+        : "[data]"(_m_data), \
+          [base]"b"(_m_base), \
           [offset]"r"(_m_offset) \
         : "memory" \
      );
@@ -114,7 +114,7 @@ asm volatile \
 ///                          to optimize the underlying hardware execution
 ///
 /// @retval     On PPE42 platform, unmasked errors will take machine check interrupts
-uint32_t putscom_abs(const uint32_t i_address, uint64_t *i_data);
+uint32_t putscom_abs(const uint32_t i_address, uint64_t i_data);
 
 /// @brief getscom with absolute address
 /// @param [in]  i_address   Fully formed SCOM address
@@ -131,7 +131,7 @@ uint32_t getscom_abs( const uint32_t i_address, uint64_t *o_data);
 ///                         to optimize the underlying hardware execution
 ///
 /// @retval     On PPE42 platform, unmasked errors will take machine check interrupts
-uint32_t _putscom( const uint32_t i_chiplet, const uint32_t i_address, uint64_t *i_data);
+uint32_t _putscom( const uint32_t i_chiplet, const uint32_t i_address, uint64_t i_data);
 
 
 /// @brief Implementation of PPE getscom functionality
@@ -142,7 +142,7 @@ uint32_t _putscom( const uint32_t i_chiplet, const uint32_t i_address, uint64_t
 /// @retval     On PPE42 platform, unmasked errors will take machine check interrupts
 uint32_t _getscom( uint32_t i_chiplet, uint32_t i_address, uint64_t *o_data);
 
-extern inline uint32_t putscom(const uint32_t i_chiplet, const uint32_t i_address, uint64_t *i_data)
+extern inline uint32_t putscom(const uint32_t i_chiplet, const uint32_t i_address, uint64_t i_data)
 {
     return _putscom(i_chiplet, i_address, i_data);
 }
diff --git a/src/ppe/pk/std/std_irq_config.h b/src/ppe/pk/std/std_irq_config.h
index 5044b42..7d70d42 100644
--- a/src/ppe/pk/std/std_irq_config.h
+++ b/src/ppe/pk/std/std_irq_config.h
@@ -35,6 +35,8 @@
 /// configuration for a standard PPE.
 ///
 
+#include "pk_app_cfg.h"
+
 /// This constant is used to define the size of the table of interrupt handler
 /// structures as well as a limit for error checking. 
 #define EXTERNAL_IRQS 64
diff --git a/src/ppe/sbe/image/Makefile b/src/ppe/sbe/image/Makefile
index a784342..388286e 100644
--- a/src/ppe/sbe/image/Makefile
+++ b/src/ppe/sbe/image/Makefile
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+
 #remove this once we have a real compiler
 export P2P_ENABLE = 1
 
@@ -78,6 +79,7 @@ HWPLIB_MAKE_DIR := $(HWPLIB_SRCDIR)
 LIB_DIRS += -L$(OBJDIR)/lib
 HWPLIB := $(OBJDIR)/libcommon.a
 LLIBS += -lcommon
+include $(HWPLIB_SRCDIR)/libcommonerrors.mk
 
 # Common Cache HWP Exit library
 CACHE_MAKE_DIR := $(CACHE_SRCDIR)
@@ -97,109 +99,206 @@ PERV_MAKE_DIR := $(PERV_SRCDIR)
 LIB_DIRS += -L$(OBJDIR)/perv
 PERVLIB := $(OBJDIR)/perv/libperv.a
 LLIBS += -lperv
+include $(PERV_SRCDIR)/perverrors.mk
+
+# Common Nest libraries
+NEST_MAKE_DIR := $(NEST_SRCDIR)
+LIB_DIRS += -L$(OBJDIR)/nest
+NESTLIB := $(OBJDIR)/nest/libnest.a
+LLIBS += -lnest
+include $(NEST_SRCDIR)/nesterrors.mk
+
+SBE_TOOLS := $(TOOLS_IMAGE_DIR)/sbe_xip_tool $(TOOLS_IMAGE_DIR)/sbe_default_tool
 
-LINK_OBJS = $(OBJS) $(PKLIB) $(SBEFWLIB) $(FAPI2LIB) $(CACHELIB) $(CORELIB) $(HWPLIB) $(P2PLIB) $(PERVLIB)
+LINK_OBJS = $(OBJS) $(SBEFWLIB) $(PKLIB) $(FAPI2LIB) $(CACHELIB) $(CORELIB) $(HWPLIB) $(P2PLIB) $(PERVLIB) $(NESTLIB)
 
 # Define the objects
 OBJS := $(addprefix $(OBJDIR)/, $(TOP_OBJECTS))
 LINK_OBJS += $(OBJS) $(GCCLIBS)
-#LINK_OBJS += $(OBJS) $(PKLIB) $(CPPLIB) $(PPELIB)
-LINK_SCRIPT = $(addprefix $(OBJDIR)/, linkscript)
 
+LINK_SCRIPT_SEEPROM = $(addprefix $(OBJDIR)/, linkscriptseeprom)
+LINK_SCRIPT_SBE = $(addprefix $(OBJDIR)/, linkscriptsbe)
+LINK_SCRIPT_LOADER = $(addprefix $(OBJDIR)/, linkscriptloader)
 
 
 #default target is to make a binary application image
 #This removes all unecessary headers from the ELF executable
-$(OBJDIR)/$(IMAGE_NAME).bin $(OBJDIR)/$(IMAGE_NAME).dis: $(OBJDIR)/$(IMAGE_NAME).out
-	$(OBJCOPY) -O binary  $< $(OBJDIR)/$(IMAGE_NAME).bin --pad-to 0x`/usr/bin/nm $(OBJDIR)/$(IMAGE_NAME).out | grep "A _sbe_base_end" | cut -d " " -f 1`
-	$(OBJDUMP) -S $< > $(OBJDIR)/$(IMAGE_NAME).dis
+$(OBJDIR)/$(IMAGE_SEEPROM_NAME).bin $(OBJDIR)/$(IMAGE_SEEPROM_NAME).dis: $(OBJDIR)/$(IMAGE_SEEPROM_NAME).out
+	$(OBJCOPY) -O binary  $< $(OBJDIR)/$(IMAGE_SEEPROM_NAME).bin --pad-to 0x`/usr/bin/nm $(OBJDIR)/$(IMAGE_SEEPROM_NAME).out | grep "A _seeprom_end" | cut -d " " -f 1`
+	$(OBJDUMP) -S $< > $(OBJDIR)/$(IMAGE_SEEPROM_NAME).dis
 
 #create a linked ELF executable
-$(OBJDIR)/$(IMAGE_NAME).out: $(LINK_OBJS) $(LINK_SCRIPT)
-	$(LD) -e __system_reset  -T$(LINK_SCRIPT) -Map $(OBJDIR)/$(IMAGE_NAME).map -Bstatic -o $(OBJDIR)/$(IMAGE_NAME).out $(LIB_DIRS) $(OBJS)  --start-group  $(LLIBS) --end-group  
-#	$(LD) -e __system_reset  -T$(LINK_SCRIPT) -Map $(OBJDIR)/$(IMAGE_NAME).map -Bstatic -o $(OBJDIR)/$(IMAGE_NAME).out $(LIB_DIRS) $(OBJS) -lpk -lp2p #-lcommon
-#	$(LD) -e __system_reset  -T$(LINK_SCRIPT) -Map $(OBJDIR)/$(IMAGE_NAME).map -Bstatic -o $(OBJDIR)/$(IMAGE_NAME).out $(LIB_DIRS) $(OBJS) $(LLIBS)
+$(OBJDIR)/$(IMAGE_SEEPROM_NAME).out: $(LINK_OBJS) $(LINK_SCRIPT_SEEPROM)
+	$(LD) -e __system_reset  -T$(LINK_SCRIPT_SEEPROM) -Map $(OBJDIR)/$(IMAGE_SEEPROM_NAME).map -Bstatic -o $(OBJDIR)/$(IMAGE_SEEPROM_NAME).out $(LIB_DIRS) $(OBJS)  --start-group  $(LLIBS) --end-group
+
+#pass the link command file through the C preprocessor to evaluate macros and remove comments
+$(LINK_SCRIPT_SEEPROM): linkseeprom.cmd
+	$(CPP) -E -x c++ -P $(DEFS) linkseeprom.cmd -o $(LINK_SCRIPT_SEEPROM)
+
+#default target is to make a binary pibmem image
+#This removes all unecessary headers from the ELF executable
+$(OBJDIR)/$(IMAGE_SBE_NAME).bin $(OBJDIR)/$(IMAGE_SBE_NAME).dis: $(OBJDIR)/$(IMAGE_SBE_NAME).out
+	$(OBJCOPY) -O binary  $< $(OBJDIR)/$(IMAGE_SBE_NAME).bin --pad-to 0x`/usr/bin/nm $(OBJDIR)/$(IMAGE_SBE_NAME).out | grep "A _sbe_end" | cut -d " " -f 1`
+	$(OBJDUMP) -S $< > $(OBJDIR)/$(IMAGE_SBE_NAME).dis
+
+#create a linked ELF executable
+$(OBJDIR)/$(IMAGE_SBE_NAME).out: $(OBJDIR)/base_sbe_fixed.o $(LINK_OBJS) $(LINK_SCRIPT_SBE)
+	$(LD) -e __system_reset  -T$(LINK_SCRIPT_SBE) -Map $(OBJDIR)/$(IMAGE_SBE_NAME).map -Bstatic -o $(OBJDIR)/$(IMAGE_SBE_NAME).out $(LIB_DIRS) $(OBJDIR)/base_sbe_fixed.o  --start-group $(LLIBS) --end-group
+
+#pass the link command file through the C preprocessor to evaluate macros and remove comments
+$(LINK_SCRIPT_SBE): linksbe.cmd
+	$(CPP) -E -x c++ -P $(DEFS) linksbe.cmd -o $(LINK_SCRIPT_SBE)
 
 
+
+
+$(OBJDIR)/$(IMAGE_LOADER_NAME).bin $(OBJDIR)/$(IMAGE_LOADER_NAME).dis: $(OBJDIR)/$(IMAGE_LOADER_NAME).out
+	$(OBJCOPY) -O binary  $< $(OBJDIR)/$(IMAGE_LOADER_NAME).bin --pad-to 0x`/usr/bin/nm $(OBJDIR)/$(IMAGE_LOADER_NAME).out | grep "A _loader_end" | cut -d " " -f 1`
+	$(OBJDUMP) -S $< > $(OBJDIR)/$(IMAGE_LOADER_NAME).dis
+
+#create a linked ELF executable
+$(OBJDIR)/$(IMAGE_LOADER_NAME).out: $(OBJDIR)/base_loader.o $(LINK_OBJS) $(LINK_SCRIPT_LOADER)
+	$(LD) -e base_loader -T$(LINK_SCRIPT_LOADER) -Map $(OBJDIR)/$(IMAGE_LOADER_NAME).map -Bstatic -o $(OBJDIR)/$(IMAGE_LOADER_NAME).out $(LIB_DIRS) $(OBJDIR)/base_loader.o  --start-group  $(SBEFWLIB) $(LLIBS) --end-group
+
 #pass the link command file through the C preprocessor to evaluate macros and remove comments
-$(LINK_SCRIPT): link.cmd
-	$(CPP) -E -x c++ -P $(DEFS) link.cmd -o $(LINK_SCRIPT)
+$(LINK_SCRIPT_LOADER): linkloader.cmd
+	$(CPP) -E -x c++ -P $(DEFS) linkloader.cmd -o $(LINK_SCRIPT_LOADER)
+
+
+
+
+all: $(OBJDIR)/$(IMAGE_SEEPROM_NAME).bin $(OBJDIR)/$(IMAGE_SBE_NAME).bin $(OBJDIR)/$(IMAGE_LOADER_NAME).bin $(SBE_TOOLS) normalize defaultset $(OBJDIR)/fixed.bin appendbase appendloader
+
+generic: $(OBJDIR)/$(IMAGE_SEEPROM_NAME).bin $(SBE_TOOLS) normalize defaultset $(OBJDIR)/fixed.bin
 
 #Create an obj directory if needed
-$(LINK_OBJS) $(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
+$(LINK_OBJS) $(OBJS) $(OBJS:.o=.d) $(OBJDIR)/base_sbe_fixed.o $(OBJDIR)/base_sbe_fixed.d: | $(OBJDIR)
+
+ATTRFILES += $(IMPORT_XML_DIR)/attribute_info/perv_attributes.xml
+ATTRFILES += $(IMPORT_XML_DIR)/attribute_info/proc_attributes.xml
+ATTRFILES += $(IMPORT_XML_DIR)/attribute_info/ex_attributes.xml
+ATTRFILES += $(IMPORT_XML_DIR)/attribute_info/eq_attributes.xml
+ATTRFILES += $(IMPORT_XML_DIR)/attribute_info/core_attributes.xml
 
 $(OBJDIR):
-	$(BASE_FAPI2_DIR)/tools/ppeParseProcSbeFixed.pl . $(TOOLS_ATTR_DIR)/p9_ppe_attributes1.xml $(ATTRFILES)
-	$(BASE_FAPI2_DIR)/tools/ppeParseAttributeInfo.pl $(PPE_FAPI2_DIR)/include $(TOOLS_ATTR_DIR)/p9_ppe_attributes1.xml $(ATTRFILES)
-	$(BASE_FAPI2_DIR)/tools/ppeCreateAttrGetSetMacros.pl -path $(BASE_FAPI2_DIR)/tools -inc $(PPE_FAPI2_DIR)/include -src $(PPE_FAPI2_DIR)/src
-	$(BASE_FAPI2_DIR)/tools/ppeCreateIfAttrService.pl $(PPE_FAPI2_DIR)/include $(TOOLS_ATTR_DIR)/p9_ppe_attributes1.xml $(ATTRFILES)
+	$(TOOLS_ATTR_DIR)/ppeParseProcSbeFixed.pl . $(IMPORT_XML_DIR)/p9_ppe_attributes.xml $(ATTRFILES)
+	$(TOOLS_ATTR_DIR)/ppeParseAttributeInfo.pl $(PPE_FAPI2_DIR)/include $(IMPORT_XML_DIR)/p9_ppe_attributes.xml $(ATTRFILES)
+	$(TOOLS_ATTR_DIR)/ppeCreateAttrGetSetMacros.pl -path $(TOOLS_ATTR_DIR)/src -inc $(PPE_FAPI2_DIR)/include -src $(PPE_FAPI2_DIR)/src
+	$(TOOLS_ATTR_DIR)/ppeCreateIfAttrService.pl $(PPE_FAPI2_DIR)/include $(IMPORT_XML_DIR)/p9_ppe_attributes.xml $(ATTRFILES)
 	mkdir -p $(OBJDIR)
 
-.PHONY: clean topfixedheaders $(PKLIB) $(P2PLIB) $(SBEFWLIB) $(PPELIB) $(FAPI2LIB) $(CACHELIB) $(CORELIB) $(PERVLIB) $(HWPLIB)
+.PHONY: clean topfixedheaders $(PKLIB) $(P2PLIB) $(PPELIB) $(FAPI2LIB) $(CACHELIB) $(CORELIB) $(PERVLIB) $(NESTLIB) $(HWPLIB)
 
-ATTRFILES += $(TOOLS_ATTR_DIR)/perv_attributes.xml
-ATTRFILES += $(TOOLS_ATTR_DIR)/proc_attributes.xml
-ATTRFILES += $(TOOLS_ATTR_DIR)/ex_attributes.xml
-ATTRFILES += $(TOOLS_ATTR_DIR)/eq_attributes.xml
-ATTRFILES += $(TOOLS_ATTR_DIR)/core_attributes.xml
+#errxml: topfixedheaders attrids platattr attrserv
 
 topfixedheaders:
-	$(BASE_FAPI2_DIR)/tools/ppeParseProcSbeFixed.pl . $(TOOLS_ATTR_DIR)/p9_ppe_attributes1.xml $(ATTRFILES)
+	$(TOOLS_ATTR_DIR)/ppeParseProcSbeFixed.pl . $(IMPORT_XML_DIR)/p9_ppe_attributes.xml $(ATTRFILES)
 
 attrids:
-	$(BASE_FAPI2_DIR)/tools/ppeParseAttributeInfo.pl $(PPE_FAPI2_DIR)/include $(TOOLS_ATTR_DIR)/p9_ppe_attributes1.xml $(ATTRFILES)
+	$(TOOLS_ATTR_DIR)/ppeParseAttributeInfo.pl $(PPE_FAPI2_DIR)/include $(IMPORT_XML_DIR)/p9_ppe_attributes.xml $(ATTRFILES)
 
 platattr:
-	$(BASE_FAPI2_DIR)/tools/ppeCreateAttrGetSetMacros.pl --path $(BASE_FAPI2_DIR)/tools --inc $(PPE_FAPI2_DIR)/include --src $(PPE_FAPI2_DIR)/src
+	$(TOOLS_ATTR_DIR)/ppeCreateAttrGetSetMacros.pl --path $(TOOLS_ATTR_DIR)/src --inc $(PPE_FAPI2_DIR)/include --src $(PPE_FAPI2_DIR)/src
 
 attrserv:
-	$(BASE_FAPI2_DIR)/tools/ppeCreateIfAttrService.pl $(PPE_FAPI2_DIR)/include $(TOOLS_ATTR_DIR)/p9_ppe_attributes1.xml $(ATTRFILES)
+	$(TOOLS_ATTR_DIR)/ppeCreateIfAttrService.pl $(PPE_FAPI2_DIR)/include $(IMPORT_XML_DIR)/p9_ppe_attributes.xml $(ATTRFILES)
 
 
 #Build macro-specific kernel code
 $(PKLIB):
-	$(MAKE) -I $(IMAGE_SRCDIR) -C $(PK_MAKE_DIR)
+	$(MAKE) -I $(IMAGE_SRCDIR) -C $(PK_MAKE_DIR) -f Makefile
 
 #Build macro-specific kernel code
 $(SBEFWLIB):
-	$(MAKE) -I $(IMAGE_SRCDIR) -C $(SBEFW_MAKE_DIR)
-
+	$(MAKE) -I $(IMAGE_SRCDIR) -C $(SBEFW_MAKE_DIR) -f Makefile
 
 #Build the code that is common for all processors (PPEs and 405)
 $(PPELIB):
 	@echo "Processing ppelibmakefile"
-	$(MAKE) -I $(IMAGE_SRCDIR) -C $(LIB_MAKE_DIR)
+	$(MAKE) -I $(IMAGE_SRCDIR) -C $(LIB_MAKE_DIR) -f Makefile
 
 #Build the cache exit code shared with the SBE
 $(CACHELIB):
 	@echo "Processing cache makefile"
-	$(MAKE) -I $(IMAGE_SRCDIR) -C $(CACHE_MAKE_DIR)
+	$(MAKE) -I $(IMAGE_SRCDIR) -C $(CACHE_MAKE_DIR) -f Makefile
 
 #Build the core exit code shared with the SBE
 $(CORELIB):
 	@echo "Processing core makefile"
-	$(MAKE) -I $(IMAGE_SRCDIR) -C $(CORE_MAKE_DIR)
+	$(MAKE) -I $(IMAGE_SRCDIR) -C $(CORE_MAKE_DIR)  -f Makefile
 
 #Build the perv code
 $(PERVLIB):
 	@echo "Processing perv makefile"
-	$(MAKE) -I $(IMAGE_SRCDIR) -C $(PERV_MAKE_DIR)
+	$(MAKE) -I $(IMAGE_SRCDIR) -C $(PERV_MAKE_DIR) -f Makefile
+
+#Build the nest code
+$(NESTLIB):
+	@echo "Processing nest makefile"
+	$(MAKE) -I $(IMAGE_SRCDIR) -C $(NEST_MAKE_DIR) -f Makefile
 
 #Build the comming HWP lib procedures
+        
+#Build the HWP lib procedures
 $(HWPLIB):
 	@echo "Processing HWP lib makefile"
-	$(MAKE) -I $(IMAGE_SRCDIR) -C $(HWPLIB_MAKE_DIR)
+	$(MAKE) -I $(IMAGE_SRCDIR) -C $(HWPLIB_MAKE_DIR) -f Makefile
 
 #Build the FAPI2 library
 $(FAPI2LIB):
 	@echo "Processing fapi2 makefile"
-	$(MAKE) -I $(IMAGE_SRCDIR) -C $(FAPI2_MAKE_DIR)/src
+	$(MAKE) -I $(IMAGE_SRCDIR) -C $(FAPI2_MAKE_DIR)/src -f Makefile
 
 ifdef P2P_ENABLE
 $(P2PLIB):
-	$(MAKE) -I $(IMAGE_SRCDIR) -C $(P2P_SRCDIR)
+	$(MAKE) -I $(IMAGE_SRCDIR) -C $(P2P_SRCDIR) -f Makefile
 endif 
 
+$(SBE_TOOLS):
+	$(MAKE) -C $(TOOLS_IMAGE_DIR) -f Makefile
+
+normalize: $(SBE_TOOLS) $(OBJDIR)/$(IMAGE_SEEPROM_NAME).bin
+	$(TOOLS_IMAGE_DIR)/sbe_xip_tool $(OBJDIR)/$(IMAGE_SEEPROM_NAME).bin normalize
+
+defaultset: $(SBE_TOOLS) $(OBJDIR)/$(IMAGE_SEEPROM_NAME).bin normalize 
+	$(TOOLS_IMAGE_DIR)/ppeSetFixed.pl $(TOOLS_IMAGE_DIR) $(BASE_OBJDIR)/$(IMAGE_SEEPROM_NAME).bin $(IMPORT_XML_DIR)/p9_ppe_attributes.xml $(ATTRFILES) 
+
+# Build hwp_error_info.H.  If the script fails then print the contents of
+# the header and then delete whatever garbage the script left to force it to
+# be built again.
+#
+# -*- HACK -*- Use local version of parseErrorInfo.pl until FW team
+# updates the standard version to work in assembly.  The source for this
+# script is : $(FAPI)/capi/scripts/parseErrorInfo.pl
+
+.PHONY : xml
+
+xml: $(FAPI_RC)
+
+$(FAPI_RC): $(TOOLS_ATTR_DIR)/parseErrorInfo.pl $(ERROR_XML_FILES)
+	$(TOOLS_ATTR_DIR)/parseErrorInfo.pl --empty-ffdc-classes --output-dir=. $(ERROR_XML_FILES)
+# 	if [ $$? -ne 0 ]; then \
+# 	echo "Build of hwp_error_info.H failed; Current contents :"; \
+# 	cat hwp_error_info.H; \
+# 	rm -f hwp_error_info.H; \
+# 	exit 1; fi
+# The above is commented out as the current version of make produces errors
+# This was taken from the P8 SBE Makefile which worked.
+
+$(OBJDIR)/fixed.bin: $(OBJDIR)/$(IMAGE_SEEPROM_NAME).bin
+	$(TOOLS_IMAGE_DIR)/sbe_xip_tool $(OBJDIR)/$(IMAGE_SEEPROM_NAME).bin extract .fixed $(BASE_OBJDIR)/fixed.bin
+
+
+appendbase: $(OBJDIR)/$(IMAGE_SEEPROM_NAME).bin $(OBJDIR)/$(IMAGE_SBE_NAME).bin
+	$(TOOLS_IMAGE_DIR)/sbe_xip_tool $(OBJDIR)/$(IMAGE_SEEPROM_NAME).bin append .base $(OBJDIR)/$(IMAGE_SBE_NAME).bin
+
+
+
+appendloader: $(OBJDIR)/$(IMAGE_SEEPROM_NAME).bin $(OBJDIR)/$(IMAGE_LOADER_NAME).bin
+	$(TOOLS_IMAGE_DIR)/sbe_xip_tool $(OBJDIR)/$(IMAGE_SEEPROM_NAME).bin append .baseloader $(OBJDIR)/$(IMAGE_LOADER_NAME).bin
+
+#/afs/bb/proj/cte/tools/ppetools/prod/powerpc-eabi/bin/objcopy -O binary --only-section=.fixed $(OBJDIR)/$(IMAGE_SEEPROM_NAME).out $(OBJDIR)/fixed.bin
+
 # collect all of the trace hash files for this image into a single trexStringFile
 .PHONY : tracehash
 tracehash:
@@ -209,12 +308,27 @@ tracehash:
 #clean the kernel directory first, then the application level clean
 clean:
 	rm -fr $(OBJDIR)
-	rm $(TOP-FIXED-HEADERS)
-	rm *.dump
-
+	rm -f $(TOP-FIXED-HEADERS)
+	rm -fr $(TOOLS_IMAGE_DIR)/bin/*
+	rm -f *.dump
+	rm -f hwp_return_codes.H hwp_error_info.H hwp_ffdc_classes.H collect_reg_ffdc.C set_sbe_error.H
 
 dump:
-	objdump -s $(OBJDIR)/$(IMAGE_NAME).out > $(IMAGE_NAME).dump
+	objdump -s $(OBJDIR)/$(IMAGE_SEEPROM_NAME).out > $(IMAGE_SEEPROM_NAME).dump
+	objdump -s $(OBJDIR)/$(IMAGE_SBE_NAME).out > $(IMAGE_SBE_NAME).dump
+
+.PHONY : run_spgpe run_pmgpe
+# load and run the SBE SeeProm image in a GPE simics environment
+run_spgpe: $(OBJDIR)/$(IMAGE_SEEPROM_NAME).out
+	$(SIMICS_WS)/simics \
+		-e '$$occ_gpe0_binary_to_load=$(OBJDIR)/$(IMAGE_SEEPROM_NAME).out' modelsetup.simics
+
+# load and run the SBE PibMem image in a GPE simics environment
+run_pmgpe: $(OBJDIR)/$(IMAGE_NAME).out
+	$(SIMICS_WS)/simics \
+		-e '$$occ_gpe0_binary_to_load=$(OBJDIR)/$(IMAGE_SBE_NAME).out' modelsetup.simics
+
+
 
 #Add dependencies to header files
 ifneq ($(MAKECMDGOALS),clean)
diff --git a/src/ppe/sbe/image/base_loader.c b/src/ppe/sbe/image/base_loader.c
new file mode 100644
index 0000000..dbba19f
--- /dev/null
+++ b/src/ppe/sbe/image/base_loader.c
@@ -0,0 +1,47 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/image/base_loader.c $                             */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#include "sbe_xip_image.h"
+#include "sbetrace.H"
+
+int32_t base_loader();
+
+
+int32_t base_loader() {
+
+    int32_t rc = 0;
+
+    SbeXipHeader *hdr = 0;//getXipHdr();
+    uint32_t idx;
+
+
+    for(idx = 0; idx < SBE_XIP_SECTIONS; idx++) {
+        
+        SBE_TRACE("Section Idx:%u Size:0x%08X", idx, hdr->iv_section[idx].iv_size);
+        
+    }
+
+    return rc;
+}
+
diff --git a/src/ppe/sbe/image/base_ppe_demo.c b/src/ppe/sbe/image/base_ppe_demo.c
index 0e8ea55..a2ece74 100644
--- a/src/ppe/sbe/image/base_ppe_demo.c
+++ b/src/ppe/sbe/image/base_ppe_demo.c
@@ -38,7 +38,9 @@
 #include "pk.h"
 #include "pk_trace.h"
 
-void base_ppe_demo_func(const char* str)
+
+//void base_ppe_demo_func(const char* str)
+void main()
 {
     PK_TRACE("TESTFUNCTION");
 }
diff --git a/src/ppe/sbe/image/base_ppe_header.S b/src/ppe/sbe/image/base_ppe_header.S
index b694bbe..8d2fa43 100644
--- a/src/ppe/sbe/image/base_ppe_header.S
+++ b/src/ppe/sbe/image/base_ppe_header.S
@@ -37,12 +37,12 @@
 #include "proc_sbe_fixed.H"
 
         
-#define PORE_SPACE_UNDEFINED 0xffff
-#define PORE_SPACE_OCI       0x8000
-#define PORE_SPACE_PNOR      0x800b
-#define PORE_SPACE_OTPROM    0x0001
-#define PORE_SPACE_SEEPROM   0x800c
-#define PORE_SPACE_PIBMEM    0x0008 
+#define IMAGE_SPACE_UNDEFINED 0xffff
+#define IMAGE_SPACE_OCI       0x8000
+#define IMAGE_SPACE_PNOR      0x800b
+#define IMAGE_SPACE_OTPROM    0x0001
+#define IMAGE_SPACE_SEEPROM   0x800c
+#define IMAGE_SPACE_BASE      0x0008 
 
 
 
@@ -73,7 +73,7 @@
     .endm
         
 	.macro	..check_default_space
-	.if	(_PGAS_DEFAULT_SPACE == PORE_SPACE_UNDEFINED)
+	.if	(_PGAS_DEFAULT_SPACE == IMAGE_SPACE_UNDEFINED)
 	.error	"The PGAS default address space has not been defined"
 	.endif
 	.endm	
@@ -132,19 +132,16 @@ __header_64_reserved:
         SbeXipSection header
         SbeXipSection fixed,                8
         SbeXipSection fixed_toc,            8
-        SbeXipSection ipl_text,             4
-        SbeXipSection ipl_data,             8
+        SbeXipSection loader_text,          4
+        SbeXipSection loader_data,          8
         SbeXipSection text,                 4
         SbeXipSection data,                 8
         SbeXipSection toc,                  4
         SbeXipSection strings
-        SbeXipSection halt,                 4, empty=1
-        SbeXipSection pibmem0,              8, empty=1
-        SbeXipSection dcrings,              8, empty=1
+        SbeXipSection base,                 4, empty=1
+        SbeXipSection baseloader,           8, empty=1
+        SbeXipSection overlay,              8, empty=1
         SbeXipSection rings,                8, empty=1
-        SbeXipSection slw,                128, empty=1
-        SbeXipSection fit,                     empty=1
-        SbeXipSection ffdc,                 8, empty=1
 
         
         //////////////////////////////////////////////////////////////////////
@@ -203,14 +200,14 @@ __header_string_reserved:
 
     .section .fixed, "a", @progbits
     .section .fixed_toc, "a", @progbits        
-    .section .ipl_data, "a", @progbits
-    .section .ipl_text, "a", @progbits        
+    .section .loader_data, "a", @progbits
+    .section .loader_text, "a", @progbits        
         
     .section .toc, "a", @progbits
     .section .strings, "aS", @progbits
     
-    ..set_default_space PORE_SPACE_SEEPROM
-    SbeXipHeader SBE_SEEPROM_MAGIC, 0xFFF00000, 0xFFF00C78, _sbe_base_size 
+    ..set_default_space IMAGE_SPACE_SEEPROM
+    SbeXipHeader SBE_SEEPROM_MAGIC, 0xFFF00000, 0xFFF00C78, _seeprom_size 
 
     // Create the .fixed section    
     .proc_sbe_fixed_proc_chip
diff --git a/src/ppe/sbe/image/base_sbe_fixed.S b/src/ppe/sbe/image/base_sbe_fixed.S
new file mode 100644
index 0000000..b9e4b04
--- /dev/null
+++ b/src/ppe/sbe/image/base_sbe_fixed.S
@@ -0,0 +1,69 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/image/base_sbe_fixed.S $                          */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/// \file sbefixed.S
+/// \brief code to generated fixed section in pibmem image
+///
+#include "sbe_xip_image.h"
+#include "proc_sbe_fixed.H"
+
+        
+	.macro	..checku, x:req, bits:req, err="Unsigned value too large"
+
+	.if	(((\bits) <= 0) || ((\bits) > 63))
+	.error	"The number of bits must be in the range 0 < bits < 64"
+	.endif
+
+	.iflt	(\x)
+	.error  "An unsigned value is required here"
+        .endif
+	
+	.ifgt	((\x) - (0xffffffffffffffff >> (64 - (\bits))))
+	.error	"\err"
+	.endif
+
+	.endm        
+
+        
+    .macro  ..check_u16, u16
+	..checku (\u16), 16, "Unsigned immediate is larger than 16 bits"
+    .endm
+
+     
+    .macro  ..set_default_space, s
+	..check_u16 (\s)
+    .set    _PGAS_DEFAULT_SPACE, (\s)
+    .endm
+        
+        
+
+    .section .fixed, "a", @progbits
+    
+
+    // Create the .fixed section    
+    .proc_sbe_fixed_proc_chip
+    .proc_sbe_fixed_perv
+    .proc_sbe_fixed_core
+    .proc_sbe_fixed_ex
+    .proc_sbe_fixed_eq
diff --git a/src/ppe/sbe/image/img_defs.mk b/src/ppe/sbe/image/img_defs.mk
index 240c5db..8140cb9 100644
--- a/src/ppe/sbe/image/img_defs.mk
+++ b/src/ppe/sbe/image/img_defs.mk
@@ -56,9 +56,13 @@
 #
 # OBJDIR             : target directory for all generated files
 
-IMAGE_NAME := sbe_main
+IMAGE_SEEPROM_NAME := seeprom_main
+IMAGE_SBE_NAME := sbe_main
+IMAGE_LOADER_NAME := loader_main
 
+ifndef PPE_TYPE
 PPE_TYPE := std
+endif
 
 ifndef IMAGE_SRCDIR
 export IMAGE_SRCDIR = $(abspath .)
@@ -76,24 +80,22 @@ ifndef PERV_SRCDIR
 export PERV_SRCDIR = $(abspath ../../hwp/perv)
 endif
 
-ifndef HWPLIB_SRCDIR
-export HWPLIB_SRCDIR = $(abspath ../../hwp/lib)
-
+ifndef NEST_SRCDIR
+export NEST_SRCDIR = $(abspath ../../hwp/nest)
 endif
 
-ifndef IMG_INCLUDES
-export IMG_INCLUDES = -I$(IMAGE_SRCDIR) -I$(CACHE_SRCDIR) -I$(CORE_SRCDIR)
-
+ifndef HWPLIB_SRCDIR
+export HWPLIB_SRCDIR = $(abspath ../../hwp/lib)
 endif
 
 ifndef IMG_INCLUDES
-export IMG_INCLUDES = -I$(IMAGE_SRCDIR) -I$(CACHE_SRCDIR) -I$(CORE_SRCDIR)
+export IMG_INCLUDES = -I$(IMAGE_SRCDIR) -I$(CACHE_SRCDIR) -I$(CORE_SRCDIR) -I$(PERV_SRCDIR) -I$(NEST_SRCDIR)
 endif
 ifndef BASE_OBJDIR
 export BASE_OBJDIR = $(abspath ../obj)
 endif
 
-export IMG_OBJDIR = $(BASE_OBJDIR)/$(IMAGE_NAME)
+export IMG_OBJDIR = $(BASE_OBJDIR)/$(IMAGE_SEEPROM_NAME)
 
 ifndef PK_SRCDIR
 export PK_SRCDIR = $(abspath ../../pk)
@@ -103,12 +105,17 @@ ifndef TOOLS_ATTR_DIR
 export TOOLS_ATTR_DIR = $(abspath ../../tools/scripts)
 endif
 
+ifndef TOOLS_IMAGE_DIR
+export TOOLS_IMAGE_DIR = $(abspath ../../tools/image)
+endif
 
-
-ifndef GCC-TOOL-PREFIX
-GCC-TOOL-PREFIX = $(CTEPATH)/tools/gcc405lin/prod/usr/bin/powerpc-linux-
+ifndef IMPORT_XML_DIR
+export IMPORT_XML_DIR = $(abspath ../../importtemp/xml)
 endif
 
+ifndef IMPORT_COMMON_DIR
+export IMPORT_COMMON_DIR = $(abspath ../../importtemp/common)
+endif
 
 ifndef P2P_SRCDIR
 export P2P_SRCDIR = $(abspath ../../tools/PowerPCtoPPE)
@@ -128,15 +135,13 @@ export PPE_FAPI2_DIR = $(abspath ../../hwpf/plat)
 endif
 
 ifndef BASE_FAPI2_DIR
-export BASE_FAPI2_DIR = $(abspath /afs/awd/projects/eclipz/lab/p8/u/rembold/ekbgit/hwpf/fapi2)
+export BASE_FAPI2_DIR = $(abspath ../../importtemp/fapi2)
 endif
 
-
 ifndef CC_ROOT
 export CC_ROOT = ${CTEPATH}/tools/gcc405lin/prod
 endif
 
-
 ifndef GCC-TOOL-PREFIX
 GCC-TOOL-PREFIX  = ${CC_ROOT}/usr/bin/powerpc-linux-
 endif
@@ -145,10 +150,16 @@ ifndef BINUTILS-TOOL-PREFIX
 BINUTILS-TOOL-PREFIX = $(CTEPATH)/tools/ppetools/prod/powerpc-eabi/bin/
 endif
 
+ifndef FAPI_RC
+FAPI_RC = hwp_return_codes.H
+#FAPI_RC =
+endif
+
 OBJDIR = $(BASE_OBJDIR)$(SUB_OBJDIR)
 
 CC_ASM  = $(GCC-TOOL-PREFIX)gcc
-TCC     = $(PPETRACEPP_DIR)/ppetracepp $(GCC-TOOL-PREFIX)g++
+#TCC     = $(PPETRACEPP_DIR)/ppetracepp $(GCC-TOOL-PREFIX)g++
+TCC     = $(PPETRACEPP_DIR)/ppetracepp $(GCC-TOOL-PREFIX)gcc
 CC      = $(PPETRACEPP_DIR)/ppetracepp $(GCC-TOOL-PREFIX)gcc
 AS      = $(BINUTILS-TOOL-PREFIX)as
 AR      = $(BINUTILS-TOOL-PREFIX)ar
@@ -184,7 +195,7 @@ endif
 # Generate a 16bit trace string hash prefix value based on the name of this image.  This will form
 # the upper 16 bits of the 32 bit trace hash values.
 ifndef PK_TRACE_HASH_PREFIX
-PK_TRACE_HASH_PREFIX := $(shell echo $(IMAGE_NAME) | md5sum | cut -c1-4 | xargs -i printf "%d" 0x{})
+PK_TRACE_HASH_PREFIX := $(shell echo $(IMAGE_SEEPROM_NAME) | md5sum | cut -c1-4 | xargs -i printf "%d" 0x{})
 endif
 
 
@@ -194,68 +205,80 @@ ifndef GCC-O-LEVEL
 GCC-O-LEVEL = -O
 endif
 
-GCC-DEFS += -DIMAGE_NAME=$(IMAGE_NAME)
+GCC-DEFS += -DIMAGE_NAME=$(IMAGE_SEEPROM_NAME)
 GCC-DEFS += -DPK_TIMER_SUPPORT=$(PK_TIMER_SUPPORT) 
 GCC-DEFS += -DPK_THREAD_SUPPORT=$(PK_THREAD_SUPPORT) 
 GCC-DEFS += -DPK_TRACE_SUPPORT=$(PK_TRACE_SUPPORT)
 GCC-DEFS += -DPK_TRACE_HASH_PREFIX=$(PK_TRACE_HASH_PREFIX)
+GCC-DEFS += -DUSE_PK_APP_CFG_H=1
 GCC-DEFS += -D__PK__=1
 GCC-DEFS += -D__SBE__=1
+GCC-DEFS += -D__PPE__=1
+GCC-DEFS += -DFAPI2_NO_FFDC=1
+GCC-DEFS += -DPK_TRACE_SZ=512
+
 DEFS += $(GCC-DEFS)
 export LD_LIBRARY_PATH = /afs/awd.austin.ibm.com/proj/p3/cte/tools/gcc405lin/vol1/usr/lib
 
 ############################################################################
 
 
-INCLUDES += $(IMG_INCLUDES) \
-	-I$(IMAGE_SRCDIR)/../../../include \
-	-I$(PLAT_FAPI2_DIR)/include \
-	-I$(PPE_FAPI2_DIR)/include \
-	-I$(BASE_FAPI2_DIR)/include \
-	-I$(PK_SRCDIR)/../include \
-	-I$(PK_SRCDIR)/$(PPE_TYPE) \
-	-I$(PK_SRCDIR)/../include \
-	-I$(PK_SRCDIR)/kernel \
-        -I$(PK_SRCDIR)/ppe \
-        -I$(PK_SRCDIR)/ppe42 \
-        -I$(PK_SRCDIR)/trace
+INCLUDES += $(IMG_INCLUDES)
+INCLUDES += -I$(IMAGE_SRCDIR)/../../../include
+INCLUDES += -I$(HWPLIB_SRCDIR)
+INCLUDES += -I$(PLAT_FAPI2_DIR)/include
+INCLUDES += -I$(PPE_FAPI2_DIR)/include
+INCLUDES += -I$(BASE_FAPI2_DIR)/include
+INCLUDES += -I$(PK_SRCDIR)/../include
+INCLUDES += -I$(PK_SRCDIR)/$(PPE_TYPE)
+INCLUDES += -I$(PK_SRCDIR)/../include
+INCLUDES += -I$(PK_SRCDIR)/kernel
+INCLUDES += -I$(PK_SRCDIR)/ppe
+INCLUDES += -I$(PK_SRCDIR)/ppe42
+INCLUDES += -I$(PK_SRCDIR)/../sbe/sbefw
+INCLUDES += -I$(PK_SRCDIR)/trace
+INCLUDES += -I$(PK_SRCDIR)/../tools/ppetracepp
+INCLUDES += -I$(IMPORT_COMMON_DIR)/include
 
 PIPE-CFLAGS = -pipe -Wa,-m405
 
-GCC-CFLAGS += -g -Wall -Werror -Wno-error=unused-label \
-	-msoft-float -mcpu=405 -mmulhw \
-	-meabi -msdata=eabi  \
-	-ffreestanding \
-        -fno-common \
-	-fsigned-char \
-	-fno-inline-functions-called-once \
-	-ffixed-r11 \
-	-ffixed-r12 \
-	-ffixed-r14 \
-	-ffixed-r15 \
-	-ffixed-r16 \
-	-ffixed-r17 \
-	-ffixed-r18 \
-	-ffixed-r19 \
-	-ffixed-r20 \
-	-ffixed-r21 \
-	-ffixed-r22 \
-	-ffixed-r23 \
-	-ffixed-r24 \
-	-ffixed-r25 \
-	-ffixed-r26 \
-	-ffixed-r27 \
-	-ffixed-cr1 \
-	-ffixed-cr2 \
-	-ffixed-cr3 \
-	-ffixed-cr4 \
-	-ffixed-cr5 \
-	-ffixed-cr6 \
-	-ffixed-cr7
-
-
-CFLAGS      	=  -c $(GCC-CFLAGS) $(PIPE-CFLAGS) $(GCC-O-LEVEL) $(INCLUDES) 
-
+# -Wno-error=unused-label , needs to be in.
+
+GCC-CFLAGS += -Wall -Werror -Wno-unused-label
+GCC-CFLAGS += -msoft-float -mcpu=405 -mmulhw
+GCC-CFLAGS += -meabi -msdata=eabi
+GCC-CFLAGS += -gpubnames -gdwarf-3
+GCC-CFLAGS += -ffreestanding
+GCC-CFLAGS += -fno-common
+GCC-CFLAGS += -fno-exceptions
+GCC-CFLAGS += -fsigned-char
+GCC-CFLAGS += -fno-inline-functions-called-once
+GCC-CFLAGS += -ffixed-r11
+GCC-CFLAGS += -ffixed-r12
+GCC-CFLAGS += -ffixed-r14
+GCC-CFLAGS += -ffixed-r15
+GCC-CFLAGS += -ffixed-r16
+GCC-CFLAGS += -ffixed-r17
+GCC-CFLAGS += -ffixed-r18
+GCC-CFLAGS += -ffixed-r19
+GCC-CFLAGS += -ffixed-r20
+GCC-CFLAGS += -ffixed-r21
+GCC-CFLAGS += -ffixed-r22
+GCC-CFLAGS += -ffixed-r23
+GCC-CFLAGS += -ffixed-r24
+GCC-CFLAGS += -ffixed-r25
+GCC-CFLAGS += -ffixed-r26
+GCC-CFLAGS += -ffixed-r27
+GCC-CFLAGS += -ffixed-cr1
+GCC-CFLAGS += -ffixed-cr2
+GCC-CFLAGS += -ffixed-cr3
+GCC-CFLAGS += -ffixed-cr4
+GCC-CFLAGS += -ffixed-cr5
+GCC-CFLAGS += -ffixed-cr6
+GCC-CFLAGS += -ffixed-cr7
+
+CFLAGS =  
+PPE-CFLAGS = $(CFLAGS) -c $(GCC-CFLAGS) $(PIPE-CFLAGS) $(GCC-O-LEVEL) $(INCLUDES)
 
 CPPFLAGS    	= -E -std=c++11
 #CPPFLAGS    	= -E
@@ -312,14 +335,14 @@ endif
 # work as Make targets. The *.d files are include-ed in the
 # subdirectory Makefiles.
 
-$(OBJDIR)/%.d: %.C
+$(OBJDIR)/%.d: %.C $(FAPI_RC)
 	@set -e; rm -f $@; \
 	echo -n "$(OBJDIR)/" > $@.$$$$; \
 	$(CC_ASM) -MM $(INCLUDES) $(CPPFLAGS) $(DEFS) $< >> $@.$$$$; \
 	sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < $@.$$$$ > $@; \
 	rm -f $@.$$$$
 
-$(OBJDIR)/%.d: %.c
+$(OBJDIR)/%.d: %.c $(FAPI_RC)
 	@set -e; rm -f $@; \
 	echo -n "$(OBJDIR)/" > $@.$$$$; \
 	echo "$(INCLUDES)"; \
@@ -327,7 +350,7 @@ $(OBJDIR)/%.d: %.c
 	sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < $@.$$$$ > $@; \
 	rm -f $@.$$$$
 
-$(OBJDIR)/%.d: %.S
+$(OBJDIR)/%.d: %.S $(FAPI_RC)
 	@set -e; rm -f $@; \
 	echo -n "$(OBJDIR)/" > $@.$$$$; \
 	$(CC_ASM) -MM $(INCLUDES) $(CPPFLAGS) $(DEFS) $< >> $@.$$$$; \
diff --git a/src/ppe/sbe/image/linkloader.cmd b/src/ppe/sbe/image/linkloader.cmd
new file mode 100644
index 0000000..33c7092
--- /dev/null
+++ b/src/ppe/sbe/image/linkloader.cmd
@@ -0,0 +1,96 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/image/linkloader.cmd $                            */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+// Need to do this so that elf32-powerpc is not modified!
+#undef powerpc
+
+#ifndef INITIAL_STACK_SIZE
+#define INITIAL_STACK_SIZE 256
+#endif
+
+OUTPUT_FORMAT(elf32-powerpc);
+
+MEMORY
+{
+ sram : ORIGIN = 0xffff2000, LENGTH = 0x10000
+}
+
+SECTIONS
+{
+    . = 0xffff2000;
+
+    ////////////////////////////////
+    // Read-only Data
+    ////////////////////////////////
+
+    . = ALIGN(8);
+    _RODATA_SECTION_BASE = .;
+
+   .text . : { *(.text) } > sram
+   .data  . : { *(.data) } > sram
+
+    // SDA2 constant sections .sdata2 and .sbss2 must be adjacent to each
+    // other.  Our SDATA sections are small so we'll use strictly positive
+    // offsets. 
+
+    _SDA2_BASE_ = .;
+   .sdata2 . : { *(.sdata2) } > sram
+   .sbss2  . : { *(.sbss2) } > sram
+
+   // Other read-only data.  
+
+   .rodata . : { *(.rodata*) *(.got2) } > sram
+
+    _RODATA_SECTION_SIZE = . - _RODATA_SECTION_BASE;
+
+    ////////////////////////////////
+    // Read-write Data
+    ////////////////////////////////
+
+    . = ALIGN(8);
+    _DATA_SECTION_BASE = .;
+
+    // SDA sections .sdata and .sbss must be adjacent to each
+    // other.  Our SDATA sections are small so we'll use strictly positive
+    // offsets. 
+
+    _SDA_BASE_ = .;
+    .sdata  . : { *(.sdata)  } > sram
+    .sbss   . : { *(.sbss)   } > sram
+
+    // Other read-write data
+    // It's not clear why boot.S is generating empty .glink,.iplt
+
+   .rela   . : { *(.rela*) } > sram
+   .rwdata . : { *(.data) *(.bss) } > sram
+
+   _PK_INITIAL_STACK_LIMIT = .;
+   . = . + INITIAL_STACK_SIZE;
+   _PK_INITIAL_STACK = . - 1;
+
+    . = ALIGN(8);
+    _loader_end = . - 0;
+
+}
diff --git a/src/ppe/sbe/image/linksbe.cmd b/src/ppe/sbe/image/linksbe.cmd
new file mode 100644
index 0000000..735a64b
--- /dev/null
+++ b/src/ppe/sbe/image/linksbe.cmd
@@ -0,0 +1,97 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/image/linksbe.cmd $                               */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+// Need to do this so that elf32-powerpc is not modified!
+#undef powerpc
+
+#ifndef INITIAL_STACK_SIZE
+#define INITIAL_STACK_SIZE 256
+#endif
+
+OUTPUT_FORMAT(elf32-powerpc);
+
+MEMORY
+{
+ sram : ORIGIN = 0xffff0000, LENGTH = 0x10000
+}
+
+SECTIONS
+{
+    . = 0xffff0000;
+
+    .vectors : {. = ALIGN(512); *(.vectors)} > sram
+    .fixed . : {. = ALIGN(512); *(.fixed) } > sram
+    .text . : {. = ALIGN(512); *(.text)} > sram
+
+    ////////////////////////////////
+    // Read-only Data
+    ////////////////////////////////
+
+    . = ALIGN(8);
+    _RODATA_SECTION_BASE = .;
+
+    // SDA2 constant sections .sdata2 and .sbss2 must be adjacent to each
+    // other.  Our SDATA sections are small so we'll use strictly positive
+    // offsets. 
+
+    _SDA2_BASE_ = .;
+   .sdata2 . : { *(.sdata2) } > sram
+   .sbss2  . : { *(.sbss2) } > sram
+
+   // Other read-only data.  
+
+   .rodata . : { *(.rodata*) *(.got2) } > sram
+
+    _RODATA_SECTION_SIZE = . - _RODATA_SECTION_BASE;
+
+    ////////////////////////////////
+    // Read-write Data
+    ////////////////////////////////
+
+    . = ALIGN(8);
+    _DATA_SECTION_BASE = .;
+
+    // SDA sections .sdata and .sbss must be adjacent to each
+    // other.  Our SDATA sections are small so we'll use strictly positive
+    // offsets. 
+
+    _SDA_BASE_ = .;
+    .sdata  . : { *(.sdata)  } > sram
+    .sbss   . : { *(.sbss)   } > sram
+
+    // Other read-write data
+    // It's not clear why boot.S is generating empty .glink,.iplt
+
+   .rela   . : { *(.rela*) } > sram
+   .rwdata . : { *(.data) *(.bss) } > sram
+
+   _PK_INITIAL_STACK_LIMIT = .;
+   . = . + INITIAL_STACK_SIZE;
+   _PK_INITIAL_STACK = . - 1;
+
+    . = ALIGN(8);
+    _sbe_end = . - 0;
+
+}
diff --git a/src/ppe/sbe/image/linkseeprom.cmd b/src/ppe/sbe/image/linkseeprom.cmd
new file mode 100644
index 0000000..6897c3d
--- /dev/null
+++ b/src/ppe/sbe/image/linkseeprom.cmd
@@ -0,0 +1,115 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/image/linkseeprom.cmd $                           */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// Need to do this so that elf32-powerpc is not modified!
+#undef powerpc
+
+#ifndef INITIAL_STACK_SIZE
+#define INITIAL_STACK_SIZE 256
+#endif
+
+OUTPUT_FORMAT(elf32-powerpc);
+
+SECTIONS
+{
+    . = 0xfff00000;
+    _seeprom_origin = . - 0;
+    ////////////////////////////////
+    // Header
+    ////////////////////////////////
+   . = ALIGN(1); _header_origin = .; _header_offset = . - _seeprom_origin; .header . : { *(.header) } _header_size = . - _header_origin;
+
+    ////////////////////////////////
+    // FIXED
+    ////////////////////////////////
+    . = ALIGN(512); _fixed_origin = .; _fixed_offset = . - _seeprom_origin; .fixed . : { *(.fixed) }  _fixed_size = . - _fixed_origin;
+
+   ////////////////////////////////
+    // FIXED_TOC
+    ////////////////////////////////
+    . = ALIGN(8); _fixed_toc_origin = .; _fixed_toc_offset = . - _seeprom_origin; .fixed_toc . : { *(.fixed_toc) } _fixed_toc_size = . - _fixed_toc_origin;
+
+    ////////////////////////////////
+    // LOADER_TEXT
+    ////////////////////////////////
+    . = ALIGN(4); _loader_text_origin = .; _loader_text_offset = . - _seeprom_origin; .loader_text . : { *(.loader_text) } _loader_text_size = . - _loader_text_origin;
+
+    ////////////////////////////////
+    // LOADER_DATA
+    ////////////////////////////////
+    . = ALIGN(8); _loader_data_origin = .; _loader_data_offset = . - _seeprom_origin; .loader_data . : { *(.loader_data) } _loader_data_size = . - _loader_data_origin;
+
+    ////////////////////////////////
+    // TEXT
+    ////////////////////////////////
+    . = ALIGN(4); _text_origin = .; _text_offset = . - _seeprom_origin; .text . : {. = ALIGN(512); *(.vectors) *(.text) *(.eh_frame) } _text_size = . - _text_origin;
+
+    ////////////////////////////////
+    // DATA
+    ////////////////////////////////
+    . = ALIGN(8); _data_origin = .; _data_offset = . - _seeprom_origin; .data . : { *(.data) *(.comment) *(.rodata*)} _data_size = . - _data_origin;
+
+   ////////////////////////////////
+    // TOC
+    ////////////////////////////////
+    . = ALIGN(4); _toc_origin = .; _toc_offset = . - _seeprom_origin; .toc . : { *(.toc) } _toc_size = . - _toc_origin;
+
+   ////////////////////////////////
+    // STRING
+    ////////////////////////////////
+    . = ALIGN(1); _strings_origin = .; _strings_offset = . - _seeprom_origin; .strings . : { *(.strings) } _strings_size = . - _strings_origin;
+
+//    . = ALIGN(8);
+//    _seeprom_size = . - _seeprom_origin;
+//    _seeprom_end = . - 0;
+
+
+    _RODATA_SECTION_BASE = .;
+
+
+    _SDA2_BASE_ = .;
+
+    _RODATA_SECTION_SIZE = . - _RODATA_SECTION_BASE;
+
+    // SDA sections .sdata and .sbss must be adjacent to each
+    // other.  Our SDATA sections are small so we'll use strictly positive
+    // offsets. 
+
+    _SDA_BASE_ = .;
+
+    .sbss   . : { *(.sbss)   }
+    .sdata   . : { *(.sdata)  }
+
+
+   _PK_INITIAL_STACK_LIMIT = .;
+   . = . + INITIAL_STACK_SIZE;
+   _PK_INITIAL_STACK = . - 1;
+
+
+    . = ALIGN(8);
+    _seeprom_size = . - _seeprom_origin;
+    _seeprom_end = . - 0;
+
+
+}
diff --git a/src/ppe/sbe/image/sbe_loader.c b/src/ppe/sbe/image/sbe_loader.c
new file mode 100644
index 0000000..43041ff
--- /dev/null
+++ b/src/ppe/sbe/image/sbe_loader.c
@@ -0,0 +1,46 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/image/sbe_loader.c $                              */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#include "sbe_xip_image.h"
+#include "sbetrace.H"
+
+int32_t sbe_loader() __attribute__ ((section (".loader_text")));
+
+
+int32_t sbe_loader() {
+
+    int32_t rc = 0;
+
+    SbeXipHeader *hdr = 0;//getXipHdr();
+    uint32_t idx;
+
+
+    for(idx = 0; idx < SBE_XIP_SECTIONS; idx++) {
+        
+        SBE_TRACE("Section Idx:%u Size:0x%08X", idx, hdr->iv_section[idx].iv_size);
+        
+    }
+
+    return rc;
+}
diff --git a/src/ppe/sbe/image/sbe_main.C b/src/ppe/sbe/image/sbe_main.C
new file mode 100644
index 0000000..025e808
--- /dev/null
+++ b/src/ppe/sbe/image/sbe_main.C
@@ -0,0 +1,388 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/image/sbe_main.C $                                */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file sample_main.c
+/// \brief Sample program that creates and starts a thread
+///
+/// This file demonstrates how to create a thread and run it.  It also provides
+/// an example of how to add traces to the code.
+#include <fapi2.H>
+//#include <p9_sbe_perv.H>
+
+#include <vector>
+
+
+
+
+extern "C"
+{
+
+#include "pk.h"
+#include "pk_trace.h"
+//#include "pk_trace_wrap.h"
+//#include "common_scom_addresses.H"
+//#include "p9_sbe_perv.H"
+#include "p9_hcd_cache.H"
+#include "p9_hcd_core.H"
+#include "proc_sbe_fixed.H"
+#include "trac_interface.h"
+
+}
+
+namespace fapi2attr
+{
+
+extern ProcChipAttributes_t* G_proc_chip_attributes asm("G_proc_chip_attributes")   __attribute__ ((section (".fixed")));
+extern PervAttributes_t*     G_perv_attributes      asm("G_perv_attributes")        __attribute__ ((section (".fixed")));
+extern CoreAttributes_t*     G_core_attributes      asm("G_core_attributes")        __attribute__ ((section (".fixed")));
+extern EQAttributes_t*       G_eq_attributes        asm("G_eq_attributes")          __attribute__ ((section (".fixed")));
+extern EXAttributes_t*       G_ex_attributes        asm("G_ex_attributes")          __attribute__ ((section (".fixed")));
+
+}
+
+extern "C" {
+
+
+#define KERNEL_STACK_SIZE   256
+#define MAIN_THREAD_STACK_SIZE  256
+
+// Necessary Kernel Structures
+uint8_t     G_kernel_stack[KERNEL_STACK_SIZE];
+uint8_t     G_main_thread_stack[MAIN_THREAD_STACK_SIZE];
+PkThread    G_main_thread;
+
+
+fapi2::ReturnCode
+hwp_chip(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target);
+
+fapi2::ReturnCode
+hwp_chip2(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target);
+
+
+fapi2::ReturnCode
+hwp_core(const fapi2::Target<fapi2::TARGET_TYPE_CORE> & i_target);
+
+fapi2::ReturnCode
+hwp_eq(const fapi2::Target<fapi2::TARGET_TYPE_EQ> & i_target);
+
+fapi2::ReturnCode
+hwp_perv(const fapi2::Target<fapi2::TARGET_TYPE_PERV> & i_target);
+
+
+//---------------------------------------------------------------------------
+
+
+void main_thread(void* arg)
+{
+
+        // This is workaround. Currently we do not have code to initialise
+        // global objects. So initializing global objects against using local
+        // initialized object
+        FAPI_DBG("Workaround temporary allocation of Global Vector");
+        std::vector<fapi2::plat_target_handle_t> targets1;
+        G_vec_targets = std::move(targets1);
+
+        // Intialize the targets
+        fapi2::plat_TargetsInit();
+
+        // Get a specific target
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>chip_target_new =
+                fapi2::plat_getChipTarget();
+                
+        FAPI_DBG("chip_target_new = 0x%08X", (uint32_t)(chip_target_new.get()>>32));
+
+        FAPI_TRY(hwp_chip(chip_target_new));
+        
+        FAPI_TRY(hwp_chip2(chip_target_new));
+
+        ///
+#ifndef __noRC__
+        // PIB Errors are masked for platforms like SBE where
+        // explict error code checking is to occur
+        fapi2::setPIBErrorMask(0b11111111);
+#else
+        // PIB Errors are unmaskd for platforms that desire to take machine
+        // check interrupts
+        fapi2::setPIBErrorMask(0b00000000);
+#endif
+
+//       FAPI_TRY(hwp_chip(chip_target_new));
+
+//       FAPI_TRY(p9_sbe_attr_setup(chip_target));
+//       FAPI_TRY(p9_sbe_check_master(chip_target));
+//       FAPI_TRY(p9_sbe_setup_evid(chip_target));
+
+
+fapi_try_exit:
+    return;
+
+}
+
+// A Chip try
+fapi2::ReturnCode
+hwp_chip(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target)
+{
+
+    FAPI_DBG("i_target = 0x%08X", (uint32_t)(i_target.get()>>32));
+
+    auto l_perv_functional_vector =
+		        i_target.getChildren<fapi2::TARGET_TYPE_PERV>
+                (fapi2::TARGET_STATE_PRESENT);
+
+    // Get the TPChiplet target
+    uint32_t i = 0;
+    for (auto it: l_perv_functional_vector)
+	{
+
+	    FAPI_DBG("Perv Functional Target %u value=%08X chiplet %02X",
+                    i,
+                    (uint32_t)(it.get()>>32),
+                    (uint32_t)(it.getChipletNumber()));
+
+        ++i;
+	}
+
+    auto l_core_functional_vector =
+		        i_target.getChildren<fapi2::TARGET_TYPE_CORE>
+                (fapi2::TARGET_STATE_PRESENT);
+
+    // Get the Core Chiplet targets
+    uint32_t j = 0;
+    for (auto it: l_core_functional_vector)
+	{
+
+	    FAPI_DBG("Core Functional Target %u value=%08X chiplet %02X",
+                    j,
+                    (uint32_t)(it.get()>>32),
+                    (uint32_t)(it.getChipletNumber()));
+
+        ++j;
+	}
+
+    
+     fapi2::buffer<uint64_t> data = 0;
+     const uint32_t address = 0x0006d010;
+
+     FAPI_INF("hwp_chip %u", address);
+
+     uint64_t databuffer;
+     getscom_abs(address, &databuffer);
+
+     databuffer = 0xDEAD000000000000ull;
+
+     putscom_abs(address, databuffer);
+
+     data = 0xBADC0DE800000000ull;
+     FAPI_TRY(fapi2::putScom(i_target, address, data));
+
+
+     FAPI_TRY(fapi2::getScom(i_target, address, data));
+     FAPI_DBG("First getSCOM: data = %016llX", revle64(data));
+
+     data.setBit<0, 16>();
+     FAPI_TRY(fapi2::putScom(i_target, 0x0006d010, data));
+
+     return fapi2::FAPI2_RC_SUCCESS;
+
+fapi_try_exit:
+     return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA;
+}
+
+// A Chip try
+fapi2::ReturnCode
+hwp_chip2(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target)
+{
+
+    FAPI_DBG("i_target = 0x%08X", (uint32_t)(i_target.get()>>32));
+
+
+    auto l_eq_functional_vector =
+		        i_target.getChildren<fapi2::TARGET_TYPE_EQ>
+                (fapi2::TARGET_STATE_PRESENT);
+
+    // Get the EQ Chiplet target
+    uint32_t k = 0;
+    for (auto it: l_eq_functional_vector)
+	{
+
+	    FAPI_DBG("EQ Functional Target %u value=%08X chiplet %02X",
+                    k,
+                    (uint32_t)(it.get()>>32),
+                    (uint32_t)(it.getChipletNumber()));
+
+        ++k;
+	}
+    
+    
+    auto l_mcs_functional_vector =
+		        i_target.getChildren<fapi2::TARGET_TYPE_MCS>
+                (fapi2::TARGET_STATE_PRESENT);
+                
+    // Get the MCS Chiplet target
+    uint32_t m = 0;
+    for (auto it: l_mcs_functional_vector)
+	{
+
+	    FAPI_DBG("MCS Functional Target %u value=%08X chiplet %02X",
+                    m,
+                    (uint32_t)(it.get()>>32),
+                    (uint32_t)(it.getChipletNumber()));
+
+        ++m;
+	}
+    
+
+     return fapi2::FAPI2_RC_SUCCESS;
+
+fapi_try_exit:
+     return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA;
+}
+
+// A Core try
+fapi2::ReturnCode
+hwp_core(const fapi2::Target<fapi2::TARGET_TYPE_CORE> & i_target)
+{
+
+    // Temporary target that pulls out only the chiplet overly.  This keeps
+    // from having to compute this for each SCOM operation.
+//    fapi2::Target<fapi2::TARGET_TYPE_ADDRESS> iv_target (i_target.getAddressOverlay());
+
+    fapi2::buffer<uint64_t> data = 0;
+    fapi2::buffer<uint64_t> mask;
+
+    uint32_t address = 0x200F5678;
+    FAPI_TRY(fapi2::getScom(i_target, address, data));
+
+    FAPI_TRY(fapi2::putScom(i_target, 0x20006789, data));
+
+    data = 0xBADC0DEBADC0DEBAull;
+    FAPI_TRY(fapi2::putScom(i_target, 0x0000AAAA, data));
+
+    FAPI_TRY(fapi2::getScom(i_target, address, data));
+
+    FAPI_TRY(fapi2::modifyScom(i_target, address, data, fapi2::CHIP_OP_MODIFY_MODE_OR));
+
+
+    mask = BITS(4,4);
+    FAPI_TRY(fapi2::putScomUnderMask(i_target, address, data, mask));
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+fapi_try_exit:
+
+    return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA;
+}
+
+// An EQ try
+fapi2::ReturnCode
+hwp_eq(const fapi2::Target<fapi2::TARGET_TYPE_EQ> & i_target)
+{
+    fapi2::buffer<uint64_t> data = 0;
+
+    uint64_t address = 0x1000F2222;
+    FAPI_TRY(fapi2::getScom(i_target, address, data));
+
+
+    FAPI_TRY(fapi2::putScom(i_target, 0x10006789, data));
+
+    data = 0xDEADBEEFDEADBEEFull;
+    FAPI_TRY(fapi2::putScom(i_target, 0x1000ABCD, data));
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+fapi_try_exit:
+
+    return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA;
+}
+
+// A Perv try
+fapi2::ReturnCode
+hwp_perv(const fapi2::Target<fapi2::TARGET_TYPE_PERV> & i_target)
+{
+    fapi2::buffer<uint64_t> data = 0;;
+
+    uint64_t address = 0x00005678;
+
+    for (uint32_t i = 0; i < 5; i++)
+    {
+        FAPI_TRY(fapi2::getScom(i_target, address+i, data));
+
+        data.setBit<4>();
+
+        FAPI_TRY(fapi2::putScom(i_target, address+i, data));
+
+        data = 0xDEADBEEFDEADBEEFull;
+        FAPI_TRY(fapi2::putScom(i_target, address+(2*i), data));
+    }
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+fapi_try_exit:
+
+    return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA;
+}
+
+
+
+// The main function is called by the boot code (after initializing some
+// registers)
+int main(int argc, char **argv)
+{
+    // initializes kernel data (stack, threads, timebase, timers, etc.)
+    pk_initialize((PkAddress)G_kernel_stack,
+                  KERNEL_STACK_SIZE,
+                  0,
+                  500000000);
+
+    PK_TRACE("Kernel init completed");
+
+    //Initialize the thread control block for G_main_thread
+    pk_thread_create(&G_main_thread,
+                      (PkThreadRoutine)main_thread,
+                      (void*)NULL,
+                      (PkAddress)G_main_thread_stack,
+                      (size_t)MAIN_THREAD_STACK_SIZE,
+                      (PkThreadPriority)1);
+
+    PK_TRACE_BIN("G_main_thread", &G_main_thread, sizeof(G_main_thread));
+
+    //Make G_main_thread runnable
+    pk_thread_resume(&G_main_thread);
+
+    PK_TRACE("Starting thread(s)");
+
+    // Start running the highest priority thread.
+    // This function never returns
+    pk_start_threads();
+
+    return 0;
+}
+
+}  // extern C
diff --git a/src/ppe/sbe/image/sbe_xip_image.c b/src/ppe/sbe/image/sbe_xip_image.c
new file mode 100644
index 0000000..bf692c3
--- /dev/null
+++ b/src/ppe/sbe/image/sbe_xip_image.c
@@ -0,0 +1,2487 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/image/sbe_xip_image.c $                           */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/// \file sbe_xip_image.c 
+/// \brief APIs for validating, normalizing, searching and manipulating
+/// SBE-XIP images.
+///
+/// The background, APIs and implementation details are documented in the
+/// document "SBE-XIP Binary format" currently available at this link:
+///
+/// - https://mcdoc.boeblingen.de.ibm.com/out/out.ViewDocument.php?documentid=2678
+///
+/// \bug The sbe_xip_validate() API should be carefully reviewed to ensure
+/// that validating even a corrupt image can not lead to a segfault, i.e., to
+/// ensure that no memory outside of the putative bounds of the image is ever
+/// referenced during validation.
+
+#ifndef PLIC_MODULE
+#include <stddef.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#endif // PLIC_MODULE
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include "sbe_xip_image.h"
+
+
+////////////////////////////////////////////////////////////////////////////
+// Local Functions
+////////////////////////////////////////////////////////////////////////////
+
+// PHYP has their own way of implementing the <string.h> functions. PHYP also
+// does not allow static functions or data, so all of the XIP_STATIC functions
+// defined here are global to PHYP.
+
+#ifdef PPC_HYP
+
+#ifdef PLIC_MODULE
+
+#define strcpy(dest, src) hvstrcpy(dest, src)
+#define strlen(s) hvstrlen(s)
+#define strcmp(s1, s2) hvstrcmp(s1, s2)
+#endif //PLIC_MODULE
+
+#define XIP_STATIC
+        
+#else // PPC_HYP
+
+#define XIP_STATIC static
+
+#endif // PPC_HYP
+
+
+#ifdef DEBUG_SBE_XIP_IMAGE
+
+// Debugging support, normally disabled. All of the formatted I/O you see in
+// the code is effectively under this switch.
+
+#ifdef __FAPI
+
+#include "fapi.H"
+#define fprintf(stream, ...) FAPI_ERR(__VA_ARGS__)
+#define printf(...) FAPI_INF(__VA_ARGS__)
+#define TRACE_NEWLINE ""
+
+#else // __FAPI
+
+#include <stdio.h>
+#define TRACE_NEWLINE "\n"
+
+#endif // __FAPI
+
+// Portable formatting of uint64_t.  The ISO C99 standard requires
+// __STDC_FORMAT_MACROS to be defined in order for PRIx64 etc. to be defined. 
+
+#define __STDC_FORMAT_MACROS
+#include <inttypes.h>
+
+#define F0x016llx "0x%016" PRIx64
+#define F0x012llx "0x%012" PRIx64
+
+XIP_STATIC SBE_XIP_ERROR_STRINGS(sbe_xip_error_strings);
+
+#define TRACE_ERROR(x)                                                  \
+    ({                                                                  \
+        fprintf(stderr, "%s:%d : Returning error code %d : %s" TRACE_NEWLINE, \
+                __FILE__, __LINE__, (x),                                \
+                SBE_XIP_ERROR_STRING(sbe_xip_error_strings, (x)));      \
+        (x);                                                            \
+    })
+
+#define TRACE_ERRORX(x, ...)                    \
+    ({                                          \
+        TRACE_ERROR(x);                         \
+        fprintf(stderr, ##__VA_ARGS__);         \
+        (x);                                    \
+    })
+
+
+// Uncomment these if required for debugging, otherwise we get warnings from
+// GCC as they are not otherwise used.
+
+#if 0
+
+XIP_STATIC uint32_t xipRevLe32(const uint32_t i_x);
+
+XIP_STATIC SBE_XIP_TYPE_STRINGS(type_strings);
+
+XIP_STATIC void
+dumpToc(int index, SbeXipToc* toc)
+{
+    printf("TOC entry %d @ %p\n" 
+           "    iv_id       = 0x%08x\n"
+           "    iv_data     = 0x%08x\n"
+           "    iv_type     = %s\n"
+           "    iv_section  = 0x%02x\n"
+           "    iv_elements = %d\n",
+           index, toc, 
+           xipRevLe32(toc->iv_id), 
+           xipRevLe32(toc->iv_data), 
+           SBE_XIP_TYPE_STRING(type_strings, toc->iv_type), 
+           toc->iv_section, 
+           toc->iv_elements);
+}
+
+#endif
+
+#if 0
+
+XIP_STATIC void
+dumpItem(SbeXipItem* item)
+{
+    printf("SbeXipItem @ %p\n"
+           "    iv_toc       = %p\n"
+           "    iv_address   = " F0x016llx "\n"
+           "    iv_imageData = %p\n"
+           "    iv_id        = %s\n"
+           "    iv_type      = %s\n"
+           "    iv_elements  = %d\n",
+           item,
+           item->iv_toc,
+           item->iv_address,
+           item->iv_imageData,
+           item->iv_id,
+           SBE_XIP_TYPE_STRING(type_strings, item->iv_type),
+           item->iv_elements);
+    dumpToc(-1, item->iv_toc);
+}
+
+#endif  /* 0 */
+
+XIP_STATIC void
+dumpSectionTable(const void* i_image)
+{
+    int i, rc;
+    SbeXipSection section;
+
+    printf("Section table dump of image @ %p\n"
+           "  Entry    Offset        Size\n"
+           "-------------------------------\n",
+           i_image);
+
+    for (i = 0; i < SBE_XIP_SECTIONS; i++) {
+        rc = sbe_xip_get_section(i_image, i, &section);
+        if (rc) {
+            printf(">>> dumpSectionTable got error at entry %d : %s\n",
+                   i, SBE_XIP_ERROR_STRING(sbe_xip_error_strings, rc));
+            break;
+        }
+        printf("%7d  0x%08x  0x%08x\n",
+               i, section.iv_offset, section.iv_size);
+    }
+}
+          
+#else
+
+#define TRACE_ERROR(x) (x)
+#define TRACE_ERRORX(x, ...) (x)
+#define dumpToc(...)
+#define dumpItem(...)
+#define dumpSectionTable(...)
+
+#endif
+
+
+// Note: For maximum flexibility we provide private versions of
+// endian-conversion routines rather than counting on a system-specific header
+// to provide these. 
+
+/// Byte-reverse a 16-bit integer if on a little-endian machine
+
+XIP_STATIC uint16_t
+xipRevLe16(const uint16_t i_x)
+{
+    uint16_t rx;
+
+#ifndef _BIG_ENDIAN
+    uint8_t *pix = (uint8_t*)(&i_x);
+    uint8_t *prx = (uint8_t*)(&rx);
+
+    prx[0] = pix[1];
+    prx[1] = pix[0];
+#else
+    rx = i_x;
+#endif
+
+    return rx;
+}
+
+
+/// Byte-reverse a 32-bit integer if on a little-endian machine
+
+XIP_STATIC uint32_t
+xipRevLe32(const uint32_t i_x)
+{
+    uint32_t rx;
+
+#ifndef _BIG_ENDIAN
+    uint8_t *pix = (uint8_t*)(&i_x);
+    uint8_t *prx = (uint8_t*)(&rx);
+
+    prx[0] = pix[3];
+    prx[1] = pix[2];
+    prx[2] = pix[1];
+    prx[3] = pix[0];
+#else
+    rx = i_x;
+#endif
+
+    return rx;
+}
+
+
+/// Byte-reverse a 64-bit integer if on a little-endian machine
+
+XIP_STATIC uint64_t
+xipRevLe64(const uint64_t i_x)
+{
+    uint64_t rx;
+
+#ifndef _BIG_ENDIAN
+    uint8_t *pix = (uint8_t*)(&i_x);
+    uint8_t *prx = (uint8_t*)(&rx);
+
+    prx[0] = pix[7];
+    prx[1] = pix[6];
+    prx[2] = pix[5];
+    prx[3] = pix[4];
+    prx[4] = pix[3];
+    prx[5] = pix[2];
+    prx[6] = pix[1];
+    prx[7] = pix[0];
+#else
+    rx = i_x;
+#endif
+
+    return rx;
+}
+
+
+/// What is the image link address?
+
+XIP_STATIC uint64_t
+xipLinkAddress(const void* i_image)
+{
+    return xipRevLe64(((SbeXipHeader*)i_image)->iv_linkAddress);
+}
+
+
+/// What is the image size?
+
+XIP_STATIC uint32_t
+xipImageSize(const void* i_image)
+{
+    return xipRevLe32(((SbeXipHeader*)i_image)->iv_imageSize);
+}
+
+
+/// Set the image size
+
+XIP_STATIC void
+xipSetImageSize(void* io_image, const size_t i_size)
+{
+    ((SbeXipHeader*)io_image)->iv_imageSize = xipRevLe32(i_size);
+}
+
+
+/// Re-establish the required final alignment
+
+XIP_STATIC void
+xipFinalAlignment(void* io_image)
+{
+    uint32_t size;
+
+    size = xipImageSize(io_image);
+
+    if ((size % SBE_XIP_FINAL_ALIGNMENT) != 0) {
+        xipSetImageSize(io_image, 
+                        size + (SBE_XIP_FINAL_ALIGNMENT -
+                                (size % SBE_XIP_FINAL_ALIGNMENT)));
+    }
+}
+
+
+/// Compute a host address from an image address and offset
+
+XIP_STATIC void*
+xipHostAddressFromOffset(const void* i_image, const uint32_t offset)
+{
+    return (void*)((unsigned long)i_image + offset);
+}
+
+
+/// Convert a IMAGE address to a host address
+
+XIP_STATIC void*
+xipImage2Host(const void* i_image, const uint64_t i_imageAddress)
+{
+    return xipHostAddressFromOffset(i_image, 
+                                    i_imageAddress - xipLinkAddress(i_image));
+}
+
+
+XIP_STATIC int
+xipValidateImageAddress(const void* i_image, 
+                       const uint64_t i_imageAddress, 
+                       const uint32_t size)
+{
+    int rc;
+
+    if ((i_imageAddress < xipLinkAddress(i_image)) ||
+        (i_imageAddress > (xipLinkAddress(i_image) + 
+                          xipImageSize(i_image) - 
+                          size))) {
+        rc = TRACE_ERRORX(SBE_XIP_INVALID_ARGUMENT,
+                          "The IMAGE address " F0x012llx 
+                          " is outside the bounds "
+                          "of the image (" 
+                          F0x012llx ":" F0x012llx 
+                          ") for %u-byte access.\n",
+                          i_imageAddress,
+                          xipLinkAddress(i_image),
+                          xipLinkAddress(i_image) + xipImageSize(i_image) - 1,
+                          size);
+    } else {
+        rc = 0;
+    }
+    return rc;
+}
+
+
+/// Get the magic number from the image
+
+XIP_STATIC uint64_t
+xipMagic(const void* i_image)
+{
+    return xipRevLe64(((SbeXipHeader*)i_image)->iv_magic);
+}
+
+
+/// Get the header version from the image
+
+XIP_STATIC uint8_t
+xipHeaderVersion(const void* i_image)
+{
+    return ((SbeXipHeader*)i_image)->iv_headerVersion;
+}
+
+
+/// Has the image been normalized?
+
+XIP_STATIC uint8_t
+xipNormalized(const void* i_image)
+{
+    return ((SbeXipHeader*)i_image)->iv_normalized;
+}
+
+
+/// Has the image TOC been sorted?
+
+XIP_STATIC uint8_t
+xipSorted(const void* i_image)
+{
+    return ((SbeXipHeader*)i_image)->iv_tocSorted;
+}
+
+
+/// A quick check that the image exists, has the correct magic and header
+/// version, and optionally is normalized.
+
+XIP_STATIC int 
+xipQuickCheck(const void* i_image, const int i_normalizationRequired)
+{
+    int rc;
+
+    do {
+        rc = 0;
+
+        if (i_image == 0) {
+            rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR, 
+                              "Image pointer is NULL (0)\n");
+            break;
+        }
+        if ((xipMagic(i_image) >> 32) != SBE_XIP_MAGIC) {
+            rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
+                              "Magic number mismatch; Found "
+                              "" F0x016llx ", expected 0x%08x........\n",
+                              xipMagic(i_image), SBE_XIP_MAGIC);
+            break;
+        }
+        if ((xipHeaderVersion(i_image)) != SBE_XIP_HEADER_VERSION) {
+            rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
+                              "Header version mismatch; Expecting %d, "
+                              "found %d\n",
+                              SBE_XIP_HEADER_VERSION, 
+                              xipHeaderVersion(i_image));
+            break;
+        }
+        if (i_normalizationRequired && !xipNormalized(i_image)) {
+            rc = TRACE_ERRORX(SBE_XIP_NOT_NORMALIZED,
+                              "Image not normalized\n");
+            break;
+        }
+    } while(0);
+
+    return rc;
+}
+
+
+/// Convert a 32-bit relocatable offset to a full IMAGE 48-bit address
+
+XIP_STATIC uint64_t 
+xipFullAddress(const void* i_image, uint32_t offset)
+{
+    return (xipLinkAddress(i_image) & 0x0000ffff00000000ull) + offset;
+}
+
+
+/// Translate a section table entry
+ 
+XIP_STATIC void
+xipTranslateSection(SbeXipSection* o_dest, const SbeXipSection* i_src)
+{
+#ifndef _BIG_ENDIAN
+
+#if SBE_XIP_HEADER_VERSION != 8
+#error This code assumes the SBE-XIP header version 8 layout
+#endif
+
+    o_dest->iv_offset = xipRevLe32(i_src->iv_offset);
+    o_dest->iv_size = xipRevLe32(i_src->iv_size);
+    o_dest->iv_alignment = i_src->iv_alignment;
+    o_dest->iv_reserved8[0] = 0;
+    o_dest->iv_reserved8[1] = 0;
+    o_dest->iv_reserved8[2] = 0;
+#else
+    if (o_dest != i_src) {
+        *o_dest = *i_src;
+    }
+#endif  /* _BIG_ENDIAN */
+}    
+
+
+/// Translate a TOC entry
+
+XIP_STATIC void
+xipTranslateToc(SbeXipToc* o_dest, SbeXipToc* i_src)
+{
+#ifndef _BIG_ENDIAN
+
+#if SBE_XIP_HEADER_VERSION != 8
+#error This code assumes the SBE-XIP header version 8 layout
+#endif
+
+    o_dest->iv_id = xipRevLe32(i_src->iv_id);
+    o_dest->iv_data = xipRevLe32(i_src->iv_data);
+    o_dest->iv_type = i_src->iv_type;
+    o_dest->iv_section = i_src->iv_section;
+    o_dest->iv_elements = i_src->iv_elements;
+    o_dest->iv_pad = 0;
+#else
+    if (o_dest != i_src) {
+        *o_dest = *i_src;
+    }
+#endif  /* _BIG_ENDIAN */
+}
+
+
+/// Find the final (highest-address) section of the image
+
+XIP_STATIC int
+xipFinalSection(const void* i_image, int* o_sectionId)
+{
+    int i, rc, found;
+    uint32_t offset;
+    SbeXipHeader hostHeader;
+    
+    sbe_xip_translate_header(&hostHeader, (SbeXipHeader*)i_image);
+
+    found = 0;
+    offset = 0;
+    *o_sectionId = 0;           /* Make GCC -O3 happy */
+    for (i = 0; i < SBE_XIP_SECTIONS; i++) {
+        if ((hostHeader.iv_section[i].iv_size != 0) && 
+            (hostHeader.iv_section[i].iv_offset >= offset)) {
+            *o_sectionId = i;
+            offset = hostHeader.iv_section[i].iv_offset;
+            found = 1;
+        }
+    }
+    if (!found) {
+        rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR, "The image is empty\n");
+    } else {
+        rc = 0;
+    }
+    return rc;
+}
+
+
+/// Return a pointer to an image-format section table entry
+
+XIP_STATIC int
+xipGetSectionPointer(const void* i_image,
+                     const int i_sectionId,
+                     SbeXipSection** o_imageSection)
+{
+    int rc;
+
+    if ((i_sectionId < 0) || (i_sectionId >= SBE_XIP_SECTIONS)) {
+        rc = TRACE_ERROR(SBE_XIP_INVALID_ARGUMENT);
+    } else {
+        *o_imageSection = 
+            &(((SbeXipHeader*)i_image)->iv_section[i_sectionId]);
+        rc = 0;
+    }
+    return rc;
+}
+
+
+/// Restore a section table entry from host format to image format.
+
+XIP_STATIC int
+xipPutSection(const void* i_image,
+              const int i_sectionId,
+              SbeXipSection* i_hostSection)
+{
+    int rc;
+    SbeXipSection *imageSection;
+
+    rc = xipGetSectionPointer(i_image, i_sectionId, &imageSection);
+
+    if (!rc) {
+        xipTranslateSection(imageSection, i_hostSection);
+    }
+
+    return rc;
+}
+
+
+/// Set the offset of a section
+
+XIP_STATIC int
+xipSetSectionOffset(void* io_image, const int i_section, 
+                    const uint32_t i_offset)
+{
+    SbeXipSection* section;
+    int rc;
+
+    rc = xipGetSectionPointer(io_image, i_section, &section);
+    if (!rc) {
+        section->iv_offset = xipRevLe32(i_offset);
+    }
+    return rc;
+}
+
+
+/// Set the size of a section
+
+XIP_STATIC int
+xipSetSectionSize(void* io_image, const int i_section, const uint32_t i_size)
+{
+    SbeXipSection* section;
+    int rc;
+
+    rc = xipGetSectionPointer(io_image, i_section, &section);
+    if (!rc) {
+        section->iv_size = xipRevLe32(i_size);
+    }
+    return rc;
+}
+
+
+/// Translate a IMAGE address in the image to a section and offset
+
+// We first check to be sure that the IMAGE address is contained in the image,
+// using the full 48-bit form.  Then we scan the section table to see which
+// section contains the address - if none then the image is corrupted. We can
+// (must) use the 32-bit offset form of the address here.
+
+XIP_STATIC int
+xipImage2Section(const void* i_image, 
+                const uint64_t i_imageAddress,
+                int* o_section,
+                uint32_t* o_offset)
+{
+    int rc, sectionId;
+    SbeXipSection section;
+    uint32_t addressOffset;
+
+    do {
+        rc = 0;
+
+        if ((i_imageAddress < xipLinkAddress(i_image)) ||
+            (i_imageAddress > 
+             (xipLinkAddress(i_image) + xipImageSize(i_image)))) {
+            rc = TRACE_ERRORX(SBE_XIP_INVALID_ARGUMENT,
+                              "image2section: The i_imageAddress argument "
+                              "(" F0x016llx ")\nis outside the bounds of the "
+                              "image (" F0x016llx ":" F0x016llx ")\n",
+                              i_imageAddress,
+                              xipLinkAddress(i_image),
+                              xipLinkAddress(i_image) + xipImageSize(i_image));
+            break;
+        }
+
+        addressOffset = (i_imageAddress - xipLinkAddress(i_image)) & 0xffffffff;
+
+        for (sectionId = 0; sectionId < SBE_XIP_SECTIONS; sectionId++) {
+            rc = sbe_xip_get_section(i_image, sectionId, &section);
+            if (rc) {
+                rc = TRACE_ERROR(SBE_XIP_BUG); /* Can't happen */
+                break;
+            }
+            if ((section.iv_size != 0) &&
+                (addressOffset >= section.iv_offset) &&
+                (addressOffset < (section.iv_offset + section.iv_size))) {
+                break;
+            }
+        }
+        if (rc) break;
+
+        if (sectionId == SBE_XIP_SECTIONS) {
+            rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
+                              "Error processing IMAGE address " F0x016llx ". "
+                              "The address is not mapped in any section.\n"
+                              "A section table dump appears below\n",
+                              i_imageAddress);
+            dumpSectionTable(i_image);
+            break;
+        }
+
+        *o_section = sectionId;
+        *o_offset = addressOffset - section.iv_offset;
+
+    } while(0);
+
+    return rc;
+}
+
+
+/// Get the information required to search the TOC.  
+///
+/// All return values are optional.
+
+XIP_STATIC int
+xipGetToc(void* i_image,
+          SbeXipToc** o_toc,
+          size_t* o_entries,
+          int* o_sorted,
+          char** o_strings)
+{
+    int rc;
+    SbeXipSection tocSection, stringsSection;
+
+    do {
+        rc = sbe_xip_get_section(i_image, SBE_XIP_SECTION_TOC, &tocSection);
+        if (rc) break;
+
+        rc = sbe_xip_get_section(i_image, SBE_XIP_SECTION_STRINGS,
+                                 &stringsSection);
+        if (rc) break;
+
+        if (o_toc) {
+            *o_toc = (SbeXipToc*)((uint8_t*)i_image + tocSection.iv_offset);
+        }
+        if (o_entries) {
+            *o_entries = tocSection.iv_size / sizeof(SbeXipToc);
+        }
+        if (o_sorted) {
+            *o_sorted = xipSorted(i_image);
+        }
+        if (o_strings) {
+            *o_strings = (char*)i_image + stringsSection.iv_offset;
+        }
+    } while (0);
+    return rc;
+}
+
+
+/// Compare two normalized TOC entries for sorting.
+
+XIP_STATIC int
+xipCompareToc(const SbeXipToc* i_a, const SbeXipToc* i_b, 
+              const char* i_strings)
+{
+    return strcmp(i_strings + xipRevLe32(i_a->iv_id),
+                  i_strings + xipRevLe32(i_b->iv_id));
+}
+
+
+/// Iterative quicksort of the TOC
+
+// Note: The stack requirement is limited to 256 bytes + minor local storage.
+
+XIP_STATIC void
+xipQuickSort(SbeXipToc* io_toc, int i_left, int i_right,
+             const char* i_strings)
+{
+    int i, j, left, right, sp;
+    SbeXipToc pivot, temp;
+    uint32_t stack[64];
+
+    sp = 0;
+    stack[sp++] = i_left;
+    stack[sp++] = i_right;
+
+    while (sp) {
+
+        right = stack[--sp];
+        left = stack[--sp];
+
+        i = left;
+        j = right;
+
+        pivot = io_toc[(i + j) / 2];
+
+        while (i <= j) {
+            while (xipCompareToc(&(io_toc[i]), &pivot, i_strings) < 0) {
+                i++;
+            }
+            while (xipCompareToc(&(io_toc[j]), &pivot, i_strings) > 0) {
+                j--;
+            }
+            if (i <= j) {
+                temp = io_toc[i];
+                io_toc[i] = io_toc[j];
+                io_toc[j] = temp;
+                i++;
+                j--;
+            }
+        }
+        if (left < j) {
+            stack[sp++] = left;
+            stack[sp++] = j;
+        }
+        if (i < right) {
+            stack[sp++] = i;
+            stack[sp++] = right;
+        }
+    }
+}
+
+
+/// TOC linear search
+
+XIP_STATIC int
+xipLinearSearch(void* i_image, const char* i_id, SbeXipToc** o_entry)
+{
+    int rc;
+    SbeXipToc *imageToc, hostToc;
+    size_t entries;
+    char* strings;
+
+    *o_entry = 0;
+    rc = xipGetToc(i_image, &imageToc, &entries, 0, &strings);
+    if (!rc) {
+        for (; entries; entries--, imageToc++) {
+            xipTranslateToc(&hostToc, imageToc);
+            if (strcmp(i_id, strings + hostToc.iv_id) == 0) {
+                break;
+            }
+        }
+        if (entries) {
+            *o_entry = imageToc;
+            rc = 0;
+        } else {
+            *o_entry = 0;
+            rc = TRACE_ERROR(SBE_XIP_ITEM_NOT_FOUND);
+        }
+    }
+    return rc;
+}
+
+
+/// A classic binary search of a (presumed) sorted array
+
+XIP_STATIC int
+xipBinarySearch(void* i_image, const char* i_id, SbeXipToc** o_entry)
+{
+    int rc;
+    SbeXipToc *imageToc;
+    size_t entries;
+    char* strings;
+    int sorted, left, right, next, sort;
+
+    do {
+        *o_entry = 0;
+
+        rc = xipGetToc(i_image, &imageToc, &entries, &sorted, &strings);
+        if (rc) break;
+
+        if (!sorted) {
+            rc = TRACE_ERROR(SBE_XIP_BUG);
+            break;
+        }
+
+        left = 0;
+        right = entries - 1;
+        while (left <= right) {
+            next = (left + right) / 2;
+            sort = strcmp(i_id, strings + xipRevLe32(imageToc[next].iv_id));
+            if (sort == 0) {
+                *o_entry = &(imageToc[next]);
+                break;
+            } else if (sort < 0) {
+                right = next - 1;
+            } else {
+                left = next + 1;
+            }
+        }
+        if (*o_entry == 0) {
+            rc = TRACE_ERROR(SBE_XIP_ITEM_NOT_FOUND);
+            break;
+        }
+    } while (0);
+    return rc;
+}
+
+
+/// Validate a TOC entry as a mapping function
+///
+/// The TOC is validated by searching for the entry, which will uncover
+/// duplicate entries or problems with sorting/searching.
+
+XIP_STATIC int
+xipValidateTocEntry(void* io_image, const SbeXipItem* i_item, void* io_arg)
+{
+    int rc;
+    SbeXipItem found;
+
+    do {
+        rc = sbe_xip_find(io_image, i_item->iv_id, &found);
+        if (rc) {
+            rc = TRACE_ERRORX(rc, "TOC entry for %s not found\n", 
+                              i_item->iv_id);
+        } else if (found.iv_toc != i_item->iv_toc) {
+            rc = TRACE_ERRORX(SBE_XIP_TOC_ERROR,
+                              "Duplicate TOC entry for '%s'\n", i_item->iv_id);
+        }
+        break;
+    } while (0);
+    return rc;
+}
+    
+
+// This is the FNV-1a hash, used for hashing symbol names in the .fixed
+// section into 32-bit hashes for the mini-TOC.
+
+// According to the authors:
+
+// "FNV hash algorithms and source code have been released into the public
+// domain. The authors of the FNV algorithmm look deliberate steps to disclose
+// the algorhtm (sic) in a public forum soon after it was invented. More than
+// a year passed after this public disclosure and the authors deliberatly took
+// no steps to patent the FNV algorithm. Therefore it is safe to say that the
+// FNV authors have no patent claims on the FNV algorithm as published."
+
+#define FNV_OFFSET_BASIS 2166136261u
+#define FNV_PRIME32 16777619u
+
+uint32_t
+xipHash32(const char* s) 
+{
+    uint32_t hash;
+
+    hash = FNV_OFFSET_BASIS;
+    while (*s) {
+        hash ^= *s++;
+        hash *= FNV_PRIME32;
+    }
+    return hash;
+}
+
+
+// Normalize a TOC entry
+
+// Normalize the TOC entry by converting relocatable pointers into 32-bit
+// offsets from the beginning of the section containing the data. All
+// addresses in the TOC are actually 32-bit offsets in the address space named
+// in bits 16:31 of the link address of the image.
+
+XIP_STATIC int
+xipNormalizeToc(void* io_image, SbeXipToc *io_imageToc,
+                SbeXipHashedToc** io_fixedTocEntry,
+                size_t* io_fixedEntriesRemaining)
+{
+    SbeXipToc hostToc;
+    int idSection, dataSection;
+    uint32_t idOffset, dataOffset;
+    char* hostString;
+    int rc;
+
+    do {
+
+        // Translate the TOC entry to host format.  Then locate the
+        // sections/offsets of the Id string (which must be in .strings) and
+        // the data.
+
+        xipTranslateToc(&hostToc, io_imageToc);
+
+        hostString = 
+            (char*)xipImage2Host(io_image, 
+                                xipFullAddress(io_image, hostToc.iv_id));
+
+        rc = xipImage2Section(io_image,
+                             xipFullAddress(io_image, hostToc.iv_id),
+                             &idSection,
+                             &idOffset);
+        if (rc) break;
+
+        if (idSection != SBE_XIP_SECTION_STRINGS) {
+            rc = TRACE_ERROR(SBE_XIP_IMAGE_ERROR);
+            break;
+        }
+
+        rc = xipImage2Section(io_image,
+                             xipFullAddress(io_image, hostToc.iv_data),
+                             &dataSection,
+                             &dataOffset);
+        if (rc) break;
+
+        // Now replace the Id and data pointers with their offsets, and update
+        // the data section in the TOC entry.
+
+        hostToc.iv_id = idOffset;
+        hostToc.iv_data = dataOffset;
+        hostToc.iv_section = dataSection;
+
+        // If this TOC entry is from .fixed, create a new record in .fixed_toc
+
+        if (hostToc.iv_section == SBE_XIP_SECTION_FIXED) {
+
+            if (*io_fixedEntriesRemaining == 0) {
+                rc = TRACE_ERRORX(SBE_XIP_TOC_ERROR,
+                                  "Too many TOC entries for .fixed\n");
+                break;
+            }
+            if (hostToc.iv_data != (uint16_t)hostToc.iv_data) {
+                rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
+                                  "The .fixed section is too big to index\n");
+                break;
+            }
+
+            (*io_fixedTocEntry)->iv_hash = xipRevLe32(xipHash32(hostString));
+            (*io_fixedTocEntry)->iv_offset = xipRevLe16(hostToc.iv_data);
+            (*io_fixedTocEntry)->iv_type = hostToc.iv_type;
+            (*io_fixedTocEntry)->iv_elements = hostToc.iv_elements;
+            
+            (*io_fixedTocEntry)++;
+            (*io_fixedEntriesRemaining)--;
+        }            
+
+        // Finally update the TOC entry
+
+        xipTranslateToc(io_imageToc, &hostToc);
+
+    } while (0);
+
+    return rc;
+}
+
+
+// Check for hash collisions in the .fixed mini-TOC.  Note that endianness is
+// not an issue here, as we're comparing for equality.
+
+XIP_STATIC int
+xipHashCollision(SbeXipHashedToc* i_fixedToc, size_t i_entries)
+{
+    int rc;
+    size_t i, j;
+
+    rc = 0;
+
+    for (i = 0; i < i_entries; i++) {
+        for (j = i + 1; j < i_entries; j++) {
+            if (i_fixedToc[i].iv_hash == i_fixedToc[j].iv_hash) {
+                rc = TRACE_ERRORX(SBE_XIP_HASH_COLLISION,
+                                  "Hash collision at index %d\n",
+                                  i);
+                break;
+            }
+        }
+        if (rc) break;
+    }
+    
+    return rc;
+}
+
+
+/// Decode a normalized image-format TOC entry into a host-format SbeXipItem
+/// structure
+
+XIP_STATIC int
+xipDecodeToc(void* i_image, 
+             SbeXipToc* i_imageToc, 
+             SbeXipItem* o_item)
+{
+    int rc;
+    SbeXipToc hostToc;
+    SbeXipSection dataSection, stringsSection;
+
+    do {
+        if (!xipNormalized(i_image)) {
+            rc = TRACE_ERROR(SBE_XIP_NOT_NORMALIZED);
+            break;
+        }
+
+
+        // Translate the TOC entry and set the TOC pointer, data type and
+        // number of elements in the outgoing structure. The Id string is
+        // always located in the TOC_STRINGS section.
+
+        xipTranslateToc(&hostToc, i_imageToc);
+
+        o_item->iv_toc = i_imageToc;
+        o_item->iv_type = hostToc.iv_type;
+        o_item->iv_elements = hostToc.iv_elements;
+    
+        sbe_xip_get_section(i_image, SBE_XIP_SECTION_STRINGS, &stringsSection);
+        o_item->iv_id = 
+            (char*)i_image + stringsSection.iv_offset + hostToc.iv_id;
+        
+
+        // The data (or text address) are addressed by relative offsets from
+        // the beginning of their section.  The TOC entry may remain in the TOC
+        // even though the section has been removed from the image, so this
+        // case needs to be covered. 
+        
+        rc = sbe_xip_get_section(i_image, hostToc.iv_section, &dataSection);
+        if (rc) break;
+
+        if (dataSection.iv_size == 0) {
+            rc = TRACE_ERROR(SBE_XIP_DATA_NOT_PRESENT);
+            break;
+        }
+
+        o_item->iv_imageData = 
+            (void*)((uint8_t*)i_image + 
+                    dataSection.iv_offset + hostToc.iv_data);
+
+        o_item->iv_address = 
+            xipLinkAddress(i_image) + dataSection.iv_offset + hostToc.iv_data;
+
+        o_item->iv_partial = 0;
+            
+    } while (0);
+    return rc;
+}    
+
+
+/// Sort the TOC
+
+XIP_STATIC int
+xipSortToc(void* io_image)
+{
+    int rc;
+    SbeXipToc *hostToc;
+    size_t entries;
+    char* strings;
+
+    do {
+        rc = xipQuickCheck(io_image, 1);
+        if (rc) break;
+
+        if (xipSorted(io_image)) break;
+
+        rc = xipGetToc(io_image, &hostToc, &entries, 0, &strings);
+        if (rc) break;
+
+        xipQuickSort(hostToc, 0, entries - 1, strings);
+
+        ((SbeXipHeader*)io_image)->iv_tocSorted = 1;
+        
+    } while (0);
+
+    return rc;
+}
+
+
+// Pad the image with 0 to a given power-of-2 alignment.  The image size is
+// modified to reflect the pad, but the caller must modify the section size to
+// reflect the pad.
+
+XIP_STATIC int
+xipPadImage(void* io_image, uint32_t i_allocation, 
+            uint32_t i_align, uint32_t* pad)
+{
+    int rc;
+
+    do {
+        rc = 0;
+
+        if ((i_align == 0) || ((i_align & (i_align - 1)) != 0)) {
+            rc = TRACE_ERRORX(SBE_XIP_INVALID_ARGUMENT,
+                              "Alignment specification (%u) "
+                              "not a power-of-2\n",
+                              i_align);
+            break;
+        }
+
+        *pad = xipImageSize(io_image) % i_align;
+        if (*pad != 0) {
+            *pad = i_align - *pad;
+
+            if ((xipImageSize(io_image) + *pad) > i_allocation) {
+                rc = TRACE_ERROR(SBE_XIP_WOULD_OVERFLOW);
+                break;
+            }
+
+            memset((void*)((unsigned long)io_image + xipImageSize(io_image)), 
+                   0, *pad);
+            xipSetImageSize(io_image, xipImageSize(io_image) + *pad);
+        }
+    } while (0);
+
+    return rc;
+}
+
+
+//  Get the .fixed_toc section
+
+XIP_STATIC int
+xipGetFixedToc(void* io_image, 
+               SbeXipHashedToc** o_imageToc, 
+               size_t* o_entries)
+{
+    int rc;
+    SbeXipSection section;
+
+    rc = sbe_xip_get_section(io_image, SBE_XIP_SECTION_FIXED_TOC, &section);
+    if (!rc) {
+
+        *o_imageToc = 
+            (SbeXipHashedToc*)((unsigned long)io_image + section.iv_offset);  
+
+        *o_entries = section.iv_size / sizeof(SbeXipHashedToc);
+    }
+
+    return rc;
+}
+
+
+// Search for an item in the fixed TOC, and populate a partial TOC entry if
+// requested. This table is small and unsorted so a linear search is
+// adequate. The TOC structures are also small so all byte-reversal is done
+// 'by hand' rather than with a translate-type API.
+
+XIP_STATIC int
+xipFixedFind(void* i_image, const char* i_id, SbeXipItem* o_item)
+{
+    int rc;
+    SbeXipHashedToc* toc;
+    size_t entries;
+    uint32_t hash;
+    SbeXipSection fixedSection;
+    uint32_t offset;
+
+    do {
+        rc = xipGetFixedToc(i_image, &toc, &entries);
+        if (rc) break;
+
+        for (hash = xipRevLe32(xipHash32(i_id)); entries != 0; entries--, toc++) {
+            if (toc->iv_hash == hash) break;
+        }
+
+        if (entries == 0) {
+            rc = SBE_XIP_ITEM_NOT_FOUND;
+            break;
+        } else {
+            rc = 0;
+        }
+
+        // The caller may have requested a lookup only (o_item == 0), in which
+        // case we're done.  Otherwise we create a partial SbeXipItem and
+        // populate the non-0 fields analogously to the xipDecodeToc()
+        // routine. The data resides in the .fixed section in this case.
+
+        if (o_item == 0) break;
+
+        o_item->iv_partial = 1;
+        o_item->iv_toc = 0;
+        o_item->iv_id = 0;
+
+        o_item->iv_type = toc->iv_type;
+        o_item->iv_elements = toc->iv_elements;
+
+        rc = sbe_xip_get_section(i_image, SBE_XIP_SECTION_FIXED, &fixedSection);
+        if (rc) break;
+
+        if (fixedSection.iv_size == 0) {
+            rc = TRACE_ERROR(SBE_XIP_DATA_NOT_PRESENT);
+            break;
+        }
+
+        offset = fixedSection.iv_offset + xipRevLe16(toc->iv_offset);
+
+        o_item->iv_imageData = (void*)((uint8_t*)i_image + offset);
+        o_item->iv_address = xipLinkAddress(i_image) + offset;
+
+    } while (0);
+
+    return rc;
+}
+
+
+// Search for an item in the special built-in TOC of header fields, and
+// populate a partial TOC entry if requested. 
+//
+// This facility was added to allow header data to be searched by name even
+// when the TOC has been stripped. This API will only be used in the case of a
+// stripped TOC since the header fields are also indexed in the main TOC.
+//
+// The table is allocated on the stack in order to make this code concurrently
+// patchable in PHYP (although PHYP applications will never use this code).
+// The table is small and unsorted so a linear search is adequate, and the
+// stack requirememts are small.
+
+XIP_STATIC int
+xipHeaderFind(void* i_image, const char* i_id, SbeXipItem* o_item)
+{
+    int rc;
+    unsigned i;
+    uint32_t offset;
+    SbeXipSection headerSection;
+
+#define HEADER_TOC(id, field, type)             \
+    {#id, offsetof(SbeXipHeader, field), type}
+
+    struct HeaderToc {
+
+        const char* iv_id;
+        uint16_t iv_offset;
+        uint8_t iv_type;
+
+    } toc[] = {
+
+        HEADER_TOC(magic,        iv_magic,       SBE_XIP_UINT64),
+        HEADER_TOC(entry_offset, iv_entryOffset, SBE_XIP_UINT64),
+        HEADER_TOC(link_address, iv_linkAddress, SBE_XIP_UINT64),
+
+        HEADER_TOC(image_size, iv_imageSize, SBE_XIP_UINT32),
+        HEADER_TOC(build_date, iv_buildDate, SBE_XIP_UINT32),
+        HEADER_TOC(build_time, iv_buildTime, SBE_XIP_UINT32),
+
+        HEADER_TOC(header_version, iv_headerVersion, SBE_XIP_UINT8),
+        HEADER_TOC(toc_normalized, iv_normalized,    SBE_XIP_UINT8),
+        HEADER_TOC(toc_sorted,     iv_tocSorted,     SBE_XIP_UINT8),
+
+        HEADER_TOC(build_user, iv_buildUser, SBE_XIP_STRING),
+        HEADER_TOC(build_host, iv_buildHost, SBE_XIP_STRING),
+
+    };
+
+    do {
+
+        rc = SBE_XIP_ITEM_NOT_FOUND;
+        for (i = 0; i < (sizeof(toc) / sizeof(struct HeaderToc)); i++) {
+            if (strcmp(i_id, toc[i].iv_id) == 0) {
+                rc = 0;
+                break;
+            }
+        }
+
+        if (rc) break;
+
+        // The caller may have requested a lookup only (o_item == 0), in which
+        // case we're done.  Otherwise we create a partial SbeXipItem and
+        // populate the non-0 fields analogously to the xipDecodeToc()
+        // routine. The data resides in the .fixed section in this case.
+
+        if (o_item == 0) break;
+
+        o_item->iv_partial = 1;
+        o_item->iv_toc = 0;
+        o_item->iv_id = 0;
+
+        o_item->iv_type = toc[i].iv_type;
+        o_item->iv_elements = 1; /* True for now... */
+
+        rc = sbe_xip_get_section(i_image, SBE_XIP_SECTION_HEADER, 
+                                 &headerSection);
+        if (rc) break;
+
+        if (headerSection.iv_size == 0) {
+            rc = TRACE_ERROR(SBE_XIP_DATA_NOT_PRESENT);
+            break;
+        }
+
+        offset = headerSection.iv_offset + toc[i].iv_offset;
+
+        o_item->iv_imageData = (void*)((uint8_t*)i_image + offset);
+        o_item->iv_address = xipLinkAddress(i_image) + offset;
+
+    } while (0);
+
+    return rc;
+}
+        
+
+////////////////////////////////////////////////////////////////////////////
+// Published API
+////////////////////////////////////////////////////////////////////////////
+
+int
+sbe_xip_validate(void* i_image, const uint32_t i_size)
+{          
+    SbeXipHeader hostHeader;
+    int rc = 0, i;
+    uint32_t linkAddress, imageSize, extent, offset, size;
+    uint8_t alignment;
+
+    sbe_xip_translate_header(&hostHeader, (SbeXipHeader*)i_image);
+
+    do {
+        
+        // Validate C/Assembler constraints.
+
+        if (sizeof(SbeXipSection) != SIZE_OF_SBE_XIP_SECTION) {
+            rc = TRACE_ERRORX(SBE_XIP_BUG,
+                              "C/Assembler size mismatch(%d/%d) "
+                              "for SbeXipSection\n",
+                              sizeof(SbeXipSection), SIZE_OF_SBE_XIP_SECTION);
+            break;
+        }
+                              
+        if (sizeof(SbeXipToc) != SIZE_OF_SBE_XIP_TOC) {
+            rc = TRACE_ERRORX(SBE_XIP_BUG,
+                              "C/Assembler size mismatch(%d/%d) "
+                              "for SbeXipToc\n",
+                              sizeof(SbeXipToc), SIZE_OF_SBE_XIP_TOC);
+            break;
+        }
+
+        if (sizeof(SbeXipHashedToc) != SIZE_OF_SBE_XIP_HASHED_TOC) {
+            rc = TRACE_ERRORX(SBE_XIP_BUG,
+                              "C/Assembler size mismatch(%d/%d) "
+                              "for SbeXipHashedToc\n",
+                              sizeof(SbeXipHashedToc), 
+                              SIZE_OF_SBE_XIP_HASHED_TOC);
+            break;
+        }
+
+        // Validate the image pointer and magic number
+
+        rc = xipQuickCheck(i_image, 0);
+        if (rc) break;
+
+        // Validate the image size
+
+        linkAddress = hostHeader.iv_linkAddress;
+        imageSize = hostHeader.iv_imageSize;
+        extent = linkAddress + imageSize;
+
+        if (imageSize < sizeof(SbeXipHeader)) {
+            rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
+                              "sbe_xip_validate(%p, %u) : "
+                              "The image size recorded in the image "
+                              "(%u) is smaller than the header size.\n",
+                              i_image, i_size, imageSize);
+            break;
+        }
+        if (imageSize != i_size) {
+            rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
+                              "sbe_xip_validate(%p, %u) : "
+                              "The image size recorded in the image "
+                              "(%u) does not match the i_size parameter.\n",
+                              i_image, i_size, imageSize);
+            break;
+        }
+        if (extent <= linkAddress) {
+            rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
+                              "sbe_xip_validate(%p, %u) : "
+                              "Given the link address (%u) and the "
+                              "image size, the image wraps the address space\n",
+                              i_image, i_size, linkAddress);
+            break;
+        }
+        if ((imageSize % SBE_XIP_FINAL_ALIGNMENT) != 0) {
+            rc = TRACE_ERRORX(SBE_XIP_ALIGNMENT_ERROR,
+                              "sbe_xip_validate(%p, %u) : "
+                              "The image size (%u) is not a multiple of %u\n",
+                              i_image, i_size, imageSize, 
+                              SBE_XIP_FINAL_ALIGNMENT);
+            break;
+        }
+
+        // Validate that all sections appear to be within the image
+        // bounds, and are aligned correctly.
+
+        for (i = 0; i < SBE_XIP_SECTIONS; i++) {
+
+            offset = hostHeader.iv_section[i].iv_offset;
+            size = hostHeader.iv_section[i].iv_size;
+            alignment = hostHeader.iv_section[i].iv_alignment;
+
+            if ((offset > imageSize) || 
+                ((offset + size) > imageSize) ||
+                ((offset + size) < offset)) {
+                rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
+                                  "Section %d does not appear to be within "
+                                  "the bounds of the image\n"
+                                  "offset = %u, size = %u, image size = %u\n",
+                                  i, offset, size, imageSize);
+                break;
+            }
+            if ((offset % alignment) != 0) {
+                rc = TRACE_ERRORX(SBE_XIP_ALIGNMENT_ERROR,
+                                  "Section %d requires %d-byte initial "
+                                  "alignment but the section offset is %u\n",
+                                  i, alignment, offset);
+                break;
+            }
+        }
+        if (rc) break;
+
+        // If the TOC exists and the image is normalized, validate each TOC
+        // entry. 
+
+        size = hostHeader.iv_section[SBE_XIP_SECTION_TOC].iv_size; 
+        if (size != 0) {
+            if (xipNormalized(i_image)) {
+                rc = sbe_xip_map_toc(i_image, xipValidateTocEntry, 0);
+                if (rc) break;
+            }
+        }
+    } while (0);
+    return rc;
+}
+
+
+int
+sbe_xip_validate2(void* i_image, const uint32_t i_size, const uint32_t i_maskIgnores)
+{          
+    SbeXipHeader hostHeader;
+    int rc = 0, i;
+    uint32_t linkAddress, imageSize, extent, offset, size;
+    uint8_t alignment;
+
+    sbe_xip_translate_header(&hostHeader, (SbeXipHeader*)i_image);
+
+    do {
+        
+        // Validate C/Assembler constraints.
+
+        if (sizeof(SbeXipSection) != SIZE_OF_SBE_XIP_SECTION) {
+            rc = TRACE_ERRORX(SBE_XIP_BUG,
+                              "C/Assembler size mismatch(%d/%d) "
+                              "for SbeXipSection\n",
+                              sizeof(SbeXipSection), SIZE_OF_SBE_XIP_SECTION);
+            break;
+        }
+                              
+        if (sizeof(SbeXipToc) != SIZE_OF_SBE_XIP_TOC) {
+            rc = TRACE_ERRORX(SBE_XIP_BUG,
+                              "C/Assembler size mismatch(%d/%d) "
+                              "for SbeXipToc\n",
+                              sizeof(SbeXipToc), SIZE_OF_SBE_XIP_TOC);
+            break;
+        }
+
+        if (sizeof(SbeXipHashedToc) != SIZE_OF_SBE_XIP_HASHED_TOC) {
+            rc = TRACE_ERRORX(SBE_XIP_BUG,
+                              "C/Assembler size mismatch(%d/%d) "
+                              "for SbeXipHashedToc\n",
+                              sizeof(SbeXipHashedToc), 
+                              SIZE_OF_SBE_XIP_HASHED_TOC);
+            break;
+        }
+
+        // Validate the image pointer and magic number
+
+        rc = xipQuickCheck(i_image, 0);
+        if (rc) break;
+
+        // Validate the image size
+
+        linkAddress = hostHeader.iv_linkAddress;
+        imageSize = hostHeader.iv_imageSize;
+        extent = linkAddress + imageSize;
+
+        if (imageSize < sizeof(SbeXipHeader)) {
+            rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
+                              "sbe_xip_validate2(%p, %u) : "
+                              "The image size recorded in the image "
+                              "(%u) is smaller than the header size.\n",
+                              i_image, i_size, imageSize);
+            break;
+        }
+        if (imageSize != i_size && !(i_maskIgnores & SBE_XIP_IGNORE_FILE_SIZE)) {
+            rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
+                              "sbe_xip_validate2(%p, %u) : "
+                              "The image size recorded in the image "
+                              "(%u) does not match the i_size parameter.\n",
+                              i_image, i_size, imageSize);
+            break;
+        }
+        if (extent <= linkAddress) {
+            rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
+                              "sbe_xip_validate2(%p, %u) : "
+                              "Given the link address (%u) and the "
+                              "image size, the image wraps the address space\n",
+                              i_image, i_size, linkAddress);
+            break;
+        }
+        if ((imageSize % SBE_XIP_FINAL_ALIGNMENT) != 0) {
+            rc = TRACE_ERRORX(SBE_XIP_ALIGNMENT_ERROR,
+                              "sbe_xip_validate2(%p, %u) : "
+                              "The image size (%u) is not a multiple of %u\n",
+                              i_image, i_size, imageSize, 
+                              SBE_XIP_FINAL_ALIGNMENT);
+            break;
+        }
+
+        // Validate that all sections appear to be within the image
+        // bounds, and are aligned correctly.
+
+        for (i = 0; i < SBE_XIP_SECTIONS; i++) {
+
+            offset = hostHeader.iv_section[i].iv_offset;
+            size = hostHeader.iv_section[i].iv_size;
+            alignment = hostHeader.iv_section[i].iv_alignment;
+
+            if ((offset > imageSize) || 
+                ((offset + size) > imageSize) ||
+                ((offset + size) < offset)) {
+                rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
+                                  "Section %d does not appear to be within "
+                                  "the bounds of the image\n"
+                                  "offset = %u, size = %u, image size = %u\n",
+                                  i, offset, size, imageSize);
+                break;
+            }
+            if ((offset % alignment) != 0) {
+                rc = TRACE_ERRORX(SBE_XIP_ALIGNMENT_ERROR,
+                                  "Section %d requires %d-byte initial "
+                                  "alignment but the section offset is %u\n",
+                                  i, alignment, offset);
+                break;
+            }
+        }
+        if (rc) break;
+
+        // If the TOC exists and the image is normalized, validate each TOC
+        // entry. 
+
+        size = hostHeader.iv_section[SBE_XIP_SECTION_TOC].iv_size; 
+        if (size != 0) {
+            if (xipNormalized(i_image)) {
+                rc = sbe_xip_map_toc(i_image, xipValidateTocEntry, 0);
+                if (rc) break;
+            }
+        }
+    } while (0);
+    return rc;
+}
+
+
+// Normalization:
+//
+// 1. Normalize the TOC, unless the image is already normalized.  The image
+// must be marked as normalized before sorting.
+//
+// 2. Sort the TOC.
+//
+// 3. Clear the section offsets of any empty sections to make the section
+// table reports less confusing.
+//
+// 4. Clear normalization status on any failure.
+
+int
+sbe_xip_normalize(void* io_image)
+{
+    int rc, i;
+    SbeXipSection section;
+    SbeXipToc* imageToc;
+    SbeXipHashedToc* fixedImageToc;
+    SbeXipHashedToc* fixedTocEntry;
+    size_t tocEntries, fixedTocEntries, fixedEntriesRemaining;
+       
+    do {
+        rc = xipQuickCheck(io_image, 0);
+        if (rc) break;
+
+        if (!xipNormalized(io_image)) {
+
+            rc = xipGetToc(io_image, &imageToc, &tocEntries, 0, 0);
+            if (rc) break;
+
+            rc = xipGetFixedToc(io_image, &fixedImageToc, &fixedTocEntries);
+            if (rc) break;
+
+            fixedTocEntry = fixedImageToc;
+            fixedEntriesRemaining = fixedTocEntries;
+
+            for (; tocEntries--; imageToc++) {
+                rc = xipNormalizeToc(io_image, imageToc, 
+                                     &fixedTocEntry, &fixedEntriesRemaining);
+                if (rc) break;
+                                  
+            }
+            if (rc) break;
+
+            if (fixedEntriesRemaining != 0) {
+                rc = TRACE_ERRORX(SBE_XIP_TOC_ERROR,
+                                  "Not enough TOC entries for .fixed");
+                break;
+            }
+
+            rc = xipHashCollision(fixedImageToc, fixedTocEntries);
+            if (rc) break;
+
+            ((SbeXipHeader*)io_image)->iv_normalized = 1;
+        }
+
+        rc = xipSortToc(io_image);
+        if (rc) break;
+
+        for (i = 0; i < SBE_XIP_SECTIONS; i++) {
+            rc = sbe_xip_get_section(io_image, i, &section);
+            if (rc) break;
+            if (section.iv_size == 0) {
+                xipSetSectionOffset(io_image, i, 0);
+            }
+        }
+        if (rc) break;
+
+    } while(0);
+
+    ((SbeXipHeader*)io_image)->iv_normalized = (rc == 0);
+
+    return rc;
+}
+
+
+int
+sbe_xip_image_size(void* io_image, uint32_t* o_size)
+{
+    int rc;
+
+    rc = xipQuickCheck(io_image, 0);
+    if (!rc) {
+        *o_size = xipImageSize(io_image);
+    }
+    return rc;
+}
+
+
+int
+sbe_xip_get_section(const void* i_image,
+                    const int i_sectionId,
+                    SbeXipSection* o_hostSection)
+{
+    int rc;
+    SbeXipSection *imageSection;
+
+    rc = xipGetSectionPointer(i_image, i_sectionId, &imageSection);
+
+    if (!rc) {
+        xipTranslateSection(o_hostSection, imageSection);
+    }
+
+    return rc;
+}
+
+
+// If the 'big' TOC is not present, search the mini-TOCs that only index the
+// .fixed and .header sections.
+
+int
+sbe_xip_find(void* i_image, 
+             const char* i_id,
+             SbeXipItem* o_item)
+{
+    int rc;
+    SbeXipToc* toc;
+    SbeXipItem item, *pitem;
+    SbeXipSection* tocSection;
+
+    do {
+        rc = xipQuickCheck(i_image, 1);
+        if (rc) break;
+
+        rc = xipGetSectionPointer(i_image, SBE_XIP_SECTION_TOC, &tocSection);
+        if (rc) break;
+
+        if (tocSection->iv_size == 0) {
+            rc = xipFixedFind(i_image, i_id, o_item);
+            if (rc) {
+                rc = xipHeaderFind(i_image, i_id, o_item);
+            }
+            break;
+        }
+
+        if (xipSorted(i_image)) {
+            rc = xipBinarySearch(i_image, i_id, &toc);
+        } else {
+            rc = xipLinearSearch(i_image, i_id, &toc);
+        }
+        if (rc) break;
+
+        if (o_item) {
+            pitem = o_item;
+        } else {
+            pitem = &item;
+        }
+        rc = xipDecodeToc(i_image, toc, pitem);
+        if (rc) break;
+
+    } while (0);
+
+    return rc;
+}
+
+
+
+
+int
+sbe_xip_get_scalar(void *i_image, const char* i_id, uint64_t* o_data)
+{
+    int rc;
+    SbeXipItem item;
+    
+    rc = sbe_xip_find(i_image, i_id, &item);
+    if (!rc) {
+        switch (item.iv_type) {
+        case SBE_XIP_UINT8:
+            *o_data = *((uint8_t*)(item.iv_imageData));
+            break;
+        case SBE_XIP_UINT16:
+            *o_data = xipRevLe16(*((uint16_t*)(item.iv_imageData)));
+            break;
+        case SBE_XIP_UINT32:
+            *o_data = xipRevLe32(*((uint32_t*)(item.iv_imageData)));
+            break;
+        case SBE_XIP_UINT64:
+            *o_data = xipRevLe64(*((uint64_t*)(item.iv_imageData)));
+            break;
+        case SBE_XIP_INT8:
+            *o_data = *((int8_t*)(item.iv_imageData));
+            break;
+        case SBE_XIP_INT16:
+            *o_data = xipRevLe16(*((int16_t*)(item.iv_imageData)));
+            break;
+        case SBE_XIP_INT32:
+            *o_data = xipRevLe32(*((int32_t*)(item.iv_imageData)));
+            break;
+        case SBE_XIP_INT64:
+            *o_data = xipRevLe64(*((int64_t*)(item.iv_imageData)));
+            break;
+        case SBE_XIP_ADDRESS:
+            *o_data = item.iv_address;
+            break;
+        default:
+            rc = TRACE_ERROR(SBE_XIP_TYPE_ERROR);
+            break;
+        }
+    }
+    return rc;
+}
+
+
+int
+sbe_xip_get_element(void *i_image, 
+                    const char* i_id,
+                    const uint32_t i_index,
+                    uint64_t* o_data)
+{
+    int rc;
+    SbeXipItem item;
+    
+    do {
+        rc = sbe_xip_find(i_image, i_id, &item);
+        if (rc) break;
+
+        if ((item.iv_elements != 0) && (i_index >= item.iv_elements)) {
+            rc = TRACE_ERROR(SBE_XIP_BOUNDS_ERROR);
+            break;
+        }
+
+        switch (item.iv_type) {
+        case SBE_XIP_UINT8:
+            *o_data = ((uint8_t*)(item.iv_imageData))[i_index];
+            break;
+        case SBE_XIP_UINT16:
+            *o_data = xipRevLe16(((uint16_t*)(item.iv_imageData))[i_index]);
+            break;
+        case SBE_XIP_UINT32:
+            *o_data = xipRevLe32(((uint32_t*)(item.iv_imageData))[i_index]);
+            break;
+        case SBE_XIP_UINT64:
+            *o_data = xipRevLe64(((uint64_t*)(item.iv_imageData))[i_index]);
+            break;
+        case SBE_XIP_INT8:
+            *o_data = ((int8_t*)(item.iv_imageData))[i_index];
+            break;
+        case SBE_XIP_INT16:
+            *o_data = xipRevLe16(((int16_t*)(item.iv_imageData))[i_index]);
+            break;
+        case SBE_XIP_INT32:
+            *o_data = xipRevLe32(((int32_t*)(item.iv_imageData))[i_index]);
+            break;
+        case SBE_XIP_INT64:
+            *o_data = xipRevLe64(((int64_t*)(item.iv_imageData))[i_index]);
+            break;
+        default:
+            rc = TRACE_ERROR(SBE_XIP_TYPE_ERROR);
+            break;
+        }
+        if (rc) break;
+
+    } while (0);
+    return rc;
+}
+
+
+int
+sbe_xip_get_string(void *i_image, const char* i_id, char** o_data)
+{
+    int rc;
+    SbeXipItem item;
+    
+    rc = sbe_xip_find(i_image, i_id, &item);
+    if (!rc) {
+        switch (item.iv_type) {
+        case SBE_XIP_STRING:
+            *o_data = (char*)(item.iv_imageData);
+            break;
+        default:
+            rc = TRACE_ERROR(SBE_XIP_TYPE_ERROR);
+            break;
+        }
+    }
+    return rc;
+}
+
+
+int
+sbe_xip_read_uint64(const void *i_image, 
+                    const uint64_t i_imageAddress,
+                    uint64_t* o_data)
+{
+    int rc;
+
+    do {
+        rc = xipQuickCheck(i_image, 0);
+        if (rc) break;
+
+        rc = xipValidateImageAddress(i_image, i_imageAddress, 8);
+        if (rc) break;
+
+        if (i_imageAddress % 8) {
+            rc = TRACE_ERROR(SBE_XIP_ALIGNMENT_ERROR);
+            break;
+        }
+
+        *o_data = 
+            xipRevLe64(*((uint64_t*)xipImage2Host(i_image, i_imageAddress)));
+
+    } while(0);
+
+    return rc;
+}
+
+
+int
+sbe_xip_set_scalar(void* io_image, const char* i_id, const uint64_t i_data)
+{
+    int rc;
+    SbeXipItem item;
+
+    rc = sbe_xip_find(io_image, i_id, &item);
+    if (!rc) {
+        switch(item.iv_type) {
+        case SBE_XIP_UINT8:
+            *((uint8_t*)(item.iv_imageData)) = (uint8_t)i_data;
+            break;
+        case SBE_XIP_UINT16:
+            *((uint16_t*)(item.iv_imageData)) = xipRevLe16((uint16_t)i_data);
+            break;
+        case SBE_XIP_UINT32:
+            *((uint32_t*)(item.iv_imageData)) = xipRevLe32((uint32_t)i_data);
+            break;
+        case SBE_XIP_UINT64:
+            *((uint64_t*)(item.iv_imageData)) = xipRevLe64((uint64_t)i_data);
+            break;
+        case SBE_XIP_INT8:
+            *((int8_t*)(item.iv_imageData)) = (int8_t)i_data;
+            break;
+        case SBE_XIP_INT16:
+            *((int16_t*)(item.iv_imageData)) = xipRevLe16((int16_t)i_data);
+            break;
+        case SBE_XIP_INT32:
+            *((int32_t*)(item.iv_imageData)) = xipRevLe32((int32_t)i_data);
+            break;
+        case SBE_XIP_INT64:
+            *((int64_t*)(item.iv_imageData)) = xipRevLe64((int64_t)i_data);
+            break;
+        default:
+            rc = TRACE_ERROR(SBE_XIP_TYPE_ERROR);
+            break;
+        }
+    }
+    return rc;
+}
+
+
+int
+sbe_xip_set_element(void *i_image, 
+                    const char* i_id,
+                    const uint32_t i_index,
+                    const uint64_t i_data)
+{
+    int rc;
+    SbeXipItem item;
+    
+    do {
+        rc = sbe_xip_find(i_image, i_id, &item);
+        if (rc) break;
+
+        if ((item.iv_elements != 0) && (i_index >= item.iv_elements)) {
+            rc = TRACE_ERROR(SBE_XIP_BOUNDS_ERROR);
+            break;
+        }
+
+        switch (item.iv_type) {
+        case SBE_XIP_UINT8:
+            ((uint8_t*)(item.iv_imageData))[i_index] = (uint8_t)i_data;
+            break;
+        case SBE_XIP_UINT32:
+            ((uint32_t*)(item.iv_imageData))[i_index] = 
+                xipRevLe32((uint32_t)i_data);
+            break;
+        case SBE_XIP_UINT64:
+            ((uint64_t*)(item.iv_imageData))[i_index] = 
+                xipRevLe64((uint64_t)i_data);
+            break;
+        default:
+            rc = TRACE_ERROR(SBE_XIP_TYPE_ERROR);
+            break;
+        }
+        if (rc) break;
+
+    } while (0);
+
+    return rc;
+}
+
+
+int
+sbe_xip_set_string(void *i_image, const char* i_id, const char* i_data)
+{
+    int rc;
+    SbeXipItem item;
+    char* dest;
+    
+    rc = sbe_xip_find(i_image, i_id, &item);
+    if (!rc) {
+        switch (item.iv_type) {
+        case SBE_XIP_STRING:
+            dest = (char*)(item.iv_imageData);
+            if (strlen(dest) < strlen(i_data)) {
+                memcpy(dest, i_data, strlen(dest));
+            } else {
+                strcpy(dest, i_data);
+            }
+            break;
+        default:
+            rc = TRACE_ERROR(SBE_XIP_TYPE_ERROR);
+            break;
+        }
+    }
+    return rc;
+}
+
+
+int
+sbe_xip_write_uint64(void *io_image, 
+                     const uint64_t i_imageAddress,
+                     const uint64_t i_data)
+{
+    int rc;
+
+    do {
+        rc = xipQuickCheck(io_image, 0);
+        if (rc) break;
+
+        rc = xipValidateImageAddress(io_image, i_imageAddress, 8);
+        if (rc) break;
+
+        if (i_imageAddress % 8) {
+            rc = TRACE_ERROR(SBE_XIP_ALIGNMENT_ERROR);
+            break;
+        }
+
+        *((uint64_t*)xipImage2Host(io_image, i_imageAddress)) = 
+            xipRevLe64(i_data);
+
+    } while(0);
+
+    return rc;
+}
+
+
+int
+sbe_xip_delete_section(void* io_image, const int i_sectionId)
+{
+    int rc, final;
+    SbeXipSection section;
+
+    do {
+        rc = xipQuickCheck(io_image, 1);
+        if (rc) break;
+
+        rc = sbe_xip_get_section(io_image, i_sectionId, &section);
+        if (rc) break;
+
+
+        // Deleting an empty section is a NOP.  Otherwise the section must be
+        // the final section of the image. Update the sizes and re-establish
+        // the final image alignment.
+
+        if (section.iv_size == 0) break;
+
+        rc = xipFinalSection(io_image, &final);
+        if (rc) break;
+
+        if (final != i_sectionId) {
+            rc = TRACE_ERRORX(SBE_XIP_SECTION_ERROR,
+                              "Attempt to delete non-final section %d\n",
+                              i_sectionId);
+            break;
+        }
+
+        xipSetSectionOffset(io_image, i_sectionId, 0);
+        xipSetSectionSize(io_image, i_sectionId, 0);
+
+
+        // For cleanliness we also remove any alignment padding that had been
+        // appended between the now-last section and the deleted section, then
+        // re-establish the final alignment. The assumption is that all images
+        // always have the correct final alignment, so there is no way this
+        // could overflow a designated buffer space since the image size is
+        // the same or has been reduced.
+
+        rc = xipFinalSection(io_image, &final);
+        if (rc) break;
+
+        rc = sbe_xip_get_section(io_image, final, &section);
+        if (rc) break;
+
+        xipSetImageSize(io_image, section.iv_offset + section.iv_size);
+        xipFinalAlignment(io_image);
+
+    } while (0);
+
+    return rc;
+}
+
+
+#ifndef PPC_HYP
+
+// This API is not needed by PHYP procedures, and is elided since PHYP does
+// not support malloc().
+
+int
+sbe_xip_duplicate_section(const void* i_image, 
+                          const int i_sectionId,
+                          void** o_duplicate,
+                          uint32_t* o_size)
+{
+    SbeXipSection section;
+    int rc;
+
+    *o_duplicate = 0;
+
+    do {
+        rc = xipQuickCheck(i_image, 0);
+        if (rc) break;
+
+        rc = sbe_xip_get_section(i_image, i_sectionId, &section);
+        if (rc) break;
+
+        if (section.iv_size == 0) {
+            rc = TRACE_ERRORX(SBE_XIP_SECTION_ERROR,
+                              "Attempt to duplicate empty section %d\n",
+                              i_sectionId);
+            break;
+        }
+
+        *o_duplicate = malloc(section.iv_size);
+        *o_size = section.iv_size;
+
+        if (*o_duplicate == 0) {
+            rc = TRACE_ERROR(SBE_XIP_NO_MEMORY);
+            break;
+        }
+
+        memcpy(*o_duplicate, 
+               xipHostAddressFromOffset(i_image, section.iv_offset),
+               section.iv_size);
+        
+        
+    } while (0);
+
+    if (rc) {
+        free(*o_duplicate);
+        *o_duplicate = 0;
+        *o_size = 0;
+    }
+
+    return rc;
+}
+
+#endif // PPC_HYP
+
+
+// The append must be done in such a way that if the append fails, the image
+// is not modified. This behavior is required by applications that
+// speculatively append until the allocation fails, but still require the
+// final image to be valid. To accomplish this the initial image size and
+// section statistics are captured at entry, and restored in the event of an
+// error.
+
+int
+sbe_xip_append(void* io_image,
+               const int i_sectionId,
+               const void* i_data,
+               const uint32_t i_size,
+               const uint32_t i_allocation,
+               uint32_t* o_sectionOffset)
+{
+    SbeXipSection section, initialSection;
+    int rc, final, restoreOnError;
+    void* hostAddress;
+    uint32_t pad, initialSize;
+
+    do {
+        restoreOnError = 0;
+
+        rc = xipQuickCheck(io_image, 1);
+        if (rc) break;
+
+        rc = sbe_xip_get_section(io_image, i_sectionId, &section);
+        if (rc) break;
+
+        if (i_size == 0) break;
+
+        initialSection = section;
+        initialSize = xipImageSize(io_image);
+        restoreOnError = 1;
+
+        if (section.iv_size == 0) {
+
+            // The section is empty, and now becomes the final section. Pad
+            // the image to the specified section alignment.  Note that the
+            // size of the previously final section does not change.
+
+            rc = xipPadImage(io_image, i_allocation, section.iv_alignment, 
+                             &pad);
+            if (rc) break;
+            section.iv_offset = xipImageSize(io_image);
+
+        } else {
+
+            // Otherwise, the section must be the final section in order to
+            // continue. Remove any padding from the image.
+
+            rc = xipFinalSection(io_image, &final);
+            if (rc) break;
+
+            if (final != i_sectionId) {
+                rc = TRACE_ERRORX(SBE_XIP_SECTION_ERROR,
+                                  "Attempt to append to non-final section "
+                                  "%d\n", i_sectionId);
+                break;
+            }
+            xipSetImageSize(io_image, section.iv_offset + section.iv_size);
+        }
+
+
+        // Make sure the allocated space won't overflow. Set the return
+        // parameter o_sectionOffset and copy the new data into the image (or
+        // simply clear the space).
+
+        if ((xipImageSize(io_image) + i_size) > i_allocation) {
+            rc = TRACE_ERROR(SBE_XIP_WOULD_OVERFLOW);
+            break;
+        }            
+        if (o_sectionOffset != 0) {
+            *o_sectionOffset = section.iv_size;
+        }
+
+        hostAddress = 
+            xipHostAddressFromOffset(io_image, xipImageSize(io_image));
+        if (i_data == 0) {
+            memset(hostAddress, 0, i_size);
+        } else {
+            memcpy(hostAddress, i_data, i_size);
+        }
+
+
+        // Update the image size and section table. Note that the final
+        // alignment may push out of the allocation.
+
+        xipSetImageSize(io_image, xipImageSize(io_image) + i_size);
+        xipFinalAlignment(io_image);
+
+        if (xipImageSize(io_image) > i_allocation) {
+            rc = TRACE_ERROR(SBE_XIP_WOULD_OVERFLOW);
+            break;
+        }            
+
+        section.iv_size += i_size;
+
+        if (xipPutSection(io_image, i_sectionId, &section) != 0) {
+            rc = TRACE_ERROR(SBE_XIP_BUG); /* Can't happen */
+            break;
+        }
+
+
+        // Special case
+
+        if (i_sectionId == SBE_XIP_SECTION_TOC) {
+            ((SbeXipHeader*)io_image)->iv_tocSorted = 0;
+        }
+
+    } while (0);
+
+    if (rc && restoreOnError) {
+        if (xipPutSection(io_image, i_sectionId, &initialSection) != 0) {
+            rc = TRACE_ERROR(SBE_XIP_BUG); /* Can't happen */
+        }
+        xipSetImageSize(io_image, initialSize);
+    }
+     
+    return rc;
+}
+
+
+int
+sbe_xip_section2image(const void* i_image, 
+                     const int i_sectionId,
+                     const uint32_t i_offset,
+                     uint64_t* o_imageAddress)
+{
+    int rc;
+    SbeXipSection section;
+
+    do {
+        rc = xipQuickCheck(i_image, 0);
+        if (rc) break;
+
+        rc = sbe_xip_get_section(i_image, i_sectionId, &section);
+        if (rc) break;
+
+        if (section.iv_size == 0) {
+            rc = TRACE_ERROR(SBE_XIP_SECTION_ERROR);
+            break;
+        }
+
+        if (i_offset > (section.iv_offset + section.iv_size)) {
+            rc = TRACE_ERROR(SBE_XIP_INVALID_ARGUMENT);
+            break;
+        }
+
+        *o_imageAddress = xipLinkAddress(i_image) + section.iv_offset + i_offset;
+
+        if (*o_imageAddress % 4) {
+            rc = TRACE_ERROR(SBE_XIP_ALIGNMENT_ERROR);
+            break;
+        }
+
+    } while(0);
+
+    return rc;
+}
+
+
+int
+sbe_xip_image2section(const void* i_image, 
+                     const uint64_t i_imageAddress,
+                     int* i_section,
+                     uint32_t* i_offset)
+{
+    int rc;
+
+    do {
+        rc = xipQuickCheck(i_image, 0);
+        if (rc) break;
+
+        rc = xipImage2Section(i_image, i_imageAddress, i_section, i_offset);
+
+    } while(0);
+
+    return rc;
+}
+
+
+int
+sbe_xip_image2host(const void* i_image, 
+                  const uint64_t i_imageAddress,
+                  void** o_hostAddress)
+{
+    int rc;
+
+    do {
+        rc = xipQuickCheck(i_image, 0);
+        if (rc) break;
+
+        if ((i_imageAddress < xipLinkAddress(i_image)) ||
+            (i_imageAddress > 
+             (xipLinkAddress(i_image) + xipImageSize(i_image)))) {
+            rc = TRACE_ERROR(SBE_XIP_INVALID_ARGUMENT);
+            break;
+        }
+
+        *o_hostAddress = 
+            xipHostAddressFromOffset(i_image, 
+                                     i_imageAddress - xipLinkAddress(i_image));
+    } while(0);
+
+    return rc;
+}
+    
+    
+int
+sbe_xip_host2image(const void* i_image, 
+                  void* i_hostAddress,
+                  uint64_t* o_imageAddress)
+{
+    int rc;
+
+    do {
+        rc = xipQuickCheck(i_image, 0);
+        if (rc) break;
+
+        if ((i_hostAddress < i_image) ||
+            (i_hostAddress > 
+             xipHostAddressFromOffset(i_image, xipImageSize(i_image)))) {
+            rc = TRACE_ERROR(SBE_XIP_INVALID_ARGUMENT);
+            break;
+        }
+
+        *o_imageAddress = xipLinkAddress(i_image) + 
+            ((unsigned long)i_hostAddress - (unsigned long)i_image);
+        if (*o_imageAddress % 4) {
+            rc = TRACE_ERROR(SBE_XIP_ALIGNMENT_ERROR);
+            break;
+        }
+    } while(0);
+
+    return rc;
+}
+        
+
+void
+sbe_xip_translate_header(SbeXipHeader* o_dest, const SbeXipHeader* i_src)
+{
+#ifndef _BIG_ENDIAN
+    int i;
+    SbeXipSection* destSection;
+    const SbeXipSection* srcSection;
+
+#if SBE_XIP_HEADER_VERSION != 8
+#error This code assumes the SBE-XIP header version 8 layout
+#endif
+
+    o_dest->iv_magic = xipRevLe64(i_src->iv_magic);
+    o_dest->iv_entryOffset = xipRevLe64(i_src->iv_entryOffset);
+    o_dest->iv_linkAddress = xipRevLe64(i_src->iv_linkAddress);
+
+    for (i = 0; i < 5; i++) {
+        o_dest->iv_reserved64[i] = 0;
+    }
+
+    for (i = 0, destSection = o_dest->iv_section, 
+             srcSection = i_src->iv_section;
+         i < SBE_XIP_SECTIONS; 
+         i++, destSection++, srcSection++) {
+        xipTranslateSection(destSection, srcSection);
+    }
+
+    o_dest->iv_imageSize = xipRevLe32(i_src->iv_imageSize);
+    o_dest->iv_buildDate = xipRevLe32(i_src->iv_buildDate);
+    o_dest->iv_buildTime = xipRevLe32(i_src->iv_buildTime);
+
+    for (i = 0; i < 5; i++) {
+        o_dest->iv_reserved32[i] = 0;
+    }
+
+    o_dest->iv_headerVersion = i_src->iv_headerVersion;
+    o_dest->iv_normalized = i_src->iv_normalized;
+    o_dest->iv_tocSorted = i_src->iv_tocSorted;
+
+    for (i = 0; i < 3; i++) {
+        o_dest->iv_reserved8[i] = 0;
+    }
+
+    memcpy(o_dest->iv_buildUser, i_src->iv_buildUser, 
+           sizeof(i_src->iv_buildUser));
+    memcpy(o_dest->iv_buildHost, i_src->iv_buildHost, 
+           sizeof(i_src->iv_buildHost));
+    memcpy(o_dest->iv_reservedChar, i_src->iv_reservedChar, 
+           sizeof(i_src->iv_reservedChar));
+
+#else
+    if (o_dest != i_src) {
+        *o_dest = *i_src;
+    }
+#endif  /* _BIG_ENDIAN */
+}
+    
+
+int
+sbe_xip_map_toc(void* io_image, 
+                int (*i_fn)(void* io_image,
+                            const SbeXipItem* i_item, 
+                            void* io_arg),
+                void* io_arg)
+{
+    int rc;
+    SbeXipToc *imageToc;
+    SbeXipItem item;
+    size_t entries;
+
+    do {
+        rc = xipQuickCheck(io_image, 0);
+        if (rc) break;
+
+        rc = xipGetToc(io_image, &imageToc, &entries, 0, 0);
+        if (rc) break;
+
+        for (; entries--; imageToc++) {
+            rc = xipDecodeToc(io_image, imageToc, &item);
+            if (rc) break;
+            rc = i_fn(io_image, &item, io_arg);
+            if (rc) break;
+        }
+    } while(0);
+
+    return rc;
+}
diff --git a/src/ppe/sbe/image/sbe_xip_image.h b/src/ppe/sbe/image/sbe_xip_image.h
index 9340fcb..5a47b0a 100644
--- a/src/ppe/sbe/image/sbe_xip_image.h
+++ b/src/ppe/sbe/image/sbe_xip_image.h
@@ -80,21 +80,18 @@
 #define SBE_XIP_SECTION_HEADER      0
 #define SBE_XIP_SECTION_FIXED       1
 #define SBE_XIP_SECTION_FIXED_TOC   2
-#define SBE_XIP_SECTION_IPL_TEXT    3
-#define SBE_XIP_SECTION_IPL_DATA    4
+#define SBE_XIP_SECTION_LOADER_TEXT 3
+#define SBE_XIP_SECTION_LOADER_DATA 4
 #define SBE_XIP_SECTION_TEXT        5
 #define SBE_XIP_SECTION_DATA        6
 #define SBE_XIP_SECTION_TOC         7
 #define SBE_XIP_SECTION_STRINGS     8
-#define SBE_XIP_SECTION_HALT        9
-#define SBE_XIP_SECTION_PIBMEM0    10
-#define SBE_XIP_SECTION_DCRINGS    11
+#define SBE_XIP_SECTION_BASE        9
+#define SBE_XIP_SECTION_BASELOADER 10
+#define SBE_XIP_SECTION_OVERLAYS   11
 #define SBE_XIP_SECTION_RINGS      12
-#define SBE_XIP_SECTION_SLW        13
-#define SBE_XIP_SECTION_FIT        14
-#define SBE_XIP_SECTION_FFDC       15
 
-#define SBE_XIP_SECTIONS 16
+#define SBE_XIP_SECTIONS 13
 
 /// @}
 
@@ -123,19 +120,16 @@
         ".header",                              \
         ".fixed",                               \
         ".fixed_toc",                           \
-        ".ipl_text",                            \
-        ".ipl_data",                            \
+        ".loader_text",                         \
+        ".loader_data",                         \
         ".text",                                \
         ".data",                                \
         ".toc",                                 \
         ".strings",                             \
-        ".halt",                                \
-        ".pibmem0",                             \
-        ".dcrings",                             \
+        ".base",                                \
+        ".baseloader",                          \
+        ".overlays",                             \
         ".rings",                               \
-        ".slw",                                 \
-        ".fit",                                 \
-        ".ffdc",                                \
     }
 
 /// Applications can use this macro to safely index the array of section
@@ -165,20 +159,35 @@
 /// Data is a single unsigned byte
 #define SBE_XIP_UINT8 0x01
 
+/// Data is a 16-bit unsigned integer
+#define SBE_XIP_UINT16 0x02
+
 /// Data is a 32-bit unsigned integer
-#define SBE_XIP_UINT32 0x02
+#define SBE_XIP_UINT32 0x03
 
 /// Data is a 64-bit unsigned integer
-#define SBE_XIP_UINT64 0x03
+#define SBE_XIP_UINT64 0x04
+
+/// Data is a single signed byte
+#define SBE_XIP_INT8 0x05
+
+/// Data is a 16-bit signed integer
+#define SBE_XIP_INT16 0x06
+
+/// Data is a 32-bit signed integer
+#define SBE_XIP_INT32 0x07
+
+/// Data is a 64-bit signed integer
+#define SBE_XIP_INT64 0x08
 
 /// Data is a 0-byte terminated ASCII string
-#define SBE_XIP_STRING 0x04
+#define SBE_XIP_STRING 0x09
 
 /// Data is an address
-#define SBE_XIP_ADDRESS 0x05
+#define SBE_XIP_ADDRESS 0x0A
 
 /// The maximum type number
-#define SBE_XIP_MAX_TYPE_INDEX 0x05
+#define SBE_XIP_MAX_TYPE_INDEX 0x0A
 
 /// Applications can expand this macro to get access to string forms of the
 /// SBE-XIP data types if desired.
@@ -186,8 +195,13 @@
     const char* var[] = {                       \
         "Illegal 0 Code",                       \
         "SBE_XIP_UINT8",                        \
+        "SBE_XIP_UINT16",                       \
         "SBE_XIP_UINT32",                       \
         "SBE_XIP_UINT64",                       \
+        "SBE_XIP_INT8",                         \
+        "SBE_XIP_INT16",                        \
+        "SBE_XIP_INT32",                        \
+        "SBE_XIP_INT64",                        \
         "SBE_XIP_STRING",                       \
         "SBE_XIP_ADDRESS",                      \
     }
@@ -198,8 +212,13 @@
     const char* var[] = {                       \
         "Illegal 0 Code",                       \
         "u8 ",                                  \
+        "u16",                                  \
         "u32",                                  \
         "u64",                                  \
+        "i8 ",                                  \
+        "i16",                                  \
+        "i32",                                  \
+        "i64",                                  \
         "str",                                  \
         "adr",                                  \
     }
@@ -215,8 +234,8 @@
 
 /// Final alignment constraint for SBE-XIP images.
 ///
-/// PORE images are required to be multiples of 8 bytes in length, to
-/// gaurantee that the PoreVe will be able to complete any 8-byte load/store.
+/// images are required to be multiples of 8 bytes in length, to
+/// gaurantee that the something will be able to complete any 8-byte load/store.
 #define SBE_XIP_FINAL_ALIGNMENT 8
 
 
@@ -266,12 +285,12 @@ typedef struct {
 
     /// The required initial alignment for the section offset
     ///
-    /// The PORE and the applications using SBE-XIP images have strict
-    /// alignment/padding requirements.  The PORE does not handle any type of
+    /// The image and the applications using SBE-XIP images have strict
+    /// alignment/padding requirements.  The image does not handle any type of
     /// unaligned instruction or data fetches.  Some sections and subsections
     /// must also be POWER cache-line aligned. The \a iv_alignment applies to
-    /// the first byte of the section. PORE images are also required to be
-    /// multiples of 8 bytes in length, to gaurantee that the PoreVe will be
+    /// the first byte of the section. image images are also required to be
+    /// multiples of 8 bytes in length, to gaurantee that the something will be
     /// able to complete any 8-byte load/store.  These constraints are checked
     /// by sbe_xip_validate() and enforced by sbe_xip_append(). The alignment
     /// constraints may force a section to be padded, which may create "holes"
@@ -303,7 +322,7 @@ typedef struct {
 /// The header is a fixed-format representation of the most critical
 /// information about the image.  The large majority of information about the
 /// image and its contents are available through the searchable table of
-/// contents. PORE code itself normally accesses the data directly through
+/// contents. image code itself normally accesses the data directly through
 /// global symbols. 
 ///
 /// The header only contains information 1) required by OTPROM code (e.g., the
@@ -311,7 +330,7 @@ typedef struct {
 /// locations and sizes of all of the sections.); a few pieces of critical
 /// meta-data (e.g., information about the image build process).
 ///
-/// Any entries that are accessed by PORE code are required to be 64 bits, and
+/// Any entries that are accessed by image code are required to be 64 bits, and
 /// will appear at the beginning of the header.
 ///
 /// The header also contains bytewise offsets and sizes of all of the sections
@@ -338,7 +357,7 @@ typedef struct {
     /// The offset of the SBE-XIP entry point from the start of the image
     uint64_t iv_entryOffset;
 
-    /// The base address used to link the image, as a full relocatable PORE
+    /// The base address used to link the image, as a full relocatable image
     /// address 
     uint64_t iv_linkAddress;
 
@@ -403,7 +422,7 @@ typedef struct {
 /// A C-structure form of the SBE-XIP Table of Contents (TOC) entries
 ///
 /// The .toc section consists entirely of an array of these structures.
-/// TOC entries are never accessed by PORE code. 
+/// TOC entries are never accessed by image code. 
 ///
 /// These structures store indexing information for global data required to be
 /// manipulated by external tools.  The actual data is usually allocated in a
@@ -530,7 +549,7 @@ typedef struct {
     ///  If \a iv_partial is set this field is returned as 0.
     SbeXipToc* iv_toc;
 
-    /// The full relocatable PORE address
+    /// The full relocatable image address
     ///
     /// All relocatable addresses are computed from the \a iv_linkAddress
     /// stored in the header. For scalar and string data, this is the
@@ -577,41 +596,6 @@ typedef struct {
 } SbeXipItem;
 
 
-/// Prototype entry in the .halt section
-///
-/// The .halt section is generated by the 'reqhalt' macro.  This structure
-/// associates the address of each halt with the string form of the FAPI
-/// return code associated with the halt.  The string form is used because the
-/// FAPI error return code is not constant.  The .halt section is 4-byte
-/// aligned, and each address/string entry is always padded to a multiple of 4
-/// bytes. 
-///
-/// In the .halt section the \a iv_string may be any length, thus the size of
-/// each actual record is variable (although guaranteed to always be a
-/// multiple of 4 bytes). Although the C compiler might natuarlly align
-/// instances of this structure on a 64-bit boundary, the APIs that allow
-/// access to the .halt section assume that the underlying machine can do
-/// non-aligned loads from a pointer to this structure.
-
-typedef struct {
-
-    /// The 64-bit relocatable address of the halt
-    ///
-    /// This is the address found in the PC (Status Register bits 16:63) when
-    /// the PORE halts.  The full 64-bit form is used rather than the simple
-    /// 32-bit offset to support merging SEEPROM and PIBMEM .halt sections in
-    /// the SEEPROM IPL images.
-    uint64_t iv_address;
-
-    /// A C-prototype for a variable-length 0-terminated ASCII string
-    ///
-    /// This is a prototype only to simplify C programming.  The actual string
-    /// may be any length.
-    char iv_string[4];
-
-} SbeXipHalt;
-
-
 /// Validate an SBE-XIP image
 ///
 /// \param[in] i_image A pointer to an SBE-XIP image in host memory. 
@@ -723,7 +707,7 @@ sbe_xip_translate_header(SbeXipHeader* o_hostHeader,
 ///
 /// This API searches the SBE-XIP Table of Contents (TOC) for the item named
 /// \a i_id, assigning \a o_data from the image if the item is found and is a
-/// scalar value.  Scalar values include 8- 32- and 64-bit integers and PORE
+/// scalar value.  Scalar values include 8- 32- and 64-bit integers and image
 /// addresses.  Image data smaller than 64 bits are extracted as unsigned
 /// types, and it is the caller's responsibility to cast or convert the
 /// returned data as appropriate.
@@ -795,24 +779,24 @@ int
 sbe_xip_get_string(void *i_image, const char* i_id, char** o_data);
 
 
-/// Directly read 64-bit data from the image based on a PORE address
+/// Directly read 64-bit data from the image based on a image address
 ///
 /// \param[in] i_image A pointer to an SBE-XIP image in host memory.  The
 /// image is assumed to be consistent with the information contained in the
 /// header regarding the presence of and sizes of all sections.
 ///
-/// \param[in] i_poreAddress A relocatable PORE address contained in the
-/// image, presumably of an 8-byte data area.  The \a i_poreAddress is
+/// \param[in] i_imageAddress A relocatable IMAGE address contained in the
+/// image, presumably of an 8-byte data area.  The \a i_imageAddress is
 /// required to be 8-byte aligned, otherwise the SBE_XIP_ALIGNMENT_ERROR code
 /// is returned.
 ///
 /// \param[out] o_data The 64 bit data in host format that was found at \a
-/// i_poreAddress.
+/// i_imageAddress.
 ///
 /// This API is provided for applications that need to manipulate SBE-XIP
-/// images in terms of their relocatable PORE addresses.  The API checks that
-/// the \a i_poreAddress is properly aligned and contained in the image, then
-/// reads the contents of \a i_poreAddress into \a o_data, performing
+/// images in terms of their relocatable IMAGE addresses.  The API checks that
+/// the \a i_imageAddress is properly aligned and contained in the image, then
+/// reads the contents of \a i_imageAddress into \a o_data, performing
 /// image-to-host endianess conversion if required.
 ///
 /// \retval 0 Success
@@ -820,7 +804,7 @@ sbe_xip_get_string(void *i_image, const char* i_id, char** o_data);
 /// \retval non-0 See \ref sbe_xip_image_errors
 int
 sbe_xip_read_uint64(const void *i_image, 
-                    const uint64_t i_poreAddress,
+                    const uint64_t i_imageAddress,
                     uint64_t* o_data);
 
 
@@ -839,8 +823,8 @@ sbe_xip_read_uint64(const void *i_image,
 /// This API searches the SBE-XIP Table of Contents (TOC) for the item named
 /// by \a i_id, updating the image from \a i_data if the item is found, has
 /// a scalar type and can be modified.  For this API the scalar types include
-/// 8- 32- and 64-bit integers.  Although PORE addresses are considered a
-/// scalar type for sbe_xip_get_scalar(), PORE addresses can not be modified
+/// 8- 32- and 64-bit integers.  Although IMAGE addresses are considered a
+/// scalar type for sbe_xip_get_scalar(), IMAGE addresses can not be modified
 /// by this API.  The caller is responsible for ensuring that the \a i_data is
 /// of the correct size for the underlying data element in the image.
 ///
@@ -910,24 +894,24 @@ int
 sbe_xip_set_string(void *io_image, const char* i_id, const char* i_data);
 
 
-/// Directly write 64-bit data into the image based on a PORE address
+/// Directly write 64-bit data into the image based on a IMAGE address
 ///
 /// \param[in, out] io_image A pointer to an SBE-XIP image in host memory.  The
 /// image is assumed to be consistent with the information contained in the
 /// header regarding the presence of and sizes of all sections.
 ///
-/// \param[in] i_poreAddress A relocatable PORE address contained in the
-/// image, presumably of an 8-byte data area.  The \a i_poreAddress is
+/// \param[in] i_imageAddress A relocatable IMAGE address contained in the
+/// image, presumably of an 8-byte data area.  The \a i_imageAddress is
 /// required to be 8-byte aligned, otherwise the SBE_XIP_ALIGNMENT_ERROR code
 /// is returned.
 ///
 /// \param[in] i_data The 64 bit data in host format to be written to \a
-/// i_poreAddress. 
+/// i_imageAddress. 
 ///
 /// This API is provided for applications that need to manipulate SBE-XIP
-/// images in terms of their relocatable PORE addresses.  The API checks that
-/// the \a i_poreAddress is properly aligned and contained in the image, then
-/// updates the contents of \a i_poreAddress with \a i_data, performing
+/// images in terms of their relocatable IMAGE addresses.  The API checks that
+/// the \a i_imageAddress is properly aligned and contained in the image, then
+/// updates the contents of \a i_imageAddress with \a i_data, performing
 /// host-to-image endianess conversion if required.
 ///
 /// \retval 0 Success
@@ -935,7 +919,7 @@ sbe_xip_set_string(void *io_image, const char* i_id, const char* i_data);
 /// \retval non-0 See \ref sbe_xip_image_errors
 int
 sbe_xip_write_uint64(void *io_image, 
-                     const uint64_t i_poreAddress,
+                     const uint64_t i_imageAddress,
                      const uint64_t i_data);
 
 
@@ -1023,73 +1007,6 @@ sbe_xip_find(void* i_image,
              SbeXipItem* o_item);
 
 
-/// Map over an SBE-XIP image .halt section
-///
-/// \param[in,out] io_image A pointer to an SBE-XIP image in host memory.  The
-/// image is assumed to be consistent with the information contained in the
-/// header regarding the presence of and sizes of all sections.
-///
-/// \param[in] i_fn A pointer to a function to call on each entry in .halt.
-/// The function has the prototype:
-///
-/// \code
-/// int (*i_fn)(void* io_image,
-///             const uint64_t i_poreAddress,
-///             const char* i_rcString,
-///             void* io_arg)
-///
-/// \endcode
-///
-/// \param[in,out] io_arg The private argument of \a i_fn.
-///
-/// This API iterates over each entry of the .halt section, calling \a i_fn
-/// with each HALT address, the string form of the return code associated with
-/// that HALT address, and a private argument. The iteration terminates either
-/// when all .halt entries have been mapped, or \a i_fn returns a non-zero
-/// code.  The \a i_poreAddddress passed to \a i_fn is the full 48-bit
-/// relocatable PORE address.
-///
-/// \retval 0 Success, including the case that the image has no .halt section.
-///
-/// \retval non-0 May be either one of the SBE-XIP image error codes (see \ref
-/// sbe_xip_image_errors), or any non-zero code from \a i_fn.  Since the
-/// standard SBE_XIP return codes are \> 0, application-defined codes should
-/// be \< 0.
-int
-sbe_xip_map_halt(void* io_image, 
-                 int (*i_fn)(void* io_image, 
-                             const uint64_t i_poreAddress,
-                             const char* i_rcString,
-                             void* io_arg),
-                 void* io_arg);
-
-
-/// Get the string from of a HALT code from an SBE-XIP image .halt section
-///
-/// \param[in,out] io_image A pointer to an SBE-XIP image in host memory.  The
-/// image is assumed to be consistent with the information contained in the
-/// header regarding the presence of and sizes of all sections.
-///
-/// \param[in] i_poreAddress This is the 48-bit address found in the PC when
-/// the PORE halts.  This address is actually 4 bytes beyond the actual HALT
-/// instruction, however for simplicity this is the address used to index the
-/// HALT. 
-///
-/// \param[out] o_rcString The caller provides the address of a string-pointer
-/// variable which is updated with a pointer to the string form of the halt
-/// code associated with \a i_poreAddress (assuming a successful completion).
-///
-/// \retval 0 Success
-///
-/// \revtal SBE_XIP_ITEM_NOT_FOUND The \a i_poreAddress is not associated
-/// with a halt code in .halt.
-///
-/// \revtal Other See \ref sbe_xip_image_errors
-int
-sbe_xip_get_halt(void* io_image, 
-                 const uint64_t i_poreAddress,
-                 const char** o_rcString);
-
 
 /// Delete a section from an SBE-XIP image in host memory
 ///
@@ -1200,8 +1117,8 @@ sbe_xip_duplicate_section(const void* i_image,
 /// - A scan program is appended to the image, or a run-time data area is
 /// allocated and cleared at the end of the image.
 ///
-/// - Pointer variables in the image are updated with PORE addresses obtained
-/// via sbe_xip_section2pore(), or
+/// - Pointer variables in the image are updated with IMAGE addresses obtained
+/// via sbe_xip_section2image(), or
 /// other procedure code initializes a newly allocated and cleared data area
 /// via host addresses obtained from sbe_xip_section2host().
 ///
@@ -1210,11 +1127,11 @@ sbe_xip_duplicate_section(const void* i_image,
 /// enforce these alignment constraints for all sections created by the API.
 /// All alignment is relative to the first byte of the image (\a io_image) -
 /// \e not to the current in-memory address of the image. By specification
-/// SBE-XIP images must be loaded at a 4K alignment in order for PORE hardware
+/// SBE-XIP images must be loaded at a 4K alignment in order for IMAGE hardware
 /// relocation to work, however the APIs don't require this 4K alignment for
-/// in-memory manipulation of images.  Images to be executed on PoreVe will
+/// in-memory manipulation of images.  Images to be executed on ImageVe will
 /// normally require at least 8-byte final aligment in order to guarantee that
-/// the PoreVe can execute an 8-byte fetch or load/store of the final
+/// the ImageVe can execute an 8-byte fetch or load/store of the final
 /// doubleword.
 ///
 /// \note If the TOC section is modified then the image is marked as having an
@@ -1235,7 +1152,7 @@ sbe_xip_append(void* io_image,
                uint32_t* o_sectionOffset);
 
 
-/// Convert an SBE-XIP section offset to a relocatable PORE address
+/// Convert an SBE-XIP section offset to a relocatable IMAGE address
 ///
 /// \param[in] i_image A pointer to an SBE-XIP image in host memory
 ///
@@ -1245,42 +1162,42 @@ sbe_xip_append(void* io_image,
 /// \param[in] i_offset An offset (in bytes) within the section.  At least one
 /// byte at \a i_offset must be currently allocated in the section.
 ///
-/// \param[in] o_poreAddress The equivalent relocatable PORE address is
-/// returned via this pointer. Since valid PORE addresses are always either
+/// \param[in] o_imageAddress The equivalent relocatable IMAGE address is
+/// returned via this pointer. Since valid IMAGE addresses are always either
 /// 4-byte (code) or 8-byte (data) aligned, this API checks the aligment of
-/// the translated address and returns SBE_XIP_ALIGNMENT_ERROR if the PORE
+/// the translated address and returns SBE_XIP_ALIGNMENT_ERROR if the IMAGE
 /// address is not at least 4-byte aligned.  Note that the translated address
 /// is still returned even if incorrectly aligned.
 ///
 /// This API is typically used to translate section offsets returned from
-/// sbe_xip_append() into relocatable PORE addresses.
+/// sbe_xip_append() into relocatable IMAGE addresses.
 ///
 /// \retval 0 Success
 ///
 /// \retval non-0 See \ref sbe_xip_image_errors
 int
-sbe_xip_section2pore(const void* i_image, 
+sbe_xip_section2image(const void* i_image, 
                      const int i_sectionId,
                      const uint32_t i_offset,
-                     uint64_t* o_poreAddress);
+                     uint64_t* o_imageAddress);
 
 
-/// Convert an SBE-XIP relocatable PORE address to a host memory address
+/// Convert an SBE-XIP relocatable image address to a host memory address
 ///
 /// \param[in] i_image A pointer to an SBE-XIP image in host memory.
 ///
-/// \param[in] i_poreAddress A relocatable PORE address putatively addressing
+/// \param[in] i_imageAddress A relocatable image address putatively addressing
 /// relocatable memory contained in the image.
 ///
 /// \param[out] o_hostAddress The API updates the location pointed to by \a
 /// o_hostAddress with the host address of the memory addressed by \a
-/// i_poreAddress.  In the event of an error (non-0 return code) the final
+/// i_imageAddress.  In the event of an error (non-0 return code) the final
 /// content of \a o_hostAddress is undefined.
 ///
-/// This API is typically used to translate relocatable PORE addresses stored
+/// This API is typically used to translate relocatable image addresses stored
 /// in the SBE-XIP image into the equivalent host address of the in-memory
 /// image, allowing host-code to manipulate arbitrary data structures in the
-/// image. If the \a i_poreAddress does not refer to memory within the image
+/// image. If the \a i_imageAddress does not refer to memory within the image
 /// (as determined by the link address and image size) then the
 /// SBE_XIP_INVALID_ARGUMENT error code is returned.
 ///
@@ -1288,32 +1205,32 @@ sbe_xip_section2pore(const void* i_image,
 ///
 /// \retval non-0 See \ref sbe_xip_image_errors
 int
-sbe_xip_pore2host(const void* i_image, 
-                  const uint64_t i_poreAddress,
+sbe_xip_image2host(const void* i_image, 
+                  const uint64_t i_imageAddress,
                   void** o_hostAddress);
 
 
-/// Convert an SBE-XIP relocatable PORE address to section Id and offset
+/// Convert an SBE-XIP relocatable image address to section Id and offset
 ///
 /// \param[in] i_image A pointer to an SBE-XIP image in host memory.
 ///
-/// \param[in] i_poreAddress A relocatable PORE address putatively addressing
+/// \param[in] i_imageAddress A relocatable image address putatively addressing
 /// relocatable memory contained in the image.
 ///
 /// \param[out] o_section The API updates the location pointed to by \a
 /// o_section with the section Id of the memory addressed by \a
-/// i_poreAddress.  In the event of an error (non-0 return code) the final
+/// i_imageAddress.  In the event of an error (non-0 return code) the final
 /// content of \a o_section is undefined.
 ///
 /// \param[out] o_offset The API updates the location pointed to by \a
-/// o_offset with the byte offset of the memory addressed by \a i_poreAddress
+/// o_offset with the byte offset of the memory addressed by \a i_imageAddress
 /// within \a o_section.  In the event of an error (non-0 return code) the
 /// final content of \a o_offset is undefined.
 ///
-/// This API is typically used to translate relocatable PORE addresses stored
+/// This API is typically used to translate relocatable image addresses stored
 /// in the SBE-XIP image into the equivalent section + offset form, allowing
 /// host-code to manipulate arbitrary data structures in the image. If the \a
-/// i_poreAddress does not refer to memory within the image (as determined by
+/// i_imageAddress does not refer to memory within the image (as determined by
 /// the link address and image size) then the SBE_XIP_INVALID_ARGUMENT error
 /// code is returned.
 ///
@@ -1321,28 +1238,28 @@ sbe_xip_pore2host(const void* i_image,
 ///
 /// \retval non-0 See \ref sbe_xip_image_errors
 int
-sbe_xip_pore2section(const void* i_image, 
-                     const uint64_t i_poreAddress,
+sbe_xip_image2section(const void* i_image, 
+                     const uint64_t i_imageAddress,
                      int* o_section,
                      uint32_t* o_offset);
 
 
-/// Convert an in-memory SBE-XIP host address to a relocatable PORE address
+/// Convert an in-memory SBE-XIP host address to a relocatable image address
 ///
 /// \param[in] i_image A pointer to an SBE-XIP image in host memory
 ///
 /// \param[in] i_hostAddress A host address addressing data within the image.
 ///
-/// \param[out] o_poreAddress The API updates the location pointed to by \a
-/// o_poreAddress with the equivelent relocatable PORE address of the memory
-/// addressed by i_hostAddress.  Since valid PORE addresses are always either
+/// \param[out] o_imageAddress The API updates the location pointed to by \a
+/// o_imageAddress with the equivelent relocatable image address of the memory
+/// addressed by i_hostAddress.  Since valid image addresses are always either
 /// 4-byte (code) or 8-byte (data) aligned, this API checks the aligment of
-/// the translated address and returns SBE_XIP_ALIGNMENT_ERROR if the PORE
+/// the translated address and returns SBE_XIP_ALIGNMENT_ERROR if the image
 /// address is not at least 4-byte aligned.  Note that the translated address
 /// is still returned evn if incorrectly aligned.
 ///
 /// This API is provided as a convenient way to convert host memory addresses
-/// for an in-memory SBE-XIP image into PORE addresses correctly relocated for
+/// for an in-memory SBE-XIP image into image addresses correctly relocated for
 /// the image, for example to update pointer variables in the image.  If the
 /// \a i_hostAddress does not refer to memory within the image (as determined
 /// by the image address and image size) then the SBE_XIP_INVALID_ARGUMENT
@@ -1352,9 +1269,9 @@ sbe_xip_pore2section(const void* i_image,
 ///
 /// \retval non-0 See \ref sbe_xip_image_errors
 int
-sbe_xip_host2pore(const void* i_image, 
+sbe_xip_host2image(const void* i_image, 
                   void* i_hostAddress,
-                  uint64_t* o_poreAddress);
+                  uint64_t* o_imageAddress);
 
 
 /// \defgroup sbe_xip_image_errors Error codes from SBE-XIP image APIs
@@ -1402,7 +1319,7 @@ sbe_xip_host2pore(const void* i_image,
 /// for those APIs that prohibit this.
 #define SBE_XIP_SECTION_ERROR 10
 
-/// An address translation API returned a PORE address that was not at least
+/// An address translation API returned a image address that was not at least
 /// 4-byte aligned, or alignment violations were observed by
 /// sbe_xip_validate() or sbe_xip_append().
 #define SBE_XIP_ALIGNMENT_ERROR 11
@@ -1628,7 +1545,7 @@ sbe_xip_host2pore(const void* i_image,
 /// \param[in] symbol The name of the scalar or vector; this name is also used
 /// as the TOC index of the data.
 ///
-/// \param[in] space A valid PORE memory space descriptor
+/// \param[in] space A valid image memory space descriptor
 ///
 /// \param[in] offset A 32-bit relocatable offset
 ///
diff --git a/src/ppe/sbe/image/topfiles.mk b/src/ppe/sbe/image/topfiles.mk
index bfcb577..cc31d9c 100644
--- a/src/ppe/sbe/image/topfiles.mk
+++ b/src/ppe/sbe/image/topfiles.mk
@@ -22,8 +22,8 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
-TOP-C-SOURCES = base_ppe_demo.c
-TOP-CPP-SOURCES = 
+TOP-C-SOURCES = sbe_loader.c
+TOP-CPP-SOURCES = sbe_main.C
 TOP-S-SOURCES = base_ppe_header.S
 
 TOP-FIXED-HEADERS += $(IMAGE_SRCDIR)/proc_sbe_fixed_perv.H
diff --git a/src/ppe/sbe/plat/include/README b/src/ppe/sbe/plat/include/README
new file mode 100644
index 0000000..4637505
--- /dev/null
+++ b/src/ppe/sbe/plat/include/README
@@ -0,0 +1,9 @@
+fapi2_hw_access.H is placed here to restore the return code get/putScom APIs 
+while allowing PPE Plat include directory to be before the Base HWPF in the 
+include path.
+
+1. SBE PLAT  (return codes)
+2, PPE PLAT  (no return codes) used by SGPE/PGPE/CME
+3. Base HWPF (return codes)
+
+This is a dual maintenance issue that should be reconsidered in the future.
diff --git a/src/ppe/sbe/plat/include/fapi2_hw_access.H b/src/ppe/sbe/plat/include/fapi2_hw_access.H
new file mode 100644
index 0000000..bc2d56b
--- /dev/null
+++ b/src/ppe/sbe/plat/include/fapi2_hw_access.H
@@ -0,0 +1,464 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/plat/include/fapi2_hw_access.H $                  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file fapi2_hw_access.H
+/// @brief Common file that defines the hardware access functions that
+/// platform code must implement.
+///
+
+#ifndef _FAPI2_COMMON_HWACCESS_H_
+#define _FAPI2_COMMON_HWACCESS_H_
+
+#ifdef FAPI_SUPPORT_SPY_AS_ENUM
+#include <spy_ids.H>
+typedef uint64_t spyId_t;
+#endif
+
+#include <stdint.h>
+#include <thread>
+#include <buffer.H>
+
+// variable_buffer isn't supported on PPE
+#ifndef __PPE__
+#include <variable_buffer.H>
+#endif
+
+#include <return_code.H>
+#include <target.H>
+#include <hw_access_def.H>
+#include <plat_hw_access.H>
+
+#ifdef FAPI_SUPPORT_MULTI_SCOM
+#include <multi_scom.H>
+#endif
+
+namespace fapi2
+{
+    //--------------------------------------------------------------------------
+    // PIB Error Functions
+    //--------------------------------------------------------------------------
+
+    /// @brief Sets the PIB error mask - platform dependant
+    /// @param[in]  i_mask     The new error mask
+    inline void setPIBErrorMask(uint8_t i_mask);
+
+    /// @brief Gets the PIB error mask - platform dependant
+    /// @return uint8_t The current PIB error mask
+    inline uint8_t getPIBErrorMask(void);
+
+    //--------------------------------------------------------------------------
+    // Operational Mode Error Functions
+    //--------------------------------------------------------------------------
+
+    /// @brief Sets the operational mode
+    /// @param[in]  i_mode     The new mode
+    inline void setOpMode(const OpModes i_mode);
+
+    /// @brief Gets the operational mode
+    /// @return the operational mode
+    inline OpModes getOpMode(void);
+
+    //--------------------------------------------------------------------------
+    // HW Communication Functions
+    //--------------------------------------------------------------------------
+
+    /// @brief Reads a SCOM register from a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target     HW target to operate on.
+    /// @param[in]  i_address    SCOM register address to read from.
+    /// @param[out] o_data       Buffer that holds data read from HW target.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode getScom(const Target<K>& i_target, const uint64_t i_address,
+                              buffer<uint64_t>& o_data);
+
+    /// @brief Writes a SCOM register on a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target     HW target to operate on.
+    /// @param[in] i_address    SCOM register address to write to.
+    /// @param[in] i_data       Buffer that holds data to write into address.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode putScom(const Target<K>& i_target, const uint64_t i_address,
+                              const buffer<uint64_t> i_data);
+
+    /// @brief Writes a SCOM register under mask on a chip
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target     HW target to operate on.
+    /// @param[in] i_address    SCOM register address to write to.
+    /// @param[in] i_data       Buffer that holds data to write into address.
+    /// @param[in] i_mask       Buffer that holds the mask value.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode putScomUnderMask(const Target<K>& i_target,
+                                       const uint64_t i_address,
+                                       const buffer<uint64_t> i_data,
+                                       const buffer<uint64_t> i_mask);
+
+    /// @brief Reads a CFAM register from a chip.
+    ///        CFAM register is 32-bit wide.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target  HW target to operate on.
+    /// @param[in]  i_address CFAM register address to read from.
+    /// @param[out] o_data    Buffer that holds data read from HW target.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode getCfamRegister(const Target<K>& i_target,
+                                      const uint32_t i_address,
+                                      buffer<uint32_t>& o_data);
+
+    /// @brief Writes a CFAM register on a chip.
+    ///        CFAM register is 32-bit wide.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target  HW target to operate on.
+    /// @param[in] i_address CFAM register address to write to.
+    /// @param[in] i_data    Buffer that holds data to write into address.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode putCfamRegister(const Target<K>& i_target,
+                                      const uint32_t i_address,
+                                      const buffer<uint32_t> i_data);
+
+    /// @brief Read-modify-write a CFAM register on a chip.
+    ///        CFAM register is 32-bit wide.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target     HW target to operate on.
+    /// @param[in] i_address    CFAM register address to modify.
+    /// @param[in] i_data       Buffer that holds data to be modified.
+    /// @param[in] i_modifyMode The modify mode (or/and/xor).
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode modifyCfamRegister(const Target<K>& i_target,
+                                         const uint32_t i_address,
+                                         const buffer<uint32_t> i_data,
+                                         const ChipOpModifyMode i_modifyMode);
+
+    // variable_buffer isn't supported on PPE
+#ifndef __PPE__
+    /// @brief Reads a ring from a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target   Target to operate on.
+    /// @param[in]  i_address  Ring address to read from.
+    /// @param[out] o_data     Buffer that holds data read from HW target.
+    /// @param[in]  i_ringMode Ring operation mode.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode getRing(const Target<K>& i_target,
+                              const scanRingId_t i_address,
+                              variable_buffer& o_data,
+                              const RingMode i_ringMode = 0);
+
+    /// @brief Writes a ring to a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target   Target to operate on.
+    /// @param[in] i_address  Ring address to write to.
+    /// @param[in] i_data     Buffer that contains RS4 compressed ring data
+    ///                       to write into address
+    /// @param[in] i_ringMode Ring operation mode.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode putRing(const Target<K>& i_target,
+                              const scanRingId_t i_address,
+                              const variable_buffer& i_data,
+                              const RingMode i_ringMode = 0);
+
+
+    /// @brief Read-modify-write a ring on a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target     Target to operate on.
+    /// @param[in] i_address    Ring address to modify.
+    /// @param[in] i_data       Buffer that contains RS4 compressed ring data
+    ///                         to be modified.
+    /// @param[in] i_modifyMode The modify mode (or/and/xor)
+    /// @param[in] i_ringMode   Ring operation mode.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode modifyRing(const Target<K>& i_target,
+                                 const scanRingId_t i_address,
+                                 const variable_buffer& i_data,
+                                 const ChipOpModifyMode i_modifyMode,
+                                 const RingMode i_ringMode = 0);
+#endif
+
+#ifdef FAPI_SUPPORT_MULTI_SCOM
+    /// @brief Performs a multiple SCOM operation
+    ///        This interface performs multiple SCOM operations on a chip in the
+    ///        order specified by the input MultiScom object.
+    ///        See fapiMultiScom.H for details of how to populate the MultiScom
+    ///        object with SCOM operations.
+    ///
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]     i_target Target to operate on.
+    /// @param[in,out] io_multiScomObj Reference to a MultiScom object,
+    ///                                pre-populated with SingleScomInfo entries
+    ///                                to perform multiple SCOMs on input target
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note   This is a synchronous interface and would return after all the
+    ///         SCOM operations are completed or on the first failed operation
+    ///
+    /// @note   SCOMs will be performed in the order they were added to the
+    ///         input MultiScom object
+    ///
+    /// @note   In case of errors, the platform code is responsible to collect
+    ///         and add all the required error info and FFDC into the error data
+    ///         for debugging
+    ///
+    /// @note   If the SCOM operations added are specific to a processor chip,
+    ///         then the FSI Shift Engine configured in scatter-gather DMA mode
+    ///         extension would be used to execute the SCOM operations in a
+    ///         performance optimize mode. In this mode, the special
+    ///         SCOM_BULK_READ_MODE and SCOM_BULK_WRITE_MODE operations are
+    ///         supported that allow a large bulk of SCOM access (in multiple of
+    ///         64 bits) for targets that support auto-increment. The
+    ///         SCOM_WRITE_UNDER_MASK operation is not supported in this mode
+    ///
+    /// @note   If the SCOM operations added are specific to a memory buffer
+    ///         chip, then the regular SCOM engine is used to execute the SCOM
+    ///         operations. SCOM_WRITE_UNDER_MASK operation is supported in
+    ///         this mode, but the special SCOM_BULK_READ_MODE and
+    ///         SCOM_BULK_WRITE_MODE operations are not supported due to
+    ///         hardware limitations.
+    ///
+    template< TargetType K >
+    fapi2::ReturnCode multiScom (const Target<K>& i_target,
+                                 MultiScom&  io_multiScomObj);
+#endif
+
+    // --------------------------------------------------------------------------
+    // NOTE:
+    // Implement platform Spy access functions if platform supports them.
+    // --------------------------------------------------------------------------
+
+    // variable_buffer isn't supported on PPE
+#ifndef __PPE__
+    /// @brief Reads a spy from a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target   Target to operate on.
+    /// @param[in]  i_spyId    Id of the spy whose data to be read.
+    /// @param[out] o_data     Buffer that holds data read from HW target.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note:  The string version is only supported for cronus.
+    ///
+    ///         The fapi design to support both FSP and cronus use of get and
+    ///         put spy functions is dependant on the SPY names being expanded
+    ///         to resemble a valid C identifier. This design places some
+    ///         restrictions on the SPY names which can be used.
+    ///
+    ///         1. if the spy name contains a # procedure writers should replace
+    ///         it with an __P__ for example -
+    ///
+    ///         ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+    ///         becomes
+    ///         ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS
+    ///
+    ///         2. if the spy name has a number following a "." it must have an
+    ///         underscore prepended to the number.
+    ///
+    ///         EH.TPCHIP.2KX100_ARY_CLK_EDGES_DLY
+    ///         becomes
+    ///         EH.TPCHIP._2KX100_ARY_CLK_EDGES_DLY
+    ///
+    ///         Example SPY name:
+    ///         The hardware procedure should call the function like:
+    ///
+    ///          ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+    ///
+    ///          fapi2::ReturnCode rc = fapiGetSpy( targ,
+    ///                  ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS, data );
+    ///
+    /// @note The ID is not in quotes the fapi code will handle adding
+    ///       the quotes for the cronus environment
+#if defined(FAPI_SUPPORT_SPY_AS_ENUM) || defined(DOXYGEN)
+
+#define FAPI_GET_SPY(TARGET, ID, DATA) fapi2::getSpy(TARGET, FAPI_SPY_NAMES::ID.value, DATA)
+
+    template< TargetType K >
+    inline ReturnCode getSpy(const Target<K>& i_target,
+                             const spyId_t i_spyId,
+                             variable_buffer& o_data);
+#endif
+
+#if defined(FAPI_SUPPORT_SPY_AS_STRING) || defined(DOXYGEN)
+
+#define FAPI_GET_SPY(TARGET, ID, DATA) fapi2::getSpy(TARGET, #ID, DATA)
+
+    template< TargetType K >
+    inline ReturnCode getSpy(const Target<K>& i_target,
+                             const char * const i_spyId,
+                             variable_buffer& o_data);
+#endif
+
+    /// @brief Writes a spy on a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target   Target to operate on.
+    /// @param[in]  i_spyId    Id of the spy to write data to.
+    /// @param[out] i_data     Buffer that holds data to write into spy.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note:  The string version is only supported for cronus.
+    ///
+    ///         The fapi design to support both FSP and cronus use of get and
+    ///         put spy functions is dependent on the SPY names being expanded
+    ///         to resemble a valid C identifier. This design places some
+    ///         restrictions on the SPY names which can be used.
+    ///
+    ///         1. if the spy name contains a # procedure writers should replace
+    ///         is with an __P__ for example -
+    ///
+    ///         ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+    ///         becomes
+    ///         ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS
+    ///
+    ///         2. if the spy name has a number following a "." it must have an
+    ///         underscore prepended to the number.
+    ///
+    ///         EH.TPCHIP.2KX100_ARY_CLK_EDGES_DLY
+    ///         becomes
+    ///         EH.TPCHIP._2KX100_ARY_CLK_EDGES_DLY
+    ///
+    ///         Example SPY name:
+    ///         The hardware procedure should call the function like:
+    ///
+    ///          ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+    ///
+    ///          fapi2::ReturnCode rc = fapiPutSpy( targ,
+    ///                  ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS, data );
+    ///
+    /// @note The ID is not in quotes the fapi code will handle adding
+    ///         the quotes for the cronus environment
+    ///
+#if defined(FAPI_SUPPORT_SPY_AS_ENUM) || defined(DOXYGEN)
+
+#define FAPI_PUT_SPY(TARGET, ID, DATA) fapi2::putSpy(TARGET, FAPI_SPY_NAMES::ID.value, DATA)
+
+    template< TargetType K >
+    inline ReturnCode putSpy(const Target<K>& i_target,
+                             const spyId_t i_spyId,
+                             variable_buffer& i_data);
+#endif
+
+#if defined(FAPI_SUPPORT_SPY_AS_STRING) || defined(DOXYGEN)
+
+#define FAPI_PUT_SPY(TARGET, ID, DATA) fapi2::putSpy(TARGET, #ID, DATA)
+
+    template< TargetType K >
+    inline ReturnCode putSpy(const Target<K>& i_target,
+                             const char* const i_spyId,
+                             variable_buffer& i_data);
+#endif
+
+    /// @brief Writes spy data into a buffer holding ring data image
+    ///        This API is used by L2/L3 repair to put column repair data
+    ///        into a ring buffer image.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target Target to operate on.
+    /// @param[in]  i_spyId  Id of the spy.
+    /// @param[in]  i_data   Buffer that holds spy data to write into ring
+    ///                      image.
+    /// @param[out] o_data   Buffer that holds updated ring image.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note:  The string version is only supported for cronus.
+    ///
+    ///         The fapi design to support both FSP and cronus use of get and
+    ///         put spy functions is dependent on the SPY names being expanded
+    ///         to resemble a valid C identifier. This design places some
+    ///         restrictions on the SPY names which can be used.
+    ///
+    ///         See fapiPutSpy for details on spy id specifics.
+    ///
+#if defined(FAPI_SUPPORT_SPY_AS_ENUM) || defined(DOXYGEN)
+
+#define FAPI_PUT_SPY_IMAGE(TARGET, ID, DATA1, DATA2)                    \
+    fapi2::putSpyImage(TARGET, FAPI_SPY_NAMES::ID.value,                \
+                       DATA1, DATA2)
+
+    template< TargetType K >
+    inline ReturnCode putSpyImage(const Target<K>& i_target,
+                                  const spyId_t i_spyId,
+                                  const variable_buffer& i_data,
+                                  variable_buffer& o_imageData);
+#endif
+
+#if defined(FAPI_SUPPORT_SPY_AS_STRING) || defined(DOXYGEN)
+
+#define FAPI_PUT_SPY_IMAGE(TARGET, ID, DATA1, DATA2) \
+    fapi2::putSpyImage(TARGET, #ID, DATA1,DATA2)
+
+    template< TargetType K >
+    inline ReturnCode putSpyImage(const Target<K>& i_target,
+                                  const char* const i_spyId,
+                                  const variable_buffer& i_data,
+                                  variable_buffer& o_imageData);
+#endif
+
+    /// @brief Reads spy data from a ring image buffer
+    /// @param[in]   i_target      Target to operate on
+    /// @param[in]   i_spyId       The spy's id
+    /// @param[out]  o_data        Buffer that holds data read from ring image.
+    /// @param[in]   i_imageData   Buffer that holds ring image to read data
+    ///                            from.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note:  The string version is only supported for cronus.
+    ///
+    ///         The fapi design to support both FSP and cronus use of get and
+    ///         put spy functions is dependent on the SPY names being expanded
+    ///         to resemble a valid C identifier. This design places some
+    ///         restrictions on the SPY names which can be used.
+    ///
+    ///         See fapiPutSpy for details on spy id specifics.
+    ///
+#if defined(FAPI_SUPPORT_SPY_AS_ENUM) || defined(DOXYGEN)
+
+#define FAPI_GET_SPY_IMAGE(TARGET, ID, DATA1, DATA2)    \
+    fapi2:getSpyImage(TARGET, FAPI_SPY_NAMES::ID.value, \
+                      DATA1, DATA2)
+
+    template< TargetType K >
+    inline ReturnCode getSpyImage(const Target<K>& i_target,
+                                  const spyId_t i_spyId,
+                                  variable_buffer& o_data,
+                                  const variable_buffer& i_imageData);
+#endif
+
+#if defined(FAPI_SUPPORT_SPY_AS_STRING) || defined(DOXYGEN)
+
+#define FAPI_GET_SPY_IMAGE(TARGET, ID, DATA1, DATA2) \
+    fapi2::getSpyImage(TARGET, #ID, DATA1,DATA2)
+
+    template< TargetType K >
+    inline ReturnCode getSpyImage(const Target<K>& i_target,
+                                  const char * const i_spyId,
+                                  variable_buffer& o_data,
+                                  const variable_buffer& i_imageData);
+#endif
+
+#endif // PPE
+};
+
+#endif // _FAPI2_HWACCESS_H_
diff --git a/src/ppe/sbe/plat/include/hw_access.H b/src/ppe/sbe/plat/include/hw_access.H
new file mode 100644
index 0000000..0f380e0
--- /dev/null
+++ b/src/ppe/sbe/plat/include/hw_access.H
@@ -0,0 +1,619 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/plat/include/hw_access.H $                        */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ *  @file hw_access.H
+ *
+*  @brief Defines the hardware access functions that platform code must
+ *         implement.
+ */
+
+#ifndef FAPI2_HWACCESS_H_
+#define FAPI2_HWACCESS_H_
+
+
+// variable_buffer isn't supported on PPE
+#ifndef __PPE__
+#include <variable_buffer.H>
+#endif
+
+#include <utils.H>
+#include <plat_hw_access.H>
+#include <fapi2_hw_access.H>
+
+namespace fapi2
+{
+
+    //--------------------------------------------------------------------------
+    // PIB Error Functions
+    //--------------------------------------------------------------------------
+
+    /// @brief Sets the PIB error mask - platform dependant
+    /// @param[in]  i_mask     The new error mask
+    void setPIBErrorMask(uint8_t i_mask)
+    {       
+        PLAT_SET_PIB_ERROR_MASK(i_mask);
+    }
+
+    /// @brief Gets the PIB error mask - platform dependant
+    /// @return uint8_t The current PIB error mask
+    uint8_t getPIBErrorMask(void)
+    {
+        PLAT_GET_PIB_ERROR_MASK(o_pib_mask);
+        return o_pib_mask;
+    }
+
+    //--------------------------------------------------------------------------
+    // Operational Mode Error Functions
+    //--------------------------------------------------------------------------
+
+    /// @brief Sets the operational mode
+    /// @param[in]  i_mode     The new mode
+    // note: this can be moved  to a C file if desired
+    inline void setOpMode(const OpModes i_mode)
+    {
+        // Keeps the compiler from complaining about the unused i_mode
+        static_cast<void>(i_mode);
+
+        // No-op for now. Should set thread-local operational mode
+        return;
+    }
+
+    /// @brief Gets the operational mode
+    /// @return the operational mode
+    // note: this can be moved  to a C file if desired
+    inline OpModes getOpMode(void)
+    {
+        // No-op for now. Should read thread-local operational mode
+        return NORMAL;
+    }
+
+    //--------------------------------------------------------------------------
+    // HW Communication Functions
+    //--------------------------------------------------------------------------
+
+    /// @brief Reads a SCOM register from a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target     HW target to operate on.
+    /// @param[in]  i_address    SCOM register address to read from.
+    /// @param[out] o_data       Buffer that holds data read from HW target.
+    /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode  getScom(const Target<K>& i_target, const uint64_t i_address,
+                       buffer<uint64_t>& o_data)
+    {
+        fapi2::ReturnCode l_rc;
+        PLAT_GETSCOM(l_rc,
+                     i_target,
+                     i_address,
+                     &(o_data()));
+
+        return l_rc;
+    }
+
+    /// @brief Writes a SCOM register on a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target     HW target to operate on.
+    /// @param[in] i_address    SCOM register address to write to.
+    /// @param[in] i_data       Buffer that holds data to write into address.
+    /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode  putScom(const Target<K>& i_target, const uint64_t i_address,
+                       const buffer<uint64_t> i_data)
+    {
+        fapi2::ReturnCode l_rc;
+        PLAT_PUTSCOM(l_rc,
+                    i_target,
+                    i_address,
+                    i_data());
+
+        return l_rc;
+    }
+
+    /// @brief Read-modify-write a SCOM register on a chip
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target     HW target to operate on.
+    /// @param[in] i_address    SCOM register address to write to.
+    /// @param[in] i_data       Buffer that holds data to be modified.
+    /// @param[in] i_modifyMode The modify mode (or/and/xor).
+    /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode modifyScom(const Target<K>& i_target,
+                                 const uint64_t i_address,
+                                 const buffer<uint64_t> i_data,
+                                 const ChipOpModifyMode i_modifyMode)
+    {
+        fapi2::buffer<uint64_t> l_modifyDataBuffer;
+        
+        fapi2::ReturnCode l_rc;     
+        PLAT_GETSCOM(l_rc,
+                     i_target,
+                     (uint32_t)(i_address & BITS(40,24)),
+                      &(l_modifyDataBuffer())); 
+        if (l_rc) goto __fapi2exit__;
+
+        if ( i_modifyMode == CHIP_OP_MODIFY_MODE_OR)
+        {
+            l_modifyDataBuffer |= i_data;
+        }
+
+        if ( i_modifyMode == CHIP_OP_MODIFY_MODE_AND)
+        {
+            l_modifyDataBuffer &= i_data;
+        }
+
+        if ( i_modifyMode == CHIP_OP_MODIFY_MODE_XOR)
+        {
+            l_modifyDataBuffer ^= i_data;
+        }
+       
+        PLAT_PUTSCOM(l_rc,
+                     i_target,
+                     (uint32_t)(i_address & BITS(40,24)),
+                      l_modifyDataBuffer()); 
+        if (l_rc) goto __fapi2exit__;                 
+
+
+__fapi2exit__:
+        return l_rc;
+
+    }
+
+    /// @brief Writes a SCOM register under mask on a chip
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target     HW target to operate on.
+    /// @param[in] i_address    SCOM register address to write to.
+    /// @param[in] i_data       Buffer that holds data to write into address.
+    /// @param[in] i_mask       Buffer that holds the mask value.
+    /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode putScomUnderMask( const Target<K>& i_target,
+                                        const uint64_t i_address,
+                                        buffer<uint64_t> i_data,
+                                        buffer<uint64_t> i_mask)
+    {
+        fapi2::buffer<uint64_t> l_modifyDataBuffer = i_data;
+
+        l_modifyDataBuffer &= i_mask;
+       
+        fapi2::ReturnCode l_rc;   
+        PLAT_PUTSCOM(l_rc,
+                     i_target,
+                    (uint32_t)(i_address & BITS(40,24)),
+                     l_modifyDataBuffer());
+
+        return l_rc;
+
+    }
+          
+
+    /// @brief Reads a CFAM register from a chip.
+    ///        CFAM register is 32-bit wide.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target  HW target to operate on.
+    /// @param[in]  i_address CFAM register address to read from.
+    /// @param[out] o_data    Buffer that holds data read from HW target.
+    /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode getCfamRegister(const Target<K>& i_target,
+                               const uint32_t i_address,
+                               buffer<uint32_t>& o_data)
+    {
+        PLAT_GETCFAM(i_target.get(),
+                    (uint32_t)(i_address & BITS(40,24)),
+                    &(o_data()));
+
+        return FAPI2_RC_SUCCESS;
+    }
+
+    /// @brief Writes a CFAM register on a chip.
+    ///        CFAM register is 32-bit wide.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target  HW target to operate on.
+    /// @param[in] i_address CFAM register address to write to.
+    /// @param[in] i_data    Buffer that holds data to write into address.
+    /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode putCfamRegister(const Target<K>& i_target,
+                               const uint32_t i_address,
+                               buffer<uint32_t>& i_data)
+    {
+        PLAT_PUTCFAM(i_target.get(),
+                    (uint32_t)(i_address & BITS(40,24)),
+                    &(i_data()));
+
+        return FAPI2_RC_SUCCESS;
+    }
+
+    /// @brief Read-modify-write a CFAM register on a chip.
+    ///        CFAM register is 32-bit wide.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target     HW target to operate on.
+    /// @param[in] i_address    CFAM register address to modify.
+    /// @param[in] i_data       Buffer that holds data to be modified.
+    /// @param[in] i_modifyMode The modify mode (or/and/xor).
+    /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode modifyCfamRegister(const Target<K>& i_target,
+                                         const uint32_t i_address,
+                                         const buffer<uint32_t>& i_data,
+                                         const ChipOpModifyMode i_modifyMode)
+    {
+        PLAT_MODCFAM(i_target.get(),
+                    (uint32_t)(i_address & BITS(40,24)),
+                    &(i_data()),
+                    i_modifyMode);
+
+        return FAPI2_RC_SUCCESS;
+    }
+
+    // variable_buffer isn't supported on PPE
+#ifndef __PPE__
+    /// @brief Reads a ring from a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target   Target to operate on.
+    /// @param[in]  i_address  Ring address to read from.
+    /// @param[out] o_data     Buffer that holds data read from HW target.
+    /// @param[in]  i_ringMode Ring operation mode.
+    /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode getRing(const Target<K>& i_target,
+                       const scanRingId_t i_address,
+                       variable_buffer& o_data,
+                       const RingMode i_ringMode = 0)
+    {
+        o_data.setBit(0);
+        o_data.setBit(3);
+#ifndef __PPE__
+        std::cout << std::hex << "   getRing "
+                  << "target: {" << i_target.getType() << ","
+                  << uint64_t(i_target) << "}; "
+                  << "ring address: " << i_address << "; "
+                  << "ring mode: " << i_ringMode << "; "
+                  << "output data:";
+                  o_data.print();
+#endif
+
+        return FAPI2_RC_SUCCESS;
+    }
+
+    /// @brief Writes a ring to a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target   Target to operate on.
+    /// @param[in] i_address  Ring address to write to.
+    /// @param[in] i_data     Buffer that contains RS4 compressed ring data
+    ///                       to write into address
+    /// @param[in] i_ringMode Ring operation mode.
+    /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode putRing(const Target<K>& i_target,
+                              const scanRingId_t i_address,
+                              variable_buffer& i_data,
+                              const RingMode i_ringMode = 0)
+    {
+
+        return FAPI2_RC_SUCCESS;
+    }
+
+
+    /// @brief Writes a ring to a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target   Target to operate on.
+    /// @param[in] i_address  Ring address to write to.
+    /// @param[in] i_data     Pointer to location that contains RS4 compressed
+    //  ring data to write into address
+    /// @param[in] i_ringMode Ring operation mode.
+    /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode putRing(const Target<K>& i_target,
+                              const scanRingId_t i_address,
+                              const void* i_data,
+                              const RingMode i_ringMode = 0)
+    {
+        uint64_t* dataPtr =   reinterpret_cast<uint64_t*>(const_cast<void*>(i_data));
+
+       return FAPI2_RC_SUCCESS;
+    }
+
+    /// @brief Read-modify-write a ring on a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in] i_target     Target to operate on.
+    /// @param[in] i_address    Ring address to modify.
+    /// @param[in] i_data       Buffer that contains RS4 compressed ring data
+    ///                         to be modified.
+    /// @param[in] i_modifyMode The modify mode (or/and/xor)
+    /// @param[in] i_ringMode   Ring operation mode.
+    /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    template< TargetType K >
+    inline ReturnCode modifyRing(const Target<K>& i_target,
+                                 const scanRingId_t i_address,
+                                 variable_buffer& i_data,
+                                 const ChipOpModifyMode i_modifyMode,
+                                 const RingMode i_ringMode = 0)
+    {
+
+        return FAPI2_RC_SUCCESS;
+    }
+#endif
+
+
+#ifdef FAPI_SUPPORT_MULTI_SCOM
+    /// @brief Performs a multiple SCOM operation
+    ///        This interface performs multiple SCOM operations on a chip in the
+    ///        order specified by the input MultiScom object.
+    ///        See fapiMultiScom.H for details of how to populate the MultiScom
+    ///        object with SCOM operations.
+    ///
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]     i_target Target to operate on.
+    /// @param[in,out] io_multiScomObj Reference to a MultiScom object,
+    ///                                pre-populated with SingleScomInfo entries
+    ///                                to perform multiple SCOMs on input target
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note   This is a synchronous interface and would return after all the
+    ///         SCOM operations are completed or on the first failed operation
+    ///
+    /// @note   SCOMs will be performed in the order they were added to the
+    ///         input MultiScom object
+    ///
+    /// @note   In case of errors, the platform code is responsible to collect
+    ///         and add all the required error info and FFDC into the error data
+    ///         for debugging
+    ///
+    /// @note   If the SCOM operations added are specific to a processor chip,
+    ///         then the FSI Shift Engine configured in scatter-gather DMA mode
+    ///         extension would be used to execute the SCOM operations in a
+    ///         performance optimize mode. In this mode, the special
+    ///         SCOM_BULK_READ_MODE and SCOM_BULK_WRITE_MODE operations are
+    ///         supported that allow a large bulk of SCOM access (in multiple of
+    ///         64 bits) for targets that support auto-increment. The
+    ///         SCOM_WRITE_UNDER_MASK operation is not supported in this mode
+    ///
+    /// @note   If the SCOM operations added are specific to a memory buffer
+    ///         chip, then the regular SCOM engine is used to execute the SCOM
+    ///         operations. SCOM_WRITE_UNDER_MASK operation is supported in
+    ///         this mode, but the special SCOM_BULK_READ_MODE and
+    ///         SCOM_BULK_WRITE_MODE operations are not supported due to
+    ///         hardware limitations.
+    ///
+    template< TargetType K >
+    fapi2::ReturnCode multiScom (const Target<K>& i_target,
+                                 MultiScom&  io_multiScomObj)
+    {
+    }
+#endif
+
+    // --------------------------------------------------------------------------
+    // NOTE:
+    // Implement platform Spy access functions if platform supports them.
+    // --------------------------------------------------------------------------
+
+    // variable_buffer isn't supported on PPE
+#ifndef __PPE__
+    /// @brief Reads a spy from a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target   Target to operate on.
+    /// @param[in]  i_spyId    Id of the spy whose data to be read.
+    /// @param[out] o_data     Buffer that holds data read from HW target.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note:  The string version is only supported for cronus.
+    ///
+    ///         The fapi design to support both FSP and cronus use of get and
+    ///         put spy functions is dependant on the SPY names being expanded
+    ///         to resemble a valid C identifier. This design places some
+    ///         restrictions on the SPY names which can be used.
+    ///
+    ///         1. if the spy name contains a # procedure writers should replace
+    ///         it with an __P__ for example -
+    ///
+    ///         ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+    ///         becomes
+    ///         ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS
+    ///
+    ///         2. if the spy name has a number following a "." it must have an
+    ///         underscore prepended to the number.
+    ///
+    ///         EH.TPCHIP.2KX100_ARY_CLK_EDGES_DLY
+    ///         becomes
+    ///         EH.TPCHIP._2KX100_ARY_CLK_EDGES_DLY
+    ///
+    ///         Example SPY name:
+    ///         The hardware procedure should call the function like:
+    ///
+    ///          ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+    ///
+    ///          fapi2::ReturnCode rc = fapiGetSpy( targ,
+    ///                  ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS, data );
+    ///
+    /// @note The ID is not in quotes the fapi code will handle adding
+    ///       the quotes for the cronus environment
+    ///
+#ifdef FAPI_SUPPORT_SPY_AS_ENUM
+    template< TargetType K >
+    inline ReturnCode getSpy(const Target<K>& i_target,
+                             const spyId_t i_spyId,
+                             variable_buffer& o_data)
+    {
+        static_assert(K == 0, "implement getSpy (string)");
+        return ~FAPI2_RC_SUCCESS;
+    }
+#endif
+#ifdef FAPI_SUPPORT_SPY_AS_STRING
+    template< TargetType K >
+    inline ReturnCode getSpy(const Target<K>& i_target,
+                             const char * const i_spyId,
+                             variable_buffer& o_data)
+    {
+        static_assert(K == 0, "implement getSpy (string)");
+        return ~FAPI2_RC_SUCCESS;
+    }
+#endif
+    /// @brief Writes a spy on a chip.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target   Target to operate on.
+    /// @param[in]  i_spyId    Id of the spy to write data to.
+    /// @param[out] i_data     Buffer that holds data to write into spy.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note:  The string version is only supported for cronus.
+    ///
+    ///         The fapi design to support both FSP and cronus use of get and
+    ///         put spy functions is dependent on the SPY names being expanded
+    ///         to resemble a valid C identifier. This design places some
+    ///         restrictions on the SPY names which can be used.
+    ///
+    ///         1. if the spy name contains a # procedure writers should replace
+    ///         is with an __P__ for example -
+    ///
+    ///         ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+    ///         becomes
+    ///         ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS
+    ///
+    ///         2. if the spy name has a number following a "." it must have an
+    ///         underscore prepended to the number.
+    ///
+    ///         EH.TPCHIP.2KX100_ARY_CLK_EDGES_DLY
+    ///         becomes
+    ///         EH.TPCHIP._2KX100_ARY_CLK_EDGES_DLY
+    ///
+    ///         Example SPY name:
+    ///         The hardware procedure should call the function like:
+    ///
+    ///          ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+    ///
+    ///          fapi2::ReturnCode rc = fapiPutSpy( targ,
+    ///                  ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS, data );
+    ///
+    /// @note The ID is not in quotes the fapi code will handle adding
+    ///         the quotes for the cronus environment
+    ///
+#ifdef FAPI_SUPPORT_SPY_AS_ENUM
+    template< TargetType K >
+    inline ReturnCode putSpy(const Target<K>& i_target,
+                             const spyId_t i_spyId,
+                             variable_buffer& i_data)
+    {
+        static_assert(K == 0, "implement putSpy (enum)");
+        return ~FAPI2_RC_SUCCESS;
+    }
+#endif
+#ifdef FAPI_SUPPORT_SPY_AS_STRING
+    template< TargetType K >
+    inline ReturnCode putSpy(const Target<K>& i_target,
+                             const char* const i_spyId,
+                             variable_buffer& i_data)
+    {
+        static_assert(K == 0, "implement putSpy (string)");
+        return ~FAPI2_RC_SUCCESS;
+    }
+#endif
+    /// @brief Writes spy data into a buffer holding ring data image
+    ///        This API is used by L2/L3 repair to put column repair data
+    ///        into a ring buffer image.
+    /// @tparam K template parameter, passed in target.
+    /// @param[in]  i_target Target to operate on.
+    /// @param[in]  i_spyId  Id of the spy.
+    /// @param[in]  i_data   Buffer that holds spy data to write into ring
+    ///                      image.
+    /// @param[out] o_data   Buffer that holds updated ring image.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note:  The string version is only supported for cronus.
+    ///
+    ///         The fapi design to support both FSP and cronus use of get and
+    ///         put spy functions is dependent on the SPY names being expanded
+    ///         to resemble a valid C identifier. This design places some
+    ///         restrictions on the SPY names which can be used.
+    ///
+    ///         See fapiPutSpy for details on spy id specifics.
+    ///
+#ifdef FAPI_SUPPORT_SPY_AS_ENUM
+    template< TargetType K >
+    inline ReturnCode putSpyImage(const Target<K>& i_target,
+                                  const spyId_t i_spyId,
+                                  const variable_buffer& i_data,
+                                  variable_buffer& o_imageData)
+    {
+        static_assert(K == 0, "implement putSpyImage (enum)");
+        return ~FAPI2_RC_SUCCESS;
+    }
+#endif
+#ifdef FAPI_SUPPORT_SPY_AS_STRING
+    template< TargetType K >
+    inline ReturnCode putSpyImage(const Target<K>& i_target,
+                                  const char* const i_spyId,
+                                  const variable_buffer& i_data,
+                                  variable_buffer& o_imageData)
+    {
+        static_assert(K == 0, "implement putSpyImage (string)");
+        return ~FAPI2_RC_SUCCESS;
+    }
+#endif
+    /// @brief Reads spy data from a ring image buffer
+    /// @param[in]   i_target      Target to operate on
+    /// @param[in]   i_spyId       The spy's id
+    /// @param[out]  o_data        Buffer that holds data read from ring image.
+    /// @param[in]   i_imageData   Buffer that holds ring image to read data
+    ///                            from.
+    /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    /// @note:  The string version is only supported for cronus.
+    ///
+    ///         The fapi design to support both FSP and cronus use of get and
+    ///         put spy functions is dependent on the SPY names being expanded
+    ///         to resemble a valid C identifier. This design places some
+    ///         restrictions on the SPY names which can be used.
+    ///
+    ///         See fapiPutSpy for details on spy id specifics.
+    ///
+#ifdef FAPI_SUPPORT_SPY_AS_ENUM
+    template< TargetType K >
+    inline ReturnCode getSpyImage(const Target<K>& i_target,
+                                  const spyId_t i_spyId,
+                                  variable_buffer& o_data,
+                                  const variable_buffer& i_imageData)
+    {
+        static_assert(K == 0, "implement getSpyImage (enum)");
+        return ~FAPI2_RC_SUCCESS;
+    }
+#endif
+#ifdef FAPI_SUPPORT_SPY_AS_STRING
+    template< TargetType K >
+    inline ReturnCode getSpyImage(const Target<K>& i_target,
+                                  const char * const i_spyId,
+                                  variable_buffer& o_data,
+                                  const variable_buffer& i_imageData)
+    {
+        static_assert(K == 0, "implement getSpyImage (string)");
+        return ~FAPI2_RC_SUCCESS;
+    }
+#endif
+
+#endif // PPE
+
+};
+
+#endif // _FAPI2_HWACCESS_H_
diff --git a/src/ppe/sbe/plat/include/plat_error_scope.H b/src/ppe/sbe/plat/include/plat_error_scope.H
new file mode 100644
index 0000000..a44ba74
--- /dev/null
+++ b/src/ppe/sbe/plat/include/plat_error_scope.H
@@ -0,0 +1,71 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/plat/include/plat_error_scope.H $                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file plat_error_scope.H
+ * @brief platform definitions which create a scope for automatic error handling
+ */
+
+#ifndef __FAPI2_PLAT_ERROR_SCOPE__
+#define __FAPI2_PLAT_ERROR_SCOPE__
+
+/// @cond
+#define PLAT_FAPI_TRY_NO_TRACE( __operation__ )                         \
+    if ((fapi2::current_err = (__operation__)) != fapi2::FAPI2_RC_SUCCESS) \
+    {                                                                   \
+        goto fapi_try_exit;                                             \
+    }
+
+#define PLAT_FAPI_TRY_TRACE( __operation__, ... )                       \
+    if ((fapi2::current_err = (__operation__)) != fapi2::FAPI2_RC_SUCCESS) \
+    {                                                                   \
+        FAPI_ERR(__VA_ARGS__);                                          \
+        goto fapi_try_exit;                                             \
+    }
+
+///
+/// @brief Assert a conditional is true.
+/// If it is not, the FFDC gathering function is called and the
+/// trace is output as a FAPI error trace.
+/// @param[in] __conditional__ the condition to assert
+/// @param[in] __ffdc__ the FFDC gathering function
+/// @param[in] ... varargs, as input to FAPI_ERR
+///
+#define PLAT_FAPI_ASSERT( __conditional__, __ffdc__, ... )      \
+    if (! (__conditional__))                                    \
+    {                                                           \
+        (__ffdc__).execute();                                   \
+        FAPI_ERR(__VA_ARGS__);                                  \
+        goto fapi_try_exit;                                     \
+    }
+    
+    
+///
+/// @brief Temporary macro for error label until all are removed.
+/// @todo REMOVE this in time.
+#define FAPI_CLEANUP()   \
+fapi_try_exit:
+/// @endcond
+
+#endif
diff --git a/src/ppe/sbe/plat/include/plat_hw_access.H b/src/ppe/sbe/plat/include/plat_hw_access.H
new file mode 100644
index 0000000..f8efc4f
--- /dev/null
+++ b/src/ppe/sbe/plat/include/plat_hw_access.H
@@ -0,0 +1,94 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/plat/include/plat_hw_access.H $                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ *  @file plat_hw_access.H
+ *
+ *  @brief Define platform specific calls for hardware accesses.
+ */
+
+#ifndef PLATHWACCESS_H_
+#define PLATHWACCESS_H_
+
+#include <plat_includes.H>
+
+/// PIB Error Mask
+
+#define PLAT_SET_PIB_ERROR_MASK(_m_mask) \
+    {   /*  Read MSR */ \
+        uint32_t msr_data = mfmsr(); \
+        /* Set SEM field */ \
+        msr_data &= ~(BITS(0,8)); \
+        msr_data |= (uint32_t)(i_mask << 24); \
+        /* Write MSR */ \
+        mtmsr(msr_data); \
+    };
+    
+#define PLAT_GET_PIB_ERROR_MASK(_m_mask) \
+        uint8_t _m_mask; \
+        uint32_t _sem = mfmsr(); \
+        _m_mask = (uint8_t)((_sem & MSR_SEM) >> (32-(MSR_SEM_START_BIT + MSR_SEM_LEN)));
+        
+// Building block PPE instructions
+#define PPE_MFMSR(_m_data) \
+asm volatile \
+    ( \
+    "mfmsr %[data] \n" \
+    :  [data]"=&r"(*_m_data) \
+    :  "[data]"(*_m_data) \
+    );
+
+#define PPE_MTMSR(_m_data) \
+asm volatile \
+    ( \
+    "mtmsr %[data] \n" \
+    :  [data]"=&r"(*_m_data) \
+    :  "[data]"(*_m_data) \
+    );
+
+/// GetScom
+#define PLAT_GETSCOM(_m_rc, _m_base, _m_offset, _m_data) \
+    _m_rc = getscom(_m_base.getAddressOverlay(), (uint32_t)(_m_offset & BITS(40,24)), _m_data);
+    
+/// PutScom
+#define PLAT_PUTSCOM(_m_rc, _m_base, _m_offset, _m_data) \
+    _m_rc = putscom(_m_base.getAddressOverlay(), (uint32_t)(_m_offset & BITS(40,24)), _m_data);
+    
+/// GetCFAM  
+#define PLAT_GETCFAM(_m_base, _m_offset, _m_data) \
+    static_assert( K == TARGET_TYPE_NONE, \
+                  "getCfamRegister is not supported by PPE platforms")
+
+/// PutCFAM
+#define PLAT_PUTCFAM(_m_base, _m_offset, _m_data) \
+     static_assert( K == TARGET_TYPE_NONE, \
+                  "putCfamRegister is not supported by PPE platforms")
+                  
+/// ModifyCFAM
+#define PLAT_MODCFAM(_m_base, _m_offset, _m_data, _m_mode) \
+     static_assert( K == TARGET_TYPE_NONE, \
+                  "modifyCfamRegister is not supported by PPE platforms")
+
+#endif // PLATHWACCESS_H_
+
diff --git a/src/ppe/sbe/plat/src/Makefile b/src/ppe/sbe/plat/src/Makefile
new file mode 100644
index 0000000..fe2b991
--- /dev/null
+++ b/src/ppe/sbe/plat/src/Makefile
@@ -0,0 +1,56 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ppe/sbe/plat/src/Makefile $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+# This Makefile is designed to be invoked with the -I argument
+
+export SUB_OBJDIR = /fapi2
+
+include img_defs.mk
+include fapi2sbefiles.mk
+
+
+OBJS := $(addprefix $(OBJDIR)/, $(FAPI2LIB_OBJECTS))
+
+libfapi2.a: fapi2 hwpf
+	$(AR) crs $(OBJDIR)/libfapi2.a $(OBJDIR)/*.o
+
+.PHONY: clean fapi2 hwpf
+fapi2: $(OBJS)
+
+#plat:
+#	$(MAKE) -I $(IMAGE_SRCDIR) -C $(PLAT_FAPI2_DIR)
+
+hwpf:
+	@echo "Processing fapi2 hwpf makefile"
+	$(MAKE) -I $(IMAGE_SRCDIR) -C $(PPE_FAPI2_DIR)/src
+
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
+
+ifneq ($(MAKECMDGOALS),clean)
+include $(OBJS:.o=.d) 
+endif
+
diff --git a/src/ppe/sbe/plat/src/fapi2sbefiles.mk b/src/ppe/sbe/plat/src/fapi2sbefiles.mk
new file mode 100644
index 0000000..0a8fa50
--- /dev/null
+++ b/src/ppe/sbe/plat/src/fapi2sbefiles.mk
@@ -0,0 +1,49 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ppe/sbe/plat/src/fapi2sbefiles.mk $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file fapi2ppefiles.mk
+#
+#  @brief mk for including fapi2 object files
+#
+#  @page ChangeLogs Change Logs
+#  @section fapi2ppefiles.mk
+#  @verbatim
+#
+#
+# Change Log ******************************************************************
+# Flag     Defect/Feature  User        Date         Description
+# ------   --------------  ----------  ------------ -----------
+#
+# @endverbatim
+#
+##########################################################################
+# Object Files
+##########################################################################
+
+FAPI2-C-SOURCES += 
+FAPI2-S-SOURCES =
+
+
+FAPI2LIB_OBJECTS += $(FAPI2-C-SOURCES:.C=.o) $(FAPI2-S-SOURCES:.S=.o)
+
diff --git a/src/ppe/sbe/plat/src/return_code.C b/src/ppe/sbe/plat/src/return_code.C
new file mode 100644
index 0000000..1db9522
--- /dev/null
+++ b/src/ppe/sbe/plat/src/return_code.C
@@ -0,0 +1,47 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/plat/src/return_code.C $                          */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+/**
+ *  @file return_code.C
+ *
+ *  @brief Fuctions that process PPE return codes
+ */
+
+#include <return_code.H>
+
+namespace fapi2
+{
+    
+    /// @brief Takes a non-zero PIB return code and inssert the value into 
+    /// a fapi2::ReturnCode
+    /// @param[in]  i_msr         Value read from the PPE MSR
+    /// @return fapi::ReturnCode. Built ReturnCode
+    ReturnCode&  ReturnCode::insertPIBcode(uint32_t& rhs)
+    {
+        iv_rc = FAPI2_RC_PLAT_MASK | rhs;
+        return iv_rc;
+    }
+
+}
diff --git a/src/ppe/sbe/sbefw/Makefile b/src/ppe/sbe/sbefw/Makefile
new file mode 100644
index 0000000..01e92b4
--- /dev/null
+++ b/src/ppe/sbe/sbefw/Makefile
@@ -0,0 +1,57 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ppe/sbe/sbefw/Makefile $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+export P2P_ENABLE = 1
+
+export SUB_OBJDIR = /sbefw
+
+include img_defs.mk
+include sbefwfiles.mk
+
+OBJS := $(addprefix $(OBJDIR)/, $(SBEFW_OBJECTS))
+
+libsbefw.a: $(OBJS)
+	$(AR) crs $(OBJDIR)/libsbefw.a $(OBJDIR)/*.o
+
+.PHONY: clean sbefw
+sbefw: $(OBJS)
+
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
+
+
+#clean the kernel directory first, then the application level clean
+clean:
+	rm -fr $(OBJDIR)
+
+ifneq ($(MAKECMDGOALS),clean)
+include $(OBJS:.o=.d)
+endif
+
+
+
+
+
diff --git a/src/ppe/sbe/sbefw/pk_app_cfg.h b/src/ppe/sbe/sbefw/pk_app_cfg.h
new file mode 100644
index 0000000..3bd29dd
--- /dev/null
+++ b/src/ppe/sbe/sbefw/pk_app_cfg.h
@@ -0,0 +1,128 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/sbefw/pk_app_cfg.h $                              */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/*
+ * @file: ppe/sbe/sbefw/pk_app_cfg.h
+ *
+ * @brief Application specific overrides go here.
+ *
+ */
+
+#ifndef __PK_APP_CFG_H__
+#define __PK_APP_CFG_H__
+
+#include "sbeirq.H"
+
+/*
+ * @brief  Static configuration data for external interrupts:
+ *     IRQ#, TYPE, POLARITY, ENABLE
+ *
+ */
+#define APPCFG_EXT_IRQS_CONFIG \
+    SBE_IRQ_START0              STD_IRQ_TYPE_EDGE    STD_IRQ_POLARITY_RISING    STD_IRQ_MASKED \
+    SBE_IRQ_START1              STD_IRQ_TYPE_EDGE    STD_IRQ_POLARITY_RISING    STD_IRQ_MASKED \
+    SBE_IRQ_INTR0               STD_IRQ_TYPE_LEVEL   STD_IRQ_POLARITY_RISING    STD_IRQ_MASKED \
+    SBE_IRQ_INTR1               STD_IRQ_TYPE_LEVEL   STD_IRQ_POLARITY_RISING    STD_IRQ_MASKED \
+    SBE_IRQ_DRTM_REQ            STD_IRQ_TYPE_LEVEL   STD_IRQ_POLARITY_RISING    STD_IRQ_MASKED \
+    SBE_IRQ_SBEFIFO_RESET       STD_IRQ_TYPE_LEVEL   STD_IRQ_POLARITY_RISING    STD_IRQ_MASKED \
+    SBE_IRQ_SBEFIFO_DATA        STD_IRQ_TYPE_LEVEL   STD_IRQ_POLARITY_RISING    STD_IRQ_MASKED \
+
+
+/*
+ * @brief This 64 bit mask specifies which of the interrupts are not to be used.
+ *
+ */
+#define APPCFG_IRQ_INVALID_MASK \
+(\
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_7) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_8) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_9) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_10) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_11) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_12) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_13) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_14) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_15) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_16) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_17) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_18) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_19) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_20) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_21) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_22) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_23) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_24) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_25) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_26) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_27) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_28) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_29) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_30) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_31) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_32) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_33) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_34) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_35) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_36) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_37) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_38) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_39) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_40) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_41) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_42) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_43) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_44) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_45) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_46) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_47) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_48) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_49) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_50) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_51) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_52) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_53) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_54) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_55) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_56) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_57) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_58) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_59) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_60) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_61) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_62) |  \
+   STD_IRQ_MASK64(SBE_IRQ_RESERVED_63))
+
+
+/*
+ * @brief  Override the default behavior of the PK API error handling.
+ *          Force PK to send the return code back to the application,
+ *          instead of a kernel panic.
+ *
+ */
+#ifndef PK_ERROR_PANIC
+#define PK_ERROR_PANIC 0
+#endif
+
+
+#endif /*__PK_APP_CFG_H__*/
diff --git a/src/ppe/sbe/sbefw/pool.C b/src/ppe/sbe/sbefw/pool.C
new file mode 100644
index 0000000..8e02dd0
--- /dev/null
+++ b/src/ppe/sbe/sbefw/pool.C
@@ -0,0 +1,71 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/sbefw/pool.C $                                    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#include <stdint.h>
+#include <sbetrace.H>
+#include <stddef.h>
+#include<pool.H>
+
+namespace SBEVECTORPOOL
+{
+
+vectorMemPool_t g_pool[G_POOLSIZE];
+
+vectorMemPool_t * allocMem()
+{
+    vectorMemPool_t *pool = NULL;
+    for( size_t idx = 0; idx < G_POOLSIZE; idx++ )
+    {
+        if( 0 == g_pool[idx].refCount )
+        {
+            pool = g_pool + idx;
+            g_pool[idx].refCount++;
+            break;
+        }
+    }
+    SBE_TRACE(" Giving pool 0x%08X", pool);
+    return pool;
+}
+
+void releaseMem( vectorMemPool_t * i_pool )
+{
+    do
+    {
+        if ( NULL == i_pool )   break;
+
+        if( 0 == i_pool->refCount )
+        {
+            //TODO via RTC 129166
+            // Assert here.  This pool was not supposed to be in use.
+            // Currenty just keeping it as is as we can not do much till the
+            // time support for assert is in.
+            break;
+        }
+        SBE_TRACE(" Releasing pool 0x%08X", i_pool);
+        i_pool->refCount--;
+        SBE_TRACE(" In releaseMem() RefCount:%u", i_pool->refCount);
+    }while(0);
+}
+
+} // namesspace SBEVECTORPOOL
diff --git a/src/ppe/sbe/sbefw/pool.H b/src/ppe/sbe/sbefw/pool.H
new file mode 100644
index 0000000..1d620d1
--- /dev/null
+++ b/src/ppe/sbe/sbefw/pool.H
@@ -0,0 +1,59 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/sbefw/pool.H $                                    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+#ifndef SBE_VECTOR_POOL_H
+#define SBE_VECTOR_POOL_H
+
+namespace SBEVECTORPOOL
+{
+
+// Size of a block  for a vector
+static const size_t G_BLOCKSIZE = 512;
+
+//Pool size
+static const size_t G_POOLSIZE = 4;
+
+typedef struct
+{
+    size_t refCount;
+    uint8_t data[G_BLOCKSIZE];
+}vectorMemPool_t;
+
+/**
+  * @brief Returns memory pool block.
+  *
+  * @return  Memory block if available, NULL otherwise.
+  */
+vectorMemPool_t * allocMem();
+
+/**
+  * @brief Release memory pool block.
+  *
+  * @param[in] i_pool pool pointer.
+  */
+void releaseMem( vectorMemPool_t * i_pool );
+
+} // namespace SBEVECTORPOOL
+#endif //SBE_VECTOR_POOL_H
diff --git a/src/ppe/sbe/sbefw/sbe_sp_intf.H b/src/ppe/sbe/sbefw/sbe_sp_intf.H
new file mode 100644
index 0000000..0952659
--- /dev/null
+++ b/src/ppe/sbe/sbefw/sbe_sp_intf.H
@@ -0,0 +1,222 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/sbefw/sbe_sp_intf.H $                             */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/*
+ *  @file sbe_sp_intf.H
+ *
+ *  @brief This file contains the SP - SBE interface protocol common details
+ */
+
+#ifndef __SBEFW_SBE_SP_INTF_H
+#define __SBEFW_SBE_SP_INTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * $Version: Conforms to SP-SBE Interface Spec v0.8
+ */
+
+/**
+ * @brief enums for SBE command classes
+ *
+*/
+enum sbeCommandClass
+{
+    SBE_CMD_CLASS_UNKNOWN                = 0,
+    SBE_CMD_CLASS_IPL_CONTROL            = 0xA1,
+    SBE_CMD_CLASS_SCOM_ACCESS            = 0xA2,
+    SBE_CMD_CLASS_RING_ACCESS            = 0xA3,
+    SBE_CMD_CLASS_MEMORY_ACCESS          = 0xA4,
+    SBE_CMD_CLASS_REGISTER_ACCESS        = 0xA5,
+    SBE_CMD_CLASS_ARRAY_ACCESS           = 0xA6,
+    SBE_CMD_CLASS_INSTRUCTION_CONTROL    = 0xA7,
+    SBE_CMD_CLASS_GENERIC_MESSAGE        = 0xA8,
+    SBE_CMD_CLASS_MPIPL_COMMANDS         = 0xA9,
+};
+
+/**
+ * @brief enums for SBE Istep Control command class
+ *
+*/
+enum sbeIplControlCommands
+{
+    SBE_CMD_EXECUTE_ISTEP      = 0x01, /* Execute istep */
+    SBE_CMD_IS_SBE_IPL_DONE    = 0x02, /* Check if SBE IPL Done */
+};
+
+/**
+ * @brief enums for SCOM Access Messages
+ *
+*/
+enum sbeScomAccessCommands
+{
+    SBE_CMD_GETSCOM          = 0x01, /* Get SCOM */
+    SBE_CMD_PUTSCOM          = 0x02, /* Put SCOM */
+    SBE_CMD_MODIFYSCOM       = 0x03, /* Modify SCOM */
+    SBE_CMD_PUTSCOM_MASK     = 0x04, /* Put SCOM under mask */
+    SBE_CMD_MULTISCOM        = 0x05, /* Execute Multi SCOM */
+};
+
+/**
+ * @brief enums for Ring Access Messages
+ *
+*/
+enum sbeRingAccessCommands
+{
+    SBE_CMD_GETRING          = 0x01, /* Get Ring */
+    SBE_CMD_PUTRING          = 0x02, /* Put Ring */
+};
+
+/**
+ * @brief enums for Memory Access Messages
+ *
+*/
+enum sbeMemoryAccesCommands
+{
+    SBE_CMD_GETMEM           = 0x01, /* Get Memory (Proc/PBA) */
+    SBE_CMD_PUTMEM           = 0x02, /* Put Memory (Proc/PBA) */
+    SBE_CMD_GETSRAM          = 0x03, /* Get Memory (SRAM) */
+    SBE_CMD_PUTSRAM          = 0x04, /* Put Memory (SRAM) */
+};
+
+/**
+ * @brief enums for GPR/SPR/FPR Access Messages
+ *
+*/
+enum sbeRegisterAccessCommands
+{
+    SBE_CMD_GETREG           = 0x01, /* Get Register (GPR,SPR,FPR) */
+    SBE_CMD_PUTREG           = 0x02, /* Put Register (GPR,SPR,FPR) */
+};
+
+/**
+ * @brief enums for Trace Array Access Messages
+ *
+*/
+enum sbeArrayAccessCommands
+{
+    SBE_CMD_GET_FAST_ARRAY        = 0x01, /* Get Fast Array */
+    SBE_CMD_GET_TRACE_ARRAY       = 0x02, /* Get Trace Array */
+    SBE_CMD_CONTROL_TRACE_ARRAY   = 0x03, /* Control Trace Array */
+};
+
+/**
+ * @brief enums for Instruction Control Messages
+ *
+*/
+enum sbeInstructionControlCommands
+{
+    SBE_CMD_CONTROL_INSTRUCTIONS  = 0x01, /* Control Instructions */
+};
+
+/**
+ * @brief enums for Generic Messages
+ *
+*/
+enum sbeGenericMessageCommands
+{
+    SBE_CMD_GET_SBE_FFDC          = 0x01, /* Get FFDC */
+    SBE_CMD_GET_SBE_VER           = 0x02, /* GET SBE Version */
+    SBE_CMD_GET_SBE_CAPABILITIES  = 0x03, /* GET SBE capabilities */
+    SBE_CMD_GET_FREQ_SUPPORTED    = 0x04, /* Get Supported frequencies */
+    SBE_CMD_GET_SBE_STATE         = 0x05, /* Get SBE State */
+};
+
+enum sbeMpIplCommands
+{
+    SBE_CMD_MPIPL_INVALID = 0x00,
+};
+
+/**
+ * @brief enums for primary SBE response
+ *
+*/
+enum sbePrimResponse
+{
+    SBE_PRI_OPERATION_SUCCESSFUL        = 0x00,
+    SBE_PRI_INVALID_COMMAND             = 0x01,
+    SBE_PRI_INVALID_DATA                = 0x02,
+    SBE_PRI_SEQUENCE_ERROR              = 0x03,
+    SBE_PRI_INTERNAL_ERROR              = 0x04,
+    SBE_PRI_GENERIC_EXECUTION_FAILURE   = 0xFE,
+};
+
+/**
+ * @brief enums for secondary SBE response
+ *   @TODO via RTC: 129763
+ *         Discuss on SBE_SEC_INVALID_TARGET_ID_PASSED
+ *
+*/
+enum sbeSecondaryResponse
+{
+    SBE_SEC_OPERATION_SUCCESSFUL              = 0x00,
+    SBE_SEC_COMMAND_CLASS_NOT_SUPPORTED       = 0x01,
+    SBE_SEC_COMMAND_NOT_SUPPORTED             = 0x02,
+    SBE_SEC_INVALID_ADDRESS_PASSED            = 0x03,
+    SBE_SEC_INVALID_TARGET_TYPE_PASSED        = 0x04,
+    SBE_SEC_INVALID_TARGET_ID_PASSED          = 0x05,
+    SBE_SEC_SPECIFIED_TARGET_NOT_PRESENT      = 0x06,
+    SBE_SEC_SPECIFIED_TARGET_NOT_FUNCTIONAL   = 0x07,
+    SBE_SEC_COMMAND_NOT_ALLOWED_IN_THIS_STATE = 0x08,
+    SBE_SEC_FUNCTIONALITY_NOT_SUPPORTED       = 0x09,
+    SBE_SEC_GENERIC_FAILURE_IN_EXECUTION      = 0x0A,
+    SBE_SEC_SECURITY_VALIDATION_FAILED        = 0x0B,
+    SBE_SEC_OS_FAILURE                        = 0x0C,
+    SBE_SEC_FIFO_ACCESS_FAILURE               = 0x0D,
+};
+
+/**
+ * @brief enums for SBE command timeout values
+ *
+*/
+enum sbeCmdRespTimeout
+{
+    SBE_CMD_TIMEOUT_SHORT_IN_MSEC = 100,
+    SBE_CMD_TIMEOUT_LONG_IN_MSEC  = 30000,
+};
+
+/**
+ * @brief enums for PCB-PIB Generic Error codes
+ *
+*/
+enum sbePCBPIBErrorRC
+{
+    SBE_PCB_PIB_ERROR_NONE                = 0x00,
+    SBE_PCB_PIB_ERROR_RESOURCE_OCCUPIED   = 0x01,
+    SBE_PCB_PIB_ERROR_CHIPLET_OFFLINE     = 0x02,
+    SBE_PCB_PIB_ERROR_PARTIAL_GOOD        = 0x03,
+    SBE_PCB_PIB_ERROR_ADDRESS_ERROR       = 0x04,
+    SBE_PCB_PIB_ERROR_CLOCK_ERROR         = 0x05,
+    SBE_PCB_PIB_ERROR_PACKET_ERROR        = 0x06,
+    SBE_PCB_PIB_ERROR_TIMEOUT             = 0x07,
+};
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SBEFW_SBE_SP_INTF_H */
diff --git a/src/ppe/sbe/sbefw/sbecmdiplcontrol.C b/src/ppe/sbe/sbefw/sbecmdiplcontrol.C
new file mode 100644
index 0000000..e9dafd9
--- /dev/null
+++ b/src/ppe/sbe/sbefw/sbecmdiplcontrol.C
@@ -0,0 +1,328 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/sbefw/sbecmdiplcontrol.C $                        */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/*
+ * @file: ppe/sbe/sbefw/sbecmdiplcontrol.C
+ *
+ * @brief This file contains the SBE FIFO Commands
+ *
+ */
+
+#include "sbecmdiplcontrol.H"
+#include "sbefifo.H"
+#include "sbetrace.H"
+#include "sbe_sp_intf.H"
+
+// Forward declaration
+
+uint32_t sbeExecuteIstep (const uint8_t i_major, const uint8_t i_minor);
+bool validateIstep (const uint8_t i_major, const uint8_t i_minor);
+
+// @TODO via RTC 129073.
+// Just a dummy code for HWP to test the flow.
+// Remove it once complete flow is ready
+uint32_t istep1SuccessHwp(  ) { SBE_DEBUG("istep1SuccessHwp"); return 0; }
+uint32_t istep1FailHwp(  ) { SBE_DEBUG("istep1FailHwp"); return 1; }
+
+
+//typedefs
+// @TODO via RTC 129073.
+// This is currently not defined as actual HWP signature as it
+// will break compilation. Once Greg FAPI codeis in master, we will
+// change it
+typedef uint32_t (*sbe_istep_hwp)();
+
+// Wrapper function for HWP IPl functions
+typedef uint32_t (*sbe_istep)( sbe_istep_hwp );
+
+// Wrapper function which will call HWP with Proc target.
+uint32_t istepWithProc( sbe_istep_hwp i_hwp );
+
+//structure for mapping SBE wrapper and HWP functions
+typedef struct
+{
+    sbe_istep istepWrapper;
+    sbe_istep_hwp istepHwp;
+}istepMap_t;
+
+// Major isteps which are supported
+typedef enum
+{
+    SBE_ISTEP2 = 2,
+    SBE_ISTEP4 = 4,
+    SBE_ISTEP5 = 5,
+}sbe_supported_steps_t;
+
+// constants
+// @TODO via RTC 129073.
+// These are random numbers now. Will fill up
+// once IPL flow document is in better shape.
+const uint32_t ISTEP2_MAX_SUBSTEPS = 15;
+const uint32_t ISTEP4_MAX_SUBSTEPS = 2;
+const uint32_t ISTEP5_MAX_SUBSTEPS = 4;
+
+// File static data
+// @TODO via RTC 129073.
+// Initialise pointer tables.
+
+static istepMap_t g_istep2PtrTbl[ ISTEP2_MAX_SUBSTEPS ] =
+                    {
+                        { NULL, NULL },
+                        { &istepWithProc, &istep1FailHwp },
+                        { &istepWithProc, &istep1SuccessHwp }
+
+                    };
+static istepMap_t g_istep4PtrTbl[ ISTEP4_MAX_SUBSTEPS ];
+static istepMap_t g_istep5PtrTbl[ ISTEP5_MAX_SUBSTEPS ];
+
+// Functions
+//----------------------------------------------------------------------------
+uint32_t sbeHandleIstep (uint8_t *i_pArg)
+{
+    #define SBE_FUNC "sbeHandleIstep "
+    SBE_DEBUG(SBE_FUNC);
+    uint32_t rc = SBE_SEC_OPERATION_SUCCESSFUL;
+    //@TODO via RTC 129073.
+    //Use proper initialisation for fapi RC
+    uint32_t fapiRc = SBE_SEC_OPERATION_SUCCESSFUL;
+    uint8_t len = 0;
+    sbeIstepReqMsg_t req;
+    sbeResponseGenericHeader_t respHdr;
+    respHdr.init();
+    sbeResponseFfdc_t ffdc;
+
+    // NOTE: In this function we will have two loops
+    // First loop will deque data and prepare the response
+    // Second response will enque the data on DS FIFO
+    //loop 1
+    do
+    {
+        // @TODO via RTC : 130575
+        // Optimize both the RC handling and
+        // FIFO operation infrastructure.
+        len = sizeof( req )/sizeof(uint32_t);
+        rc = sbeUpFifoDeq_mult ( len, (uint32_t *)&req);
+        if (rc) //FIFO access issue
+        {
+            SBE_ERROR(SBE_FUNC"FIFO dequeue failed, rc[0x%X]", rc);
+            break;
+        }
+        len = 1;
+        rc = sbeUpFifoDeq_mult ( len, NULL, true );
+
+        // If we didn't receive EOT yet
+        if ( rc != SBE_FIFO_RC_EOT_ACKED )
+        {
+            SBE_ERROR(SBE_FUNC"FIFO dequeue failed, rc[0x%X]", rc);
+            break;
+        }
+        // override Rc as we do not want to treat SBE_FIFO_RC_EOT_ACKED as error
+        rc = SBE_SEC_OPERATION_SUCCESSFUL;
+
+        SBE_DEBUG(SBE_FUNC"Major number:0x%08x minor number:0x%08x",
+                  req.major, req.minor );
+
+        if( false == validateIstep( req.major, req.minor ) )
+        {
+            SBE_ERROR(SBE_FUNC" Invalid Istep. major:0x%08x"
+                      " minor:0x%08x", req.major, req.minor);
+            // @TODO via RTC 129073.
+            // Need to change code asper better error handling.
+            respHdr.setStatus( SBE_PRI_INVALID_DATA,
+                               SBE_SEC_GENERIC_FAILURE_IN_EXECUTION);
+            break;
+        }
+        fapiRc = sbeExecuteIstep( req.major, req.minor );
+        if( fapiRc )
+        {
+            SBE_ERROR(SBE_FUNC" sbeExecuteIstep() Failed. major:0x%08x"
+                                      " minor:0x%08x", req.major, req.minor);
+            respHdr.setStatus( SBE_PRI_GENERIC_EXECUTION_FAILURE,
+                               SBE_SEC_GENERIC_FAILURE_IN_EXECUTION);
+            ffdc.setRc(fapiRc);
+        }
+
+    }while(0);
+
+    //loop 2
+    do
+    {
+        // FIFO error
+        if ( rc )
+        {
+            break;
+        }
+
+        uint32_t distance = 1; //initialise by 1 for entry count itself.
+        len = sizeof(respHdr)/sizeof(uint32_t);
+        // sbeDownFifoEnq_mult.
+        rc = sbeDownFifoEnq_mult ( len, ( uint32_t *) &respHdr);
+        if (rc)
+        {
+            break;
+        }
+        distance += len;
+
+        // If no ffdc , exit;
+        if( ffdc.fapiRc )
+        {
+            len = sizeof(ffdc)/sizeof(uint32_t);
+            rc = sbeDownFifoEnq_mult ( len, ( uint32_t *) &ffdc);
+            if (rc)
+            {
+                break;
+            }
+            distance += len;
+        }
+        len = sizeof(distance)/sizeof(uint32_t);
+        //@TODO via 129076.
+        //Need to add FFDC data as well.
+        rc = sbeDownFifoEnq_mult ( len, &distance);
+        if (rc)
+        {
+            break;
+        }
+    }while(0);
+
+    if( rc )
+    {
+        SBE_ERROR( SBE_FUNC"Failed. rc[0x%X]", rc);
+    }
+    return rc;
+    #undef SBE_FUNC
+}
+
+//----------------------------------------------------------------------------
+// @TODO via RTC 129073.
+// Change return code as per design
+// @note This is the responsibilty of caller to verify major/minor
+//       number before calling this function
+
+// @TODO via RTC 129077.
+// This function should check for system checkstop as well.
+uint32_t sbeExecuteIstep (const uint8_t i_major, const uint8_t i_minor)
+{
+    #define SBE_FUNC "sbeExecuteIstep "
+    SBE_DEBUG(SBE_FUNC"Major number:0x%x minor number:0x%x",
+                       i_major, i_minor );
+    uint32_t rc = 0;
+
+    switch( i_major )
+    {
+        case SBE_ISTEP2:
+            rc = (g_istep2PtrTbl[i_minor-1].istepWrapper)(
+                                g_istep2PtrTbl[i_minor-1].istepHwp);
+            break;
+
+        case SBE_ISTEP4:
+            rc = (g_istep4PtrTbl[i_minor-1].istepWrapper)(
+                              g_istep4PtrTbl[i_minor-1].istepHwp);
+            break;
+
+        case SBE_ISTEP5:
+            rc = (g_istep5PtrTbl[i_minor-1].istepWrapper)(
+                              g_istep5PtrTbl[i_minor-1].istepHwp);
+            break;
+
+        // We should never reach here as before calling this validation has
+        // been done.
+        // @TODO via RTC 129166.
+        // assert if we reach in default case.
+        default:
+            break;
+        }
+
+    return rc;
+    #undef SBE_FUNC
+}
+
+//----------------------------------------------------------------------------
+bool validateIstep (const uint8_t i_major, const uint8_t i_minor)
+{
+    bool valid = true;
+    do
+    {
+        if( 0 == i_minor )
+        {
+            valid = false;
+            break;
+        }
+
+        switch( i_major )
+        {
+            case SBE_ISTEP2:
+                // istep 2.1 loads image to PIBMEM
+                // So SBE control loop can not execute istep 2.1.
+                if(( i_minor > ISTEP2_MAX_SUBSTEPS ) || ( i_minor == 1) )
+                {
+                    valid = false;
+                }
+                break;
+
+            case SBE_ISTEP4:
+                if( i_minor > ISTEP4_MAX_SUBSTEPS )
+                {
+                    valid = false;
+                }
+                break;
+
+            case SBE_ISTEP5:
+                if( i_minor > ISTEP5_MAX_SUBSTEPS )
+                {
+                    valid = false;
+                }
+                break;
+
+            default:
+                valid= false;
+                break;
+        }
+    } while(0);
+
+    return valid;
+}
+
+//----------------------------------------------------------------------------
+
+uint32_t istepWithProc( sbe_istep_hwp i_hwp)
+{
+    SBE_DEBUG("istepWithProc");
+    uint32_t rc = 0;
+    if( i_hwp )
+    {
+        rc = i_hwp();
+    }
+    return rc;
+}
+
+//----------------------------------------------------------------------------
+
+uint32_t sbeWaitForSbeIplDone (uint8_t *i_pArg)
+{
+    uint32_t rc = 0;
+    SBE_TRACE("sbeWaitForSbeIplDone");
+
+
+    return rc;
+}
diff --git a/src/ppe/sbe/sbefw/sbecmdiplcontrol.H b/src/ppe/sbe/sbefw/sbecmdiplcontrol.H
new file mode 100644
index 0000000..06332bb
--- /dev/null
+++ b/src/ppe/sbe/sbefw/sbecmdiplcontrol.H
@@ -0,0 +1,58 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/sbefw/sbecmdiplcontrol.H $                        */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/*
+ * @file: ppe/sbe/sbefw/sbecmdiplcontrol.H
+ *
+ * @brief This file contains the SBE command details
+ *
+ */
+
+#ifndef __SBEFW_SBECMDIPLCONTROL_H
+#define __SBEFW_SBECMDIPLCONTROL_H
+
+#include <stdint.h>
+
+
+/**
+  * @brief execute istep chipop (0xA101)
+  *
+  * @param[in] i_pArg Buffer to be passed to the function (not used as of now)
+  *
+  * @return    Rc from the FIFO access utility
+  */
+uint32_t sbeHandleIstep(uint8_t *i_pArg);
+
+
+/**
+  * @brief  Handles wait for IPL done chipop (0xA102)
+  *
+  * @param[in] i_pArg Buffer to be passed to the function (not used as of now)
+  *
+  * @return    Rc from the FIFO access utility
+  */
+uint32_t sbeWaitForSbeIplDone (uint8_t *i_pArg);
+
+
+#endif // __SBEFW_SBECMDIPLCONTROL_H
diff --git a/src/ppe/sbe/sbefw/sbecmdparser.C b/src/ppe/sbe/sbefw/sbecmdparser.C
new file mode 100644
index 0000000..65bf271
--- /dev/null
+++ b/src/ppe/sbe/sbefw/sbecmdparser.C
@@ -0,0 +1,186 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/sbefw/sbecmdparser.C $                            */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/*
+ * @file: ppe/sbe/sbefw/sbecmdparser.C
+ *
+ * @brief This file contains the SBE FIFO Commands
+ *
+ */
+
+#include "sbecmdparser.H"
+#include "sbecmdscomaccess.H"
+#include "sbecmdiplcontrol.H"
+#include "sbetrace.H"
+#include "sbe_sp_intf.H"
+
+
+////////////////////////////////////////////////////////////////
+// @brief g_sbeScomCmdArray
+////////////////////////////////////////////////////////////////
+static sbeCmdStruct_t g_sbeScomCmdArray [] =
+{
+    {sbeGetScom,
+     SBE_CMD_GETSCOM,
+     SBE_FENCE_AT_CONTINUOUS_IPL,
+     },
+
+    {sbePutScom,
+     SBE_CMD_PUTSCOM,
+     SBE_FENCE_AT_CONTINUOUS_IPL,
+     },
+};
+
+////////////////////////////////////////////////////////////////
+// @brief g_sbeScomCmdArray
+//
+////////////////////////////////////////////////////////////////
+static sbeCmdStruct_t g_sbeIplControlCmdArray [] =
+{
+    {sbeHandleIstep,
+     SBE_CMD_EXECUTE_ISTEP,
+     SBE_FENCE_AT_CONTINUOUS_IPL|SBE_FENCE_AT_RUNTIME|SBE_FENCE_AT_MPIPL,
+     },
+
+    {sbeWaitForSbeIplDone,
+     SBE_CMD_IS_SBE_IPL_DONE,
+     SBE_FENCE_AT_ISTEP|SBE_FENCE_AT_RUNTIME|SBE_FENCE_AT_MPIPL,
+     },
+};
+
+
+
+////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////
+uint8_t sbeGetCmdStructAttr (const uint8_t  i_cmdClass,
+                                   sbeCmdStruct_t **o_ppCmd)
+{
+    #define SBE_FUNC " sbeGetCmdStructAttr "
+    SBE_DEBUG(SBE_FUNC);
+    uint8_t l_numCmds  = 0;
+    *o_ppCmd = NULL;
+
+    switch(i_cmdClass)
+    {
+        case SBE_CMD_CLASS_IPL_CONTROL:
+            // @TODO via RTC : 128655
+            //       Use C++ style typecase
+            l_numCmds = sizeof(g_sbeIplControlCmdArray) /
+                        sizeof(sbeCmdStruct_t);
+            *o_ppCmd    = (sbeCmdStruct_t*)g_sbeIplControlCmdArray;
+            break;
+        case SBE_CMD_CLASS_SCOM_ACCESS:
+            l_numCmds = sizeof(g_sbeScomCmdArray) /
+                        sizeof(sbeCmdStruct_t);
+            *o_ppCmd    = (sbeCmdStruct_t*)g_sbeScomCmdArray;
+            break;
+
+        // This will grow with each class of chipOp in future
+        default:
+                break;
+    }
+    return l_numCmds;
+    #undef SBE_FUNC
+}
+
+
+////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////
+uint8_t sbeValidateCmdClass (const uint8_t i_cmdClass,
+                             const uint8_t i_cmdOpcode)
+{
+    #define SBE_FUNC " sbeValidateCmdClass "
+    uint8_t l_rc           = SBE_SEC_COMMAND_NOT_SUPPORTED;
+
+    SBE_DEBUG(SBE_FUNC"i_cmdClass[0x%02X], "
+              "i_cmdOpcode[0x%02X]", i_cmdClass, i_cmdOpcode);
+
+    do
+    {
+        uint8_t l_numCmds      = 0;
+        sbeCmdStruct_t *l_pCmd = NULL;
+
+        l_numCmds = sbeGetCmdStructAttr (i_cmdClass, &l_pCmd);
+        if (!l_numCmds)
+        {
+            // Command class not supported
+            l_rc = SBE_SEC_COMMAND_CLASS_NOT_SUPPORTED;
+            break;
+        }
+
+        // @TODO via RTC : 128654
+        //       Analyze on merging the validation functions into one
+        //       and also on using loop vs switch case performance
+        for (uint8_t l_cnt = 0; l_cnt < l_numCmds; ++l_cnt, ++l_pCmd)
+        {
+            if (i_cmdOpcode == l_pCmd->cmd_opcode)
+            {
+                // Command found
+                l_rc = SBE_SEC_OPERATION_SUCCESSFUL;
+                break;
+            }
+        }
+    } while (false);
+
+    return l_rc;
+    #undef SBE_FUNC
+}
+
+////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////
+bool sbeIsCmdAllowedAtState (const uint8_t i_cmdClass,
+                             const uint8_t i_cmdOpcode)
+{
+    // @TODO via RTC : 126146
+    //       SBE state management
+    return 0;
+}
+
+////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////
+sbeCmdFunc_t sbeFindCmdFunc (const uint8_t i_cmdClass,
+                             const uint8_t i_cmdOpcode)
+
+{
+    #define SBE_FUNC " sbeFindCmdFunc "
+    uint8_t l_numCmds      = 0;
+    sbeCmdStruct_t *l_pCmd = NULL;
+
+    l_numCmds = sbeGetCmdStructAttr (i_cmdClass, &l_pCmd);
+
+    SBE_DEBUG(SBE_FUNC"i_cmdClass[0x%02X], "
+              "i_cmdOpcode[0x%02X], l_numCmds[0x%02X]",
+               i_cmdClass, i_cmdOpcode, l_numCmds);
+
+    for (uint8_t l_cnt = 0; l_cnt < l_numCmds; ++l_cnt, ++l_pCmd)
+    {
+        if (i_cmdOpcode == l_pCmd->cmd_opcode)
+        {
+            break;
+        }
+    }
+
+    return l_pCmd ? (l_pCmd->cmd_func) : NULL;
+    #undef SBE_FUNC
+}
diff --git a/src/ppe/sbe/sbefw/sbecmdparser.H b/src/ppe/sbe/sbefw/sbecmdparser.H
new file mode 100644
index 0000000..921637a
--- /dev/null
+++ b/src/ppe/sbe/sbefw/sbecmdparser.H
@@ -0,0 +1,116 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/sbefw/sbecmdparser.H $                            */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/*
+ * @file: ppe/sbe/sbefw/sbecmdparser.H
+ *
+ * @brief This file contains the SBE command details
+ *
+ */
+
+#ifndef __SBEFW_SBECMDPARSER_H
+#define __SBEFW_SBECMDPARSER_H
+
+#include <stdint.h>
+
+
+/**
+ *  @brief SBE Command structure associating an opcode of a command
+ *         to the processing function as well as the allowed states
+ *
+ */
+typedef uint32_t (*sbeChipOpFunc_t) (uint8_t *i_pArg);
+
+typedef struct {
+    sbeChipOpFunc_t   cmd_func;   /* Command function pointer */
+    uint8_t           cmd_opcode; /* Command opcode */
+    uint8_t  cmd_state_fence;     /* Command fencing based on SBE state */
+} sbeCmdStruct_t;
+
+
+/**
+ *  @brief SBE Command Fence attributes
+ *
+ */
+enum sbe_command_fence_attrs
+{
+    SBE_FENCE_AT_ISTEP          = 0x80, ///< Fence off the cmd at istep state
+    SBE_FENCE_AT_CONTINUOUS_IPL = 0x40, ///< Fence off the cmd at cont IPL
+    SBE_FENCE_AT_RUNTIME        = 0x20, ///< Fence off the cmd at Runtime state
+    SBE_FENCE_AT_MPIPL          = 0x10, ///< Fence off the cmd at MPIPL state
+};
+
+
+/**
+  * @brief sbeValidateCmdClass  Validates the command class and opcode
+  *
+  * @param[in]     i_cmdClass    Command class code
+  * @param[in]     i_cmdOpcode   Command opcode
+  *
+  * @return uint8_t  return code
+  *               SBE_SEC_OPERATION_SUCCESSFUL - Command found
+  *               SBE_SEC_COMMAND_CLASS_NOT_SUPPORTED
+  *               SBE_SEC_COMMAND_NOT_SUPPORTED
+  */
+uint8_t sbeValidateCmdClass (const uint8_t i_cmdClass,
+                             const uint8_t i_cmdOpcode);
+
+/**
+  * @brief sbeIsCmdAllowedAtState  Validates if the command is allowed
+  *        at the current SBE state
+  *
+  * @param[in]    i_cmdClass    Command class code
+  * @param[in]    i_cmdOpcode   Command opcode
+  *
+  * @return       true  command is allowed at the current state
+  *               false command is not allowed at the current state
+  */
+bool sbeIsCmdAllowedAtState (const uint8_t i_cmdClass,
+                             const uint8_t i_cmdOpcode);
+
+
+/**
+  * @brief sbeCmdFunc_t Typical signature for any SBE ChipOp back-end function
+  *
+  * @param[in]  uint8_t *i_pArg  Pointer to the argument to be passed to
+  *                              the chipOp function
+  *
+  * @return     uint32_t Return code from the chipOp function
+  */
+typedef uint32_t ( *sbeCmdFunc_t ) (uint8_t *i_pArg);
+
+
+/**
+  * @brief sbeFindCmdFunc  Finds the function corresponding to the command
+  *
+  * @param[in]     i_cmdClass    Command class code
+  * @param[in]     i_cmdOpcode   Command opcode
+  *
+  * @return  sbeCmdFunc_t A pointer to the corresponding ChipOps function
+  */
+sbeCmdFunc_t sbeFindCmdFunc (const uint8_t i_cmdClass,
+                             const uint8_t i_cmdOpcode);
+
+
+#endif // __SBEFW_SBECMDPARSER_H
diff --git a/src/ppe/sbe/sbefw/sbecmdprocessor.C b/src/ppe/sbe/sbefw/sbecmdprocessor.C
new file mode 100644
index 0000000..31391d0
--- /dev/null
+++ b/src/ppe/sbe/sbefw/sbecmdprocessor.C
@@ -0,0 +1,263 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/sbefw/sbecmdprocessor.C $                         */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/*
+ * @file: ppe/sbe/sbefw/sbecmdprocessor.C
+ *
+ * @brief This file contains the SBE Command processing Thread Routines
+ *
+ */
+
+
+#include "sbeexeintf.H"
+#include "sbefifo.H"
+#include "sbecmdparser.H"
+#include "sbeirq.H"
+#include "sbetrace.H"
+#include "sbe_sp_intf.H"
+
+//////////////////////////////////////////////////////
+//////////////////////////////////////////////////////
+void sbeSyncCommandProcessor_routine(void *i_pArg)
+{
+    #define SBE_FUNC " sbeSyncCommandProcessor_routine "
+    SBE_ENTER(SBE_FUNC);
+
+    do
+    {
+        uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL;
+        uint8_t  l_dist2StatusHdr        = 0;
+        uint32_t l_sbeDownFifoRespBuf[4] = {0};
+
+        // Wait for new command processing
+        int l_rcPk = pk_semaphore_pend (
+                    &g_sbeSemCmdProcess, PK_WAIT_FOREVER);
+
+        do
+        {
+            uint16_t l_primStatus = g_sbeCmdRespHdr.prim_status;
+            uint16_t l_secStatus  = g_sbeCmdRespHdr.sec_status ;
+            SBE_DEBUG (SBE_FUNC"l_primStatus=[0x%04X], l_secStatus=[0x%04X]",
+                            l_primStatus, l_secStatus);
+
+            // PK API failure
+            if (l_rcPk != PK_OK)
+            {
+                SBE_ERROR(SBE_FUNC"pk_semaphore_pend failed, "
+                          "l_rcPk=%d, g_sbeSemCmdRecv.count=%d",
+                           l_rcPk, g_sbeSemCmdRecv.count);
+
+                // if the command receiver thread already updated
+                // the response status codes, don't override them.
+                if (l_primStatus != SBE_PRI_OPERATION_SUCCESSFUL)
+                {
+                    l_primStatus = SBE_PRI_INTERNAL_ERROR;
+                    l_secStatus  = SBE_SEC_OS_FAILURE;
+                }
+            }
+
+            SBE_DEBUG(SBE_FUNC"unblocked");
+
+            // if there was a PK API failure or the
+            // command receiver thread indicated of
+            // a failure due to
+            //    Command Validation or
+            //    FIFO Reset request
+            if (l_primStatus)
+            {
+                uint8_t  l_len2dequeue           = 0;
+                switch (l_primStatus)
+                {
+                    case SBE_FIFO_RESET_RECEIVED:
+                        SBE_ERROR(SBE_FUNC"FIFO reset received");
+                        l_rc = SBE_FIFO_RC_RESET;
+                        break;
+
+                    case SBE_PRI_INVALID_COMMAND:
+                        // Command or SBE state validation failed
+                        // just follow through
+
+                    case SBE_PRI_INTERNAL_ERROR:
+                        // Flush out the upstream FIFO till EOT arrives
+                        l_len2dequeue = 1;
+                        l_rc = sbeUpFifoDeq_mult (l_len2dequeue, NULL, true);
+                        if (l_rc == SBE_FIFO_RC_RESET)
+                        {
+                           break;
+                        }
+
+                        // Not handling any other RC from sbeUpFifoDeq_mult
+                        // while flushing out to keep this code simple.
+
+                        // Don't break here to force the flow through
+                        // the next case to enqueue the response into
+                        // the downstream FIFO
+
+                    case SBE_PRI_INVALID_DATA:
+                        // SBE caller already wrongly sent EOT
+                        // before sending two mandatory header entries
+                        //
+                        // enqueue the response payload now into
+                        // the downstream FIFO
+
+                        // @TODO via RTC : 130575
+                        //       Optimize RC handling infrastructure code
+
+                        // Build the response packet first
+                        sbeBuildMinRespHdr(&l_sbeDownFifoRespBuf[0],
+                                            l_dist2StatusHdr,
+                                            l_primStatus,
+                                            l_secStatus,
+                                            0);
+
+                        // Now enqueue into the downstream FIFO
+                        l_rc = sbeDownFifoEnq_mult (++l_dist2StatusHdr,
+                                                &l_sbeDownFifoRespBuf[0]);
+                        if (l_rc)
+                        {
+                            SBE_ERROR(SBE_FUNC"sbeDownFifoEnq_mult failure,"
+                                      " l_rc[0x%X]", l_rc);
+                        }
+                        break;
+
+                        // Signal EOT in Downstream FIFO
+                        l_rc = sbeDownFifoSignalEot();
+                        if (l_rc)
+                        {
+                            SBE_ERROR(SBE_FUNC"sbeDownFifoSignalEot failure,"
+                                   " l_rc[0x0%08X]", l_rc);
+                            break;
+                        }
+
+                    default:
+                        break;
+                } // End switch
+
+                break;
+            }
+
+            SBE_DEBUG(SBE_FUNC"New cmd arrived, g_sbeSemCmdProcess.count=%d",
+                         g_sbeSemCmdProcess.count);
+
+            uint8_t  l_cmdClass  = 0;
+            uint8_t  l_cmdOpCode = 0;
+            uint32_t (*l_pFuncP) (uint8_t *) ;
+
+            // @TODO via RTC: 128658
+            //       Review if Mutex protection is required
+            //       for all the globals used between threads
+            l_cmdClass  = g_sbeCmdHdr.cmdClass;
+            l_cmdOpCode = g_sbeCmdHdr.command;
+
+            // Get the command function
+            l_pFuncP = sbeFindCmdFunc (l_cmdClass, l_cmdOpCode) ;
+
+            if (!l_pFuncP)
+            {
+                // No Supported function found
+                SBE_ERROR(SBE_FUNC"No supported function");
+                l_rc = SBE_FUNC_NOT_SUPPORTED;
+
+                // @TODO via RTC : 129166
+                //       force assert
+                break;
+            }
+
+            // Call the ChipOp function
+            l_rc = l_pFuncP ((uint8_t *)i_pArg);
+
+        } while(false); // Inner do..while loop ends here
+
+        SBE_DEBUG(SBE_FUNC"l_rc=[0x%08X]", l_rc);
+
+        // Handle FIFO reset case
+        if (l_rc == SBE_FIFO_RC_RESET)
+        {
+            // @TODO via RTC : 126147
+            //       Handle FIFO reset flow
+            pk_irq_enable(SBE_IRQ_SBEFIFO_DATA);
+            continue;
+        }
+
+        switch (l_rc)
+        {
+            // EOT arrived prematurely in upstream FIFO
+            // or there were unexpected data in upstream
+            // FIFO
+            case SBE_FIFO_RC_EOT_ACKED:
+            case SBE_FIFO_RC_EOT_ACK_FAILED:
+                SBE_ERROR(SBE_FUNC"Received unexpected EOT, l_rc[0x%08X]",
+                                 l_rc);
+                sbeBuildMinRespHdr(&l_sbeDownFifoRespBuf[0],
+                                    l_dist2StatusHdr,
+                                    SBE_PRI_INVALID_DATA,
+                                    SBE_SEC_GENERIC_FAILURE_IN_EXECUTION,
+                                    0);
+                l_rc = sbeDownFifoEnq_mult (++l_dist2StatusHdr,
+                                        &l_sbeDownFifoRespBuf[0]);
+                if (l_rc)
+                {
+                    SBE_ERROR(SBE_FUNC"sbeDownFifoEnq_mult failure,"
+                        " l_rc[0x0%08X]", l_rc);
+                    // not attempting to signal EOT
+                    break;
+                }
+                // Follow through to signal EOT in downstream
+
+            case SBE_SEC_OPERATION_SUCCESSFUL: // Successful execution
+                // Signal EOT in Downstream FIFO
+                l_rc = sbeDownFifoSignalEot();
+                if (l_rc)
+                {
+                    SBE_ERROR(SBE_FUNC"sbeDownFifoSignalEot failure,"
+                        " l_rc[0x0%08X]", l_rc);
+                }
+                SBE_INFO(SBE_FUNC"ChipOp Done");
+                break;
+
+             default:
+                break;
+        }
+
+        // @TODO via RTC : 126147
+        //       Review all the scenarios
+        // Enable the new data available interrupt
+        pk_irq_enable(SBE_IRQ_SBEFIFO_DATA);
+
+    } while(true); // Thread always exists
+}
+
+//////////////////////////////////////////////////////
+//////////////////////////////////////////////////////
+void sbeAsyncCommandProcessor_routine(void *arg)
+{
+    SBE_TRACE("sbeAsyncCommandProcessor Thread started");
+
+    do
+    {
+        //  @TODO RTC via : 130392
+        //        Add infrastructure for host interface
+
+    } while(0);
+}
diff --git a/src/ppe/sbe/sbefw/sbecmdreceiver.C b/src/ppe/sbe/sbefw/sbecmdreceiver.C
new file mode 100644
index 0000000..a58636b
--- /dev/null
+++ b/src/ppe/sbe/sbefw/sbecmdreceiver.C
@@ -0,0 +1,175 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/sbefw/sbecmdreceiver.C $                          */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/*
+ * @file: ppe/sbe/sbefw/sbecmdreceiver.C
+ *
+ * @brief This file contains the SBE Command Receiver Thread Routine
+ *
+ */
+
+
+#include "sbeexeintf.H"
+#include "sbefifo.H"
+#include "sbecmdparser.H"
+#include "sbeirq.H"
+#include "sbetrace.H"
+#include "sbe_sp_intf.H"
+
+sbeCmdReqBuf_t g_sbeCmdHdr;
+sbeCmdRespHdr_t g_sbeCmdRespHdr;
+
+//////////////////////////////////////////////////////
+//////////////////////////////////////////////////////
+void sbeCommandReceiver_routine(void *i_pArg)
+{
+    #define SBE_FUNC " sbeCommandReceiver_routine "
+    SBE_ENTER(SBE_FUNC);
+
+    do
+    {
+        uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL;
+
+        // @TODO via RTC: 128944
+        //       Read Scratchpad
+
+        // Wait for new data in FIFO or FIFO reset interrupt
+        int l_rcPk = pk_semaphore_pend (&g_sbeSemCmdRecv, PK_WAIT_FOREVER);
+
+        // @TODO via RTC: 128658
+        //       Review if Mutex protection is required
+        //       for all the globals used between threads
+        g_sbeCmdRespHdr.prim_status = SBE_PRI_OPERATION_SUCCESSFUL;
+        g_sbeCmdRespHdr.sec_status  = SBE_SEC_OPERATION_SUCCESSFUL;
+        g_sbeCmdHdr.cmdClass = SBE_CMD_CLASS_UNKNOWN;
+
+        // inner loop for command handling
+        do
+        {
+            // pk API failure
+            if (l_rcPk != PK_OK)
+            {
+                break;
+            }
+
+            SBE_DEBUG(SBE_FUNC"unblocked");
+
+            // @TODO via RTC: 128943
+            //       Host services / OPAL handling
+
+            // @TODO via RTC: 128945
+            // Handle protocol violation if needed (a long term goal)
+
+            // The responsibility of this thread is limited to dequeueing
+            // only the first two word entries from the protocol header.
+            uint8_t len = sizeof( g_sbeCmdHdr)/ sizeof(uint32_t);
+            l_rc = sbeUpFifoDeq_mult ( len, (uint32_t *)&g_sbeCmdHdr );
+
+            // If FIFO reset is requested,
+            if (l_rc == SBE_FIFO_RC_RESET)
+            {
+                SBE_ERROR(SBE_FUNC"FIFO reset received");
+                g_sbeCmdRespHdr.prim_status =
+                    (uint16_t)SBE_FIFO_RESET_RECEIVED;
+                g_sbeCmdRespHdr.sec_status  =
+                    (uint16_t)SBE_SEC_GENERIC_FAILURE_IN_EXECUTION;
+                break;
+            }
+
+            // If we received EOT pre-maturely or
+            // got an error while Ack'ing EOT
+            if ( (l_rc == SBE_FIFO_RC_EOT_ACKED)  ||
+                 (l_rc == SBE_FIFO_RC_EOT_ACK_FAILED) )
+            {
+                SBE_ERROR(SBE_FUNC"sbeUpFifoDeq_mult failure, "
+                          " l_rc=[0x%08X]", l_rc);
+                g_sbeCmdRespHdr.prim_status =
+                            SBE_PRI_INVALID_DATA;
+                g_sbeCmdRespHdr.sec_status  =
+                            SBE_SEC_GENERIC_FAILURE_IN_EXECUTION;
+                l_rc = SBE_SEC_OPERATION_SUCCESSFUL;
+                break;
+            }
+
+            // Any other FIFO access issue
+            if ( l_rc != SBE_SEC_OPERATION_SUCCESSFUL)
+            {
+                SBE_ERROR(SBE_FUNC"sbeUpFifoDeq_mult failue, "
+                          "l_rc=[0x%08X]", l_rc);
+                break;
+            }
+
+            // validate the command class and sub-class opcodes
+            l_rc = sbeValidateCmdClass (
+                        g_sbeCmdHdr.cmdClass,
+                        g_sbeCmdHdr.command ) ;
+
+            if (l_rc)
+            {
+                // Command Validation failed;
+                SBE_ERROR(SBE_FUNC"Command validation failed");
+                g_sbeCmdRespHdr.prim_status = SBE_PRI_INVALID_COMMAND;
+                g_sbeCmdRespHdr.sec_status  = l_rc;
+                l_rc = SBE_SEC_OPERATION_SUCCESSFUL;
+                break;
+            }
+
+            // @TODO via RTC: 126146
+            //       validate state machine constraints
+
+        } while (false); // Inner do..while ends
+
+        // Unblock the command processor thread
+        // if we could dequeue the header successfully
+        if ((l_rcPk == PK_OK) && (l_rc == SBE_SEC_OPERATION_SUCCESSFUL))
+        {
+            l_rcPk = pk_semaphore_post(&g_sbeSemCmdProcess);
+        }
+
+        if ((l_rcPk != PK_OK) || (l_rc != SBE_SEC_OPERATION_SUCCESSFUL))
+        {
+            // It's likely a code bug or PK failure, or
+            // FIFO reset request arrived or any other
+            // FIFO access failure.
+
+            // @TODO via RTC : 129166
+            //       Review if we need to add ASSERT here
+
+            // Add Error trace, collect FFDC and
+            // continue wait for the next interrupt
+            SBE_ERROR(SBE_FUNC"Unexpected failure, "
+                "l_rcPk=[%d], g_sbeSemCmdProcess.count=[%d], l_rc=[%d]",
+                l_rcPk, g_sbeSemCmdProcess.count, l_rc);
+
+            pk_irq_enable(SBE_IRQ_SBEFIFO_DATA);
+
+            continue;
+        }
+
+        SBE_DEBUG(SBE_FUNC"Posted g_sbeSemCmdProcess, "
+               "g_sbeSemCmdProcess.count=[%d]", g_sbeSemCmdProcess.count);
+
+    } while (true); // thread always exists
+    #undef SBE_FUNC
+}
diff --git a/src/ppe/sbe/sbefw/sbecmdscomaccess.C b/src/ppe/sbe/sbefw/sbecmdscomaccess.C
new file mode 100644
index 0000000..b485937
--- /dev/null
+++ b/src/ppe/sbe/sbefw/sbecmdscomaccess.C
@@ -0,0 +1,306 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/sbefw/sbecmdscomaccess.C $                        */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/*
+ * @file: ppe/sbe/sbefw/sbecmdscomaccess.C
+ *
+ * @brief This file contains the SBE SCOM Access chipOps
+ *
+ */
+
+#include "sbecmdscomaccess.H"
+#include "sbefifo.H"
+#include "sbe_sp_intf.H"
+#include "sbetrace.H"
+
+//////////////////////////////////////////////////////
+//////////////////////////////////////////////////////
+uint32_t sbeGetScom (uint8_t *i_pArg)
+{
+    #define SBE_FUNC " sbeGetScom "
+    SBE_ENTER(SBE_FUNC);
+
+    uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL;
+
+    do
+    {
+        uint16_t l_primStatus = g_sbeCmdRespHdr.prim_status;
+        uint16_t l_secStatus  = g_sbeCmdRespHdr.sec_status ;
+
+        // Will attempt to dequeue two entries for
+        // the scom addresses plus the expected
+        // EOT entry at the end
+
+        // @TODO via RTC : 130575
+        //       Optimize both the RC handling and
+        //       FIFO operation infrastructure.
+        uint8_t  l_len2dequeue  = 3;
+        uint32_t l_scomAddr[3] = {0};
+        l_rc = sbeUpFifoDeq_mult (l_len2dequeue, &l_scomAddr[0]);
+
+        // If FIFO access failure
+        if (l_rc == SBE_SEC_FIFO_ACCESS_FAILURE)
+        {
+            // Let command processor routine to handle the RC.
+            break;
+        }
+
+        // If we didn't receive EOT yet
+        if ( (l_rc != SBE_FIFO_RC_EOT_ACKED)  &&
+             (l_rc != SBE_FIFO_RC_EOT_ACK_FAILED) )
+        {
+            // We must have received unexpected data
+            // on the upstream FIFO.
+
+            // Flush upstream FIFO until EOT;
+            l_len2dequeue = 1;
+            l_rc = sbeUpFifoDeq_mult ( l_len2dequeue, NULL, true );
+
+            // We will break out here to force
+            // command processor routine to handle the RC.
+            // If the RC indicates the receipt of EOT,
+            // It would send the appropriate response
+            // back into the down stream FIFO.
+            // For all other failures, it would force
+            // timeout the chipOp operation
+            break;
+        }
+
+        // If EOT arrived prematurely
+        if ( ((l_rc == SBE_FIFO_RC_EOT_ACKED)  ||
+              (l_rc == SBE_FIFO_RC_EOT_ACK_FAILED))
+              && (l_len2dequeue < 2) )
+        {
+            // We will break out here to force
+            // command processor routine to respond
+            // into the downstream FIFO with
+            // primary response code as SBE_PRI_INVALID_DATA
+            break;
+        }
+
+        uint32_t l_sbeDownFifoRespBuf[6] = {0};
+        uint32_t l_pcbpibStatus = SBE_PCB_PIB_ERROR_NONE;
+        uint8_t  l_len2enqueue  = 0;
+        uint8_t  l_index = 0;
+        // successfully dequeued two entries for
+        // scom address followed by the EOT entry
+        if ( ((l_rc == SBE_FIFO_RC_EOT_ACKED)  ||
+              (l_rc == SBE_FIFO_RC_EOT_ACK_FAILED))
+              && (l_len2dequeue == 2) )
+        {
+            // @TODO via RTC : 126140
+            //       Support Indirect SCOM
+            // Data entry 1 : Scom Register Address (0..31)
+            // Data entry 2 : Register Address (32..63)
+            // For Direct SCOM, will ignore entry 1
+
+            uint64_t l_scomData = 0;
+            SBE_TRACE(SBE_FUNC"scomAddr1[0x%08X]", l_scomAddr[1]);
+            l_rc = getscom (0, l_scomAddr[1], &l_scomData);
+
+            if (l_rc) // scom failed
+            {
+                SBE_ERROR(SBE_FUNC"getscom failed, l_rc[0x%08X]", l_rc);
+                l_primStatus = SBE_PRI_GENERIC_EXECUTION_FAILURE;
+                l_secStatus  = SBE_SEC_GENERIC_FAILURE_IN_EXECUTION;
+                l_pcbpibStatus = l_rc;
+            }
+
+            if (!l_rc) // successful scom
+            {
+                SBE_TRACE(SBE_FUNC"getscom succeeds, l_scomData[0x%X]",
+                                   l_scomData);
+
+                l_sbeDownFifoRespBuf[0] = (uint32_t)(l_scomData>>32);
+                l_sbeDownFifoRespBuf[1] = (uint32_t)(l_scomData);
+
+                // Push the data into downstream FIFO
+                l_len2enqueue = 2;
+                l_rc = sbeDownFifoEnq_mult (l_len2enqueue,
+                                      &l_sbeDownFifoRespBuf[0]);
+                if (l_rc)
+                {
+                    // will let command processor routine
+                    // handle the failure
+                    break;
+                }
+                l_index = 2;
+            } // end successful scom
+        } // end successful dequeue
+
+        // Build the response header packet
+
+        uint8_t l_curIndex = l_index ;
+        sbeBuildMinRespHdr(&l_sbeDownFifoRespBuf[0],
+                            l_curIndex,
+                            l_primStatus,
+                            l_secStatus,
+                            l_pcbpibStatus,
+                            l_index);
+
+        // Now enqueue into the downstream FIFO
+        l_len2enqueue = ++l_curIndex - l_index;
+        l_rc = sbeDownFifoEnq_mult (l_len2enqueue,
+                               &l_sbeDownFifoRespBuf[l_index]);
+        if (l_rc)
+        {
+           // will let command processor routine
+           // handle the failure
+           break;
+        }
+
+    } while(false);
+
+    return l_rc;
+    #undef SBE_FUNC
+}
+
+/////////////////////////////////////////////////////
+//////////////////////////////////////////////////////
+uint32_t sbePutScom (uint8_t *i_pArg)
+{
+    #define SBE_FUNC " sbePutScom "
+    SBE_ENTER(SBE_FUNC);
+
+    uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL;
+
+    do
+    {
+        uint16_t l_primStatus = g_sbeCmdRespHdr.prim_status;
+        uint16_t l_secStatus  = g_sbeCmdRespHdr.sec_status ;
+
+        // Will attempt to dequeue four entries for
+        // the scom address (two entries) and the
+        // corresponding data (two entries) plus
+        // the expected EOT entry at the end
+
+        // @TODO via RTC : 130575
+        //       Optimize both the RC handling and
+        //       FIFO operation infrastructure.
+        uint8_t  l_len2dequeue  = 5;
+        uint32_t l_scomAddr_Data[5] = {0};
+        l_rc = sbeUpFifoDeq_mult (l_len2dequeue, &l_scomAddr_Data[0]);
+
+        // If FIFO access failure
+        if (l_rc == SBE_SEC_FIFO_ACCESS_FAILURE)
+        {
+            // Let command processor routine to handle the RC.
+            break;
+        }
+
+        // If we didn't receive EOT yet
+        if ( (l_rc != SBE_FIFO_RC_EOT_ACKED)  &&
+             (l_rc != SBE_FIFO_RC_EOT_ACK_FAILED) )
+        {
+            // We must have received unexpected data
+            // on the upstream FIFO.
+
+            // Flush upstream FIFO until EOT;
+            l_len2dequeue = 1;
+            l_rc = sbeUpFifoDeq_mult ( l_len2dequeue, NULL, true );
+
+            // We will break out here to force
+            // command processor routine to handle the RC.
+            // If the RC indicates the receipt of EOT,
+            // It would send the appropriate response
+            // back into the down stream FIFO.
+            // For all other failures, it would force
+            // timeout the chipOp operation
+            break;
+        }
+
+        // If EOT arrived prematurely
+        if ( ((l_rc == SBE_FIFO_RC_EOT_ACKED)  ||
+              (l_rc == SBE_FIFO_RC_EOT_ACK_FAILED))
+              && (l_len2dequeue < 4) )
+        {
+            // We will break out here to force
+            // command processor routine to respond
+            // into the downstream FIFO with
+            // primary response code as SBE_PRI_INVALID_DATA
+            break;
+        }
+
+        uint64_t l_scomData = 0;
+        uint32_t l_sbeDownFifoRespBuf[4] = {0};
+        uint32_t l_pcbpibStatus = SBE_PCB_PIB_ERROR_NONE;
+        uint8_t  l_len2enqueue  = 0;
+        // successfully dequeued two entries for
+        // scom address followed by the EOT entry
+        if ( ((l_rc == SBE_FIFO_RC_EOT_ACKED)  ||
+              (l_rc == SBE_FIFO_RC_EOT_ACK_FAILED))
+              && (l_len2dequeue == 4) )
+        {
+            // @TODO via RTC : 126140
+            //       Support Indirect SCOM
+            // Data entry 1 : Scom Register Address (0..31)
+            // Data entry 2 : Scom Register Address (32..63)
+            // Data entry 3 : Scom Register Data (0..31)
+            // Data entry 4 : Scom Register Data (32..63)
+            // For Direct SCOM, will ignore entry 1
+            l_scomData = ((uint64_t)(l_scomAddr_Data[2])<<32)
+                           | (l_scomAddr_Data[3]);
+
+            SBE_DEBUG(SBE_FUNC"scomAddr0[0x%X]"
+                              "scomAddr1[0x%X]"
+                              "scomData0[0x%X]"
+                              "scomData1[0x%X]",
+                  l_scomAddr_Data[0], l_scomAddr_Data[1],
+                  l_scomAddr_Data[2], l_scomAddr_Data[3]);
+
+            l_rc = putscom (0, l_scomAddr_Data[1], l_scomData);
+
+            if (l_rc) // scom failed
+            {
+                SBE_ERROR(SBE_FUNC"putscom failed, l_rc[0x%08X]", l_rc);
+                l_primStatus = SBE_PRI_GENERIC_EXECUTION_FAILURE;
+                l_secStatus  = SBE_SEC_GENERIC_FAILURE_IN_EXECUTION;
+                l_pcbpibStatus = l_rc;
+            }
+        } // end successful dequeue
+
+        // Build the response header packet
+
+        uint8_t  l_curIndex = 0;
+        sbeBuildMinRespHdr(&l_sbeDownFifoRespBuf[0],
+                            l_curIndex,
+                            l_primStatus,
+                            l_secStatus,
+                            l_pcbpibStatus);
+
+        // Now enqueue into the downstream FIFO
+        l_len2enqueue = ++l_curIndex;
+        l_rc = sbeDownFifoEnq_mult (l_len2enqueue, &l_sbeDownFifoRespBuf[0]);
+        if (l_rc)
+        {
+           // will let command processor routine
+           // handle the failure
+           break;
+        }
+
+    } while(false);
+
+    return l_rc;
+    #undef SBE_FUNC
+}
diff --git a/src/ppe/sbe/sbefw/sbecmdscomaccess.H b/src/ppe/sbe/sbefw/sbecmdscomaccess.H
new file mode 100644
index 0000000..6377512
--- /dev/null
+++ b/src/ppe/sbe/sbefw/sbecmdscomaccess.H
@@ -0,0 +1,59 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/sbefw/sbecmdscomaccess.H $                        */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/*
+ * @file: ppe/sbe/sbefw/sbecmdscomaccess.H
+ *
+ * @brief This file contains the Interfaces for the SCOM Access chip-ops
+ *
+ */
+
+#ifndef __SBEFW_SBECMDSCOMACCESS_H
+#define __SBEFW_SBECMDSCOMACCESS_H
+
+#include <stdint.h>
+
+/**
+  * @brief sbeDownFifoGetStatus : Write data into Downstream FIFO
+  *
+  * @param[in] i_pArg Buffer to be passed to the function (not used as of now)
+  *
+  * @return    Rc from the FIFO access utility
+  */
+uint32_t sbeGetScom (uint8_t *i_pArg);
+
+
+/**
+  * @brief sbeDownFifoGetStatus : Write data into Downstream FIFO
+  *
+  * @param[in] i_pArg Buffer to be passed to the function (not used as of now)
+  *
+  * @return    Rc from the FIFO access utility
+  */
+uint32_t sbePutScom (uint8_t *i_pArg);
+
+
+
+
+#endif /* __SBEFW_SBECMDSCOMACCESS_H */
diff --git a/src/ppe/sbe/sbefw/sbeexeintf.H b/src/ppe/sbe/sbefw/sbeexeintf.H
new file mode 100644
index 0000000..ba558b0
--- /dev/null
+++ b/src/ppe/sbe/sbefw/sbeexeintf.H
@@ -0,0 +1,195 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/sbefw/sbeexeintf.H $                              */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/*
+ * @file: ppe/sbe/sbefw/sbeexeintf.H
+ *
+ * @brief This file contains the SBE control loop firmware details like
+ *        - Thread priority enums
+ *        - Thread stack size and space enums
+ *        - Thread sub-rountine declarations
+ *        - IRQ setup and ISR declarations
+ *        - Other Common declaration among all the threads
+ */
+
+#ifndef __SBEFW_SBE_H
+#define __SBEFW_SBE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "pk.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @brief enums for priorities for thread creation
+ *
+ */
+typedef enum
+{
+    THREAD_PRIORITY_MAX_0,
+    THREAD_PRIORITY_1,
+    THREAD_PRIORITY_2,
+    THREAD_PRIORITY_3,
+    THREAD_PRIORITY_4,
+    THREAD_PRIORITY_5,
+    THREAD_PRIORITY_6,
+    THREAD_PRIORITY_7,
+    THREAD_PRIORITY_8,
+    THREAD_PRIORITY_MIN_30 = 30,
+} sbeThreadPriorities ;
+
+/**
+ * @brief enums for thread stack sizes
+ *  - Non-Critical Stack used by non-critical interrupt handlers
+ *  - Critical Stack used for critical interrupts
+ *  - Stacks for each thread
+ *
+ * @TODO via RTC : 128657
+ *  - Measure the actual thread stack utilization
+ *  - This will be a continuous activity
+ */
+enum sbeThreadStackSize
+{
+    SBE_NONCRITICAL_STACK_SIZE           = 256,
+    SBE_THREAD_ASYNC_CMD_PROC_STACK_SIZE = 256,
+    SBE_THREAD_CMD_RECV_STACK_SIZE       = 512,
+    SBE_THREAD_SYNC_CMD_PROC_STACK_SIZE  = 2048,
+};
+
+/**
+ * @brief enums SBE internal error codes
+ *
+*/
+enum sbeInternalResponseCodes
+{
+    SBE_FIFO_RESET_RECEIVED  = 0xFA,
+    SBE_FIFO_RESET_HANDLING_FAILED = 0xFB,
+    SBE_FUNC_NOT_SUPPORTED   = 0xFC,
+};
+
+/**
+ * @brief Global semaphore : g_sbeSemCmdRecv
+ *
+ *   This is used to synchronize between the ISR and
+ *   the command receiver thread.
+ *
+ */
+extern PkSemaphore g_sbeSemCmdRecv;
+
+/**
+ * @brief Global semaphore : g_sbeSemCmdProcess
+ *
+ *   This is used to synchronize between command receiver thread
+ *   and synchronous command processor thread.
+ *
+ */
+extern PkSemaphore g_sbeSemCmdProcess;
+
+/**
+ * @brief Global semaphore : g_sbeSemFifoReset
+ *
+ *   This is used to synchronize the graceful handling of FIFO reset
+ *   between command receiver and synchronous command processor threads.
+ *
+ */
+extern PkSemaphore g_sbeSemFifoReset;
+
+/**
+ * @TODO via RTC : 128658
+ *   Mutex protect the critical data
+ *   e.g., add Mutex g_sbeMutCmdReqBuf etc.
+ */
+
+/**
+ * @brief sbeCommandReceiver_routine
+ *    The major responsibilities of this thread are :
+ *        - Determine the reason for the interrupt
+ *             - FIFO New data
+ *             - FIFO reset
+ *             - Host services
+ *        - Dequeue the mandatory 2 entry header from upstream FIFO
+ *        - Command input data validation
+ *        - SBE State and pre-requirements validation
+ *        - FFDC collection and FIFO flush upon validation failure
+ *        - Unblock SBE command processor thread
+ *        - Perform FIFO reset upon request from SP
+ *
+ *  @param[in]  i_pArg - Any buffer needed to be passed to the thread routine
+ */
+void sbeCommandReceiver_routine(void *i_pArg);
+
+/**
+ * @brief sbeSyncCommandProcessor_routine
+ *    The major responsibilities of this thread are :
+ *        - Dequeue data payload from upstream FIFO
+ *        - Un-marshalling of the command request data
+ *        - Blacklist validation
+ *        - FFDC collection upon validation failure
+ *        - Invoke the corresponding Hardware access utility
+ *          or the HWP corresponding to the chipOp request
+ *        - FFDC collection and FIFO flush upon hardware access / HWP failure
+ *        - Build the response buffer with the data and the header
+ *        - Enqueue the response into the Downstream FIFO
+ *        - Un-mask the new data available interrupt
+ *
+ *  @param[in]  i_pArg - Any buffer needed to be passed to the thread routine
+ */
+void sbeSyncCommandProcessor_routine(void *i_pArg);
+
+/**
+ * @brief sbeAsyncCommandProcessor_routine
+ *        @TODO RTC via : 130392
+ *               Add infrastructure for host interface
+ *
+ *  @param[in]  i_pArg - Any buffer needed to be passed to the thread routine
+ */
+void sbeAsyncCommandProcessor_routine(void *i_pArg);
+
+
+/* @brief  ISR for all application FIFO Interrupts
+ *         - FIFO : New data available
+ *         - FIFO : Reset Request
+ *
+ * @param[in/out]  i_pArg - Any buffer needed to be passed to the handler
+ * @param[in]      i_irq  - IRQ number as defined in the SBE PPE spec
+ */
+void sbe_fifo_interrupt_handler(void* i_pArg, PkIrqId i_irq);
+
+
+/* brief : Register SBE interrupt handlers and enable the IRQs
+ *
+ * @return int   PK_OK - Success (IRQ Setup was successful)
+ *               PK_INVALID_ARGUMENT_IRQ_HANDLER - Invalid argument passed
+ *                                                 (Code bug)
+ *
+ */
+int sbeIRQSetup (void);
+
+
+#endif /* __SBEFW_SBE_H  */
diff --git a/src/ppe/sbe/sbefw/sbefifo.C b/src/ppe/sbe/sbefw/sbefifo.C
new file mode 100644
index 0000000..1489ad1
--- /dev/null
+++ b/src/ppe/sbe/sbefw/sbefifo.C
@@ -0,0 +1,274 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/sbefw/sbefifo.C $                                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/*
+ * @file: ppe/sbe/sbefw/sbefifo.C
+ *
+ * @brief This file contains the SBE FIFO Commands
+ *
+ */
+
+#include "sbeexeintf.H"
+#include "sbefifo.H"
+#include "sbetrace.H"
+#include "sbe_sp_intf.H"
+
+//////////////////////////////////////////////////////
+//////////////////////////////////////////////////////
+uint32_t sbeUpFifoDeq_mult (uint8_t     &io_len,
+                            uint32_t    *o_pData,
+                            const bool  i_flush)
+{
+    #define SBE_FUNC " sbeUpFifoDeq_mult "
+    uint32_t l_rc = SBE_FIFO_RC_UNKNOWN;
+    uint8_t  l_len = 0;
+
+    // @TODO via RTC : 130575
+    //       Refactor this utility to
+    //       optimize RC handling, stack usage
+    //       and FIFO operation infrastructure.
+    //
+
+    do
+    {
+        sbe_upfifo_entry_t l_data = {0};
+        uint64_t l_upfifo_data = 0;
+
+        // Read Double word from the Upstream FIFO;
+        // The DW data represents the first 32 bits of data word entry
+        // followed by the status bits.
+
+        // Bit 0-31    : Data
+        // Bit 32      : Data valid flag
+        // Bit 33      : EOT flag
+        // Bit 34-63   : Status (2-31)
+        // Valid : EOT
+        //    1  : 0   -> data=message
+        //    0  : 1   -> data=dummy_data of EOT operation
+        //    0  : 0   -> data=dummy_data
+        //    1  : 1   -> Not used
+
+        l_rc = sbeUpFifoDeq ( &l_upfifo_data );
+
+        if (l_rc)
+        {
+            // Error while dequeueing from upstream FIFO
+            SBE_ERROR(SBE_FUNC"sbeUpFifoDeq failed,"
+                         "l_rc=[0x%08X]", l_rc);
+            l_rc = SBE_SEC_FIFO_ACCESS_FAILURE;
+            break;
+        }
+
+        l_data.upfifo_data   =   (uint32_t)(l_upfifo_data>>32);
+        l_data.upfifo_status.upfifo_status_uint32 = (uint32_t)
+                                               (l_upfifo_data);
+
+        SBE_DEBUG(SBE_FUNC"sbeUpFifoDeq, "
+                    "l_data.upfifo_data=[0x%08X],"
+                    "l_data.upfifo_status=[0x%08X]",
+                     l_data.upfifo_data,
+                     l_data.upfifo_status.upfifo_status_uint32);
+
+        // If FIFO reset is requested
+        if(l_data.upfifo_status.upfifo_status_bitset.req_upfifo_reset)
+        {
+            // @TODO via RTC : 126147
+            //       Review reset loop flow in here.
+            //       Received a FIFO reset request
+            l_rc = SBE_FIFO_RC_RESET;
+            break;
+        }
+
+        // if EOT flag is set
+        //    clear EOT
+        if (l_data.upfifo_status.upfifo_status_bitset.eot_flag)
+        {
+            l_rc = sbeUpFifoAckEot();
+            if (l_rc)
+            {
+                // Error while ack'ing EOT in upstream FIFO
+                SBE_ERROR(SBE_FUNC"sbeUpFifoAckEot failed,"
+                          "l_rc=[0x%08X]", l_rc);
+                // Collect FFDC
+                l_rc = SBE_FIFO_RC_EOT_ACK_FAILED;
+            }
+            else
+            {
+                l_rc = SBE_FIFO_RC_EOT_ACKED;
+            }
+            break;
+        }
+
+        // if Upstream FIFO is empty,
+        if (l_data.upfifo_status.upfifo_status_bitset.fifo_empty)
+        {
+            l_rc = SBE_FIFO_RC_EMPTY;
+            continue;
+        }
+
+        if (i_flush)
+        {
+            l_len  = 0; // to force the upFIFO flush until EOT arrives
+            continue;
+        }
+
+        o_pData[l_len] = l_data.upfifo_data;
+        ++l_len;
+        l_rc = SBE_SEC_OPERATION_SUCCESSFUL;
+
+    } while(l_len<io_len);
+
+    // Return the length of entries dequeued.
+    // When user sets i_flush as true, this
+    // would return io_len as 0;
+    io_len = l_len;
+    return l_rc;
+
+    #undef SBE_FUNC
+}
+
+//////////////////////////////////////////////////////
+//////////////////////////////////////////////////////
+uint32_t sbeDownFifoEnq_mult (uint8_t        &io_len,
+                              const uint32_t *i_pData)
+{
+    #define SBE_FUNC " sbeDownFifoEnq_mult "
+    uint8_t  l_rc   = SBE_FIFO_RC_UNKNOWN;
+    uint8_t  l_len = 0;
+
+    // @TODO via RTC : 130575
+    //       Refactor this utility to
+    //       optimize RC handling, stack usage
+    //       and FIFO operation infrastructure.
+
+    do
+    {
+        sbe_downfifo_status_t l_downFifoStatus ;
+        typedef union
+        {
+            uint64_t status;
+            uint64_t data;
+        } sbeDownFiFoEntry_t;
+        sbeDownFiFoEntry_t l_sbeDownFiFoEntry ;
+
+        // Read the down stream FIFO status
+        l_rc = sbeDownFifoGetStatus (&l_sbeDownFiFoEntry.status);
+        if (l_rc)
+        {
+            // Error while reading downstream FIFO status
+            SBE_ERROR(SBE_FUNC"sbeDownFifoGetStatus failed, "
+                      "l_rc=[0x%08X]", l_rc);
+            l_rc = SBE_SEC_FIFO_ACCESS_FAILURE;
+            break;
+        }
+
+        l_downFifoStatus.downfifo_status_uint32 = (uint32_t)
+                                      (l_sbeDownFiFoEntry.status>>32);
+
+        SBE_DEBUG(SBE_FUNC"downstream fifo status[0x%08X]",
+                   l_downFifoStatus.downfifo_status_uint32);
+
+        // Check if there was a FIFO reset request from SP
+        if (l_downFifoStatus.downfifo_status_bitset.req_upfifo_reset)
+        {
+            // @TODO via RTC : 126147
+            //       Review reset loop flow in here.
+            //       Received an upstream FIFO reset request
+            SBE_ERROR(SBE_FUNC"Received reset request");
+            l_rc = SBE_FIFO_RC_RESET;
+            break;
+        }
+
+        // Check if downstream FIFO is full
+        if (l_downFifoStatus.downfifo_status_bitset.fifo_full)
+        {
+            // Downstream FIFO is full
+            SBE_INFO(SBE_FUNC"Downstream FIFO is full");
+            l_rc = SBE_FIFO_RC_FULL; // in case we ever add timeout
+            continue;
+        }
+
+        // PIB write data format:
+        // Bit 0 - 31  : Data
+        // Bit 32 - 63 : Unused
+
+        l_sbeDownFiFoEntry.data   = (uint64_t)(*(i_pData+l_len));
+        l_sbeDownFiFoEntry.data   = l_sbeDownFiFoEntry.data<<32;
+
+        SBE_DEBUG(SBE_FUNC"Downstream fifo data entry[0x%08X]",
+                                    (l_sbeDownFiFoEntry.data>>32));
+
+        // Write the data into the downstream FIFO
+        l_rc = sbeDownFifoEnq (l_sbeDownFiFoEntry.data);
+        if (l_rc)
+        {
+            SBE_ERROR(SBE_FUNC"sbeDownFifoEnq failed, "
+                              "l_rc[0x%08X]", l_rc);
+            l_rc = SBE_SEC_FIFO_ACCESS_FAILURE;
+            break;
+        }
+
+        l_rc = SBE_SEC_OPERATION_SUCCESSFUL;
+        ++l_len;
+
+    } while(l_len<io_len);
+
+    io_len = l_len;
+    return l_rc;
+    #undef SBE_FUNC
+}
+
+////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////
+void sbeBuildMinRespHdr ( uint32_t *io_pBuf,
+                          uint8_t  &io_curIndex,
+                    const uint16_t  i_primStatus,
+                    const uint16_t  i_secStatus,
+                    const uint32_t  i_pcbpibStatus,
+                    const uint8_t   i_startIndex )
+{
+    do
+    {
+        if (!io_pBuf)
+        {
+            break;
+        }
+
+        io_pBuf[io_curIndex] = sbeBuildRespHeaderMagicCodeCmdClass();
+        io_pBuf[++io_curIndex] = sbeBuildRespHeaderStatusWordLocal(
+                                          i_primStatus, i_secStatus);
+
+        // @TODO via RTC: 128916
+        //       pcb-pib error is optional,
+        //       not needed for success case
+        io_pBuf[++io_curIndex]    = i_pcbpibStatus;
+
+        // Somehow this compiler isn't allowing the
+        // index pre-increment for the last array entry
+        // directly embedded into the assignment
+        ++io_curIndex;
+        io_pBuf[io_curIndex]   = io_curIndex - i_startIndex + 1;
+
+    } while(false);
+}
diff --git a/src/ppe/sbe/sbefw/sbefifo.H b/src/ppe/sbe/sbefw/sbefifo.H
new file mode 100644
index 0000000..6838f3d
--- /dev/null
+++ b/src/ppe/sbe/sbefw/sbefifo.H
@@ -0,0 +1,490 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/sbefw/sbefifo.H $                                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/*
+ * @file: ppe/sbe/sbefw/sbefifo.H
+ *
+ * @brief This file contains the SBE FIFO Commands
+ *
+ */
+
+#ifndef __SBEFW_SBEFIFO_H
+#define __SBEFW_SBEFIFO_H
+
+#include "sbeexeintf.H"
+#include "sbetrace.H"
+#include "ppe42_scom.h"
+#include "sbe_sp_intf.H"
+
+/**
+  * @brief SBE FIFO Access addresses
+  *
+  */
+const uint32_t SBE_FIFO_BASE                     =  0x000B0000;
+
+const uint32_t SBE_UPSTREAM_FIFO_DEQ_ADD         = SBE_FIFO_BASE + 0x0000;
+const uint32_t SBE_UPSTREAM_FIFO_STATUS          = SBE_FIFO_BASE + 0x0001;
+const uint32_t SBE_UPSTREAM_FIFO_SIGNAL_EOT      = SBE_FIFO_BASE + 0x0002;
+const uint32_t SBE_UPSTREAM_FIFO_REQ_RESET       = SBE_FIFO_BASE + 0x0003;
+const uint32_t SBE_UPSTREAM_FIFO_PERFORM_RESET   = SBE_FIFO_BASE + 0x0004;
+const uint32_t SBE_UPSTREAM_FIFO_ACK_EOT         = SBE_FIFO_BASE + 0x0005;
+
+const uint32_t SBE_DOWNSTREAM_FIFO_ENQ_ADD       = SBE_FIFO_BASE + 0x0010;
+const uint32_t SBE_DOWNSTREAM_FIFO_STATUS        = SBE_FIFO_BASE + 0x0011;
+const uint32_t SBE_DOWNSTREAM_FIFO_SIGNAL_EOT    = SBE_FIFO_BASE + 0x0012;
+const uint32_t SBE_DOWNSTREAM_FIFO_REQ_RESET     = SBE_FIFO_BASE + 0x0013;
+const uint32_t SBE_DOWNSTREAM_FIFO_PERFORM_RESET = SBE_FIFO_BASE + 0x0014;
+const uint32_t SBE_DOWNSTREAM_FIFO_ACK_EOT       = SBE_FIFO_BASE + 0x0015;
+
+/**
+  * @brief SBE Upstream FIFO Status bits
+  *
+  */
+
+typedef struct
+{
+    uint32_t   valid_flag:1;         // Bit 0
+    uint32_t   eot_flag:1;           // Bit 1
+    uint32_t   parity_err:1;         // Bit 2
+    uint32_t   reserved3_5:3;        // Bit 3:5
+    uint32_t   req_upfifo_reset:1;   // Bit 6
+    uint32_t   req_downfifo_reset:1; // Bit 7
+    uint32_t   signaling_eot:1;      // Bit 8
+    uint32_t   reserved9:1;          // Bit 9
+    uint32_t   fifo_full:1;          // Bit 10
+    uint32_t   fifo_empty:1;         // Bit 11
+    uint32_t   fifo_entry_count:4;   // Bit 12:15
+    uint32_t   fifo_valid_flags:8;   // Bit 16:23
+    uint32_t   fifo_eot_flags:8;     // Bit 24:31
+
+} sbe_upfifo_status_bitset_t ;
+
+typedef union
+{
+    sbe_upfifo_status_bitset_t upfifo_status_bitset;
+    uint32_t upfifo_status_uint32;
+} sbe_upfifo_status_t;
+
+/**
+  * @brief FIFO access return codes for internal purpose
+  *
+  */
+typedef enum
+{
+    SBE_FIFO_RC_ACCESS_SUCCESS = 0,
+    SBE_FIFO_RC_RESET          = 0xE0,
+    SBE_FIFO_RC_FULL,
+    SBE_FIFO_RC_EMPTY,
+    SBE_FIFO_RC_DUMMY_DATA,
+    SBE_FIFO_RC_EOT_ACKED,
+    SBE_FIFO_RC_EOT_ACK_FAILED,
+    SBE_FIFO_RC_UNKNOWN,
+} sbe_fifo_access_rc_t;
+
+
+/**
+  * @brief 64-bit DW structure for Upstream FIFO Read
+  *
+  */
+typedef struct
+{
+    uint32_t upfifo_data;
+    sbe_upfifo_status_t upfifo_status;
+} sbe_upfifo_entry_t ;
+
+
+/**
+  * @brief SBE Downstream FIFO Status bits
+  *
+  */
+typedef struct
+{
+    uint32_t   reserved0_1:2;        // Bit 0:1
+    uint32_t   parity_err:1;         // Bit 2
+    uint32_t   reserved3_5:3;        // Bit 3:5
+    uint32_t   req_downfifo_reset:1; // Bit 6
+    uint32_t   req_upfifo_reset:1;   // Bit 7
+    uint32_t   signaling_eot:1;      // Bit 8
+    uint32_t   reserved9:1;          // Bit 9
+    uint32_t   fifo_full:1;          // Bit 10
+    uint32_t   fifo_empty:1;         // Bit 11
+    uint32_t   fifo_entry_count:4;   // Bit 12:15
+    uint32_t   fifo_valid_flags:8;   // Bit 16:23
+    uint32_t   fifo_eot_flags:8;     // Bit 24:31
+
+} sbe_downfifo_status_bitset_t ;
+
+typedef union
+{
+    sbe_downfifo_status_bitset_t downfifo_status_bitset;
+    uint32_t                     downfifo_status_uint32;
+} sbe_downfifo_status_t;
+
+
+// @TODO via RTC 129073.
+// Put these structures in separate file as these are not FIFO specific.
+// Also make sure all FIFO structures are 32 bit alligned ( the largest
+// member should be atleast 4 byte). It is required as in sbe fifo
+// operation we are casting these structures to uint32_t pointer. It can
+// cause allignment issue if largest member of structure is not atleast
+// 32 bit. We can use bit fields to optimize  memory requirements.
+/**
+  * @brief Command Request Header
+  */
+typedef struct
+{
+    uint32_t len;
+    uint16_t reserved;
+    uint8_t cmdClass;
+    uint8_t command;
+}sbeCmdReqBuf_t;
+
+extern sbeCmdReqBuf_t g_sbeCmdHdr;
+
+/**
+  * @brief structure for generic header for fifo response.
+  *
+  */
+typedef struct
+{
+    uint16_t magicCode;
+    uint8_t cmdClass;
+    uint8_t command;
+    uint16_t primaryStatus;
+    uint16_t secondaryStatus;
+
+    /**
+      * @brief set the primary and secondary status
+      *
+      * @param[in] i_prim  Primary status
+      * @param[in] i_sec   Secondary status
+      *
+      * @return
+      */
+    void setStatus( const uint16_t i_prim, const uint16_t i_sec)
+    {
+        primaryStatus = i_prim;
+        secondaryStatus = i_sec;
+    }
+
+    /**
+      * @brief set initial values for response header
+      *
+      * @note  We did not set this in constructor as based on use case
+      *        it is possible that g_sbeCmdHdr does not have proper
+      *        values at time of object creation.
+      *
+      */
+    void init()
+    {
+        magicCode = 0xC0DE;
+        cmdClass  = g_sbeCmdHdr.cmdClass;
+        command = g_sbeCmdHdr.command;
+        primaryStatus = SBE_PRI_OPERATION_SUCCESSFUL;
+        secondaryStatus = SBE_SEC_OPERATION_SUCCESSFUL;
+    }
+
+}sbeResponseGenericHeader_t;
+
+/**
+  * @brief structure for ffdc header for fifo response.
+  *
+  */
+typedef struct sbeResponseFfdc
+{
+    uint16_t magicBytes;
+    uint16_t lenInWords;  // length in word( 4 byte )
+    //@TODO via RTC 129073.
+    //make fapiRc 64 bit
+    uint32_t fapiRc;
+
+    /**
+      * @brief set rc
+      *
+      * @param[in] i_rc  FAPI RC
+      *
+      * @return
+      */
+    void setRc(const uint32_t i_rc)
+    {
+        fapiRc = i_rc;
+    }
+
+    /**
+      * @brief constructor
+      *
+      * @param[in] i_rc  FAPI RC
+      *
+      * @return
+      */
+    sbeResponseFfdc()
+    {
+        magicBytes = 0xFFDC;
+        //TODO via 129076.
+        //Need to change value for length once FFDC design is final.
+        lenInWords  = ( sizeof(magicBytes) + sizeof(lenInWords)
+                            + sizeof(fapiRc) )/ sizeof(uint32_t);
+        fapiRc = 0;
+    }
+}sbeResponseFfdc_t;
+
+/**
+  * @brief structure for execute istep chipop (0xA101) contents.
+  *
+  */
+typedef struct
+{
+    uint8_t reserved1;
+    uint8_t major;
+    uint8_t reserved2;
+    uint8_t minor;
+}sbeIstepReqMsg_t;
+
+
+/**
+  * @brief Command response structure to hold the primary and secondary
+  *        status values. This will be utilized when a command class
+  *        validation or state machine check fails.
+  *
+  */
+typedef struct
+{
+    uint16_t          prim_status ;    // Primary Response Status
+    uint16_t          sec_status  ;    // Secondary Response Status
+} sbeCmdRespHdr_t;
+
+extern sbeCmdRespHdr_t g_sbeCmdRespHdr;
+
+typedef struct
+{
+    uint16_t magic_bytes;
+    uint16_t len;
+} sbeCmdResp_FFDC_t;
+
+
+/*****************************************************************/
+/** Upstream FIFO access utilities **/
+/*****************************************************************/
+
+/**
+  * @brief sbeUpFifoDeq : Read entry and status from Upstream FIFO
+  *
+  * @param[out] 64-Bit Data read from Upstream FIFO
+  *
+  * @return     Rc from the underlying scom utility
+  *
+  */
+extern inline uint32_t sbeUpFifoDeq (uint64_t *o_data)
+{
+    /* For SBE FIFO (PIB) access, chiplet ID should be passed as 0 */
+    return getscom(0, SBE_UPSTREAM_FIFO_DEQ_ADD, o_data);
+}
+
+
+/**
+  * @brief sbeUpFifoPerformReset : Perform Upstream FIFO reset request
+  *
+  * @return     Rc from the underlying scom utility
+  *
+  */
+extern inline uint32_t sbeUpFifoPerformReset (void)
+{
+    SBE_TRACE(">sbeUpFifoPerformReset");
+    return putscom(0, SBE_UPSTREAM_FIFO_PERFORM_RESET, ((uint64_t)0x1)<<32);
+}
+
+
+/**
+  * @brief sbeUpFifoAckEot : Acknowledge EOT in Upstream FIFO
+  *
+  * @return     Rc from the underlying scom utility
+  *
+  */
+extern inline uint32_t sbeUpFifoAckEot (void)
+{
+    SBE_DEBUG("sbeUpFifoAckEot");
+
+    return putscom(0, SBE_UPSTREAM_FIFO_ACK_EOT, ((uint64_t)0x1)<<32);
+}
+
+
+/*****************************************************************/
+/** Downstream FIFO access utilities **/
+/*****************************************************************/
+
+/**
+  * @brief sbeDownFifoEnq : Write data into Downstream FIFO
+  *
+  * @param[in] 64-Bit Data write into Downstream FIFO
+  *            Bit 0-31  : Data
+  *            Bit 32-63 : Unused
+  *
+  * @return    Rc from the underlying scom utility
+  */
+extern inline uint32_t sbeDownFifoEnq (const uint64_t i_data)
+{
+    SBE_DEBUG(">sbeDownFifoEnq");
+    return putscom(0, SBE_DOWNSTREAM_FIFO_ENQ_ADD, i_data);
+}
+
+
+/**
+  * @brief sbeDownFifoGetStatus : Read status from downstream FIFO
+  *
+  * @param[out] 64-Bit Read status from downstream FIFO
+  *            Bit 0-31  : Data
+  *            Bit 32-63 : Unused
+  *
+  * @return    Rc from the underlying scom utility
+  */
+extern inline uint32_t sbeDownFifoGetStatus (uint64_t *o_data)
+{
+    SBE_DEBUG(">sbeDownFifoStatus");
+    return getscom(0, SBE_DOWNSTREAM_FIFO_STATUS, o_data);
+}
+
+/**
+  * @brief sbeDownFifoSignalEot : Signal EOT in Downstream FIFO
+  *
+  * @return     Rc from the underlying scom utility
+  *
+  */
+extern inline uint32_t sbeDownFifoSignalEot (void)
+{
+    SBE_DEBUG(">sbeDownFifoSignalEot");
+    return putscom(0, SBE_DOWNSTREAM_FIFO_SIGNAL_EOT, ((uint64_t)0x1)<<32);
+}
+
+
+/**********************************************************************/
+// Utilities
+/**********************************************************************/
+
+/**
+  * @brief sbeUpFifoDeq_mult : Dequeue multiple entries from upstream FIFO
+  *
+  * @param[in/out] io_len
+  *                    number of entries to dequeue as input,
+  *                    number of entries dequeued as output without
+  *                    taking EOT dummy entry into consideration
+  * @param[out]    o_pData  entries dequeued into the buffer
+  * @param[in]     i_flush true / false
+  *                    true - caller requested FIFO flush,
+  *                       io_len would be returned as 0
+  *                    false - default case,
+  *                       io_len would be number of entries dequeued
+  *
+  * @return        Rc from the underlying scom utility
+  *
+  */
+extern uint32_t sbeUpFifoDeq_mult (uint8_t     &io_len,
+                                   uint32_t    *o_pData,
+                                   const bool  i_flush = false);
+
+
+/**
+  * @brief sbeDownFifoEnq_mult : Enqueue into downstream FIFO
+  *
+  * @param[in/out] io_len   number of entries to enqueue as input,
+  *                         number of entries enqueued as output
+  * @param[in]     i_pData  buffer containting data to be enqueued
+  *
+  * @return        Rc from the underlying scom utility
+  *
+  */
+extern uint32_t sbeDownFifoEnq_mult (uint8_t        &io_len,
+                                     const uint32_t *i_pData) ;
+
+
+/**
+  * @brief sbeBuildRespHeaderMagicCodeCmdClass
+  *          Builds the header word containing the magic code,
+  *          the command class and the opcode
+  *
+  * @return     Returns the header word in the response header
+  *             containing  the magic code, command class and opcode
+  *
+  */
+extern inline uint32_t sbeBuildRespHeaderMagicCodeCmdClass (void)
+{
+    return ( (0xC0DE0000 ) |
+             (uint32_t)(g_sbeCmdHdr.cmdClass << 8) |
+             (uint32_t)(g_sbeCmdHdr.command ));
+}
+
+/**
+  * @brief sbeBuildRespHeaderStatusWordGlobal
+  *          Builds the status header word from global variables
+  *
+  * @return     Returns the status word in the response header
+  *
+  */
+extern inline uint32_t sbeBuildRespHeaderStatusWordGlobal (void)
+{
+    return ( (((uint32_t)g_sbeCmdRespHdr.prim_status)<<16) |
+                        (g_sbeCmdRespHdr.sec_status) );
+}
+
+/**
+  * @brief sbeBuildRespHeaderStatusWordLocal
+  *          Builds the status header word from passed in parameters
+  *
+  * @param[in]  const uint16_t i_primStatus Primary Response Status Code
+  * @param[in]  const uint16_t i_secStatus  Secondary Response Status Code
+  *
+  * @return     Returns the status word in the response header
+  *
+  */
+extern inline uint32_t sbeBuildRespHeaderStatusWordLocal (
+                                const uint16_t i_primStatus,
+                                const uint16_t i_secStatus)
+{
+    return ( (((uint32_t)i_primStatus)<<16) | (i_secStatus) );
+}
+
+/**
+ * @brief sbeBuildMinRespHdr : Builds minimum response header
+ *
+ * @desc  This builds the buffer with the following status words
+ *           - Magic Bytes, Command Class, Command opcode
+ *           - Primary Status Code, Secondary Status Code
+ *           - PCB / PIB Status Code [optional]
+ *           - Distance to Status Header
+ * @param[in/out]    uint32_t *io_pBuf      Buffer to be filled in
+ * @param[in/out]    uint8_t  &io_curIndex  Current Index into the buffer
+ * @param[in]  const uint16_t  i_primStatus Primary Response Status Code
+ * @param[in]  const uint16_t  i_secStatus  Secondary Response Status Code
+ * @param[in]  const uint32_t  i_pcbpibStatus PCB-PIB Response Status Code
+ * @param[in]  const uint8_t   i_startIndex   Starting Index into the buffer
+ */
+
+void sbeBuildMinRespHdr ( uint32_t *io_pBuf,
+                          uint8_t  &io_curIndex,
+                    const uint16_t  i_primStatus,
+                    const uint16_t  i_secStatus,
+                    const uint32_t  i_pcbpibStatus,
+                    const uint8_t   i_startIndex = 0 );
+
+
+#endif // __SBEFW_SBEFIFO_H
diff --git a/src/ppe/sbe/sbefw/sbefwfiles.mk b/src/ppe/sbe/sbefw/sbefwfiles.mk
new file mode 100644
index 0000000..d7454c3
--- /dev/null
+++ b/src/ppe/sbe/sbefw/sbefwfiles.mk
@@ -0,0 +1,37 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ppe/sbe/sbefw/sbefwfiles.mk $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+SBEFW-CPP-SOURCES = sbemain.C
+SBEFW-CPP-SOURCES += sbeirq.C
+SBEFW-CPP-SOURCES += sbecmdreceiver.C
+SBEFW-CPP-SOURCES += sbecmdprocessor.C
+SBEFW-CPP-SOURCES += sbecmdparser.C
+SBEFW-CPP-SOURCES += sbecmdscomaccess.C
+SBEFW-CPP-SOURCES += sbecmdiplcontrol.C
+SBEFW-CPP-SOURCES += sbefifo.C
+SBEFW-CPP-SOURCES += pool.C
+SBEFW-C-SOURCES =
+SBEFW-S-SOURCES = 
+
+SBEFW_OBJECTS = $(SBEFW-C-SOURCES:.c=.o) $(SBEFW-CPP-SOURCES:.C=.o) $(SBEFW-S-SOURCES:.S=.o)
diff --git a/src/ppe/sbe/sbefw/sbeirq.C b/src/ppe/sbe/sbefw/sbeirq.C
new file mode 100644
index 0000000..c421d13
--- /dev/null
+++ b/src/ppe/sbe/sbefw/sbeirq.C
@@ -0,0 +1,128 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/sbefw/sbeirq.C $                                  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/*
+ * @file: ppe/sbe/sbefw/sbeirq.C
+ *
+ * @brief This sets up and registers SBE ISRs
+ *
+ */
+
+#include "sbeexeintf.H"
+#include "sbeirq.H"
+#include "sbetrace.H"
+
+
+////////////////////////////////////////////////////////////////
+// @brief:     SBE control loop ISR:
+//               - FIFO new data available
+//               - FIFO reset request
+//
+// @param[in]  i_pArg - Unused
+// @param[in]  i_irq  - IRQ number as defined in sbeirq.h
+//
+////////////////////////////////////////////////////////////////
+void sbe_fifo_interrupt_handler (void *i_pArg, PkIrqId i_irq)
+{
+    #define SBE_FUNC " sbe_fifo_interrupt_handler "
+    SBE_ENTER(SBE_FUNC"i_irq=[0x%02X]",i_irq);
+
+    int l_rc = 0;
+    switch (i_irq)
+    {
+        case SBE_IRQ_SBEFIFO_DATA:
+        case SBE_IRQ_SBEFIFO_RESET:
+            // Mask the interrupt
+            pk_irq_disable(i_irq);
+
+            // Unblock the command receiver thread
+            l_rc = pk_semaphore_post(&g_sbeSemCmdRecv);
+            if (l_rc)
+            {
+                // If we received an error while posting the semaphore,
+                // unmask the interrupt back and assert
+                // @TODO via RTC : 129166
+                //       Add support for ASSERT here
+                SBE_ERROR(SBE_FUNC"pk_semaphore_post failed, rc=[%d]", l_rc);
+                pk_irq_enable(i_irq);
+            }
+            break;
+
+        default:
+            SBE_ERROR(SBE_FUNC"Unknown IRQ, assert");
+            // @TODO via RTC : 129166
+            //       Add support for ASSERT here
+            break;
+    }
+    #undef SBE_FUNC
+}
+
+////////////////////////////////////////////////////////////////
+// See sbeexeintf.h for more details
+////////////////////////////////////////////////////////////////
+int sbeIRQSetup (void)
+{
+    #define SBE_FUNC " sbeIRQSetup "
+    int l_rc = 0;
+
+    // Disable the relevant IRQs while we set them up
+    pk_irq_disable(SBE_IRQ_SBEFIFO_DATA);
+    pk_irq_disable(SBE_IRQ_SBEFIFO_RESET);
+
+    do
+    {
+        // Register the IRQ handler with PK
+
+        // FIFO New data available interrupt
+        l_rc = pk_irq_handler_set(SBE_IRQ_SBEFIFO_DATA,
+                              sbe_fifo_interrupt_handler,
+                              NULL);
+
+        if(l_rc)
+        {
+            SBE_ERROR (SBE_FUNC"pk_irq_handler_set failed, IRQ=[0x%02X], "
+                   "rc=[%d]", SBE_IRQ_SBEFIFO_DATA, l_rc);
+            break;
+        }
+
+        // FIFO Reset request
+        l_rc = pk_irq_handler_set(SBE_IRQ_SBEFIFO_RESET,
+                              sbe_fifo_interrupt_handler,
+                              NULL);
+
+        if(l_rc)
+        {
+            SBE_ERROR (SBE_FUNC"pk_irq_handler_set failed, IRQ=[0x%02X], "
+                  "rc=[%d]", SBE_IRQ_SBEFIFO_RESET, l_rc);
+            break;
+        }
+
+        // Enable the IRQ
+        pk_irq_enable(SBE_IRQ_SBEFIFO_RESET);
+        pk_irq_enable(SBE_IRQ_SBEFIFO_DATA);
+    } while(false);
+
+    return l_rc;
+    #undef SBE_FUNC
+}
diff --git a/src/ppe/sbe/sbefw/sbeirq.H b/src/ppe/sbe/sbefw/sbeirq.H
new file mode 100644
index 0000000..61477f4
--- /dev/null
+++ b/src/ppe/sbe/sbefw/sbeirq.H
@@ -0,0 +1,108 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/sbefw/sbeirq.H $                                  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/*
+ * $file: ppe/sbe/sbefw/sbeirq.H
+ *
+ * @brief This file contains the SBE PPE Interrupt Request numbers
+ */
+
+#ifndef _SBE_IRQ_H
+#define _SBE_IRQ_H
+
+/**
+ * @brief SBE PPE IRQ numbers
+ *
+ */
+
+#define SBE_IRQ_START0   0       /* SBE Start Vector 0 */
+#define SBE_IRQ_START1   1       /* SBE Start Vector 1 */
+#define SBE_IRQ_INTR0    2       /* SBE Interrupt S0 */
+#define SBE_IRQ_INTR1    3       /* SBE Interrupt S1 */
+#define SBE_IRQ_DRTM_REQ 4       /* DRTM late launch request */
+#define SBE_IRQ_SBEFIFO_RESET 5  /* FIFO - Reset request from SE */
+#define SBE_IRQ_SBEFIFO_DATA  6  /* FIFO - Incoming Data Available */
+
+#define SBE_IRQ_RESERVED_7  7
+#define SBE_IRQ_RESERVED_8  8
+#define SBE_IRQ_RESERVED_9  9
+
+#define SBE_IRQ_RESERVED_10 10
+#define SBE_IRQ_RESERVED_11 11
+#define SBE_IRQ_RESERVED_12 12
+#define SBE_IRQ_RESERVED_13 13
+#define SBE_IRQ_RESERVED_14 14
+#define SBE_IRQ_RESERVED_15 15
+#define SBE_IRQ_RESERVED_16 16
+#define SBE_IRQ_RESERVED_17 17
+#define SBE_IRQ_RESERVED_18 18
+#define SBE_IRQ_RESERVED_19 19
+#define SBE_IRQ_RESERVED_20 20
+#define SBE_IRQ_RESERVED_21 21
+#define SBE_IRQ_RESERVED_22 22
+#define SBE_IRQ_RESERVED_23 23
+#define SBE_IRQ_RESERVED_24 24
+#define SBE_IRQ_RESERVED_25 25
+#define SBE_IRQ_RESERVED_26 26
+#define SBE_IRQ_RESERVED_27 27
+#define SBE_IRQ_RESERVED_28 28
+#define SBE_IRQ_RESERVED_29 29
+#define SBE_IRQ_RESERVED_30 30
+#define SBE_IRQ_RESERVED_31 31
+#define SBE_IRQ_RESERVED_32 32
+#define SBE_IRQ_RESERVED_33 33
+#define SBE_IRQ_RESERVED_34 34
+#define SBE_IRQ_RESERVED_35 35
+#define SBE_IRQ_RESERVED_36 36
+#define SBE_IRQ_RESERVED_37 37
+#define SBE_IRQ_RESERVED_38 38
+#define SBE_IRQ_RESERVED_39 39
+#define SBE_IRQ_RESERVED_40 40
+#define SBE_IRQ_RESERVED_41 41
+#define SBE_IRQ_RESERVED_42 42
+#define SBE_IRQ_RESERVED_43 43
+#define SBE_IRQ_RESERVED_44 44
+#define SBE_IRQ_RESERVED_45 45
+#define SBE_IRQ_RESERVED_46 46
+#define SBE_IRQ_RESERVED_47 47
+#define SBE_IRQ_RESERVED_48 48
+#define SBE_IRQ_RESERVED_49 49
+#define SBE_IRQ_RESERVED_50 50
+#define SBE_IRQ_RESERVED_51 51
+#define SBE_IRQ_RESERVED_52 52
+#define SBE_IRQ_RESERVED_53 53
+#define SBE_IRQ_RESERVED_54 54
+#define SBE_IRQ_RESERVED_55 55
+#define SBE_IRQ_RESERVED_56 56
+#define SBE_IRQ_RESERVED_57 57
+#define SBE_IRQ_RESERVED_58 58
+#define SBE_IRQ_RESERVED_59 59
+#define SBE_IRQ_RESERVED_60 60
+#define SBE_IRQ_RESERVED_61 61
+#define SBE_IRQ_RESERVED_62 62
+#define SBE_IRQ_RESERVED_63 63
+
+
+
+#endif  //_SBE_IRQ_H
diff --git a/src/ppe/sbe/sbefw/sbemain.C b/src/ppe/sbe/sbefw/sbemain.C
new file mode 100644
index 0000000..04e1f9b
--- /dev/null
+++ b/src/ppe/sbe/sbefw/sbemain.C
@@ -0,0 +1,289 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/sbefw/sbemain.C $                                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+/* @file: ppe/sbe/sbefw/sbemain.C
+ *
+ * @brief This file does the following
+ *        - SBE Application Main entry point
+ *        - PK initialization
+ *        - Thread initialization
+ *        - Semaphore initialization
+ *        - IRQ setup
+ *        - Scheduling of the threads and
+ *        - Starting of the control loop code flow
+ *
+ */
+
+
+#include "sbeexeintf.H"
+#include "sbetrace.H"
+
+
+////////////////////////////////////////////////////////////////
+// @brief Global semaphores
+////////////////////////////////////////////////////////////////
+PkSemaphore g_sbeSemCmdRecv;
+PkSemaphore g_sbeSemCmdProcess;
+PkSemaphore g_sbeSemFifoReset;
+
+////////////////////////////////////////////////////////////////
+// @brief Stacks for Non-critical Interrupts and Threads
+////////////////////////////////////////////////////////////////
+uint8_t g_sbe_Kernel_NCInt_stack[SBE_NONCRITICAL_STACK_SIZE];
+uint8_t g_sbeCommandReceiver_stack[SBE_THREAD_CMD_RECV_STACK_SIZE];
+uint8_t g_sbeSyncCommandProcessor_stack[SBE_THREAD_SYNC_CMD_PROC_STACK_SIZE];
+uint8_t g_sbeAsyncCommandProcessor_stack[SBE_THREAD_ASYNC_CMD_PROC_STACK_SIZE];
+
+////////////////////////////////////////////////////////////////
+// @brief PkThread structure for SBE Command Receiver thread
+////////////////////////////////////////////////////////////////
+PkThread g_sbeCommandReceiver_thread;
+
+////////////////////////////////////////////////////////////////
+// @brief PkThread structure for SBE Synchronous ChipOps
+//        processing thread
+////////////////////////////////////////////////////////////////
+PkThread g_sbeSyncCommandProcessor_thread;
+
+////////////////////////////////////////////////////////////////
+//// @brief PkThread structure for SBE Asynchronous ChipOps
+////        processing thread
+////////////////////////////////////////////////////////////////
+PkThread g_sbeAsyncCommandProcessor_thread;
+
+
+////////////////////////////////////////////////////////////////
+// @brief  sbeInitSems - Create the necessary semaphores
+//
+// @return  PK_OK                          - Success
+//         PK_INVALID_SEMAPHORE_AT_CREATE - Invalid PkSemaphore
+//         PK_INVALID_ARGUMENT_SEMAPHORE  - max_count is non-zero
+//                               and less than the initial_count
+////////////////////////////////////////////////////////////////
+uint32_t sbeInitSems(void)
+{
+    SBE_ENTER("sbeInitSems");
+    int l_rc = PK_OK;
+
+    do
+    {
+        l_rc = pk_semaphore_create(&g_sbeSemCmdRecv, 0, 1);
+        if (l_rc)
+        {
+            break;
+        }
+        l_rc = pk_semaphore_create(&g_sbeSemCmdProcess, 0, 1);
+        if (l_rc)
+        {
+            break;
+        }
+        l_rc = pk_semaphore_create(&g_sbeSemFifoReset, 0, 1);
+        if (l_rc)
+        {
+            break;
+        }
+    } while (false);
+
+    if (l_rc)
+    {
+        SBE_ERROR ("pk_semaphore_create, rc=[%d]", l_rc);
+    }
+    return l_rc;
+}
+
+////////////////////////////////////////////////////////////////
+// @brief  createAndResumeThreadHelper
+//            - Create and resume the given thread
+//
+// @param[in/out] io_thread  A pointer to an PkThread structure to initialize
+// @param[in]     i_thread_routine The subroutine that implements the thread
+// @param[in/out] io_arg     Private data to be passed as the argument to the
+//                              thread routine when it begins execution
+// @param[in]     i_stack    The stack space of the thread
+// @param[in]     i_stack_size The size of the stack in bytes
+// @param[in]     i_priority The initial priority of the thread
+//
+// @return        PK_OK Successfully created and resumed the thread
+//
+// @return        PK_INVALID_THREAD_AT_CREATE io_thread is null
+// @return        PK_INVALID_ARGUMENT_THREAD1 i_thread_routine is null
+// @return        PK_INVALID_ARGUMENT_THREAD2 i_priority is invalid
+// @return        PK_INVALID_ARGUMENT_THREAD3 the stack area wraps around
+//                                      the end of memory.
+// @return        PK_STACK_OVERFLOW           The stack area at thread creation
+//                                      is smaller than the min safe size
+// @return        PK_INVALID_THREAD_AT_RESUME1 io_thread is null (unlikely)
+// @return        PK_INVALID_THREAD_AT_RESUME2 The thread is not active,
+//                                      i.e. has completed or been deleted,
+// @return        PK_PRIORITY_IN_USE_AT_RESUME Another thread is already
+//                                      mapped at the priority of the thread
+////////////////////////////////////////////////////////////////
+uint32_t createAndResumeThreadHelper(PkThread    *io_pThread,
+                                PkThreadRoutine   i_thread_routine,
+                                void             *io_pArg,
+                                PkAddress         i_stack,
+                                size_t            i_stack_size,
+                                sbeThreadPriorities  i_priority)
+{
+    int l_rc = PK_OK;
+
+    // Thread creation
+    l_rc =  pk_thread_create(io_pThread,
+                             i_thread_routine,
+                             io_pArg,
+                             i_stack,
+                             i_stack_size,
+                             (PkThreadPriority)i_priority);
+    if(l_rc == PK_OK)
+    {
+        // resume the thread once created
+        l_rc = pk_thread_resume(io_pThread);
+    }
+
+    // Check for errors creating or resuming the thread
+    if(l_rc != PK_OK)
+    {
+        SBE_ERROR ("Failure creating/resuming thread, rc=[%d]", l_rc);
+    }
+
+    return l_rc;
+}
+
+////////////////////////////////////////////////////////////////
+// @brief   sbeInitThreads
+//          Create the resume all the firmware threads
+//
+// @return  See createAndResumeThreadHelper for more details
+////////////////////////////////////////////////////////////////
+int sbeInitThreads(void)
+{
+    // Locals
+    uint32_t l_rc         = PK_OK;
+
+    do
+    {
+        // Initialize Command receiver thread
+        l_rc = createAndResumeThreadHelper(&g_sbeCommandReceiver_thread,
+                            sbeCommandReceiver_routine,
+                            (void *)0,
+                            (PkAddress)g_sbeCommandReceiver_stack,
+                            SBE_THREAD_CMD_RECV_STACK_SIZE,
+                            THREAD_PRIORITY_5);
+        if (l_rc)
+        {
+            break;
+        }
+
+        // Initialize Synchronous Command Processor thread
+        l_rc = createAndResumeThreadHelper(&g_sbeSyncCommandProcessor_thread,
+                            sbeSyncCommandProcessor_routine,
+                            (void *)0,
+                            (PkAddress)g_sbeSyncCommandProcessor_stack,
+                            SBE_THREAD_SYNC_CMD_PROC_STACK_SIZE,
+                            THREAD_PRIORITY_7);
+        if (l_rc)
+        {
+            break;
+        }
+
+        // Initialize Asynchronous Command Processor thread
+        l_rc = createAndResumeThreadHelper(&g_sbeAsyncCommandProcessor_thread,
+                            sbeAsyncCommandProcessor_routine,
+                            (void *)0,
+                            (PkAddress)g_sbeAsyncCommandProcessor_stack,
+                            SBE_THREAD_ASYNC_CMD_PROC_STACK_SIZE,
+                            THREAD_PRIORITY_6);
+        if (l_rc)
+        {
+            break;
+        }
+    } while (false);
+
+    // If there are any errors initializing the threads
+    if( l_rc )
+    {
+        SBE_ERROR ("Error Initializing a thread, rc=[%d]", l_rc);
+    }
+
+    return l_rc;
+}
+
+////////////////////////////////////////////////////////////////
+// @brief - main : SBE Application main
+////////////////////////////////////////////////////////////////
+uint32_t main(int argc, char **argv)
+{
+    SBE_TRACE("Enter SBE main");
+    int l_rc = 0;
+
+    // @TODO via RTC : 128818
+    //       Explore on reclaiming the stack
+    //       used by this Initialization code
+
+    do
+    {
+        // initializes kernel data -
+        // stack, threads, timebase, timers, etc.
+        l_rc = pk_initialize((PkAddress)g_sbe_Kernel_NCInt_stack,
+             SBE_NONCRITICAL_STACK_SIZE,
+             0,
+             500000000); // @TODO via RTC : 128819
+                         //       Need to obtain at Runtime, a new attribute?
+        if (l_rc)
+        {
+            break;
+        }
+
+        SBE_DEBUG("Completed PK init");
+
+        // Initialize the semaphores
+        l_rc = sbeInitSems();
+        if (l_rc)
+        {
+            break;
+        }
+
+        // Initialize SBE control loop threads
+        l_rc = sbeInitThreads();
+        if (l_rc)
+        {
+            break;
+        }
+
+        // Setup SBE PPE IRQs
+        l_rc = sbeIRQSetup();
+        if (l_rc)
+        {
+            break;
+        }
+
+        // Start running the highest priority thread.
+        // This function never returns
+        pk_start_threads();
+
+    } while (false);
+
+    return l_rc;
+}
diff --git a/src/ppe/sbe/sbefw/sbetrace.H b/src/ppe/sbe/sbefw/sbetrace.H
new file mode 100644
index 0000000..b5b9c6c
--- /dev/null
+++ b/src/ppe/sbe/sbefw/sbetrace.H
@@ -0,0 +1,59 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/sbefw/sbetrace.H $                                */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __SBEFW_SBE_TRACE_H
+#define __SBEFW_SBE_TRACE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "pk_api.h"
+#include "trac_interface.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#define  SBE_ENTER_MRK ">>"
+#define  SBE_EXIT_MRK "<<"
+#define  SBE_ERR_MRK "E>"
+#define  SBE_INF_MRK "I>"
+
+#define SBE_TRACE(args...) PK_TRACE(args)
+#define SBE_ENTER(args...) PK_TRACE(SBE_ENTER_MRK"" args)
+#define SBE_EXIT(args...) PK_TRACE(SBE_EXIT_MRK"" args)
+#define SBE_ERROR(args...) PK_TRACE(SBE_ERR_MRK"" args)
+#define SBE_INFO(args...) PK_TRACE(SBE_INF_MRK"" args)
+
+//Debug traces
+#define  SBE_FW_DEBUG
+#ifdef SBE_FW_DEBUG
+#define  SBE_DEBUG_MRK "D>"
+#define SBE_DEBUG(args...) PK_TRACE(SBE_DEBUG_MRK"" args)
+#else
+#define SBE_DEBUG(args...)
+#endif  //SBE_FW_DEBUG
+
+#endif // __SBEFW_SBE_TRACE_H
diff --git a/src/ppe/sbe/sbefw/vector b/src/ppe/sbe/sbefw/vector
new file mode 100644
index 0000000..bcd13a5
--- /dev/null
+++ b/src/ppe/sbe/sbefw/vector
@@ -0,0 +1,399 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/sbe/sbefw/vector $                                    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+#ifndef stl_vector
+#define stl_vector
+
+/**
+ * @file vector
+ * @brief simple stl vector template class declaration.
+ */
+
+#include <stddef.h>
+
+#if !defined( __STDC_LIMIT_MACROS)
+#define __STDC_LIMIT_MACROS
+#endif
+#include <stdint.h>
+#include <pool.H>
+//TODO via RTC 129166
+// Add implementation for assert
+#define assert(X)
+namespace std
+{
+
+    /**
+     * @class vector
+     * subset of stl vector
+     * @note Does not support allocators, reverse iterators.
+     */
+    template <class T>
+        class vector
+        {
+            public:
+
+                typedef T * iterator;
+                typedef const T * const_iterator;
+                typedef T & reference;
+                typedef const T & const_reference;
+                typedef size_t size_type;
+                typedef T value_type;
+                typedef T * pointer;
+                typedef const T * const_pointer;
+
+            protected:
+
+                pointer iv_start;
+                pointer iv_finish;
+                SBEVECTORPOOL::vectorMemPool_t *iv_poolPtr;
+            public:
+
+                /**
+                 * Constructor default
+                 * @post     The vector is created with storage of
+                 *           G_BLOCKSIZE bytes.
+                 */
+                explicit vector(void)
+                {
+                    iv_poolPtr = SBEVECTORPOOL::allocMem();
+                    assert ( NULL != iv_poolPtr)
+                    iv_start = ( T* )iv_poolPtr->data;
+                    iv_finish = iv_start;
+                }
+
+
+                /**
+                 * MOVE COPY CTOR create a vector from another vector
+                 * @param[in] x  source vector
+                 * @post     Vector of x.size() is created from x with same
+                 *           memory.
+                 *           size() == capacity() == x.size()
+                 * @note     move Copy construtor willuse shallow copy. So input
+                 *           as well as output vector will point to same data
+                 */
+                vector(const vector<T>&& x)
+                {
+                        iv_start = x.iv_start;
+                        iv_finish = x.iv_finish;
+                        iv_poolPtr = x.iv_poolPtr;
+                        iv_poolPtr->refCount++;
+                }
+
+                /**
+                 * Reserve space for atleast n elements
+                 * @param[in] n Number of elements
+                 * @note    We are having fixed size vectors in ppe. Defining
+                 *          this function to avoid compile issues in standard
+                 *          library. This function is noop for less than 512
+                 *          bytes requirement. For more than 512 bytes, it will
+                 *          assert.
+                 */
+                void reserve(size_type n)
+                {
+                    assert(n < max_size());
+                    return;
+                 }
+                /**
+                 * DTOR
+                 * @post     Storage released
+                 */
+                __attribute__ ((always_inline))
+                ~vector()
+                {
+                    clear();  // call dtors
+                    SBEVECTORPOOL::releaseMem(iv_poolPtr);
+                }
+
+                /**
+                 * Move Assignment operator.
+                 * @param[in] x   A vector.
+                 * @return  A vector (for the purpose of multiple assigns).
+                 * @pre     None.
+                 * @post    *this == x, this->capacity() == x.size().
+                 *           All previously obtained iterators are invalid.
+                 */
+                vector<T>& operator=(const vector<T>&& x)
+                {
+                    // Just check here for pool to make sure
+                    // input vector and current vector are not same;
+                    if( iv_poolPtr != x.iv_poolPtr)
+                    {
+                        clear();
+                        SBEVECTORPOOL::releaseMem(iv_poolPtr);
+                        iv_start = x.iv_start;
+                        iv_finish = x.iv_finish;
+                        iv_poolPtr = x.iv_poolPtr;
+                        iv_poolPtr->refCount++;
+                     }
+                    return(*this);
+                }
+
+                // Iterators --------------------
+
+                /**
+                 * Get iterator to the first vector element
+                 * @return iterator of rist vector element
+                 * @pre None.
+                 * @post None.
+                 */
+                __attribute__ ((always_inline))
+                iterator begin()
+                {
+                    return (iv_start);
+                }
+
+                /**
+                 * Get const_iterator to the first vector element
+                 * @return const_iterator of rist vector element
+                 * @pre None.
+                 * @post None.
+                 */
+                __attribute__ ((always_inline))
+                const_iterator begin() const
+                {
+                    return (iv_start);
+                }
+
+                /**
+                 * Get iterator to the last vector element + 1
+                 * @return iterator
+                 * @pre None.
+                 * @post None.
+                 */
+                __attribute__ ((always_inline))
+                iterator end()
+                {
+                    return (iv_finish);
+                }
+
+                /**
+                 * Get const_iterator to the last vector element + 1
+                 * @return const_iterator
+                 * @pre None.
+                 * @post None.
+                 */
+                __attribute__ ((always_inline))
+                const_iterator end() const
+                {
+                    return (iv_finish);
+                }
+
+                //  Capacity -----------------------------------------------
+
+                /**
+                 * Get the number of elements in the container
+                 * @return number of elements in the container
+                 */
+                __attribute__ ((always_inline))
+                size_type size() const
+                {
+                    return(iv_finish - iv_start);
+                }
+
+                /**
+                 * Return the maximum potential size the container could reach.
+                 * @return number of the maximum element count this container
+                 *         could reach
+                 */
+                __attribute__ ((always_inline))
+                size_type max_size() const
+                {
+                    return SBEVECTORPOOL::G_BLOCKSIZE/(sizeof(T));
+                }
+
+                /**
+                 * Query for empty container
+                 * @return bool, true if size()==0 else false.
+                 * @pre none
+                 * @post none
+                 */
+                __attribute__ ((always_inline))
+                bool empty() const
+                {
+                    return(size() == 0);
+                }
+
+                // - Element Access -----------------------------------
+
+                /**
+                 * Access a mutable reference to an element in the container
+                 * @param An index into the vector
+                 * @return A reference to an element
+                 * @pre    0 <= n < size()
+                 * @post   None.
+                 */
+                __attribute__ ((always_inline))
+                reference operator[](size_type n)
+                {
+                    assert(n < size());
+                    return(*(iv_start + n));
+                }
+
+                /**
+                 * Access a mutable reference to an element in the container
+                 * @param[in] index An index into the vector
+                 * @return A reference to an element
+                 * @pre    0 <= n < size()
+                 * @post   None.
+                 * @note no exception handling
+                 */
+                __attribute__ ((always_inline))
+                reference at(size_type index)
+                {
+                    assert(index < size());
+                    return(*(iv_start + index));
+                }
+
+                /**
+                 * Get an immutable reference to an element in the container
+                 * @param[in] index An index into the vector
+                 * @return A const_reference to an object or type T
+                 * @pre    0 <= n < size()
+                 * @post   None.
+                 */
+                __attribute__ ((always_inline))
+                const_reference operator[](size_type index) const
+                {
+                    assert(index < size());
+                    return(*(iv_start + index));
+                }
+
+                /**
+                 * Get an immutable reference to an element in the container
+                 * @param[in] index An index into the vector
+                 * @return A const_reference to an object or type T
+                 * @pre    0 <= n < size()
+                 * @post   None.
+                 * @note no exception handling
+                 */
+                __attribute__ ((always_inline))
+                const_reference at(size_type index) const
+                {
+                    assert(index < size());
+                    return(*(iv_start + index));
+                }
+
+                /**
+                 * Get a mutable reference to the first element in the container
+                 * @return reference to first element
+                 * @pre none
+                 * @post None
+                 */
+                __attribute__ ((always_inline))
+                reference front()
+                {
+                    return *iv_start;
+                }
+
+                /**
+                 * Get an Immutable reference to the first element in the
+                 * container
+                 * @return const_reference to first element
+                 * @pre none
+                 * @post None
+                 */
+                __attribute__ ((always_inline))
+                const_reference front() const
+                {
+                    return *iv_start;
+                }
+
+                /**
+                 * Get a mutable reference to the last element in the container
+                 * @return reference to last element
+                 * @pre none
+                 * @post None
+                 */
+                __attribute__ ((always_inline))
+                reference back()
+                {
+                    return *(iv_finish-1);
+                }
+
+                /**
+                 * Get an Immutable reference to the last element in the
+                 * container
+                 * @return reference to last element
+                 * @pre none
+                 * @post None
+                 */
+                __attribute__ ((always_inline))
+                const_reference back() const
+                {
+                    return *(iv_finish-1);
+                }
+
+                /**
+                 * Add element to the back of the container
+                 * @param[in] x reference to object used to create new element
+                 * @pre none
+                 * @post All previously obtained iterators are invalid.
+                 */
+                __attribute__ ((always_inline))
+                void push_back(const T& x)
+                {
+                    assert(max_size() > size())
+                    new (iv_finish++) T(x);
+                }
+
+                /**
+                 * Clear the vector
+                 * @pre none.
+                 * @post size() = 0, All previously obtained iterators are
+                 *       invalid
+                 * @note capacity unchanged
+                 */
+                void clear ()
+                {
+                    while(iv_finish != iv_start)
+                    {
+                        --iv_finish;
+                        (iv_finish)->~T();
+                    }
+                }
+
+                /*
+                 * Assign new content to the vector object
+                 * @param[in] n number of elements to assign
+                 * @param[in] x reference to element to copy in
+                 */
+                void assign ( size_type n, const T& x)
+                {
+                    assert(n < max_size());
+                    clear();
+                    for (  ; n> 0; n--)
+                        push_back( x);
+                }
+
+            private:
+                vector(const vector<T>& x);
+                vector<T>& operator=(const vector<T>& x);
+};
+
+}; // end namespace std
+
+
+#endif
+/* vim: set filetype=cpp : */
diff --git a/src/ppe/tools/image/Makefile b/src/ppe/tools/image/Makefile
new file mode 100644
index 0000000..e4d60da
--- /dev/null
+++ b/src/ppe/tools/image/Makefile
@@ -0,0 +1,148 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ppe/tools/image/Makefile $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+############################################################################
+
+# Makefile for image tools
+# works on X86 Linux hosts.
+
+# Make targets:
+
+# all          : 
+#
+# utilities    : Build utility programs and procedures
+#
+# clean        : Removes the bin/ directory and all symbolic links
+#
+
+############################################################################
+
+
+ifeq ($(CTEPATH),)
+$(warning CTEPATH not defined; defaulting to awd)
+CTEPATH = /afs/awd/projects/cte
+endif
+
+
+# Are we setup for eCMD, if so let's get our eCMD Release from there
+ifneq ($(strip $(ECMD_RELEASE)),)
+  ECMD_RELEASE := $(shell ecmdVersion full)
+  # Make sure we got a valid version back
+  ifeq ($(findstring ver,$(ECMD_RELEASE)),)
+    ECMD_RELEASE := rel
+  endif
+else
+  # If not setup for eCMD, default to rel
+  ECMD_RELEASE := rel
+endif
+
+
+# Ok, now set our eCMD Path, if not set already
+ifeq ($(strip $(ECMD_PATH)),)
+  ECMD_PATH   := ${CTEPATH}/tools/ecmd/${ECMD_RELEASE}/
+endif
+
+ifeq ($(strip $(ECMD_PLUGIN)),cro)
+# Cronus plugin specific setup
+  CRONUS_PATH := $(shell echo ${ECMD_EXE} | sed -n 's|\([a-zA-Z0-9]*\)\(_*\)\([a-zA-Z0-9]*\)_x86\.exe|prcd_d|p')
+  ifeq ($(strip $(CRONUS_PATH)),)
+    $(error "Error determining CRONUS_PATH from env!")
+  endif
+endif
+
+# We need common up-to-date headers for FAPI - currently using these.
+FAPI = $(ECMD_PATH)ext/fapi
+
+#  Locations of required headers.
+INCLUDES += -I. -I../../ -I../../utils 
+INCLUDES += -I ../../sbe/image/
+INCLUDES += -I ../../sbe/sbefw/
+INCLUDES += -I ../../sbe/plat/include
+INCLUDES += -I ../../hwpf/plat/include/
+INCLUDES += -I ../../pk/ppe42/
+INCLUDES += -I ../../pk/kernel/
+INCLUDES += -I ../../pk/std/
+INCLUDES += -I ../../pk/trace/
+INCLUDES += -I ../../tools/ppetracepp/
+INCLUDES += -I ../../importtemp/fapi2/include/
+
+INCLUDES +=	-I$(CRONUS_PATH)
+INCLUDES +=	-I$(ECMD_PATH)/capi 
+INCLUDES +=	-I$(FAPI)/capi
+
+# Under Linux the scheme is to use a common compiler to create procedures.
+# However, the common compiler can be VERY slow, so if the system compiler is
+# also 4.1.2 we're using that one instead.  Also, the Linux FAPI libraries we
+# link with are 32-bit only so we need to force 32-bit mode.
+
+ifeq ($(wildcard /etc/ldap.conf), )
+  GSACELL     = ausgsa
+else
+  GSACELL     = $(shell cat /etc/ldap.conf | grep "host " | \
+        cut -d" " -f2 | cut -d. -f1)
+endif
+
+GCC-RELEASE = 4.8.2
+GCC-VERSION = $(shell gcc -v 2>&1 | grep "$(GCC-RELEASE)")
+
+ifeq ($(GCC-VERSION),)
+$(error wrong compiler version. Use $(GCC-RELEASE) compiler. Try: "scl enable devtoolset-2 bash")
+else
+CC   = gcc
+CXX  = g++
+endif
+
+#UTILITIES-SOURCES += ../../sbe/image/sbe_xip_image.c 
+UTILITIES-SOURCES = sbe_xip_tool.c sbe_default_tool.c
+
+UTILITIES = sbe_xip_tool sbe_default_tool
+
+#  Utility targets
+UTILITIES-OBJc         = $(patsubst %.c,bin/%.o,$(UTILITIES-SOURCES))
+UTILITIES-OBJECTS      += $(patsubst %.C,bin/%.o,$(UTILITIES-OBJc))
+UTILITIES-DEPENDENCIES = $(patsubst %.o,%.d,$(UTILITIES-OBJECTS))
+UTILITIES-EXECUTABLES  = $(patsubst %,bin/%,$(UTILITIES))
+
+
+.PHONY : utilities
+utilities: $(UTILITIES-EXECUTABLES)
+
+bin/%.o: %.c
+	$(CXX) -std=c++11 $(INCLUDES) $(CXXFLAGS) -DDEBUG_SBE_XIP_IMAGE=1 -DFAPI2_NO_FFDC -c -o $@ $<
+
+bin/sbe_xip_image.o: ../../sbe/image/sbe_xip_image.c
+	$(CXX) -std=c++11 $(INCLUDES) $(CXXFLAGS) -DDEBUG_SBE_XIP_IMAGE=1 -DFAPI2_NO_FFDC -c -o $@ $<
+
+bin/sbe_xip_tool: bin/sbe_xip_image.o bin/p9_ring_identification.o bin/sbe_xip_tool.o
+	$(CXX) $(CXXFLAGS) ${INCLUDES} -o $@ $^
+	ln -sf bin/sbe_xip_tool sbe_xip_tool
+
+bin/sbe_default_tool: bin/sbe_xip_image.o bin/sbe_default_tool.o 
+	$(CXX) $(CXXFLAGS) ${INCLUDES} -o $@ $^
+	ln -sf bin/sbe_default_tool sbe_default_tool
+
+clean:
+	rm sbe_xip_tool sbe_default_tool
+	rm -rf bin
+	mkdir -p bin
\ No newline at end of file
diff --git a/src/ppe/tools/image/bin/.empty b/src/ppe/tools/image/bin/.empty
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/ppe/tools/image/bin/.empty
diff --git a/src/ppe/tools/image/p9_image_help_base.H b/src/ppe/tools/image/p9_image_help_base.H
new file mode 100644
index 0000000..f9b6369
--- /dev/null
+++ b/src/ppe/tools/image/p9_image_help_base.H
@@ -0,0 +1,119 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/tools/image/p9_image_help_base.H $                    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef _P9_IMAGE_HELP_BASE_H_
+#define _P9_IMAGE_HELP_BASE_H_
+
+#include <sbe_xip_image.h>
+
+//
+// Various image/ring buffer sizes. Must be used by all users (VBU, FSP, HB, HBI, Cronus)
+//
+const uint32_t  MAX_REF_IMAGE_SIZE      =   5000000; // Max reference image size.
+const uint32_t  FIXED_SEEPROM_WORK_SPACE=  128*1024; // Max work space for Seeprom img.
+const uint32_t  MAX_SEEPROM_IMAGE_SIZE  =   56*1024; // Max Seeprom image size.
+const uint32_t  FIXED_RING_BUF_SIZE     =     60000; // Fixed ring buf size for _fixed.
+
+const uint8_t   MAX_VPD_TYPES           =   2;   // #G and #R, so far.
+#define         CHIPLET_ID_MIN            0x00 
+#define         CHIPLET_ID_MAX            0x1F 
+#define         CHIPLET_ID_EX_MIN         0x10 
+#define         CHIPLET_ID_EX_MAX         0x1F 
+const uint8_t   MAX_CHIPLETS            = CHIPLET_ID_MAX-CHIPLET_ID_MIN+1;
+const uint32_t  ASM_RS4_LAUNCH_BUF_SIZE =  24; // Byte size of RS4 launch buffer. 
+const uint32_t  WF_ENCAP_SIZE           = 400; // Byte size of WF encapsulation.
+                                               // (Actually, only 304B but may change.)
+const uint32_t  WF_WORST_CASE_SIZE_FAC  =   4; // WC WF size = 3x ring length.
+                                               // (Assumes 12B per write.)
+                                               // (4x w/waits instructions.)
+const uint32_t  LISTING_STRING_SIZE     = 256;
+const uint64_t  MAX_UINT64_T            = (uint64_t)0xFFFFFFFF<<32 | (uint64_t)0xFFFFFFFF;
+
+const uint8_t RING_SECTION_ID[] = {
+  SBE_XIP_SECTION_RINGS,
+  SBE_XIP_SECTION_OVERLAYS,
+};
+const uint8_t RING_SECTION_ID_SIZE = sizeof(RING_SECTION_ID) / sizeof(RING_SECTION_ID[0]);
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Base (shared) ring layout for both RS4 and Wiggle-flip layouts.
+typedef struct {
+  uint64_t entryOffset;
+  uint64_t backItemPtr;
+  uint32_t sizeOfThis;
+  uint32_t sizeOfMeta; // Exact size of meta data. Arbitrary size. Not null terminated.
+} BaseRingLayout;
+
+// RS4 specific layout.
+typedef struct {
+  uint64_t entryOffset;
+  uint64_t backItemPtr;
+  uint32_t sizeOfThis;
+  uint32_t sizeOfMeta; // Exact size of meta data. Arbitrary size. Not null terminated.
+  uint32_t ddLevel;
+  uint8_t  sysPhase;
+  uint8_t  override;
+  uint8_t  reserved1;
+  uint8_t  reserved2;
+} Rs4RingLayout;
+
+// PairingInfo is used for pairing, or matching, a back pointer address of a
+// ring block with its corresponding TOC name.
+typedef struct {
+    uint64_t address;     // (in) Holds HOMER backPtr addr of the ring
+    uint8_t  vectorpos;   // (in) Vector position of fwdPtr [0;31]
+                          //      max=0  for most VPD rings 
+                          //      max=1  for all non-VPD rings
+                          //      max=1  for perv_ VPD rings
+                          //      max=15 for most VPD ex_ rings
+                          //      max=31 for 16 ex_ chiplets with override
+    char     *name;       // (out) TOC name
+    uint8_t  isvpd;       // (out) 0: Non-VPD ring  1: VPD ring
+    uint8_t  overridable; // (out) 0: No (most VPD rings)  1: Yes (all non-VPD rings)
+    uint8_t  override;    // (out) 0: base  1: override
+} PairingInfo;
+
+
+///
+/// ****************************************************************************
+/// Function declares.
+/// ****************************************************************************
+///
+int over_write_ring_data_in_image(  void            *io_image,
+                                    const char      *i_ringName,
+                                    const void      *i_ringData,    // WF or RS4
+                                    const uint32_t  i_sizeRingData, // Byte size
+                                    const uint8_t   i_idxVector,
+                                    const uint8_t   i_override,
+                                    const uint8_t   i_overridable );
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //_P8_IMAGE_HELP_BASE_H_
diff --git a/src/ppe/tools/image/p9_ring_identification.H b/src/ppe/tools/image/p9_ring_identification.H
new file mode 100644
index 0000000..452fcf2
--- /dev/null
+++ b/src/ppe/tools/image/p9_ring_identification.H
@@ -0,0 +1,65 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/tools/image/p9_ring_identification.H $                */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef _P9_RING_IDENT_H_
+#define _P9_RING_IDENT_H_
+#include <stddef.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h> 
+
+
+// Ring ID list structure.
+typedef struct {
+  const char  *ringName;
+  uint8_t     ringId;
+  uint8_t     chipIdMin;    // the min chipletId
+  uint8_t     chipIdMax;    // the max chipletId
+  const char  *ringNameImg; // Ring name in image: ringName + "_ring"
+  uint8_t     vpdKeyword;
+  uint8_t      bWcSpace;     // 0: fitted  1: worst-case space (3 x ring length)
+} RingIdList;
+
+extern const RingIdList  RING_ID_LIST_PG[], RING_ID_LIST_PR[];
+extern const uint32_t    RING_ID_LIST_PG_SIZE, RING_ID_LIST_PR_SIZE;
+extern const RingIdList  RING_ID_LIST[];
+extern const uint32_t    RING_ID_LIST_SIZE;
+
+// Enumerated VPD keyword values.
+// Note! This is DIFFERENT from the MvpdKeyword list in fapiMvpdAccess.H which
+//       can't be used in this file since it's not, per se, a fapi file. So
+//       these values need to be translated in xip_customize when passing the
+//       mvpdKeyword to getMvpdRing();
+enum VpdKeyword  {
+  VPD_KEYWORD_PDG,
+  VPD_KEYWORD_PDR,
+  NUM_OF_VPD_TYPES
+};
+
+int get_vpd_ring_list_entry(const char *i_ringName,
+                            const uint8_t i_ringId,
+                            RingIdList **i_ringIdList);
+
+
+#endif
diff --git a/src/ppe/tools/image/p9_ring_identification.c b/src/ppe/tools/image/p9_ring_identification.c
new file mode 100644
index 0000000..126293b
--- /dev/null
+++ b/src/ppe/tools/image/p9_ring_identification.c
@@ -0,0 +1,146 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/tools/image/p9_ring_identification.c $                */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#include <p9_ring_identification.H>
+
+const RingIdList RING_ID_LIST_PG[] = {
+  /* ringName       ringId  chipletId    ringNameImg            mvpdKeyword    wc */
+  /*                        min   max                                               */
+  {"ab_gptr_ab",     0xA0, 0x08, 0x08, "ab_gptr_ab_ring",     VPD_KEYWORD_PDG, 0},
+  {"ab_gptr_ioa",    0xA1, 0x08, 0x08, "ab_gptr_ioa_ring",    VPD_KEYWORD_PDG, 0},
+  {"ab_gptr_perv",   0xA2, 0x08, 0x08, "ab_gptr_perv_ring",   VPD_KEYWORD_PDG, 0},
+  {"ab_gptr_pll",    0xA3, 0x08, 0x08, "ab_gptr_pll_ring",    VPD_KEYWORD_PDG, 0},
+  {"ab_time",        0xA4, 0x08, 0x08, "ab_time_ring",        VPD_KEYWORD_PDG, 0},
+  {"ex_gptr_core",   0xA5, 0xFF, 0xFF, "ex_gptr_core_ring",   VPD_KEYWORD_PDG, 0},   //Chip specific
+  {"ex_gptr_dpll",   0xA6, 0xFF, 0xFF, "ex_gptr_dpll_ring",   VPD_KEYWORD_PDG, 0},   //Chip specific
+  {"ex_gptr_l2",     0xA7, 0xFF, 0xFF, "ex_gptr_l2_ring",     VPD_KEYWORD_PDG, 0},     //Chip specific
+  {"ex_gptr_l3",     0xA8, 0xFF, 0xFF, "ex_gptr_l3_ring",     VPD_KEYWORD_PDG, 0},     //Chip specific
+  {"ex_gptr_l3refr", 0xA9, 0xFF, 0xFF, "ex_gptr_l3refr_ring", VPD_KEYWORD_PDG, 0}, //Chip specific
+  {"ex_gptr_perv",   0xAA, 0xFF, 0xFF, "ex_gptr_perv_ring",   VPD_KEYWORD_PDG, 0},   //Chip specific
+  {"ex_time_core",   0xAB, 0x10, 0x1F, "ex_time_core_ring",   VPD_KEYWORD_PDG, 0},   //Chiplet specfc
+  {"ex_time_eco",    0xAC, 0x10, 0x1F, "ex_time_eco_ring",    VPD_KEYWORD_PDG, 0},    //Chiplet specfc
+  {"pb_gptr_dmipll", 0xAD, 0x02, 0x02, "pb_gptr_dmipll_ring", VPD_KEYWORD_PDG, 0},
+  {"pb_gptr_mcr",    0xAE, 0x02, 0x02, "pb_gptr_mcr_ring",    VPD_KEYWORD_PDG, 0},
+  {"pb_gptr_nest",   0xAF, 0x02, 0x02, "pb_gptr_nest_ring",   VPD_KEYWORD_PDG, 0},
+  {"pb_gptr_nx",     0xB0, 0x02, 0x02, "pb_gptr_nx_ring",     VPD_KEYWORD_PDG, 0},
+  {"pb_gptr_pcis",   0xB1, 0x02, 0x02, "pb_gptr_pcis_ring",   VPD_KEYWORD_PDG, 0},
+  {"pb_gptr_perv",   0xB2, 0x02, 0x02, "pb_gptr_perv_ring",   VPD_KEYWORD_PDG, 0},
+  {"pb_time",        0xB3, 0x02, 0x02, "pb_time_ring",        VPD_KEYWORD_PDG, 0},
+  {"pb_time_mcr",    0xB4, 0x02, 0x02, "pb_time_mcr_ring",    VPD_KEYWORD_PDG, 0},
+  {"pb_time_nx",     0xB5, 0x02, 0x02, "pb_time_nx_ring",     VPD_KEYWORD_PDG, 0},
+  {"pci_gptr_iopci", 0xB6, 0x09, 0x09, "pci_gptr_iopci_ring", VPD_KEYWORD_PDG, 0},
+  {"pci_gptr_pbf",   0xB7, 0x09, 0x09, "pci_gptr_pbf_ring",   VPD_KEYWORD_PDG, 0},
+  {"pci_gptr_pci0",  0xB8, 0x09, 0x09, "pci_gptr_pci0_ring",  VPD_KEYWORD_PDG, 0},
+  {"pci_gptr_pci1",  0xB9, 0x09, 0x09, "pci_gptr_pci1_ring",  VPD_KEYWORD_PDG, 0},
+  {"pci_gptr_pci2",  0xBA, 0x09, 0x09, "pci_gptr_pci2_ring",  VPD_KEYWORD_PDG, 0},
+  {"pci_gptr_perv",  0xBB, 0x09, 0x09, "pci_gptr_perv_ring",  VPD_KEYWORD_PDG, 0},
+  {"pci_gptr_pll",   0xBC, 0x09, 0x09, "pci_gptr_pll_ring",   VPD_KEYWORD_PDG, 0},
+  {"pci_time",       0xBD, 0x09, 0x09, "pci_time_ring",       VPD_KEYWORD_PDG, 0},
+  {"perv_gptr_net",  0xBE, 0x00, 0x00, "perv_gptr_net_ring",  VPD_KEYWORD_PDG, 0},
+  {"perv_gptr_occ",  0xBF, 0x00, 0x00, "perv_gptr_occ_ring",  VPD_KEYWORD_PDG, 0},
+  {"perv_gptr_perv", 0xC0, 0x00, 0x00, "perv_gptr_perv_ring", VPD_KEYWORD_PDG, 0},
+  {"perv_gptr_pib",  0xC1, 0x00, 0x00, "perv_gptr_pib_ring",  VPD_KEYWORD_PDG, 0},
+  {"perv_gptr_pll",  0xC2, 0x00, 0x00, "perv_gptr_pll_ring",  VPD_KEYWORD_PDG, 0},
+  {"perv_time",      0xC3, 0x00, 0x00, "perv_time_ring",      VPD_KEYWORD_PDG, 0},
+  {"xb_gptr_iopci",  0xC4, 0x04, 0x04, "xb_gptr_iopci_ring",  VPD_KEYWORD_PDG, 0},
+  {"xb_gptr_iox",    0xC5, 0x04, 0x04, "xb_gptr_iox_ring",    VPD_KEYWORD_PDG, 0},
+  {"xb_gptr_pben",   0xC6, 0x04, 0x04, "xb_gptr_pben_ring",   VPD_KEYWORD_PDG, 0},
+  {"xb_gptr_perv",   0xC7, 0x04, 0x04, "xb_gptr_perv_ring",   VPD_KEYWORD_PDG, 0},
+  {"xb_time",        0xC8, 0x04, 0x04, "xb_time_ring",        VPD_KEYWORD_PDG, 0},
+  {"pb_gptr_mcl",    0xC9, 0x02, 0x02, "pb_gptr_mcl_ring",    VPD_KEYWORD_PDG, 0},
+  {"pb_time_mcl",    0xCA, 0x02, 0x02, "pb_time_mcl_ring",    VPD_KEYWORD_PDG, 0},
+};
+
+const RingIdList RING_ID_LIST_PR[] = {
+  /*   ringName      ringId chipIdMin chipIdMax     ringNameImg        mvpdKeyword   */
+  {"ab_repr",        0xE0, 0x08, 0x08, "ab_repr_ring",        VPD_KEYWORD_PDR, 0},
+  {"ex_repr_core",   0xE1, 0x10, 0x1F, "ex_repr_core_ring",   VPD_KEYWORD_PDR, 1},
+  {"ex_repr_eco",    0xE2, 0x10, 0x1F, "ex_repr_eco_ring",    VPD_KEYWORD_PDR, 1},
+  {"pb_repr",        0xE3, 0x02, 0x02, "pb_repr_ring",        VPD_KEYWORD_PDR, 0},
+  {"pb_repr_mcr",    0xE4, 0x02, 0x02, "pb_repr_mcr_ring",    VPD_KEYWORD_PDR, 0},
+  {"pb_repr_nx",     0xE5, 0x02, 0x02, "pb_repr_nx_ring",     VPD_KEYWORD_PDR, 0},
+  {"pci_repr",       0xE6, 0x09, 0x09, "pci_repr_ring",       VPD_KEYWORD_PDR, 0},
+  {"perv_repr",      0xE7, 0x00, 0x00, "perv_repr_ring",      VPD_KEYWORD_PDR, 0},
+  {"perv_repr_net",  0xE8, 0x00, 0x00, "perv_repr_net_ring",  VPD_KEYWORD_PDR, 0},
+  {"perv_repr_pib",  0xE9, 0x00, 0x00, "perv_repr_pib_ring",  VPD_KEYWORD_PDR, 0},
+  {"xb_repr",        0xEA, 0x04, 0x04, "xb_repr_ring",        VPD_KEYWORD_PDR, 0},
+  {"pb_repr_mcl",    0xEB, 0x02, 0x02, "pb_repr_mcl_ring",    VPD_KEYWORD_PDR, 0},
+};
+
+const uint32_t RING_ID_LIST_PG_SIZE = sizeof(RING_ID_LIST_PG)/sizeof(RING_ID_LIST_PG[0]);
+const uint32_t RING_ID_LIST_PR_SIZE = sizeof(RING_ID_LIST_PR)/sizeof(RING_ID_LIST_PR[0]);
+
+// get_vpd_ring_list_entry() retrieves the MVPD list entry based on either a ringName
+//   or a ringId.  If both are supplied, only the ringName is used. If ringName==NULL,
+//   then the ringId is used. A pointer to the RingIdList is returned.
+int get_vpd_ring_list_entry(const char *i_ringName, 
+                            const uint8_t i_ringId, 
+                            RingIdList **i_ringIdList)
+{
+  int rc=0, NOT_FOUND=1, FOUND=0;
+  uint8_t iVpdType;
+  uint8_t iRing;
+  RingIdList *ring_id_list=NULL;
+  uint8_t ring_id_list_size;
+
+  rc = NOT_FOUND;
+  for (iVpdType=0; iVpdType<NUM_OF_VPD_TYPES; iVpdType++)  {
+    if (iVpdType==0)  {
+      ring_id_list = (RingIdList*)RING_ID_LIST_PG;
+      ring_id_list_size = (uint32_t)RING_ID_LIST_PG_SIZE;
+    }
+    else  {
+      ring_id_list = (RingIdList*)RING_ID_LIST_PR;
+      ring_id_list_size = (uint32_t)RING_ID_LIST_PR_SIZE;
+    }
+    // Search the MVPD reference lists for either a:
+		// - ringName match with or w/o _image in the name, or
+		// - ringId match.
+    if (i_ringName)  {
+			// Search for ringName match.
+      for (iRing=0; iRing<ring_id_list_size; iRing++)  {
+        if ( strcmp((ring_id_list+iRing)->ringName,   i_ringName)==0  ||
+             strcmp((ring_id_list+iRing)->ringNameImg,i_ringName)==0 )  {
+          *i_ringIdList = ring_id_list+iRing;
+          return FOUND;
+        }
+      }
+    }
+   	else  {  
+			// Search for ringId match (since ringName was not supplied).
+      for (iRing=0; iRing<ring_id_list_size; iRing++)  {
+        if ((ring_id_list+iRing)->ringId==i_ringId)  {
+          *i_ringIdList = ring_id_list+iRing;
+          return FOUND;
+        }
+      }
+    }
+
+  }
+  return rc;
+}
+
+
+
+
diff --git a/src/ppe/tools/image/p9_scan_compression.H b/src/ppe/tools/image/p9_scan_compression.H
new file mode 100644
index 0000000..c2254ab
--- /dev/null
+++ b/src/ppe/tools/image/p9_scan_compression.H
@@ -0,0 +1,369 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/tools/image/p9_scan_compression.H $                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __P9_SCAN_COMPRESSION_H__
+#define __P9_SCAN_COMPRESSION_H__
+
+/// This header declares and documents the entry points defined in
+/// p9_scan_compression.C.  Some constants are also required by the scan
+/// decompression HOMER assembly procedures.
+
+#include "fapi_sbe_common.H"
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+/// Compressed Scan Chain Data Structure Format
+///
+/// The compressed scan ring data structure must be 8-byte aligned in
+/// memory. The container data structure consists of this 24-byte header
+/// followed by an arbitrary number of 8 byte doublewords containing the
+/// compressed scan data.  Images are always stored and processed in
+/// big-endian byte order.  This container format is common across all
+/// decompression algorithms.
+///
+/// Bytes - Content
+/// 
+/// 0:3 - A 32-bit "magic number" that identifies and validates the
+/// compression algorithm and algorithm version used to compress the data.
+///
+/// 4:7 - The 32-bit size of the entire data structure in \e bytes.  This
+/// consists of this 24-byte header plus the compressed scan data.  This value
+/// is always a multiple of 8.
+///
+/// 8:11 - This 32-bit value is reserved to the compression
+/// algorithm. Typically this field is used to record the 'size' of the
+/// compressed string in units specific to each algorithm.
+///
+/// 12:15 - The length of the original scan chain in \e bits.
+///
+/// 16:19 - The 32 high-order bits of the value written to the Scan Select
+/// register to set up the scan.  The Scan Select register only defines these
+/// bits. 
+///
+/// 20 - The Scan Chain Data Structure version number
+///
+/// 21 - Flush-optimize : Is this byte is non-zero, the ring state to be
+/// modified is the flush state of the ring.
+///
+/// 22 - The ring ID uniquely identifying the repair ring name.
+///
+/// 23 - The 7-bit pervasive chiplet Id + Multicast bit of the chiplet to
+/// scan.  This value is loaded directly into P0.  The decompression
+/// algorithms provide two entry points - one that uses this value as the
+/// chiplet Id, and another that allows the caller to specify the chiplet Id
+/// in the call.
+
+typedef struct {
+
+    /// Magic number - See \ref scan_compression_magic
+    uint32_t iv_magic;
+
+    /// Total size in bytes, including the container header
+    uint32_t iv_size;
+
+    /// Reserved to the algorithm
+    uint32_t iv_algorithmReserved;
+
+    /// Length of the original scan chain in bits
+    uint32_t iv_length;
+
+    /// The high-order 32 bits of the Scan Select Register
+    ///
+    /// Note that the Scan Select register only defines the high order 32
+    /// bits, so we only need store the 32 high-order bits.  This field is
+    /// 8-byte aligned so that the doubleword loaded by the HOMER can be
+    /// directly written to the scan select register.
+    uint32_t iv_scanSelect;
+
+    /// Data structure (header) version
+    uint8_t iv_headerVersion;
+
+    /// Flush-state optimization
+    ///
+    /// Normally, modifying the state of the ring requires XOR-ing the
+    /// difference state (the compressed state) with the current ring state as
+    /// it will appear in the Scan Data Register. If the current state of the
+    /// ring is the scan-0 flush state, then by definition the Scan Data
+    /// Register is always 0. Therefore we can simply write the difference to
+    /// the Scan Data Register rather than using a read-XOR-write.
+    uint8_t iv_flushOptimization;
+
+    /// Ring ID uniquely identifying the repair name. (See the list of ring
+		/// name vs ring IDs in p8_ring_identification.c).
+    uint8_t iv_ringId;
+
+    /// 7-bit pervasive chiplet Id + Multicast bit
+    ///
+    /// This field is right-justified in an 8-byte aligned doubleword so that
+    /// the P0 register can be directly updated from the doubelword value in a
+    /// data register.
+    uint8_t iv_chipletId;
+
+} CompressedScanData;
+
+
+/// Endian-translate a CompressedScanData structure
+///
+/// \param o_data A pointer to a CompressedScanData structure to receive the
+/// endian-translated form of \a i_data.
+///
+/// \param i_data A pointer to the original CompressedScanData structure.
+///
+/// This API performs an endian-converting copy of a CompressedScanData
+/// structure. This copy is guaranteed to be done in such a way that \a i_data
+/// and \a o_data may be the same pointer for in-place conversion.  Due to the
+/// symmetry of reverse, translating a structure twice is always guaranteed to
+/// return the origial structure to its original byte order.
+void
+compressed_scan_data_translate(CompressedScanData* o_data,
+                               CompressedScanData* i_data);
+
+
+/// Compress a scan string using the RS4 compression algorithm
+///
+/// \param[in,out] io_data This is a pointer to a memory area which must be
+/// large enough to hold the worst-case result of compressing \a i_string (see
+/// below).  Note that the CompressedScanData is always created in big-endian
+/// format, however the caller can use compresed_scan_data_translate() to
+/// create a copy of the header in host format.
+///
+/// \param[in] i_dataSize The size of \a io_data in bytes.
+///
+/// \param[out] o_imageSize The effective size of the entire compressed scan
+/// data structure (header + compressed data) created in \a io_data, in bytes.
+/// This value will always be a multiple of 8.
+///
+/// \param[in] i_string The string to compress.  Scan data to compress is
+/// left-justified in this input string.
+///
+/// \param[in] i_length The length of the input string in \e bits.  It is
+/// assumed the \a i_string contains at least (\a i_length + 7) / 8 bytes.
+///
+/// \param[in] i_scanSelect The 64-bit value written to the Scan Select
+/// register to set up for the scan. Only the 32 high-order bits are actually
+/// stored.
+///
+/// \param[in] i_ringId The ring ID that uniquely identifies the ring name of
+/// a repair ring. (See p8_ring_identification.c for more info.)
+///
+/// \param[in] i_chipletId The 7-bit value for the iv_chipletId field of the
+/// CompressedScanData.
+///
+/// \param[in] i_flushOptimization This input parameter should be set to a
+/// non-0 value if it is known that this ring difference will be applied to a
+/// scan-0 flush state.  This will improve the performance of the
+/// decompress-scan routine. If the initial state of the ring is unknown, set
+/// this parameter to 0.
+///
+/// This API is required for integration with PHYP which does not support
+/// malloc().  Applications in environments supporting malloc() can use
+/// rs4_compress() instead.
+///
+/// The worst-case compression for RS4 requires 2 nibbles of control overhead
+/// per 15 nibbles of data (17/15), plus a maximum of 2 nibbles of termination.
+/// We always require this worst-case amount of memory including the header and
+/// any rounding required to guarantee that the data size is a multiple of 8
+/// bytes.  The final image size is also rounded up to a multiple of 8 bytes.
+/// If the \a i_dataSize is less than this amount (based on \a i_length) the
+/// call will fail.
+///
+/// \returns See \ref scan_compression_codes
+int
+_rs4_compress(CompressedScanData* io_data,
+              uint32_t i_dataSize,
+              uint32_t* o_imageSize,
+              const uint8_t* i_string, 
+              const uint32_t i_length,
+              const uint64_t i_scanSelect,
+              const uint8_t i_ringId,
+              const uint8_t i_chipletId,
+              const uint8_t i_flushOptimization);
+             
+
+/// Compress a scan string using the RS4 compression algorithm
+///
+/// \param[out] o_data This algorithm uses malloc() to allocate memory for the
+/// compresed data, and returns a pointer to this memory in \a o_data. After
+/// the call this memory is owned by the caller who is responsible for
+/// free()-ing the data area once it is no longer required. Note that the
+/// CompressedScanData is always created in big-endian format, however the
+/// caller can use compresed_scan_data_translate() to create a copy of the
+/// header in host format.
+///
+/// \param[out] o_size The effective size of the entire compressed scan data
+/// structure (header + compressed data) pointed to by \a o_data, in bytes.
+/// This value will always be a multiple of 8.
+///
+/// \param[in] i_string The string to compress.  Scan data to compress is
+/// left-justified in this input string.
+///
+/// \param[in] i_length The length of the input string in \e bits.  It is
+/// assumed the \a i_string contains at least (\a i_length + 7) / 8 bytes.
+///
+/// \param[in] i_scanSelect The 64-bit value written to the Scan Select
+/// register to set up for the scan. Only the 32 high-order bits are actually
+/// stored.
+///
+/// \param[in] i_ringId The ring ID that uniquely identifies the ring name of
+/// a repair ring. (See p8_ring_identification.c for more info.)
+///
+/// \param[in] i_chipletId The 7-bit value for the iv_chipletId field of the
+/// CompressedScanData.
+///
+/// \param[in] i_flushOptimization This input parameter should be set to a
+/// non-0 value if it is known that this ring difference will be applied to a
+/// scan-0 flush state.  This will improve the performance of the
+/// decompress-scan routine. If the initial state of the ring is unknown, set
+/// this parameter to 0.
+///
+/// \returns See \ref scan_compression_codes
+int
+rs4_compress(CompressedScanData** o_data,
+             uint32_t* o_size,
+             const uint8_t* i_string, 
+             const uint32_t i_length,
+             const uint64_t i_scanSelect,
+             const uint8_t i_ringId,
+             const uint8_t i_chipletId,
+             const uint8_t i_flushOptimization);
+             
+
+/// Decompress a scan string compressed using the RS4 compression algorithm
+///
+/// \param[in,out] io_string A caller-supplied data area to contain the
+/// decompressed string. The \a i_stringSize must be large enough to contain
+/// the decompressed string, which is the size of the original string in bits
+/// rounded up to the nearest byte.
+///
+/// \param[in] i_stringSize The size (in bytes) of \a i_string.
+///
+/// \param[out] o_length The length of the decompressed string in \e bits.
+///
+/// \param[in] i_data A pointer to the CompressedScanData header + data to be
+/// decompressed.
+///
+/// This API is required for integration with PHYP which does not support
+/// malloc().  Applications in environments supporting malloc() can use
+/// rs4_decompress() instead.
+///
+/// \returns See \ref scan_compression_codes
+int
+_rs4_decompress(uint8_t* i_string,
+                uint32_t i_stringSize,
+                uint32_t* o_length,
+                const CompressedScanData* i_data);
+             
+
+/// Decompress a scan string compressed using the RS4 compression algorithm
+///
+/// \param[out] o_string The API malloc()-s this data area to contain the
+/// decompressed string. After this call the caller owns \a o_string and is
+/// responsible for free()-ing this data area once it is no longer required.
+///
+/// \param[out] o_length The length of the decompressed string in \e bits.
+/// The caller may assume that \a o_string contains at least (\a o_length + 7)
+/// / 8 \e bytes.
+///
+/// \param[in] i_data A pointer to the CompressedScanData header + data to be
+/// decompressed.
+///
+/// \returns See \ref scan_compression_codes
+int
+rs4_decompress(uint8_t** o_string,
+               uint32_t* o_length,
+               const CompressedScanData* i_data);
+
+
+/// Determine if an RS4 compressed scan string is all 0
+///
+/// \param[in] i_data A pointer to the CompressedScanData header + data to be
+///
+/// \param[out] o_redundant Set to 1 if the RS4 string is the compressed form
+/// of a scan string that is all 0; Otherwise set to 0.
+///
+/// \returns See \ref scan _compression_code
+int
+rs4_redundant(const CompressedScanData* i_data, int* o_redundant);
+             
+
+#endif  // __ASSEMBLER__
+
+
+/// The current version of the CompressedScanData structure
+///
+/// This constant is required to be a #define to guarantee consistency between
+/// the header format and cmopiled code.
+#define COMPRESSED_SCAN_DATA_VERSION 1
+
+/// The size of the CompressedScanData structure
+CONST_UINT8_T(COMPRESSED_SCAN_DATA_SIZE, 24);
+
+
+/// \defgroup scan_compression_magic Scan Compression Magic Numbers
+///
+/// @ {
+
+/// RS4 Magic
+CONST_UINT32_T(RS4_MAGIC, 0x52533401);      /* "RS4" + Version 0x01 */
+
+/// @}
+
+
+/// \defgroup scan_compression_codes Scan Compression Return Codes
+///
+/// @{
+
+/// Normal return code
+CONST_UINT8_T(SCAN_COMPRESSION_OK, 0);
+
+/// The (de)compression algorithm could not allocate enough memory for the
+/// (de)compression.
+CONST_UINT8_T(SCAN_COMPRESSION_NO_MEMORY, 1);
+
+/// Magic number mismatch on scan decompression
+CONST_UINT8_T(SCAN_DECOMPRESSION_MAGIC_ERROR, 2);
+
+/// Decompression size error
+///
+/// Decompression produced a string of a size different than indicated in the
+/// header, indicating either a bug or data corruption.  Note that the entire
+/// application should be considered corrupted if this error occurs since it
+/// may not be discovered until after the decompression buffer is
+/// overrun. This error may also be returned by rs4_redundant() in the event
+/// of inconsistencies in the compressed string.
+CONST_UINT8_T(SCAN_DECOMPRESSION_SIZE_ERROR, 3);
+
+/// A buffer would overflow
+///
+/// Either the caller-supplied memory buffer to _rs4_decompress() was too
+/// small to contain the decompressed string, or a caller-supplied buffer to
+/// _rs4_compress() was not large enough to hold the worst-case compressed
+/// string.
+CONST_UINT8_T(SCAN_COMPRESSION_BUFFER_OVERFLOW, 4);
+
+/// @}
+
+#endif  //  __P8_SCAN_COMPRESSION_H__
diff --git a/src/ppe/tools/image/ppeSetFixed.pl b/src/ppe/tools/image/ppeSetFixed.pl
new file mode 100755
index 0000000..4315a8c
--- /dev/null
+++ b/src/ppe/tools/image/ppeSetFixed.pl
@@ -0,0 +1,234 @@
+#!/usr/bin/perl
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ppe/tools/image/ppeSetFixed.pl $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+# Purpose:  This perl script will parse the attribute and default list and
+# and set the default values into the image.
+
+use strict;
+
+my $attrpath = "../../importtemp/xml";
+my $sbedefaultpath = "../../script/image";
+
+#------------------------------------------------------------------------------
+# Print Command Line Help
+#------------------------------------------------------------------------------
+my $numArgs = $#ARGV + 1;
+if ($numArgs < 3)
+{
+    print ("Usage: ppeSetFixed.pl <image> <attributes and default list> <attribute file> ...\n");
+    print ("  This perl script will the attributes and default list to lookup the defaults\n");
+    print ("  and parse the attribute file to lookup the types.\n");
+    print ("  The default values will be set in the image.\n");
+    print ("example:\n");
+    print ("./ppeSetFixed.pl \\\n" );
+    print (". \\\n" );
+    print (" ../../sbe/obj/seeprom_main.bin \\\n" );
+    print ("$attrpath/p9_ppe_attributes.xml \\\n" );
+    print ("$attrpath/attribute_info/perv_attributes.xml \\\n" );
+    print ("$attrpath/attribute_info/proc_attributes.xml \\\n" );
+    print ("$attrpath/attribute_info/ex_attributes.xml \\\n" );
+    print ("$attrpath/attribute_info/eq_attributes.xml \\\n" );
+    print ("$attrpath/attribute_info/core_attributes.xml \n");
+    exit(1);
+}
+
+#------------------------------------------------------------------------------
+# Specify perl modules to use
+#------------------------------------------------------------------------------
+use XML::Simple;
+my $xml = new XML::Simple (KeyAttr=>[]);
+
+
+my $xmlFiles = 0;
+my $attCount = 0;
+my $numIfAttrFiles = 0;
+my @attrChipIds;
+my @attrExIds;
+my @attrCoreIds;
+my @attrEqIds;
+my @attrPervIds;
+
+
+
+#------------------------------------------------------------------------------
+# Element names
+#------------------------------------------------------------------------------
+my $attribute = 'attribute';
+
+#------------------------------------------------------------------------------
+# For each argument
+#------------------------------------------------------------------------------
+my $sbedefaultpath = $ARGV[0];
+my $image = $ARGV[1];
+my $argfile = $ARGV[2];
+my $entries = $xml->XMLin($argfile, ForceArray => ['entry']);
+
+if ( ! -e $image) {die "ppeSetFixed.pl: $image $!"};
+
+foreach my $entr (@{$entries->{entry}}) {
+
+    my $inname = $entr->{name};
+
+    # read XML file. The ForceArray option ensures that there is an array of
+    # elements even if there is only one such element in the file
+
+    foreach my $argnum (3 .. $#ARGV)
+    {
+        my $infile = $ARGV[$argnum];
+
+        if ( ! -e $infile) {die "ppeSetFixed.pl: $infile $!"};
+
+        my $attributes = $xml->XMLin($infile, ForceArray => ['attribute']);
+
+        #--------------------------------------------------------------------------
+        # For each Attribute
+        #--------------------------------------------------------------------------
+        foreach my $attr (@{$attributes->{attribute}})
+        {
+
+            if($attr->{id} eq $inname) {
+
+            #------------------------------------------------------------------
+            # Check that the AttributeId exists
+            #------------------------------------------------------------------
+            if (! exists $attr->{id})
+            {
+                print ("ppeSbeFixed.pl ERROR. Att 'id' missing\n");
+                exit(1);
+            }
+
+
+            if($attr->{targetType} eq "TARGET_TYPE_PROC_CHIP") {
+
+                push(@attrChipIds, $entr);
+
+            } elsif($attr->{targetType} eq "TARGET_TYPE_CORE") {
+
+                push(@attrCoreIds, $entr);
+                
+            } elsif($attr->{targetType} eq "TARGET_TYPE_EQ") {
+
+                push(@attrEqIds, $entr);
+
+            } elsif($attr->{targetType} eq "TARGET_TYPE_EX") { 
+
+                push(@attrExIds, $entr);
+
+            } elsif($attr->{targetType} eq "TARGET_TYPE_PERV") { 
+
+                push(@attrPervIds, $entr);
+
+            } else {
+
+                print ("ppeSetFixed.pl ERROR. Wrong attribute type: $attr->{targetType}\n");
+                exit(1);
+
+            }
+
+            }
+        }
+    }
+
+}
+
+
+
+setFixed("TARGET_TYPE_PROC_CHIP", @attrChipIds);
+setFixed("TARGET_TYPE_CORE", @attrCoreIds);
+setFixed("TARGET_TYPE_EQ", @attrEqIds);
+setFixed("TARGET_TYPE_EX", @attrExIds);
+setFixed("TARGET_TYPE_PERV", @attrPervIds);
+
+
+
+sub setFixed {
+ 
+    my ($string, @entries) =  @_;
+
+foreach my $attr (@entries)
+{
+
+    my $inname = $attr->{name};
+    
+    my @values = $attr->{value};
+
+
+    if(scalar @values > 0) {
+
+    foreach my $val (@values)
+    {
+
+        if(defined $val && ref($val) eq "") {
+
+            if ($val =~ /(0x)?[0-9a-fA-F]+/) {
+             
+                my $systemRc = system("$sbedefaultpath/sbe_default_tool $image $inname $val $string 0");
+        
+                if ($systemRc) {
+                    print "sbe_default_tool: error in execution\n";
+                    exit 1;
+                }
+                
+            } else {
+                print ("ppeSetFixed.pl ERROR. not hex\n");
+                exit(1);
+            }
+
+        } elsif(defined $val && ref($val) eq "ARRAY") {
+
+            my $index = 0;
+
+            foreach my $arr (@{$val}) {
+
+                if(defined $arr && ref($arr) eq "") {
+                    if ($arr =~ /(0x)?[0-9a-fA-F]+/) {
+
+                        my $systemRc = system("$sbedefaultpath/sbe_default_tool $image $inname $arr $string $index");
+
+                        if ($systemRc) {
+                            print "sbe_default_tool: error in execution\n";
+                            exit 1;
+                        }
+
+
+                    }
+                }
+                $index++;
+            }
+
+
+
+        }
+
+
+    }
+    }
+
+
+}
+
+}
+
+
diff --git a/src/ppe/tools/image/sbe_default_tool.c b/src/ppe/tools/image/sbe_default_tool.c
new file mode 100644
index 0000000..d0e728d
--- /dev/null
+++ b/src/ppe/tools/image/sbe_default_tool.c
@@ -0,0 +1,310 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/tools/image/sbe_default_tool.c $                      */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/// \file sbe_default_tool.c
+/// \brief SBE-XIP image setter tool for attributes in fixed section
+///
+#include <sys/mman.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+
+#include <errno.h>
+#include <fcntl.h>
+#include <regex.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <endian.h>
+
+
+#define __PPE__
+#include "fapi2.H"
+#include "proc_sbe_fixed.H"
+
+const char* g_usage =
+"Usage: sbe_default_tool <image> <attribute> <value> <target type> <index>\n"
+"The 'image' is the binary image with fixed section.\n"
+"\n"
+"The 'attribute' is the attribute to be set.\n"
+"\n"
+"The 'value' is the value of the attribute to be set.\n"
+"\n"
+"The 'target type' is the type of the target. The following targets are defined:\n"
+"TARGET_TYPE_PROC_CHIP: chip target\n"
+"TARGET_TYPE_PERV: pervasive target\n"
+"TARGET_TYPE_CORE: core target\n"
+"TARGET_TYPE_EQ: eq target\n"
+"TARGET_TYPE_EX: ex target\n"
+"\n"
+"The 'index' is the index of the value. Checking is performed.\n"
+"example:\n"
+"./sbe_default_tool ./sbe_main.bin ATTR_PLL_RING 0x33CAFE34 TARGET_TYPE_PERV 0\n"
+"./sbe_default_tool ./sbe_main.bin ATTR_SCRATCH_UINT8_1 12 TARGET_TYPE_PROC_CHIP 0\n"
+    ;
+
+
+void assertTarget(const char* str, unsigned int index)
+{
+
+    if(strcmp(str, "TARGET_TYPE_PROC_CHIP") == 0) {
+        if (index > 0) {
+            fprintf(stderr, "sbe_default_tool: index is larger than 0\n");
+            exit(1);
+        } 
+        return;
+    } else if(strcmp(str, "TARGET_TYPE_EX") == 0)  {
+        if (index >= EX_TARGET_COUNT) {
+            fprintf(stderr, "sbe_default_tool: index is larger than EX_TARGET_COUNT\n");
+            exit(1);
+        } 
+        return;
+    } else if(strcmp(str, "TARGET_TYPE_EQ") == 0)  {
+        if (index >= EQ_TARGET_COUNT) {
+            fprintf(stderr, "sbe_default_tool: index is larger than EQ_TARGET_COUNT\n");
+            exit(1);
+        } 
+        return;
+    } else if(strcmp(str, "TARGET_TYPE_CORE") == 0)  {
+        if (index >= CORE_TARGET_COUNT) {
+            fprintf(stderr, "sbe_default_tool: index is larger than EQ_TARGET_COUNT\n");
+            exit(1);
+        } 
+        return;
+    } else if(strcmp(str, "TARGET_TYPE_PERV") == 0)  {
+        if (index >= PERV_TARGET_COUNT) {
+            fprintf(stderr, "sbe_default_tool: index is larger than PERV_TARGET_COUNT\n");
+            exit(1);
+        } 
+        return;
+    } else {
+
+        if (index >= PERV_TARGET_COUNT) {
+            fprintf(stderr, "sbe_default_tool: target not supported:");
+            fprintf(stderr, " %s\n", str);
+            exit(1);
+        }    
+    }
+}
+
+void setAttribute(void* image, const char* attribute, unsigned int index, uint64_t val) {
+
+
+    SbeXipItem item;
+    void *thePointer;
+    int rc;
+
+    rc = sbe_xip_find(image, attribute, &item);
+    if (rc) {
+        fprintf(stderr, "sbe_default_tool: attribute not existing:");
+        fprintf(stderr, " %s", attribute);
+        exit(1);
+    }
+
+    // debug purpose
+    //printf("offset in string section: 0x%x \n",     be32toh(item.iv_toc->iv_id));
+    //printf("address: 0x%x \n", item.iv_address);
+
+    sbe_xip_image2host(image, item.iv_address, &thePointer);
+
+    // debug purpose
+    //printf("pointer1: 0x%x \n", thePointer);
+    //printf("val: 0x%llx \n", val);
+
+    if(item.iv_toc->iv_type == SBE_XIP_UINT8) {
+
+        *((uint8_t*)thePointer + index) = (uint8_t)val;
+
+    } else if(item.iv_toc->iv_type == SBE_XIP_INT8) {
+
+        *((int8_t*)thePointer + index) = (int8_t)val;
+
+    } else if(item.iv_toc->iv_type == SBE_XIP_UINT16) {
+
+        *((uint16_t*)thePointer + index) = (uint16_t)val;
+
+    } else if(item.iv_toc->iv_type == SBE_XIP_INT16) {
+
+        *((int16_t*)thePointer + index) = (int16_t)val;
+
+    } else if(item.iv_toc->iv_type == SBE_XIP_UINT32) {
+
+        *((uint32_t*)thePointer + index) = (uint32_t)val;
+
+    } else if(item.iv_toc->iv_type == SBE_XIP_INT32) {
+
+        *((int32_t*)thePointer + index) = (int32_t)val;
+
+    } else if(item.iv_toc->iv_type == SBE_XIP_UINT64) {
+
+        *((uint64_t*)thePointer + index) = (uint64_t)val;
+
+    } else if(item.iv_toc->iv_type == SBE_XIP_INT64) {
+
+        *((int64_t*)thePointer + index) = (int64_t)val;
+
+    } else {
+        fprintf(stderr, "sbe_default_tool: type not available");
+        exit(1);
+    }
+
+
+
+
+    SBE_XIP_SECTION_NAMES(section_name);
+    SBE_XIP_TYPE_STRINGS(type_name);
+
+    // debug purpose
+    //printf("pointer2: 0x%x \n", thePointer);
+    //printf("section id: %s \n",  section_name[item.iv_toc->iv_section]);
+    //printf("location in section: 0x%x \n",  be32toh(item.iv_toc->iv_data));
+    //printf("type name: %s \n",  type_name[item.iv_toc->iv_type]);
+
+    return;
+}
+
+
+uint64_t getAttribute(void* image, const char* attribute, unsigned int index) {
+
+    uint64_t val = 0;
+
+    SbeXipItem item;
+    void *thePointer;
+    int rc;
+
+    rc = sbe_xip_find(image, attribute, &item);
+    if (rc) {
+        fprintf(stderr, "sbe_default_tool: attribute not existing:");
+        fprintf(stderr, " %s", attribute);
+        exit(1);
+    }
+    
+    sbe_xip_image2host(image, item.iv_address, &thePointer);
+
+    if(item.iv_toc->iv_type == SBE_XIP_UINT8) {
+
+        val = *((uint8_t*)thePointer + index);
+        
+    } else if(item.iv_toc->iv_type == SBE_XIP_INT8) {
+
+        val = *((int8_t*)thePointer + index);
+        val &= 0xFF; 
+
+    } else if(item.iv_toc->iv_type == SBE_XIP_UINT16) {
+
+        val = *((uint16_t*)thePointer + index);
+
+    } else if(item.iv_toc->iv_type == SBE_XIP_INT16) {
+
+        val = *((int16_t*)thePointer + index);
+        val &= 0xFFFF; 
+
+    } else if(item.iv_toc->iv_type == SBE_XIP_UINT32) {
+
+        val = *((uint32_t*)thePointer + index);
+
+    } else if(item.iv_toc->iv_type == SBE_XIP_INT32) {
+
+        val = *((int32_t*)thePointer + index);
+        val &= 0xFFFFFFFF; 
+
+    } else if(item.iv_toc->iv_type == SBE_XIP_UINT64) {
+
+        val = *((uint64_t*)thePointer + index);
+
+    } else if(item.iv_toc->iv_type == SBE_XIP_INT64) {
+
+        val = *((int64_t*)thePointer + index);
+
+    } else {
+        fprintf(stderr, "sbe_default_tool: type not available");
+        exit(1);
+    }
+
+
+
+    return val;
+}
+
+int  main(int argc, const char** argv)
+{
+
+    int fileFd, rc;
+    void* image;
+    struct stat buf;
+
+    if(argc != 6) {
+        fprintf(stderr, "sbe_default_tool: argument missing\n");
+        fprintf(stderr, g_usage);
+        exit(1);
+    } 
+
+    printf("sbe_default_tool %s %s %s %s %s\n", argv[1], argv[2], argv[3], argv[4], argv[5]);
+
+    fileFd = open(argv[1], O_RDWR);
+    if (fileFd < 0) {
+        fprintf(stderr, "sbe_default_tool: open() of the file to be appended failed");
+        exit(1);
+    }
+
+    rc = fstat(fileFd, &buf);
+    if (rc) {
+        fprintf(stderr, "sbe_default_tool: fstat() of the file to be appended failed");
+        exit(1);
+    }
+
+    image = mmap(0, buf.st_size, PROT_READ | PROT_WRITE, MAP_SHARED, fileFd, 0);
+    if (image == MAP_FAILED) {
+        fprintf(stderr, "sbe_default_tool: mmap() of the file to be appended failed");
+        exit(1);
+    }
+
+
+    uint64_t val=strtoull(argv[3], 0, 0);
+
+    unsigned int index = strtoul(argv[5], 0, 10);
+
+    assertTarget(argv[4], index);
+
+    setAttribute(image, argv[2], index, val);
+
+    uint64_t check = getAttribute(image, argv[2], index);
+
+    if((check & val) != check) {
+            
+        fprintf(stderr, "sbe_default_tool: set and get values not equal");
+        fprintf(stderr, "%lx != %lx\n", check, val);
+        exit(1);
+
+    }
+
+    rc = close(fileFd);
+    if (rc) {
+        fprintf(stderr, "sbe_default_tool: close() of modified image failed");
+        exit(1);
+    }
+
+			
+    return 0;
+}
diff --git a/src/ppe/tools/image/sbe_xip_tool.c b/src/ppe/tools/image/sbe_xip_tool.c
new file mode 100644
index 0000000..111d9a8
--- /dev/null
+++ b/src/ppe/tools/image/sbe_xip_tool.c
@@ -0,0 +1,2135 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/tools/image/sbe_xip_tool.c $                          */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: sbe_xip_tool.c,v 1.13 2014/06/27 20:50:16 maploetz Exp $
+
+/// \file sbe_xip_tool.c
+/// \brief SBE-XIP image search/edit tool
+///
+/// Note: This file was originally stored under .../procedures/ipl/sbe.  It
+/// was moved here at version 1.19.
+
+#include <sys/mman.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+
+#include <errno.h>
+#include <fcntl.h>
+#include <regex.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+
+
+#define __PPE__
+#include "fapi2.H"
+#include "proc_sbe_fixed.H"
+#include "sbe_xip_image.h"
+
+#include "sbe_link.H"
+#include "p9_image_help_base.H"
+#include "p9_ring_identification.H"
+#include "p9_scan_compression.H"
+
+// Usage: sbe_xip_tool <image> [-<flag> ...] normalize
+//        sbe_xip_tool <image> [-<flag> ...] get <item>
+//        sbe_xip_tool <image> [-<flag> ...] getv <item> <index>
+//        sbe_xip_tool <image> [-<flag> ...] set <item> <value> [ <item1> <value1> ... ]
+//        sbe_xip_tool <image> [-<flag> ...] setv <item> <index> <value> [ <item1> <index1> <value1> ... ]
+//        sbe_xip_tool <image> [-<flag> ...] report [<regex>]
+//        sbe_xip_tool <image> [-<flag> ...] append <section> <file>
+//        sbe_xip_tool <image> [-<flag> ...] extract <section> <file>
+//        sbe_xip_tool <image> [-<flag> ...] delete [ <section0> ... <sectionN> ]
+//        sbe_xip_tool <image> [-<flag> ...] dis <section or .rings_summary>\n"//
+// 
+// This simple application uses the SBE-XIP image APIs to normalize, search
+// update and edit SBE-XIP images. This program encapsulates several commands
+// in a common command framework which requires an image to operate on, a
+// command name, and command arguments that vary by command.  Commands that
+// modify the image always rewrite the image in-place in the filesystem;
+// however the original image is only modified if the command has completed
+// without error.
+// 
+// The program operates on an SBE-XIP format binary image, which must be
+// normalized - unless the tool is being called to normalize the image in the
+// first place using the 'normalize' command. The tool also validates the
+// image prior to operating on the image.
+// 
+// The 'get' command retrieves a scalar value from the image and prints its
+// representation on stdout (followed by a newline).  Scalar integer values
+// and image addresses are printed as hex numbers (0x...).  Strings are printed
+// verbatim.
+// 
+// The 'getv' command retrieves a vector element from the image and prints its
+// representation on stdout (followed by a newline).  Integer values
+// and image addresses are printed as hex numbers (0x...).  Vectors of strings
+// are not supported.
+// 
+// The 'set' command allows setting integer and string values in the image.
+// New integer values can be specified in decimal or hex (0x...).  Strings are
+// taken verbatim from the command line.  Note that new string values will be
+// silently truncated to the length of the current string if the new value is
+// longer than the current string. Updating address values is currently not
+// supported.  Any number of item/value pairs can be specified with a single
+// 'set' command.
+//
+// The 'setv' command is provided to set individual vector elements of
+// integral arrays.
+// 
+// The 'report' command prints a report including a dump of the header and
+// section table, a listing of the types and values of all items that appear
+// in the TOC. The TOC listing includes the
+// sequence number of the entry in the TOC, the item name, the item type and
+// the item value.
+//
+// The 'append' command either creates or extends the section named by the
+// section argument, by appending the contents of the named file verbatim.
+// Currently the section must either be the final (highest address) section of
+// the image, or must be empty, in which case the append command creates the
+// section as the final section of the image. The 'append' command writes the
+// relocatable image address where the input file was loaded to stdout.
+//
+// The 'extract' command extracts a sections from the binary image.
+//
+// The 'delete' command deletes 0 or more sections, starting with <section0>.
+// Each section to be deleted must either be the final (highest address)
+// section of the image at the time it is deleted, or must be empty. The
+// 'delete' command writes the size of the final modified image to stdout.
+//
+// The 'dis' command disassembles the section named by the section argument.
+// Note that the section name .rings_summary, which is not an actual XIP
+// section name, merely indicates to summarize the .rings section.
+//
+// The following -i<flag> are supported:
+// -ifs
+//    causes the validation step to ignore image size check against the file
+//    size.
+// -iv
+//    causes all validation checking to be ignored. (Skips validation step.)
+
+const char* g_usage =
+"Usage: sbe_xip_tool <image> [-i<flag> ...] normalize\n"
+"       sbe_xip_tool <image> [-i<flag> ...] get <item>\n"
+"       sbe_xip_tool <image> [-i<flag> ...] getv <item> <index>\n"
+"       sbe_xip_tool <image> [-i<flag> ...] set <item> <value> [ <item1> <value1> ... ]\n"
+"       sbe_xip_tool <image> [-i<flag> ...] setv <item> <index> <value> [ <item1> <index1> <value1> ... ]\n"
+"       sbe_xip_tool <image> [-i<flag> ...] report [<regex>]\n"
+"       sbe_xip_tool <image> [-i<flag> ...] append <section> <file>\n"
+"       sbe_xip_tool <image> [-i<flag> ...] extract <section> <file>\n"
+"       sbe_xip_tool <image> [-i<flag> ...] delete [ <section0> ... <sectionN> ]\n"
+"       sbe_xip_tool <image> [-i<flag> ...] dis <section or .rings_summary>\n"//\n"
+"\n"
+"This simple application uses the SBE-XIP image APIs to normalize, search\n"
+"update and edit SBE-XIP images. This program encapsulates several commands\n"
+"in a common command framework which requires an image to operate on, a\n"
+"command name, and command arguments that vary by command.  Commands that\n"
+"modify the image always rewrite the image in-place in the filesystem;\n"
+"however the original image is only modified if the command has completed\n"
+"without error.\n"
+"\n"
+"The program operates on an SBE-XIP format binary image, which must be\n"
+"normalized - unless the tool is being called to normalize the image in the\n"
+"first place using the 'normalize' command. The tool also validates the\n"
+"image prior to operating on the image.\n"
+"\n"
+"The 'get' command retrieves a scalar value from the image and prints its\n"
+"representation on stdout (followed by a newline).  Scalar integer values\n"
+"and image addresses are printed as hex numbers (0x...).  Strings are printed\n"
+"verbatim.\n"
+"\n"
+"The 'getv' command retrieves a vector element from the image and prints its\n"
+"representation on stdout (followed by a newline).  Integer values\n"
+"and image addresses are printed as hex numbers (0x...).  Vectors of strings\n"
+"are not supported.\n"
+"\n"
+"The 'set' command allows setting integer and string values in the image.\n"
+"New integer values can be specified in decimal or hex (0x...).  Strings are\n"
+"taken verbatim from the command line.  Note that new string values will be\n"
+"silently truncated to the length of the current string if the new value is\n"
+"longer than the current string. Updating address values is currently not\n"
+"supported.  Any number of item/value pairs can be specified with a single\n"
+"'set' command.\n"
+"\n"
+"The 'setv' command is provided to set individual vector elements of\n"
+"integral arrays.\n"
+"\n"
+"The 'report' command prints a report including a dump of the header and\n"
+"section table, a listing of the types and values of all items that appear\n"
+"in the TOC. The TOC listing includes the\n"
+"sequence number of the entry in the TOC, the item name, the item type and\n"
+"the item value.\n"
+"\n"
+"The 'append' command either creates or extends the section named by the\n"
+"section argument, by appending the contents of the named file verbatim.\n"
+"Currently the section must either be the final (highest address) section of\n"
+"the image, or must be empty, in which case the append command creates the\n"
+"section as the final section of the image. The 'append' command writes the\n"
+"relocatable image address where the input file was loaded to stdout.\n"
+"\n"
+"The 'extract' command extracs a sections from a binary image.\n"
+"\n"
+"The 'delete' command deletes 0 or more sections, starting with <section0>.\n"
+"Each section to be deleted must either be the final (highest address)\n"
+"section of the image at the time it is deleted, or must be empty. The\n"
+"'delete' command writes the size of the final modified image to stdout.\n"
+"\n"
+"The 'dis' command disassembles the section named by the section argument.\n"
+"Note that the section name .rings_summary, which is not an actual XIP\n"
+"section name, merely indicates to summarize the .rings section.\n"
+"\n"
+"-i<flag>:\n"
+"\t-ifs  Causes the validation step to ignore image size check against the\n"
+"\tfile size.\n"
+"\t-iv   Causes all validation checking to be ignored.\n"
+    ;
+
+SBE_XIP_ERROR_STRINGS(g_errorStrings);
+SBE_XIP_TYPE_STRINGS(g_typeStrings);
+SBE_XIP_TYPE_ABBREVS(g_typeAbbrevs);
+SBE_XIP_SECTION_NAMES(g_sectionNames);
+// Disassembler error support.
+DIS_ERROR_STRINGS(g_errorStringsDis);
+
+#define ERRBUF_SIZE 60
+
+typedef struct {
+    int index;
+    int regex;
+    regex_t preg;
+} ReportControl;
+
+off_t g_imageSize;
+
+
+// Byte-reverse a 32-bit integer if on an LE machine
+inline uint32_t 
+myRev32(const uint32_t i_x)
+{
+    uint32_t rx;
+
+#ifdef _BIG_ENDIAN
+    rx = i_x;
+#else
+    uint8_t *pix = (uint8_t*)(&i_x);
+    uint8_t *prx = (uint8_t*)(&rx);
+
+    prx[0] = pix[3];
+    prx[1] = pix[2];
+    prx[2] = pix[1];
+    prx[3] = pix[0];
+#endif
+
+    return rx;
+}
+
+// Byte-reverse a 64-bit integer if on a little-endian machine
+inline uint64_t 
+myRev64(const uint64_t i_x)
+{
+    uint64_t rx;
+
+#ifdef _BIG_ENDIAN
+    rx = i_x;
+#else
+    uint8_t *pix = (uint8_t*)(&i_x);
+    uint8_t *prx = (uint8_t*)(&rx);
+
+    prx[0] = pix[7];
+    prx[1] = pix[6];
+    prx[2] = pix[5];
+    prx[3] = pix[4];
+    prx[4] = pix[3];
+    prx[5] = pix[2];
+    prx[6] = pix[1];
+    prx[7] = pix[0];
+#endif
+
+    return rx;
+}
+
+// Normalize an SBE-XIP image.  We normalize a copy of the image first so that
+// the original image will be available for debugging in case the
+// normalization fails, then validate and copy the normalized image back to
+// the mmap()-ed file.
+
+int
+normalize(void* io_image, const int i_argc, const char** i_argv, uint32_t i_maskIgnores)
+{
+    int rc;
+    void *copy;
+
+    do {
+
+        // The 'normalize' command takes no arguments
+
+        if (i_argc != 0) {
+            fprintf(stderr, g_usage);
+            exit(1);
+        }
+
+        copy = malloc(g_imageSize);
+        if (copy == 0) {
+            perror("malloc() failed : ");
+            exit(1);
+        }
+
+        memcpy(copy, io_image, g_imageSize);
+    
+        rc = sbe_xip_normalize(copy);
+        if (rc) break;
+
+        if ( !(i_maskIgnores & SBE_XIP_IGNORE_ALL) )  {
+            rc = sbe_xip_validate2(copy, g_imageSize, i_maskIgnores);
+        }
+        if (rc) break;
+
+        memcpy(io_image, copy, g_imageSize);
+
+    } while (0);
+
+    return rc;
+}
+
+
+// Print a line of a report, listing the index, symbol, type and current
+// value. 
+
+int
+tocListing(void* io_image,
+           const SbeXipItem* i_item, 
+           void* arg)
+{
+    int rc;
+    ReportControl *control;
+    uint64_t data;
+    char* s;
+
+    control = (ReportControl*)arg;
+
+    do {
+        rc = 0;
+
+        if (control->regex) {
+            if (regexec(&(control->preg), i_item->iv_id, 0, 0, 0)) {
+                break;
+            }
+        }
+                        
+        printf("0x%04x | %-42s | %s | ",
+               control->index, i_item->iv_id, 
+               SBE_XIP_TYPE_STRING(g_typeAbbrevs, i_item->iv_type));
+
+        switch (i_item->iv_type) {
+        case SBE_XIP_UINT8:
+            rc = sbe_xip_get_scalar(io_image, i_item->iv_id, &data);
+            if (rc) break;
+            printf("0x%02x", (uint8_t)data);
+            break;
+        case SBE_XIP_INT8:
+            rc = sbe_xip_get_scalar(io_image, i_item->iv_id, &data);
+            if (rc) break;
+            printf("%d", (int8_t)data);
+            break;
+        case SBE_XIP_UINT16:
+            rc = sbe_xip_get_scalar(io_image, i_item->iv_id, &data);
+            if (rc) break;
+            printf("0x%08x", (uint16_t)data);
+            break;
+        case SBE_XIP_INT16:
+            rc = sbe_xip_get_scalar(io_image, i_item->iv_id, &data);
+            if (rc) break;
+            printf("%d", (int16_t)data);
+            break;
+        case SBE_XIP_UINT32:
+            rc = sbe_xip_get_scalar(io_image, i_item->iv_id, &data);
+            if (rc) break;
+            printf("0x%08x", (uint32_t)data);
+            break;
+        case SBE_XIP_INT32:
+            rc = sbe_xip_get_scalar(io_image, i_item->iv_id, &data);
+            if (rc) break;
+            printf("%d", (int32_t)data);
+            break;
+        case SBE_XIP_UINT64:
+            rc = sbe_xip_get_scalar(io_image, i_item->iv_id, &data);
+            if (rc) break;
+            printf("0x%016llx", data);
+            break;
+        case SBE_XIP_INT64:
+            rc = sbe_xip_get_scalar(io_image, i_item->iv_id, &data);
+            if (rc) break;
+            printf("%d", (int64_t)data);
+            break;
+        case SBE_XIP_STRING:
+            rc = sbe_xip_get_string(io_image, i_item->iv_id, &s);
+            if (rc) break;
+            printf("%s", s);
+            break;
+        case SBE_XIP_ADDRESS:
+            rc = sbe_xip_get_scalar(io_image, i_item->iv_id, &data);
+            if (rc) break;
+            printf("0x%04x:0x%08x", 
+                   (uint16_t)((data >> 32) & 0xffff),
+                   (uint32_t)(data & 0xffffffff));
+            break;
+        default:
+            printf("unknown type\n");
+            rc = SBE_XIP_BUG;
+            break;
+        }
+        printf("\n");
+    } while (0);
+    control->index += 1;
+    return rc;
+}
+
+
+// Dump the image header, including the section table
+
+int
+dumpHeader(void* i_image)
+{
+    int i;
+    SbeXipHeader header;
+    SbeXipSection* section;
+    char magicString[9];
+
+    SBE_XIP_SECTION_NAMES(section_name);
+
+    // Dump header information. Since the TOC may not exist we need to get
+    // the information from the header explicitly.
+
+    sbe_xip_translate_header(&header, (SbeXipHeader*)i_image);
+
+    memcpy(magicString, (char*)(&(((SbeXipHeader*)i_image)->iv_magic)), 8);
+    magicString[8] = 0;
+
+    printf("Magic Number   : 0x%016llx \"%s\"\n", 
+           header.iv_magic, magicString);
+    printf("Header Version : 0x%02x\n", header.iv_headerVersion);
+    printf("Link Address   : 0x%016llx\n", header.iv_linkAddress);
+    printf("Entry Offset   : 0x%08x\n", (uint32_t)header.iv_entryOffset);
+    printf("Image Size     : 0x%08x (%d)\n",
+           header.iv_imageSize, header.iv_imageSize);
+    printf("Normalized     : %s\n", header.iv_normalized ? "Yes" : "No");
+    printf("TOC Sorted     : %s\n", header.iv_tocSorted ? "Yes" : "No");
+    printf("Build Date     : %02d/%02d/%04d\n", 
+           (header.iv_buildDate / 100) % 100,
+           header.iv_buildDate % 100,
+           header.iv_buildDate / 10000);
+    printf("Build Time     : %02d:%02d\n", 
+           header.iv_buildTime / 100,
+           header.iv_buildTime % 100);
+    printf("Build User     : %s\n", header.iv_buildUser);
+    printf("Build Host     : %s\n", header.iv_buildHost);
+    printf("\n");
+
+    printf("Section Table  :   Offset      Size\n");
+    printf("\n");
+
+    for (i = 0; i < SBE_XIP_SECTIONS; i++) {
+        section = &(header.iv_section[i]);
+        printf("%-16s 0x%08x 0x%08x (%d)\n",
+               section_name[i], 
+               section->iv_offset, section->iv_size, section->iv_size);
+    }
+
+    printf("\n");
+
+    return 0;
+}
+
+
+// Print a report
+
+int
+report(void* io_image, const int i_argc, const char** i_argv)
+{
+    int rc;
+    ReportControl control;
+    char errbuf[ERRBUF_SIZE];
+
+    do {
+
+        // Basic syntax check : [<regexp>]
+        
+        if (i_argc > 1) {
+            fprintf(stderr, g_usage);
+            exit(1);
+        }
+
+        // Compile a regular expression if supplied
+
+        if (i_argc == 1) {
+            rc = regcomp(&(control.preg), i_argv[0], REG_NOSUB);
+            if (rc) {
+                regerror(rc, &(control.preg), errbuf, ERRBUF_SIZE);
+                fprintf(stderr, "Error from regcomp() : %s\n", errbuf);
+                exit(1);
+            }
+            control.regex = 1;
+        } else {
+            control.regex = 0;
+
+            dumpHeader(io_image);
+            printf("TOC Report\n\n");
+        }
+            
+        // Map the TOC with the mapReport() function
+
+        control.index = 0;
+        rc = sbe_xip_map_toc(io_image, tocListing, (void*)(&control));
+        if (rc) break;
+
+    } while (0);
+
+    return rc;
+}
+
+
+// Set a scalar or vector element values in the image.  The 'i_setv' argument
+// indicates set/setv (0/1).
+
+int
+set(void* io_image, const int i_argc, const char** i_argv, int i_setv)
+{
+    int rc, arg, base, clause_args, index_val;
+    SbeXipItem item;
+    unsigned long long newValue;
+    const char *key, *index, *value;
+    char *endptr;
+
+    do {
+
+        // Basic syntax check: <item> <value> [ <item1> <value1> ... ]
+        // Basic syntax check: <item> <index> <value> [ <item1> <index1> <value1> ... ]
+
+        clause_args = (i_setv ? 3 : 2);
+
+        if ((i_argc % clause_args) != 0) {
+            fprintf(stderr, g_usage);
+            exit(1);
+        }
+
+        for (arg = 0; arg < i_argc; arg += clause_args) {
+
+            key = i_argv[arg];
+            if (i_setv) {
+                index = i_argv[arg + 1];
+                index_val = strtol(index, 0, 0);
+                value = i_argv[arg + 2];
+            } else {
+                index = "";
+                index_val = 0;
+                value = i_argv[arg + 1];
+            }
+
+            // Search for the item to see what type of data it expects, then
+            // case split on the type.
+
+            rc = sbe_xip_find(io_image, key, &item);
+            if (rc) break;
+
+            if (index_val < 0) {
+                fprintf(stderr, 
+                        "Illegal negative vector index %s for %s\n", 
+                        index, key);
+                exit(1);
+            } else if ((item.iv_elements != 0) && 
+                       (index_val >= item.iv_elements)) {
+                fprintf(stderr, 
+                        "Index %s out-of-bounds for %s (%d elements)\n", 
+                        index, key, item.iv_elements);
+                exit(1);
+            }
+            
+            switch (item.iv_type) {
+            case SBE_XIP_UINT8:
+            case SBE_XIP_UINT16:
+            case SBE_XIP_UINT32:
+            case SBE_XIP_UINT64:
+
+                // We need to do a bit of preprocessing on the string to
+                // determine its format and set the base for strtoull(),
+                // otherwise strtoull() will be confused by leading zeros
+                // e.g. in time strings generated by `date +%H%M`, and try to
+                // process the string as octal.
+
+                if ((strlen(value) >= 2) && (value[0] == '0') &&
+                    ((value[1] == 'x') || (value[1] == 'X'))) {
+                    base = 16;
+                } else {
+                    base = 10;
+                }
+
+                errno = 0;
+                newValue = strtoull(value, &endptr, base);
+                if ((errno != 0) || (endptr != (value + strlen(value)))) {
+                    fprintf(stderr, 
+                            "Error parsing putative integer value : %s\n",
+                            value);
+                    exit(1);
+                }
+
+                switch (item.iv_type) {
+
+                case SBE_XIP_UINT8:
+                    if ((uint8_t)newValue != newValue) {
+                        fprintf(stderr, 
+                                "Value 0x%016llx too large for 8-bit type\n",
+                                newValue);
+                        exit(1);
+                    }
+                    break;
+                    
+                case SBE_XIP_UINT16:
+                    if ((uint16_t)newValue != newValue) {
+                        fprintf(stderr, 
+                                "Value 0x%016llx too large for 16-bit type\n",
+                                newValue);
+                        exit(1);
+                    }
+                    break;
+
+                case SBE_XIP_UINT32:
+                    if ((uint32_t)newValue != newValue) {
+                        fprintf(stderr, 
+                                "Value 0x%016llx too large for 32-bit type\n",
+                                newValue);
+                        exit(1);
+                    }
+                    break;
+
+                case SBE_XIP_UINT64:
+                    break;
+
+                default:
+                    break;
+                }
+
+                rc = sbe_xip_set_element(io_image, key, index_val, newValue);
+                if (rc) rc = SBE_XIP_BUG;
+                break;
+
+            case SBE_XIP_STRING:
+
+                if (i_setv) {
+                    fprintf(stderr, "Can't use 'setv' for string data %s\n",
+                            key);
+                    exit(1);
+                }
+                rc = sbe_xip_set_string(io_image, key, (char*)value);
+                if (rc) rc = SBE_XIP_BUG;
+                break;
+            case SBE_XIP_INT8:
+            case SBE_XIP_INT16:
+            case SBE_XIP_INT32:
+            case SBE_XIP_INT64:
+                fprintf(stderr, 
+                        "Item %s has int type %s, "
+                        "which is not supported for '%s'.\n",
+                        i_argv[arg], 
+                        SBE_XIP_TYPE_STRING(g_typeStrings, item.iv_type),
+                        (i_setv ? "setv" : "set"));
+                exit(1);
+                break;
+            default:
+                fprintf(stderr, 
+                        "Item %s has type %s, "
+                        "which is not supported for '%s'.\n",
+                        i_argv[arg], 
+                        SBE_XIP_TYPE_STRING(g_typeStrings, item.iv_type),
+                        (i_setv ? "setv" : "set"));
+                exit(1);
+                break;
+            }
+
+            if (rc) break;
+
+        }
+    } while (0);
+
+    //if good rc, we need to msync the mmaped file to push contents to
+    //the actual file. Per man page this is required although some
+    //file systems (notably AFS) don't seem to require (GSA does)
+    if(!rc)
+    {
+        uint8_t i = 0;
+        do {
+                rc = msync(io_image, g_imageSize , MS_SYNC);
+                if(rc)
+                {
+                    i++;
+                    fprintf(stderr, 
+                             "msync failed with errno %d\n", errno);
+                }
+        } while(rc && i < 5);
+
+        if(rc)
+        {
+            exit(3);
+        }
+    }
+
+    return rc;
+}
+    
+
+// Get a value from the image, and return on stdout.  The 'i_getv' argument
+// indicates get/getv (0/1)
+
+int
+get(void* i_image, const int i_argc, const char** i_argv, int i_getv)
+{
+    int rc, nargs, index_val;
+    SbeXipItem item;
+    const char *key, *index;
+    uint64_t data;
+    char* s;
+
+    do {
+
+        // Basic syntax check: <item>
+        // Basic syntax check: <item> <index>
+
+        nargs = (i_getv ? 2 : 1);
+
+        if (i_argc != nargs) {
+            fprintf(stderr, g_usage);
+            exit(1);
+        }
+
+        key = i_argv[0];
+        if (i_getv) {
+            index = i_argv[1];
+            index_val = strtol(index, 0, 0);
+        } else {
+            index = "";
+            index_val = 0;
+        }
+
+        // Search for the item to determine its type, then case split on the
+        // type. 
+
+        rc = sbe_xip_find(i_image, key, &item);
+        if (rc) break;
+
+        if (index_val < 0) {
+            fprintf(stderr, 
+                    "Illegal negative vector index %s for %s\n", 
+                    index, key);
+            exit(1);
+        } else if ((item.iv_elements != 0) && 
+                   (index_val >= item.iv_elements)) {
+            fprintf(stderr, "Index %s out-of-bounds for %s (%d elements)\n", 
+                    index, key, item.iv_elements);
+            exit(1);
+        }
+
+        switch (item.iv_type) {
+
+        case SBE_XIP_UINT8:
+        case SBE_XIP_UINT16:
+        case SBE_XIP_UINT32:
+        case SBE_XIP_UINT64:
+            rc = sbe_xip_get_element(i_image, key, index_val, &data);
+            if (rc) {
+                rc = SBE_XIP_BUG;
+                break;
+            }
+            switch (item.iv_type) {
+            case SBE_XIP_UINT8:
+                printf("0x%02x\n", (uint8_t)data);
+                break;
+            case SBE_XIP_UINT16:
+                printf("0x%04x\n", (uint16_t)data);
+                break;
+            case SBE_XIP_UINT32:
+                printf("0x%08x\n", (uint32_t)data);
+                break;
+            case SBE_XIP_UINT64:
+                printf("0x%016llx\n", data);
+                break;
+            default:
+                break;
+            }
+            break;
+
+        case SBE_XIP_ADDRESS:
+            if (i_getv) {
+                fprintf(stderr, "Can't use 'getv' for address data : %s\n",
+                        key);
+                exit(1);
+            }
+            rc = sbe_xip_get_scalar(i_image, key, &data);
+            if (rc) {
+                rc = SBE_XIP_BUG;
+                break;
+            }
+            printf("0x%012llx\n", data);
+            break;
+
+        case SBE_XIP_STRING:
+            if (i_getv) {
+                fprintf(stderr, "Can't use 'getv' for string data : %s\n",
+                        key);
+                exit(1);
+            }
+            rc = sbe_xip_get_string(i_image, key, &s);
+            if (rc) {
+                rc = SBE_XIP_BUG;
+                break;
+            }
+            printf("%s\n", s);
+            break;
+        case SBE_XIP_INT8:
+        case SBE_XIP_INT16:
+        case SBE_XIP_INT32:
+        case SBE_XIP_INT64:
+            fprintf(stderr, "%s%d : Bug, int types not implemented %d\n",
+                    __FILE__, __LINE__, item.iv_type);
+            exit(1);
+            break;
+        default:
+            fprintf(stderr, "%s%d : Bug, unexpected type %d\n",
+                    __FILE__, __LINE__, item.iv_type);
+            exit(1);
+            break;
+        }
+    } while (0);
+
+    return rc;
+}
+
+
+// strtoul() with application-specific error handling
+
+unsigned long
+localStrtoul(const char* s)
+{
+    unsigned long v;
+    char* endptr;
+
+    errno = 0;
+    v = strtoul(s, &endptr, 0);
+    if ((errno != 0) || (endptr != (s + strlen(s)))) {
+        fprintf(stderr, 
+                "Error parsing putative integer value : %s\n",
+                s);
+        exit(1);
+    }
+    return v;
+}
+
+
+// Append a file to section
+int
+append(const char* i_imageFile, const int i_imageFd, void* io_image, 
+       int i_argc, const char** i_argv)
+{
+    int fileFd, newImageFd, sectionId, rc;
+    struct stat buf;
+    const char* section;
+    const char* file;
+    void* appendImage;
+    void* newImage;
+    uint32_t size, newSize, sectionOffset;
+    uint64_t homerAddress;
+
+    do {
+
+        // Basic syntax check: <section> <file>
+
+        if (i_argc != 2) {
+            fprintf(stderr, g_usage);
+            exit(1);
+        }
+        section = i_argv[0];
+        file = i_argv[1];
+        
+        // Translate the section name to a section Id
+
+        for (sectionId = 0; sectionId < SBE_XIP_SECTIONS; sectionId++) {
+            if (strcmp(section, g_sectionNames[sectionId]) == 0) {
+                break;
+            }
+        }
+        if (sectionId == SBE_XIP_SECTIONS) {
+            fprintf(stderr, "Unrecognized section name : '%s;\n",
+                    section);
+            exit(1);
+        }
+
+
+        // Open and mmap the file to be appended
+
+        fileFd = open(file, O_RDONLY);
+        if (fileFd < 0) {
+            perror("open() of the file to be appended failed : ");
+            exit(1);
+        }
+
+        rc = fstat(fileFd, &buf);
+        if (rc) {
+            perror("fstat() of the file to be appended failed : ");
+            exit(1);
+        }
+
+        appendImage = mmap(0, buf.st_size, PROT_READ, MAP_SHARED, fileFd, 0);
+        if (appendImage == MAP_FAILED) {
+            perror("mmap() of the file to be appended failed : ");
+            exit(1);
+        }
+
+
+        // malloc() a buffer for the new image, adding space for alignment
+
+        rc = sbe_xip_image_size(io_image, &size);
+        if (rc) break;
+
+        newSize = size + buf.st_size + SBE_XIP_MAX_SECTION_ALIGNMENT;
+
+        newImage = malloc(newSize);
+
+        if (newImage == 0) {
+            fprintf(stderr, "Can't malloc() a buffer for the new image\n");
+            exit(1);
+        }
+
+
+        // Copy the image.  At this point the original image file must be
+        // closed.
+
+        memcpy(newImage, io_image, size);
+
+        rc = close(i_imageFd);
+        if (rc) {
+            perror("close() of the original image file failed : ");
+            exit(1);
+        }
+
+
+        // Do the append and print the image address where the data was loaded.
+        // We will not fail for unaligned addresses, as we have no knowledge
+        // of whether or why the user wants the final image address.
+
+        rc = sbe_xip_append(newImage, sectionId, 
+                            appendImage, buf.st_size,
+                            newSize, &sectionOffset);
+        if (rc) break;
+
+        rc = sbe_xip_section2image(newImage, sectionId, sectionOffset,
+                                  &homerAddress);
+        if (rc && (rc != SBE_XIP_ALIGNMENT_ERROR)) break;
+
+        printf("0x%016llx\n", homerAddress);
+
+
+        // Now write the new image back to the filesystem
+
+        newImageFd = open(i_imageFile, O_WRONLY | O_TRUNC);
+        if (newImageFd < 0) {
+            perror("re-open() of image file failed : ");
+            exit(1);
+        }
+
+        rc = sbe_xip_image_size(newImage, &size);
+        if (rc) break;
+
+        rc = write(newImageFd, newImage, size);
+        if ((rc < 0) || ((uint32_t)rc != size)) {
+            perror("write() of modified image failed : ");
+            exit(1);
+        }
+
+        rc = close(newImageFd);
+        if (rc) {
+            perror("close() of modified image failed : ");
+            exit(1);
+        }
+    } while (0);
+
+    return rc;
+}
+
+// Extract section from a file
+int
+extract(const char* i_imageFile, const int i_imageFd, void* io_image, 
+        int i_argc, const char** i_argv)
+{
+    int fileFd, newImageFd, sectionId, rc;
+    void* newImage;
+    const char* section;
+    const char* file;
+    struct stat buf;
+    SbeXipHeader header;
+    SbeXipSection* xSection;
+    uint32_t size;
+    uint32_t offset;
+    unsigned int i;
+
+    do {
+
+        if (i_argc != 2) {
+            fprintf(stderr, g_usage);
+            exit(1);
+        }
+        section = i_argv[0];
+        file = i_argv[1];
+
+        printf("%s %s\n", section , file);
+
+        for (sectionId = 0; sectionId < SBE_XIP_SECTIONS; sectionId++) {
+            if (strcmp(section, g_sectionNames[sectionId]) == 0) {
+                break;
+            }
+        }
+        if (sectionId == SBE_XIP_SECTIONS) {
+            fprintf(stderr, "Unrecognized section name : '%s;\n",
+                    section);
+            exit(1);
+        }
+
+        sbe_xip_translate_header(&header, (SbeXipHeader*)io_image);
+
+        for (i = 0; i < SBE_XIP_SECTIONS; i++) {
+            xSection = &(header.iv_section[i]);
+            
+            if (strcmp(section, g_sectionNames[i]) == 0) {
+              
+                size = xSection->iv_size;
+                offset = xSection->iv_offset;
+
+                printf("%-16s 0x%08x 0x%08x (%d)\n",
+                       g_sectionNames[i], 
+                       xSection->iv_offset, xSection->iv_size, xSection->iv_size);
+                
+                break;
+            }
+        }
+
+        newImage = malloc(size);
+
+        if (newImage == 0) {
+            fprintf(stderr, "Can't malloc() a buffer for the new image\n");
+            exit(1);
+        }
+
+        memcpy(newImage, (void*)((uint64_t)io_image + offset), size);
+
+        fileFd = open(file, O_CREAT | O_WRONLY | O_TRUNC, 0755);
+        if (fileFd < 0) {
+            perror("open() of the fixed section : ");
+            exit(1);
+        }
+
+        rc = write(fileFd, newImage, size);
+        if ((rc < 0) || ((uint32_t)rc != size)) {
+            perror("write() of fixed section : ");
+            exit(1);
+        }
+
+        rc = close(fileFd);
+        if (rc) {
+            perror("close() of fixed section : ");
+            exit(1);
+        }
+
+    } while (0);
+
+    return rc;
+
+}
+    
+
+// Delete 0 or more sections in order.  
+
+int
+deleteSection(const char* i_imageFile, const int i_imageFd, void* io_image, 
+              int i_argc, const char** i_argv)
+{
+    int newImageFd, sectionId, rc, argc;
+    const char* section;
+    const char** argv;
+    void* newImage;
+    uint32_t size;
+
+    do {
+
+        // malloc() a buffer for the new image
+
+        rc = sbe_xip_image_size(io_image, &size);
+        if (rc) break;
+
+        newImage = malloc(size);
+
+        if (newImage == 0) {
+            fprintf(stderr, "Can't malloc() a buffer for the new image\n");
+            exit(1);
+        }
+
+
+        // Copy the image. At this point the original image file must be
+        // closed.
+
+        memcpy(newImage, io_image, size);
+
+        rc = close(i_imageFd);
+        if (rc) {
+            perror("close() of the original image file failed : ");
+            exit(1);
+        }
+
+        // Delete the sections in argument order
+
+        for (argc = i_argc, argv = i_argv; argc != 0; argc--, argv++) {
+
+            // Translate the section name to a section Id
+
+            section = *argv;
+
+            for (sectionId = 0; sectionId < SBE_XIP_SECTIONS; sectionId++) {
+                if (strcmp(section, g_sectionNames[sectionId]) == 0) {
+                    break;
+                }
+            }
+            if (sectionId == SBE_XIP_SECTIONS) {
+                fprintf(stderr, "Unrecognized section name : '%s;\n",
+                        section);
+                exit(1);
+            }
+
+            // Delete the section
+
+            rc = sbe_xip_delete_section(newImage, sectionId);
+            if (rc) break;
+        }
+        if (rc) break;
+
+        // Print the final size of the new image
+    
+        rc = sbe_xip_image_size(newImage, &size);
+        if (rc) break;
+
+        printf("%u\n", size);
+
+        // Now write the new image back to the filesystem
+
+        newImageFd = open(i_imageFile, O_WRONLY | O_TRUNC);
+        if (newImageFd < 0) {
+            perror("re-open() of image file failed : ");
+            exit(1);
+        }
+
+        rc = write(newImageFd, newImage, size);
+        if ((rc < 0) || ((uint32_t)rc != size)) {
+            perror("write() of modified image failed : ");
+            exit(1);
+        }
+
+        rc = close(newImageFd);
+        if (rc) {
+            perror("close() of modified image failed : ");
+            exit(1);
+        }
+    } while (0);
+
+    return rc;
+}
+    
+
+// 'TEST' is an undocumented command provided to test the APIs.  It searches
+// and modifies a copy of the image but puts the image back together as it
+// was, then verifies that the the original image and the copy are identical.
+
+#define BOMB_IF(test)                                   \
+    if (test) {                                         \
+        fprintf(stderr, "%s:%d : Error in TEST\n",      \
+                __FILE__, __LINE__);                    \
+        exit(1);                                        \
+    }
+
+#define BOMB_IF_RC                                              \
+    if (rc) {                                                   \
+        fprintf(stderr, "%s:%d : Error in TEST, rc = %s\n",     \
+                __FILE__, __LINE__,                             \
+                SBE_XIP_ERROR_STRING(g_errorStrings, rc));      \
+        exit(1);                                                \
+    }
+
+
+int
+TEST(void* io_image, const int i_argc, const char** i_argv)
+{
+    int rc;
+    uint64_t linkAddress, entryPoint, data, data1, magicKey, entry_offset[2];
+    char *key, *revision, *revdup, *longString, *shortString;
+    void *originalImage, *deleteAppendImage;
+    uint32_t imageSize;
+    SbeXipItem item;
+    SbeXipHeader header;
+    SbeXipSection section;
+    //ProcSbeFixed* fixed;
+    uint32_t tocSize;
+
+    do {
+        rc = sbe_xip_image_size(io_image, &imageSize);
+        BOMB_IF_RC;
+        originalImage = malloc(imageSize);
+        BOMB_IF(originalImage == 0);
+        memcpy(originalImage, io_image, imageSize);
+        
+        rc = sbe_xip_get_scalar(io_image, "toc_sorted", &data);
+        BOMB_IF_RC;
+        BOMB_IF(data != 1);
+
+        rc = sbe_xip_get_scalar(io_image, "image_size", &data);
+        BOMB_IF_RC;
+        BOMB_IF(data != (uint64_t)g_imageSize);
+
+        rc = sbe_xip_get_scalar(io_image, "magic", &magicKey);
+        BOMB_IF_RC;
+
+        switch (magicKey) {
+        case SBE_BASE_MAGIC:
+            key = (char*)"proc_sbe_fabricinit_revision";
+            rc = sbe_xip_get_string(io_image, key, &revision);
+            BOMB_IF_RC;
+            BOMB_IF(strncmp(revision, "1.", 2) != 0);
+            break;
+        case SBE_SEEPROM_MAGIC:
+            key = (char*)"";
+            // Can't do this test here as the TOC has been stripped
+            break;
+        case SBE_CENTAUR_MAGIC:
+            key = (char*)"cen_sbe_initf_revision";
+            rc = sbe_xip_get_string(io_image, key, &revision);
+            BOMB_IF_RC;
+            BOMB_IF(strncmp(revision, "1.", 2) != 0);
+            break;
+        default:
+            BOMB_IF(1);
+            break;
+        }
+
+        rc = sbe_xip_get_scalar(io_image, "link_address", &linkAddress);
+        BOMB_IF_RC;
+        if (magicKey != SBE_SEEPROM_MAGIC) {
+            rc = sbe_xip_get_scalar(io_image, "entry_point", &entryPoint);
+            BOMB_IF_RC;
+        }
+        rc = sbe_xip_get_scalar(io_image, "entry_offset", &data);
+        BOMB_IF_RC;
+        BOMB_IF((magicKey != SBE_SEEPROM_MAGIC) && (entryPoint != (linkAddress + data)));
+
+        rc = 
+            sbe_xip_set_scalar(io_image, "toc_sorted", 0) ||
+            sbe_xip_set_scalar(io_image, "image_size", 0);
+        BOMB_IF_RC;
+
+        data = 0;
+        data += (rc = sbe_xip_get_scalar(io_image, "toc_sorted", &data), data);
+        BOMB_IF_RC;
+        data += (rc = sbe_xip_get_scalar(io_image, "image_size", &data), data);
+        BOMB_IF_RC;
+        BOMB_IF(data != 0);
+
+        // Write back keys found during read check.
+
+        rc = 
+            sbe_xip_set_scalar(io_image, "toc_sorted", 1) ||
+            sbe_xip_set_scalar(io_image, "image_size", g_imageSize);
+        BOMB_IF_RC;
+
+        // We'll rewrite the revision keyword with a long string and a short
+        // string, and verify that rewriting is being done correctly.  In the
+        // end we copy the original revision string back in, which is safe
+        // because the memory allocation for strings does not change when they
+        // are modified.
+
+        revdup = strdup(revision);
+        longString = (char*)"A very long string";
+        shortString = (char*)"?";
+
+        if (magicKey != SBE_SEEPROM_MAGIC) {
+            rc = 
+                sbe_xip_set_string(io_image, key, longString) ||
+                sbe_xip_get_string(io_image, key, &revision);
+            BOMB_IF_RC;
+            BOMB_IF((strlen(revision) != strlen(revdup)) ||
+                    (strncmp(revision, longString, strlen(revdup)) != 0));
+
+            rc = 
+                sbe_xip_set_string(io_image, key, shortString) ||
+                sbe_xip_get_string(io_image, key, &revision);
+            BOMB_IF_RC;
+            BOMB_IF(strcmp(revision, shortString) != 0);
+
+            memcpy(revision, revdup, strlen(revdup) + 1);
+        }
+
+        // Use sbe_xip_[read,write]_uint64 to modify the image and restore it
+        // to its original form.
+
+        rc = sbe_xip_find(io_image, "entry_offset", &item);
+        BOMB_IF_RC;
+        rc = sbe_xip_get_scalar(io_image, "entry_offset", &(entry_offset[0]));
+        BOMB_IF_RC;
+
+        rc = sbe_xip_read_uint64(io_image, item.iv_address, &(entry_offset[1]));
+        BOMB_IF_RC;
+        BOMB_IF(entry_offset[0] != entry_offset[1]);
+
+        rc = sbe_xip_write_uint64(io_image, item.iv_address, 
+                                  0xdeadbeefdeadc0deull);
+        BOMB_IF_RC;
+        rc = sbe_xip_read_uint64(io_image, item.iv_address, &(entry_offset[1]));
+        BOMB_IF_RC;
+        BOMB_IF(entry_offset[1] != 0xdeadbeefdeadc0deull);
+
+        rc = sbe_xip_write_uint64(io_image, item.iv_address, entry_offset[0]);
+        BOMB_IF_RC;
+
+        // Try sbe_xip_get_section against the translated header
+
+        sbe_xip_translate_header(&header, (SbeXipHeader*)io_image);
+        rc = sbe_xip_get_section(io_image, SBE_XIP_SECTION_TOC, &section);
+        BOMB_IF_RC;
+        BOMB_IF((section.iv_size != 
+                 header.iv_section[SBE_XIP_SECTION_TOC].iv_size));
+
+
+        // Make sure the .fixed section access compiles and seems to
+        // work. Modify an entry via the .fixed and verify it with normal TOC
+        // access. 
+
+        if (magicKey == SBE_SEEPROM_MAGIC) {
+
+            BOMB_IF(0 != 0);
+
+            exit(1);
+
+            rc = sbe_xip_get_scalar(io_image, "proc_sbe_ex_dpll_initf_control",
+                                    &data);
+            BOMB_IF_RC;
+            //fixed = 
+            //(ProcSbeFixed*)((unsigned long)io_image + SBE_XIP_FIXED_OFFSET);
+            //fixed->proc_sbe_ex_dpll_initf_control = 0xdeadbeefdeadc0deull;
+            rc = sbe_xip_get_scalar(io_image, "proc_sbe_ex_dpll_initf_control",
+                                    &data1);
+            BOMB_IF_RC;
+#ifdef _BIG_ENDIAN
+            BOMB_IF(data1 != 0xdeadbeefdeadc0deull);
+#else
+            BOMB_IF(data1 != 0xdec0addeefbeaddeull);
+#endif
+            rc = sbe_xip_set_scalar(io_image, "proc_sbe_ex_dpll_initf_control",
+                                    data);
+            BOMB_IF_RC;
+        }
+
+        // Temporarily "delete" the .toc section and try to get/set via the
+        // mini-TOC for .fixed, and make sure that we can't get things that
+        // are not in the mini-toc.
+
+        tocSize = 
+            ((SbeXipHeader*)io_image)->iv_section[SBE_XIP_SECTION_TOC].iv_size;
+
+        ((SbeXipHeader*)io_image)->iv_section[SBE_XIP_SECTION_TOC].iv_size = 
+            0;
+
+        rc = sbe_xip_get_scalar(io_image, "proc_sbe_ex_dpll_initf_control",
+                                &data);
+        rc = sbe_xip_set_scalar(io_image, "proc_sbe_ex_dpll_initf_control",
+                                0xdeadbeef);
+        rc = sbe_xip_get_scalar(io_image, "proc_sbe_ex_dpll_initf_control",
+                                &data1);
+        BOMB_IF(data1 != 0xdeadbeef);
+        rc = sbe_xip_set_scalar(io_image, "proc_sbe_ex_dpll_initf_control",
+                                data);
+        BOMB_IF_RC;
+
+        BOMB_IF(sbe_xip_find(io_image, "proc_sbe_ex_dpll_initf", 0) !=
+                SBE_XIP_ITEM_NOT_FOUND);
+
+        ((SbeXipHeader*)io_image)->iv_section[SBE_XIP_SECTION_TOC].iv_size = 
+            tocSize;
+
+        if (magicKey != SBE_SEEPROM_MAGIC) {
+            BOMB_IF(sbe_xip_find(io_image, "proc_sbe_ex_dpll_initf", 0) != 0);
+        }
+
+
+#ifdef DEBUG_SBE_XIP_IMAGE
+        printf("\nYou will see an expected warning below "
+               "about SBE_XIP_WOULD_OVERFLOW\n"
+               "It means the TEST is working (not failing)\n\n");
+#endif
+
+        // Finally compare against the original
+
+        BOMB_IF(memcmp(io_image, originalImage, imageSize));
+
+    } while (0);
+
+    return rc;
+}
+
+
+/// Function:  pairRingNameAndAddr()  to be used w/sbe_xip_map_toc()
+///
+/// Brief:  Looks for address match for both base and override rings and
+///         for multi-chiplet rings. Returns the ring name and other good
+///         stuff in the PairingInfo structure upon a match. 
+/// 
+/// \param[in] i_image  A pointer to an SBE-XIP image in host memory. 
+///
+/// \param[in] i_item  A pointer to the "next" SbeXipItem in the TOC.
+///
+/// \param[io] io_pairing   A pointer to the structure, PairingInfo.
+///
+/// Assumptions:
+/// - On input, io_pairing contains 
+///   - address = the backPtr of the next ring block,
+///   - vectorpos = the next vector position, starting from 0,1,2,..,31 and
+///                 which includes possible override pos.
+/// - The TOC is then traversed and each TOC entry is put into i_item.
+/// - The backPtr in io_pairing is kept constant until TOC has been exhausted.
+/// - On output, io_pairing contains
+///   - name = TOC name
+///   - isvpd = whether it's a VPD or non-VPD ring
+///   - overridable = whether it's an overridable ring
+///   - override = whether it's a base or an override ring
+/// - In general, we don't know if a ring is a base or an override of if it is a 
+///   multi-chiplet type.  Thus, we first look for a match to the vector in
+///   in position zero, then we try position one, then position two, ..., and up
+///   to a max of position 31 (which would be an override for ex chiplet 0x1F).
+/// 
+static int pairRingNameAndAddr( void *i_image, const SbeXipItem *i_item, void *io_pairing)
+{
+  int rc=0,rcLoc=-1;
+  SbeXipItem tocItem;
+	PairingInfo *pairingInfo;
+	RingIdList  *ringIdList;
+  
+  SBE_XIP_ERROR_STRINGS(g_errorStrings);
+
+  rcLoc = sbe_xip_find( i_image, i_item->iv_id, &tocItem);
+  if (rcLoc)  {
+    fprintf( stderr, "sbe_xip_find() failed : %s\n", SBE_XIP_ERROR_STRING(g_errorStrings, rcLoc));
+    rc = DIS_RING_NAME_ADDR_MATCH_FAILURE;
+  }
+  else  {
+		pairingInfo = (PairingInfo*)io_pairing;
+		// Do a sanity check.
+		if (pairingInfo->vectorpos>31)  {
+    	fprintf( stderr, "vectorpos (=%i) must be between [0;31]\n",pairingInfo->vectorpos);
+    	rc = DIS_RING_NAME_ADDR_MATCH_FAILURE;
+		}
+    // Check for match.
+    // - vectorpos is passed in such that first we look for base match, then for override
+		//   or chiplet range match.
+    if (tocItem.iv_address == pairingInfo->address-8*pairingInfo->vectorpos &&
+        tocItem.iv_id!=NULL  )  {
+      pairingInfo->name = tocItem.iv_id;
+			rcLoc = get_vpd_ring_list_entry(pairingInfo->name,0,&ringIdList);
+			if (!rcLoc)  {
+				// It is a VPD ring...and they never have overrides.
+				pairingInfo->isvpd = 1;
+				pairingInfo->overridable = 0;
+			}
+			else  {
+				// It is a non-VPD ring...and they all have override capability.
+				pairingInfo->isvpd = 0;
+				pairingInfo->overridable = 1;
+			}
+      if (pairingInfo->vectorpos==0)
+			  // This can only be a base match.
+				pairingInfo->override = 0;
+      else  {
+				// This is not a base match. Investigating further if override. (Note,
+				//   this includes a multi-dim vector with multi-dim override.)
+				if (pairingInfo->overridable && 
+						2*(pairingInfo->vectorpos/2)!=pairingInfo->vectorpos)
+					pairingInfo->override = 1;
+				else
+					pairingInfo->override = 0;
+			}
+    	rc = DIS_RING_NAME_ADDR_MATCH_SUCCESS;
+		}
+  }
+  return rc;
+}
+
+// this function is just defined out, because there is a future need.
+#ifdef BLUBBER
+/// Function:  disassembleSection
+///
+/// Brief:  Disassembles a section and returns a pointer to a buffer that 
+///         contains the listing.
+/// 
+/// \param[in] i_image  A pointer to an SBE-XIP image in host memory. 
+///
+/// \param[in] i_argc  Additional number of arguments beyond "dis" keyword.
+///
+/// \param[in] i_argv  Additional arguments beyond "dis" keyword.
+///
+/// Assumptions: 
+/// 
+int disassembleSection(void         *i_image, 
+                       int          i_argc, 
+                       const char   **i_argv)
+{
+    int rc=0, rcSet=0;
+    uint32_t  rcCount=0;
+    char      *disList=NULL;
+    uint32_t  sizeSection=0, nextLinkOffsetBlock=0;
+    uint32_t  sizeBlock=0, sizeData=0, sizeCode=0, sizeData2=0;
+    uint32_t  sizeDisLine=0, sizeList=0, sizeListMax=0;
+    uint32_t  offsetCode=0;
+    uint8_t   typeRingsSection=0;  // 0: RS4  1: Wiggle-Flip
+    uint8_t   bSummary=0, bFoundInToc=0;
+    uint32_t  sectionId;
+    uint64_t  backPtr=0, fwdPtr=0;
+    PairingInfo pairingInfo;
+    const char *sectionName;
+	char      *ringName;
+	uint32_t  ringSeqNo=0; // Ring sequence location counter.
+	uint8_t   vectorPos,overRidable;
+    void *nextBlock, *nextSection;
+    SbeXipHeader hostHeader;
+    SbeXipSection hostSection;
+    ImageInlineContext ctx;
+    ImageInlineDisassembly dis;
+    char lineDis[LISTING_STRING_SIZE];
+    void      *hostRs4Container;
+    uint32_t  compressedBits=0, ringLength=0;
+    double    compressionPct=0;
+
+    if (i_argc != 1) {
+        fprintf(stderr, g_usage);
+        exit(1);
+    }
+    sectionName = i_argv[0];
+
+    // Determine SBE-XIP section ID from the section name, e.g.
+    //         .loader_text =>  SBE_XIP_SECTION_LOADER_TEXT
+    //         .text     =>  SBE_XIP_SECTION_TEXT
+    //         .rings    =>  SBE_XIP_SECTION_RINGS
+    if (strcmp(sectionName, ".header")==0)
+        sectionId = SBE_XIP_SECTION_HEADER;
+    else
+        if (strcmp(sectionName, ".fixed")==0)
+            sectionId = SBE_XIP_SECTION_FIXED;
+        else
+            if (strcmp(sectionName, ".fixed_toc")==0)
+                sectionId = SBE_XIP_SECTION_FIXED_TOC;
+            else
+                if (strcmp(sectionName, ".loader_text")==0)
+                    sectionId = SBE_XIP_SECTION_LOADER_TEXT;
+                else
+                    if (strcmp(sectionName, ".loader_data")==0)
+                        sectionId = SBE_XIP_SECTION_LOADER_DATA;
+                    else
+                        if (strcmp(sectionName, ".text")==0)
+                            sectionId = SBE_XIP_SECTION_TEXT;
+                        else
+                            if (strcmp(sectionName, ".data")==0)
+                                sectionId = SBE_XIP_SECTION_DATA;
+                            else
+                                if (strcmp(sectionName, ".toc")==0)
+                                    sectionId = SBE_XIP_SECTION_TOC;
+                                else
+                                    if (strcmp(sectionName, ".strings")==0)
+                                        sectionId = SBE_XIP_SECTION_STRINGS;
+                                    else
+                                        if (strcmp(sectionName, ".base")==0)
+                                            sectionId = SBE_XIP_SECTION_BASE;
+                                        else
+                                            if (strcmp(sectionName, ".baseloader")==0)
+                                                sectionId = SBE_XIP_SECTION_BASELOADER;
+                                            else
+                                                if (strcmp(sectionName, ".rings")==0)
+                                                    sectionId = SBE_XIP_SECTION_RINGS;
+                                                else
+                                                    if (strcmp(sectionName, ".rings_summary")==0)  {
+                                                        sectionId = SBE_XIP_SECTION_RINGS;
+                                                        bSummary = 1;
+                                                    }
+                                                    else
+                                                        if (strcmp(sectionName, ".overlays")==0)
+                                                            sectionId = SBE_XIP_SECTION_OVERLAYS;
+                                                        else  {
+                                                            fprintf(stderr,"ERROR : %s is an invalid section name.\n",sectionName);
+                                                            fprintf(stderr,"Valid <section> names for the 'dis' function are:\n");
+                                                            fprintf(stderr,"\t.header\n");
+                                                            fprintf(stderr,"\t.fixed\n");
+                                                            fprintf(stderr,"\t.fixed_toc\n");
+                                                            fprintf(stderr,"\t.loader_text\n");
+                                                            fprintf(stderr,"\t.loader_data\n");
+                                                            fprintf(stderr,"\t.text\n");
+                                                            fprintf(stderr,"\t.data\n");
+                                                            fprintf(stderr,"\t.toc\n");
+                                                            fprintf(stderr,"\t.strings\n");
+                                                            fprintf(stderr,"\t.base\n");
+                                                            fprintf(stderr,"\t.baseloader\n");
+                                                            fprintf(stderr,"\t.overlays\n");
+                                                            fprintf(stderr,"\t.rings\n");
+                                                            fprintf(stderr,"\t.rings_summary\n");
+                                                            exit(1);
+                                                        }
+
+    // Get host header and section pointer.
+    //
+    sbe_xip_translate_header( &hostHeader, (SbeXipHeader*)i_image);
+    rc = sbe_xip_get_section( i_image, sectionId, &hostSection);
+    if (rc)  {
+        fprintf( stderr, "sbe_xip_get_section() failed : %s\n", SBE_XIP_ERROR_STRING(g_errorStrings, rc));
+        return SBE_XIP_DISASSEMBLER_ERROR;
+    }
+    sizeSection = hostSection.iv_size;
+    nextBlock = (void*)(hostSection.iv_offset + (uintptr_t)i_image);
+    nextSection = (void*)((uint64_t)nextBlock + (uint64_t)sizeSection);
+  
+    // Relocatable offset of section at hand.
+    nextLinkOffsetBlock = (uint32_t)hostHeader.iv_linkAddress + hostSection.iv_offset;
+
+    // Allocate buffer to hold disassembled listing. (Start out with minimum 10k buffer size.)
+    //
+    if (sizeSection>10000)
+        sizeListMax = sizeSection; // Just to use something as an initial guess.
+    else
+        sizeListMax = 10000;
+    disList = (char*)malloc(sizeListMax);
+    if (disList==NULL) {
+        fprintf( stderr, "ERROR : malloc() failed.\n");
+        fprintf( stderr, "\tMore info: %s\n", DIS_ERROR_STRING(g_errorStringsDis, DIS_MEMORY_ERROR));
+        return SBE_XIP_DISASSEMBLER_ERROR;
+    }
+    *disList = '\0'; // Make sure the buffer is NULL terminated (though probably not needed.)
+    sizeList = 0;
+
+    // Create context and point it to image section.
+    //
+    rc = image_inline_context_create(  &ctx,
+                                       nextBlock,
+                                       sizeSection,
+                                       nextLinkOffsetBlock,
+                                       0);
+    if (rc)  {
+        fprintf( stderr, "ERROR : %s (rc=%i)\n",image_inline_error_strings[rc],rc);
+        fprintf( stderr, "\tMore info: %s\n", DIS_ERROR_STRING(g_errorStringsDis, DIS_DISASM_ERROR));
+        return SBE_XIP_DISASSEMBLER_ERROR;
+    }
+
+    while ((uint64_t)nextBlock<(uint64_t)nextSection) {
+
+        // Disassemble sections based on their types and intents.
+        //
+        if (sectionId==SBE_XIP_SECTION_RINGS || sectionId==SBE_XIP_SECTION_OVERLAYS)  {
+            // Ring section (with a mix of data and code.)
+            // ...use BaseRingLayout structure to decode each ring block.
+            offsetCode = (uint32_t)myRev64(((BaseRingLayout*)nextBlock)->entryOffset);
+            sizeBlock = myRev32(((BaseRingLayout*)nextBlock)->sizeOfThis);
+            // ...determine ring type, either RS4 or Wiggle-flip.
+            if (offsetCode-(myRev32(((BaseRingLayout*)nextBlock)->sizeOfMeta)+3)/4*4>28)  {
+                typeRingsSection = 0;  // RS4 w/32-byte header.
+                sizeData2 = sizeBlock - offsetCode - ASM_RS4_LAUNCH_BUF_SIZE;
+            }
+            else
+                typeRingsSection = 1;  // Wiggle-flip w/24-byte header.
+            // ...get the backPtr and fwdPtr and put at top of disasm listing.
+            backPtr = myRev64(((BaseRingLayout*)nextBlock)->backItemPtr);
+            sbe_xip_read_uint64(i_image,
+                                backPtr,
+                                &fwdPtr);
+      
+            // Calculate RS4 compression efficiency if RS4 rings.
+            if (typeRingsSection==0)  {
+                hostRs4Container = (void*)( (uintptr_t)nextBlock + 
+                                            offsetCode + ASM_RS4_LAUNCH_BUF_SIZE );
+                compressedBits = myRev32(((CompressedScanData*)hostRs4Container)->iv_algorithmReserved) * 4;
+                ringLength = myRev32(((CompressedScanData*)hostRs4Container)->iv_length);
+                compressionPct = (double)compressedBits / (double)ringLength * 100.0;
+			}
+      
+            //
+			//   Map over TOC or do a targeted search of FIXED_TOC to pair backPtr addr 
+			//   with ring name and override and/or vector position (i.e. multi-chiplet).
+			//
+            sbe_xip_get_section( i_image, SBE_XIP_SECTION_TOC, &hostSection);
+			if (hostSection.iv_offset)  {
+                // TOC exists.
+                pairingInfo.address = backPtr;
+				// Search for pairing. First exhaust base position (pos=0), then next, then next, ...
+				for (pairingInfo.vectorpos=0;pairingInfo.vectorpos<32;pairingInfo.vectorpos++)  {
+                    rc = sbe_xip_map_toc( i_image, pairRingNameAndAddr, (void*)(&pairingInfo));
+					if (rc)
+						break;
+				}
+                if (rc==DIS_RING_NAME_ADDR_MATCH_FAILURE)  {
+                    fprintf( stderr,"ERROR : Error associated with sbe_xip_map_toc().\n");
+                    fprintf( stderr, "\tMore info: %s\n", DIS_ERROR_STRING(g_errorStringsDis, DIS_RING_NAME_ADDR_MATCH_FAILURE));
+                    return SBE_XIP_DISASSEMBLER_ERROR;
+                }
+                ringSeqNo++;
+				if (rc==DIS_RING_NAME_ADDR_MATCH_SUCCESS)  {
+					bFoundInToc = 1;
+                    ringName = pairingInfo.name;       // The ring name matched in pairRingNameAndAddr()
+					vectorPos = pairingInfo.vectorpos; // The vector position matched in pairRingNameAndAddr()
+					overRidable = pairingInfo.overridable; // Whether the ring supports on override ring.
+                    if (pairingInfo.override)  {
+                        sizeDisLine = snprintf(lineDis,LISTING_STRING_SIZE,
+                                               "# ------------------------------\n# %i.\n# ringName = %s (override)\n# vectorPos = %i\n# overRidable = %i\n# backPtr = 0x%08x\n# fwdPtr  = 0x%08x\n# Compressed Bits  = %u\n# Ring Length Bits = %u\n# Compression      = %0.2f%%\n",
+                                               ringSeqNo, ringName,vectorPos,overRidable,(uint32_t)backPtr,(uint32_t)fwdPtr,compressedBits,ringLength,compressionPct);
+                    }
+                    else  {
+                        sizeDisLine = snprintf(lineDis,LISTING_STRING_SIZE,
+                                               "# ------------------------------\n# %i.\n# ringName = %s (base)\n# vectorPos = %i\n# overRidable = %i\n# backPtr = 0x%08x\n# fwdPtr  = 0x%08x\n# Compressed Bits  = %u\n# Ring Length Bits = %u\n# Compression      = %0.2f%%\n",
+                                               ringSeqNo,ringName,vectorPos,overRidable,(uint32_t)backPtr,(uint32_t)fwdPtr,compressedBits,ringLength,compressionPct);
+                    }
+				}
+                else  {
+                    sizeDisLine = snprintf(lineDis,LISTING_STRING_SIZE,
+                                           "# ------------------------------\n# %i.\n# ringName = Not found (but TOC's available)\n# backPtr = 0x%08x\n# fwdPtr  = 0x%08x\n",
+                                           ringSeqNo,(uint32_t)backPtr,(uint32_t)fwdPtr);
+				}
+            }
+			else  {
+                // TOC doesn't exist. First try targeted search of MVPD ring names in FIXED_TOC.
+                bFoundInToc = 0; // If we find in fixed_toc, then change to 1.
+				// 2012-11-13: CMO TBD. Try using pairRingNameAndAddr by enabling a sequential 
+			    //             traversing of each of the MVPD lists inside that function. You'll
+                //             need to call pairRing manually from right here (or from a
+                //             sbe_xip_search_fixed_toc()-like function). Maybe you can add a
+				//             4th arg to pairRing that is zero by default, meaning it is to be
+				//             used by xip_map_toc(). But if non-zero, it is to be used in a
+				//             traversing manner. Or you could add another member to the
+                //             PairingInfo struct to indirectly pass this info to the function.
+				//             You'd also need to pass two more arguments to get_vpd_ring_list_
+                //             entry() to indicate sequence number and the MVPD keyword.
+                // rc = pairRingNameAndAddr();
+				// if (rc==DIS_RING_NAME_ADDR_MATCH_SUCCESS)  {
+                //   bFoundInToc = 1;
+                // // Do same as in TOC section above.
+                //   break;
+                // }
+                // // OK, so ring name wasn't in TOC nor in FIXED_TOC. That happens if the ring
+                // //   is a non-Mvpd ring and the TOC has been removed, such as in an IPL or
+                // //   Seeprom image.
+                ringSeqNo++;
+                if (typeRingsSection==0)  {
+                    // RS4 header, which has override info
+                    if (((Rs4RingLayout*)nextBlock)->override==0)  {
+                        sizeDisLine = snprintf(lineDis,LISTING_STRING_SIZE,
+                                               "# ------------------------------\n# %i.\n# ringName = Not available (base)\n# backPtr = 0x%08x\n# fwdPtr  = 0x%08x\n# Compressed Bits  = %u\n# Ring Length Bits = %u\n# Compression      = %0.2f%%\n",
+                                               ringSeqNo,(uint32_t)backPtr,(uint32_t)fwdPtr,compressedBits,ringLength,compressionPct);
+                    }
+					else  {
+                        sizeDisLine = snprintf(lineDis,LISTING_STRING_SIZE,
+                                               "# ------------------------------\n# %i.\n# ringName = Not available (override)\n# backPtr = 0x%08x\n# fwdPtr  = 0x%08x\n# Compressed Bits  = %u\n# Ring Length Bits = %u\n# Compression      = %0.2f%%\n",
+                                               ringSeqNo,(uint32_t)backPtr,(uint32_t)fwdPtr,compressedBits,ringLength,compressionPct);
+					}
+                }
+				else  {
+                    // WF header, which doesn't have override info
+                    sizeDisLine = snprintf(lineDis,LISTING_STRING_SIZE,
+                                           "# ------------------------------\n# %i.\n# ringName and override = Not available\n# backPtr = 0x%08x\n# fwdPtr  = 0x%08x\n",
+                                           ringSeqNo,(uint32_t)backPtr,(uint32_t)fwdPtr);
+				}
+            }
+            sizeList = sizeList + sizeDisLine;
+            disList = strcat(disList,lineDis);
+		}
+        else  if (  sectionId==SBE_XIP_SECTION_LOADER_TEXT || 
+                    sectionId==SBE_XIP_SECTION_TEXT)  {
+            // Sections that have only code.
+            offsetCode = 0;
+            sizeBlock = sizeSection;
+        }
+        else  {
+            // Sections that have only data.
+            offsetCode = sizeSection;
+            sizeBlock = sizeSection;
+        }
+        sizeData = offsetCode;
+        sizeCode = sizeBlock - offsetCode - sizeData2;
+
+        if (sectionId==SBE_XIP_SECTION_RINGS && bSummary)  {  
+            //
+            // Summarize rings section.
+
+            if (typeRingsSection==0)  {  // RS4 header.
+                sizeDisLine = snprintf(lineDis,LISTING_STRING_SIZE,
+                                       "# ddLevel = 0x%02x\n# override= %i\n# sysPhase= %i\n# Block size= %i\n",
+                                       myRev32(((Rs4RingLayout*)nextBlock)->ddLevel),
+                                       ((Rs4RingLayout*)nextBlock)->override,
+                                       ((Rs4RingLayout*)nextBlock)->sysPhase,
+                                       sizeBlock);
+            }
+            else  {                      // WF header.
+				if (bFoundInToc)  {
+                    sizeDisLine = snprintf(lineDis,LISTING_STRING_SIZE,
+                                           "# override= %i\n# Block size= %i\n",
+                                           pairingInfo.override, sizeBlock);
+				}
+				else  {
+                    sizeDisLine = snprintf(lineDis,LISTING_STRING_SIZE,
+                                           "# override= Not available\n# Block size= %i\n",
+                                           sizeBlock);
+				}
+            }
+            sizeList = sizeList + sizeDisLine;
+            disList = strcat(disList,lineDis);
+            // Readjust list buffer size, if needed.
+            if (sizeList > sizeListMax-1000)  {
+                sizeListMax = 2*sizeListMax;
+                disList = (char*)realloc( (void*)(disList), sizeListMax);
+            }
+    
+        }
+        else  {  
+            //
+            // Do disassembly.
+    
+            // ...data disassembly
+            if (sizeData>0)  {
+                ctx.options = IMAGE_INLINE_LISTING_MODE | IMAGE_INLINE_DISASSEMBLE_DATA;
+                do  {
+                    rc = image_inline_disassemble( &ctx, &dis);
+                    sizeDisLine = snprintf(lineDis,LISTING_STRING_SIZE,"%s\n",dis.s);
+                    sizeList = sizeList + sizeDisLine;
+                    disList = strcat(disList,lineDis);
+                    if (rc)  {
+                        rcSet = rcSet | 0x1;
+                        sizeDisLine = snprintf(lineDis,LISTING_STRING_SIZE,
+                                               "WARNING: %s (rc=%i) -> Stopping disasm. Check code and sectionID=%i.\n",
+                                               image_inline_error_strings[rc],rc,sectionId);
+                        sizeList = sizeList + sizeDisLine;
+                        disList = strcat(disList,lineDis);
+                    }
+                    // Readjust list buffer size, if needed.
+                    if (sizeList > sizeListMax-1000)  {
+                        sizeListMax = 2*sizeListMax;
+                        disList = (char*)realloc( (void*)(disList), sizeListMax);
+                    }
+                } while (rc==0 && ctx.lc<nextLinkOffsetBlock+sizeData);
+            }
+            if (rcSet)
+                rc = 0;
+      
+            // ...code disassembly
+            if (sizeCode>0)  {
+                ctx.options = IMAGE_INLINE_LISTING_MODE;
+                do  {
+                    rc = image_inline_disassemble( &ctx, &dis);
+                    ctx.options = IMAGE_INLINE_LISTING_MODE;
+                    sizeDisLine = snprintf(lineDis,LISTING_STRING_SIZE,"%s\n",dis.s);
+                    sizeList = sizeList + sizeDisLine;
+                    disList = strcat(disList,lineDis);
+                    if (rc && rcCount<100)  {
+                        rcSet = rcSet | 0x2;
+                        rcCount++;
+                        if (sectionId==SBE_XIP_SECTION_RINGS)  {
+                            sizeDisLine = snprintf(lineDis,LISTING_STRING_SIZE,
+                                                   "WARNING: %s (rc=%i) -> Trying data disasm mode. Check code, xyzRingLayout structures and image section.\n",
+                                                   image_inline_error_strings[rc],rc);
+                        }
+                        else  {
+                            sizeDisLine = snprintf(lineDis,LISTING_STRING_SIZE,
+                                                   "WARNING: %s (rc=%i) -> Trying data disasm mode.\n",
+                                                   image_inline_error_strings[rc],rc);
+                        }
+                        sizeList = sizeList + sizeDisLine;
+                        disList = strcat(disList,lineDis);
+                        ctx.options = IMAGE_INLINE_LISTING_MODE | IMAGE_INLINE_DISASSEMBLE_DATA;
+                        rc = 0;
+                    }
+                    else  {
+                        if (rc && rcCount>=1000)  {
+                            fprintf(stderr, "Too many disasm warnings. Check output listing.\n");
+                            fprintf( stderr, "\tMore info: %s\n", DIS_ERROR_STRING(g_errorStringsDis, DIS_TOO_MANY_DISASM_WARNINGS));
+                            return SBE_XIP_DISASSEMBLER_ERROR;
+                        }
+                    }
+                    // Readjust list buffer size, if needed.
+                    if (sizeList > sizeListMax-1000)  {
+                        sizeListMax = 2*sizeListMax;
+                        disList = (char*)realloc( (void*)(disList), sizeListMax);
+                    }
+                } while (rc==0 && ctx.lc<nextLinkOffsetBlock+sizeData+sizeCode);
+            }
+            if (rcSet)
+                rc = 0;
+        
+            // ...data2 disassembly (only done for rings section if RS4 type.)
+            if (sizeData2>0)  {
+                ctx.options = IMAGE_INLINE_LISTING_MODE | IMAGE_INLINE_DISASSEMBLE_DATA;
+                do  {
+                    rc = image_inline_disassemble( &ctx, &dis);
+                    sizeDisLine = snprintf(lineDis,LISTING_STRING_SIZE,"%s\n",dis.s);
+                    sizeList = sizeList + sizeDisLine;
+                    disList = strcat(disList,lineDis);
+                    if (rc)  {
+                        rcSet = rcSet | 0x4;
+                        sizeDisLine = snprintf(lineDis,LISTING_STRING_SIZE,
+                                               "WARNING: %s (rc=%i) -> Stopping disasm. Check code and sectionID=%i.\n",
+                                               image_inline_error_strings[rc],rc,sectionId);
+                        sizeList = sizeList + sizeDisLine;
+                        disList = strcat(disList,lineDis);
+                    }
+                    // Readjust list buffer size, if needed.
+                    if (sizeList > sizeListMax-1000)  {
+                        sizeListMax = 2*sizeListMax;
+                        disList = (char*)realloc( (void*)(disList), sizeListMax);
+                    }
+                } while (rc==0 && ctx.lc<nextLinkOffsetBlock+sizeBlock);
+            }
+            if (rcSet)
+                rc = 0;
+      
+        }  // End of if (bSummary) condition.
+
+        nextBlock = (void*)((uint64_t)nextBlock + (uint64_t)sizeBlock);
+        nextLinkOffsetBlock = nextLinkOffsetBlock + sizeBlock;
+
+    }  // End of while(nextBlock...) loop.
+
+    // Adjust final buffer size, add 1 for NULL char and print it.
+    if (disList)  {
+        disList = (char*)realloc( (void*)(disList), sizeList+1);
+        fprintf(stdout,"%s\n",disList);
+        free(disList);
+    }
+  
+    if (rcSet)
+        fprintf( stderr, "INFO : There were some hickups: %s\n", DIS_ERROR_STRING(g_errorStringsDis, DIS_DISASM_TROUBLES));
+
+    return 0;
+
+}
+#endif
+
+// open() and mmap() the file 
+
+void
+openAndMap(const char* i_fileName, int i_writable, int* o_fd, void** o_image, const uint32_t i_maskIgnores)
+{
+    int rc, openMode, mmapProt, mmapShared;
+    struct stat buf;
+
+    if (i_writable) {
+        openMode = O_RDWR;
+        mmapProt = PROT_READ | PROT_WRITE;
+        mmapShared = MAP_SHARED;
+    } else {
+        openMode = O_RDONLY;
+        mmapProt = PROT_READ;
+        mmapShared = MAP_PRIVATE;
+    }
+
+    *o_fd = open(i_fileName, openMode);
+    if (*o_fd < 0) {
+        perror("open() of the image failed : ");
+        exit(1);
+    }
+
+    rc = fstat(*o_fd, &buf);
+    if (rc) {
+        perror("fstat() of the image failed : ");
+        exit(1);
+    }
+    g_imageSize = buf.st_size;
+
+    *o_image = mmap(0, g_imageSize, mmapProt, mmapShared, *o_fd, 0);
+    if (*o_image == MAP_FAILED) {
+        perror("mmap() of the image failed : ");
+        exit(1);
+    }
+
+    if ( !(i_maskIgnores & SBE_XIP_IGNORE_ALL) )  {
+        rc = sbe_xip_validate2(*o_image, g_imageSize, i_maskIgnores);
+        if (rc) {
+            fprintf(stderr, "sbe_xip_validate2() failed : %s\n",
+                    SBE_XIP_ERROR_STRING(g_errorStrings, rc)); 
+            exit(1);
+        }
+    }
+
+}
+
+
+static inline void
+openAndMapWritable(const char* i_imageFile, int* o_fd, void** o_image, const uint32_t i_maskIgnores)
+{
+    openAndMap(i_imageFile, 1, o_fd, o_image, i_maskIgnores);
+}
+
+
+static inline void
+openAndMapReadOnly(const char* i_imageFile, int* o_fd, void** o_image, const uint32_t i_maskIgnores)
+{
+    openAndMap(i_imageFile, 0, o_fd, o_image, i_maskIgnores);
+}
+
+
+// Parse and execute a pre-tokenized command
+
+void
+command(const char* i_imageFile, const int i_argc, const char** i_argv, const uint32_t i_maskIgnores)
+{
+    void* image;
+    int fd, rc = 0;
+
+    if (strcmp(i_argv[0], "normalize") == 0) {
+
+        openAndMapWritable(i_imageFile, &fd, &image, i_maskIgnores);
+        rc = normalize(image, i_argc - 1, &(i_argv[1]), i_maskIgnores);
+
+    } else if (strcmp(i_argv[0], "set") == 0) {
+
+        openAndMapWritable(i_imageFile, &fd, &image, i_maskIgnores);
+        rc = set(image, i_argc - 1, &(i_argv[1]), 0);
+
+    } else if (strcmp(i_argv[0], "setv") == 0) {
+
+        openAndMapWritable(i_imageFile, &fd, &image, i_maskIgnores);
+        rc = set(image, i_argc - 1, &(i_argv[1]), 1);
+
+    } else if (strcmp(i_argv[0], "get") == 0) {
+
+        openAndMapReadOnly(i_imageFile, &fd, &image, i_maskIgnores);
+        rc = get(image, i_argc - 1, &(i_argv[1]), 0);
+
+    } else if (strcmp(i_argv[0], "getv") == 0) {
+
+        openAndMapReadOnly(i_imageFile, &fd, &image, i_maskIgnores);
+        rc = get(image, i_argc - 1, &(i_argv[1]), 1);
+
+    } else if (strcmp(i_argv[0], "report") == 0) {
+
+        openAndMapReadOnly(i_imageFile, &fd, &image, i_maskIgnores);
+        rc = report(image, i_argc - 1, &(i_argv[1]));
+
+    } else if (strcmp(i_argv[0], "append") == 0) {
+
+        openAndMapWritable(i_imageFile, &fd, &image, i_maskIgnores);
+        rc = append(i_imageFile, fd, image, i_argc - 1, &(i_argv[1]));
+
+    } else if (strcmp(i_argv[0], "extract") == 0) {
+
+        openAndMapWritable(i_imageFile, &fd, &image, i_maskIgnores);
+        rc = extract(i_imageFile, fd, image, i_argc - 1, &(i_argv[1]));
+
+    } else if (strcmp(i_argv[0], "delete") == 0) {
+
+        openAndMapWritable(i_imageFile, &fd, &image, i_maskIgnores);
+        rc = deleteSection(i_imageFile, fd, image, i_argc - 1, 
+                           &(i_argv[1]));
+
+    } else if (strcmp(i_argv[0], "dis") == 0) {
+
+        //openAndMapReadOnly(i_imageFile, &fd, &image, i_maskIgnores);
+        //rc = disassembleSection(image, i_argc - 1, &(i_argv[1]));
+        fprintf(stderr, "not supported\n"); 
+        exit(1);
+
+
+    } else if (strcmp(i_argv[0], "TEST") == 0) {
+
+        openAndMapWritable(i_imageFile, &fd, &image, i_maskIgnores);
+        rc = TEST(image, i_argc - 1, &(i_argv[1]));
+
+    } else {
+        fprintf(stderr, g_usage);
+        exit(1);
+    }
+    if (rc) {
+        fprintf(stderr, "Command failed : %s\n",
+                SBE_XIP_ERROR_STRING(g_errorStrings, rc)); 
+        exit(1);
+    }
+}
+
+
+// Open, map and validate the image, then parse and execute the command.  The
+// image is memory-mapped read/write, i.e, it may be modified in-place.
+// Commands that modify the size of the image will close and recreate the
+// file.
+
+int
+main(int argc, const char** argv)
+{
+    uint8_t   argcMin, idxArgvFlagsStart;
+    uint8_t   numFlags=0, idxArgv, bMoreFlags;
+    uint32_t  maskIgnores=0;
+
+    argcMin = 3;
+    idxArgvFlagsStart = argcMin - 1; // -i flags must start after image file name.
+
+    numFlags = 0;
+    bMoreFlags = 1;
+    do  {
+      idxArgv = idxArgvFlagsStart + numFlags;
+      if (idxArgv <= (argc-1))  {
+        if (strncmp(argv[idxArgv], "-i", 1) == 0)  {
+          numFlags++;
+          bMoreFlags = 1;
+          if (strncmp(argv[idxArgv], "-ifs", 4) == 0)  {
+              maskIgnores = maskIgnores | SBE_XIP_IGNORE_FILE_SIZE;
+          }
+          else
+          if (strncmp(argv[idxArgv], "-iv", 3) == 0)  {
+              maskIgnores = maskIgnores | SBE_XIP_IGNORE_ALL;
+          }
+          else  {
+            fprintf(stderr, g_usage);
+            fprintf(stderr, "\n");
+            fprintf(stderr,"argv[%i]=%s is an unsupported flag.",idxArgv,argv[idxArgv]);
+            fprintf(stderr,"See top of above help menu for supported flags.\n");
+            exit(1);
+          }
+        }
+        else
+          bMoreFlags = 0;
+      }
+      else  {
+        bMoreFlags = 0;
+        break;
+      }
+    }  while (bMoreFlags);
+
+    if ((argc < (argcMin+numFlags)) ||
+        (strncmp(argv[1], "-h", 2) == 0) ||
+        (strncmp(argv[1], "--h", 3) == 0) )  {
+      fprintf(stderr, g_usage);
+      exit(1);
+    }
+
+    command(argv[1], argc - idxArgv, &(argv[idxArgv]), maskIgnores);
+				
+    return 0;
+}
diff --git a/src/ppe/tools/scripts/parseErrorInfo.pl b/src/ppe/tools/scripts/parseErrorInfo.pl
new file mode 100755
index 0000000..1211940
--- /dev/null
+++ b/src/ppe/tools/scripts/parseErrorInfo.pl
@@ -0,0 +1,1511 @@
+#!/usr/bin/perl
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ppe/tools/scripts/parseErrorInfo.pl $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2011,2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+# $Id: fapiParseErrorInfo.pl,v 1.30 2014/07/25 00:36:41 jmcgill Exp $
+# Purpose:  This perl script will parse HWP Error XML files and create required
+#           FAPI code.
+#
+# Author: CamVan Nguyen and Mike Jones
+# Reworked for fapi2/P9
+#
+# Usage:
+# fapiParseErrorInfo.pl <output dir> <filename1> <filename2> ...
+
+use strict;
+
+#------------------------------------------------------------------------------
+# Set PREFERRED_PARSER to XML::Parser. Otherwise it uses XML::SAX which contains
+# bugs that result in XML parse errors that can be fixed by adjusting white-
+# space (i.e. parse errors that do not make sense).
+#------------------------------------------------------------------------------
+$XML::Simple::PREFERRED_PARSER = 'XML::Parser';
+
+#------------------------------------------------------------------------------
+# Specify perl modules to use
+#------------------------------------------------------------------------------
+use Digest::MD5 qw(md5_hex);
+use XML::Simple;
+my $xml = new XML::Simple (KeyAttr=>[]);
+
+# Uncomment to enable debug output
+use Data::Dumper;
+use Getopt::Long;
+
+my $target_ffdc_type = "fapi2::Target<T>";
+my $buffer_ffdc_type = "fapi2::buffer";
+my $variable_buffer_ffdc_type = "fapi2::variable_buffer";
+my $ffdc_type = "fapi2::ffdc_t";
+
+# We want to keep the signatures for the ffdc gathering hwp so that
+# we can create members of the proper types for the ffdc classes.
+my %signatures = ("proc_extract_pore_halt_ffdc" => ["por_base_state",
+                                                    "por_halt_type_t",
+                                                    "por_ffdc_offset_t"],
+                  "hwpTestFfdc1" => [$target_ffdc_type],
+                  "proc_extract_pore_base_ffdc" => ["por_base_state", "por_sbe_base_state"],
+                  "proc_tp_collect_dbg_data" => [$target_ffdc_type],
+    );
+
+# There are some names used in the XML files which exist in either
+# c++ keywords (case, for example) or macros (DOMAIN). The one's which
+# cause problems and need to be changed are here.
+#
+# DOMAIN is defined to 1 in math.h
+my %mangle_names = ("DOMAIN" => "FAPI2_DOMAIN");
+
+# A list of deprecated elements. These will report messages to the
+# user, and not define anything. They have not been found to be used,
+# but that doesn't mean they're not ...
+my %deprecated = ("RC_PROCPM_PMCINIT_TIMEOUT" => "CHIP_IN_ERROR is defined as a callout procedure");
+
+#------------------------------------------------------------------------------
+# Print Command Line Help
+#------------------------------------------------------------------------------
+my $arg_empty_ffdc = undef;
+my $arg_output_dir = undef;
+my $arg_use_variable_buffers = undef;
+
+# Get the options from the command line - the rest of @ARGV will
+# be filenames
+GetOptions("empty-ffdc-classes" => \$arg_empty_ffdc,
+           "output-dir=s" => \$arg_output_dir,
+           "use-variable-buffers" => \$arg_use_variable_buffers);
+
+my $numArgs = $#ARGV + 1;
+if (($numArgs < 1) || ($arg_output_dir eq undef))
+{
+    print ("Usage: parseErrorInfo.pl [--empty-ffdc-classes] [--use-variable-buffers] --output-dir=<output dir> <filename1> <filename2> ...\n");
+    print ("  This perl script will parse HWP Error XML files and creates\n");
+    print ("  the following files:\n");
+    print ("  - hwp_return_codes.H. HwpReturnCode enumeration (HWP generated errors)\n");
+    print ("  - hwp_error_info.H.   Error information (used by FAPI_SET_HWP_ERROR\n");
+    print ("                        when a HWP generates an error)\n");
+    print ("  - collect_reg_ffdc.C. Function to collect register FFDC\n");
+    print ("  - set_sbe_error.H.    Macro to create an SBE error\n");
+    print ("  The --empty-ffdc-classes option is for platforms which don't collect ffdc.\n");
+    exit(1);
+}
+
+#------------------------------------------------------------------------------
+# Hashes containing error names/enum-values
+#------------------------------------------------------------------------------
+my %errNameToValueHash;
+my %errValuePresentHash;
+
+#------------------------------------------------------------------------------
+# Hashes containing ffdc names/enum-values
+#------------------------------------------------------------------------------
+my %ffdcNameToValueHash;
+my %ffdcValuePresentHash;
+
+#------------------------------------------------------------------------------
+# Subroutine that checks if an entry exists in an array. If it doesn't exist
+# then it is added. The index of the entry within the array is returned
+#------------------------------------------------------------------------------
+sub addEntryToArray
+{
+    my ($arrayref, $entry ) = @_;
+
+    my $match = 0;
+    my $index = 0;
+
+    foreach my $element (@$arrayref)
+    {
+        if ($element eq $entry)
+        {
+            $match = 1;
+            last;
+        }
+        else
+        {
+            $index++;
+        }
+    }
+
+    if (!($match))
+    {
+        push(@$arrayref, $entry);
+    }
+
+    return $index;
+}
+
+#------------------------------------------------------------------------------
+# Subroutine that figures out an error enum value from an error name and stores
+# it in global hashes
+#------------------------------------------------------------------------------
+sub setErrorEnumValue
+{
+    my $name = $_[0];
+
+    #--------------------------------------------------------------------------
+    # Check that the error name is not a duplicate
+    #--------------------------------------------------------------------------
+    if (exists($errNameToValueHash{$name}))
+    {
+        # Two different errors with the same name!
+        print ("fapiParseErrorInfo.pl ERROR. Duplicate error name ", $name, "\n");
+        exit(1);
+    }
+
+    #--------------------------------------------------------------------------
+    # Figure out the error enum-value. This is a hash value generated from
+    # the error name. A hash is used for Cronus so that if a HWP is not
+    # recompiled against a new eCMD/Cronus version where the errors have
+    # changed then there will not be a mismatch in error values.
+    # This is a 24bit hash value because FAPI has a requirement that the
+    # top byte of the 32 bit error value be zero to store flags indicating
+    # the creator of the error
+    #--------------------------------------------------------------------------
+    my $errHash128Bit = md5_hex($name);
+    my $errHash24Bit = substr($errHash128Bit, 0, 6);
+
+    #--------------------------------------------------------------------------
+    # Check that the error enum-value is not a duplicate
+    #--------------------------------------------------------------------------
+    if (exists($errValuePresentHash{$errHash24Bit}))
+    {
+        # Two different errors generate the same hash-value!
+        print ("fapiParseAttributeInfo.pl ERROR. Duplicate error hash value\n");
+        exit(1);
+    }
+
+    #--------------------------------------------------------------------------
+    # Update the hashes with the error name and ID
+    #--------------------------------------------------------------------------
+    $errValuePresentHash{$errHash24Bit} = 1;
+    $errNameToValueHash{$name} = $errHash24Bit;
+}
+
+#------------------------------------------------------------------------------
+# Subroutine that figures out an FFDC ID value from an FFDC name and stores it
+# in global hashes for use when creating the enumeration of FFDC IDs
+#------------------------------------------------------------------------------
+sub setFfdcIdValue
+{
+    my $name = $_[0];
+
+    #--------------------------------------------------------------------------
+    # Check that the FFDC name is not a duplicate
+    #--------------------------------------------------------------------------
+    if (exists($ffdcNameToValueHash{$name}))
+    {
+        # Two different FFDCs with the same name!
+        print ("fapiParseErrorInfo.pl ERROR. Duplicate FFDC name ", $name, "\n");
+        exit(1);
+    }
+
+    #--------------------------------------------------------------------------
+    # Figure out the FFDC enum-value. This is a hash value generated from
+    # the FFDC name.
+    #--------------------------------------------------------------------------
+    my $ffdcHash128Bit = md5_hex($name);
+    my $ffdcHash32Bit = substr($ffdcHash128Bit, 0, 8);
+
+    #--------------------------------------------------------------------------
+    # Check that the error enum-value is not a duplicate
+    #--------------------------------------------------------------------------
+    if (exists($ffdcValuePresentHash{$ffdcHash32Bit}))
+    {
+        # Two different FFDCs generate the same hash-value!
+        print ("fapiParseAttributeInfo.pl ERROR. Duplicate FFDC hash value\n");
+        exit(1);
+    }
+
+    #--------------------------------------------------------------------------
+    # Update the hashes with the error name and ID
+    #--------------------------------------------------------------------------
+    $ffdcValuePresentHash{$ffdcHash32Bit} = 1;
+    $ffdcNameToValueHash{$name} = $ffdcHash32Bit;
+}
+
+#------------------------------------------------------------------------------
+# Subroutine to create ffdc methods
+#------------------------------------------------------------------------------
+sub addFfdcMethod
+{
+    my $methods = shift;
+    my $ffdc_uc = shift;
+    my $class_name = shift;
+    my $type = shift;
+
+    # Remove the leading *_
+    $class_name = (split (/_/, $class_name, 2))[1];
+
+    # If we didn't get a type passed in, this element will get an ffdc_t pair.
+    $type = $ffdc_type if ($type eq undef);
+
+    # Mangle the uppercase name if needed
+    $ffdc_uc = $mangle_names{$ffdc_uc} if ($mangle_names{$ffdc_uc} ne undef);
+
+    my $key = $ffdc_uc.$type;
+    my $key_target = $ffdc_uc.$target_ffdc_type;
+    my $key_ffdc = $ffdc_uc.$ffdc_type;
+
+    # Check to see if this element already has been recorded with this
+    # type or a target type. Note the effect we're shooting for here is
+    # to define the member if it's not been defined before *or* it's
+    # changing from an ffdc_t to a target due to other information in the xml
+    return if ($methods->{$key}{type} eq $type);
+    return if ($methods->{$key_target}{type} eq $target_ffdc_type);
+
+    # Just leave if this is a variable_buffer ans we're not supporting that.
+    return if (($type eq $variable_buffer_ffdc_type) && ($arg_use_variable_buffers eq undef));
+
+    # Set the proper type, and clear out any previous members/methods if
+    # we're going from an ffdc_t to a target.
+    $methods->{$key}{type} = $type;
+    delete $methods->{$key_ffdc} if ($type eq $target_ffdc_type);
+
+    my $method = "";
+    my $method_body = "";
+
+    # If we're generating empty classes, not using an argument name will avoid the unused parameter warnings
+    my $param = ($arg_empty_ffdc eq undef) ? "i_value" : "";
+
+    if ($type eq $ffdc_type)
+    {
+        $method =      "\n    template< typename T >\n";
+        $method  .=      "    inline $class_name& set_$ffdc_uc(const T& $param)\n";
+        $method_body  =  "    {$ffdc_uc.ptr() = &i_value; $ffdc_uc.size() = fapi2::getErrorInfoFfdcSize(i_value); return *this;}\n\n";
+
+        $methods->{$key}{member} = "$ffdc_type $ffdc_uc;\n    ";
+    }
+
+    elsif ($type eq $buffer_ffdc_type)
+    {
+        # Two methods - one for integral buffers and one for variable_buffers
+        $method =      "\n    template< typename T >\n";
+        $method  .=      "    inline $class_name& set_$ffdc_uc(const fapi2::buffer<T>& $param)\n";
+        $method_body  =  "    {$ffdc_uc.ptr() = &i_value(); $ffdc_uc.size() = i_value.template getLength<uint8_t>(); return *this;}\n\n";
+
+        $methods->{$key}{member} = "$ffdc_type $ffdc_uc;\n    ";
+    }
+
+    elsif ($type eq $variable_buffer_ffdc_type)
+    {
+        $method       =  "\n    inline $class_name& set_$ffdc_uc(const fapi2::variable_buffer& $param)\n";
+        $method_body  =    "    {$ffdc_uc.ptr() = &i_value(); $ffdc_uc.size() = i_value.template getLength<uint8_t>(); return *this;}\n\n";
+
+        # No need to add the member here, it was added with fapi2::buffer. And we can't have variable
+        # buffer support with out integral buffer support (can we?)
+    }
+
+    elsif ($type eq $target_ffdc_type)
+    {
+        $method =      "\n    template< TargetType T >\n";
+        $method .=       "    inline $class_name& set_$ffdc_uc(const $type& $param)\n";
+        $method_body .=  "    {$ffdc_uc.ptr() = &i_value; $ffdc_uc.size() = fapi2::getErrorInfoFfdcSize(i_value); return *this;}\n\n";
+
+        $methods->{$key}{member} = "$ffdc_type $ffdc_uc;\n    ";
+    }
+
+    else
+    {
+        print ("ffdc type $type is unknown");
+        exit(1);
+    }
+
+    $method .= ($arg_empty_ffdc eq undef) ? $method_body : "    {return *this;}\n\n";
+    $methods->{$key}{method} = $method;
+}
+
+#------------------------------------------------------------------------------
+# Open output files for writing
+#------------------------------------------------------------------------------
+my $rcFile = $arg_output_dir;
+$rcFile .= "/";
+$rcFile .= "hwp_return_codes.H";
+open(RCFILE, ">", $rcFile);
+
+my $eiFile = $arg_output_dir;
+$eiFile .= "/";
+$eiFile .= "hwp_error_info.H";
+open(EIFILE, ">", $eiFile);
+
+my $ecFile = $arg_output_dir;
+$ecFile .= "/";
+$ecFile .= "hwp_ffdc_classes.H";
+open(ECFILE, ">", $ecFile);
+
+my $crFile = $arg_output_dir;
+$crFile .= "/";
+$crFile .= "collect_reg_ffdc.C";
+open(CRFILE, ">", $crFile);
+
+my $sbFile = $arg_output_dir;
+$sbFile .= "/";
+$sbFile .= "set_sbe_error.H";
+open(SBFILE, ">", $sbFile);
+
+#------------------------------------------------------------------------------
+# Print start of file information to hwp_error_info.H
+#------------------------------------------------------------------------------
+print EIFILE "// hwp_error_info.H\n";
+print EIFILE "// This file is generated by the perl script parseErrorInfo.pl\n\n";
+print EIFILE "#ifndef FAPI2_HWPERRORINFO_H_\n";
+print EIFILE "#define FAPI2_HWPERRORINFO_H_\n\n";
+print EIFILE "#include <target.H>\n";
+print EIFILE "#include <plat_trace.H>\n";
+print EIFILE "#include <hwp_return_codes.H>\n";
+print EIFILE "#include <set_sbe_error.H>\n";
+print EIFILE "/**\n";
+print EIFILE " * \@brief Error Information macros and HwpFfdcId enumeration\n";
+print EIFILE " *\/\n";
+
+#------------------------------------------------------------------------------
+# Print start of file information to hwp_ffdc_classes.H
+#------------------------------------------------------------------------------
+print ECFILE "// hwp_ffdc_classes.H\n";
+print ECFILE "// This file is generated by the perl script parseErrorInfo.pl\n\n";
+print ECFILE "#ifndef FAPI2_HWP_FFDC_CLASSES_H_\n";
+print ECFILE "#define FAPI2_HWP_FFDC_CLASSES_H_\n\n";
+print ECFILE "#include <ffdc.H>\n";
+print ECFILE "#include <buffer.H>\n";
+print ECFILE "#include <variable_buffer.H>\n" if ($arg_use_variable_buffers ne undef);
+print ECFILE "#include <error_info.H>\n";
+print ECFILE "#include <utils.H>\n";
+print ECFILE "#include <hwp_error_info.H>\n";
+print ECFILE "#include <collect_reg_ffdc.H>\n";
+#print ECFILE "#include <proc_extract_sbe_rc.H>\n\n";
+print ECFILE "/**\n";
+print ECFILE " * \@brief FFDC gathering classes\n";
+print ECFILE " *\/\n";
+print ECFILE "namespace fapi2\n{\n";
+
+#------------------------------------------------------------------------------
+# Print start of file information to collectRegFfdc.C
+#------------------------------------------------------------------------------
+print CRFILE "// collect_reg_ffdc.C\n";
+print CRFILE "// This file is generated by the perl script parseErrorInfo.pl\n\n";
+print CRFILE "#include <stdint.h>\n";
+print CRFILE "#include <vector>\n";
+
+print CRFILE "#include <buffer.H>\n";
+print CRFILE "#include <collect_reg_ffdc.H>\n";
+print CRFILE "#include <target.H>\n";
+print CRFILE "#include <return_code.H>\n";
+print CRFILE "#include <hw_access.H>\n";
+print CRFILE "#include <plat_trace.H>\n\n";
+
+print CRFILE "namespace fapi2\n";
+print CRFILE "{\n";
+print CRFILE "void collectRegFfdc(const fapi2::ffdc_t& i_target,\n";
+print CRFILE "                        const fapi2::HwpFfdcId i_ffdcId,\n";
+print CRFILE "                        fapi2::ReturnCode & o_rc,\n";
+print CRFILE "                        const TargetType i_child,\n";
+print CRFILE "                        const TargetType i_presChild,\n";
+print CRFILE "                        uint32_t i_childOffsetMult)\n";
+print CRFILE "{\n";
+print CRFILE "    FAPI_INF(\"collectRegFfdc. FFDC ID: 0x%x\", i_ffdcId);\n";
+print CRFILE "    fapi2::ReturnCode l_rc;\n";
+print CRFILE "    fapi2::buffer<uint64_t> l_buf;\n";
+print CRFILE "    uint32_t l_cfamData = 0;\n";
+print CRFILE "    uint64_t l_scomData = 0;\n";
+print CRFILE "    std::vector<uint32_t> l_cfamAddresses;\n";
+print CRFILE "    std::vector<uint64_t> l_scomAddresses;\n";
+print CRFILE "    uint32_t l_ffdcSize = 0;\n\n";
+print CRFILE "    switch (i_ffdcId)\n";
+print CRFILE "    {\n";
+print CRFILE "        // void statments for the unused variables\n";
+print CRFILE "        static_cast<void>(l_cfamData);\n";
+print CRFILE "        static_cast<void>(l_scomData);\n";
+print CRFILE "        static_cast<void>(l_ffdcSize);\n";
+print CRFILE "        static_cast<const void>(i_target);\n";
+print CRFILE "        static_cast<void>(o_rc);\n";
+print CRFILE "        static_cast<void>(i_child);\n";
+print CRFILE "        static_cast<void>(i_presChild);\n";
+print CRFILE "        static_cast<void>(i_childOffsetMult);\n";
+#------------------------------------------------------------------------------
+# Print start of file information to setSbeError.H
+#------------------------------------------------------------------------------
+print SBFILE "// setSbeError.H\n";
+print SBFILE "// This file is generated by the perl script parseErrorInfo.pl\n\n";
+print SBFILE "// When SBE code creates an error, it produces an error value\n";
+print SBFILE "// that matches a value in the HwpReturnCode enum in\n";
+print SBFILE "// fapiHwpReturnCodes.H. The SBE uses the __ASSEMBLER__\n";
+print SBFILE "// primitives in hwpReturnCodes.H to do this. The function\n";
+print SBFILE "// that extracts the error value from the SBE needs to call\n";
+print SBFILE "// FAPI_SET_HWP_ERROR to create the error and get all the\n";
+print SBFILE "// actions in the error XML file performed, but that macro can\n";
+print SBFILE "// only be called with the enumerator, not the value. This\n";
+print SBFILE "// FAPI_SET_SBE_ERROR macro can be called instead, it calls\n";
+print SBFILE "// FAPI_SET_HWP_ERROR with the correct error enumerator.\n";
+print SBFILE "// Errors containing <sbeError/> in their XML are supported\n";
+print SBFILE "// in this macro.\n\n";
+print SBFILE "// Note that it is expected that this macro will be called\n";
+print SBFILE "// in one place (the function that extracts the error from\n";
+print SBFILE "// the SBE), if this changes and it is called in multiple\n";
+print SBFILE "// places then the macro could be turned into a function to\n";
+print SBFILE "// avoid the code size increase of expanding the macro in\n";
+print SBFILE "// multiple places. The function approach is slightly more\n";
+print SBFILE "// complicated, there is an extra C file and the function\n";
+print SBFILE "// must take a parameter for the generic chip ID in the error\n";
+print SBFILE "// XML.\n\n";
+print SBFILE "#ifndef FAPI2_SETSBEERROR_H_\n";
+print SBFILE "#define FAPI2_SETSBEERROR_H_\n\n";
+print SBFILE "#define FAPI_SET_SBE_ERROR(RC, ERRVAL)\\\n";
+print SBFILE "{\\\n";
+print SBFILE "switch (ERRVAL)\\\n";
+print SBFILE "{\\\n";
+
+#------------------------------------------------------------------------------
+# For each XML file
+#------------------------------------------------------------------------------
+foreach my $argnum (0 .. $#ARGV)
+{
+    my $infile = $ARGV[$argnum];
+    my $count = 0;
+
+    #--------------------------------------------------------------------------
+    # Read XML file. The ForceArray option ensures that there is an array of
+    # elements even if there is only one element
+    #--------------------------------------------------------------------------
+    my $errors = $xml->XMLin($infile, ForceArray =>
+        ['hwpError', 'collectFfdc', 'ffdc', 'callout', 'deconfigure', 'gard',
+         'registerFfdc', 'collectRegisterFfdc', 'cfamRegister', 'scomRegister',
+         'id','collectTrace', 'buffer']);
+
+    # Uncomment to get debug output of all errors
+    #print "\nFile: ", $infile, "\n", Dumper($errors), "\n";
+
+    #--------------------------------------------------------------------------
+    # For each Error
+    #--------------------------------------------------------------------------
+    foreach my $err (@{$errors->{hwpError}})
+    {
+        # Hash of methods for the ffdc-gathering class
+        my %methods;
+
+        #----------------------------------------------------------------------
+        # Check that expected fields are present
+        #----------------------------------------------------------------------
+        if (! exists $err->{rc})
+        {
+            print ("parseErrorInfo.pl ERROR. rc missing\n");
+            exit(1);
+        }
+
+        if (! exists $err->{description})
+        {
+            print ("parseErrorInfo.pl ERROR in $err->{rc}. description missing\n");
+            exit(1);
+        }
+
+        #----------------------------------------------------------------------
+        # Check that this rc hasn't been deprecated
+        #----------------------------------------------------------------------
+        if ($deprecated{$err->{rc}} ne undef)
+        {
+            print "WARNING: $err->{rc} has been deprecated because $deprecated{$err->{rc}}\n";
+            next;
+        }
+
+        #----------------------------------------------------------------------
+        # Set the error enum value in a global hash
+        #---------------------------------------------------------------------
+        setErrorEnumValue($err->{rc});
+
+        #----------------------------------------------------------------------
+        # If this is an SBE error, add it to set_sbe_error.H
+        #----------------------------------------------------------------------
+        if (exists $err->{sbeError})
+        {
+            print SBFILE "    case fapi2::$err->{rc}:\\\n";
+            print SBFILE "        FAPI_SET_HWP_ERROR(RC, $err->{rc});\\\n";
+            print SBFILE "        break;\\\n";
+        }
+
+        #----------------------------------------------------------------------
+        # Print the CALL_FUNCS_TO_COLLECT_FFDC macro to hwp_error_info.H
+        #----------------------------------------------------------------------
+        print EIFILE "#define $err->{rc}_CALL_FUNCS_TO_COLLECT_FFDC(RC) ";
+
+        # For now, this code is removed. It appears to work just fine but
+        # will require more of the fapi2 infrastructure to be in place.
+        # Because the ffdc collection classes create members with real types,
+        # the declarations of the types need to be visible - and they're not
+        # right now. When we get further along, we can enable this code.
+=begin NO_FFDC_COLLECT_HWP
+        $count = 0;
+
+        foreach my $collectFfdc (@{$err->{collectFfdc}})
+        {
+            if ($count == 0)
+            {
+                print EIFILE "{ fapi2::ReturnCode l_tempRc; ";
+            }
+            $count++;
+
+            print EIFILE "FAPI_EXEC_HWP(l_tempRc, $collectFfdc, RC); ";
+
+            # collectFfdc is a string we're going to stuff into FAPI_EXEC_HWP
+            # but we need to create the arguments in the ffdc class. The first
+            # element inthe collectFfdc string is the function to call.
+            my @elements = split /,/, $collectFfdc;
+            my @signature = @{$signatures{@elements[0]}};
+            for (my $i = 1; $i <= $#elements; $i++)
+            {
+                @elements[$i] =~ s/^\s+|\s+$//g;
+                addFfdcMethod(\%methods, @elements[$i], $err->{rc}, @signature[$i-1]);
+            }
+        }
+
+        if ($count > 0)
+        {
+            print EIFILE "}";
+        }
+=cut NO_FFDC_COLLECT_HWP
+        print EIFILE "\n";
+
+        #----------------------------------------------------------------------
+        # Print the CALL_FUNCS_TO_COLLECT_REG_FFDC macro to hwp_error_info.H
+        #----------------------------------------------------------------------
+        print EIFILE "#define $err->{rc}_CALL_FUNCS_TO_COLLECT_REG_FFDC(RC) ";
+
+        foreach my $collectRegisterFfdc (@{$err->{collectRegisterFfdc}})
+        {
+            #------------------------------------------------------------------
+            # Check that expected fields are present
+            #------------------------------------------------------------------
+            if (! exists $collectRegisterFfdc->{id}[0])
+            {
+                print ("parseErrorInfo.pl ERROR in $err->{rc}. id(s) missing from collectRegisterFfdc\n");
+                exit(1);
+            }
+            foreach my $id (@{$collectRegisterFfdc->{id}})
+            {
+                #---------------------------------------------------------------------------------
+                # Check FFDC register collection type: target, child, or based on present children
+                #---------------------------------------------------------------------------------
+                if (exists $collectRegisterFfdc->{target})
+                {
+                    print EIFILE "fapi2::collectRegFfdc($collectRegisterFfdc->{target}, ";
+                    print EIFILE "fapi2::$id, RC, fapi2::TARGET_TYPE_NONE, fapi2::TARGET_TYPE_NONE); ";
+                    addFfdcMethod(\%methods, $collectRegisterFfdc->{target},
+                                  $err->{rc}, $target_ffdc_type);
+                }
+                elsif (exists $collectRegisterFfdc->{childTargets})
+                {
+                    if (! exists $collectRegisterFfdc->{childTargets}->{parent})
+                    {
+                        print ("parseErrorInfo.pl ERROR: parent missing from collectRegisterFfdc\n");
+                        exit(1);
+                    }
+                    if (! exists $collectRegisterFfdc->{childTargets}->{childType})
+                    {
+                        print ("parseErrorInfo.pl ERROR: childType missing from collectRegisterFfdc\n");
+                        exit(1);
+                    }
+                    print EIFILE "fapi2::collectRegFfdc($collectRegisterFfdc->{childTargets}->{parent}, fapi2::$id, ";
+                    print EIFILE "RC, fapi2::$collectRegisterFfdc->{childTargets}->{childType}, fapi2::TARGET_TYPE_NONE); ";
+                    addFfdcMethod(\%methods, $collectRegisterFfdc->{childTargets}->{parent},
+                                  $err->{rc}, $target_ffdc_type);
+                }
+                elsif (exists $collectRegisterFfdc->{basedOnPresentChildren})
+                {
+                    if (! exists $collectRegisterFfdc->{basedOnPresentChildren}->{target})
+                    {
+                        print ("parseErrorInfo.pl ERROR: target missing from collectRegisterFfdc\n");
+                        exit(1);
+                    }
+                    if (! exists $collectRegisterFfdc->{basedOnPresentChildren}->{childType})
+                    {
+                        print ("parseErrorInfo.pl ERROR: childType missing from collectRegisterFfdc\n");
+                        exit(1);
+                    }
+                    if (! exists $collectRegisterFfdc->{basedOnPresentChildren}->{childPosOffsetMultiplier})
+                    {
+                        print ("parseErrorInfo.pl ERROR: childPosOffsetMultiplier missing from collectRegisterFfdc\n");
+                        exit(1);
+                    }
+                    print EIFILE "fapi2::collectRegFfdc($collectRegisterFfdc->{basedOnPresentChildren}->{target}, fapi2::$id, RC, ";
+                    print EIFILE "fapi2::TARGET_TYPE_NONE, fapi2::$collectRegisterFfdc->{basedOnPresentChildren}->{childType}, ";
+                    print EIFILE "$collectRegisterFfdc->{basedOnPresentChildren}->{childPosOffsetMultiplier}); ";
+                    addFfdcMethod(\%methods, $collectRegisterFfdc->{basedOnPresentChildren}->{target},
+                                  $err->{rc}, $target_ffdc_type);
+                }
+                else
+                {
+                    print ("parseErrorInfo.pl ERROR: Invalid collectRegisterFfdc configuration\n");
+                    exit(1);
+                }
+            }
+        }
+
+        print EIFILE "\n";
+
+        #----------------------------------------------------------------------
+        # Print the ADD_ERROR_INFO macro to hwp_error_info.H
+        #----------------------------------------------------------------------
+        print EIFILE "#define $err->{rc}_ADD_ERROR_INFO(RC) ";
+
+        # Array of EI Objects
+        my @eiObjects;
+
+        my $eiObjectStr = "const void * l_objects[] = {";
+        my $eiEntryStr = "";
+        my $eiEntryCount = 0;
+        my %cdgTargetHash; # Records the callout/deconfigure/gards for Targets
+        my %cdgChildHash;  # Records the callout/deconfigure/gards for Children
+
+        # collect firmware trace
+        foreach my $collectTrace (@{$err->{collectTrace}})
+        {
+            # Add an EI entry to eiEntryStr
+            $eiEntryStr .= "  l_entries[$eiEntryCount].iv_type = fapi2::EI_TYPE_COLLECT_TRACE; \\\n";
+            $eiEntryStr .= "  l_entries[$eiEntryCount].collect_trace.iv_eieTraceId =  fapi2::CollectTraces::$collectTrace; \\\n";
+            $eiEntryCount++;
+        }
+
+        # Local FFDC
+        foreach my $ffdc (@{$err->{ffdc}})
+        {
+            # Set the FFDC ID value in a global hash. The name is <rc>_<ffdc>
+            my $ffdcName = $err->{rc} . "_";
+            $ffdcName = $ffdcName . $ffdc;
+            setFfdcIdValue($ffdcName);
+
+            # Add the FFDC data to the EI Object array if it doesn't already exist
+            my $objNum = addEntryToArray(\@eiObjects, $ffdc);
+
+            # Add a method to the ffdc-gathering class
+            addFfdcMethod(\%methods, $ffdc, $err->{rc});
+
+            $ffdc = $mangle_names{$ffdc} if ($mangle_names{$ffdc} ne undef);
+
+            # Add an EI entry to eiEntryStr
+            $eiEntryStr .= "  l_entries[$eiEntryCount].iv_type = fapi2::EI_TYPE_FFDC; \\\n";
+            $eiEntryStr .= "  l_entries[$eiEntryCount].ffdc.iv_ffdcObjIndex = $objNum; \\\n";
+            $eiEntryStr .= "  l_entries[$eiEntryCount].ffdc.iv_ffdcId = fapi2::$ffdcName; \\\n";
+            $eiEntryStr .= "  l_entries[$eiEntryCount].ffdc.iv_ffdcSize = $ffdc.size(); \\\n";
+            $eiEntryCount++;
+        }
+
+        # Buffers, looks a lot like local ffdc
+        foreach my $buffer (@{$err->{buffer}})
+        {
+            # Set the FFDC ID value in a global hash. The name is <rc>_<ffdc>
+            my $bufferName = $err->{rc} . "_";
+            $bufferName = $bufferName . $buffer;
+            setFfdcIdValue($bufferName);
+
+            # Add the FFDC data to the EI Object array if it doesn't already exist
+            my $objNum = addEntryToArray(\@eiObjects, $buffer);
+
+            # Add a method to the ffdc-gathering class - one for each buffer type
+            addFfdcMethod(\%methods, $buffer, $err->{rc}, $buffer_ffdc_type);
+            addFfdcMethod(\%methods, $buffer, $err->{rc}, $variable_buffer_ffdc_type);
+
+            # Add an EI entry to eiEntryStr
+            $eiEntryStr .= "  l_entries[$eiEntryCount].iv_type = fapi2::EI_TYPE_FFDC; \\\n";
+            $eiEntryStr .= "  l_entries[$eiEntryCount].ffdc.iv_ffdcObjIndex = $objNum; \\\n";
+            $eiEntryStr .= "  l_entries[$eiEntryCount].ffdc.iv_ffdcId = fapi2::$bufferName; \\\n";
+            $eiEntryStr .= "  l_entries[$eiEntryCount].ffdc.iv_ffdcSize = fapi2::getErrorInfoFfdcSize($buffer); \\\n";
+            $eiEntryCount++;
+        }
+
+        # Procedure/Target/Bus/Child callouts
+        foreach my $callout (@{$err->{callout}})
+        {
+            if (! exists $callout->{priority})
+            {
+                print ("parseErrorInfo.pl ERROR in $err->{rc}. Callout priority missing\n");
+                exit(1);
+            }
+
+            my $elementsFound = 0;
+            if (exists $callout->{hw})
+            {
+                # HW Callout
+                if (! exists $callout->{hw}->{hwid})
+                {
+                    print ("parseErrorInfo.pl ERROR in $err->{rc}. HW Callout hwid missing\n");
+                    exit(1);
+                }
+
+                # Check that those HW callouts that need reference targets have them
+                if (($callout->{hw}->{hwid} eq "TOD_CLOCK") ||
+                    ($callout->{hw}->{hwid} eq "MEM_REF_CLOCK") ||
+                    ($callout->{hw}->{hwid} eq "PROC_REF_CLOCK") ||
+                    ($callout->{hw}->{hwid} eq "PCI_REF_CLOCK"))
+                {
+                    if (! exists $callout->{hw}->{refTarget})
+                    {
+                        print ("parseErrorInfo.pl ERROR in $err->{rc}. Callout missing refTarget\n");
+                        exit(1);
+                    }
+                }
+
+                # Add an EI entry to eiEntryStr
+                $eiEntryStr .= "  l_entries[$eiEntryCount].iv_type = fapi2::EI_TYPE_HW_CALLOUT; \\\n";
+                $eiEntryStr .= "  l_entries[$eiEntryCount].hw_callout.iv_hw = fapi2::HwCallouts::$callout->{hw}->{hwid}; \\\n";
+                $eiEntryStr .= "  l_entries[$eiEntryCount].hw_callout.iv_calloutPriority = fapi2::CalloutPriorities::$callout->{priority}; \\\n";
+                if (exists $callout->{hw}->{refTarget})
+                {
+                    # Add the Targets to the objectlist if they don't already exist
+                    my $objNum = addEntryToArray(\@eiObjects, $callout->{hw}->{refTarget});
+                    $eiEntryStr .= "  l_entries[$eiEntryCount].hw_callout.iv_refObjIndex = $objNum; \\\n";
+
+                    # Add a method to the ffdc-gathering class
+                    addFfdcMethod(\%methods, $callout->{hw}->{refTarget}, $err->{rc});
+                }
+                else
+                {
+                    $eiEntryStr .= "  l_entries[$eiEntryCount].hw_callout.iv_refObjIndex = 0xff; \\\n";
+                }
+                $eiEntryCount++;
+                $elementsFound++;
+            }
+            if (exists $callout->{procedure})
+            {
+                # Procedure Callout
+                # Add an EI entry to eiEntryStr
+                $eiEntryStr .= "  l_entries[$eiEntryCount].iv_type = fapi2::EI_TYPE_PROCEDURE_CALLOUT; \\\n";
+                $eiEntryStr .= "  l_entries[$eiEntryCount].proc_callout.iv_procedure = fapi2::ProcedureCallouts::$callout->{procedure}; \\\n";
+                $eiEntryStr .= "  l_entries[$eiEntryCount].proc_callout.iv_calloutPriority = fapi2::CalloutPriorities::$callout->{priority}; \\\n";
+                $eiEntryCount++;
+                $elementsFound++;
+            }
+            if (exists $callout->{bus})
+            {
+                # A Bus Callout consists of two targets separated by
+                # commas/spaces
+                my @targets = split(/\s*,\s*|\s+/, $callout->{bus});
+
+                if (scalar @targets != 2)
+                {
+                    print ("parseErrorInfo.pl ERROR in $err->{rc}. did not find two targets in bus callout\n");
+                    exit(1);
+                }
+
+                # Add the Targets to the objectlist if they don't already exist
+                my $objNum1 = addEntryToArray(\@eiObjects, $targets[0]);
+
+                my $objNum2 = addEntryToArray(\@eiObjects, $targets[1]);
+
+                # Add a method to the ffdc-gathering class
+                addFfdcMethod(\%methods, $targets[0], $err->{rc}, $target_ffdc_type);
+                addFfdcMethod(\%methods, $targets[1], $err->{rc}, $target_ffdc_type);
+
+                # Add an EI entry to eiEntryStr
+                $eiEntryStr .= "  l_entries[$eiEntryCount].iv_type = fapi2::EI_TYPE_BUS_CALLOUT; \\\n";
+                $eiEntryStr .= "  l_entries[$eiEntryCount].bus_callout.iv_endpoint1ObjIndex = $objNum1; \\\n";
+                $eiEntryStr .= "  l_entries[$eiEntryCount].bus_callout.iv_endpoint2ObjIndex = $objNum2; \\\n";
+                $eiEntryStr .= "  l_entries[$eiEntryCount].bus_callout.iv_calloutPriority = fapi2::CalloutPriorities::$callout->{priority}; \\\n";
+                $eiEntryCount++;
+                $elementsFound++;
+            }
+            if (exists $callout->{target})
+            {
+                # Add the Target to cdgTargetHash to be processed with any
+                # deconfigure and GARD requests
+                $cdgTargetHash{$callout->{target}}{callout} = 1;
+                $cdgTargetHash{$callout->{target}}{priority} =
+                    $callout->{priority};
+
+                $elementsFound++;
+            }
+            if (exists $callout->{childTargets})
+            {
+                # Check that the parent and childType subelements exist
+                if (! exists $callout->{childTargets}->{parent})
+                {
+                    print ("parseErrorInfo.pl ERROR in $err->{rc}. Child Callout parent missing\n");
+                    exit(1);
+                }
+
+                if (! exists $callout->{childTargets}->{childType})
+                {
+                    print ("parseErrorInfo.pl ERROR in $err->{rc}. Child Callout childType missing\n");
+                    exit(1);
+                }
+
+                # Add the child info to cdgChildHash to be processed with
+                # any deconfigure and GARD requests
+                my $parent = $callout->{childTargets}->{parent};
+                my $childType = $callout->{childTargets}->{childType};
+                $cdgChildHash{$parent}{$childType}{callout} = 1;
+                $cdgChildHash{$parent}{$childType}{priority} =
+                    $callout->{priority};
+
+                $elementsFound++;
+
+                if (exists $callout->{childTargets}->{childPort})
+                {
+                    my $childPort = $callout->{childTargets}->{childPort};
+
+                    $cdgChildHash{$parent}{$childType}{childPort} = $childPort;
+                }
+
+                if (exists $callout->{childTargets}->{childNumber})
+                {
+                    my $childNum = $callout->{childTargets}->{childNumber};
+                    $cdgChildHash{$parent}{$childType}{childNumber} = $childNum;
+                }
+
+            }
+            if ($elementsFound == 0)
+            {
+                print ("parseErrorInfo.pl ERROR in $err->{rc}. Callout incomplete\n");
+                exit(1);
+            }
+            elsif ($elementsFound > 1)
+            {
+                print ("parseErrorInfo.pl ERROR in $err->{rc}. Callout has multiple elements\n");
+                exit(1);
+            }
+        } # callout
+
+        # Target/Child deconfigures
+        foreach my $deconfigure (@{$err->{deconfigure}})
+        {
+            my $elementsFound = 0;
+            if (exists $deconfigure->{target})
+            {
+                # Add the Target to cdgTargetHash to be processed with any
+                # callout and GARD requests
+                $cdgTargetHash{$deconfigure->{target}}{deconf} = 1;
+                $elementsFound++;
+            }
+            if (exists $deconfigure->{childTargets})
+            {
+                # Check that the parent and childType subelements exist
+                if (! exists $deconfigure->{childTargets}->{parent})
+                {
+                    print ("parseErrorInfo.pl ERROR in $err->{rc}. Child Deconfigure parent missing\n");
+                    exit(1);
+                }
+                if (! exists $deconfigure->{childTargets}->{childType})
+                {
+                    print ("parseErrorInfo.pl ERROR in $err->{rc}. Child Deconfigure childType missing\n");
+                    exit(1);
+                }
+
+                # Add the child info to cdgChildHash to be processed with
+                # any callout and GARD requests
+                my $parent = $deconfigure->{childTargets}->{parent};
+                my $childType = $deconfigure->{childTargets}->{childType};
+                $cdgChildHash{$parent}{$childType}{deconf} = 1;
+
+                $elementsFound++;
+
+                if ( exists $deconfigure->{childTargets}->{childPort})
+                {
+                    my $childPort = $deconfigure->{childTargets}->{childPort};
+
+                    $cdgChildHash{$parent}{$childType}{childPort} = $childPort;
+                }
+
+                if ( exists $deconfigure->{childTargets}->{childNumber})
+                {
+                    my $childNum = $deconfigure->{childTargets}->{childNumber};
+                    $cdgChildHash{$parent}{$childType}{childNumber} = $childNum;
+
+                }
+            }
+            if ($elementsFound == 0)
+            {
+                print ("parseErrorInfo.pl ERROR in $err->{rc}. Deconfigure incomplete\n");
+                exit(1);
+            }
+            elsif ($elementsFound > 1)
+            {
+                print ("parseErrorInfo.pl ERROR in $err->{rc}. Deconfigure has multiple elements\n");
+                exit(1);
+            }
+        } # deconfigure
+
+        # Target/Child Gards
+        foreach my $gard (@{$err->{gard}})
+        {
+            my $elementsFound = 0;
+            if (exists $gard->{target})
+            {
+                # Add the Target to cdgTargetHash to be processed with any
+                # callout and deconfigure requests
+                $cdgTargetHash{$gard->{target}}{gard} = 1;
+                $elementsFound++;
+            }
+            if (exists $gard->{childTargets})
+            {
+                # Check that the parent and childType subelements exist
+                if (! exists $gard->{childTargets}->{parent})
+                {
+                    print ("parseErrorInfo.pl ERROR in $err->{rc}. Child GARD parent missing\n");
+                    exit(1);
+                }
+                if (! exists $gard->{childTargets}->{childType})
+                {
+                    print ("parseErrorInfo.pl ERROR in $err->{rc}. Child GARD childType missing\n");
+                    exit(1);
+                }
+
+                # Add the child info to cdgChildHash to be processed with
+                # any callout and deconfigure requests
+                my $parent = $gard->{childTargets}->{parent};
+                my $childType = $gard->{childTargets}->{childType};
+                $cdgChildHash{$parent}{$childType}{gard} = 1;
+
+                $elementsFound++;
+
+                if ( exists $gard->{childTargets}->{childPort})
+                {
+                    my $childPort = $gard->{childTargets}->{childPort};
+
+                    $cdgChildHash{$parent}{$childType}{childPort} = $childPort;
+
+                }
+
+                if ( exists $gard->{childTargets}->{childNumber})
+                {
+                    my $childNum = $gard->{childTargets}->{childNumber};
+                    $cdgChildHash{$parent}{$childType}{childNumber} = $childNum;
+                }
+            }
+            if ($elementsFound == 0)
+            {
+                print ("parseErrorInfo.pl ERROR in $err->{rc}. GARD incomplete\n");
+                exit(1);
+            }
+            elsif ($elementsFound > 1)
+            {
+                print ("parseErrorInfo.pl ERROR in $err->{rc}. GARD has multiple elements\n");
+                exit(1);
+            }
+        } # gard
+
+        # Process the callout, deconfigures and GARDs for each Target
+        foreach my $cdg (keys %cdgTargetHash)
+        {
+            my $callout = 0;
+            my $priority = 'LOW';
+            my $deconf = 0;
+            my $gard = 0;
+
+            if (exists $cdgTargetHash{$cdg}->{callout})
+            {
+                $callout = 1;
+            }
+            if (exists $cdgTargetHash{$cdg}->{priority})
+            {
+                $priority = $cdgTargetHash{$cdg}->{priority};
+            }
+            if (exists $cdgTargetHash{$cdg}->{deconf})
+            {
+                $deconf = 1;
+            }
+            if (exists $cdgTargetHash{$cdg}->{gard})
+            {
+                $gard = 1;
+            }
+
+            # Add the Target to the objectlist if it doesn't already exist
+            my $objNum = addEntryToArray(\@eiObjects, $cdg);
+
+            # Add a method to the ffdc-gathering class
+            addFfdcMethod(\%methods, $cdg, $err->{rc}, $target_ffdc_type);
+
+            # Add an EI entry to eiEntryStr
+            $eiEntryStr .= "  l_entries[$eiEntryCount].iv_type = fapi2::EI_TYPE_CDG; \\\n";
+            $eiEntryStr .= "  l_entries[$eiEntryCount].target_cdg.iv_targetObjIndex = $objNum; \\\n";
+            $eiEntryStr .= "  l_entries[$eiEntryCount].target_cdg.iv_callout = $callout; \\\n";
+            $eiEntryStr .= "  l_entries[$eiEntryCount].target_cdg.iv_deconfigure = $deconf; \\\n";
+            $eiEntryStr .= "  l_entries[$eiEntryCount].target_cdg.iv_gard = $gard; \\\n";
+            $eiEntryStr .= "  l_entries[$eiEntryCount].target_cdg.iv_calloutPriority = fapi2::CalloutPriorities::$priority; \\\n";
+            $eiEntryCount++;
+        }
+
+        # Process the callout, deconfigures and GARDs for Child Targets
+        foreach my $parent (keys %cdgChildHash)
+        {
+            foreach my $childType (keys %{$cdgChildHash{$parent}})
+            {
+                my $callout = 0;
+                my $priority = 'LOW';
+                my $deconf = 0;
+                my $gard = 0;
+                my $childPort = 0xFF;
+                my $childNumber = 0xFF;
+
+                if (exists $cdgChildHash{$parent}{$childType}->{callout})
+                {
+                    $callout = 1;
+                }
+                if (exists $cdgChildHash{$parent}->{$childType}->{priority})
+                {
+                    $priority =
+                        $cdgChildHash{$parent}->{$childType}->{priority};
+                }
+                if (exists $cdgChildHash{$parent}->{$childType}->{deconf})
+                {
+                    $deconf = 1;
+                }
+                if (exists $cdgChildHash{$parent}->{$childType}->{childPort})
+                {
+                    $childPort =
+                        $cdgChildHash{$parent}->{$childType}->{childPort} ;
+                     addFfdcMethod(\%methods, $childPort, $err->{rc});
+                }
+                if (exists $cdgChildHash{$parent}->{$childType}->{childNumber})
+                {
+                    $childNumber =
+                        $cdgChildHash{$parent}->{$childType}->{childNumber} ;
+                    addFfdcMethod(\%methods, $childNumber, $err->{rc});
+                }
+                if (exists $cdgChildHash{$parent}->{$childType}->{gard})
+                {
+                    $gard = 1;
+                }
+
+
+                # Add the Target to the objectlist if it doesn't already exist
+                my $objNum = addEntryToArray(\@eiObjects, $parent);
+                addFfdcMethod(\%methods, $parent, $err->{rc}, $target_ffdc_type);
+
+                # Add an EI entry to eiEntryStr
+                $eiEntryStr .=
+                    "  l_entries[$eiEntryCount].iv_type = fapi2::EI_TYPE_CHILDREN_CDG; \\\n";
+                $eiEntryStr .=
+                    "  l_entries[$eiEntryCount].children_cdg.iv_parentObjIndex = $objNum; \\\n";
+                $eiEntryStr .=
+                    "  l_entries[$eiEntryCount].children_cdg.iv_callout = $callout; \\\n";
+                $eiEntryStr .=
+                    "  l_entries[$eiEntryCount].children_cdg.iv_deconfigure = $deconf; \\\n";
+                $eiEntryStr .=
+                    "  l_entries[$eiEntryCount].children_cdg.iv_childType = fapi2::$childType; \\\n";
+                $eiEntryStr .=
+                    "  l_entries[$eiEntryCount].children_cdg.iv_childPort = $childPort; \\\n";
+                $eiEntryStr .=
+                    "  l_entries[$eiEntryCount].children_cdg.iv_childNumber = $childNumber; \\\n";
+                $eiEntryStr .=
+                    "  l_entries[$eiEntryCount].children_cdg.iv_gard = $gard; \\\n";
+                $eiEntryStr .=
+                    "  l_entries[$eiEntryCount].children_cdg.iv_calloutPriority = fapi2::CalloutPriorities::$priority; \\\n";
+                $eiEntryCount++;
+            }
+        }
+
+        # Add all objects to $eiObjectStr
+        my $objCount = 0;
+
+        foreach my $eiObject (@eiObjects)
+        {
+            if ($objCount > 0)
+            {
+                $eiObjectStr .= ", ";
+            }
+
+            if ($mangle_names{$eiObject} eq undef)
+            {
+                $eiObjectStr .= "$eiObject"
+            }
+            else
+            {
+                $eiObjectStr .= $mangle_names{$eiObject};
+            }
+
+            $objCount++;
+        }
+        $eiObjectStr .= "};";
+
+        # Print info to file
+        if ($eiEntryCount > 0)
+        {
+            print EIFILE "\\\n{ \\\n  $eiObjectStr \\\n";
+            print EIFILE "  fapi2::ErrorInfoEntry l_entries[$eiEntryCount]; \\\n";
+            print EIFILE "$eiEntryStr";
+            print EIFILE "  RC.addErrorInfo(l_objects, l_entries, $eiEntryCount); \\\n}";
+        }
+
+        print EIFILE "\n";
+
+        #----------------------------------------------------------------------
+        # Print the return code class to hwp_error_info.H
+        #----------------------------------------------------------------------
+        # Remove the repeated whitespace and newlines other characters from the description
+        $err->{description} =~ s/^\s+|\s+$|"//g;
+        $err->{description} =~ tr{\n}{ };
+        $err->{description} =~ s/\h+/ /g;
+
+        #----------------------------------------------------------------------
+        # Print the return code class to hwp_error_info.H
+        #----------------------------------------------------------------------
+        my $class_name = $err->{rc};
+        # Remove everything upto and including the first _. This makes the ffdc class
+        # names different from the error code value enum names.
+        $class_name = (split (/_/, $class_name, 2))[1];
+
+        # Class declaration
+        print ECFILE "\nclass $class_name\n{\n  public:\n";
+
+        # Constructor. This traces the description. If this is too much, we can
+        # remove it.
+        if ($arg_empty_ffdc eq undef)
+        {
+            print ECFILE "    $class_name(fapi2::errlSeverity_t i_sev = fapi2::FAPI2_ERRL_SEV_UNRECOVERABLE, fapi2::ReturnCode& i_rc = fapi2::current_err):\n";
+            print ECFILE "        iv_rc(i_rc),\n";
+            print ECFILE "        iv_sev(i_sev)\n";
+            print ECFILE "    { FAPI_ERR(\"$err->{description}\"); }\n";
+        }
+        else
+        {
+            # Void expression keeps the compiler from complaining about the unused arguments.
+            # We want to set the i_rc to the RC if we're empty. This otherwise gets done in _setHwpError()
+            print ECFILE "    $class_name(fapi2::errlSeverity_t i_sev = fapi2::FAPI2_ERRL_SEV_UNRECOVERABLE, fapi2::ReturnCode& i_rc = fapi2::current_err)\n";
+            print ECFILE "    {\n";
+            print ECFILE "        static_cast<void>(i_sev);\n";
+            print ECFILE "        i_rc = $err->{rc};\n";
+            print ECFILE "    }\n\n";
+        }
+
+        # Methods
+        foreach my $key (keys %methods)
+        {
+            print ECFILE $methods{$key}{method};
+        }
+
+        # Stick the execute method at the end of the other methods. We allow
+        # passing in of the severity so that macros which call execute() can over-ride
+        # the default severity.
+        print ECFILE "    void execute(fapi2::errlSeverity_t i_sev = fapi2::FAPI2_ERRL_SEV_UNDEFINED)\n";
+        if ($arg_empty_ffdc eq undef)
+        {
+            print ECFILE "    {\n";
+            print ECFILE "        FAPI_SET_HWP_ERROR(iv_rc, $err->{rc});\n";
+            print ECFILE "        fapi2::logError(iv_rc, (i_sev == fapi2::FAPI2_ERRL_SEV_UNDEFINED) ? iv_sev : i_sev);\n";
+            print ECFILE "    }\n\n";
+        }
+        else
+        {
+            print ECFILE "    {\n";
+            print ECFILE "        static_cast<void>(i_sev);\n";
+            print ECFILE "    }\n\n";
+        }
+
+        # Instance variables
+        if ($arg_empty_ffdc eq undef)
+        {
+            print ECFILE "  private:\n    ";
+            foreach my $key (keys %methods)
+            {
+                print ECFILE $methods{$key}{member};
+            }
+
+            print ECFILE "fapi2::ReturnCode& iv_rc;\n";
+            print ECFILE "    fapi2::errlSeverity_t iv_sev;\n";
+        }
+
+        print ECFILE "};\n\n\n\n";
+    }
+
+    #--------------------------------------------------------------------------
+    # For each registerFfdc.
+    #--------------------------------------------------------------------------
+    foreach my $registerFfdc (@{$errors->{registerFfdc}})
+    {
+        #----------------------------------------------------------------------
+        # Check that expected fields are present
+        #----------------------------------------------------------------------
+        if (! exists $registerFfdc->{id}[0])
+        {
+            print ("parseErrorInfo.pl ERROR. id missing from registerFfdc\n");
+            exit(1);
+        }
+
+        if (scalar @{$registerFfdc->{id}} > 1)
+        {
+            print ("parseErrorInfo.pl ERROR. multiple ids in registerFfdc\n");
+            exit(1);
+        }
+
+        #----------------------------------------------------------------------
+        # Set the FFDC ID value in a global hash
+        #----------------------------------------------------------------------
+        setFfdcIdValue($registerFfdc->{id}[0]);
+
+        #----------------------------------------------------------------------
+        # Generate code to capture the registers in collect_reg_ffdc.C
+        #----------------------------------------------------------------------
+        print CRFILE "        case $registerFfdc->{id}[0]:\n";
+
+=begin NEED_P9_REGISTERS
+        # Look for CFAM Register addresses
+        foreach my $cfamRegister (@{$registerFfdc->{cfamRegister}})
+        {
+            print CRFILE "            l_cfamAddresses.push_back($cfamRegister);\n";
+            print CRFILE "            l_ffdcSize += sizeof(l_cfamData);\n";
+        }
+
+        # Look for SCOM Register addresses
+        foreach my $scomRegister (@{$registerFfdc->{scomRegister}})
+        {
+            print CRFILE "            l_scomAddresses.push_back($scomRegister);\n";
+            print CRFILE "            l_ffdcSize += sizeof(l_scomData);\n";
+        }
+=cut NEED_P9_REGISTERS
+
+        print CRFILE "            break;\n";
+    }
+
+}
+
+#------------------------------------------------------------------------------
+# Print end of file information to collect_reg_ffdc.C
+#------------------------------------------------------------------------------
+print CRFILE "        default:\n";
+print CRFILE "            FAPI_ERR(\"collect_reg_ffdc.C: Invalid FFDC ID 0x%x\", ";
+print CRFILE                     "i_ffdcId);\n";
+print CRFILE "            return;\n";
+print CRFILE "    }\n\n";
+
+=begin NEED_P9_REGISTERS
+
+print CRFILE "    uint8_t * l_pBuf = NULL;\n";
+print CRFILE "    uint8_t * l_pData = NULL;\n";
+print CRFILE "    std::vector<fapi::Target> l_targets;\n";
+print CRFILE "    uint32_t l_chipletPos32 = 0;\n";
+#---------------------------------------------------------------------------------------------------------
+# Populate chiplet vectors (if required by register collection method) and adjust buffer sizes accordingly
+#---------------------------------------------------------------------------------------------------------
+print CRFILE "    if (fapi2::TARGET_TYPE_NONE != i_child)\n";
+print CRFILE "    {\n";
+print CRFILE "        l_rc = fapiGetChildChiplets(i_target, i_child, l_targets, TARGET_STATE_FUNCTIONAL);\n";
+print CRFILE "        if (l_rc)\n";
+print CRFILE "        {\n";
+print CRFILE "            FAPI_ERR(\"collect_reg_ffdc.C: Error: fapiGetChildChiplets: failed to get chiplets.\");\n";
+print CRFILE "            return;\n";
+print CRFILE "        }\n";
+print CRFILE "        if (l_targets.empty())\n";
+print CRFILE "        {\n";
+print CRFILE "            FAPI_INF(\"collect_reg_ffdc.C: Error: No functional chiplets found. \");\n";
+print CRFILE "            return;\n";
+print CRFILE "        }\n";
+print CRFILE "        l_ffdcSize += sizeof(l_chipletPos32);\n";
+print CRFILE "        l_ffdcSize *= l_targets.size();\n";
+print CRFILE "        l_pBuf = new uint8_t[l_ffdcSize];\n";
+print CRFILE "        l_pData = l_pBuf;\n";
+print CRFILE "    }\n";
+print CRFILE "    else if (fapi2::TARGET_TYPE_NONE != i_presChild)\n";
+print CRFILE "    {\n";
+print CRFILE "        l_rc = fapiGetChildChiplets(i_target, i_presChild, l_targets, TARGET_STATE_PRESENT);\n";
+print CRFILE "        if (l_rc)\n";
+print CRFILE "        {\n";
+print CRFILE "            FAPI_ERR(\"collect_reg_ffdc.C: Error: fapiGetChildChiplets: failed to get chiplets.\");\n";
+print CRFILE "            return;\n";
+print CRFILE "        }\n";
+print CRFILE "        if (l_targets.empty())\n";
+print CRFILE "        {\n";
+print CRFILE "            FAPI_INF(\"collect_reg_ffdc.C: Error: No functional chiplets found. \");\n";
+print CRFILE "            return;\n";
+print CRFILE "        }\n";
+print CRFILE "        l_ffdcSize += sizeof(l_chipletPos32);\n";
+print CRFILE "        l_ffdcSize *= l_targets.size();\n";
+print CRFILE "        l_pBuf = new uint8_t[l_ffdcSize];\n";
+print CRFILE "        l_pData = l_pBuf;\n";
+print CRFILE "    }\n";
+print CRFILE "    else\n";
+print CRFILE "    {\n";
+print CRFILE "        l_ffdcSize += sizeof(l_chipletPos32);\n";
+print CRFILE "        l_pBuf = new uint8_t[l_ffdcSize];\n";
+print CRFILE "        l_pData = l_pBuf;\n";
+print CRFILE "        l_targets.push_back(i_target);\n";
+print CRFILE "    }\n\n";
+#---------------------------------------------------------------------------------------------------------
+# Obtain target position and insert as the first word in the buffer
+#---------------------------------------------------------------------------------------------------------
+print CRFILE "    bool l_targIsChiplet = i_target.isChiplet();\n\n";
+print CRFILE "    for (std::vector<fapi::Target>::const_iterator targetIter = l_targets.begin();\n";
+print CRFILE "        targetIter != l_targets.end(); ++targetIter)\n";
+print CRFILE "    {\n";
+print CRFILE "        if ((fapi2::TARGET_TYPE_NONE != i_child) ||\n";
+print CRFILE "            (fapi2::TARGET_TYPE_NONE != i_presChild) ||\n";
+print CRFILE "            (true == l_targIsChiplet))\n";
+print CRFILE "        {\n";
+print CRFILE "            uint8_t l_chipletPos = 0;\n";
+print CRFILE "            l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*targetIter), l_chipletPos);\n";
+print CRFILE "            if (l_rc)\n";
+print CRFILE "            {\n";
+print CRFILE "                FAPI_ERR(\"collect_reg_ffdc.C: Error getting chiplet position\");\n";
+print CRFILE "                l_chipletPos = 0xFF;\n";
+print CRFILE "            }\n";
+                          #-------------------------------------------------------------------------
+                          # We print the target's position in the error log whether the target is a
+                          # chip or chiplet, so we need to store the chiplet position in a uint32_t
+                          # to have consitency in the buffer as ATTR_POS below returns a uint32_t
+                          #-------------------------------------------------------------------------
+print CRFILE "            l_chipletPos32 = l_chipletPos;\n";
+print CRFILE "        }\n";
+print CRFILE "        else\n";
+print CRFILE "        {\n";
+print CRFILE "            l_rc = FAPI_ATTR_GET(ATTR_POS, &(*targetIter), l_chipletPos32);\n";
+print CRFILE "            if (l_rc)\n";
+print CRFILE "            {\n";
+print CRFILE "                FAPI_ERR(\"collect_reg_ffdc.C: Error getting chip position\");\n";
+print CRFILE "                l_chipletPos32 = 0xFFFFFFFF;\n";
+print CRFILE "            }\n";
+print CRFILE "        }\n";
+print CRFILE "        *(reinterpret_cast<uint32_t *>(l_pData)) = l_chipletPos32;\n";
+print CRFILE "        l_pData += sizeof(l_chipletPos32);\n";
+#---------------------------------------------------------------------------------------------------------
+# Instert cfam data (if any) related to this chip / chiplet into the buffer
+# If collecting FFDC based on present children, adjust the register address by the appropriate offset
+#---------------------------------------------------------------------------------------------------------
+print CRFILE "        for (std::vector<uint32_t>::const_iterator cfamIter = l_cfamAddresses.begin();\n";
+print CRFILE "             cfamIter != l_cfamAddresses.end(); ++cfamIter)\n";
+print CRFILE "        {\n";
+print CRFILE "            if (fapi2::TARGET_TYPE_NONE != i_presChild)\n";
+print CRFILE "            {\n";
+print CRFILE "                l_rc = fapiGetCfamRegister(i_target, (*cfamIter + (l_chipletPos32 * i_childOffsetMult)), l_buf);\n";
+print CRFILE "            }\n";
+print CRFILE "            else\n";
+print CRFILE "            {\n";
+print CRFILE "                l_rc = fapiGetCfamRegister(*targetIter, *cfamIter, l_buf);\n";
+print CRFILE "            }\n";
+print CRFILE "            if (l_rc)\n";
+print CRFILE "            {\n";
+print CRFILE "                FAPI_ERR(\"collect_reg_ffdc.C: CFAM error for 0x%x\",";
+print CRFILE                          "*cfamIter);\n";
+print CRFILE "                l_cfamData = 0xbaddbadd;\n";
+print CRFILE "            }\n";
+print CRFILE "            else\n";
+print CRFILE "            {\n";
+print CRFILE "                l_cfamData = l_buf.getWord(0);\n";
+print CRFILE "            }\n";
+print CRFILE "            *(reinterpret_cast<uint32_t *>(l_pData)) = l_cfamData;\n";
+print CRFILE "            l_pData += sizeof(l_cfamData);\n";
+print CRFILE "        }\n\n";
+#---------------------------------------------------------------------------------------------------------
+# Instert any scom data (if any) related to this chip / chiplet into the buffer
+# If collecting FFDC based on present children, adjust the register address by the appropriate offset
+#---------------------------------------------------------------------------------------------------------
+print CRFILE "        for (std::vector<uint64_t>::const_iterator scomIter = l_scomAddresses.begin();\n";
+print CRFILE "            scomIter != l_scomAddresses.end(); ++scomIter)\n";
+print CRFILE "        {\n";
+print CRFILE "            if (fapi2::TARGET_TYPE_NONE != i_presChild)\n";
+print CRFILE "            {\n";
+print CRFILE "                l_rc = fapiGetScom(i_target, (*scomIter + (l_chipletPos32 * i_childOffsetMult)), l_buf);\n";
+print CRFILE "            }\n";
+print CRFILE "            else\n";
+print CRFILE "            {\n";
+print CRFILE "                l_rc = fapiGetScom(*targetIter, *scomIter, l_buf);\n";
+print CRFILE "            }\n";
+print CRFILE "            if (l_rc)\n";
+print CRFILE "            {\n";
+print CRFILE "                FAPI_ERR(\"collect_reg_ffdc.C: SCOM error for 0x%llx\",";
+print CRFILE                         "*scomIter);\n";
+print CRFILE "                l_scomData = 0xbaddbaddbaddbaddULL;\n";
+print CRFILE "            }\n";
+print CRFILE "            else\n";
+print CRFILE "            {\n";
+print CRFILE "                 l_scomData = l_buf.getDoubleWord(0);\n";
+print CRFILE "            }\n";
+print CRFILE "            *(reinterpret_cast<uint64_t *>(l_pData)) = l_scomData;\n";
+print CRFILE "            l_pData += sizeof(l_scomData);\n";
+print CRFILE "        }\n";
+print CRFILE "    }\n\n";
+print CRFILE "    o_rc.addEIFfdc(i_ffdcId, l_pBuf, l_ffdcSize);\n";
+print CRFILE "    delete [] l_pBuf;\n";
+=cut NEED_P9_REGISTERS
+
+print CRFILE "}\n";
+print CRFILE "}\n";
+
+
+#------------------------------------------------------------------------------
+# Print the fapiHwpReturnCodes.H file
+#------------------------------------------------------------------------------
+print RCFILE "// fapiHwpReturnCodes.H\n";
+print RCFILE "// This file is generated by perl script parseErrorInfo.pl\n\n";
+print RCFILE "#ifndef FAPI2_HWPRETURNCODES_H_\n";
+print RCFILE "#define FAPI2_HWPRETURNCODES_H_\n\n";
+print RCFILE "#ifndef __ASSEMBLER__\n";
+print RCFILE "namespace fapi2\n";
+print RCFILE "{\n\n";
+print RCFILE "/**\n";
+print RCFILE " * \@brief Enumeration of HWP return codes\n";
+print RCFILE " *\/\n";
+print RCFILE "enum HwpReturnCode\n";
+print RCFILE "{\n";
+foreach my $key (keys %errNameToValueHash)
+{
+    print RCFILE "    $key = 0x$errNameToValueHash{$key},\n";
+}
+print RCFILE "};\n\n";
+print RCFILE "}\n\n";
+print RCFILE "#else\n";
+foreach my $key (keys %errNameToValueHash)
+{
+    print RCFILE "    .set $key, 0x$errNameToValueHash{$key}\n";
+}
+print RCFILE "#endif\n";
+print RCFILE "#endif\n";
+
+#------------------------------------------------------------------------------
+# Print the HwpFfdcId enumeration to hwp_error_info.H
+#------------------------------------------------------------------------------
+print EIFILE "namespace fapi2\n";
+print EIFILE "{\n\n";
+print EIFILE "/**\n";
+print EIFILE " * \@brief Enumeration of FFDC identifiers\n";
+print EIFILE " *\/\n";
+print EIFILE "enum HwpFfdcId\n";
+print EIFILE "{\n";
+foreach my $key (keys %ffdcNameToValueHash)
+{
+    print EIFILE "    $key = 0x$ffdcNameToValueHash{$key},\n";
+}
+print EIFILE "};\n\n";
+print EIFILE "}\n\n";
+
+#------------------------------------------------------------------------------
+# Print end of file information to hwp_error_info.H
+#------------------------------------------------------------------------------
+print EIFILE "\n\n#endif\n";
+
+#------------------------------------------------------------------------------
+# Print end of file information to hwp_ffdc_classes.H
+#------------------------------------------------------------------------------
+print ECFILE "\n};\n"; # close the namespace
+print ECFILE "\n\n#endif\n";
+
+#------------------------------------------------------------------------------
+# Print end of file information to set_sbe_error.H
+#------------------------------------------------------------------------------
+print SBFILE "    default:\\\n";
+print SBFILE "        FAPI_SET_HWP_ERROR(RC, RC_SBE_UNKNOWN_ERROR);\\\n";
+print SBFILE "        break;\\\n";
+print SBFILE "}\\\n";
+print SBFILE "}\n\n";
+print SBFILE "#endif\n";
+
+#------------------------------------------------------------------------------
+# Close output files
+#------------------------------------------------------------------------------
+close(RCFILE);
+close(EIFILE);
+close(ECFILE);
+close(CRFILE);
+close(SBFILE);
diff --git a/src/ppe/tools/scripts/ppeCreateAttrGetSetMacros.pl b/src/ppe/tools/scripts/ppeCreateAttrGetSetMacros.pl
new file mode 100755
index 0000000..0948e2d
--- /dev/null
+++ b/src/ppe/tools/scripts/ppeCreateAttrGetSetMacros.pl
@@ -0,0 +1,557 @@
+#!/usr/bin/perl -w
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ppe/tools/scripts/ppeCreateAttrGetSetMacros.pl $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#find enums in AttributeId
+#for each enum check for ${enum}_Type
+#check for type and array values
+#Check Plat file for ${enum}_GETMACRO and ${enum}_SETMACRO
+#If they do not exist add apporpriate _SETMACRO and _GETMACRO to Plat file
+
+use strict;
+use File::Copy;
+use Getopt::Long;
+
+sub enumParser ($);
+sub help;
+
+my $DEBUG = 0;
+my $VERBOSE = 0;
+
+my $state = 0;
+my $last_value = -1;
+my $current_entry;
+my $current_enum_name;
+
+my %enums;
+
+my %attributeTypes;
+my %attributeArrayTypes;
+
+my %getMacros;
+my %setMacros;
+my %targetMacros;
+
+
+
+my $fapiAttributeIdsFile = "fapi2AttributeIds.H";
+my $fapiPlatAttributeServiceFile= "fapi2PlatAttributeService.H";
+my $fapiPlatAttributeServiceImpl= "fapi2PlatAttributeService.C";
+
+
+my $includePath = "./";
+my $srcPath = "./";
+
+my @newAttributeDefines;
+my @newTargetDefines;
+my @newTargetImplementations;
+
+
+my $servicePath;
+my $help;
+
+GetOptions ("verbose" => \$VERBOSE, 
+            "help" => \$help,
+            "debug" => \$DEBUG,
+            "path=s" => \$servicePath,
+            "inc=s" => \$includePath,
+            "src=s" => \$srcPath,
+);
+
+help() if $help;
+
+open (FILE, $includePath . "/" . $fapiAttributeIdsFile) or die "ERROR:: could not open $fapiAttributeIdsFile\n";
+
+while (<FILE>) {
+  # attempt to parse attributes from current line in file
+  enumParser($_);
+
+  # see if the line describes an attribute
+  if (m/\s*typedef\s+(\w+)\s+(\w+)_Type(\S*)\s*;/) {
+    my $type = $1;
+    my $attribute = $2;
+    my $arrayType = $3;
+
+    if ($DEBUG) { print "DEBUG:: type = $type : attribute = $attribute : arrayType = $arrayType\n"; }
+
+    # save attribute type and if it is an array and its size
+    $attributeTypes{$attribute} = $type;
+    if ($arrayType) {
+      $attributeArrayTypes{$attribute} = $arrayType;
+    } else {
+      $attributeArrayTypes{$attribute} = "none";
+    }
+  }
+
+  # look for MACROs
+  # look for: #define ATTR_CHIP_HAS_SBE_GETMACRO ATTRIBUTE_NOT_WRITABLE
+  if (m/\s*#define\s+(\w+)_GETMACRO\s+(\S+)\s*/) {
+    $getMacros{$1} = $2;
+    if ($DEBUG) { print "DEBUG:: attribute = $1 : GETMACRO = $2\n"; }
+  # look for: #define ATTR_CHIP_EC_FEATURE_TEST1_GETMACRO(ID, PTARGET, VAL) fapi::fapiQueryChipEcFeature(ID, PTARGET, VAL)
+  } elsif (m/\s*#define\s+(\w+)_GETMACRO\(ID\,\sPTARGET\,\sVAL\)\s(.+)/) {
+    $getMacros{$1} = $2;
+    if ($DEBUG) { print "DEBUG:: attribute = $1 : GETMACRO = $2\n"; }
+  # look for: #define ATTR_CHIP_HAS_SBE_SETMACRO ATTRIBUTE_NOT_WRITABLE
+  } elsif (m/\s*#define\s+(\w+)_SETMACRO\s+(\S+)\s*/) {
+    $setMacros{$1} = $2;
+    if ($DEBUG) { print "DEBUG:: attribute = $1 : SETMACRO = $2\n"; }
+  # look for: #define ATTR_CHIP_EC_FEATURE_TEST2_SETMACRO(ID, PTARGET, VAL) CHIP_EC_FEATURE_ATTRIBUTE_NOT_WRITABLE
+  } elsif (m/\s*#define\s+(\w+)_SETMACRO\(ID\,\sPTARGET\,\sVAL\)\s(.+)/) {
+    $setMacros{$1} = $2;
+    if ($DEBUG) { print "DEBUG:: attribute = $1 : SETMACRO = $2\n"; }
+  } elsif (m/\s*const\s*TargetTypes_t\s+(\w+)_TargetTypes\s*=\s*(\S+)\s*;\s*/) {
+    $targetMacros{$1} = $2;
+#    print "DEBUG:: attribute = $1 : TARGET = $2\n";
+    if ($DEBUG) { print "DEBUG:: attribute = $1 : TARGET = $2\n"; }
+  }
+}
+
+close (FILE);
+
+#find copy of fapiPlatAttributeService.H
+if (!$servicePath) {
+  #$CTEPATH/tools/ecmd/$ECMD_RELEASE/ext/fapi/capi
+  my $ctepath = $ENV{CTEPATH};
+  my $ecmd_release = $ENV{ECMD_RELEASE};
+  if ($DEBUG) { print "DEBUG:: ctepath = $ctepath\n"; }
+  if ($DEBUG) { print "DEBUG:: ecmd_release = $ecmd_release\n"; }
+  if (!$ctepath) {
+    print "ERROR:: environment variable CTEPATH not defined!\n";
+    exit 1;
+  }
+  if (!$ecmd_release) {
+    print "ERROR:: environment variable ECMD_RELEASE not defined!\n";
+    exit 1;
+  }
+  $servicePath = "$ctepath/tools/ecmd/$ecmd_release/ext/fapi/capi";
+}
+
+if ($DEBUG) { print "DEBUG:: servicePath = $servicePath\n"; }
+
+# test that servicePath exists
+if (!-d $servicePath) {
+  print "ERROR:: path $servicePath does not exist!\n";
+  exit 1;
+}
+
+# test that fapiPlatAttributeService.H is in that directory
+if (!-f "$servicePath/$fapiPlatAttributeServiceFile") {
+  print "ERROR:: $fapiPlatAttributeServiceFile does not exist in $servicePath\n";
+  exit 1;
+}
+
+# copy fapiPlatAttributeService.H to local dir
+#my $systemRc = system("cp $servicePath/$fapiPlatAttributeServiceFile $includePath");
+copy("$servicePath/$fapiPlatAttributeServiceFile","$includePath") or die "Copy failed: $!";
+
+#if ($systemRc) {
+#  print "ERROR:: error copying $fapiPlatAttributeServiceFile from $servicePath\n";
+#  exit 1;
+#}
+
+
+
+# look in fapiPlatAttributeService.H for MACROs
+open (FILE, $includePath . "/". $fapiPlatAttributeServiceFile) or die "ERROR:: could not open $fapiPlatAttributeServiceFile\n";
+while (<FILE>) {
+  if (m/\s*#define\s+(\w+)_GETMACRO\s+(\S+)\s*/) {
+    $getMacros{$1} = $2;
+    if ($DEBUG) { print "DEBUG:: attribute = $1 : GETMACRO = $2\n"; }
+  } elsif (m/\s*#define\s+(\w+)_SETMACRO\s+(\S+)\s*/) {
+    $setMacros{$1} = $2;
+    if ($DEBUG) { print "DEBUG:: attribute = $1 : SETMACRO = $2\n"; }
+  } elsif (m/\s*const\s*TargetTypes_t\s+(\w+)_TargetTypes\s*=\s*(\S+)\s*;\s*/) {
+    $targetMacros{$1} = $2;
+    if ($DEBUG) { print "DEBUG:: attribute = $1 : TARGET = $2\n"; }
+  }
+}
+close (FILE);
+
+# go through attributes found in file
+for my $attribute (sort keys %{$enums{AttributeId}}) {
+  if ($DEBUG) { print "DEBUG:: attribute = $attribute\n"; }
+  my $type;
+  my $arrayType;
+  my $dimension = 0;
+
+  # check that each attribute has attributeType
+  if ($attributeTypes{$attribute}) {
+    if ($attributeArrayTypes{$attribute}) {
+      $type = $attributeTypes{$attribute};
+      $arrayType = $attributeArrayTypes{$attribute};
+    } else {
+      print "ERROR:: arrayType not found for $attribute\n";
+      next;
+    }
+  } else {
+    print "ERROR:: type not found for $attribute\n";
+    next;
+  }
+
+  # determine if attribute is an array
+  if ($arrayType =~ m/none/) {
+    if ($DEBUG) { print "DEBUG:: $attribute = $type\n"; }
+  } else {
+    # find dimension for array
+    my $tempArrayType = $arrayType;
+    while ($tempArrayType =~ m/\[\d*\].*/) {
+      $dimension++;
+      $tempArrayType =~ s/\[\d*\]//;
+    }
+    if ($DEBUG) { print "DEBUG:: $attribute = $type$arrayType dimension = $dimension\n"; }
+  }
+
+  my $setMacro = $setMacros{$attribute};
+  my $getMacro = $getMacros{$attribute};
+  my $targetMacro = $targetMacros{$attribute};
+
+#  print "$attribute $setMacro $getMacro $targetMacro \n";
+
+  # if an attribute is missing the SET or GET MACRO add to list in insert into file later
+  if (!($getMacro && $setMacro)) {
+    my $macroPrefix = "PLAT_ATTR_";
+    my $macroPostfix = "";
+
+    if ($dimension == 0) {
+      $macroPostfix = "_GLOBAL_INT";
+    } else {
+      if ($type =~ m/uint8_t/) {
+        $macroPostfix = "_UINT8_" . $dimension . "D_ARRAY";
+      } elsif ($type =~ m/uint32_t/) {
+        $macroPostfix = "_UINT32_" . $dimension . "D_ARRAY";
+      } elsif ($type =~ m/uint64_t/) {
+        $macroPostfix = "_UINT64_" . $dimension . "D_ARRAY";
+      } elsif ($type =~ m/int8_t/) {
+        $macroPostfix = "_INT8_" . $dimension . "D_ARRAY";
+      } elsif ($type =~ m/int32_t/) {
+        $macroPostfix = "_INT32_" . $dimension . "D_ARRAY";
+      } elsif ($type =~ m/int64_t/) {
+        $macroPostfix = "_INT64_" . $dimension . "D_ARRAY";
+      } else {
+        print "ERROR:: unknown type $type for attribute $attribute\n";
+        next;
+      }
+    }
+
+    my $macroTarget = "";
+    if(defined $targetMacro) {
+        if($targetMacro eq "TARGET_TYPE_PROC_CHIP") {
+            $macroTarget = "ProcChipAttributes_t";
+        } elsif ($targetMacro eq "TARGET_TYPE_CORE") {
+            $macroTarget = "CoreAttributes_t";
+        } elsif ($targetMacro eq "TARGET_TYPE_EX") {
+            $macroTarget = "EXAttributes_t";
+        } elsif ($targetMacro eq "TARGET_TYPE_EQ") {
+            $macroTarget = "EQAttributes_t";
+        } elsif ($targetMacro eq "TARGET_TYPE_PERV") {
+            $macroTarget = "PervAttributes_t";
+        } else {
+        print "ERROR:: unknown type $targetMacro for attribute $attribute\n";
+        next;
+      }
+    }
+
+    if (!$getMacro) {
+      if ($VERBOSE) { print "INFO:: did not find ${attribute}_GETMACRO\n"; }
+      my $attributeDefine = "#define ${attribute}_GETMACRO ${macroPrefix}GET${macroPostfix}";
+      push(@newAttributeDefines, $attributeDefine);
+      
+      if(defined $targetMacro) {
+
+
+          my $targetFunction = "template<> void __get<fapi2::$targetMacro, fapi2attr::$macroTarget, $type, fapi2::${attribute}>   ( const fapi2::Target<fapi2::$targetMacro>* i_ptarget, fapi2attr::$macroTarget* object, const fapi2::AttributeId attrid, $type *value )";
+          push(@newTargetDefines, $targetFunction . ";");
+
+          my $targetImplementation = "";
+          if($targetMacro eq "TARGET_TYPE_PROC_CHIP") {
+
+              $targetImplementation .= "\n" . $targetFunction . "\n{\n   *value = object->fapi2attr::${macroTarget}::${attribute};\n}\n";
+           
+          } else {
+
+              $targetImplementation .= "\n" . $targetFunction . "\n{\n   uint32_t index = (i_ptarget)->getTargetNumber();\n   *value = object->fapi2attr::${macroTarget}::${attribute}[index];\n}\n";
+
+          }
+          push(@newTargetImplementations, $targetImplementation);
+      }
+    }
+    if (!$setMacro) {
+      if ($VERBOSE) { print "INFO:: did not find ${attribute}_SETMACRO\n"; }
+      my $attributeDefine = "#define ${attribute}_SETMACRO ${macroPrefix}SET${macroPostfix}";
+      push(@newAttributeDefines, $attributeDefine);
+
+      if(defined $targetMacro) {
+
+          my $targetFunction = "template<> void __set<fapi2::$targetMacro, fapi2attr::$macroTarget, $type, fapi2::${attribute}>   ( const fapi2::Target<fapi2::$targetMacro>* i_ptarget, fapi2attr::$macroTarget* object, const fapi2::AttributeId attrid,  $type* value )";
+          push(@newTargetDefines, $targetFunction . ";");
+
+          my $targetImplementation = "";
+
+          if($targetMacro eq "TARGET_TYPE_PROC_CHIP") {
+
+              $targetImplementation = "\n" . $targetFunction . "\n{\n  object->fapi2attr::${macroTarget}::${attribute} = *value;\n}\n";
+          } else {
+              $targetImplementation = "\n" . $targetFunction . "\n{\n   uint32_t index = (i_ptarget)->getTargetNumber();\n   object->fapi2attr::${macroTarget}::${attribute}[index] = *value;\n}\n";
+          }
+
+          push(@newTargetImplementations, $targetImplementation);
+      }
+    }
+  }
+}
+
+# if file is missing any GET or SET MACROs
+if (@newAttributeDefines != 0) {
+
+  my $updatedFapiPlatAttributeServiceFile = "$fapiPlatAttributeServiceFile.temp";
+  open (OUTFILE, ">$updatedFapiPlatAttributeServiceFile") or die "ERROR:: could not open $updatedFapiPlatAttributeServiceFile\n";
+  open (FILE, $includePath . "/" . $fapiPlatAttributeServiceFile) or die "ERROR:: could not open $fapiPlatAttributeServiceFile\n";
+
+  my $insertTagFound = 0;
+
+  while (<FILE>) {
+    print OUTFILE $_;
+    # search for tag to insert after
+    if (m/\/\*.*INSERT NEW ATTRIBUTES HERE.*\*\//) {
+      $insertTagFound = 1;
+      # insert missing GET or SET MACROs
+      print OUTFILE "\n";
+      foreach my $attributeDefine (@newAttributeDefines) {
+        print OUTFILE "$attributeDefine\n";
+        if ($VERBOSE) { print "INFO:: adding $attributeDefine\n"; }
+      }
+    }
+
+    if (m/\/\*.*INSERT NEW GETTER AND SETTER FUNCTIONS HERE.*\*\//) {
+
+      $insertTagFound = 1;
+      # insert missing GET or SET MACROs
+      print OUTFILE "\n";
+      foreach my $targetDefine (@newTargetDefines) {
+        print OUTFILE "$targetDefine\n";
+        if ($VERBOSE) { print "INFO:: adding getter setter method\n"; }
+      }
+    }
+
+
+  }
+  close (FILE);
+  close (OUTFILE);
+
+  if ($insertTagFound == 0) {
+    # remove file that we did not update
+    system("rm $updatedFapiPlatAttributeServiceFile");
+    print ("WARNING:: did not find tag \"INSERT NEW ATTRIBUTES HERE\" in $fapiPlatAttributeServiceFile. no updates performed.\n");
+  } else {
+    # copy new file over the old one
+    system("mv $updatedFapiPlatAttributeServiceFile $includePath/$fapiPlatAttributeServiceFile");
+  }
+
+
+  my $updatedFapiPlatAttributeServiceImpl = $srcPath . "/" . $fapiPlatAttributeServiceImpl; 
+  open (OUTFILE, ">$updatedFapiPlatAttributeServiceImpl") or die "ERROR:: could not open $updatedFapiPlatAttributeServiceImpl\n";
+
+  print OUTFILE "// $fapiPlatAttributeServiceImpl\n";
+  print OUTFILE "// This file is generated by perl script ppeCreateAttrGetSetMacros.pl\n\n";
+
+  print OUTFILE "#include <fapi2.H>\n";
+  print OUTFILE "#include <fapi2PlatAttributeService.H>\n";
+  print OUTFILE "#include \"proc_sbe_fixed.H\"\n";
+  print OUTFILE "#include \"plat_target_parms.H\"\n\n";
+  print OUTFILE "namespace fapi2 {\n";
+
+
+  foreach my $impl (@newTargetImplementations) {
+   
+      print OUTFILE $impl;
+
+  }
+
+  print OUTFILE "\n} // namespace fapi2\n";
+
+
+  close (OUTFILE);
+}
+
+
+
+
+exit;
+
+# enumParser state machine
+#     "enum"      "enum_name"      "{"        "entry"          "}"
+# [0] ------> [1] -------------> [2] ---> [3] -----------> [4] -------------------------------------> [7]
+#                                                      ","     "="       "value"       "}"
+#                                         [3] <----------- [4] ----> [5] --------> [6] -------------> [7]
+#                                              "}"                                                        ";"
+#                                         [3]  -----------------------------------------------------> [7] ---> [0]
+#                                                                              ","
+#
+#                                         [3] <----------------------------------- [6]
+#
+
+sub enumParser ($){
+  my $line = $_[0];
+  chomp($line);
+
+  if ($DEBUG) { print "DEBUG:: state = $state : line = \"$line\"\n"; }
+
+  if ($state == 0) {
+    # find enum as first word
+    if ($line =~ m/\s*enum\s*.*/) {
+      if ($DEBUG) { print "DEBUG:: found enum in $line\n"; }
+      $state = 1;
+      # reset last_value
+      $last_value = -1;
+      # reset current_entry
+      $current_entry = "";
+      # reset current_enum_name;
+      $current_enum_name = "";
+      # remove enum from line recheck
+      $line =~ s/\s*enum\s*//;
+      enumParser($line);
+    }
+  } elsif ($state == 1) {
+    # find ENUM_NAME as first word
+    if ($line =~ m/\s*(\w+)\s*.*/) {
+      if ($DEBUG) { print "DEBUG:: found ENUM_NAME $1 in $line\n"; }
+      $state = 2;
+      my $enum_name = $1;
+      $current_enum_name = $enum_name;
+      # remove ENUM_NAME from line
+      $line =~ s/\s*$enum_name\s*//;
+      #recheck
+      enumParser($line);
+    }
+  } elsif ($state == 2) {
+    # find { as first word
+    if ($line =~ m/\s*{\s*.*/) {
+      if ($DEBUG) { print "DEBUG:: found { in $line\n"; }
+      $state = 3;
+      # remove { from line recheck
+      $line =~ s/\s*{\s*//;
+      enumParser($line);
+    }
+  } elsif ($state == 3) {
+    # find ENTRY as first word
+    if ($line =~ m/\s*(\w+)\s*.*/) {
+      if ($DEBUG) { print "DEBUG:: found ENTRY $1 in $line\n"; }
+      my $entry = $1;
+      $current_entry = $entry;
+      # remove ENTRY from line
+      $line =~ s/\s*$entry\s*//;
+      $state = 4;
+      #recheck
+      enumParser($line);
+    }
+    # find } as first word
+    elsif ($line =~ m/\s*}\s*.*/) {
+      if ($DEBUG) { print "DEBUG:: found } in $line\n"; }
+      $state = 7;
+      # remove } from line recheck
+      $line =~ s/\s*}\s*//;
+      enumParser($line);
+    }
+  } elsif ($state == 4) {
+    # find = as first word
+    if ($line =~ m/\s*=\s*.*/) {
+      if ($DEBUG) { print "DEBUG:: found = in $line\n"; }
+      $state = 5;
+      # remove = from line recheck
+      $line =~ s/\s*=\s*//;
+      enumParser($line);
+    }
+    # find , as first word
+    elsif ($line =~ m/\s*,\s*.*/) {
+      if ($DEBUG) { print "DEBUG:: found , in $line\n"; }
+      $state = 3;
+      # assign next last_value to entry
+      $last_value++;
+      my $value = $last_value;
+      if ($DEBUG) { print "DEBUG:: default VALUE $value assigned to $current_entry\n"; }
+      $enums{$current_enum_name}{$current_entry} = $value;
+      # remove , from line recheck
+      $line =~ s/\s*,\s*//;
+      enumParser($line);
+    }
+    # find } as first word
+    elsif ($line =~ m/\s*}\s*.*/) {
+      if ($DEBUG) { print "DEBUG:: found } in $line\n"; }
+      $state = 7;
+      # remove } from line recheck
+      $line =~ s/\s*}\s*//;
+      enumParser($line);
+    }
+  } elsif ($state == 5) {
+    # find VALUE as first word
+    if ($line =~ m/\s*(\w+)\s*.*/) {
+      if ($DEBUG) { print "DEBUG:: found VALUE $1 in $line\n"; }
+      my $value = $1;
+      $last_value = $value;
+      # assign value to entry
+      if ($DEBUG) { print "DEBUG:: VALUE $value assigned to $current_entry\n"; }
+      $enums{$current_enum_name}{$current_entry} = $value;
+      # remove VALUE from line
+      $line =~ s/\s*$value\s*//;
+      $state = 6;
+      #recheck
+      enumParser($line);
+    }
+  } elsif ($state == 6) {
+    # find , as first word
+    if ($line =~ m/\s*,\s*.*/) {
+      if ($DEBUG) { print "DEBUG:: found , in $line\n"; }
+      $state = 3;
+      # remove , from line recheck
+      $line =~ s/\s*,\s*//;
+      enumParser($line);
+    }
+    # find } as first word
+    elsif ($line =~ m/\s*}\s*.*/) {
+      if ($DEBUG) { print "DEBUG:: found } in $line\n"; }
+      $state = 7;
+      # remove } from line recheck
+      $line =~ s/\s*}\s*//;
+      enumParser($line);
+    }
+  } elsif ($state == 7) {
+    # find ; as first word
+    if ($line =~ m/\s*;\s*.*/) {
+      if ($DEBUG) { print "DEBUG:: found ; in $line\n"; }
+      $state = 0;
+      # remove ; from line recheck
+      $line =~ s/\s*;\s*//;
+      enumParser($line);
+    }
+  }
+}
+
+sub help {
+  printf("Usage:  ppeCreateAttrGetSetMacros.pl [--path <pathToFapiHeaders>] [--verbose] [--help] [--src <pathToFapiTemplate>] [--inc <pathToFapiOutput]\n");
+  printf("-path <pathToFapiHeaders>     Option to enable specifying alternate path to fapi headers\n");
+  printf("-v | -verbose     Inform user of findings and changes\n");
+  printf("-h | -help        print this message\n");
+  exit(0);
+}
diff --git a/src/ppe/tools/scripts/ppeCreateIfAttrService.pl b/src/ppe/tools/scripts/ppeCreateIfAttrService.pl
new file mode 100755
index 0000000..a6abbfe
--- /dev/null
+++ b/src/ppe/tools/scripts/ppeCreateIfAttrService.pl
@@ -0,0 +1,241 @@
+#!/usr/bin/perl
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ppe/tools/scripts/ppeCreateIfAttrService.pl $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+# Purpose:  This perl script will parse HWP Attribute XML files and
+# initfile attr files and create the fapiGetInitFileAttr() function
+# in a file called fapi2AttributeService.C
+
+use strict;
+
+#------------------------------------------------------------------------------
+# Print Command Line Help
+#------------------------------------------------------------------------------
+my $numArgs = $#ARGV + 1;
+if ($numArgs < 3)
+{
+    print ("Usage: fapi2CreateIfAttrService.pl <output dir>\n");
+    print ("           [<if-attr-file1> <if-attr-file2> ...]\n");
+    print ("           -a <attr-xml-file1> [<attr-xml-file2> ...]\n");
+    print ("  This perl script will parse if-attr files (containing the\n");
+    print ("  attributes used by the initfile) and attribute XML files\n");
+    print ("  (containing all HWPF attributes) and create the\n");
+    print ("  fapiGetInitFileAttr() function in a file called\n");
+    print ("  fapiAttributeService.C. Only the attributes specified in\n");
+    print ("  the if-attr files are supported. If no if-attr files are\n");
+    print ("  specified then all attributes are supported\n");
+    exit(1);
+}
+
+#------------------------------------------------------------------------------
+# Specify perl modules to use
+#------------------------------------------------------------------------------
+use XML::Simple;
+my $xml = new XML::Simple (KeyAttr=>[]);
+
+# Uncomment to enable debug output
+#use Data::Dumper;
+
+#------------------------------------------------------------------------------
+# Open output file for writing
+#------------------------------------------------------------------------------
+my $asFile = $ARGV[0];
+$asFile .= "/";
+$asFile .= "fapi2AttributeService.C";
+open(ASFILE, ">", $asFile);
+
+#------------------------------------------------------------------------------
+# Print Start of file information to fapiAttributeService.C
+#------------------------------------------------------------------------------
+print ASFILE "// fapi2AttributeService.C\n";
+print ASFILE "// This file is generated by perl script fapi2CreateIfAttrService.pl\n\n";
+print ASFILE "#include <fapi2AttributeService.H>\n";
+print ASFILE "//#include <fapi2ChipEcFeature.H>\n";
+print ASFILE "//#include <fapi2PlatTrace.H>\n\n";
+print ASFILE "namespace fapi2\n";
+print ASFILE "{\n\n";
+print ASFILE "ReturnCode fapiGetInitFileAttr(const AttributeId i_id,\n";
+print ASFILE "                               const Target * i_pTarget,\n";
+print ASFILE "                               uint64_t & o_val,\n";
+print ASFILE "                               const uint32_t i_arrayIndex1,\n";
+print ASFILE "                               const uint32_t i_arrayIndex2,\n";
+print ASFILE "                               const uint32_t i_arrayIndex3,\n";
+print ASFILE "                               const uint32_t i_arrayIndex4)\n";
+print ASFILE "{\n";
+print ASFILE "    ReturnCode l_rc;\n\n";
+
+my $xmlFiles = 0;
+my $attCount = 0;
+my $numIfAttrFiles = 0;
+my @attrIds;
+
+#------------------------------------------------------------------------------
+# Element names
+#------------------------------------------------------------------------------
+my $attribute = 'attribute';
+
+#------------------------------------------------------------------------------
+# For each argument
+#------------------------------------------------------------------------------
+my $argfile = $ARGV[1];
+my $entries = $xml->XMLin($argfile, ForceArray => ['entry']);
+foreach my $entr (@{$entries->{entry}}) {
+
+    my $inname = $entr->{name};
+
+    # read XML file. The ForceArray option ensures that there is an array of
+    # elements even if there is only one such element in the file
+
+    foreach my $argnum (2 .. $#ARGV)
+    {
+        my $infile = $ARGV[$argnum];
+
+        my $attributes = $xml->XMLin($infile, ForceArray => ['attribute']);
+
+        # Uncomment to get debug output of all attributes
+        #print "\nFile: ", $infile, "\n", Dumper($attributes), "\n";
+
+        #--------------------------------------------------------------------------
+        # For each Attribute
+        #--------------------------------------------------------------------------
+        foreach my $attr (@{$attributes->{attribute}})
+        {
+
+
+
+            if($attr->{id} eq $inname) {
+
+            #------------------------------------------------------------------
+            # Check that the AttributeId exists
+            #------------------------------------------------------------------
+            if (! exists $attr->{id})
+            {
+                print ("fapiParseAttributeInfo.pl ERROR. Att 'id' missing\n");
+                exit(1);
+            }
+
+
+            #------------------------------------------------------------------
+            # Figure out the number of attribute array dimensions
+            #------------------------------------------------------------------
+            my $numArrayDimensions = 0;
+            if ($attr->{array})
+            {
+                # Remove leading whitespace
+                my $dimText = $attr->{array};
+                $dimText =~ s/^\s+//;
+
+                # Split on commas or whitespace
+                my @vals = split(/\s*,\s*|\s+/, $dimText);
+
+                $numArrayDimensions=@vals;
+            }
+
+            #------------------------------------------------------------------
+            # Print the attribute get code to fapiAttributeService.C
+            #------------------------------------------------------------------
+            if ($attCount > 0)
+            {
+                print ASFILE "    else ";
+            }
+            else
+            {
+                print ASFILE "    ";
+            }
+            $attCount++;
+
+            print ASFILE "if (i_id == $attr->{id})\n";
+            print ASFILE "    {\n"; 
+            print ASFILE "        $attr->{id}_Type l_attr;\n";
+
+            if (exists $attr->{privileged})
+            {
+                print ASFILE "        l_rc = FAPI_ATTR_GET_PRIVILEGED($attr->{id}, i_pTarget, l_attr);\n";
+            }
+            else
+            {
+                print ASFILE "        l_rc = FAPI_ATTR_GET($attr->{id}, i_pTarget, l_attr);\n";
+            }
+            print ASFILE "        o_val = l_attr";
+
+            if ($numArrayDimensions >= 5)
+            {
+                print ("fapiParseAttributeInfo.pl ERROR. More than 4 array dimensions!!\n");
+                exit(1);
+            }
+            else
+            {
+                for (my $i = 0; $i < $numArrayDimensions; $i++)
+                {
+                    print ASFILE "[i_arrayIndex";
+                    print ASFILE $i+1;
+                    print ASFILE "]";
+                }
+            }
+
+            print ASFILE ";\n";
+            print ASFILE "    }\n";
+                
+
+
+            }
+        }
+    }
+
+}
+
+#------------------------------------------------------------------------------
+# Print End of file information to fapiAttributeService.C
+#--------------------------------------------------------------------------
+if ($attCount > 0)
+{
+    print ASFILE "    else\n";
+}
+print ASFILE "    {\n";
+print ASFILE "        FAPI_ERR(\"fapiGetInitFileAttr: Unrecognized attr ID: 0x%x\", i_id);\n";
+print ASFILE "        l_rc.setFapiError(FAPI_RC_INVALID_ATTR_GET);\n";
+print ASFILE "        l_rc.addEIFfdc(0, &i_id, sizeof(i_id));\n";
+print ASFILE "    }\n\n";
+print ASFILE "    if (l_rc)\n";
+print ASFILE "    {\n";
+print ASFILE "        if (i_pTarget)\n";
+print ASFILE "        {\n";
+print ASFILE "            FAPI_ERR(\"fapiGetInitFileAttr: Error getting attr ID 0x%x from targType 0x%x\",\n";
+print ASFILE "                     i_id, i_pTarget->getType());\n";
+print ASFILE "        }\n";
+print ASFILE "        else\n";
+print ASFILE "        {\n";
+print ASFILE "            FAPI_ERR(\"fapiGetInitFileAttr: Error getting attr ID 0x%x from system target\",\n";
+print ASFILE "                     i_id);\n";
+print ASFILE "        }\n";
+print ASFILE "    }\n\n";
+print ASFILE "    return l_rc;\n";
+print ASFILE "}\n\n";
+print ASFILE "}\n";
+
+
+#------------------------------------------------------------------------------
+# Close output file
+#------------------------------------------------------------------------------
+close(ASFILE);
diff --git a/src/ppe/tools/scripts/ppeParseAttrGetSetMacros.pl b/src/ppe/tools/scripts/ppeParseAttrGetSetMacros.pl
new file mode 100644
index 0000000..a1edf32
--- /dev/null
+++ b/src/ppe/tools/scripts/ppeParseAttrGetSetMacros.pl
@@ -0,0 +1,284 @@
+#!/usr/bin/perl
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ppe/tools/scripts/ppeParseAttrGetSetMacros.pl $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+# Purpose:  This perl script will parse HWP Attribute XML files and
+# initfile attr files and create the fapiGetInitFileAttr() function
+# in a file called fapiAttributeService.C
+
+use strict;
+
+#------------------------------------------------------------------------------
+# Print Command Line Help
+#------------------------------------------------------------------------------
+my $numArgs = $#ARGV + 1;
+if ($numArgs < 3)
+{
+    print ("Usage: ppeParseAttrGetSetMacros.pl <output dir>\n");
+    print ("           [<if-attr-file1> <if-attr-file2> ...]\n");
+    print ("           -a <attr-xml-file1> [<attr-xml-file2> ...]\n");
+    print ("  This perl script will parse if-attr files (containing the\n");
+    print ("  attributes used by the initfile) and attribute XML files\n");
+    print ("  (containing all HWPF attributes) and create the\n");
+    print ("  fapiGetInitFileAttr() function in a file called\n");
+    print ("  fapiAttributeService.C. Only the attributes specified in\n");
+    print ("  the if-attr files are supported. If no if-attr files are\n");
+    print ("  specified then all attributes are supported\n");
+    exit(1);
+}
+
+#------------------------------------------------------------------------------
+# Specify perl modules to use
+#------------------------------------------------------------------------------
+use XML::Simple;
+my $xml = new XML::Simple (KeyAttr=>[]);
+
+# Uncomment to enable debug output
+#use Data::Dumper;
+
+#------------------------------------------------------------------------------
+# Open output file for writing
+#------------------------------------------------------------------------------
+my $chipFile = $ARGV[0];
+$chipFile .= "/";
+$chipFile .= "fapi2_attribute_getsettemplates.h";
+open(CHFILE, ">", $chipFile);
+
+my $exFile = $ARGV[0];
+$exFile .= "/";
+$exFile .= "proc_sbe_fixed_ex.H";
+open(EXFILE, ">", $exFile);
+
+my $coreFile = $ARGV[0];
+$coreFile .= "/";
+$coreFile .= "proc_sbe_fixed_core.H";
+open(COFILE, ">", $coreFile);
+
+my $eqFile = $ARGV[0];
+$eqFile .= "/";
+$eqFile .= "proc_sbe_fixed_eq.H";
+open(EQFILE, ">", $eqFile);
+
+my $pervFile = $ARGV[0];
+$pervFile .= "/";
+$pervFile .= "proc_sbe_fixed_perv.H";
+open(PEFILE, ">", $pervFile);
+
+
+#------------------------------------------------------------------------------
+# Print Start of file information to fapiAttributeService.C
+#------------------------------------------------------------------------------
+#print ASFILE "// proc_sbe_func.H\n";
+#print ASFILE "// This file is generated by perl script fapi2ParseProcSbeFixed.pl\n\n";
+#print ASFILE "#ifndef __PROC_SBE_FIXED_H__\n";
+#print ASFILE "#define __PROC_SBE_FIXED_H__\n";
+#print ASFILE "#include \"p9_sbe.H\"\n";
+#print ASFILE "#include \"plat_target_parms.H\"\n";
+#print ASFILE "#include \"fapi2AttributeIds.H\"\n\n";
+
+
+my $xmlFiles = 0;
+my $attCount = 0;
+my $numIfAttrFiles = 0;
+my @attrChipIds;
+my @attrExIds;
+my @attrCoreIds;
+my @attrEqIds;
+my @attrPervIds;
+
+
+
+#------------------------------------------------------------------------------
+# Element names
+#------------------------------------------------------------------------------
+my $attribute = 'attribute';
+
+#------------------------------------------------------------------------------
+# For each argument
+#------------------------------------------------------------------------------
+my $argfile = $ARGV[1];
+my $entries = $xml->XMLin($argfile, ForceArray => ['entry']);
+foreach my $entr (@{$entries->{entry}}) {
+
+    my $inname = $entr->{name};
+
+    # read XML file. The ForceArray option ensures that there is an array of
+    # elements even if there is only one such element in the file
+
+    foreach my $argnum (2 .. $#ARGV)
+    {
+        my $infile = $ARGV[$argnum];
+
+        my $attributes = $xml->XMLin($infile, ForceArray => ['attribute']);
+
+        # Uncomment to get debug output of all attributes
+        #print "\nFile: ", $infile, "\n", Dumper($attributes), "\n";
+
+        #--------------------------------------------------------------------------
+        # For each Attribute
+        #--------------------------------------------------------------------------
+        foreach my $attr (@{$attributes->{attribute}})
+        {
+
+            if($attr->{id} eq $inname) {
+
+            #------------------------------------------------------------------
+            # Check that the AttributeId exists
+            #------------------------------------------------------------------
+            if (! exists $attr->{id})
+            {
+                print ("ppeParseGetSetMacros.pl ERROR. Att 'id' missing\n");
+                exit(1);
+            }
+
+
+            if($attr->{targetType} eq "TARGET_TYPE_PROC_CHIP") {
+
+                push(@attrChipIds, $attr);
+
+            } elsif($attr->{targetType} eq "TARGET_TYPE_CORE") {
+
+                push(@attrCoreIds, $attr);
+                
+            } elsif($attr->{targetType} eq "TARGET_TYPE_EQ") {
+
+                push(@attrEqIds, $attr);
+
+            } elsif($attr->{targetType} eq "TARGET_TYPE_EX") { 
+
+                push(@attrExIds, $attr);
+
+            } elsif($attr->{targetType} eq "TARGET_TYPE_PERV") { 
+
+#                push(@attrPervIds, $attr->{id});
+                push(@attrPervIds, $attr);
+
+            } else {
+
+                print ("ppeParseAttrGetSetMacros.pl ERROR. Wrong attribute type: $attr->{targetType}\n");
+                exit(1);
+
+            }
+
+            }
+        }
+    }
+
+}
+
+
+print CHFILE "// proc_sbe_fixed_proc_chip.H\n";
+print CHFILE "// This file is generated by perl script ppeParseAttrGetSetMacros.pl\n\n";
+print CHFILE "#ifndef __PROC_SBE_FIXED_PROC_CHIP_H__\n";
+print CHFILE "#define __PROC_SBE_FIXED_PROC_CHIP_H__\n\n";
+foreach my $attr (@attrChipIds)
+{
+
+    my $value = uc $attr->{valueType};
+    print CHFILE "PROC_SBE_FIXED_$value($attr->{id});\n"
+    
+
+}
+print CHFILE "\n#endif  // __PROC_SBE_FIXED_PROC_CHIP_H__";
+
+print EXFILE "// proc_sbe_fixed_ex.H\n";
+print EXFILE "// This file is generated by perl script ppeParseAttrGetSetMacros.pl\n\n";
+print EXFILE "#ifndef __PROC_SBE_FIXED_EX_H__\n";
+print EXFILE "#define __PROC_SBE_FIXED_EX_H__\n";
+foreach my $attr (@attrExIds)
+{
+
+    my $value = uc $attr->{valueType};
+    print EXFILE "PROC_SBE_FIXED_TARGET_$value($attr->{id}, EX_TARGET_COUNT);\n"
+    
+
+}
+print EXFILE "\n#endif  // __PROC_SBE_FIXED_EX_H__";
+
+
+print COFILE "// proc_sbe_fixed_co.H\n";
+print COFILE "// This file is generated by perl script ppeParseAttrGetSetMacros.pl\n\n";
+print COFILE "#ifndef __PROC_SBE_FIXED_CO_H__\n";
+print COFILE "#define __PROC_SBE_FIXED_CO_H__\n";
+foreach my $attr (@attrCoreIds)
+{
+
+    my $value = uc $attr->{valueType};
+    print COFILE "PROC_SBE_FIXED_TARGET_$value($attr->{id}, CORE_TARGET_COUNT);\n"
+    
+
+}
+print COFILE "\n#endif  // __PROC_SBE_FIXED_CO_H__";
+
+
+
+print EQFILE "// proc_sbe_fixed_eq.H\n";
+print EQFILE "// This file is generated by perl script ppeParseAttrGetSetMacros.pl\n\n";
+print EQFILE "#ifndef __PROC_SBE_FIXED_EQ_H__\n";
+print EQFILE "#define __PROC_SBE_FIXED_EQ_H__\n";
+foreach my $attr (@attrEqIds)
+{
+
+    my $value = uc $attr->{valueType};
+    print EQFILE "PROC_SBE_FIXED_TARGET_$value($attr->{id}, EQ_TARGET_COUNT);\n"
+    
+
+}
+print EQFILE "\n#endif  // __PROC_SBE_FIXED_EQ_H__";
+
+
+
+print PEFILE "// proc_sbe_fixed_perv.H\n";
+print PEFILE "// This file is generated by perl script ppeParseAttrGetSetMacros.pl\n\n";
+print PEFILE "#ifndef __PROC_SBE_FIXED_PERV_H__\n";
+print PEFILE "#define __PROC_SBE_FIXED_PERV_H__\n";
+foreach my $attr (@attrPervIds)
+{
+
+    my $value = uc $attr->{valueType};
+    print PEFILE "PROC_SBE_FIXED_TARGET_$value($attr->{id}, PERV_TARGET_COUNT);\n"
+    
+
+}
+print PEFILE "\n#endif  // __PROC_SBE_FIXED_PERV_H__";
+
+
+
+
+
+
+
+
+#print ASFILE "#endif  // __PROC_SBE_FIXED_H__";
+
+
+#------------------------------------------------------------------------------
+# Close output file
+#------------------------------------------------------------------------------
+close(CHFILE);
+close(COFILE);
+close(EXFILE);
+close(PEFILE);
+close(EQFILE);
+
diff --git a/src/ppe/tools/scripts/ppeParseAttributeInfo.pl b/src/ppe/tools/scripts/ppeParseAttributeInfo.pl
new file mode 100755
index 0000000..339f5d0
--- /dev/null
+++ b/src/ppe/tools/scripts/ppeParseAttributeInfo.pl
@@ -0,0 +1,1090 @@
+#!/usr/bin/perl -w
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ppe/tools/scripts/ppeParseAttributeInfo.pl $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+# Purpose:  This perl script will parse HWP Attribute XML files
+# and add attribute information to a file called fapi2AttributeIds.H
+
+use strict;
+
+#------------------------------------------------------------------------------
+# Print Command Line Help
+#------------------------------------------------------------------------------
+my $numArgs = $#ARGV + 1;
+if ($numArgs < 2)
+{
+    print ("Usage: ppeParseAttributeInfo.pl <output dir> <attr-xml-file1> [<attr-xml-file2> ...]\n");
+    print ("  This perl script will parse attribute XML files and create the following files:\n");
+    print ("  - fapi2AttributeIds.H.          Contains IDs, type, value enums and other information\n");
+    print ("  - fapi2ChipEcFeature.C.         Contains a function to query chip EC features\n");
+    print ("  - fapi2AttributePlatCheck.H.    Contains compile time checks that all attributes are\n");
+    print ("                                  handled by the platform\n");
+    print ("  - fapi2AttributesSupported.html Contains the HWPF attributes supported\n");
+    print ("  - fapi2AttrInfo.csv             Used to process Attribute Override Text files\n");
+    print ("  - fapi2AttrEnumInfo.csv         Used to process Attribute Override Text files\n");
+    exit(1);
+}
+
+#------------------------------------------------------------------------------
+# Specify perl modules to use
+#------------------------------------------------------------------------------
+use Digest::MD5 qw(md5_hex);
+use XML::Simple;
+my $xml = new XML::Simple (KeyAttr=>[]);
+
+# Uncomment to enable debug output
+#use Data::Dumper;
+
+#------------------------------------------------------------------------------
+# Set PREFERRED_PARSER to XML::Parser. Otherwise it uses XML::SAX which contains
+# bugs that result in XML parse errors that can be fixed by adjusting white-
+# space (i.e. parse errors that do not make sense).
+#------------------------------------------------------------------------------
+$XML::Simple::PREFERRED_PARSER = 'XML::Parser';
+
+#------------------------------------------------------------------------------
+# Open output files for writing
+#------------------------------------------------------------------------------
+my $aiFile = $ARGV[0];
+$aiFile .= "/";
+$aiFile .= "fapi2AttributeIds.H";
+open(AIFILE, ">", $aiFile);
+
+my $ecFile = $ARGV[0];
+$ecFile .= "/";
+$ecFile .= "fapi2ChipEcFeature.C";
+open(ECFILE, ">", $ecFile);
+
+my $acFile = $ARGV[0];
+$acFile .= "/";
+$acFile .= "fapi2AttributePlatCheck.H";
+open(ACFILE, ">", $acFile);
+
+my $asFile = $ARGV[0];
+$asFile .= "/";
+$asFile .= "fapi2AttributesSupported.html";
+open(ASFILE, ">", $asFile);
+
+my $itFile = $ARGV[0];
+$itFile .= "/";
+$itFile .= "fapi2AttrInfo.csv";
+open(ITFILE, ">", $itFile);
+
+my $etFile = $ARGV[0];
+$etFile .= "/";
+$etFile .= "fapi2AttrEnumInfo.csv";
+open(ETFILE, ">", $etFile);
+
+#------------------------------------------------------------------------------
+# Print Start of file information to fapiAttributeIds.H
+#------------------------------------------------------------------------------
+print AIFILE "// fapi2AttributeIds.H\n";
+print AIFILE "// This file is generated by perl script fapiParseAttributeInfo.pl\n\n";
+print AIFILE "#ifndef FAPI2ATTRIBUTEIDS_H_\n";
+print AIFILE "#define FAPI2ATTRIBUTEIDS_H_\n\n";
+print AIFILE "#ifndef __ASSEMBLER__\n\n";
+print AIFILE "#include <target.H>\n";
+print AIFILE "#include <target_types.H>\n\n";
+print AIFILE "namespace fapi2\n";
+print AIFILE "{\n\n";
+print AIFILE "\/**\n";
+print AIFILE " * \@brief Enumeration of attribute IDs\n";
+print AIFILE " *\/\n";
+print AIFILE "enum AttributeId\n{\n";
+
+#------------------------------------------------------------------------------
+# Print Start of file information to fapiChipEcFeature.C
+#------------------------------------------------------------------------------
+print ECFILE "// fapiChipEcFeature.C\n";
+print ECFILE "// This file is generated by perl script fapiParseAttributeInfo.pl\n";
+print ECFILE "// It implements the fapiQueryChipEcFeature function\n\n";
+print ECFILE "#include <fapiChipEcFeature.H>\n";
+print ECFILE "#include <fapiAttributeService.H>\n";
+print ECFILE "#include <fapiSystemConfig.H>\n";
+print ECFILE "#include <fapiPlatTrace.H>\n\n";
+print ECFILE "namespace fapi2\n";
+print ECFILE "{\n\n";
+print ECFILE "fapi::ReturnCode fapiQueryChipEcFeature(fapi::AttributeId i_id,\n";
+print ECFILE "                                        const fapi::Target * i_pTarget,\n";
+print ECFILE "                                        uint8_t & o_hasFeature)\n";
+print ECFILE "{\n";
+print ECFILE "    o_hasFeature = false;\n";
+print ECFILE "    fapi::ReturnCode l_rc;\n";
+print ECFILE "    uint8_t l_chipName = 0;\n";
+print ECFILE "    uint8_t l_chipEc = 0;\n";
+print ECFILE "    fapi::Target l_target = *i_pTarget;\n\n";
+print ECFILE "    if (i_pTarget->isChiplet())\n";
+print ECFILE "    {\n";
+print ECFILE "        l_rc = fapiGetParentChip(*i_pTarget, l_target);\n\n";
+print ECFILE "        if (l_rc)\n";
+print ECFILE "        {\n";
+print ECFILE "            FAPI_ERR(\"fapiQueryChipEcFeature: error getting parent chip\");\n";
+print ECFILE "        }\n";
+print ECFILE "    }\n\n";
+print ECFILE "    if (!l_rc)\n";
+print ECFILE "    {\n";
+print ECFILE "        l_rc = FAPI_ATTR_GET_PRIVILEGED(ATTR_NAME, &l_target, l_chipName);\n\n";
+print ECFILE "        if (l_rc)\n";
+print ECFILE "        {\n";
+print ECFILE "            FAPI_ERR(\"fapiQueryChipEcFeature: error getting chip name\");\n";
+print ECFILE "        }\n";
+print ECFILE "        else\n";
+print ECFILE "        {\n";
+print ECFILE "            l_rc = FAPI_ATTR_GET_PRIVILEGED(ATTR_EC, &l_target, l_chipEc);\n\n";
+print ECFILE "            if (l_rc)\n";
+print ECFILE "            {\n";
+print ECFILE "                FAPI_ERR(\"fapiQueryChipEcFeature: error getting chip ec\");\n";
+print ECFILE "            }\n";
+print ECFILE "            else\n";
+print ECFILE "            {\n";
+print ECFILE "                switch (i_id)\n";
+print ECFILE "                {\n";
+
+#------------------------------------------------------------------------------
+# Print Start of file information to fapiAttributePlatCheck.H
+#------------------------------------------------------------------------------
+print ACFILE "// fapiAttributePlatCheck.H\n";
+print ACFILE "// This file is generated by perl script fapiParseAttributeInfo.pl\n";
+print ACFILE "// A platform can include it to ensure that it handles all HWPF\n";
+print ACFILE "// attributes\n\n";
+print ACFILE "#ifndef FAPIATTRIBUTEPLATCHECK_H_\n";
+print ACFILE "#define FAPIATTRIBUTEPLATCHECK_H_\n\n";
+
+#------------------------------------------------------------------------------
+# Print Start of file information to fapiAttributesSupported.html
+#------------------------------------------------------------------------------
+print ASFILE "<html>\n";
+print ASFILE "<body>\n\n";
+print ASFILE "<!-- fapiAttributesSupported.html -->\n";
+print ASFILE "<!-- This file is generated by perl script fapiParseAttributeInfo.pl -->\n";
+print ASFILE "<!-- It lists all HWPF attributes supported -->\n\n";
+print ASFILE "<h4>HWPF Attributes supported by this build.</h4>\n";
+print ASFILE "<table border=\"4\">\n";
+print ASFILE "<tr><th>Attribute ID</th><th>Attribute Description</th></tr>";
+
+#------------------------------------------------------------------------------
+# Print Start of file information to fapiAttrInfo.csv
+#------------------------------------------------------------------------------
+print ITFILE "# fapiAttrInfo.csv\n";
+print ITFILE "# This file is generated by perl script fapiParseAttributeInfo.pl\n";
+print ITFILE "# It lists information about FAPI attributes and is used to\n";
+print ITFILE "# process FAPI Attribute text files (overrides/syncs)\n";
+print ITFILE "# Format:\n";
+print ITFILE "# <FAPI-ATTR-ID-STR>,<LAYER-ATTR-ID-STR>,<ATTR-ID-VAL>,<ATTR-TYPE>\n";
+print ITFILE "# Note that for the AttributeTanks at the FAPI layer, the\n";
+print ITFILE "# FAPI-ATTR-ID-STR and LAYER-ATTR-ID-STR will be identical\n";
+
+#------------------------------------------------------------------------------
+# Print Start of file information to fapiAttrEnumInfo.csv
+#------------------------------------------------------------------------------
+print ETFILE "# fapiAttrEnumInfo.csv\n";
+print ETFILE "# This file is generated by perl script fapiParseAttributeInfo.pl\n";
+print ETFILE "# It lists information about FAPI attribute enumeratorss and is\n";
+print ETFILE "# used to process FAPI Attribute text files (overrides/syncs)\n";
+print ETFILE "# Format:\n";
+print ETFILE "# <ENUM-STR>,<ENUM-VAL>\n";
+
+my %attrIdHash;  # Records which Attribute IDs have been used
+my %attrValHash; # Records which Attribute values have been used
+
+#------------------------------------------------------------------------------
+# For each XML file
+#------------------------------------------------------------------------------
+#my $argfile = "p9_ppe_attributes.xml";
+my $argfile = $ARGV[1];
+my $entries = $xml->XMLin($argfile, ForceArray => ['entry']);
+foreach my $entr (@{$entries->{entry}}) {
+
+#    print "    $entr->{file}, $entr->{name}\n";
+
+    #my $infile = $entr->{file};
+    my $inname = $entr->{name};
+
+foreach my $argnum (2 .. $#ARGV)
+{
+    my $infile = $ARGV[$argnum];
+
+
+    # read XML file. The ForceArray option ensures that there is an array of
+    # elements even if there is only one such element in the file
+    my $attributes = $xml->XMLin($infile, ForceArray => ['attribute']);
+
+    # Uncomment to get debug output of all attributes
+    #print "\nFile: ", $infile, "\n", Dumper($attributes), "\n";
+
+    #--------------------------------------------------------------------------
+    # For each Attribute
+    #--------------------------------------------------------------------------
+    foreach my $attr (@{$attributes->{attribute}})
+    {
+
+        #print "?    $attr->{id}, $inname\n";
+
+        if($attr->{id} eq $inname) {
+
+        #print "yes    $attr->{id}, $inname\n";
+
+        #----------------------------------------------------------------------
+        # Print the Attribute ID and calculated value to fapiAttributeIds.H and
+        # fapiAttributeIds.txt. The value for an attribute is a hash value
+        # generated from the attribute name, this ties a specific value to a
+        # specific attribute name. This is done for Cronus so that if a HWP is
+        # not recompiled against a new eCMD/Cronus version where the attributes
+        # have changed then there will not be a mismatch in enumerator values.
+        # This is a 28bit hash value because the Initfile compiler has a
+        # requirement that the top nibble of the 32 bit attribute ID be zero to
+        # store flags
+        #----------------------------------------------------------------------
+        if (! exists $attr->{id})
+        {
+            print ("fapiParseAttributeInfo.pl ERROR. Attribute 'id' missing in $infile\n");
+            exit(1);
+        }
+
+        if (exists($attrIdHash{$attr->{id}}))
+        {
+            # Two different attributes with the same id!
+            print ("fapiParseAttributeInfo.pl ERROR. Duplicate Attribute id $attr->{id} in $infile\\n");
+            exit(1);
+        }
+
+        # Calculate a 28 bit hash value.
+        my $attrHash128Bit = md5_hex($attr->{id});
+        my $attrHash28Bit = substr($attrHash128Bit, 0, 7);
+
+        # Print the attribute ID/value to fapiAttributeIds.H
+        print AIFILE "    $attr->{id} = 0x$attrHash28Bit,\n";
+
+        if (exists($attrValHash{$attrHash28Bit}))
+        {
+            # Two different attributes generate the same hash-value!
+            print ("fapiParseAttributeInfo.pl ERROR. Duplicate attr id hash value for $attr->{id} in $infile\ \n");
+            exit(1);
+        }
+
+        $attrIdHash{$attr->{id}} = $attrHash28Bit;
+        $attrValHash{$attrHash28Bit} = 1;
+        }
+    };
+}
+}
+
+#------------------------------------------------------------------------------
+# Print AttributeId enumeration end to fapiAttributeIds.H
+#------------------------------------------------------------------------------
+print AIFILE "};\n\n";
+
+#------------------------------------------------------------------------------
+# Print Attribute Information comment to fapiAttributeIds.H
+#------------------------------------------------------------------------------
+print AIFILE "\/**\n";
+print AIFILE " * \@brief Attribute Information\n";
+print AIFILE " *\/\n";
+
+
+foreach my $entr (@{$entries->{entry}}) {
+
+#    print "    $entr->{file}, $entr->{name}\n";
+
+#    my $infile = $entr->{file};
+    my $inname = $entr->{name};
+
+    # read XML file. The ForceArray option ensures that there is an array of
+    # elements even if there is only one such element in the file
+
+foreach my $argnum (2 .. $#ARGV)
+{
+    my $infile = $ARGV[$argnum];
+
+    my $attributes = $xml->XMLin($infile, ForceArray => ['attribute']);
+
+    # Uncomment to get debug output of all attributes
+    #print "\nFile: ", $infile, "\n", Dumper($attributes), "\n";
+
+    #--------------------------------------------------------------------------
+    # For each Attribute
+    #--------------------------------------------------------------------------
+    foreach my $attr (@{$attributes->{attribute}})
+    {
+
+
+
+        if($attr->{id} eq $inname) {
+
+        #----------------------------------------------------------------------
+        # Print a comment with the attribute ID fapiAttributeIds.H
+        #----------------------------------------------------------------------
+        print AIFILE "/* $attr->{id} */\n";
+
+        #----------------------------------------------------------------------
+        # Print the AttributeId and description to fapiAttributesSupported.html
+        #----------------------------------------------------------------------
+        if (! exists $attr->{description})
+        {
+            print ("fapiParseAttributeInfo.pl ERROR. Attribute 'description' missing for $attr->{id} in $infile\n");
+            exit(1);
+        }
+
+
+        #----------------------------------------------------------------------
+        # Figure out the attribute array dimensions (if array)
+        #----------------------------------------------------------------------
+        my $arrayDimensions = "";
+        my $numArrayDimensions = 0;
+        if ($attr->{array})
+        {
+            # Remove leading whitespace
+            my $dimText = $attr->{array};
+            $dimText =~ s/^\s+//;
+
+            # Split on commas or whitespace
+            my @vals = split(/\s*,\s*|\s+/, $dimText);
+
+            foreach my $val (@vals)
+            {
+                $arrayDimensions .= "[${val}]";
+                $numArrayDimensions++;
+            }
+        }
+
+        #----------------------------------------------------------------------
+        # Print the typedef for each attribute's val type to fapiAttributeIds.H
+        # Print the attribute information to fapiAttrInfo.csv
+        #----------------------------------------------------------------------
+        if (exists $attr->{chipEcFeature})
+        {
+            # The value type of chip EC feature attributes is uint8_t
+            print AIFILE "typedef uint8_t $attr->{id}_Type;\n";
+            print ITFILE "$attr->{id},$attr->{id},0x$attrIdHash{$attr->{id}},u8\n"
+        }
+        else
+        {
+            if (! exists $attr->{valueType})
+            {
+                print ("fapiParseAttributeInfo.pl ERROR. Att 'valueType' missing for $attr->{id} in $infile\n");
+                exit(1);
+            }
+
+            if ($attr->{valueType} eq 'uint8')
+            {
+                print AIFILE "typedef uint8_t $attr->{id}_Type$arrayDimensions;\n";
+                print ITFILE "$attr->{id},$attr->{id},0x$attrIdHash{$attr->{id}},u8" .
+                             "$arrayDimensions\n";                                                         
+            }
+            elsif ($attr->{valueType} eq 'uint16')
+            {
+                print AIFILE "typedef uint16_t $attr->{id}_Type$arrayDimensions;\n";
+                print ITFILE "$attr->{id},$attr->{id},0x$attrIdHash{$attr->{id}},u8" .
+                             "$arrayDimensions\n";
+            }
+            elsif ($attr->{valueType} eq 'uint32')
+            {
+                print AIFILE "typedef uint32_t $attr->{id}_Type$arrayDimensions;\n";
+                print ITFILE "$attr->{id},$attr->{id},0x$attrIdHash{$attr->{id}},u32" .
+                             "$arrayDimensions\n";
+            }
+            elsif ($attr->{valueType} eq 'uint64')
+            {
+                print AIFILE "typedef uint64_t $attr->{id}_Type$arrayDimensions;\n";
+                print ITFILE "$attr->{id},$attr->{id},0x$attrIdHash{$attr->{id}},u64" .
+                             "$arrayDimensions\n";
+            }
+            elsif ($attr->{valueType} eq 'int8')
+            {
+                print AIFILE "typedef int8_t $attr->{id}_Type$arrayDimensions;\n";
+                print ITFILE "$attr->{id},$attr->{id},0x$attrIdHash{$attr->{id}},8" .
+                             "$arrayDimensions\n";
+            }
+             elsif ($attr->{valueType} eq 'int16')
+            {
+                print AIFILE "typedef int16_t $attr->{id}_Type$arrayDimensions;\n";
+                print ITFILE "$attr->{id},$attr->{id},0x$attrIdHash{$attr->{id}},32" .
+                             "$arrayDimensions\n";
+            }
+            elsif ($attr->{valueType} eq 'int32')
+            {
+                print AIFILE "typedef int32_t $attr->{id}_Type$arrayDimensions;\n";
+                print ITFILE "$attr->{id},$attr->{id},0x$attrIdHash{$attr->{id}},32" .
+                             "$arrayDimensions\n";
+            }
+            elsif ($attr->{valueType} eq 'int64')
+            {
+                print AIFILE "typedef int64_t $attr->{id}_Type$arrayDimensions;\n";
+                print ITFILE "$attr->{id},$attr->{id},0x$attrIdHash{$attr->{id}},64" .
+                             "$arrayDimensions\n";
+            }
+            else
+            {
+                print ("fapi2ParseAttributeInfo.pl ERROR. valueType not recognized: ");
+                print $attr->{valueType}, " for $attr->{id} in $infile\n";
+                exit(1);
+            }
+        }
+
+        #----------------------------------------------------------------------
+        # Print if the attribute is privileged
+        #----------------------------------------------------------------------
+        if (exists $attr->{privileged})
+        {
+            print AIFILE "const bool $attr->{id}_Privileged = true;\n";
+        }
+        else
+        {
+            print AIFILE "const bool $attr->{id}_Privileged = false;\n";
+        }
+
+        #----------------------------------------------------------------------
+        # Print the target type(s) that the attribute is associated with
+        #----------------------------------------------------------------------
+        if (! exists $attr->{targetType})
+        {
+            print ("fapiParseAttributeInfo.pl ERROR. Att 'targetType' missing for $attr->{id} in $infile\n");
+            exit(1);
+        }
+
+        print AIFILE "const TargetTypes_t $attr->{id}_TargetTypes = ";
+
+        # Split on commas
+        my @targTypes = split(',', $attr->{targetType});
+
+        my $targTypeCount = 0;
+        foreach my $targType (@targTypes)
+        {
+            # Remove newlines and leading/trailing whitespace
+            $targType =~ s/\n//;
+            $targType =~ s/^\s+//;
+            $targType =~ s/\s+$//;
+
+            if ($targTypeCount != 0)
+            {
+                print AIFILE " | ";
+            }
+            print AIFILE "$targType";
+            $targTypeCount++;
+        }
+        print AIFILE ";\n";
+
+        #----------------------------------------------------------------------
+        # Print if the attribute is a platInit attribute
+        #----------------------------------------------------------------------
+        if (exists $attr->{platInit})
+        {
+            print AIFILE "const bool $attr->{id}_PlatInit = true;\n";
+        }
+        else
+        {
+            print AIFILE "const bool $attr->{id}_PlatInit = false;\n";
+        }
+
+        #----------------------------------------------------------------------
+        # Print if the attribute is a initToZero attribute
+        #----------------------------------------------------------------------
+        if (exists $attr->{initToZero})
+        {
+            print AIFILE "const bool $attr->{id}_InitToZero = true;\n";
+        }
+        else
+        {
+            print AIFILE "const bool $attr->{id}_InitToZero = false;\n";
+        }
+
+        #----------------------------------------------------------------------
+        # Print the value enumeration (if specified) to fapiAttributeIds.H and
+        # fapiAttributeEnums.txt
+        #----------------------------------------------------------------------
+        if (exists $attr->{enum})
+        {
+            print AIFILE "enum $attr->{id}_Enum\n{\n";
+
+            # Values must be separated by commas to allow for values to be
+            # specified: <enum>VAL_A = 3, VAL_B = 5, VAL_C = 0x23</enum>
+            my @vals = split(',', $attr->{enum});
+
+            foreach my $val (@vals)
+            {
+                # Remove newlines and leading/trailing whitespace
+                $val =~ s/\n//;
+                $val =~ s/^\s+//;
+                $val =~ s/\s+$//;
+
+                # Print the attribute enum to fapiAttributeIds.H
+                print AIFILE "    ENUM_$attr->{id}_${val}";
+
+                # Print the attribute enum to fapiAttrEnumInfo.csv
+                my $attrEnumTxt = "$attr->{id}_${val}\n";
+                $attrEnumTxt =~ s/ = /,/;
+                print ETFILE $attrEnumTxt;
+
+                if ($attr->{valueType} eq 'uint64')
+                {
+                    print AIFILE "ULL";
+                }
+
+                print AIFILE ",\n";
+            }
+
+            print AIFILE "};\n";
+        }
+
+        #----------------------------------------------------------------------
+        # Print _GETMACRO and _SETMACRO where appropriate to fapiAttributeIds.H
+        #----------------------------------------------------------------------
+        if (exists $attr->{chipEcFeature})
+        {
+            #------------------------------------------------------------------
+            # The attribute is a Chip EC Feature, define _GETMACRO to call a
+            # fapi function and define _SETMACRO to something that will cause a
+            # compile failure if a set is attempted
+            #------------------------------------------------------------------
+            print AIFILE "#define $attr->{id}_GETMACRO(ID, PTARGET, VAL) \\\n";
+            print AIFILE "    PLAT_GET_CHIP_EC_FEATURE_OVERRIDE(ID, PTARGET, VAL) ? fapi::FAPI_RC_SUCCESS : \\\n";
+            print AIFILE "    fapi::fapiQueryChipEcFeature(fapi::ID, PTARGET, VAL)\n";
+            print AIFILE "#define $attr->{id}_SETMACRO(ID, PTARGET, VAL) ";
+            print AIFILE "CHIP_EC_FEATURE_ATTRIBUTE_NOT_WRITABLE\n";
+        }
+        elsif (! exists $attr->{writeable})
+        {
+            #------------------------------------------------------------------
+            # The attribute is read-only, define the _SETMACRO to something
+            # that will cause a compile failure if a set is attempted
+            #------------------------------------------------------------------
+            if (! exists $attr->{writeable})
+            {
+                print AIFILE "#define $attr->{id}_SETMACRO ATTRIBUTE_NOT_WRITABLE\n";
+            }
+        }
+
+        #----------------------------------------------------------------------
+        # If the attribute is a Chip EC Feature, print the chip EC feature
+        # query to fapiChipEcFeature.C
+        #----------------------------------------------------------------------
+        if (exists $attr->{chipEcFeature})
+        {
+            my $chipCount = 0;
+            print ECFILE "                case $attr->{id}:\n";
+            print ECFILE "                    if (\n";
+
+            foreach my $chip (@{$attr->{chipEcFeature}->{chip}})
+            {
+                $chipCount++;
+
+                if (! exists $chip->{name})
+                {
+                    print ("fapiParseAttributeInfo.pl ERROR. Att 'name' missing\n");
+                    exit(1);
+                }
+
+                if (! exists $chip->{ec})
+                {
+                    print ("fapiParseAttributeInfo.pl ERROR. Att 'ec' missing\n");
+                    exit(1);
+                }
+
+                if (! exists $chip->{ec}->{value})
+                {
+                    print ("fapiParseAttributeInfo.pl ERROR. Att 'value' missing\n");
+                    exit(1);
+                }
+
+                if (! exists $chip->{ec}->{test})
+                {
+                    print ("fapiParseAttributeInfo.pl ERROR. Att 'test' missing\n");
+                    exit(1);
+                }
+
+                my $test;
+                if ($chip->{ec}->{test} eq 'EQUAL')
+                {
+                    $test = '==';
+                }
+                elsif ($chip->{ec}->{test} eq 'GREATER_THAN')
+                {
+                    $test = '>';
+                }
+                elsif ($chip->{ec}->{test} eq 'GREATER_THAN_OR_EQUAL')
+                {
+                    $test = '>=';
+                }
+                elsif ($chip->{ec}->{test} eq 'LESS_THAN')
+                {
+                    $test = '<';
+                }
+                elsif ($chip->{ec}->{test} eq 'LESS_THAN_OR_EQUAL')
+                {
+                    $test = '<=';
+                }
+                else
+                {
+                    print ("fapiParseAttributeInfo.pl ERROR. test '$chip->{ec}->{test}' unrecognized\n");
+                    exit(1);
+                }
+
+                if ($chipCount > 1)
+                {
+                    print ECFILE "                    ||\n";
+                }
+                print ECFILE "                        ((l_chipName == $chip->{name}) &&\n";
+                print ECFILE "                         (l_chipEc $test $chip->{ec}->{value}))\n";
+            }
+
+            print ECFILE "                       )\n";
+            print ECFILE "                    {\n";
+            print ECFILE "                        o_hasFeature = true;\n";
+            print ECFILE "                    }\n";
+            print ECFILE "                    break;\n";
+        }
+
+        #----------------------------------------------------------------------
+        # Print the platform attribute checks to fapiAttributePlatCheck.H
+        #----------------------------------------------------------------------
+        if (exists $attr->{writeable})
+        {
+            print ACFILE "#ifndef $attr->{id}_SETMACRO\n";
+            print ACFILE "#error Platform does not support set of HWPF attr $attr->{id}\n";
+            print ACFILE "#endif\n";
+        }
+
+        print ACFILE "#ifndef $attr->{id}_GETMACRO\n";
+        print ACFILE "#error Platform does not support get of HWPF attr $attr->{id}\n";
+        print ACFILE "#endif\n\n";
+
+        #----------------------------------------------------------------------
+        # Print newline between each attribute's info to fapiAttributeIds.H
+        #----------------------------------------------------------------------
+        print AIFILE "\n";
+
+
+
+
+
+        }
+    };
+}
+}
+
+
+
+=for comment
+
+#------------------------------------------------------------------------------
+# For each XML file
+#------------------------------------------------------------------------------
+foreach my $argnum (1 .. $#ARGV)
+{
+    my $infile = $ARGV[$argnum];
+
+    # read XML file. The ForceArray option ensures that there is an array of
+    # elements even if there is only one such element in the file
+    my $attributes = $xml->XMLin($infile, ForceArray => ['attribute', 'chip']);
+
+    #--------------------------------------------------------------------------
+    # For each Attribute
+    #--------------------------------------------------------------------------
+    foreach my $attr (@{$attributes->{attribute}})
+    {
+        #----------------------------------------------------------------------
+        # Print a comment with the attribute ID fapiAttributeIds.H
+        #----------------------------------------------------------------------
+        print AIFILE "/* $attr->{id} */\n";
+
+        #----------------------------------------------------------------------
+        # Print the AttributeId and description to fapiAttributesSupported.html
+        #----------------------------------------------------------------------
+        if (! exists $attr->{description})
+        {
+            print ("fapiParseAttributeInfo.pl ERROR. Att 'description' missing\n");
+            exit(1);
+        }
+
+        print ASFILE "<tr>\n";
+        print ASFILE "  <td>$attr->{id}</td>\n";
+        print ASFILE "  <td>$attr->{description}</td>\n";
+        print ASFILE "</tr>\n";
+
+        #----------------------------------------------------------------------
+        # Figure out the attribute array dimensions (if array)
+        #----------------------------------------------------------------------
+        my $arrayDimensions = "";
+        my $numArrayDimensions = 0;
+        if ($attr->{array})
+        {
+            # Remove leading whitespace
+            my $dimText = $attr->{array};
+            $dimText =~ s/^\s+//;
+
+            # Split on commas or whitespace
+            my @vals = split(/\s*,\s*|\s+/, $dimText);
+
+            foreach my $val (@vals)
+            {
+                $arrayDimensions .= "[${val}]";
+                $numArrayDimensions++;
+            }
+        }
+
+        #----------------------------------------------------------------------
+        # Print the typedef for each attribute's val type to fapiAttributeIds.H
+        # Print the attribute information to fapiAttrInfo.csv
+        #----------------------------------------------------------------------
+        if (exists $attr->{chipEcFeature})
+        {
+            # The value type of chip EC feature attributes is uint8_t
+            print AIFILE "typedef uint8_t $attr->{id}_Type;\n";
+            print ITFILE "$attr->{id},$attr->{id},0x$attrIdHash{$attr->{id}},u8\n"
+        }
+        else
+        {
+            if (! exists $attr->{valueType})
+            {
+                print ("fapiParseAttributeInfo.pl ERROR. Att 'valueType' missing\n");
+                exit(1);
+            }
+
+            if ($attr->{valueType} eq 'uint8')
+            {
+                print AIFILE "typedef uint8_t $attr->{id}_Type$arrayDimensions;\n";
+                print ITFILE "$attr->{id},$attr->{id},0x$attrIdHash{$attr->{id}},u8" .
+                             "$arrayDimensions\n";
+            }
+            elsif ($attr->{valueType} eq 'uint32')
+            {
+                print AIFILE "typedef uint32_t $attr->{id}_Type$arrayDimensions;\n";
+                print ITFILE "$attr->{id},$attr->{id},0x$attrIdHash{$attr->{id}},u32" .
+                             "$arrayDimensions\n";
+            }
+            elsif ($attr->{valueType} eq 'uint64')
+            {
+                print AIFILE "typedef uint64_t $attr->{id}_Type$arrayDimensions;\n";
+                print ITFILE "$attr->{id},$attr->{id},0x$attrIdHash{$attr->{id}},u64" .
+                             "$arrayDimensions\n";
+            }
+            else
+            {
+                print ("fapiParseAttributeInfo.pl ERROR. valueType not recognized: ");
+                print $attr->{valueType}, "\n";
+                exit(1);
+            }
+        }
+
+        #----------------------------------------------------------------------
+        # Print if the attribute is privileged
+        #----------------------------------------------------------------------
+        if (exists $attr->{privileged})
+        {
+            print AIFILE "const bool $attr->{id}_Privileged = true;\n";
+        }
+        else
+        {
+            print AIFILE "const bool $attr->{id}_Privileged = false;\n";
+        }
+
+        #----------------------------------------------------------------------
+        # Print the target type(s) that the attribute is associated with
+        #----------------------------------------------------------------------
+        if (! exists $attr->{targetType})
+        {
+            print ("fapiParseAttributeInfo.pl ERROR. Att 'targetType' missing\n");
+            exit(1);
+        }
+
+        print AIFILE "const TargetTypes_t $attr->{id}_TargetTypes = ";
+
+        # Split on commas
+        my @targTypes = split(',', $attr->{targetType});
+
+        my $targTypeCount = 0;
+        foreach my $targType (@targTypes)
+        {
+            # Remove newlines and leading/trailing whitespace
+            $targType =~ s/\n//;
+            $targType =~ s/^\s+//;
+            $targType =~ s/\s+$//;
+
+            if ($targTypeCount != 0)
+            {
+                print AIFILE " | ";
+            }
+            print AIFILE "$targType";
+            $targTypeCount++;
+        }
+        print AIFILE ";\n";
+
+        #----------------------------------------------------------------------
+        # Print if the attribute is a platInit attribute
+        #----------------------------------------------------------------------
+        if (exists $attr->{platInit})
+        {
+            print AIFILE "const bool $attr->{id}_PlatInit = true;\n";
+        }
+        else
+        {
+            print AIFILE "const bool $attr->{id}_PlatInit = false;\n";
+        }
+
+        #----------------------------------------------------------------------
+        # Print if the attribute is a initToZero attribute
+        #----------------------------------------------------------------------
+        if (exists $attr->{initToZero})
+        {
+            print AIFILE "const bool $attr->{id}_InitToZero = true;\n";
+        }
+        else
+        {
+            print AIFILE "const bool $attr->{id}_InitToZero = false;\n";
+        }
+
+        #----------------------------------------------------------------------
+        # Print the value enumeration (if specified) to fapiAttributeIds.H and
+        # fapiAttributeEnums.txt
+        #----------------------------------------------------------------------
+        if (exists $attr->{enum})
+        {
+            print AIFILE "enum $attr->{id}_Enum\n{\n";
+
+            # Values must be separated by commas to allow for values to be
+            # specified: <enum>VAL_A = 3, VAL_B = 5, VAL_C = 0x23</enum>
+            my @vals = split(',', $attr->{enum});
+
+            foreach my $val (@vals)
+            {
+                # Remove newlines and leading/trailing whitespace
+                $val =~ s/\n//;
+                $val =~ s/^\s+//;
+                $val =~ s/\s+$//;
+
+                # Print the attribute enum to fapiAttributeIds.H
+                print AIFILE "    ENUM_$attr->{id}_${val}";
+
+                # Print the attribute enum to fapiAttrEnumInfo.csv
+                my $attrEnumTxt = "$attr->{id}_${val}\n";
+                $attrEnumTxt =~ s/ = /,/;
+                print ETFILE $attrEnumTxt;
+
+                if ($attr->{valueType} eq 'uint64')
+                {
+                    print AIFILE "ULL";
+                }
+
+                print AIFILE ",\n";
+            }
+
+            print AIFILE "};\n";
+        }
+
+        #----------------------------------------------------------------------
+        # Print _GETMACRO and _SETMACRO where appropriate to fapiAttributeIds.H
+        #----------------------------------------------------------------------
+        if (exists $attr->{chipEcFeature})
+        {
+            #------------------------------------------------------------------
+            # The attribute is a Chip EC Feature, define _GETMACRO to call a
+            # fapi function and define _SETMACRO to something that will cause a
+            # compile failure if a set is attempted
+            #------------------------------------------------------------------
+            print AIFILE "#define $attr->{id}_GETMACRO(ID, PTARGET, VAL) \\\n";
+            print AIFILE "    PLAT_GET_CHIP_EC_FEATURE_OVERRIDE(ID, PTARGET, VAL) ? fapi::FAPI_RC_SUCCESS : \\\n";
+            print AIFILE "    fapi::fapiQueryChipEcFeature(fapi::ID, PTARGET, VAL)\n";
+            print AIFILE "#define $attr->{id}_SETMACRO(ID, PTARGET, VAL) ";
+            print AIFILE "CHIP_EC_FEATURE_ATTRIBUTE_NOT_WRITABLE\n";
+        }
+        elsif (! exists $attr->{writeable})
+        {
+            #------------------------------------------------------------------
+            # The attribute is read-only, define the _SETMACRO to something
+            # that will cause a compile failure if a set is attempted
+            #------------------------------------------------------------------
+            if (! exists $attr->{writeable})
+            {
+                print AIFILE "#define $attr->{id}_SETMACRO ATTRIBUTE_NOT_WRITABLE\n";
+            }
+        }
+
+        #----------------------------------------------------------------------
+        # If the attribute is a Chip EC Feature, print the chip EC feature
+        # query to fapiChipEcFeature.C
+        #----------------------------------------------------------------------
+        if (exists $attr->{chipEcFeature})
+        {
+            my $chipCount = 0;
+            print ECFILE "                case $attr->{id}:\n";
+            print ECFILE "                    if (\n";
+
+            foreach my $chip (@{$attr->{chipEcFeature}->{chip}})
+            {
+                $chipCount++;
+
+                if (! exists $chip->{name})
+                {
+                    print ("fapiParseAttributeInfo.pl ERROR. Att 'name' missing\n");
+                    exit(1);
+                }
+
+                if (! exists $chip->{ec})
+                {
+                    print ("fapiParseAttributeInfo.pl ERROR. Att 'ec' missing\n");
+                    exit(1);
+                }
+
+                if (! exists $chip->{ec}->{value})
+                {
+                    print ("fapiParseAttributeInfo.pl ERROR. Att 'value' missing\n");
+                    exit(1);
+                }
+
+                if (! exists $chip->{ec}->{test})
+                {
+                    print ("fapiParseAttributeInfo.pl ERROR. Att 'test' missing\n");
+                    exit(1);
+                }
+
+                my $test;
+                if ($chip->{ec}->{test} eq 'EQUAL')
+                {
+                    $test = '==';
+                }
+                elsif ($chip->{ec}->{test} eq 'GREATER_THAN')
+                {
+                    $test = '>';
+                }
+                elsif ($chip->{ec}->{test} eq 'GREATER_THAN_OR_EQUAL')
+                {
+                    $test = '>=';
+                }
+                elsif ($chip->{ec}->{test} eq 'LESS_THAN')
+                {
+                    $test = '<';
+                }
+                elsif ($chip->{ec}->{test} eq 'LESS_THAN_OR_EQUAL')
+                {
+                    $test = '<=';
+                }
+                else
+                {
+                    print ("fapiParseAttributeInfo.pl ERROR. test '$chip->{ec}->{test}' unrecognized\n");
+                    exit(1);
+                }
+
+                if ($chipCount > 1)
+                {
+                    print ECFILE "                    ||\n";
+                }
+                print ECFILE "                        ((l_chipName == $chip->{name}) &&\n";
+                print ECFILE "                         (l_chipEc $test $chip->{ec}->{value}))\n";
+            }
+
+            print ECFILE "                       )\n";
+            print ECFILE "                    {\n";
+            print ECFILE "                        o_hasFeature = true;\n";
+            print ECFILE "                    }\n";
+            print ECFILE "                    break;\n";
+        }
+
+        #----------------------------------------------------------------------
+        # Print the platform attribute checks to fapiAttributePlatCheck.H
+        #----------------------------------------------------------------------
+        if (exists $attr->{writeable})
+        {
+            print ACFILE "#ifndef $attr->{id}_SETMACRO\n";
+            print ACFILE "#error Platform does not support set of HWPF attr $attr->{id}\n";
+            print ACFILE "#endif\n";
+        }
+
+        print ACFILE "#ifndef $attr->{id}_GETMACRO\n";
+        print ACFILE "#error Platform does not support get of HWPF attr $attr->{id}\n";
+        print ACFILE "#endif\n\n";
+
+        #----------------------------------------------------------------------
+        # Print newline between each attribute's info to fapiAttributeIds.H
+        #----------------------------------------------------------------------
+        print AIFILE "\n";
+    };
+}
+
+=cut
+
+#------------------------------------------------------------------------------
+# Print End of file information to fapiAttributeIds.H
+#------------------------------------------------------------------------------
+print AIFILE "} //fapi2 \n\n";
+print AIFILE "#endif // __ASSEMBLER__\n\n";
+print AIFILE "#endif\n";
+
+#------------------------------------------------------------------------------
+# Print End of file information to fapiChipEcFeature.C
+#------------------------------------------------------------------------------
+print ECFILE "                default:\n";
+print ECFILE "                    FAPI_ERR(\"fapiQueryChipEcFeature: Unknown feature 0x%x\",\n";
+print ECFILE "                        i_id);\n";
+print ECFILE "                    l_rc.setFapiError(FAPI_RC_INVALID_CHIP_EC_FEATURE_GET);\n";
+print ECFILE "                    l_rc.addEIFfdc(0, &i_id, sizeof(i_id));\n";
+print ECFILE "                    break;\n";
+print ECFILE "                }\n\n";
+print ECFILE "                if (o_hasFeature)\n";
+print ECFILE "                {\n";
+print ECFILE "                    FAPI_INF(\"fapiQueryChipEcFeature: Chip (0x%x:0x%x) has ";
+print ECFILE "feature (0x%x)\", l_chipName, l_chipEc, i_id);\n";
+print ECFILE "                }\n";
+print ECFILE "                else\n";
+print ECFILE "                {\n";
+print ECFILE "                    FAPI_INF(\"fapiQueryChipEcFeature: Chip (0x%x:0x%x) does not ";
+print ECFILE "have feature (0x%x)\", l_chipName, l_chipEc, i_id);\n";
+print ECFILE "                }\n";
+print ECFILE "            }\n";
+print ECFILE "        }\n";
+print ECFILE "    }\n";
+print ECFILE "    return l_rc;\n";
+print ECFILE "}\n\n";
+print ECFILE "}\n";
+
+
+#------------------------------------------------------------------------------
+# Print End of file information to fapiAttributePlatCheck.H
+#------------------------------------------------------------------------------
+print ACFILE "#endif\n";
+
+#------------------------------------------------------------------------------
+# Print End of file information to fapiAttributesSupported.html
+#------------------------------------------------------------------------------
+print ASFILE "</table>\n\n";
+print ASFILE "</body>\n";
+print ASFILE "</html>\n";
+
+
+
+
+
+
+
+
+
+#------------------------------------------------------------------------------
+# Close output files
+#------------------------------------------------------------------------------
+close(AIFILE);
+close(ECFILE);
+close(ACFILE);
+close(ASFILE);
+close(ITFILE);
+close(ETFILE);
+
diff --git a/src/ppe/tools/scripts/ppeParseProcSbeFixed.pl b/src/ppe/tools/scripts/ppeParseProcSbeFixed.pl
new file mode 100755
index 0000000..8f25582
--- /dev/null
+++ b/src/ppe/tools/scripts/ppeParseProcSbeFixed.pl
@@ -0,0 +1,277 @@
+#!/usr/bin/perl
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ppe/tools/scripts/ppeParseProcSbeFixed.pl $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+# Purpose:  This perl script will parse HWP Attribute XML files and
+# initfile attr files and create the fapiGetInitFileAttr() function
+# in a file called fapiAttributeService.C
+
+use strict;
+
+#------------------------------------------------------------------------------
+# Print Command Line Help
+#------------------------------------------------------------------------------
+my $numArgs = $#ARGV + 1;
+if ($numArgs < 3)
+{
+    print ("Usage: ppeParseProcSbeFixed.pl <output dir>\n");
+    print ("           [<if-attr-file1> <if-attr-file2> ...]\n");
+    print ("           -a <attr-xml-file1> [<attr-xml-file2> ...]\n");
+    print ("  This perl script will parse if-attr files (containing the\n");
+    print ("  attributes used by the initfile) and attribute XML files\n");
+    print ("  (containing all HWPF attributes) and create the\n");
+    print ("  fapiGetInitFileAttr() function in a file called\n");
+    print ("  fapiAttributeService.C. Only the attributes specified in\n");
+    print ("  the if-attr files are supported. If no if-attr files are\n");
+    print ("  specified then all attributes are supported\n");
+    exit(1);
+}
+
+#------------------------------------------------------------------------------
+# Specify perl modules to use
+#------------------------------------------------------------------------------
+use XML::Simple;
+my $xml = new XML::Simple (KeyAttr=>[]);
+
+# Uncomment to enable debug output
+#use Data::Dumper;
+
+#------------------------------------------------------------------------------
+# Open output file for writing
+#------------------------------------------------------------------------------
+my $chipFile = $ARGV[0];
+$chipFile .= "/";
+$chipFile .= "proc_sbe_fixed_proc_chip.H";
+open(CHFILE, ">", $chipFile);
+
+my $exFile = $ARGV[0];
+$exFile .= "/";
+$exFile .= "proc_sbe_fixed_ex.H";
+open(EXFILE, ">", $exFile);
+
+my $coreFile = $ARGV[0];
+$coreFile .= "/";
+$coreFile .= "proc_sbe_fixed_core.H";
+open(COFILE, ">", $coreFile);
+
+my $eqFile = $ARGV[0];
+$eqFile .= "/";
+$eqFile .= "proc_sbe_fixed_eq.H";
+open(EQFILE, ">", $eqFile);
+
+my $pervFile = $ARGV[0];
+$pervFile .= "/";
+$pervFile .= "proc_sbe_fixed_perv.H";
+open(PEFILE, ">", $pervFile);
+
+
+
+my $xmlFiles = 0;
+my $attCount = 0;
+my $numIfAttrFiles = 0;
+my @attrChipIds;
+my @attrExIds;
+my @attrCoreIds;
+my @attrEqIds;
+my @attrPervIds;
+
+
+
+#------------------------------------------------------------------------------
+# Element names
+#------------------------------------------------------------------------------
+my $attribute = 'attribute';
+
+#------------------------------------------------------------------------------
+# For each argument
+#------------------------------------------------------------------------------
+my $argfile = $ARGV[1];
+my $entries = $xml->XMLin($argfile, ForceArray => ['entry']);
+foreach my $entr (@{$entries->{entry}}) {
+
+    my $inname = $entr->{name};
+
+    # read XML file. The ForceArray option ensures that there is an array of
+    # elements even if there is only one such element in the file
+
+    foreach my $argnum (2 .. $#ARGV)
+    {
+        my $infile = $ARGV[$argnum];
+
+        my $attributes = $xml->XMLin($infile, ForceArray => ['attribute']);
+
+        # Uncomment to get debug output of all attributes
+        #print "\nFile: ", $infile, "\n", Dumper($attributes), "\n";
+
+        #--------------------------------------------------------------------------
+        # For each Attribute
+        #--------------------------------------------------------------------------
+        foreach my $attr (@{$attributes->{attribute}})
+        {
+
+            if($attr->{id} eq $inname) {
+
+            #------------------------------------------------------------------
+            # Check that the AttributeId exists
+            #------------------------------------------------------------------
+            if (! exists $attr->{id})
+            {
+                print ("fapiParseAttributeInfo.pl ERROR. Att 'id' missing\n");
+                exit(1);
+            }
+
+
+            if($attr->{targetType} eq "TARGET_TYPE_PROC_CHIP") {
+
+                #push(@attrChipIds, $attr->{id});
+                push(@attrChipIds, $attr);
+
+            } elsif($attr->{targetType} eq "TARGET_TYPE_CORE") {
+
+   #             push(@attrCoreIds, $attr->{id});
+                push(@attrCoreIds, $attr);
+                
+            } elsif($attr->{targetType} eq "TARGET_TYPE_EQ") {
+
+  #              push(@attrEqIds, $attr->{id});
+                push(@attrEqIds, $attr);
+
+            } elsif($attr->{targetType} eq "TARGET_TYPE_EX") { 
+
+ #               push(@attrExIds, $attr->{id});
+                push(@attrExIds, $attr);
+
+            } elsif($attr->{targetType} eq "TARGET_TYPE_PERV") { 
+
+#                push(@attrPervIds, $attr->{id});
+                push(@attrPervIds, $attr);
+
+            } else {
+
+                print ("ppeParseProcSbeFixed.pl ERROR. Wrong attribute type: $attr->{targetType} for attribute $attr->{id} in $infile\n");
+                exit(1);
+
+            }
+
+            }
+        }
+    }
+
+}
+
+
+print CHFILE "// proc_sbe_fixed_proc_chip.H\n";
+print CHFILE "// This file is generated by perl script ppeParseProcSbeFixed.pl\n\n";
+print CHFILE "#ifndef __PROC_SBE_FIXED_PROC_CHIP_H__\n";
+print CHFILE "#define __PROC_SBE_FIXED_PROC_CHIP_H__\n\n";
+foreach my $attr (@attrChipIds)
+{
+
+    my $value = uc $attr->{valueType};
+    print CHFILE "PROC_SBE_FIXED_$value($attr->{id});\n"
+    
+
+}
+print CHFILE "\n#endif  // __PROC_SBE_FIXED_PROC_CHIP_H__";
+
+print EXFILE "// proc_sbe_fixed_ex.H\n";
+print EXFILE "// This file is generated by perl script ppeParseProcSbeFixed.pl\n\n";
+print EXFILE "#ifndef __PROC_SBE_FIXED_EX_H__\n";
+print EXFILE "#define __PROC_SBE_FIXED_EX_H__\n";
+foreach my $attr (@attrExIds)
+{
+
+    my $value = uc $attr->{valueType};
+    print EXFILE "PROC_SBE_FIXED_TARGET_$value($attr->{id}, EX_TARGET_COUNT);\n"
+    
+
+}
+print EXFILE "\n#endif  // __PROC_SBE_FIXED_EX_H__";
+
+
+print COFILE "// proc_sbe_fixed_co.H\n";
+print COFILE "// This file is generated by perl script ppeParseProcSbeFixed.pl\n\n";
+print COFILE "#ifndef __PROC_SBE_FIXED_CO_H__\n";
+print COFILE "#define __PROC_SBE_FIXED_CO_H__\n";
+foreach my $attr (@attrCoreIds)
+{
+
+    my $value = uc $attr->{valueType};
+    print COFILE "PROC_SBE_FIXED_TARGET_$value($attr->{id}, CORE_TARGET_COUNT);\n"
+    
+
+}
+print COFILE "\n#endif  // __PROC_SBE_FIXED_CO_H__";
+
+
+
+print EQFILE "// proc_sbe_fixed_eq.H\n";
+print EQFILE "// This file is generated by perl script ppeParseProcSbeFixed.pl\n\n";
+print EQFILE "#ifndef __PROC_SBE_FIXED_EQ_H__\n";
+print EQFILE "#define __PROC_SBE_FIXED_EQ_H__\n";
+foreach my $attr (@attrEqIds)
+{
+
+    my $value = uc $attr->{valueType};
+    print EQFILE "PROC_SBE_FIXED_TARGET_$value($attr->{id}, EQ_TARGET_COUNT);\n"
+    
+
+}
+print EQFILE "\n#endif  // __PROC_SBE_FIXED_EQ_H__";
+
+
+
+print PEFILE "// proc_sbe_fixed_perv.H\n";
+print PEFILE "// This file is generated by perl script ppeParseProcSbeFixed.pl\n\n";
+print PEFILE "#ifndef __PROC_SBE_FIXED_PERV_H__\n";
+print PEFILE "#define __PROC_SBE_FIXED_PERV_H__\n";
+foreach my $attr (@attrPervIds)
+{
+
+    my $value = uc $attr->{valueType};
+    print PEFILE "PROC_SBE_FIXED_TARGET_$value($attr->{id}, PERV_TARGET_COUNT);\n"
+    
+
+}
+print PEFILE "\n#endif  // __PROC_SBE_FIXED_PERV_H__";
+
+
+
+
+
+
+
+
+#print ASFILE "#endif  // __PROC_SBE_FIXED_H__";
+
+
+#------------------------------------------------------------------------------
+# Close output file
+#------------------------------------------------------------------------------
+close(CHFILE);
+close(COFILE);
+close(EXFILE);
+close(PEFILE);
+close(EQFILE);
+
diff --git a/src/ppe/tools/scripts/src/fapi2PlatAttributeService.H b/src/ppe/tools/scripts/src/fapi2PlatAttributeService.H
new file mode 100644
index 0000000..fdb65a6
--- /dev/null
+++ b/src/ppe/tools/scripts/src/fapi2PlatAttributeService.H
@@ -0,0 +1,1085 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ppe/tools/scripts/src/fapi2PlatAttributeService.H $       */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ *  @file fapiPlatAttributeService.H
+ *
+ *  @brief Defines the PLAT attribute access macros and defines which macro
+ *         handles each attribute.
+ *
+ */
+
+
+#ifndef FAPI2PLATATTRIBUTESERVICE_H_
+#define FAPI2PLATATTRIBUTESERVICE_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <fapi2AttributeIds.H>
+#include <plat_includes.H>
+#include "proc_sbe_fixed.H"
+#include "plat_target_parms.H"
+
+#define PLAT_GET_CHIP_EC_FEATURE_OVERRIDE(ID, PTARGET, VAL) \
+      fapi2::_getEcFeatureOverride<fapi2::ID##_Type>(fapi2::ID, PTARGET, VAL)
+
+/* INSERT NEW ATTRIBUTES HERE */
+
+#define ATTR_TARGET_SCOMABLE_GETMACRO PLAT_ATTR_GET_GLOBAL_INT
+#define ATTR_TARGET_SCOMABLE_SETMACRO PLAT_ATTR_SET_GLOBAL_INT
+
+
+
+/******************************************************************************/
+/*                          * Global macros *                                 */
+/* These macros are called by the macros above to invoke the appropriate API. */
+/* These macros do not need to change when a new attribute is introduced.     */
+/******************************************************************************/
+
+/* global get uint8_t 1D array macro */
+#define PLAT_ATTR_GET_UINT8_1D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeArrayShort<fapi2::ID##_Type, static_cast<TargetType>(fapi2::ID##_TargetTypes), fapi2::ID> \
+            (fapi2::ID, PTARGET, VAL)    
+     
+/* global set uint8_t 1D array macro */
+#define PLAT_ATTR_SET_UINT8_1D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_setAttributeArrayShort<fapi2::ID##_Type, static_cast<TargetType>(fapi2::ID##_TargetTypes), fapi2::ID> \
+            (fapi2::ID, PTARGET, VAL)   
+
+/* global get uint8_t 2D array macro */
+#define PLAT_ATTR_GET_UINT8_2D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeArrayShort(fapi2::ID, PTARGET, VAL[0])
+/* global set uint8_t 2D array macro */
+#define PLAT_ATTR_SET_UINT8_2D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_setAttributeArrayShort(fapi2::ID, PTARGET, VAL[0])
+
+/* global get uint8_t 3D array macro */
+#define PLAT_ATTR_GET_UINT8_3D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeArrayShort(fapi2::ID, PTARGET, VAL[0][0])
+/* global set uint8_t 3D array macro */
+#define PLAT_ATTR_SET_UINT8_3D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_setAttributeArrayShort(fapi2::ID, PTARGET, VAL[0][0])
+
+/* global get uint8_t 4D array macro */
+#define PLAT_ATTR_GET_UINT8_4D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeArrayShort(fapi2::ID, PTARGET, VAL[0][0][0])
+/* global set uint8_t 4D array macro */
+#define PLAT_ATTR_SET_UINT8_4D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_setAttributeArrayShort(fapi2::ID, PTARGET, VAL[0][0][0])
+
+/* global get uint32_t 1D array macro */
+#define PLAT_ATTR_GET_UINT32_1D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeArrayWord(fapi2::ID, PTARGET, VAL)
+/* global set uint32_t 1D array macro */
+#define PLAT_ATTR_SET_UINT32_1D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_setAttributeArrayWord(fapi2::ID, PTARGET, VAL)
+
+/* global get uint32_t 2D array macro */
+#define PLAT_ATTR_GET_UINT32_2D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeArrayWord(fapi2::ID, PTARGET, VAL[0])
+/* global set uint32_t 2D array macro */
+#define PLAT_ATTR_SET_UINT32_2D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_setAttributeArrayWord(fapi2::ID, PTARGET, VAL[0])
+
+/* global get uint32_t 3D array macro */
+#define PLAT_ATTR_GET_UINT32_3D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeArrayWord(fapi2::ID, PTARGET, VAL[0][0])
+/* global set uint32_t 3D array macro */
+#define PLAT_ATTR_SET_UINT32_3D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_setAttributeArrayWord(fapi2::ID, PTARGET, VAL[0][0])
+
+/* global get uint32_t 4D array macro */
+#define PLAT_ATTR_GET_UINT32_4D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeArrayWord(fapi2::ID, PTARGET, VAL[0][0][0])
+/* global set uint32_t 4D array macro */
+#define PLAT_ATTR_SET_UINT32_4D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_setAttributeArrayWord(fapi2::ID, PTARGET, VAL[0][0][0])
+
+
+/* global get uint64_t 1D array macro */
+#define PLAT_ATTR_GET_UINT64_1D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeArrayDoubleWord(fapi2::ID, PTARGET, VAL)
+/* global set uint64_t 1D array macro */
+#define PLAT_ATTR_SET_UINT64_1D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_setAttributeArrayDoubleWord(fapi2::ID, PTARGET, VAL)
+
+/* global get uint64_t 2D array macro */
+#define PLAT_ATTR_GET_UINT64_2D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeArrayDoubleWord(fapi2::ID, PTARGET, VAL[0])
+/* global set uint64_t 2D array macro */
+#define PLAT_ATTR_SET_UINT64_2D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_setAttributeArrayDoubleWord(fapi2::ID, PTARGET, VAL[0])
+
+/* global get uint64_t 3D array macro */
+#define PLAT_ATTR_GET_UINT64_3D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeArrayDoubleWord(fapi2::ID, PTARGET, VAL[0][0])
+/* global set uint64_t 3D array macro */
+#define PLAT_ATTR_SET_UINT64_3D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_setAttributeArrayDoubleWord(fapi2::ID, PTARGET, VAL[0][0])
+
+/* global get uint64_t 4D array macro */
+#define PLAT_ATTR_GET_UINT64_4D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeArrayDoubleWord(fapi2::ID, PTARGET, VAL[0][0][0])
+/* global set uint64_t 4D array macro */
+#define PLAT_ATTR_SET_UINT64_4D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_setAttributeArrayDoubleWord(fapi2::ID, PTARGET, VAL[0][0][0])
+
+/* global get int macro (uint8_t, 32 and 64) */
+#define PLAT_ATTR_GET_GLOBAL_INT(ID, PTARGET, VAL) \
+     fapi2::_get<fapi2::ID##_Type, static_cast<TargetType>(fapi2::ID##_TargetTypes), fapi2::ID> \
+                (fapi2::ID, PTARGET, VAL)
+
+/* global set int macro (uint8_t, 32 and 64) */
+#define PLAT_ATTR_SET_GLOBAL_INT(ID, PTARGET, VAL) \
+     fapi2::_set<fapi2::ID##_Type, static_cast<TargetType>(fapi2::ID##_TargetTypes), fapi2::ID> \
+                (fapi2::ID, PTARGET, VAL)
+
+
+//here
+
+/******************************************************************************/
+// Get Override Macros
+/******************************************************************************/
+/* global get override uint8_t 1D array macro */
+#define PLAT_ATTR_GET_OVERRIDE_UINT8_1D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeOverrideArrayShort(fapi2::ID, PTARGET, VAL)
+/* global get override uint8_t 2D array macro */
+#define PLAT_ATTR_GET_OVERRIDE_UINT8_2D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeOverrideArrayShort(fapi2::ID, PTARGET, VAL[0])
+/* global get override uint8_t 3D array macro */
+#define PLAT_ATTR_GET_OVERRIDE_UINT8_3D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeOverrideArrayShort(fapi2::ID, PTARGET, VAL[0][0])
+/* global get override uint8_t 4D array macro */
+#define PLAT_ATTR_GET_OVERRIDE_UINT8_4D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeOverrideArrayShort(fapi2::ID, PTARGET, VAL[0][0][0])
+
+
+/* global get override uint32_t 1D array macro */
+#define PLAT_ATTR_GET_OVERRIDE_UINT32_1D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeOverrideArrayWord(fapi2::ID, PTARGET, VAL)
+/* global get override uint32_t 2D array macro */
+#define PLAT_ATTR_GET_OVERRIDE_UINT32_2D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeOverrideArrayWord(fapi2::ID, PTARGET, VAL[0])
+/* global get override uint32_t 3D array macro */
+#define PLAT_ATTR_GET_OVERRIDE_UINT32_3D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeOverrideArrayWord(fapi2::ID, PTARGET, VAL[0][0])
+/* global get override uint32_t 4D array macro */
+#define PLAT_ATTR_GET_OVERRIDE_UINT32_4D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeOverrideArrayWord(fapi2::ID, PTARGET, VAL[0][0][0])
+
+
+/* global get override uint64_t 1D array macro */
+#define PLAT_ATTR_GET_OVERRIDE_UINT64_1D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeOverrideArrayDoubleWord(fapi2::ID, PTARGET, VAL)
+/* global get override uint64_t 2D array macro */
+#define PLAT_ATTR_GET_OVERRIDE_UINT64_2D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeOverrideArrayDoubleWord(fapi2::ID, PTARGET, VAL[0])
+/* global get override uint64_t 3D array macro */
+#define PLAT_ATTR_GET_OVERRIDE_UINT64_3D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeOverrideArrayDoubleWord(fapi2::ID, PTARGET, VAL[0][0])
+/* global get override uint64_t 4D array macro */
+#define PLAT_ATTR_GET_OVERRIDE_UINT64_4D_ARRAY(ID, PTARGET, VAL) \
+     fapi2::_getAttributeOverrideArrayDoubleWord(fapi2::ID, PTARGET, VAL[0][0][0])
+
+/* global get override int macro (uint8_t, 32 and 64) */
+#define PLAT_ATTR_GET_OVERRIDE_GLOBAL_INT(ID, PTARGET, VAL) \
+     fapi2::_getOverride<fapi2::ID##_Type>(fapi2::ID, PTARGET, VAL)
+
+/******************************************************************************/
+// Get string 
+/******************************************************************************/
+
+extern "C" 
+{ 
+    extern fapi2attr::ProcChipAttributes_t* G_proc_chip_attributes asm("G_proc_chip_attributes")  __attribute__ ((section (".fixed")));
+    extern fapi2attr::PervAttributes_t*     G_perv_attributes      asm("G_perv_attributes")  __attribute__ ((section (".fixed")));
+    extern fapi2attr::CoreAttributes_t*     G_core_attributes      asm("G_core_attributes")        __attribute__ ((section (".fixed")));
+    extern fapi2attr::EQAttributes_t*       G_eq_attributes        asm("G_eq_attributes")          __attribute__ ((section (".fixed")));
+    extern fapi2attr::EXAttributes_t*       G_ex_attributes        asm("G_ex_attributes")          __attribute__ ((section (".fixed")));
+
+}
+
+namespace fapi2 
+{
+
+
+// Parameters are done as pointers (vs references) to allow the attribute 
+// storage to be relocated
+template<fapi2::TargetType K, typename TAttrStruct, typename TValue, fapi2::AttributeId AId>
+void __set( const fapi2::Target<K>* i_ptarget, TAttrStruct* object, const fapi2::AttributeId attrid, TValue* value );
+
+template<fapi2::TargetType K, typename TAttrStruct, typename TValue, fapi2::AttributeId AId>
+void __get( const fapi2::Target<K>* i_ptarget, TAttrStruct* object, const fapi2::AttributeId attrid, TValue* value );
+
+
+/* INSERT NEW GETTER AND SETTER FUNCTIONS HERE */
+
+
+
+//******************************************************************************
+// Get base template
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _get(const AttributeId i_Id,
+                const Target<K> * const i_pTarget,
+                T& o_value)
+{
+    return FAPI2_RC_SUCCESS;    
+}
+
+//******************************************************************************
+// Get uint8_t 
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _get(const fapi2::AttributeId i_id,
+                const Target<K> * const i_pTarget,
+                uint8_t& o_value)
+{
+    static_assert(std::is_same<T, uint8_t>::value, "Attribute type mismatch");
+
+    if(K & TARGET_TYPE_PROC_CHIP)
+    {
+        __get<K, fapi2attr::ProcChipAttributes_t, T, A>( i_pTarget, G_proc_chip_attributes, i_id, &o_value );  
+    }
+
+    if(K & TARGET_TYPE_PERV)
+    {
+         __get<K, fapi2attr::PervAttributes_t, T, A>( i_pTarget, G_perv_attributes, i_id, &o_value );  
+    }
+
+    if(K & TARGET_TYPE_CORE)
+    {
+        __get<K, fapi2attr::CoreAttributes_t, T, A>( i_pTarget, G_core_attributes, i_id, &o_value );  
+    }
+
+    if(K & TARGET_TYPE_EQ)
+    {
+        __get<K, fapi2attr::EQAttributes_t, T, A>( i_pTarget, G_eq_attributes, i_id, &o_value );  
+    }
+    
+    if(K & TARGET_TYPE_EX)
+    {                                           
+        __get<K, fapi2attr::EXAttributes_t, T, A>( i_pTarget, G_ex_attributes, i_id, &o_value );                     
+    }        
+ 
+    return FAPI2_RC_SUCCESS;
+}
+
+
+//******************************************************************************
+// Get uint32_t 
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _get(const AttributeId i_id,
+                const Target<K> * const i_pTarget,
+                uint32_t& o_value)
+{
+    static_assert(std::is_same<T, uint32_t>::value, "Attribute type mismatch");
+    
+    if(K & TARGET_TYPE_PROC_CHIP)
+    {
+        __get<K, fapi2attr::ProcChipAttributes_t, T, A>( i_pTarget, G_proc_chip_attributes, i_id, &o_value );  
+    }
+
+    if(K & TARGET_TYPE_PERV)
+    {
+         __get<K, fapi2attr::PervAttributes_t, T, A>( i_pTarget, G_perv_attributes, i_id, &o_value );  
+    }
+
+    if(K & TARGET_TYPE_CORE)
+    {
+        __get<K, fapi2attr::CoreAttributes_t, T, A>( i_pTarget, G_core_attributes, i_id, &o_value );  
+    }
+
+    if(K & TARGET_TYPE_EQ)
+    {
+        __get<K, fapi2attr::EQAttributes_t, T, A>( i_pTarget, G_eq_attributes, i_id, &o_value );  
+    }
+    
+    if(K & TARGET_TYPE_EX)
+    {                                           
+        __get<K, fapi2attr::EXAttributes_t, T, A>( i_pTarget, G_ex_attributes, i_id, &o_value );                     
+    }        
+ 
+    return FAPI2_RC_SUCCESS;
+}
+
+
+//******************************************************************************
+// Get uint64_t 
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _get(const AttributeId i_id,
+                const Target<K> * const i_pTarget,
+                uint64_t& o_value)
+{
+    static_assert(std::is_same<T, uint64_t>::value, "Attribute type mismatch");
+    
+
+    if(K & TARGET_TYPE_PROC_CHIP)
+    {
+        __get<K, fapi2attr::ProcChipAttributes_t, T, A>( i_pTarget, G_proc_chip_attributes, i_id, &o_value );  
+    }
+
+    if(K & TARGET_TYPE_PERV)
+    {
+         __get<K, fapi2attr::PervAttributes_t, T, A>( i_pTarget, G_perv_attributes, i_id, &o_value );  
+    }
+
+    if(K & TARGET_TYPE_CORE)
+    {
+        __get<K, fapi2attr::CoreAttributes_t, T, A>( i_pTarget, G_core_attributes, i_id, &o_value );  
+    }
+
+    if(K & TARGET_TYPE_EQ)
+    {
+        __get<K, fapi2attr::EQAttributes_t, T, A>( i_pTarget, G_eq_attributes, i_id, &o_value );  
+    }
+    
+    if(K & TARGET_TYPE_EX)
+    {                                           
+        __get<K, fapi2attr::EXAttributes_t, T, A>( i_pTarget, G_ex_attributes, i_id, &o_value );                     
+    }        
+
+    return FAPI2_RC_SUCCESS;    
+}
+
+
+//******************************************************************************
+// Get Override uint8_t 
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _getOverride(const AttributeId i_id,
+                        const Target<K> * const i_pTarget,
+                        uint8_t& o_value)
+{
+    static_assert(std::is_same<T, uint8_t>::value, "Attribute type mismatch");
+
+    return FAPI2_RC_SUCCESS;    
+}
+
+
+//******************************************************************************
+// Get Override uint32_t 
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _getOverride(const AttributeId i_id,
+                        const Target<K> * const i_pTarget,
+                        uint32_t& o_value)
+{
+    static_assert(std::is_same<T, uint32_t>::value, "Attribute type mismatch");
+
+    return FAPI2_RC_SUCCESS;   
+}
+
+
+//******************************************************************************
+// Get Override uint64_t 
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _getOverride(const AttributeId i_id,
+                        const Target<K> * const i_pTarget,
+                        uint64_t& o_value)
+{
+    static_assert(std::is_same<T, uint64_t>::value, "Attribute type mismatch");
+
+    return FAPI2_RC_SUCCESS;    
+}
+
+
+//******************************************************************************
+// Get override EC Feature (uint8_t)
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _getEcFeatureOverride(const AttributeId i_id,
+                                 const Target<K> * const i_pTarget,
+                                 uint8_t& o_value)
+{
+    static_assert(std::is_same<T, uint8_t>::value, "Attribute type mismatch");
+
+    // The way this is implemented, we want to return a non-zero return code if we found an override.  
+    // Return 0 if there was an error.
+    // This is how it's implemented:
+    // PLAT_GET_CHIP_EC_FEATURE_OVERRIDE(ID, PTARGET, VAL) ? fapi::FAPI_RC_SUCCESS : fapi::fapiQueryChipEcFeature(fapi::ID, PTARGET, VAL)
+
+    return FAPI2_RC_SUCCESS;    
+}
+
+
+//******************************************************************************
+// Get uint8_t array
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _getAttributeArrayShort(const AttributeId i_id,
+                                   const Target<K> * const i_pTarget,
+                                   uint8_t * o_pValues)
+{
+//       fapi2::Attributeta o_data;
+//     fapi2::ReturnCode l_fapi_rc(FAPI2_RC_SUCCESS); 
+//     uint32_t l_ecmd_rc = ECMD_SUCCESS;
+// 
+//     ecmdChipTarget l_ecmd_target;
+//     fapiTargetPointerToEcmdTarget(i_pTarget, l_ecmd_target);
+// 
+//     o_data.faValidMask = FAPI_ATTRIBUTE_TYPE_UINT8ARY;
+//     o_data.faUint8ary = o_pValues;
+// 
+//     l_ecmd_rc = fapi2GetAttribute(l_ecmd_target, i_id, o_data); 
+//     if (l_ecmd_rc)
+//     {
+//         l_fapi_rc = (ReturnCodes) l_ecmd_rc;
+//     }
+//     return l_fapi_rc;
+    return FAPI2_RC_SUCCESS;
+}
+
+//******************************************************************************
+// Set uint8_t array
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _setAttributeArrayShort(const AttributeId i_id,
+                                   const Target<K> * const i_pTarget,
+                                   uint8_t * i_pValues)
+{
+    if(K & TARGET_TYPE_PROC_CHIP)
+    {
+        __set<K, fapi2attr::CoreAttributes_t, T, A>( *i_pTarget, G_proc_chip_attributes, *i_pValues );  
+    }
+
+    if(K & TARGET_TYPE_PERV)
+    {
+        __set<K, fapi2attr::PervAttributes_t, T, A>( *i_pTarget, G_perv_attributes, i_pValues );  
+    }
+
+    if(K & TARGET_TYPE_CORE)
+    {
+        __set<K, fapi2attr::CoreAttributes_t, T, A>( *i_pTarget, G_core_attributes, *i_pValues );  
+    }
+
+    if(K & TARGET_TYPE_EQ)
+    {
+        __set<K, fapi2attr::EQAttributes_t, T, A>( *i_pTarget, G_eq_attributes, *i_pValues );  
+    }
+    
+    if(K & TARGET_TYPE_EX)
+    {                                           
+        __set<K, fapi2attr::EXAttributes_t, T, A>( *i_pTarget, G_ex_attributes, *i_pValues );                         
+    }
+    
+    return FAPI2_RC_SUCCESS;
+}
+
+//******************************************************************************
+// Get uint32_t array
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _getAttributeArrayWord(const AttributeId i_id,
+                                  const Target<K> * const i_pTarget,
+                                  uint32_t * o_pValues)
+{
+    return FAPI2_RC_SUCCESS;
+}
+
+//******************************************************************************
+// Set uint32_t array
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _setAttributeArrayWord(const AttributeId i_id,
+                                  const Target<K> * const i_pTarget,
+                                  uint32_t * i_pValues)
+{
+    return FAPI2_RC_SUCCESS;
+}
+
+//******************************************************************************
+// Get uint64_t array
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _getAttributeArrayDoubleWord(const AttributeId i_id,
+                                        const Target<K> * const i_pTarget,
+                                        uint64_t * o_pValues)
+{
+    return FAPI2_RC_SUCCESS;
+}
+
+//******************************************************************************
+// Set uint64_t array
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _setAttributeArrayDoubleWord(const AttributeId i_id,
+                                        const Target<K> * const i_pTarget,
+                                        uint64_t * i_pValues)
+{
+    return FAPI2_RC_SUCCESS;
+}
+
+//******************************************************************************
+// Get Override uint8_t array
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _getAttributeOverrideArrayShort(const AttributeId i_id,
+                                           const Target<K> * const i_pTarget,
+                                           uint8_t * o_pValues)
+{
+    return FAPI2_RC_SUCCESS;
+}
+
+//******************************************************************************
+// Get Override uint32_t array
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _getAttributeOverrideArrayWord(const AttributeId i_id,
+                                          const Target<K> * const i_pTarget,
+                                          uint32_t * o_pValues)
+{
+    return FAPI2_RC_SUCCESS;
+}
+
+//******************************************************************************
+// Get Override uint64_t array
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _getAttributeOverrideArrayDoubleWord(const AttributeId i_id,
+                                                const Target<K> * const i_pTarget,
+                                                uint64_t * o_pValues)
+{
+    return FAPI2_RC_SUCCESS;
+}
+
+
+//******************************************************************************
+// Set base template
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _set(const AttributeId i_Id,
+                const Target<K> * const i_pTarget,
+                T& i_value)
+{
+    return FAPI2_RC_SUCCESS;    
+}
+
+
+
+//******************************************************************************
+// Set uint8_t 
+//******************************************************************************
+template<typename T, TargetType K, typename A>
+ReturnCode _set(const AttributeId i_Id,
+                const Target<K> * const i_pTarget,
+                uint8_t& i_value)
+{
+    static_assert(std::is_same<T, uint8_t>::value, "Attribute type mismatch"); // May need to remove
+
+    if(K & TARGET_TYPE_PROC_CHIP)
+    {
+        __set<K, fapi2attr::CoreAttributes_t, T, A>( *i_pTarget, G_proc_chip_attributes, i_value );  
+    }
+
+    if(K & TARGET_TYPE_PERV)
+    {
+        __set<K, fapi2attr::PervAttributes_t, T, A>( *i_pTarget, G_perv_attributes, i_value );  
+    }
+
+    if(K & TARGET_TYPE_CORE)
+    {
+        __set<K, fapi2attr::CoreAttributes_t, T, A>( *i_pTarget, G_core_attributes, i_value );  
+    }
+
+    if(K & TARGET_TYPE_EQ)
+    {
+        __set<K, fapi2attr::EQAttributes_t, T, A>( *i_pTarget, G_eq_attributes, i_value );  
+    }
+    
+    if(K & TARGET_TYPE_EX)
+    {                                           
+        __set<K, fapi2attr::EXAttributes_t, T, A>( *i_pTarget, G_ex_attributes, i_value );                         
+    }
+    
+    return FAPI2_RC_SUCCESS;
+}
+
+
+//******************************************************************************
+// Set uint32_t 
+//******************************************************************************
+template<typename T, TargetType K, typename A>
+ReturnCode _set(
+                const Target<K> * const i_pTarget,
+                uint32_t& i_value)
+{
+    static_assert(std::is_same<T, uint32_t>::value, "Attribute type mismatch"); // May need to remove
+
+    if(K & TARGET_TYPE_PROC_CHIP)
+    {
+        __set<K, fapi2attr::CoreAttributes_t, T, A>( *i_pTarget, G_proc_chip_attributes, i_value );  
+    }
+
+    if(K & TARGET_TYPE_PERV)
+    {
+        __set<K, fapi2attr::PervAttributes_t, T, A>( *i_pTarget, G_perv_attributes, i_value );  
+    }
+
+    if(K & TARGET_TYPE_CORE)
+    {
+        __set<K, fapi2attr::CoreAttributes_t, T, A>( *i_pTarget, G_core_attributes, i_value );  
+    }
+
+    if(K & TARGET_TYPE_EQ)
+    {
+        __set<K, fapi2attr::EQAttributes_t, T, A>( *i_pTarget, G_eq_attributes, i_value );  
+    }
+    
+    if(K & TARGET_TYPE_EX)
+    {                                           
+        __set<K, fapi2attr::EXAttributes_t, T, A>( *i_pTarget, G_ex_attributes, i_value );                         
+    }
+    
+    return FAPI2_RC_SUCCESS;
+}
+
+
+//******************************************************************************
+// Set uint64_t 
+//******************************************************************************
+
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _set(const AttributeId i_Id,
+                const Target<K> * const i_pTarget,
+                const uint64_t & i_value)
+{
+    static_assert(std::is_same<T, uint64_t>::value, "Attribute type mismatch"); // May need to remove
+
+    if(K & TARGET_TYPE_PROC_CHIP)
+    {
+        __set<K, fapi2attr::CoreAttributes_t, T, A>( *i_pTarget, G_proc_chip_attributes, i_value );  
+    }
+
+    if(K & TARGET_TYPE_PERV)
+    {
+        __set<K, fapi2attr::PervAttributes_t, T, A>( *i_pTarget, G_perv_attributes, i_value );  
+    }
+
+    if(K & TARGET_TYPE_CORE)
+    {
+        __set<K, fapi2attr::CoreAttributes_t, T, A>( *i_pTarget, G_core_attributes, i_value );  
+    }
+
+    if(K & TARGET_TYPE_EQ)
+    {
+        __set<K, fapi2attr::EQAttributes_t, T, A>( *i_pTarget, G_eq_attributes, i_value );  
+    }
+    
+    if(K & TARGET_TYPE_EX)
+    {                                           
+        __set<K, fapi2attr::EXAttributes_t, T, A>( *i_pTarget, G_ex_attributes, i_value );                         
+    }
+    
+    return FAPI2_RC_SUCCESS;
+}
+
+
+//******************************************************************************
+// Get int8_t 
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _get(const AttributeId i_id,
+                const Target<K> * const i_pTarget,
+                int8_t& o_value)
+{
+    static_assert(std::is_same<T, int8_t>::value, "Attribute type mismatch");
+
+    if(K & TARGET_TYPE_PROC_CHIP)
+    {
+        __get<K, fapi2attr::ProcChipAttributes_t, T, A>( i_pTarget, G_proc_chip_attributes, i_id, &o_value );  
+    }
+
+    if(K & TARGET_TYPE_PERV)
+    {
+         __get<K, fapi2attr::PervAttributes_t, T, A>( i_pTarget, G_perv_attributes, i_id, &o_value );  
+    }
+
+    if(K & TARGET_TYPE_CORE)
+    {
+        __get<K, fapi2attr::CoreAttributes_t, T, A>( i_pTarget, G_core_attributes, i_id, &o_value );  
+    }
+
+    if(K & TARGET_TYPE_EQ)
+    {
+        __get<K, fapi2attr::EQAttributes_t, T, A>( i_pTarget, G_eq_attributes, i_id, &o_value );  
+    }
+    
+    if(K & TARGET_TYPE_EX)
+    {                                           
+        __get<K, fapi2attr::EXAttributes_t, T, A>( i_pTarget, G_ex_attributes, i_id, &o_value );                     
+    }        
+
+    return FAPI2_RC_SUCCESS;    
+}
+
+
+//******************************************************************************
+// Get int32_t 
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _get(const AttributeId i_id,
+                const Target<K> * const i_pTarget,
+                int32_t& o_value)
+{
+    static_assert(std::is_same<T, int32_t>::value, "Attribute type mismatch");
+
+    if(K & TARGET_TYPE_PROC_CHIP)
+    {
+        __get<K, fapi2attr::ProcChipAttributes_t, T, A>( i_pTarget, G_proc_chip_attributes, i_id, &o_value );  
+    }
+
+    if(K & TARGET_TYPE_PERV)
+    {
+         __get<K, fapi2attr::PervAttributes_t, T, A>( i_pTarget, G_perv_attributes, i_id, &o_value );  
+    }
+
+    if(K & TARGET_TYPE_CORE)
+    {
+        __get<K, fapi2attr::CoreAttributes_t, T, A>( i_pTarget, G_core_attributes, i_id, &o_value );  
+    }
+
+    if(K & TARGET_TYPE_EQ)
+    {
+        __get<K, fapi2attr::EQAttributes_t, T, A>( i_pTarget, G_eq_attributes, i_id, &o_value );  
+    }
+    
+    if(K & TARGET_TYPE_EX)
+    {                                           
+        __get<K, fapi2attr::EXAttributes_t, T, A>( i_pTarget, G_ex_attributes, i_id, &o_value );                     
+    }        
+
+    return FAPI2_RC_SUCCESS;    
+}
+
+
+//******************************************************************************
+// Get int64_t 
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _get(const AttributeId i_id,
+                const Target<K> * const i_pTarget,
+                int64_t& o_value)
+{
+    static_assert(std::is_same<T, int64_t>::value, "Attribute type mismatch");
+
+    if(K & TARGET_TYPE_PROC_CHIP)
+    {
+        __get<K, fapi2attr::ProcChipAttributes_t, T, A>( i_pTarget, G_proc_chip_attributes, i_id, &o_value );  
+    }
+
+    if(K & TARGET_TYPE_PERV)
+    {
+         __get<K, fapi2attr::PervAttributes_t, T, A>( i_pTarget, G_perv_attributes, i_id, &o_value );  
+    }
+
+    if(K & TARGET_TYPE_CORE)
+    {
+        __get<K, fapi2attr::CoreAttributes_t, T, A>( i_pTarget, G_core_attributes, i_id, &o_value );  
+    }
+
+    if(K & TARGET_TYPE_EQ)
+    {
+        __get<K, fapi2attr::EQAttributes_t, T, A>( i_pTarget, G_eq_attributes, i_id, &o_value );  
+    }
+    
+    if(K & TARGET_TYPE_EX)
+    {                                           
+        __get<K, fapi2attr::EXAttributes_t, T, A>( i_pTarget, G_ex_attributes, i_id, &o_value );                     
+    }        
+
+    return FAPI2_RC_SUCCESS;    
+}
+
+
+//******************************************************************************
+// Get Override int8_t 
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _getOverride(const AttributeId i_id,
+                        const Target<K> * const i_pTarget,
+                        int8_t& o_value)
+{
+    static_assert(std::is_same<T, int8_t>::value, "Attribute type mismatch");
+
+    return FAPI2_RC_SUCCESS;
+}
+
+
+//******************************************************************************
+// Get Override int32_t 
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _getOverride(const AttributeId i_id,
+                        const Target<K> * const i_pTarget,
+                        int32_t& o_value)
+{
+    static_assert(std::is_same<T, int32_t>::value, "Attribute type mismatch");
+
+    return FAPI2_RC_SUCCESS;
+}
+
+
+//******************************************************************************
+// Get Override int64_t 
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _getOverride(const AttributeId i_id,
+                        const Target<K> * const i_pTarget,
+                        int64_t& o_value)
+{
+    static_assert(std::is_same<T, int64_t>::value, "Attribute type mismatch");
+    
+    return FAPI2_RC_SUCCESS;
+}
+
+
+//******************************************************************************
+// Get int8_t array
+//******************************************************************************
+template<TargetType K>
+ReturnCode _getAttributeArraySignedShort(const AttributeId i_id,
+                                         const Target<K> * const i_pTarget,
+                                         int8_t * o_pValues)
+{
+    return FAPI2_RC_SUCCESS;
+}
+
+
+//******************************************************************************
+// Set int8_t array
+//******************************************************************************
+template<TargetType K>
+ReturnCode _setAttributeArraySignedShort(const AttributeId i_id,
+                                         const Target<K> * const i_pTarget,
+                                         int8_t * i_pValues)
+{
+    return FAPI2_RC_SUCCESS;
+}
+
+
+//******************************************************************************
+// Get int32_t array
+//******************************************************************************
+template<TargetType K>
+ReturnCode _getAttributeArraySignedWord(const AttributeId i_id,
+                                        const Target<K> * const i_pTarget,
+                                        int32_t * o_pValues)
+{
+    return FAPI2_RC_SUCCESS;
+}
+
+
+//******************************************************************************
+// Set int32_t array
+//******************************************************************************
+template<TargetType K>
+ReturnCode _setAttributeArraySignedWord(const AttributeId i_id,
+                                        const Target<K> * const i_pTarget,
+                                        int32_t * i_pValues)
+{
+    return FAPI2_RC_SUCCESS;
+}
+
+
+//******************************************************************************
+// Get int64_t array
+//******************************************************************************
+template<TargetType K>
+ReturnCode _getAttributeArraySignedDoubleWord(const AttributeId i_id,
+                                              const Target<K> * const i_pTarget,
+                                              int64_t * o_pValues)
+{
+    return FAPI2_RC_SUCCESS;
+}
+
+//******************************************************************************
+// Set int64_t array
+//******************************************************************************
+template<TargetType K>
+ReturnCode _setAttributeArraySignedDoubleWord(const AttributeId i_id,
+                                              const Target<K> * const i_pTarget,
+                                              int64_t * i_pValues)
+{
+    return FAPI2_RC_SUCCESS;
+}
+
+//******************************************************************************
+// Get Override int8_t array
+//******************************************************************************
+template<TargetType K>
+ReturnCode _getAttributeOverrideArraySignedShort(const AttributeId i_id,
+                                                 const Target<K> * const i_pTarget,
+                                                 int8_t * o_pValues)
+{
+    return FAPI2_RC_SUCCESS;
+}
+
+
+//******************************************************************************
+// Get Override int32_t array
+//******************************************************************************
+template<TargetType K>
+ReturnCode _getAttributeOverrideArraySignedWord(const AttributeId i_id,
+                                                const Target<K> * const i_pTarget,
+                                                int32_t * o_pValues)
+{
+    return FAPI2_RC_SUCCESS;
+}
+
+
+//******************************************************************************
+// Get Override int64_t array
+//******************************************************************************
+template<TargetType K>
+ReturnCode _getAttributeOverrideArraySignedDoubleWord(const AttributeId i_id,
+                                                      const Target<K> * const i_pTarget,
+                                                      int64_t * o_pValues)
+{
+    return FAPI2_RC_SUCCESS;
+}
+
+
+//******************************************************************************
+// Set int8_t 
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _set(const AttributeId i_id,
+                const Target<K> * const i_pTarget,
+                int8_t& i_value)
+{
+    static_assert(std::is_same<T, int8_t>::value, "Attribute type mismatch"); // May need to remove
+
+    if(K & TARGET_TYPE_PROC_CHIP)
+    {
+        __set<K, fapi2attr::CoreAttributes_t, T, A>( *i_pTarget, G_proc_chip_attributes, i_value );  
+    }
+
+    if(K & TARGET_TYPE_PERV)
+    {
+        __set<K, fapi2attr::PervAttributes_t, T, A>( *i_pTarget, G_perv_attributes, i_value );  
+    }
+
+    if(K & TARGET_TYPE_CORE)
+    {
+        __set<K, fapi2attr::CoreAttributes_t, T, A>( *i_pTarget, G_core_attributes, i_value );  
+    }
+
+    if(K & TARGET_TYPE_EQ)
+    {
+        __set<K, fapi2attr::EQAttributes_t, T, A>( *i_pTarget, G_eq_attributes, i_value );  
+    }
+    
+    if(K & TARGET_TYPE_EX)
+    {                                           
+        __set<K, fapi2attr::EXAttributes_t, T, A>( *i_pTarget, G_ex_attributes, i_value );                         
+    }
+    
+    return FAPI2_RC_SUCCESS;
+}
+
+
+//******************************************************************************
+// Set int32_t 
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _set(const AttributeId i_id,
+                const Target<K> * const i_pTarget,
+                int32_t& i_value)
+{
+    static_assert(std::is_same<T, int32_t>::value, "Attribute type mismatch"); // May need to remove
+
+    if(K & TARGET_TYPE_PROC_CHIP)
+    {
+        __set<K, fapi2attr::CoreAttributes_t, T, A>( *i_pTarget, G_proc_chip_attributes, i_value );  
+    }
+
+    if(K & TARGET_TYPE_PERV)
+    {
+        __set<K, fapi2attr::PervAttributes_t, T, A>( *i_pTarget, G_perv_attributes, i_value );  
+    }
+
+    if(K & TARGET_TYPE_CORE)
+    {
+        __set<K, fapi2attr::CoreAttributes_t, T, A>( *i_pTarget, G_core_attributes, i_value );  
+    }
+
+    if(K & TARGET_TYPE_EQ)
+    {
+        __set<K, fapi2attr::EQAttributes_t, T, A>( *i_pTarget, G_eq_attributes, i_value );  
+    }
+    
+    if(K & TARGET_TYPE_EX)
+    {                                           
+        __set<K, fapi2attr::EXAttributes_t, T, A>( *i_pTarget, G_ex_attributes, i_value );                         
+    }
+    
+    return FAPI2_RC_SUCCESS;
+}
+
+
+//******************************************************************************
+// Set int64_t 
+//******************************************************************************
+template<typename T, TargetType K, AttributeId A>
+ReturnCode _set(const AttributeId i_id,
+                const Target<K> * const i_pTarget,
+                const int64_t & i_value)
+{
+    static_assert(std::is_same<T, int64_t>::value, "Attribute type mismatch"); // May need to remove
+
+    if(K & TARGET_TYPE_PROC_CHIP)
+    {
+        __set<K, fapi2attr::CoreAttributes_t, T, A>( *i_pTarget, G_proc_chip_attributes, i_value );  
+    }
+
+    if(K & TARGET_TYPE_PERV)
+    {
+        __set<K, fapi2attr::PervAttributes_t, T, A>( *i_pTarget, G_perv_attributes, i_value );  
+    }
+
+    if(K & TARGET_TYPE_CORE)
+    {
+        __set<K, fapi2attr::CoreAttributes_t, T, A>( *i_pTarget, G_core_attributes, i_value );  
+    }
+
+    if(K & TARGET_TYPE_EQ)
+    {
+        __set<K, fapi2attr::EQAttributes_t, T, A>( *i_pTarget, G_eq_attributes, i_value );  
+    }
+    
+    if(K & TARGET_TYPE_EX)
+    {                                           
+        __set<K, fapi2attr::EXAttributes_t, T, A>( *i_pTarget, G_ex_attributes, i_value );                         
+    }
+    
+    return FAPI2_RC_SUCCESS;
+}
+
+
+} // namespace fapi2
+#endif // FAPIPLATATTRIBUTESERVICE_H_