Update new PPE HW code

Change-Id: I8e0f107fc08c857b00102fa67f35516a04ee6c78
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20731
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Tested-by: William A. Bryan <wilbryan@us.ibm.com>

3 files changed, 21 insertions, 19 deletions

diff --git a/src/ppe/pk/ppe42/ppe42_scom.c b/src/ppe/pk/ppe42/ppe42_scom.c
index 20da4df..220712c 100755
--- a/src/ppe/pk/ppe42/ppe42_scom.c
+++ b/src/ppe/pk/ppe42/ppe42_scom.c
@@ -48,11 +48,11 @@
 #include "ppe42_msr.h"
 
 
-uint32_t putscom_abs(const uint32_t i_address, uint64_t *i_data)
+uint32_t putscom_abs(const uint32_t i_address, uint64_t i_data)
 {
 
     // Perform the Store Virtual Double instruction
-    PPE_STVD(i_address, &i_data);
+    PPE_STVD(i_address, i_data);
 
     // Get the MSR[SIBRC] as the return code   
     uint32_t rc = mfmsr();
@@ -61,11 +61,11 @@ uint32_t putscom_abs(const uint32_t i_address, uint64_t *i_data)
     
 }
 
-uint32_t _putscom( uint32_t i_chiplet_id, uint32_t i_address, uint64_t *i_data)
+uint32_t _putscom( uint32_t i_chiplet_id, uint32_t i_address, uint64_t i_data)
 {
 
     // Perform the Store Virtual Double Index instruction
-    PPE_STVDX(i_chiplet_id, i_address, &i_data);
+    PPE_STVDX(i_chiplet_id, i_address, i_data);
 
     // Get the MSR[SIBRC] as the return code   
     uint32_t rc = mfmsr();
@@ -78,7 +78,7 @@ uint32_t getscom_abs( const uint32_t i_address, uint64_t *o_data)
 {
     
     // Perform the Load Virtual Double instruction
-    PPE_LVD(i_address, &o_data);
+    PPE_LVD(i_address, o_data);
 
     // Get the MSR[SIBRC] as the return code   
     uint32_t rc = mfmsr();
@@ -91,7 +91,7 @@ uint32_t _getscom( const uint32_t i_chiplet_id, const uint32_t i_address, uint64
 {
     
     // Perform the Load Virtual Double Index instruction
-    PPE_LVDX(i_chiplet_id, i_address, &o_data);
+    PPE_LVDX(i_chiplet_id, i_address, o_data);
 
     // Get the MSR[SIBRC] as the return code   
     uint32_t rc = mfmsr();
diff --git a/src/ppe/pk/ppe42/ppe42_scom.h b/src/ppe/pk/ppe42/ppe42_scom.h
index 42bc87a..7368594 100755
--- a/src/ppe/pk/ppe42/ppe42_scom.h
+++ b/src/ppe/pk/ppe42/ppe42_scom.h
@@ -59,9 +59,9 @@ extern "C" {
 asm volatile \
     ( \
     "lvd %[data], 0(%[address]) \n" \
-    :  [data]"=&r"(*_m_data) \
-    :  "[data]"(*_m_data), \
-       [address]"r"(_m_address) \
+    :  [data]"=&r"(_m_data) \
+    :  "[data]"(_m_data), \
+       [address]"b"(_m_address) \
     );
 
 
@@ -70,9 +70,9 @@ asm volatile \
 asm volatile \
     ( \
         "stvd %[data], 0(%[address]) \n" \
-        : [data]"=&r"(*_m_data) \
-        : "[data]"(*_m_data), \
-          [address]"r"(_m_address) \
+        : [data]"=&r"(_m_data) \
+        : "[data]"(_m_data), \
+          [address]"b"(_m_address) \
         : "memory" \
      );
 
@@ -83,7 +83,7 @@ asm volatile \
     "lvdx %[data], %[base], %[offset] \n" \
     :  [data]"=&r"(*_m_data) \
     :  "[data]"(*_m_data), \
-       [base]"r"(_m_base), \
+       [base]"b"(_m_base), \
        [offset]"r"(_m_offset) \
     );
 
@@ -93,9 +93,9 @@ asm volatile \
 asm volatile \
     ( \
         "stvdx %[data], %[base], %[offset] \n" \
-        : [data]"=&r"(*_m_data) \
-        : "[data]"(*_m_data), \
-          [base]"r"(_m_base), \
+        : [data]"=&r"(_m_data) \
+        : "[data]"(_m_data), \
+          [base]"b"(_m_base), \
           [offset]"r"(_m_offset) \
         : "memory" \
      );
@@ -114,7 +114,7 @@ asm volatile \
 ///                          to optimize the underlying hardware execution
 ///
 /// @retval     On PPE42 platform, unmasked errors will take machine check interrupts
-uint32_t putscom_abs(const uint32_t i_address, uint64_t *i_data);
+uint32_t putscom_abs(const uint32_t i_address, uint64_t i_data);
 
 /// @brief getscom with absolute address
 /// @param [in]  i_address   Fully formed SCOM address
@@ -131,7 +131,7 @@ uint32_t getscom_abs( const uint32_t i_address, uint64_t *o_data);
 ///                         to optimize the underlying hardware execution
 ///
 /// @retval     On PPE42 platform, unmasked errors will take machine check interrupts
-uint32_t _putscom( const uint32_t i_chiplet, const uint32_t i_address, uint64_t *i_data);
+uint32_t _putscom( const uint32_t i_chiplet, const uint32_t i_address, uint64_t i_data);
 
 
 /// @brief Implementation of PPE getscom functionality
@@ -142,7 +142,7 @@ uint32_t _putscom( const uint32_t i_chiplet, const uint32_t i_address, uint64_t
 /// @retval     On PPE42 platform, unmasked errors will take machine check interrupts
 uint32_t _getscom( uint32_t i_chiplet, uint32_t i_address, uint64_t *o_data);
 
-extern inline uint32_t putscom(const uint32_t i_chiplet, const uint32_t i_address, uint64_t *i_data)
+extern inline uint32_t putscom(const uint32_t i_chiplet, const uint32_t i_address, uint64_t i_data)
 {
     return _putscom(i_chiplet, i_address, i_data);
 }
diff --git a/src/ppe/pk/std/std_irq_config.h b/src/ppe/pk/std/std_irq_config.h
index 5044b42..7d70d42 100644
--- a/src/ppe/pk/std/std_irq_config.h
+++ b/src/ppe/pk/std/std_irq_config.h
@@ -35,6 +35,8 @@
 /// configuration for a standard PPE.
 ///
 
+#include "pk_app_cfg.h"
+
 /// This constant is used to define the size of the table of interrupt handler
 /// structures as well as a limit for error checking. 
 #define EXTERNAL_IRQS 64