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| author | Chris Cain <cjcain@us.ibm.com> | 2017-08-16 12:14:00 -0500 |
|---|---|---|
| committer | Christopher J. Cain <cjcain@us.ibm.com> | 2017-08-16 15:01:22 -0400 |
| commit | 3b72373a3bfd5716902b48515f96faac683ef8dd (patch) | |
| tree | 25403fdc4f180fb9933e995fc4001a7e9f052045 /src/occ_gpe1 | |
| parent | 02cc125420d489610790e8d66890c383af0738a4 (diff) | |
| download | talos-occ-3b72373a3bfd5716902b48515f96faac683ef8dd.tar.gz talos-occ-3b72373a3bfd5716902b48515f96faac683ef8dd.zip | |
Delay DIMM collection for 60 seconds to prevent I2C bus contention with OPAL
Change-Id: Ia296230333cce7be3e2db385fc2293f6374ef104
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44693
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Diffstat (limited to 'src/occ_gpe1')
| -rwxr-xr-x | src/occ_gpe1/gpe1_dimm.h | 4 | ||||
| -rw-r--r-- | src/occ_gpe1/gpe1_dimm_read.c | 2 | ||||
| -rw-r--r-- | src/occ_gpe1/gpe1_dimm_reset.c | 2 |
3 files changed, 6 insertions, 2 deletions
diff --git a/src/occ_gpe1/gpe1_dimm.h b/src/occ_gpe1/gpe1_dimm.h index b151f87..59dbdac 100755 --- a/src/occ_gpe1/gpe1_dimm.h +++ b/src/occ_gpe1/gpe1_dimm.h @@ -51,6 +51,10 @@ #define PEEK_ERROR_MASK 0x00000000FC000000 #define PEEK_MORE_DATA 0x0000000002000000 +// 0-15: Bit Rate Divisor - 0x0049 gives approx 391kHz (and allows margin for clock variation) +// 16-21: Port Number (0-5) +// 22-26: reserved (0s) +#define I2C_MODE_REG_DIVISOR 0x0049000000000000 void dimm_set_ffdc(GpeErrorStruct *o_error, uint32_t i_addr, uint32_t i_rc, uint64_t i_ffdc); diff --git a/src/occ_gpe1/gpe1_dimm_read.c b/src/occ_gpe1/gpe1_dimm_read.c index 133ad9f..90f4a4b 100644 --- a/src/occ_gpe1/gpe1_dimm_read.c +++ b/src/occ_gpe1/gpe1_dimm_read.c @@ -268,7 +268,7 @@ void dimm_write_mode(ipc_msg_t* cmd, void* arg) // 0-15: Bit Rate Divisor - 0x0049 gives approx 391kHz (and allows margin for clock variation) // 16-21: Port Number (0-5) // 22-26: reserved (0s) - regValue = 0x0049000000000000; + regValue = I2C_MODE_REG_DIVISOR; if ((args->i2cPort > 0) && (args->i2cPort < 6)) { regValue |= ((uint64_t)args->i2cPort << 42); diff --git a/src/occ_gpe1/gpe1_dimm_reset.c b/src/occ_gpe1/gpe1_dimm_reset.c index 161bd43..16cf8da 100644 --- a/src/occ_gpe1/gpe1_dimm_reset.c +++ b/src/occ_gpe1/gpe1_dimm_reset.c @@ -126,7 +126,7 @@ void dimm_reset_slave(ipc_msg_t* cmd, void* arg) // 0-15: Bit Rate Divisor - 0x0049 gives approx 391kHz (and allows margin for clock variation) // 16-21: Port Number (0-5) // 22-26: reserved (0s) - regValue = 0x0049000000000000; + regValue = I2C_MODE_REG_DIVISOR; if ((args->i2cPort > 0) && (args->i2cPort < 6)) { regValue |= ((uint64_t)args->i2cPort << 42); |
