Amended 24x7 code- 7/11/2017 config,500us tic

Change-Id: I6a016fc0158f4210f0e944dfcf770f3b87837c2e
changes to accomodate occ tic duration
change from 250us to 500us
assumes runtime of 50us per tic
also added ALINK3 mask in header to reflect UAV change
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43130
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>

3 files changed, 1558 insertions, 32 deletions

diff --git a/src/occ_gpe1/gpe1_24x7.c b/src/occ_gpe1/gpe1_24x7.c
index eb9d25f..42d6b28 100644
--- a/src/occ_gpe1/gpe1_24x7.c
+++ b/src/occ_gpe1/gpe1_24x7.c
@@ -24,12 +24,15 @@
 /* IBM_PROLOG_END_TAG                                                     */
 
 #include "pk.h"
+#include "pk_app_cfg.h"
 #include "ppe42_scom.h"
 #include "ipc_api.h"
 #include "ipc_async_cmd.h"
 #include "gpe_util.h"
 #include "gpe_24x7_structs.h"
-
+#include "gpe_pba_cntl.h"
+#include "gpe1_24x7.h"
+#include "string.h"
 /*
  * Function Specifications:
  *
@@ -44,58 +47,320 @@
  *
  * End Function Specification
  */
-
+uint8_t G_test_array_24x7[100];
+uint64_t* test_addr = (uint64_t*) (TEST_ADDR | PBA_ENABLE);
 void gpe_24x7(ipc_msg_t* cmd, void* arg)
 {
     // Note: arg was set to 0 in ipc func table (ipc_func_tables.c), so don't use it.
     // the ipc arguments passed through the ipc_msg_t structure, has a pointer
     // to the gpe_24x7_args_t struct.
-
+    
     int      rc = 0;
     ipc_async_cmd_t *async_cmd = (ipc_async_cmd_t*)cmd;
     gpe_24x7_args_t *args = (gpe_24x7_args_t*)async_cmd->cmd_data;
 
-    uint8_t ticks = args->numTicksPassed; // number of 250us ticks since last call
+    uint8_t ticks = args->numTicksPassed; // number of 500us ticks since last call
     static uint8_t  L_current_state = 1;  // 24x7 collection "state" to execute when called
-
+    //
+    static uint8_t  L_DELAY_1 = 0;  
+    static uint8_t  L_DELAY_2 = 0;  
+    static uint8_t  L_DELAY_3 = 0;  
+    static uint8_t  L_DELAY_4 = 0;  
+    static uint8_t  L_DELAY_5 = 0;  
+    static uint8_t  L_DELAY_6 = 0;  
+    static uint8_t  L_DELAY_7 = 0;  
+    static uint8_t  L_CUR_DELAY = 0;  
+    static uint64_t  L_cur_speed = 0;  
+    //
+    static bool L_configure = false;
+    static bool L_DONT_RUN = false;
+    static bool L_INIT = false;
+    static bool L_PART_INIT = false;
+    //
+    //control block memory area.
+    //
+    static volatile uint64_t* L_status = (uint64_t*) (CNTL_STATUS_OFFSET | PBA_ENABLE);
+    static volatile uint64_t* L_cmd = (uint64_t*) (CNTL_CMD_OFFSET | PBA_ENABLE);
+    static volatile uint64_t* L_speed = (uint64_t*) (CNTL_SPEED_OFFSET | PBA_ENABLE);
+    static volatile uint64_t* L_uav = (uint64_t*) (CNTL_UAV_OFFSET | PBA_ENABLE);
+    static volatile uint64_t* L_mode = (uint64_t*) (CNTL_MODE_OFFSET | PBA_ENABLE);
+    //
+    static volatile uint64_t* L_tics_exceded = (uint64_t*) (DBG_TICS_OFFSET | PBA_ENABLE);
     args->error.error = 0; // default success
     args->error.ffdc = 0;
-
+       
+    //PBA Slave setup. Do this each time you enter this loop to be safe.
+    gpe_pba_reset();
     if(ticks == 0)  // First time 24x7 called since OCC started?
     {
-        PK_TRACE("gpe_24x7: First call since OCC started");
+//1. read and update the control block 
+        PK_TRACE("gpe_24x7: First call since OCC started. ticks = 0");
+        //set configure to true
+        L_configure = true;
+        //initialize posting area
+        initialize_postings();
+
+        putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+        
+        //set status as initializing
+        *L_status = CNTL_STATUS_INIT;
+        //initialize cmd to NOP
+        *L_cmd = CNTL_CMD_NOP;
+        //UAV - currently filled with system dependent static value. Need to be replaced with value from reading HDAT.
+        if (*L_uav == 0)
+            *L_uav = CNTL_UAV_TEMP;
+        //get speed of collection and set delays accordingly.
+        L_cur_speed = *L_speed;
+        set_speed(&L_cur_speed,&L_CUR_DELAY,L_status);
+        //check if mode is set to monitor
+        //support for debug modes (flexible IMA) not present currently.
+        if(*L_mode != CNTL_MODE_MONITOR)
+            *L_status = CNTL_STATUS_ERR2;
+        //set Dont run if the speed and mode info is not set to legal values.
+        if( (*L_status == CNTL_STATUS_ERR1)||(*L_status == CNTL_STATUS_ERR2) )
+            L_DONT_RUN = true;
     }
-    else if(ticks > 1)  // longer than 250us since last call?
+    else if(ticks > 1)  // longer than 500us since last call?
     {
-       // It has been ticks*250us since last call
+       // It has been ticks*500us since last call
         PK_TRACE("gpe_24x7: It has been 0x%02X ticks since last call", ticks);
+        putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+        *L_tics_exceded ++;
     }
-
-    switch(L_current_state)
+//2. get any new command
+    if (*L_cmd != CNTL_CMD_NOP)
     {
-        case 1:
-        case 2:
-        case 3:
-        case 4:
-        case 5:
-        case 6:
-        case 7:
-        case 8:
-        case 9:
-        case 10:
-        case 11:
-        case 12:
-        case 13:
-        case 14:
-        case 15:
-        case 16:
-            break;
+       putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+       switch(*L_cmd)
+       {
+           case CNTL_CMD_PAUSE:
+               L_DONT_RUN = true;
+               *L_status = CNTL_STATUS_PAUSE;
+               *L_cmd = CNTL_CMD_NOP;
+               break;
+           case CNTL_CMD_RESUME:
+               L_DONT_RUN = false;
+               *L_status = CNTL_STATUS_RUN;
+               *L_cmd = CNTL_CMD_NOP;
+               break;
+           case CNTL_CMD_CLEAR:
+               L_DONT_RUN = false;
+               L_INIT = true;
+               *L_cmd = CNTL_CMD_NOP;
+               break;
+       }
+    }
+//3.get any new speed setting
+    if (*L_speed != L_cur_speed)
+        L_INIT = true;
+//4.check for any system config changes via uav
+    if (*L_uav != G_CUR_UAV)
+    {
+        L_INIT = true;
+        L_PART_INIT = true;
+    }
+    //initialize postings if required from new cmd or change of speed or UAV change.
+    if (L_INIT)
+    {
+        putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+        *L_status = CNTL_STATUS_INIT;
+        //need not initialize postings for UAV change.
+        if (L_PART_INIT)
+            L_PART_INIT = false;
+        else
+            initialize_postings();
 
-        default:
-            PK_TRACE("gpe_24x7: Invalid collection state: 0x%02X", L_current_state);
-            break;
+        L_configure = true;
+        L_cur_speed = *L_speed;
+        G_CUR_UAV = *L_uav;
+        set_speed(&L_cur_speed,&L_CUR_DELAY,L_status);
+        //set the state to 1 if reconfig is required. config scoms are split across multiple states starting from 1.
+        L_current_state = 1;
+        L_INIT = false;
     }
+//5. Based on the current entry state number, appropriate group posting is done.
+//G1(1,5,9,13), G2(2,6,10,14), G3(3,7,11,15) in G4(4), G5(8), G6(12), G7(16).
+//during first time entry or a re-init is trigered, the current run is used for pmu configuration.
+//configuration will continue across multiple re-entry slots till all configuration scoms are done.
+//scoms are generally kept at 8 per slot, to prevent from exceeding 25us runtime buget.
+    if (L_DONT_RUN == false)
+    {
+        switch(L_current_state)
+        {
+            case 1:
+                if(L_configure)
+                {
+                    configure_pmu(L_current_state, L_cur_speed);
+                }
+                else
+                {
+                    if(L_DELAY_1 == 0)
+                    {
+                        post_pmu_events(G1);
+                        L_DELAY_1 = L_CUR_DELAY;
+                    }
+                    else
+                        L_DELAY_1--;
 
+                    if(L_DELAY_2 == 0)
+                    {
+                        post_pmu_events(G2);
+                        L_DELAY_2 = L_CUR_DELAY;
+                    }
+                    else
+                        L_DELAY_2--;
+                }
+                break;
+            case 2:
+                if(L_configure)
+                {
+                    configure_pmu(L_current_state, L_cur_speed);
+                }
+                else
+                {
+                    if(L_DELAY_3 == 0)
+                    {
+                        post_pmu_events(G3);
+                        L_DELAY_3 = L_CUR_DELAY;
+                    }
+                    else
+                        L_DELAY_3--;
+                
+      		    if(L_DELAY_4 == 0)
+      		    {
+      		        post_pmu_events(G4);
+//for groups 4,5,6,7 8ms is the fastest possible collection speed.
+      		        L_DELAY_4 = L_CUR_DELAY/8;
+      		    }
+      		    else
+      		        L_DELAY_4--;
+                }
+                break;
+            case 3:
+                if(L_configure)
+                {
+                    configure_pmu(L_current_state, L_cur_speed);
+                }
+                else
+                {
+    		    if(L_DELAY_1 == 0)
+    		    {
+    		        post_pmu_events(G1);
+    		        L_DELAY_1 = L_CUR_DELAY;
+    		    }
+    		    else
+    		        L_DELAY_1--;
+                
+                    if(L_DELAY_2 == 0)
+                    {
+                        post_pmu_events(G2);
+                        L_DELAY_2 = L_CUR_DELAY;
+                    }
+                    else
+                        L_DELAY_2--;
+                }
+                break;
+            case 4:
+                if(L_configure)
+                {
+                    configure_pmu(L_current_state, L_cur_speed);
+                }
+                else
+                {
+                    if(L_DELAY_3 == 0)
+                    {
+                        post_pmu_events(G3);
+                        L_DELAY_3 = L_CUR_DELAY;
+                    }
+                    else
+                        L_DELAY_3--;
+                
+                    if(L_DELAY_5 == 0)
+                    {
+                        post_pmu_events(G5);
+//for groups 4,5,6,7 8ms is the fastest possible collection speed.
+                        L_DELAY_5 = L_CUR_DELAY/8;
+                    }
+                    else
+                        L_DELAY_5--;
+                }
+                break;
+            case 5:
+                if(L_DELAY_1 == 0)
+                {
+                    post_pmu_events(G1);
+                    L_DELAY_1 = L_CUR_DELAY;
+                }
+                else
+                    L_DELAY_1--;
+            
+                if(L_DELAY_2 == 0)
+                {
+                    post_pmu_events(G2);
+                    L_DELAY_2 = L_CUR_DELAY;
+                }
+                else
+                    L_DELAY_2--;
+                break;
+            case 6:
+                if(L_DELAY_3 == 0)
+                {
+                    post_pmu_events(G3);
+                    L_DELAY_3 = L_CUR_DELAY;
+                }
+                else
+                    L_DELAY_3--;
+            
+                if(L_DELAY_6 == 0)
+                {
+                    post_pmu_events(G6);
+//for groups 4,5,6,7 8ms is the fastest possible collection speed.
+                    L_DELAY_6 = L_CUR_DELAY/8;
+                }
+                else
+                    L_DELAY_6--;
+                break;
+            case 7:
+                if(L_DELAY_1 == 0)
+                {
+                    post_pmu_events(G1);
+                    L_DELAY_1 = L_CUR_DELAY;
+                }
+                else
+                    L_DELAY_1--;
+            
+                if(L_DELAY_2 == 0)
+                {
+                    post_pmu_events(G2);
+                    L_DELAY_2 = L_CUR_DELAY;
+                }
+                else
+                    L_DELAY_2--;
+                break;
+            case 8:
+                if(L_DELAY_3 == 0)
+                {
+                    post_pmu_events(G3);
+                    L_DELAY_3 = L_CUR_DELAY;
+                }
+                else
+                    L_DELAY_3--;
+            
+                if(L_DELAY_7 == 0)
+                {
+                    post_pmu_events(G7);
+//for groups 4,5,6,7 8ms is the fastest possible collection speed.
+                    L_DELAY_7 = L_CUR_DELAY/8;
+                }
+                else
+                    L_DELAY_7--;
+                break;
+    
+            default:
+                PK_TRACE("gpe_24x7: Invalid collection state: 0x%02X", L_current_state);
+                break;
+        }
+    }
     // Setup state to run on next call
     if(L_current_state == MAX_24x7_STATES)
         L_current_state = 1;
@@ -111,3 +376,758 @@ void gpe_24x7(ipc_msg_t* cmd, void* arg)
         pk_halt();
     }
 }
+
+void configure_pmu(uint8_t state, uint64_t speed)
+{//write the configuration SCOMs for all pmus.
+    int i,start = (state - 1) * 16,end = state * 16;
+    static volatile uint64_t* L_conf_last = (uint64_t*) (DBG_CONF_OFFSET | PBA_ENABLE);
+    putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+    
+    if(end > TOTAL_CONFIGS)
+        end = TOTAL_CONFIGS;
+    for(i = start; i < end; i++)
+    {
+//check the availability of unit before writing the configurations to the config scoms.
+//use the unit wise masks to acertain availability of a unit.
+        if( (i==4) && !(G_CUR_UAV & MASK_MCS4) )
+            continue;
+        else if( (i==5) && !(G_CUR_UAV & MASK_MCS5) )
+            continue;
+        else if( (i==6) && !(G_CUR_UAV & MASK_MCS6) )
+            continue;
+        else if( (i==7) && !(G_CUR_UAV & MASK_MCS7) )
+            continue;
+        else if( ((i==8)||(i==9)||(i==10)||(i==11)) && (!(G_CUR_UAV & MASK_MCS4)||!(G_CUR_UAV & MASK_MCS5)) )
+            continue;
+        else if( ((i==12)||(i==13)||(i==14)||(i==15)) && (!(G_CUR_UAV & MASK_MCS6)||!(G_CUR_UAV & MASK_MCS7)) )
+            continue;
+        else if( (i==16) && !(G_CUR_UAV & MASK_MCS0) )
+            continue;
+        else if( (i==17) && !(G_CUR_UAV & MASK_MCS1) )
+            continue;
+        else if( (i==18) && !(G_CUR_UAV & MASK_MCS2) )
+            continue;
+        else if( (i==19) && !(G_CUR_UAV & MASK_MCS3) )
+            continue;
+        else if( ((i==20)||(i==21)||(i==22)||(i==23)) && (!(G_CUR_UAV & MASK_MCS0)||!(G_CUR_UAV & MASK_MCS1)) )
+            continue;
+        else if( ((i==24)||(i==25)||(i==26)||(i==27)) && (!(G_CUR_UAV & MASK_MCS2)||!(G_CUR_UAV & MASK_MCS3)) ) 
+            continue;
+        else if( (i==28) && (!(G_CUR_UAV & MASK_XLNK0)||!(G_CUR_UAV & MASK_XLNK1)||!(G_CUR_UAV & MASK_XLNK2)) )
+            continue;
+        else if( ((i==29)||(i==30)||(i==31)||(i==32)) && !(G_CUR_UAV & MASK_NX) )
+            continue;
+        else if( (i==33) && !(G_CUR_UAV & MASK_NVLNK0) )
+            continue;
+        else if( (i==34) && !(G_CUR_UAV & MASK_NVLNK1) )
+            continue;
+        else if( (i==35) && !(G_CUR_UAV & MASK_NVLNK2) )
+            continue;
+        else if( (i==36) && !(G_CUR_UAV & MASK_NVLNK3) )
+            continue;
+        else if( (i==37) && !(G_CUR_UAV & MASK_NVLNK4) )
+            continue;
+        else if( (i==38) && !(G_CUR_UAV & MASK_NVLNK5) )
+            continue;
+        else if( ((i==39)||(i==40)) && (!(G_CUR_UAV & MASK_NVLNK5)||!(G_CUR_UAV & MASK_NVLNK4)||!(G_CUR_UAV & MASK_NVLNK3)||
+                             !(G_CUR_UAV & MASK_NVLNK2)||!(G_CUR_UAV & MASK_NVLNK1)||!(G_CUR_UAV & MASK_NVLNK0)) )
+            continue;
+        else if( (i==41) && !(G_CUR_UAV & MASK_PHB0) )
+            continue;
+        else if( (i==42) && !(G_CUR_UAV & MASK_PHB1) )
+            continue;
+        else if( (i==43) && !(G_CUR_UAV & MASK_PHB2) )
+            continue;
+        else if( (i==44) && !(G_CUR_UAV & MASK_PHB3) )
+            continue;
+        else if( (i==45) && !(G_CUR_UAV & MASK_PHB4) )
+            continue;
+        else if( (i==46) && !(G_CUR_UAV & MASK_PHB5) )
+            continue;
+        else if( (i==47) && (!(G_CUR_UAV & MASK_NVLNK1)||!(G_CUR_UAV & MASK_NVLNK0)) )
+            continue;
+        else if( (i==48) && (!(G_CUR_UAV & MASK_NVLNK3)||!(G_CUR_UAV & MASK_NVLNK2)) )
+            continue;
+        else if( (i==49) && (!(G_CUR_UAV & MASK_NVLNK5)||!(G_CUR_UAV & MASK_NVLNK4)) )
+            continue;
+        else if( ((i==50)||(i==51)||(i==52)||(i==53)) && !(G_CUR_UAV & MASK_CAPP0) )
+            continue;
+        else if( ((i==54)||(i==55)||(i==56)||(i==57)) && !(G_CUR_UAV & MASK_CAPP1) )
+            continue;
+        else
+        {
+            //Two sets of configurations. 
+            //1.for speeds till 8ms- 8 bit prescale
+            if((speed == CNTL_SPEED_1MS)||(speed == CNTL_SPEED_2MS)||(speed == CNTL_SPEED_4MS)||(speed == CNTL_SPEED_8MS))
+            {
+                putscom_abs(G_PMU_CONFIGS_8[i][0], G_PMU_CONFIGS_8[i][1]);
+                *L_conf_last = (uint64_t)i;            
+            }
+            //2.for all speeds above 8 ms till 2s - 16bit prescale
+            else
+            {
+                putscom_abs(G_PMU_CONFIGS_16[i][0], G_PMU_CONFIGS_16[i][1]);
+                *L_conf_last = (uint64_t)i;            
+            }
+        }
+    }
+}
+
+
+void post_pmu_events(int grp)
+{//read the scom pmulets. split/extract the counters.accumulate to main memory.
+    volatile uint64_t* post_addr;
+    static int L_phb_events =0;    
+    static volatile uint64_t* L_DBG_GRP = (uint64_t*) (DBG_GRP_OFFSET | PBA_ENABLE);
+    static volatile uint64_t* L_DBG_UNIT = (uint64_t*) (DBG_UNIT_OFFSET | PBA_ENABLE);
+    static uint64_t L_PHB_pmulets[24];
+    static uint64_t L_MBA_pmulets[16];
+    uint64_t temp;
+//union to split a pmulet containg 4 counters into its constituents.
+    union u1
+    { 
+        struct event
+        {
+            uint16_t e[4];
+        } ev;
+        uint64_t pmulet;
+    } u3;
+     
+    int i=0,j=0,phb_epoch=0;
+    uint64_t TOD;
+    post_addr = (uint64_t*) (POSTING_START | PBA_ENABLE);
+    putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+    //FIXME:restricting groups for test on witherspoon
+    //remove once done.
+    //int test_grp = G1;
+    //
+    switch(grp)
+    //switch(test_grp)
+    {
+        case G1://cnpm group - always written
+            post_addr = (uint64_t*) (POST_OFFSET_G1H | PBA_ENABLE);
+            *L_DBG_GRP = 1;
+            *L_DBG_UNIT = 1;
+            putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+            *post_addr = INC_UPD_COUNT;
+            post_addr++;
+            for(i=0; i<8; i++)
+            {
+                getscom_abs(G_PMULETS_1[i], &u3.pmulet);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+            }
+            post_addr = (uint64_t*) (POST_OFFSET_G1T | PBA_ENABLE);
+            *post_addr = INC_UPD_COUNT;
+            break;
+        case G2://XLINKS and NX. Read scoms based on availability.
+            *L_DBG_GRP = 2;
+            post_addr = (uint64_t*) (POST_OFFSET_G2H | PBA_ENABLE);
+            putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+            *post_addr = INC_UPD_COUNT;
+            post_addr++;
+            if (G_CUR_UAV & MASK_XLNK1)
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 1;
+                post_addr = (uint64_t*) (POST_OFFSET_G2_1 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                getscom_abs(G_PMULETS_2[0], &u3.pmulet);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+                getscom_abs(G_PMULETS_2[1], &u3.pmulet);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+            }
+            if (G_CUR_UAV & MASK_XLNK0)
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 2;
+                post_addr = (uint64_t*) (POST_OFFSET_G2_2 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                getscom_abs(G_PMULETS_2[2], &u3.pmulet);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+                getscom_abs(G_PMULETS_2[3], &u3.pmulet);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+            }
+            if (G_CUR_UAV & MASK_XLNK2)
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 3;
+                post_addr = (uint64_t*) (POST_OFFSET_G2_3 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                getscom_abs(G_PMULETS_2[4], &u3.pmulet);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+                getscom_abs(G_PMULETS_2[5], &u3.pmulet);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+            }
+            if (G_CUR_UAV & MASK_NX)
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 4;
+                post_addr = (uint64_t*) (POST_OFFSET_G2_4 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                getscom_abs(G_PMULETS_2[6], &u3.pmulet);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+                getscom_abs(G_PMULETS_2[7], &u3.pmulet);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+            }
+            post_addr = (uint64_t*) (POST_OFFSET_G2T | PBA_ENABLE);
+            *post_addr = INC_UPD_COUNT;
+            break;
+        case G3://NVLINKS -NTL,ATS,XTS
+            *L_DBG_GRP = 3;
+            post_addr = (uint64_t*) (POST_OFFSET_G3H | PBA_ENABLE);
+            putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+            *post_addr = INC_UPD_COUNT;
+            post_addr++;
+            if (G_CUR_UAV & MASK_NVLNK0)
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 1;
+                getscom_abs(G_PMULETS_3[0], &u3.pmulet);
+                post_addr = (uint64_t*) (POST_OFFSET_G3_1 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+            }
+            if (G_CUR_UAV & MASK_NVLNK1)
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 2;
+                getscom_abs(G_PMULETS_3[1], &u3.pmulet);
+                post_addr = (uint64_t*) (POST_OFFSET_G3_2 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+            }
+            if (G_CUR_UAV & MASK_NVLNK2)
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 3;
+                getscom_abs(G_PMULETS_3[2], &u3.pmulet);
+                post_addr = (uint64_t*) (POST_OFFSET_G3_3 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+            }
+            if (G_CUR_UAV & MASK_NVLNK3)
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 4;
+                getscom_abs(G_PMULETS_3[3], &u3.pmulet);
+                post_addr = (uint64_t*) (POST_OFFSET_G3_4 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+            }
+            if (G_CUR_UAV & MASK_NVLNK4)
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 5;
+                getscom_abs(G_PMULETS_3[4], &u3.pmulet);
+                post_addr = (uint64_t*) (POST_OFFSET_G3_5 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+            }
+            if (G_CUR_UAV & MASK_NVLNK5)
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 6;
+                getscom_abs(G_PMULETS_3[5], &u3.pmulet);
+                post_addr = (uint64_t*) (POST_OFFSET_G3_6 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+            }
+            if ((G_CUR_UAV & MASK_NVLNK0)||(G_CUR_UAV & MASK_NVLNK1)||(G_CUR_UAV & MASK_NVLNK2)||
+                (G_CUR_UAV & MASK_NVLNK3)||(G_CUR_UAV & MASK_NVLNK4)||(G_CUR_UAV & MASK_NVLNK5) )
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 7;
+                getscom_abs(G_PMULETS_3[6], &u3.pmulet);
+                post_addr = (uint64_t*) (POST_OFFSET_G3_7 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+                *L_DBG_UNIT = 8;
+                getscom_abs(G_PMULETS_3[7], &u3.pmulet);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+            }
+            post_addr = (uint64_t*) (POST_OFFSET_G3T | PBA_ENABLE);
+            *post_addr = INC_UPD_COUNT;
+            break;
+        case G4:
+//PHB events are present on separate 48-bit SCOM registers. They dont clear on read.
+//But wrap around. After each read, the value is subtracted from the prvious value to 
+//get current increment which is then atomically added to the main memory.
+//Totally 24 scoms of the PHB are split across 3 epochs for the same group.
+// Only 8 scoms are read and updated to memory in an epoch to abide the 25us run time restriction.
+            *L_DBG_GRP = 4;
+            post_addr = (uint64_t*) (POST_OFFSET_G4H | PBA_ENABLE);
+            putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+            *post_addr = INC_UPD_COUNT;
+            post_addr++;
+            if(L_phb_events > 23)
+                L_phb_events = 0;  
+            phb_epoch = L_phb_events/8;
+            switch(phb_epoch)
+            {
+                case 0:
+                    if (G_CUR_UAV & MASK_PHB0)
+                    {
+                        putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                        *L_DBG_UNIT = 1;
+                        putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                        post_addr = (uint64_t*) (POST_OFFSET_G4a | PBA_ENABLE);
+                        for(i=0; i<4; i++)
+                        {
+                            getscom_abs(G_PMULETS_4a[i], &temp);
+                            L_PHB_pmulets[L_phb_events] = temp - L_PHB_pmulets[L_phb_events];
+                            *post_addr = L_PHB_pmulets[L_phb_events];
+                            post_addr++;
+                            L_phb_events++;
+                        }
+                    }
+                    else
+                        L_phb_events += 4;
+                    
+              
+                    if (G_CUR_UAV & MASK_PHB1)
+                    {
+                        putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                        *L_DBG_UNIT = 2;
+                        putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                        post_addr = (uint64_t*) (POST_OFFSET_G4b | PBA_ENABLE);
+                        for(i=0; i<4; i++)
+                        {
+                            getscom_abs(G_PMULETS_4b[i], &temp);
+                            L_PHB_pmulets[L_phb_events] = temp - L_PHB_pmulets[L_phb_events];
+                            *post_addr = L_PHB_pmulets[L_phb_events];
+                            post_addr++;
+                            L_phb_events++;
+                        }
+                    }
+                    else
+                        L_phb_events += 4;
+                    break;
+                 case 1:
+                    if (G_CUR_UAV & MASK_PHB2)
+                    {
+                        putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                        *L_DBG_UNIT = 3;
+                        putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                        post_addr = (uint64_t*) (POST_OFFSET_G4c | PBA_ENABLE);
+                        for(i=0; i<4; i++)
+                        {
+                            getscom_abs(G_PMULETS_4c[i], &temp);
+                            L_PHB_pmulets[L_phb_events] = temp - L_PHB_pmulets[L_phb_events];
+                            *post_addr = L_PHB_pmulets[L_phb_events];
+                            post_addr++;
+                            L_phb_events++;
+                        }
+                    }
+                    else
+                        L_phb_events += 4;
+                    if (G_CUR_UAV & MASK_PHB3)
+                    {
+                        putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                        *L_DBG_UNIT = 4;
+                        putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                        post_addr = (uint64_t*) (POST_OFFSET_G4d | PBA_ENABLE);
+                        for(i=0; i<4; i++)
+                        {
+                            getscom_abs(G_PMULETS_4d[i], &temp);
+                            L_PHB_pmulets[L_phb_events] = temp - L_PHB_pmulets[L_phb_events];
+                            *post_addr = L_PHB_pmulets[L_phb_events];
+                            post_addr++;
+                            L_phb_events++;
+                        }
+                    }
+                    else
+                        L_phb_events += 4;
+                    break; 
+                 case 2:
+                    if (G_CUR_UAV & MASK_PHB4)
+                    {
+                        putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                        *L_DBG_UNIT = 5;
+                        putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                        post_addr = (uint64_t*) (POST_OFFSET_G4e | PBA_ENABLE);
+                        for(i=0; i<4; i++)
+                        {
+                            getscom_abs(G_PMULETS_4e[i], &temp);
+                            L_PHB_pmulets[L_phb_events] = temp - L_PHB_pmulets[L_phb_events];
+                            *post_addr = L_PHB_pmulets[L_phb_events];
+                            post_addr++;
+                            L_phb_events++;
+                        }
+                    }
+                    else
+                        L_phb_events += 4;
+                    if (G_CUR_UAV & MASK_PHB5)
+                    {
+                        putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                        *L_DBG_UNIT = 6;
+                        putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                        post_addr = (uint64_t*) (POST_OFFSET_G4f | PBA_ENABLE);
+                        for(i=0; i<4; i++)
+                        {
+                            getscom_abs(G_PMULETS_4f[i], &temp);
+                            L_PHB_pmulets[L_phb_events] = temp - L_PHB_pmulets[L_phb_events];
+                            *post_addr = L_PHB_pmulets[L_phb_events];
+                            post_addr++;
+                            L_phb_events++;
+                        }
+                    }
+                    else
+                        L_phb_events += 4;
+                    break;  
+            }
+            post_addr = (uint64_t*) (POST_OFFSET_G4T | PBA_ENABLE);
+            *post_addr = INC_UPD_COUNT;
+            break;
+        case G5://MBAs - 8 fixed counters  for MBA0-3 that dont clear on read but wraparound on overflow.
+            *L_DBG_GRP = 5;
+            post_addr = (uint64_t*) (POST_OFFSET_G5H | PBA_ENABLE);
+            putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+            *post_addr = INC_UPD_COUNT;
+            post_addr++;
+            if (G_CUR_UAV & MASK_MBA0)
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 1;
+                post_addr = (uint64_t*) (POST_OFFSET_G5_1 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                getscom_abs(G_PMULETS_5[0], &temp);
+                L_MBA_pmulets[0] = temp - L_MBA_pmulets[0];
+                *post_addr = L_MBA_pmulets[0];
+                post_addr++;
+                getscom_abs(G_PMULETS_5[1], &temp);
+                L_MBA_pmulets[1] = temp - L_MBA_pmulets[1];
+                *post_addr = L_MBA_pmulets[1];
+            }
+            if (G_CUR_UAV & MASK_MBA1)
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 2;
+                post_addr = (uint64_t*) (POST_OFFSET_G5_2 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                getscom_abs(G_PMULETS_5[2], &temp);
+                L_MBA_pmulets[2] = temp - L_MBA_pmulets[2];
+                *post_addr = L_MBA_pmulets[2];
+                post_addr++;
+                getscom_abs(G_PMULETS_5[3], &temp);
+                L_MBA_pmulets[3] = temp - L_MBA_pmulets[3];
+                *post_addr = L_MBA_pmulets[3];
+            }
+            if (G_CUR_UAV & MASK_MBA2)
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 3;
+                post_addr = (uint64_t*) (POST_OFFSET_G5_3 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                getscom_abs(G_PMULETS_5[4], &temp);
+                L_MBA_pmulets[4] = temp - L_MBA_pmulets[4];
+                *post_addr = L_MBA_pmulets[4];
+                post_addr++;
+                getscom_abs(G_PMULETS_5[5], &temp);
+                L_MBA_pmulets[5] = temp - L_MBA_pmulets[5];
+                *post_addr = L_MBA_pmulets[5];
+            }
+            if (G_CUR_UAV & MASK_MBA3)
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 4;
+                post_addr = (uint64_t*) (POST_OFFSET_G5_4 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                getscom_abs(G_PMULETS_5[6], &temp);
+                L_MBA_pmulets[6] = temp - L_MBA_pmulets[6];
+                *post_addr = L_MBA_pmulets[6];
+                post_addr++;
+                getscom_abs(G_PMULETS_5[7], &temp);
+                L_MBA_pmulets[7] = temp - L_MBA_pmulets[7];
+                *post_addr = L_MBA_pmulets[7];
+            }
+            post_addr = (uint64_t*) (POST_OFFSET_G5T | PBA_ENABLE);
+            *post_addr = INC_UPD_COUNT;
+            break;
+        case G6://8 more fixed scoms for MBA4-7. no clear on read.wraparound.
+            *L_DBG_GRP = 6;
+            post_addr = (uint64_t*) (POST_OFFSET_G6H | PBA_ENABLE);
+            putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+            *post_addr = INC_UPD_COUNT;
+            post_addr++;
+            if (G_CUR_UAV & MASK_MBA4)
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 1;
+                post_addr = (uint64_t*) (POST_OFFSET_G6_1 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                getscom_abs(G_PMULETS_6[0], &temp);
+                L_MBA_pmulets[8] = temp - L_MBA_pmulets[8];
+                *post_addr = L_MBA_pmulets[8];
+                post_addr++;
+                getscom_abs(G_PMULETS_6[1], &temp);
+                L_MBA_pmulets[9] = temp - L_MBA_pmulets[9];
+                *post_addr = L_MBA_pmulets[9];
+            }
+            if (G_CUR_UAV & MASK_MBA5)
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 2;
+                post_addr = (uint64_t*) (POST_OFFSET_G6_2 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                getscom_abs(G_PMULETS_6[2], &temp);
+                L_MBA_pmulets[10] = temp - L_MBA_pmulets[10];
+                *post_addr = L_MBA_pmulets[10];
+                post_addr++;
+                getscom_abs(G_PMULETS_6[3], &temp);
+                L_MBA_pmulets[11] = temp - L_MBA_pmulets[11];
+                *post_addr = L_MBA_pmulets[11];
+            }
+            if (G_CUR_UAV & MASK_MBA6)
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 3;
+                post_addr = (uint64_t*) (POST_OFFSET_G6_3 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                getscom_abs(G_PMULETS_6[4], &temp);
+                L_MBA_pmulets[12] = temp - L_MBA_pmulets[12];
+                *post_addr = L_MBA_pmulets[12];
+                post_addr++;
+                getscom_abs(G_PMULETS_6[5], &temp);
+                L_MBA_pmulets[13] = temp - L_MBA_pmulets[13];
+                *post_addr = L_MBA_pmulets[13];
+            }
+            if (G_CUR_UAV & MASK_MBA7)
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 4;
+                post_addr = (uint64_t*) (POST_OFFSET_G6_4 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                getscom_abs(G_PMULETS_6[6], &temp);
+                L_MBA_pmulets[14] = temp - L_MBA_pmulets[14];
+                *post_addr = L_MBA_pmulets[14];
+                post_addr++;
+                getscom_abs(G_PMULETS_6[7], &temp);
+                L_MBA_pmulets[15] = temp - L_MBA_pmulets[15];
+                *post_addr = L_MBA_pmulets[15];
+            }
+            post_addr = (uint64_t*) (POST_OFFSET_G6T | PBA_ENABLE);
+            *post_addr = INC_UPD_COUNT;
+            break;
+        case G7://3 NVLINK-NPCQ's and 2 CAPP pmulets each with 4 counters.TOD present here.
+            *L_DBG_GRP = 7;
+            post_addr = (uint64_t*) (POST_OFFSET_G6H | PBA_ENABLE);
+            putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+            *post_addr = INC_UPD_COUNT;
+            post_addr++;
+            if ((G_CUR_UAV & MASK_NVLNK0)||(G_CUR_UAV & MASK_NVLNK1))
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 1;
+                post_addr = (uint64_t*) (POST_OFFSET_G7_1 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                getscom_abs(G_PMULETS_7[0], &u3.pmulet);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+            }
+            if ((G_CUR_UAV & MASK_NVLNK2)||(G_CUR_UAV & MASK_NVLNK3))
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 2;
+                post_addr = (uint64_t*) (POST_OFFSET_G7_2 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                getscom_abs(G_PMULETS_7[1], &u3.pmulet);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+            }
+            if ((G_CUR_UAV & MASK_NVLNK4)||(G_CUR_UAV & MASK_NVLNK5))
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 3;
+                post_addr = (uint64_t*) (POST_OFFSET_G7_3 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                getscom_abs(G_PMULETS_7[2], &u3.pmulet);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+            }
+            if (G_CUR_UAV & MASK_CAPP0)
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 4;
+                post_addr = (uint64_t*) (POST_OFFSET_G7_4 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                getscom_abs(G_PMULETS_7[3], &u3.pmulet);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+                getscom_abs(G_PMULETS_7[4], &u3.pmulet);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+            }
+            if (G_CUR_UAV & MASK_CAPP1)
+            {
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+                *L_DBG_UNIT = 5;
+                post_addr = (uint64_t*) (POST_OFFSET_G7_5 | PBA_ENABLE);
+                putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+                getscom_abs(G_PMULETS_7[5], &u3.pmulet);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+                getscom_abs(G_PMULETS_7[6], &u3.pmulet);
+                for(j=0; j<4; j++)
+                {
+                    *post_addr = (uint64_t)u3.ev.e[j];
+                    post_addr++;
+                }
+            }
+            getscom_abs(TOD_VALUE_REG,&TOD);
+            post_addr = (uint64_t*) (POST_OFFSET_G7_6 | PBA_ENABLE);
+            putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+            *post_addr = TOD;
+            post_addr = (uint64_t*) (POST_OFFSET_G7T | PBA_ENABLE);
+            putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
+            *post_addr = INC_UPD_COUNT;
+            break;
+        default:
+            PK_TRACE("gpe_24x7: Invalid Group:%d",grp);
+            break;
+    }
+}
+
+void initialize_postings()
+{//initialize posting area.
+    volatile uint64_t* post_addr;
+    int i;
+    putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
+    post_addr = (uint64_t*) (POSTING_START | PBA_ENABLE);
+    for(i=0; i<TOTAL_POSTINGS; i++)
+    {
+        *post_addr = (uint64_t)0x0;
+        post_addr++;
+    }
+}
+
+void set_speed(uint64_t* speed, uint8_t* delay, volatile uint64_t* status)
+{//set counter-scom read delay according to speed setting.
+    switch(*speed)
+    {
+        case CNTL_SPEED_1MS: 
+           *delay = 0;
+           break;
+        case CNTL_SPEED_2MS: 
+           *delay = 1;
+           break;
+        case CNTL_SPEED_4MS: 
+           *delay = 2;
+           break;
+        case CNTL_SPEED_8MS: 
+           *delay = 3;
+           break;
+        case CNTL_SPEED_16MS: 
+           *delay = 4;
+           break;
+        case CNTL_SPEED_32MS: 
+           *delay = 5;
+           break;
+        case CNTL_SPEED_64MS: 
+           *delay = 6;
+           break;
+        case CNTL_SPEED_128MS: 
+           *delay = 7;
+           break;
+        case CNTL_SPEED_256MS: 
+           *delay = 8;
+           break;
+        case CNTL_SPEED_512MS: 
+           *delay = 9;
+           break;
+        case CNTL_SPEED_1024MS: 
+           *delay = 10;
+           break;
+        case CNTL_SPEED_2048MS: 
+           *delay = 11;
+           break;
+        default:
+          *status = CNTL_STATUS_ERR1;
+        break;
+     }
+}
diff --git a/src/occ_gpe1/gpe1_24x7.h b/src/occ_gpe1/gpe1_24x7.h
new file mode 100755
index 0000000..ddfb300
--- /dev/null
+++ b/src/occ_gpe1/gpe1_24x7.h
@@ -0,0 +1,504 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/occ_gpe1/gpe1_24x7.h $                                    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2017                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+#ifndef _GPE1_24x7_H
+    #define _GPE1_24x7_H
+//
+//PMU config table defined below.
+#define TOTAL_CONFIGS 60
+#define TOTAL_POSTINGS 238
+#define INC_UPD_COUNT 1
+//
+#define TOTAL_CONFIG_SCOMS 60
+#define TOTAL_COUNTER_SCOMS 71
+//
+uint64_t  G_CUR_UAV = 0;
+uint64_t G_PMU_CONFIGS_8[][2] = 
+{
+//cnpm//
+    {0x5011c13, 0x92aaaa82ac000bf8},//0
+    {0x5011c14, 0x92a8aaaaac000bf8},//1
+    {0x5011c15, 0xaaaaaaaaaaaaaaaa},//2
+    {0x5011c16, 0x0400c0ffffffff00},//3
+//MC23//
+    {0x3010829, 0x0500000000000000},//port0//4
+    {0x3010839, 0x0500000000000000},//port1//5
+    {0x30108a9, 0x0500000000000000},//port2//6
+    {0x30108b9, 0x0500000000000000},//port3//7
+    {0x301083c, 0x0000000000000000},//port0,1//8
+    {0x301083d, 0x0000000053457500},//port0,1//9
+    {0x301083e, 0x0000000000000000},//port0,1//10
+    {0x301083f, 0x00c0800000000000},//port0,1//11
+    {0x30108bc, 0x0000000000000000},//port2,3//12
+    {0x30108bd, 0x000000000000005b},//port2,3//13
+    {0x30108be, 0x64715345755b6000},//port2,3//14
+    {0x30108bf, 0x003e800000000000},//port2,3//15
+//MC01//
+    {0x5010829, 0x0500000000000000},//port0//16
+    {0x5010839, 0x0500000000000000},//port1//17
+    {0x50108a9, 0x0500000000000000},//port2//18
+    {0x50108b9, 0x0500000000000000},//port3//19
+    {0x501083c, 0x0000000000000000},//port0,1//20
+    {0x501083d, 0x0000000053457557},//port0,1//21
+    {0x501083e, 0x5471000000000000},//port0,1//22
+    {0x501083f, 0x00f0800000000000},//port0,1//23
+    {0x50108bc, 0x0000000000000000},//port2,3//24
+    {0x50108bd, 0x0000000000000000},//port2,3//25
+    {0x50108be, 0x00005345755b6000},//port2,3//26
+    {0x50108bf, 0x000e800000000000},//port2,3//27
+//xlinks//
+    {0x501341a, 0xff015daad55aa000},//all xlinks//28
+//nx//
+    {0x20110a6, 0xcaa00000e0000000},//29
+    {0x20110a9, 0xcaa04924f0000000},//30
+    {0x2011054, 0x0000000000000000},//31
+    {0x2011055, 0x00000000600002aa},//32
+//nvlinks-NTL,ATS,XTS//
+    {0x501111e, 0x90aa01444f8a0000},//NTL0//33
+    {0x501113e, 0x90aa01444f8a0000},//NTL1//34
+    {0x501131e, 0x90aa01444f8a0000},//NTL2//35
+    {0x501133e, 0x90aa01444f8a0000},//NTL3//36
+    {0x501151e, 0x90aa01444f8a0000},//NTL4//37
+    {0x501153e, 0x90aa01444f8a0000},//NTL5//38
+    {0x5011600, 0x80aa420000000000},//ATS//39
+    {0x5011645, 0x80aa03050d0e0000},//XTS//40
+//PHB
+    {0xd010917, 0x8000011516190000},//PHB0//41
+    {0xe010917, 0x8000011516190000},//PHB1//42
+    {0xe010957, 0x8000011516190000},//PHB2//43
+    {0xf010917, 0x8000011516190000},//PHB3//44
+    {0xf010957, 0x8000011516190000},//PHB4//45
+    {0xf010997, 0x8000011516190000},//PHB5//46
+//nvlinks-NPCQ//
+    {0x50110C7, 0x80aa1012181a0000},//NPCQ01//47
+    {0x50112C7, 0x80aa1012181a0000},//NPCQ02//48
+    {0x50114C7, 0x80aa1012181a0000},//NPCQ03//49
+//CAPP
+    {0x2010814, 0x8058812200000000},//CAPP01//50
+    {0x2010816, 0x6000000000000000},//CAPP01//51
+    {0x2010824, 0x8058914202000000},//CAPP01//52
+    {0x2010822, 0x1000000000000000},//CAPP01//53
+    {0x2010817, 0x0000000000000000},//CAPP01//54
+    {0x4010814, 0x8058812200000000},//CAPP02//55
+    {0x4010816, 0x6000000000000000},//CAPP02//56
+    {0x4010824, 0x8058914202000000},//CAPP02//57
+    {0x4010822, 0x1000000000000000},//CAPP02//58
+    {0x4010817, 0x0000000000000000} //CAPP02//59
+};
+
+uint64_t G_PMU_CONFIGS_16[][2] = 
+{
+//cnpm
+    {0x5011c13, 0x92aaaa82ac000bf8},//0
+    {0x5011c14, 0x92a8aaaaac000bf8},//1
+    {0x5011c15, 0x5555555555555555},//2
+    {0x5011c16, 0x0400c0ffffffff00},//3
+//MC23//	                        
+    {0x3010829, 0x0500000000000000},//port0//4
+    {0x3010839, 0x0500000000000000},//port1//5
+    {0x30108a9, 0x0500000000000000},//port2//6
+    {0x30108b9, 0x0500000000000000},//port3//7
+    {0x301083c, 0x0000000000000000},//port0,1//8
+    {0x301083d, 0x0000000053457500},//port0,1//9
+    {0x301083e, 0x0000000000000000},//port0,1//10
+    {0x301083f, 0x00c0800000000000},//port0,1//11
+    {0x30108bc, 0x0000000000000000},//port2,3//12
+    {0x30108bd, 0x000000000000005b},//port2,3//13
+    {0x30108be, 0x64715345755b6000},//port2,3//14
+    {0x30108bf, 0x003e800000000000},//port2,3//15
+//MC01//                            
+    {0x5010829, 0x0500000000000000},//port0//16
+    {0x5010839, 0x0500000000000000},//port1//17
+    {0x50108a9, 0x0500000000000000},//port2//18
+    {0x50108b9, 0x0500000000000000},//port3//19
+    {0x501083c, 0x0000000000000000},//port0,1//20
+    {0x501083d, 0x0000000053457557},//port0,1//21
+    {0x501083e, 0x5471000000000000},//port0,1//22
+    {0x501083f, 0x00f0800000000000},//port0,1//23
+    {0x50108bc, 0x0000000000000000},//port2,3//24
+    {0x50108bd, 0x0000000000000000},//port2,3//25
+    {0x50108be, 0x00005345755b6000},//port2,3//26
+    {0x50108bf, 0x000e800000000000},//port2,3//27
+//xlinks                            
+    {0x501341a, 0xff015d55d55aa000},//all xlinks//28
+//nx                                
+    {0x20110a6, 0xc5500000e0000000},//29
+    {0x20110a9, 0xc5504924f0000000},//30
+    {0x2011054, 0x0000000000000000},//31
+    {0x2011055, 0x00000000600002aa},//32
+//nvlinks-NTL,ATS,XTS//             
+    {0x501111e, 0x805501444f8a0000},//NTL0//33
+    {0x501113e, 0x805501444f8a0000},//NTL1//34
+    {0x501131e, 0x805501444f8a0000},//NTL2//35
+    {0x501133e, 0x805501444f8a0000},//NTL3//36
+    {0x501151e, 0x805501444f8a0000},//NTL4//37
+    {0x501153e, 0x805501444f8a0000},//NTL5//38
+    {0x5011600, 0x8055420000000000},//ATS//39
+    {0x5011645, 0x805503050d0e0000},//XTS//40
+//PHB                               
+    {0xd010917, 0x8000011516190000},//PHB0//41
+    {0xe010917, 0x8000011516190000},//PHB1//42
+    {0xe010957, 0x8000011516190000},//PHB2//43
+    {0xf010917, 0x8000011516190000},//PHB3//44
+    {0xf010957, 0x8000011516190000},//PHB4//45
+    {0xf010997, 0x8000011516190000},//PHB5//46
+//nvlinks-NPCQ//                    
+    {0x50110C7, 0x80551012181a0000},//NPCQ01//47
+    {0x50112C7, 0x80551012181a0000},//NPCQ02//48
+    {0x50114C7, 0x80551012181a0000},//NPCQ03//49
+//CAPP                              
+    {0x2010814, 0x803840a100000000},//CAPP01//50
+    {0x2010816, 0x6000000000000000},//CAPP01//51
+    {0x2010824, 0x803850c102000000},//CAPP01//52
+    {0x2010822, 0x1000000000000000},//CAPP01//53
+    {0x2010817, 0x0000000000000000},//CAPP01//54
+    {0x4010814, 0x803840a100000000},//CAPP02//55
+    {0x4010816, 0x6000000000000000},//CAPP02//56
+    {0x4010824, 0x803850c102000000},//CAPP02//57
+    {0x4010822, 0x1000000000000000},//CAPP02//58
+    {0x4010817, 0x0000000000000000} //CAPP02//59
+};
+//
+//PMU counters below
+uint64_t G_PMULETS_1[] =
+{
+//CNPM counters (4 east and 4 west)
+    0x5011c1a,//0//0
+    0x5011c1b,//1//1
+    0x5011c1c,//2//2
+    0x5011c1d,//3//3
+    0x5011c1e,//4//4
+    0x5011c1f,//5//5
+    0x5011c20,//6//6
+    0x5011c21 //7//7
+};
+
+uint64_t G_PMULETS_2[] =
+{
+//x1
+    0x501341b,//0//8
+    0x501341c,//1//9
+//x0
+    0x501341d,//2//10
+    0x501341e,//3//11
+//x2
+    0x501341f,//4//12
+    0x5013420,//5//13
+//nx
+    0x20110a7,//6//14
+    0x20110aa //7//15
+};
+
+uint64_t G_PMULETS_3[] =
+{
+//NTL0
+    0x501111f,//0//16
+//NTL1
+    0x501113f,//1//17
+//NTL2
+    0x501131f,//2//18
+//NTL3
+    0x501133f,//3//19
+//NTL4
+    0x501151f,//4//20
+//NTL5
+    0x501153f,//5//21
+//ATS
+    0x5011601,//6//22
+//XTS
+    0x5011648 //7//23
+};
+
+uint64_t G_PMULETS_4a[] =
+{//PHB0
+    0xd010918,//0//24
+    0xd010919,//1//25
+    0xd01091a,//2//26
+    0xd01091b //3//27
+};
+
+uint64_t G_PMULETS_4b[] =
+{//PHB1
+    0xe010918,//0//28
+    0xe010919,//1//29
+    0xe01091a,//2//30
+    0xe01091b //3//31
+};
+
+uint64_t G_PMULETS_4c[] =
+{//PHB2
+    0xe010958,//0//32
+    0xe010959,//1//33
+    0xe01095a,//2//34
+    0xe01095b //3//35
+};
+
+uint64_t G_PMULETS_4d[] =
+{//PHB3
+    0xf010918,//0//36
+    0xf010919,//1//37
+    0xf01091a,//2//38
+    0xf01091b //3//39
+};
+
+uint64_t G_PMULETS_4e[] =
+{//PHB4
+    0xf010958,//0//40
+    0xf010959,//1//41
+    0xf01095a,//2//42
+    0xf01095b //3//43
+};
+
+uint64_t G_PMULETS_4f[] =
+{//PHB5
+    0xf010998,//0//44
+    0xf010999,//1//45
+    0xf01099a,//2//46
+    0xf01099b //3//47
+};
+
+uint64_t G_PMULETS_5[] =
+{
+//MBA0
+    0x7010937,//0//48
+    0x7010939,//1//49
+//MBA1
+    0x7010977,//2//50
+    0x7010979,//3//51
+//MBA2
+    0x70109b7,//4//52
+    0x70109b9,//5//53
+//MBA3
+    0x70109f7,//6//54
+    0x70109f9 //7//55
+};
+
+uint64_t G_PMULETS_6[] =
+{
+//MBA4
+    0x8010937,//0//56
+    0x8010939,//1//57
+//MBA5
+    0x8010977,//2//58
+    0x8010979,//3//59
+//MBA6
+    0x80109b7,//4//60
+    0x80109b9,//5//61
+//MBA7
+    0x80109f7,//6//62
+    0x80109f9 //7//63
+};
+
+uint64_t G_PMULETS_7[] =
+{
+//NPCQ01
+    0x5011086,//0//64
+//NPCQ02
+    0x5011186,//1//65
+//NPCQ03
+    0x5011286,//2//66
+//CAPP01
+    0x2010815,//3//67
+    0x2010825,//4//68
+//CAPP02
+    0x4010815,//5//69
+    0x4010825//6//70
+};
+
+enum groups {G1=1,G2=2,G3=3,G4=4,G5=5,G6=6,G7=7};
+
+enum
+{
+    TOD_VALUE_REG               = 0x00040020,
+    ZERO                        = 0,
+    PBA_ENABLE                  = 0x80000000,
+    SGPE_24x7_OFFSET            = 0x00180000,//1MB + 512KB
+    TEST_ADDR                   = 0x00180110,
+    PB_PMU_CNPME_05011C13       = 0x05011C13,
+    PBASLVCTL3_C0040030         = 0xC0040030,
+    PBASLV_SET_DMA              = 0x97005EC000000000,
+    PBASLV_SET_ATOMIC           = 0x97405EC060000000,
+    //POSTING OFFSETS for groups
+    POSTING_START               = 0x00180000,//1MB + 512KB
+//
+    POST_OFFSET_G1H             = 0x00180000,
+    POST_OFFSET_G1T             = 0x00180108,
+//
+    POST_OFFSET_G2H             = 0x00180110,
+    POST_OFFSET_G2_1            = 0x00180118,
+    POST_OFFSET_G2_2            = 0x00180158,
+    POST_OFFSET_G2_3            = 0x00180198,
+    POST_OFFSET_G2_4            = 0x001801D8,
+    POST_OFFSET_G2T             = 0x00180218,
+//
+    POST_OFFSET_G3H             = 0x00180220,
+    POST_OFFSET_G3_1            = 0x00180228,
+    POST_OFFSET_G3_2            = 0x00180248,
+    POST_OFFSET_G3_3            = 0x00180268,
+    POST_OFFSET_G3_4            = 0x00180288,
+    POST_OFFSET_G3_5            = 0x001802A8,
+    POST_OFFSET_G3_6            = 0x001802C8,
+    POST_OFFSET_G3_7            = 0x001802E8,
+    POST_OFFSET_G3T             = 0x00180328,
+//
+    POST_OFFSET_G4H             = 0x00180330,
+    POST_OFFSET_G4a             = 0x00180338,
+    POST_OFFSET_G4b             = 0x00180358,
+    POST_OFFSET_G4c             = 0x00180378,
+    POST_OFFSET_G4d             = 0x00180398,
+    POST_OFFSET_G4e             = 0x001803B8,
+    POST_OFFSET_G4f             = 0x001803D8,
+    POST_OFFSET_G4T             = 0x00180438,
+//
+    POST_OFFSET_G5H             = 0x00180440,
+    POST_OFFSET_G5_1            = 0x00180448,
+    POST_OFFSET_G5_2            = 0x00180460,
+    POST_OFFSET_G5_3            = 0x00180478,
+    POST_OFFSET_G5_4            = 0x00180490,
+    POST_OFFSET_G5T             = 0x00180548,
+//
+    POST_OFFSET_G6H             = 0x00180550,
+    POST_OFFSET_G6_1            = 0x00180558,
+    POST_OFFSET_G6_2            = 0x00180570,
+    POST_OFFSET_G6_3            = 0x00180588,
+    POST_OFFSET_G6_4            = 0x001805A0,
+    POST_OFFSET_G6T             = 0x00180658,
+//
+    POST_OFFSET_G7H             = 0x00180660,
+    POST_OFFSET_G7_1            = 0x00180668,
+    POST_OFFSET_G7_2            = 0x00180688,
+    POST_OFFSET_G7_3            = 0x001806A8,
+    POST_OFFSET_G7_4            = 0x001806C8,
+    POST_OFFSET_G7_5            = 0x00180708,
+    POST_OFFSET_G7_6            = 0x00180748,
+    POST_OFFSET_G7T             = 0x00180768,
+    //CONTROL BLOCK FIELD OFFSETS
+    //cntl block @ last 1k of 24x7 space
+    CNTL_STATUS_OFFSET          = 0x001BFC00,
+    CNTL_CMD_OFFSET             = 0x001BFC08,
+    CNTL_SPEED_OFFSET           = 0x001BFC10,
+    CNTL_UAV_OFFSET             = 0x001BFC18,
+    CNTL_MODE_OFFSET            = 0x001BFC20,
+///////////////////////////////////////////////////
+    //error tracking fields(internal)
+    //last conf scom
+    DBG_CONF_OFFSET             = 0x001BFC40,
+    DBG_GRP_OFFSET              = 0x001BFC50,
+    DBG_UNIT_OFFSET             = 0x001BFC58,
+    DBG_TICS_OFFSET             = 0x001BFC60,
+//////////////////////////////////////////////////
+    //cntl status values
+    CNTL_STATUS_INIT            = 0x0,
+    CNTL_STATUS_RUN             = 0x1,
+    CNTL_STATUS_PAUSE           = 0x2,
+    CNTL_STATUS_ERR1            = 0x3,
+    CNTL_STATUS_ERR2            = 0x4,
+    //cntl cmd values
+    CNTL_CMD_NOP                = 0x0,
+    CNTL_CMD_RESUME             = 0x1,
+    CNTL_CMD_PAUSE              = 0x2,
+    CNTL_CMD_CLEAR              = 0x3,
+    //cntl speed values
+    CNTL_SPEED_1MS              = 0x0,
+    CNTL_SPEED_2MS              = 0x1,
+    CNTL_SPEED_4MS              = 0x2,
+    CNTL_SPEED_8MS              = 0x3,
+    CNTL_SPEED_16MS             = 0x4,
+    CNTL_SPEED_32MS             = 0x5,
+    CNTL_SPEED_64MS             = 0x6,
+    CNTL_SPEED_128MS            = 0x7,
+    CNTL_SPEED_256MS            = 0x8,
+    CNTL_SPEED_512MS            = 0x9,
+    CNTL_SPEED_1024MS           = 0xA,
+    CNTL_SPEED_2048MS           = 0xB,
+    //cntl cmd uav temp
+    //CNTL_UAV_TEMP               = 0xFFFF807000000000,
+    CNTL_UAV_TEMP               = 0x8000007000000000,
+    //cntl block modes
+    CNTL_MODE_MONITOR           = 0x0
+};
+//MASKS used to identify individual units from Unit availability vector (UAV)
+enum MASKS
+{
+    MASK_PB     = 0x8000000000000000,
+    MASK_MCS0   = 0x4000000000000000,
+    MASK_MCS1   = 0x2000000000000000,
+    MASK_MCS2   = 0x1000000000000000,
+    MASK_MCS3   = 0x800000000000000,
+    MASK_MCS4   = 0x400000000000000,
+    MASK_MCS5   = 0x200000000000000,
+    MASK_MCS6   = 0x100000000000000,
+    MASK_MCS7   = 0x80000000000000,
+    MASK_MBA0   = 0x40000000000000,
+    MASK_MBA1   = 0x20000000000000,
+    MASK_MBA2   = 0x10000000000000,
+    MASK_MBA3   = 0x8000000000000,
+    MASK_MBA4   = 0x4000000000000,
+    MASK_MBA5   = 0x2000000000000,
+    MASK_MBA6   = 0x1000000000000,
+    MASK_MBA7   = 0x800000000000,
+    MASK_Cen1   = 0x400000000000,
+    MASK_Cen2   = 0x200000000000,
+    MASK_Cen0   = 0x100000000000,
+    MASK_Cen3   = 0x80000000000,
+    MASK_Cen4   = 0x40000000000,
+    MASK_Cen5   = 0x20000000000,
+    MASK_Cen6   = 0x10000000000,
+    MASK_Cen7   = 0x8000000000,
+    MASK_XLNK0  = 0x4000000000,
+    MASK_XLNK1  = 0x2000000000,
+    MASK_XLNK2  = 0x1000000000,
+    MASK_MCD0   = 0x800000000,
+    MASK_MCD1   = 0x400000000,
+    MASK_PHB0   = 0x200000000,
+    MASK_PHB1   = 0x100000000,
+    MASK_PHB2   = 0x80000000,
+    MASK_PHB3   = 0x40000000,
+    MASK_PHB4   = 0x20000000,
+    MASK_PHB5   = 0x10000000,
+    MASK_NX     = 0x8000000,
+    MASK_CAPP0  = 0x4000000,
+    MASK_CAPP1  = 0x2000000,
+    MASK_VAS    = 0x1000000,
+    MASK_INT    = 0x800000,
+    MASK_ALNK0  = 0x400000,
+    MASK_ALNK1  = 0x200000,
+    MASK_ALNK2  = 0x100000,
+    MASK_ALNK3  = 0x80000,
+    MASK_NVLNK0 = 0x40000,
+    MASK_NVLNK1 = 0x20000,
+    MASK_NVLNK2 = 0x10000,
+    MASK_NVLNK3 = 0x8000,
+    MASK_NVLNK4 = 0x4000,
+    MASK_NVLNK5 = 0x2000
+};
+//
+//function declarations below.
+//
+void configure_pmu (uint8_t, uint64_t);
+void post_pmu_events (int);
+void initialize_postings();
+void set_speed(uint64_t*, uint8_t*, volatile uint64_t*);
+#endif //_GPE1_24x7_H
diff --git a/src/occ_gpe1/pk_app_cfg.h b/src/occ_gpe1/pk_app_cfg.h
index fa1e2c6..39c1a25 100644
--- a/src/occ_gpe1/pk_app_cfg.h
+++ b/src/occ_gpe1/pk_app_cfg.h
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -57,5 +57,7 @@
 #define STATIC_IRQ_TABLE
 
 #define STATIC_IPC_TABLES
+// PBA Slave allocated to Gpe 1 is PBA_SLAVE 2. SET PBASLVCTLN to 2 here.
+#define PBASLVCTLN 2
 
 #endif /*__PK_APP_CFG_H__*/