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| author | Zane Shelley <zshelle@us.ibm.com> | 2018-12-06 11:17:18 -0600 |
|---|---|---|
| committer | Martha Broyles <mbroyles@us.ibm.com> | 2019-01-02 12:50:23 -0600 |
| commit | d85d3c5387ec9829ef29b98c16112210f343bae7 (patch) | |
| tree | 21e10696fc5d278c430c6466ee53544d00469b6f /src/occ_gpe0/firdata/scom_util.h | |
| parent | d60be21fc39657514717869098f8da519a3e0b40 (diff) | |
| download | talos-occ-d85d3c5387ec9829ef29b98c16112210f343bae7.tar.gz talos-occ-d85d3c5387ec9829ef29b98c16112210f343bae7.zip | |
FIRDATA: add Axone memory subsystem SCOM support
Change-Id: Iaa32e0cc115f5c72e2b8e19f55e3148d115b5aa8
RTC: 201994
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69530
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Diffstat (limited to 'src/occ_gpe0/firdata/scom_util.h')
| -rw-r--r-- | src/occ_gpe0/firdata/scom_util.h | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/src/occ_gpe0/firdata/scom_util.h b/src/occ_gpe0/firdata/scom_util.h index 1ec7fd2..278f304 100644 --- a/src/occ_gpe0/firdata/scom_util.h +++ b/src/occ_gpe0/firdata/scom_util.h @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/occ_405/firdata/scom_util.h $ */ +/* $Source: src/occ_gpe0/firdata/scom_util.h $ */ /* */ /* OpenPOWER OnChipController Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -73,6 +73,22 @@ typedef enum N2_PCIS0_0_RING_ID = 0x3, ///< PCIS0_0 } p9_n2_ring_id_t; +typedef enum +{ + P9A_MC_OMIC0_RING_ID = 0x4, ///< OMIC0 + P9A_MC_OMIC2_RING_ID = 0x6, ///< OMIC2 + P9A_MC_OMIC0_PPE_RING_ID = 0x9, ///< OMIC0 PPE + P9A_MC_OMIC2_PPE_RING_ID = 0xB, ///< OMIC2 PPE +} p9a_mc_ring_id_t; + +typedef enum +{ + P9A_MC_DSTL_CHAN0_SAT_ID = 0x4, ///< DSTL registers channel 0 + P9A_MC_DSTL_CHAN3_SAT_ID = 0x7, ///< DSTL registers channel 3 + P9A_MC_USTL_CHAN0_SAT_ID = 0x8, ///< USTL registers channel 0 + P9A_MC_USTL_CHAN3_SAT_ID = 0xB, ///< USTL registers channel 3 +} p9a_mc_sat_id_t; + /** @brief Performs a hardware scom on a regular register. * @param i_trgt The SCOM target. * @param i_addr 32-bit SCOM address. |
