Enable Sensor support

add necessary sensor, amec, and other files to the build list.
add the task_amec_slave to the rtls tick tables
modify the gpe request structures to reflect the new P9 design
enrich the .dis files contects for better debugging

Change-Id: Iae39bb1c430da56310478c24a28aad6dfbc6d6d9
RTC: 133865
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21789
Tested-by: FSP CI Jenkins
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>

19 files changed, 225 insertions, 124 deletions

diff --git a/src/occ_405/Makefile b/src/occ_405/Makefile
index cfe7af0..2bc5d36 100755
--- a/src/occ_405/Makefile
+++ b/src/occ_405/Makefile
@@ -61,6 +61,9 @@ LIB_DIRS =  -L$(OBJDIR) \
             -L$(OBJDIR)/thread \
             -L$(OBJDIR)/timer \
             -L$(OBJDIR)/trac \
+            -L$(OBJDIR)/amec \
+            -L$(OBJDIR)/dcom \
+            -L$(OBJDIR)/proc
 
 #default target is to make a binary application image
 #This removes all unecessary headers from the ELF executable
diff --git a/src/occ_405/amec/amec_freq.c b/src/occ_405/amec/amec_freq.c
index ee05d00..9ae4c03 100755
--- a/src/occ_405/amec/amec_freq.c
+++ b/src/occ_405/amec/amec_freq.c
@@ -47,6 +47,7 @@
 #include <amec_sensors_fw.h>
 #include <amec_data.h>
 #include <amec_freq.h>
+#include "pss_constants.h"
 
 //*************************************************************************
 // Externs
@@ -77,7 +78,7 @@ const uint32_t G_pmc_ffdc_scom_addrs[PMC_FFDC_SCOM_ADDRS_SIZE] =
     PMC_LFIR_ERR_MASK_REG,
     OCB_OCCLFIR,
     PBA_FIR,
-    TOD_VALUE_REG
+    TOD_VALUE_REG 
 };
 
 //FFDC OCI addresses as requested by Greg Still in defect SW247927
@@ -212,6 +213,9 @@ errlHndl_t amec_set_freq_range(const OCC_MODE i_mode)
     return l_err;
 }
 
+// @TODO - TEMP - Code not ready yet
+#if 0
+
 // Function Specification
 //
 // Name: amec_slv_voting_box
@@ -546,6 +550,8 @@ void amec_slv_freq_smh(void)
     }
 }
 
+#endif // @TODO - TEMP - Code not ready yet
+
 // Function Specification
 //
 // Name: amec_slv_freq_smh
@@ -621,11 +627,14 @@ void amec_slv_mem_voting_box(void)
         if(!L_throttle_traced)
         {
             L_throttle_traced = TRUE;
+// @TODO - TEMP - No dimm temp Colection yet
+/*
             TRAC_INFO("Memory is being throttled. reason[%d] vote[%d] cent_expired[0x%02x] dimm_expired[0x%02x]",
                        l_reason,
                        l_vote,
                        G_cent_temp_expired_bitmap,
                        G_dimm_temp_expired_bitmap);
+*/
         }
     }
     else
@@ -865,6 +874,8 @@ void amec_slv_check_perf(void)
 // time to stabilize
 void amec_verify_pstate()
 {
+//  @TODO - TEMP Pstate functions not defined yet
+#if 0
     uint8_t                             l_core = 0;
     int8_t                              l_pstate_from_fmax = 0;
     gpe_bulk_core_data_t *              l_core_data_ptr;
@@ -956,6 +967,7 @@ void amec_verify_pstate()
             REQUEST_RESET(l_err);
         }
     }
+#endif // #if 0: @TODO - TEMP Pstate functions not defined yet
 }
 
 // Fills in a pmc ffdc buffer with lots of PMC related OCI and SCOM registers
diff --git a/src/occ_405/amec/amec_init.c b/src/occ_405/amec/amec_init.c
index 487c9ef..bd2d0d2 100644
--- a/src/occ_405/amec/amec_init.c
+++ b/src/occ_405/amec/amec_init.c
@@ -68,9 +68,10 @@ amec_sys_t g_amec_sys = {0};
 amec_sys_t * g_amec = &g_amec_sys;
 
 // GPE Request Structure that is used to measure the worst case GPE timings
-PoreFlex G_gpe_nop_request[NUM_GPE_ENGINES];
+GpeRequest G_gpe_nop_request[NUM_GPE_ENGINES];
 
-extern PoreEntryPoint GPE_pore_nop;
+// @TODO - TEMP: not ready yet
+//extern PoreEntryPoint GPE_pore_nop;
 extern void amec_slv_update_gpe_sensors(uint8_t i_gpe_engine);
 extern void amec_slv_update_gpe_sensors(uint8_t i_gpe_engine);
 
@@ -78,6 +79,8 @@ extern void amec_slv_update_gpe_sensors(uint8_t i_gpe_engine);
 // Function Prototypes
 //*************************************************************************
 
+// @TODO - TEMP: not ready yet
+#if 0
 //*************************************************************************
 // Functions
 //*************************************************************************
@@ -236,6 +239,7 @@ void amec_init_vector_sensors(void)
   }
 #endif
 }
+#endif // #if 0 @TODO - TEMP: not ready yet
 
 // Function Specification
 //
@@ -286,6 +290,8 @@ void amec_init_gamec_struct(void)
   g_amec->vrhotproc.freq_request = -1;
   g_amec->vrhotproc.speed_request = 1000;
 
+// @TODO - TEMP: not ready yet in Phase 1
+/*
   // Initialize partition information
   amec_part_init();
 
@@ -294,6 +300,7 @@ void amec_init_gamec_struct(void)
   {
     amec_core_perf_counter_ctor(&g_amec->proc[0].core[l_idx].core_perf, 0, l_idx);
   }
+*/
 
   //Initialize processor fields
   g_amec->proc[0].core_max_freq = G_sysConfigData.sys_mode_freq.table[OCC_MODE_TURBO];
@@ -355,14 +362,20 @@ void amec_init_gamec_struct(void)
 // End Function Specification
 void amec_slave_init()
 {
+// @TODO - TEMP: not ready yet
+/*
   errlHndl_t l_err = NULL;   // Error handler
   int         rc   = 0;      // Return code
   int         rc2  = 0;      // Return code
+*/
 
   // Set the GPE Request Pointers to NULL in case the create fails.
   G_fw_timing.gpe0_timing_request = NULL;
   G_fw_timing.gpe1_timing_request = NULL;
 
+// @TODO - TEMP: not ready yet
+#if 0
+
   // Initializes the GPE routine that will be used to measure the worst case
   // timings for GPE0
   rc  = pore_flex_create( &G_gpe_nop_request[0],        //gpe_req for the task
@@ -427,6 +440,8 @@ void amec_slave_init()
   // Initialize Vector Sensors for AMEC use
   amec_init_vector_sensors();
 
+#endif // #if 0 - @TODO - TEMP - Not ready yet
+
   // Initialize AMEC internal parameters
   amec_init_gamec_struct();
 }
diff --git a/src/occ_405/amec/amec_sensors_fw.c b/src/occ_405/amec/amec_sensors_fw.c
index 1bc3811..8447f2c 100644
--- a/src/occ_405/amec/amec_sensors_fw.c
+++ b/src/occ_405/amec/amec_sensors_fw.c
@@ -162,13 +162,15 @@ void amec_update_fw_sensors(void)
             // Update Time used to measure GPE duration.
             G_fw_timing.rtl_start_gpe = G_fw_timing.rtl_start;
 
+// @TODO - TEMP - Old PORE SCHEDULE, needs to be replaced with GPE schedule code.
+/*
             // Schedule the GPE Routines that will run and update the worst
             // case timings (via callback) after they complete.  These GPE
             // routines are the last GPE routines added to the queue
             // during the RTL tick.
             rc  = pore_flex_schedule(G_fw_timing.gpe0_timing_request);
             rc2 = pore_flex_schedule(G_fw_timing.gpe1_timing_request);
-
+*/
             if(rc || rc2)
             {
                 /* @
@@ -197,6 +199,8 @@ void amec_update_fw_sensors(void)
         }
         else if(L_consec_trace_count < MAX_CONSEC_TRACE)
         {
+// @TODO: TEMP - PORE GPE Codes, needs to reflect PPE architecture.
+/*
             uint64_t l_dbg0;
             uint64_t l_dbg1;
             uint64_t l_status;
@@ -233,6 +237,7 @@ void amec_update_fw_sensors(void)
                          (uint32_t)(l_status & 0x00000000ffffffffull));
             }
             L_consec_trace_count++;
+*/
         }
     }
 }
diff --git a/src/occ_405/amec/amec_sensors_power.c b/src/occ_405/amec/amec_sensors_power.c
index 8d08db3..3369a5e 100755
--- a/src/occ_405/amec/amec_sensors_power.c
+++ b/src/occ_405/amec/amec_sensors_power.c
@@ -43,7 +43,8 @@
 #include "amec_service_codes.h"
 #include <amec_sensors_power.h>
 #include <cmdh_snapshot.h>
-#include <vrm.h>
+// @TODO - TEMP - uncomment when vrm file is updated
+//#include <vrm.h>
 #include "amec_oversub.h"
 
 /******************************************************************************/
@@ -435,6 +436,8 @@ void amec_update_apss_sensors(void)
     }
 }
 
+// @TODO - TEMP - SPIVRMs are no longer defined, pgp_vrm.h and vrm.c are not present
+#if 0
 
 // Function Specification
 //
@@ -571,6 +574,8 @@ void amec_update_vrm_sensors(void)
     }
 }
 
+#endif // #if 0 @TODO - TEMP - SPIVRMs are no longer defined, pgp_vrm.h and vrm.c are not present
+
 // Function Specification
 //
 // Name: amec_update_external_voltage
@@ -594,7 +599,8 @@ void amec_update_external_voltage()
     /*  Code                                                                  */
     /*------------------------------------------------------------------------*/
     // Collect the external voltage data
-    l_data = in32(PMC_GLOBAL_ACTUAL_VOLTAGE_REG);
+// @TODO - TEMP - External Votage regulator is not defined in simics yet
+//    l_data = in32(PMC_GLOBAL_ACTUAL_VOLTAGE_REG);
 
     // Extract the Vdd vid code and convert to voltage
     l_temp = (l_data & 0xFF000000) >>24;
diff --git a/src/occ_405/amec/amec_slave_smh.c b/src/occ_405/amec/amec_slave_smh.c
index 1b5dbc0..93e96eb 100755
--- a/src/occ_405/amec/amec_slave_smh.c
+++ b/src/occ_405/amec/amec_slave_smh.c
@@ -75,6 +75,9 @@ smh_state_t G_amec_slv_state = {AMEC_INITIAL_STATE,
 // Number of ticks for periodically updating VRM-related data
 #define AMEC_UPDATE_VRM_TICKS   4000
 
+// @TODO - TEMP: Not Ready yet in Phase 1.
+#if 0
+
 // --------------------------------------------------------
 // AMEC Slave State 6 Substate Table
 // --------------------------------------------------------
@@ -132,6 +135,8 @@ const smh_tbl_t amec_slv_state_table[AMEC_SMH_STATES_PER_LVL] =
   {amec_slv_state_7, amec_slv_state_7_substate_table},
 };
 
+#endif // #if 0 @TODO - TEMP: Not Ready yet in Phase 1.
+
 // This sets up the function pointer that will be called to update the
 // fw timings when the AMEC Slave State Machine finishes.
 smh_state_timing_t G_amec_slv_state_timings = {amec_slv_update_smh_sensors};
@@ -152,6 +157,9 @@ smh_state_timing_t G_amec_slv_state_timings = {amec_slv_update_smh_sensors};
 // Functions
 //*************************************************************************
 
+// @TODO - TEMP: Not Ready yet in Phase 1.
+#if 0
+
 // Function Specification
 //
 // Name: amec_slv_check_apss_fail
@@ -311,6 +319,8 @@ void amec_slv_pstate_uplift_check(void)
     }
 }
 
+#endif // #if 0 @TODO - TEMP - Not ready yet in Phase 1
+
 // Function Specification
 //
 // Name: amec_slv_common_tasks_pre
@@ -323,24 +333,28 @@ void amec_slv_pstate_uplift_check(void)
 // End Function Specification
 void amec_slv_common_tasks_pre(void)
 {
-  static uint16_t L_counter = 0;
+//  @TODO - TEMP - Not ready yet in Phase 1
+//  static uint16_t L_counter = 0;
 
   AMEC_DBG("\tAMEC Slave Pre-State Common\n");
 
   // Check if we need to apply a voltage uplift to the Global Pstate table
-  amec_slv_pstate_uplift_check();
+// @TODO - TEMP: Not Ready yet in Phase 1.
+//  amec_slv_pstate_uplift_check();
 
   // Update the FW Worst Case sensors every tick
   amec_update_fw_sensors();
 
   // Update the fast core data sensors every tick
-  amec_update_fast_core_data_sensors();
+//  @TODO - TEMP - Not ready yet in Phase 1
+//  amec_update_fast_core_data_sensors();
 
   // Update the sensors that come from the APSS every tick
   amec_update_apss_sensors();
 
   // Call the stream buffer recording function
-  amec_analytics_sb_recording();
+//  @TODO - TEMP - Not ready yet in Phase 1
+/*  amec_analytics_sb_recording();
 
   // Update the sensors that come from the VRM
   L_counter++;
@@ -352,6 +366,7 @@ void amec_slv_common_tasks_pre(void)
       }
       L_counter = 0;
   }
+*/
 
   // Update the external voltage sensors
   amec_update_external_voltage();
@@ -361,9 +376,12 @@ void amec_slv_common_tasks_pre(void)
   amec_update_current_sensor(); // Compute estimate for Vdd output current
 
   // Over-subscription check
-  amec_oversub_check();
+//  @TODO - TEMP - Not ready yet in Phase 1
+//  amec_oversub_check();
 }
 
+// @TODO - TEMP: Not Ready yet in Phase 1.
+#if 0
 
 // Function Specification
 //
@@ -762,7 +780,7 @@ void amec_slv_substate_7_7(void)
     // Call health monitor to check for processor error temperature conditions
     amec_health_check_proc_temp();
 }
-
+#endif // #if 0 -  @TODO - TEMP: Not Ready yet in Phase 1.
 /*----------------------------------------------------------------------------*/
 /* End                                                                        */
 /*----------------------------------------------------------------------------*/
diff --git a/src/occ_405/amec/amec_tasks.c b/src/occ_405/amec/amec_tasks.c
index ce306a9..7925507 100755
--- a/src/occ_405/amec/amec_tasks.c
+++ b/src/occ_405/amec/amec_tasks.c
@@ -279,10 +279,12 @@ void task_amec_slave( task_t *i_self)
 
   amec_slv_common_tasks_pre();
 
+// @TODO TEMP: Not ready yet in phase 1
+/*
   amec_generic_smh( amec_slv_state_table, &G_amec_slv_state, &G_amec_slv_state_timings );
 
   amec_slv_common_tasks_post();
-
+*/
   // Set the total AMEC int task time for this tick, to the duration of the slave tasks.
   G_fw_timing.ameint_dur = DURATION_IN_US_UNTIL_NOW_FROM(l_start);
 }
diff --git a/src/occ_405/dcom/dcom.c b/src/occ_405/dcom/dcom.c
index 23db8e0..b5f8a52 100755
--- a/src/occ_405/dcom/dcom.c
+++ b/src/occ_405/dcom/dcom.c
@@ -39,6 +39,7 @@
 #include <amec_data.h>
 #include <amec_sys.h>
 #include "scom.h"
+#include "pss_constants.h"  // @TODO: move with HW registers? 
 
 #define PBAX_CONFIGURE_RCV_GROUP_MASK 0xff
 
@@ -257,6 +258,8 @@ void dcom_initialize_roles(void)
         G_occ_role = OCC_MASTER;
         rtl_set_run_mask(RTL_FLAG_MSTR);
 
+// @TODO TEMP - not ready yet for multiple DCMs
+/*
         // Save off OCC role inside DCM chip
         if(gpsm_dcm_slave_p())
         {
@@ -273,6 +276,7 @@ void dcom_initialize_roles(void)
                 gpsm_dcm_mode_p(),
                 !gpsm_dcm_slave_p(),
                 cfam_id() );
+*/
     }
     else
     {
@@ -316,10 +320,12 @@ void dcom_initialize_roles(void)
     G_occ_num_present = __builtin_popcount(G_sysConfigData.is_occ_present);
 
     // Initialize DCOM Thread Sem
+// @TODO - TEMP - Not ready yet in phase 1
+/*
     ssx_semaphore_create( &G_dcomThreadWakeupSem, // Semaphore
                           1,                      // Initial Count
                           0);                     // No Max Count
-
+*/
 }
 
 // Function Specification
@@ -338,7 +344,8 @@ void dcom_initialize_pbax_queues(void)
 
     do
     {
-        pbax_send_disable();
+// @TODO - TEMP - PBA_XCFG (Address 0x40020108) is not mapped in simics yet
+//        pbax_send_disable();
 
         // Check if conversion has valid information
         if (( l_pbaxid.chip_id > MAX_PBAX_CHIP_ID ) ||
@@ -362,7 +369,8 @@ void dcom_initialize_pbax_queues(void)
         }
 
         //enabled pbax send does not return errors
-        pbax_send_enable();
+// @TODO - TEMP - PBA_XCFG (Address 0x40020108) is not mapped in simics yet
+//        pbax_send_enable();
 
         if(G_occ_role == OCC_SLAVE)
         {
@@ -655,6 +663,8 @@ void dcom_build_occfw_msg( const dcom_error_type_t i_which_msg )
 
 }
 
+#if 0 // TODO - TEMP - Phase1 - Not ready yet for multi OCC communications.
+
 // Function Specification
 //
 // Name: task_dcom_parse_occfwmsg
@@ -811,5 +821,7 @@ void task_dcom_parse_occfwmsg(task_t *i_self)
     G_slave_event_flags = (G_slave_event_flags & (~(G_dcom_slv_inbox_rx.occ_fw_mailbox[3])));
 }
 
+#endif // #if 0 -  // TODO - TEMP - Phase1 - Not ready yet for multi OCC communications.
+
 #endif //_DCOM_C
 
diff --git a/src/occ_405/dcom/dcomMasterRx.c b/src/occ_405/dcom/dcomMasterRx.c
index b5da6b3..fcd6662 100644
--- a/src/occ_405/dcom/dcomMasterRx.c
+++ b/src/occ_405/dcom/dcomMasterRx.c
@@ -25,9 +25,7 @@
 
 #ifndef _DCOMMASTERRX_C
 #define _DCOMMASTERRX_C
-
-#include <pgp_pmc.h>
-#include "pgp_pba.h"
+#include "occhw_pba.h"
 #include <rtls.h>
 #include <apss.h>
 #include <dcom.h>
diff --git a/src/occ_405/dcom/dcomSlaveRx.c b/src/occ_405/dcom/dcomSlaveRx.c
index 0eb6be3..d4d8aff 100644
--- a/src/occ_405/dcom/dcomSlaveRx.c
+++ b/src/occ_405/dcom/dcomSlaveRx.c
@@ -25,9 +25,7 @@
 
 #ifndef _DCOMSLAVERX_C
 #define _DCOMSLAVERX_C
-
-#include <pgp_pmc.h>
-#include "pgp_pba.h"
+#include "occhw_pba.h"
 #include <rtls.h>
 #include <apss.h>
 #include <dcom.h>
diff --git a/src/occ_405/dcom/dcomSlaveTx.c b/src/occ_405/dcom/dcomSlaveTx.c
index 41a19cf..0e16782 100755
--- a/src/occ_405/dcom/dcomSlaveTx.c
+++ b/src/occ_405/dcom/dcomSlaveTx.c
@@ -25,9 +25,7 @@
 
 #ifndef _DCOMSLAVETX_C
 #define _DCOMSLAVETX_C
-
-#include <pgp_pmc.h>
-#include "pgp_pba.h"
+#include "occhw_pba.h"
 #include <rtls.h>
 #include <apss.h>
 #include <dcom.h>
diff --git a/src/occ_405/main.c b/src/occ_405/main.c
index 845b68a..d489cfc 100755
--- a/src/occ_405/main.c
+++ b/src/occ_405/main.c
@@ -62,9 +62,7 @@ extern uint32_t __ssx_boot; // Function address is 32 bits
 extern uint32_t G_occ_phantom_critical_count;
 extern uint32_t G_occ_phantom_noncritical_count;
 extern uint8_t G_occ_interrupt_type;
-
-// Remove the next LOC when dcom_initialize_roles() is un-commented
-uint8_t     G_occ_role = OCC_MASTER;  // TEMP
+extern uint8_t G_occ_role;
 
 extern GpeRequest G_meas_start_request;
 extern GpeRequest G_meas_cont_request;
@@ -761,13 +759,13 @@ void master_occ_init()
  *
  * End Function Specification
  */
-/* TEMP -- NO SLAVES YET
 void slave_occ_init()
 {
     // Init the DPSS oversubscription IRQ handler
     MAIN_DBG("Initializing Oversubscription IRQ...");
     // TEMP -- NO DPSS/ERRL YET
-    //errlHndl_t l_errl = dpss_oversubscription_irq_initialize();
+/*
+    errlHndl_t l_errl = dpss_oversubscription_irq_initialize();
 
     if( l_errl )
     {
@@ -782,15 +780,16 @@ void slave_occ_init()
     {
         MAIN_TRAC_INFO("Oversubscription IRQ initialized");
     }
-
+*/
     //Set up doorbell queues
     // TEMP -- NO DCOM YET
     //dcom_initialize_pbax_queues();
 
     // Run AMEC Slave Init Code
-    // TEMP -- NO AMEC YET
-    //amec_slave_init();
+    amec_slave_init();
 
+// @TODO - TEMP: SMGR not ready yet
+/*
     // Initialize SMGR State Semaphores
     extern SsxSemaphore G_smgrModeChangeSem;
     ssx_semaphore_create(&G_smgrModeChangeSem, 1, 1);
@@ -798,8 +797,8 @@ void slave_occ_init()
     // Initialize SMGR Mode Semaphores
     extern SsxSemaphore G_smgrStateChangeSem;
     ssx_semaphore_create(&G_smgrStateChangeSem, 1, 1);
-}
 */
+}
 
 /*
  * Function Specification
@@ -978,6 +977,10 @@ void Main_thread_routine(void *private)
 
     // TEMP -- NO DCOM YET, init as OCC Master
     //dcom_initialize_roles();
+
+    // Remove the next LOC when dcom_initialize_roles() is un-commented
+    G_occ_role = OCC_MASTER;  // TEMP - @TODO
+
         // Remove the next 2 LOC when dcom_initialize_roles is un-commented
         // AND cmdh is running to call master_occ_init
         rtl_set_run_mask(RTL_FLAG_MSTR);
@@ -988,8 +991,7 @@ void Main_thread_routine(void *private)
     // Sensor Initialization
     // All Master & Slave Sensor are initialized here, it is up to the
     // rest of the firmware if it uses them or not.
-// TEMP -- NO SENSORS YET
-//    sensor_init_all();
+    sensor_init_all();
     CHECKPOINT(SENSORS_INITIALIZED);
 
     // SPIVID Initialization must be done before Pstates
@@ -1004,8 +1006,7 @@ void Main_thread_routine(void *private)
 
     // Run slave OCC init on all OCCs. Master-only initialization will be
     // done after determining actual role. By default all OCCs are slave.
-// TEMP -- SLAVES NOT SUPPORTED YET
-//    slave_occ_init();
+    slave_occ_init();
     CHECKPOINT(SLAVE_OCC_INITIALIZED);
 
     // Initialize watchdog timers. This needs to be right before
diff --git a/src/occ_405/occLinkInputFile b/src/occ_405/occLinkInputFile
index a3070a1..58fb6a6 100644
--- a/src/occ_405/occLinkInputFile
+++ b/src/occ_405/occLinkInputFile
@@ -1,54 +1,71 @@
-INPUT (
+INPUT ( amec_data.o
+        amec_freq.o
+        amec_init.o
+        amec_master_smh.o
+        amec_part.o
+        amec_sensors_fw.o
+        amec_sensors_power.o
+        amec_slave_smh.o
+        amec_tasks.o
         apss.o
         cmdh_dbug_cmd.o
-        cmdh_fsp.o
-        cmdh_fsp_cmds.o
         cmdh_fsp_cmds_datacnfg.o
+        cmdh_fsp_cmds.o
+        cmdh_fsp.o
+        cmdh_snapshot.o
         cmdh_thread.o
+        dcom.o
+        dcomMasterRx.o
+        dcomSlaveRx.o
+        dcomSlaveTx.o
         errl.o
         ffdc.o
         homer.o
         ll_ffdc.o
         main.o
+        mode.o
         occ_sys_config.o
         occbuildname.o
-        reset.o
-        rtls.o
-        rtls_tables.o
-        threadSch.o
-        thrm_thread.o
-        timer.o
-        trac_interface.o
-        scom.o
-        sensor_query_list.o
-        state.o
-        ssx_core.o
-        ssx_init.o
-        ssx_stack_init.o
-        ssx_timer_core.o
-        ssx_timer_init.o
-        ssx_thread_init.o
-        ssx_thread_core.o
-        ssx_semaphore_init.o
-        ssx_semaphore_core.o
+        occhw_async_ocb.o
+        occhw_async_pba.o
+        occhw_async.o
+        occhw_cache.o
+        occhw_id.o
         occhw_init.o
         occhw_irq_init.o
         occhw_ocb.o
         occhw_pba.o
-        occhw_id.o
-        occhw_cache.o
-        occhw_async.o
-        occhw_async_ocb.o
-        occhw_async_pba.o
-        ppc405_core.o
-        ppc405_lib_core.o
+        ppc405_boot.o
+        ppc405_breakpoint.o
         ppc405_cache_core.o
+        ppc405_cache_init.o
+        ppc405_core.o
+        ppc405_exceptions.o
         ppc405_init.o
         ppc405_irq_core.o
         ppc405_irq_init.o
-        ppc405_boot.o
-        ppc405_exceptions.o
-        ppc405_cache_init.o
+        ppc405_lib_core.o
         ppc405_mmu_asm.o
-        ppc405_breakpoint.o
-        ppc405_thread_init.o )
+        ppc405_thread_init.o
+        proc_pstate.o
+        reset.o
+        rtls_tables.o
+        rtls.o
+        scom.o
+        sensor_query_list.o
+        sensor_table.o
+        sensor.o
+        ssx_core.o
+        ssx_init.o
+        ssx_semaphore_core.o
+        ssx_semaphore_init.o
+        ssx_stack_init.o
+        ssx_thread_core.o
+        ssx_thread_init.o
+        ssx_timer_core.o
+        ssx_timer_init.o
+        state.o
+        threadSch.o
+        thrm_thread.o
+        timer.o
+        trac_interface.o)
diff --git a/src/occ_405/proc/proc_pstate.c b/src/occ_405/proc/proc_pstate.c
index 870e1b4..26704de 100755
--- a/src/occ_405/proc/proc_pstate.c
+++ b/src/occ_405/proc/proc_pstate.c
@@ -32,9 +32,9 @@
 #include "occ_common.h"
 #include "state.h"
 #include "cmdh_fsp_cmds.h"
-#include "cmdh_cbug_cmd.h"
-#include "gpsm.h"
-#include "pstates.h"
+// @TODO - TEMP Pstate include files
+//#include "gpsm.h"
+//#include "pstates.h"
 #include "proc_data.h"
 #include "proc_pstate.h"
 #include "scom.h"
@@ -56,7 +56,8 @@ typedef enum
 
 // Instance of the PState Table in OCC SRAM.  Should be placed in RO section
 // so that OCC FW can't corrupt it
-GLOBAL_PSTATE_TABLE(G_global_pstate_table);
+// @TODO - TEMP Pstates changed in P9
+//GLOBAL_PSTATE_TABLE(G_global_pstate_table);
 
 // Used for passing DCM Master & Slave States to each other over MBOX
 proc_gpsm_dcm_sync_occfw_t G_proc_dcm_sync_state = {0, PROC_GPSM_SYNC_NO_PSTATE_TABLE, PROC_GPSM_SYNC_NO_PSTATE_TABLE,0,0};
@@ -113,16 +114,17 @@ bool proc_is_hwpstate_enabled(void)
 // End Function Specification
 void proc_gpsm_dcm_sync_update_from_mbox(proc_gpsm_dcm_sync_occfw_t * i_dcm_sync_state)
 {
-    if(!gpsm_dcm_slave_p())
+// @TODO - TEMP - global state table changes in P9
+/*    if(!gpsm_dcm_slave_p())
     {
         G_proc_dcm_sync_state.sync_state_slave = i_dcm_sync_state->sync_state_slave;
     }
     else
     {
-        G_proc_dcm_sync_state.sync_state_master = i_dcm_sync_state->sync_state_master;
+*/        G_proc_dcm_sync_state.sync_state_master = i_dcm_sync_state->sync_state_master;
         G_proc_dcm_sync_state.pstate_v = i_dcm_sync_state->pstate_v;
         G_proc_dcm_sync_state.pstate_f = i_dcm_sync_state->pstate_f;
-    }
+/*    } */
 }
 
 
@@ -151,6 +153,7 @@ inline bool proc_is_dcm(void)
   return G_isDcm;
 }
 
+#if 0 // @TODO - TEMP - global state table changes in P9
 
 // Function Specification
 //
@@ -959,6 +962,8 @@ void populate_pstate_to_sapphire_tbl()
     }
 }
 
+#endif // @TODO - TEMP - global state table changes in P9
+
 // Function Specification
 //
 // Name:  populate_sapphire_tbl_to_mem
diff --git a/src/occ_405/proc/proc_pstate.h b/src/occ_405/proc/proc_pstate.h
index f775bd2..b8be793 100755
--- a/src/occ_405/proc/proc_pstate.h
+++ b/src/occ_405/proc/proc_pstate.h
@@ -103,7 +103,7 @@ extern sapphire_table_t G_sapphire_table;
 //void proc_gpsm_dcm_sync_enable_pstates_smh(void);
 
 // Get DCM Sync State
-//proc_gpsm_dcm_sync_occfw_t proc_gpsm_dcm_sync_get_state(void);
+proc_gpsm_dcm_sync_occfw_t proc_gpsm_dcm_sync_get_state(void);
 
 // Pull down DCM pair's Sync State & Info via Mbox
 void proc_gpsm_dcm_sync_update_from_mbox(proc_gpsm_dcm_sync_occfw_t * i_dcm_sync_state);
diff --git a/src/occ_405/rtls/rtls.c b/src/occ_405/rtls/rtls.c
index ae838bc..51a0bba 100755
--- a/src/occ_405/rtls/rtls.c
+++ b/src/occ_405/rtls/rtls.c
@@ -51,8 +51,7 @@ uint32_t G_run_mask_deferred = GLOBAL_RUN_MASK;
 uint32_t G_current_tick = 0xFFFFFFFF;
 
 // The durations measured within the current tick
-// TEMP -- PORE ISSUES
-//fw_timing_t G_fw_timing;
+fw_timing_t G_fw_timing;
 
 // The global TICK table
 // See notes regarding this table in rtls_tables.c.
@@ -284,8 +283,7 @@ void rtl_ocb_init(void)
 // End Function Specification
 void rtl_do_tick( void *private, SsxIrqId irq, int priority )
 {
-// TEMP / TODO  -- Unused var warning
-//    uint64_t l_start = ssx_timebase_get();
+    uint64_t l_start = ssx_timebase_get();
 
     uint8_t *l_taskid_ptr = NULL;   // Pointer to the current task ID in the current tick sequence
     task_t *l_task_ptr = NULL;      // Pointer to the currently executing task
@@ -305,8 +303,7 @@ void rtl_do_tick( void *private, SsxIrqId irq, int priority )
     CURRENT_TICK++;
 
     // Save off start time of RTL tick
-// TEMP -- COMMENTED OUT DUE TO PORE ISSUES
-//    G_fw_timing.rtl_start = l_start;
+    G_fw_timing.rtl_start = l_start;
 
     // Set global run mask point to deferred mask so that any modification
     // to the deferred mask flag is taken into effect for this tick.
@@ -390,8 +387,7 @@ void rtl_do_tick( void *private, SsxIrqId irq, int priority )
     } while(TRUE);
 
     // Save timing of RTL tick
-// TEMP -- PORE ISSUES
-//    G_fw_timing.rtl_dur = DURATION_IN_US_UNTIL_NOW_FROM(l_start);
+    G_fw_timing.rtl_dur = DURATION_IN_US_UNTIL_NOW_FROM(l_start);
 
     RTLS_DBG("RTL Tick Duration: %d us\n",(int)G_fw_timing.rtl_dur);
 
diff --git a/src/occ_405/rtls/rtls.h b/src/occ_405/rtls/rtls.h
index edd6de4..91d3e81 100755
--- a/src/occ_405/rtls/rtls.h
+++ b/src/occ_405/rtls/rtls.h
@@ -29,6 +29,7 @@
 #include <occ_common.h>
 #include <ssx.h>
 #include <ssx_app_cfg.h>
+#include "occhw_async.h"
 
 typedef struct task {
     uint32_t flags;
@@ -47,12 +48,12 @@ typedef enum {
 //    TASK_ID_DCOM_RX_INBX,
 //    TASK_ID_DCOM_TX_INBX,
     TASK_ID_POKE_WDT,                 // Reset ppc405 watchdog and OCB timer
-//    TASK_ID_DCOM_WAIT_4_MSTR,
-//    TASK_ID_DCOM_RX_OUTBX,
-//    TASK_ID_DCOM_TX_OUTBX,
+    TASK_ID_DCOM_WAIT_4_MSTR,
+    TASK_ID_DCOM_RX_OUTBX,
+    TASK_ID_DCOM_TX_OUTBX,
 //    TASK_ID_DCOM_PARSE_FW_MSG,
     TASK_ID_CHECK_FOR_CHECKSTOP,
-//    TASK_ID_AMEC_SLAVE,             // AMEC SMH tasks
+    TASK_ID_AMEC_SLAVE,             // AMEC SMH tasks
 //    TASK_ID_AMEC_MASTER,            // AMEC SMH tasks
 //    TASK_ID_CORE_DATA_CONTROL,
 //    TASK_ID_GPU_SM,                 // GPU State Machine
@@ -63,7 +64,6 @@ typedef enum {
 } task_id_t;
 
 // Structure containing the durations measured within a tick
-/* TEMP -- PoreFlex object no longer exists
 typedef struct
 {
   uint32_t rtl_dur;         // Duration of RTL tick interrupt
@@ -73,10 +73,9 @@ typedef struct
   uint64_t rtl_start;       // SsxTimebase of Start of current RTL Tick
   uint64_t rtl_start_gpe;   // SsxTimebase of Start of current RTL Tick (for GPE > 250us meas)
   uint32_t gpe_dur[2];      // Duration of the GPE Engines / tick
-  PoreFlex * gpe0_timing_request;   // GPE Request that facilitates GPE WC meas
-  PoreFlex * gpe1_timing_request;   // GPE Request that facilitates GPE WC meas
+  GpeRequest* gpe0_timing_request;   // GPE Request that facilitates GPE WC meas
+  GpeRequest* gpe1_timing_request;   // GPE Request that facilitates GPE WC meas
 } fw_timing_t;
-*/
 
 // Bit flags to define when a task can run
 // NOTE: whenever new flag is added, it must also be added to the
@@ -114,7 +113,7 @@ typedef struct
 extern uint32_t G_current_tick;
 
 // The durations measured within the current tick
-// extern fw_timing_t G_fw_timing;
+extern fw_timing_t G_fw_timing;
 
 // Preferred macro for accessing the current tick value
 #define CURRENT_TICK G_current_tick
diff --git a/src/occ_405/rtls/rtls_tables.c b/src/occ_405/rtls/rtls_tables.c
index c4dc9d3..ee48da2 100755
--- a/src/occ_405/rtls/rtls_tables.c
+++ b/src/occ_405/rtls/rtls_tables.c
@@ -107,16 +107,16 @@ task_t G_task_table[TASK_END] = {
 //    { FLAGS_DCOM_TX_SLV_INBX,      task_dcom_tx_slv_inbox,         NULL },  // TASK_ID_DCOM_TX_INBX
     { FLAGS_POKE_WDT,              task_poke_watchdogs,            NULL },  // TASK_ID_POKE_WDT
 // TEMP -- NOT SUPPORTED YET IN PHASE1
-//    { FLAGS_DCOM_WAIT_4_MSTR,      task_dcom_wait_for_master,      NULL },  // TASK_ID_DCOM_WAIT_4_MSTR
+    { FLAGS_DCOM_WAIT_4_MSTR,      task_dcom_wait_for_master,      NULL },  // TASK_ID_DCOM_WAIT_4_MSTR
 // TEMP -- NOT SUPPORTED YET IN PHASE1
-//    { FLAGS_DCOM_RX_SLV_OUTBOX,    task_dcom_rx_slv_outboxes,      NULL },  // TASK_ID_DCOM_RX_OUTBX
+    { FLAGS_DCOM_RX_SLV_OUTBOX,    task_dcom_rx_slv_outboxes,      NULL },  // TASK_ID_DCOM_RX_OUTBX
 // TEMP -- NOT SUPPORTED YET IN PHASE1
-//    { FLAGS_DCOM_TX_SLV_OUTBOX,    task_dcom_tx_slv_outbox,        NULL },  // TASK_ID_DCOM_TX_OUTBX
+    { FLAGS_DCOM_TX_SLV_OUTBOX,    task_dcom_tx_slv_outbox,        NULL },  // TASK_ID_DCOM_TX_OUTBX
 // TEMP -- NOT SUPPORTED YET IN PHASE1
 //    { FLAGS_DCOM_PARSE_OCC_FW_MSG, task_dcom_parse_occfwmsg,       NULL },  // TASK_ID_DCOM_PARSE_FW_MSG
     { FLAGS_CHECK_FOR_CHECKSTOP,   task_check_for_checkstop,       NULL },  // TASK_ID_CHECK_FOR_CHECKSTOP
 // TEMP -- NOT SUPPORTED YET IN PHASE1
-//    { FLAGS_AMEC_SLAVE,            task_amec_slave,                NULL },  // TASK_ID_AMEC_SLAVE
+    { FLAGS_AMEC_SLAVE,            task_amec_slave,                NULL },  // TASK_ID_AMEC_SLAVE
 // TEMP -- NOT SUPPORTED YET IN PHASE1
 //    { FLAGS_AMEC_MASTER,           task_amec_master,               NULL },  // TASK_ID_AMEC_MASTER
 // TEMP -- NOT SUPPORTED YET IN PHASE1
@@ -143,7 +143,7 @@ const uint8_t G_tick0_seq[] = {
                                 TASK_ID_POKE_WDT,
                                 //TASK_ID_DCOM_TX_OUTBX,
                                 //TASK_ID_DCOM_TX_INBX,
-                                //TASK_ID_AMEC_SLAVE,
+                                TASK_ID_AMEC_SLAVE,
                                 //TASK_ID_AMEC_MASTER,
                                 //TASK_ID_DCOM_PARSE_FW_MSG,
                                 //TASK_ID_CHECK_FOR_CHECKSTOP,
@@ -162,7 +162,7 @@ const uint8_t G_tick1_seq[] = {
                                 //TASK_ID_DCOM_RX_OUTBX,
                                 //TASK_ID_DCOM_TX_OUTBX,
                                 //TASK_ID_DCOM_TX_INBX,
-                                //TASK_ID_AMEC_SLAVE,
+                                TASK_ID_AMEC_SLAVE,
                                 //TASK_ID_AMEC_MASTER,
                                 //TASK_ID_DCOM_PARSE_FW_MSG,
                                 //TASK_ID_CHECK_FOR_CHECKSTOP,
@@ -181,7 +181,7 @@ const uint8_t G_tick2_seq[] = {
                                 //TASK_ID_DCOM_RX_OUTBX,
                                 //TASK_ID_DCOM_TX_OUTBX,
                                 //TASK_ID_DCOM_TX_INBX,
-                                //TASK_ID_AMEC_SLAVE,
+                                TASK_ID_AMEC_SLAVE,
                                 //TASK_ID_AMEC_MASTER,
                                 //TASK_ID_DCOM_PARSE_FW_MSG,
                                 //TASK_ID_CHECK_FOR_CHECKSTOP,
@@ -200,7 +200,7 @@ const uint8_t G_tick3_seq[] = {
                                 //TASK_ID_DCOM_RX_OUTBX,
                                 //TASK_ID_DCOM_TX_OUTBX,
                                 //TASK_ID_DCOM_TX_INBX,
-                                //TASK_ID_AMEC_SLAVE,
+                                TASK_ID_AMEC_SLAVE,
                                 //TASK_ID_AMEC_MASTER,
                                 //TASK_ID_DCOM_PARSE_FW_MSG,
                                 //TASK_ID_CHECK_FOR_CHECKSTOP,
@@ -220,7 +220,7 @@ const uint8_t G_tick4_seq[] = {
                                 TASK_ID_POKE_WDT,
                                 //TASK_ID_DCOM_TX_OUTBX,
                                 //TASK_ID_DCOM_TX_INBX,
-                                //TASK_ID_AMEC_SLAVE,
+                                TASK_ID_AMEC_SLAVE,
                                 //TASK_ID_AMEC_MASTER,
                                 //TASK_ID_DCOM_PARSE_FW_MSG,
                                 //TASK_ID_CHECK_FOR_CHECKSTOP,
@@ -239,7 +239,7 @@ const uint8_t G_tick5_seq[] = {
                                 //TASK_ID_DCOM_RX_OUTBX,
                                 //TASK_ID_DCOM_TX_OUTBX,
                                 //TASK_ID_DCOM_TX_INBX,
-                                //TASK_ID_AMEC_SLAVE,
+                                TASK_ID_AMEC_SLAVE,
                                 //TASK_ID_AMEC_MASTER,
                                 //TASK_ID_DCOM_PARSE_FW_MSG,
                                 //TASK_ID_CHECK_FOR_CHECKSTOP,
@@ -258,7 +258,7 @@ const uint8_t G_tick6_seq[] = {
                                 //TASK_ID_DCOM_RX_OUTBX,
                                 //TASK_ID_DCOM_TX_OUTBX,
                                 //TASK_ID_DCOM_TX_INBX,
-                                //TASK_ID_AMEC_SLAVE,
+                                TASK_ID_AMEC_SLAVE,
                                 //TASK_ID_AMEC_MASTER,
                                 //TASK_ID_DCOM_PARSE_FW_MSG,
                                 //TASK_ID_CHECK_FOR_CHECKSTOP,
@@ -277,7 +277,7 @@ const uint8_t G_tick7_seq[] = {
                                 //TASK_ID_DCOM_RX_OUTBX,
                                 //TASK_ID_DCOM_TX_OUTBX,
                                 //TASK_ID_DCOM_TX_INBX,
-                                //TASK_ID_AMEC_SLAVE,
+                                TASK_ID_AMEC_SLAVE,
                                 //TASK_ID_AMEC_MASTER,
                                 //TASK_ID_DCOM_PARSE_FW_MSG,
                                 //TASK_ID_CHECK_FOR_CHECKSTOP,
@@ -297,7 +297,7 @@ const uint8_t G_tick8_seq[] = {
                                 TASK_ID_POKE_WDT,
                                 //TASK_ID_DCOM_TX_OUTBX,
                                 //TASK_ID_DCOM_TX_INBX,
-                                //TASK_ID_AMEC_SLAVE,
+                                TASK_ID_AMEC_SLAVE,
                                 //TASK_ID_AMEC_MASTER,
                                 //TASK_ID_DCOM_PARSE_FW_MSG,
                                 //TASK_ID_CHECK_FOR_CHECKSTOP,
@@ -316,7 +316,7 @@ const uint8_t G_tick9_seq[] = {
                                 //TASK_ID_DCOM_RX_OUTBX,
                                 //TASK_ID_DCOM_TX_OUTBX,
                                 //TASK_ID_DCOM_TX_INBX,
-                                //TASK_ID_AMEC_SLAVE,
+                                TASK_ID_AMEC_SLAVE,
                                 //TASK_ID_AMEC_MASTER,
                                 //TASK_ID_DCOM_PARSE_FW_MSG,
                                 //TASK_ID_CHECK_FOR_CHECKSTOP,
@@ -335,7 +335,7 @@ const uint8_t G_tick10_seq[] = {
                                 //TASK_ID_DCOM_RX_OUTBX,
                                 //TASK_ID_DCOM_TX_OUTBX,
                                 //TASK_ID_DCOM_TX_INBX,
-                                //TASK_ID_AMEC_SLAVE,
+                                TASK_ID_AMEC_SLAVE,
                                 //TASK_ID_AMEC_MASTER,
                                 //TASK_ID_DCOM_PARSE_FW_MSG,
                                 //TASK_ID_CHECK_FOR_CHECKSTOP,
@@ -354,7 +354,7 @@ const uint8_t G_tick11_seq[] = {
                                 //TASK_ID_DCOM_RX_OUTBX,
                                 //TASK_ID_DCOM_TX_OUTBX,
                                 //TASK_ID_DCOM_TX_INBX,
-                                //TASK_ID_AMEC_SLAVE,
+                                TASK_ID_AMEC_SLAVE,
                                 //TASK_ID_AMEC_MASTER,
                                 //TASK_ID_DCOM_PARSE_FW_MSG,
                                 //TASK_ID_CHECK_FOR_CHECKSTOP,
@@ -374,7 +374,7 @@ const uint8_t G_tick12_seq[] = {
                                 TASK_ID_POKE_WDT,
                                 //TASK_ID_DCOM_TX_OUTBX,
                                 //TASK_ID_DCOM_TX_INBX,
-                                //TASK_ID_AMEC_SLAVE,
+                                TASK_ID_AMEC_SLAVE,
                                 //TASK_ID_AMEC_MASTER,
                                 //TASK_ID_DCOM_PARSE_FW_MSG,
                                 //TASK_ID_CHECK_FOR_CHECKSTOP,
@@ -393,7 +393,7 @@ const uint8_t G_tick13_seq[] = {
                                 //TASK_ID_DCOM_RX_OUTBX,
                                 //TASK_ID_DCOM_TX_OUTBX,
                                 //TASK_ID_DCOM_TX_INBX,
-                                //TASK_ID_AMEC_SLAVE,
+                                TASK_ID_AMEC_SLAVE,
                                 //TASK_ID_AMEC_MASTER,
                                 //TASK_ID_DCOM_PARSE_FW_MSG,
                                 //TASK_ID_CHECK_FOR_CHECKSTOP,
@@ -412,7 +412,7 @@ const uint8_t G_tick14_seq[] = {
                                 //TASK_ID_DCOM_RX_OUTBX,
                                 //TASK_ID_DCOM_TX_OUTBX,
                                 //TASK_ID_DCOM_TX_INBX,
-                                //TASK_ID_AMEC_SLAVE,
+                                TASK_ID_AMEC_SLAVE,
                                 //TASK_ID_AMEC_MASTER,
                                 //TASK_ID_DCOM_PARSE_FW_MSG,
                                 //TASK_ID_CHECK_FOR_CHECKSTOP,
@@ -431,7 +431,7 @@ const uint8_t G_tick15_seq[] = {
                                 //TASK_ID_DCOM_RX_OUTBX,
                                 //TASK_ID_DCOM_TX_OUTBX,
                                 //TASK_ID_DCOM_TX_INBX,
-                                //TASK_ID_AMEC_SLAVE,
+                                TASK_ID_AMEC_SLAVE,
                                 //TASK_ID_AMEC_MASTER,
                                 //TASK_ID_DCOM_PARSE_FW_MSG,
                                 //TASK_ID_CHECK_FOR_CHECKSTOP,
diff --git a/src/occ_405/topfiles.mk b/src/occ_405/topfiles.mk
index 920a81c..7e5fe37 100644
--- a/src/occ_405/topfiles.mk
+++ b/src/occ_405/topfiles.mk
@@ -22,33 +22,49 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
-TOP-C-SOURCES = cmdh/cmdh_dbug_cmd.c \
-                cmdh/cmdh_fsp.c \
-                cmdh/cmdh_fsp_cmds.c \
+TOP-C-SOURCES = amec/amec_data.c \
+                amec/amec_freq.c \
+                amec/amec_init.c \
+                amec/amec_master_smh.c \
+                amec/amec_part.c \
+                amec/amec_sensors_fw.c \
+                amec/amec_sensors_power.c \
+                amec/amec_slave_smh.c \
+                amec/amec_tasks.c \
+                amec/sensor_power.c \
+                cmdh/cmdh_dbug_cmd.c \
                 cmdh/cmdh_fsp_cmds_datacnfg.c \
+                cmdh/cmdh_fsp_cmds.c \
+                cmdh/cmdh_fsp.c \
                 cmdh/cmdh_mnfg_intf.c \
+                cmdh/cmdh_snapshot.c \
                 cmdh/cmdh_thread.c \
                 cmdh/cmdh_tunable_parms.c \
-                cmdh/snapshot.c \
                 cmdh/ffdc.c \
+                dcom/dcom.c \
+                dcom/dcomMasterRx.c \
+                dcom/dcomSlaveRx.c \
+                dcom/dcomSlaveTx.c \
                 errl/errl.c \
                 homer.c \
                 main.c \
+                mode.c \
                 occ_sys_config.c \
                 occbuildname.c \
+                proc/proc_pstate.c \
                 pss/apss.c \
                 reset.c \
-                rtls/rtls.c \
                 rtls/rtls_tables.c \
+                rtls/rtls.c \
                 scom.c \
-                sensor/sensor.c \
                 sensor/sensor_query_list.c \
                 sensor/sensor_table.c \
+                sensor/sensor.c \
                 state.c \
                 thread/threadSch.c \
                 thread/thrm_thread.c \
                 timer/timer.c \
-                trac/trac_interface.c \
+                trac/trac_interface.c 
 
 TOP-S-SOURCES = cmdh/ll_ffdc.S \