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author | Wael El-Essawy <welessa@us.ibm.com> | 2016-05-02 22:20:14 -0500 |
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committer | Wael El-Essawy <welessa@us.ibm.com> | 2016-05-25 16:19:23 -0400 |
commit | 6d29cab23da5bacaf0772bb8dd6265c4b442760c (patch) | |
tree | d7dee4b726108c87734bd1508abccf47d1a230e4 /src/occ_405/amec/amec_data.c | |
parent | 6f82299cb1e306dabef5bbae1a9d4e5817dbcea9 (diff) | |
download | talos-occ-6d29cab23da5bacaf0772bb8dd6265c4b442760c.tar.gz talos-occ-6d29cab23da5bacaf0772bb8dd6265c4b442760c.zip |
Pstate Infrastructure & Support config data required for active state
- Support all config data required for active state.
- Set 'active ready' bit in poll response when all config data has been received.
- Rewrite & rename proc_gpsm_pstate_initialize() - Delete GPSM, doesn't exist.
- Put in TODO call PGPE to enable pstates this will also be telling PGPE how to
set PMCR mode register (OCC control pstates or OPAL).
- Initialize globals for fmax, fmin, pmax and mhz_per_pstate with temporary hard
codes until PGPE is available.
- Call to "proc_pstate_initialize()" moved to state transition to observation
- Cleanup proc_freq2pstate()
- rewrite amec_slv_freq_smh()
- the calls to proc_set_core_bounds() and proc_set_core_pstate() will be
replaced with 1 IPC call to the PGPE to set pmin/pmax given all cores
or set pstate for all given cores.
- Remove all DCM related code.
Change-Id: I449d188b2cffc345afca19717dcbea037f159114
RTC:130224
RTC:150935
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23977
Tested-by: FSP CI Jenkins
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
Diffstat (limited to 'src/occ_405/amec/amec_data.c')
-rwxr-xr-x | src/occ_405/amec/amec_data.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/occ_405/amec/amec_data.c b/src/occ_405/amec/amec_data.c index 97aa8a7..61af8fe 100755 --- a/src/occ_405/amec/amec_data.c +++ b/src/occ_405/amec/amec_data.c @@ -64,6 +64,8 @@ // Globals //************************************************************************* extern uint8_t G_occ_interrupt_type; +extern uint32_t G_proc_fmin; +extern uint32_t G_proc_fmax; //************************************************************************* // Function Prototypes @@ -112,8 +114,8 @@ errlHndl_t AMEC_data_write_fcurr(const OCC_MODE i_mode) // min/max for AMEC component if(G_occ_interrupt_type != FSP_SUPPORTED_OCC) { - g_amec->sys.fmax = G_sysConfigData.sys_mode_freq.table[OCC_MODE_TURBO]; - g_amec->sys.fmin = G_sysConfigData.sys_mode_freq.table[OCC_MODE_MIN_FREQUENCY]; + g_amec->sys.fmax = G_proc_fmax; + g_amec->sys.fmin = G_proc_fmin; // = G_sysConfigData.sys_mode_freq.table[OCC_MODE_MIN_FREQUENCY] TRAC_INFO("AMEC_data_write_fcurr: New frequency range Fmin[%u] Fmax[%u]", g_amec->sys.fmin, |