Merge latest hcode headers into OCC

Change-Id: I1365d14bee48c287fcfd0faab8ba8a1a517e5bcb
RTC: 169886
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38107
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>

5 files changed, 848 insertions, 100 deletions

diff --git a/src/include/p9_pstates_cmeqm.h b/src/include/p9_pstates_cmeqm.h
new file mode 100644
index 0000000..f7047cb
--- /dev/null
+++ b/src/include/p9_pstates_cmeqm.h
@@ -0,0 +1,336 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/include/p9_pstates_cmeqm.h $                              */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/// @file  p9_pstates_cmeqm.h
+/// @brief Pstate structures and support routines for CME Hcode
+///
+// *HWP HW Owner        : Rahul Batra <rbatra@us.ibm.com>
+// *HWP HW Owner        : Michael Floyd <mfloyd@us.ibm.com>
+// *HWP Team            : PM
+// *HWP Level           : 1
+// *HWP Consumed by     : CME:PGPE
+
+#ifndef __P9_PSTATES_CME_H__
+#define __P9_PSTATES_CME_H__
+
+#include <p9_pstates_common.h>
+
+/// \defgroup QM Flags
+///
+/// These are flag bits for the \a Quad Manager field.
+///
+/// @{
+
+/// qmflag() - Disable Resonant Clock use.
+#define PSTATE_RESCLK_DISABLE               0x8000
+
+/// qmflag() - Disable IVRM use.
+#define PSTATE_IVRMS_DISABLE                0x4000
+
+/// qmflag() - Disable VDM use.
+#define PSTATE_VDM_DISABLE                  0x2000
+
+/// qmflag() - Disable WOF.
+#define PSTATE_WOF_DISABLE                  0x1000
+
+/// qmflag() - dpll_dynamic_fmax_enable
+#define PSTATE_DPLL_DYNAMIC_FMAX_ENABLE     0x0800
+
+/// qmflag() - dpll_dynamic_fmin_enable
+#define PSTATE_DPLL_DYNAMIC_FMIN_ENABLE     0x0400
+
+/// qmflag() - dpll_droop_protect_enable
+#define PSTATE_DPLL_DROOP_PROTECT_ENABLE    0x0200
+
+/// @}
+
+#ifndef __ASSEMBLER__
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/// LocalParmsBlock Magic Number
+///
+/// This magic number identifies a particular version of the
+/// PstateParmsBlock and its substructures.  The version number should be
+/// kept up to date as changes are made to the layout or contents of the
+/// structure.
+
+#define LOCAL_PARMSBLOCK_MAGIC 0x434d455050423030ull /* CMEPPB00 */
+
+/// Quad Manager Flags
+///
+
+typedef union
+{
+    uint16_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint16_t    resclk_enable               : 1;
+        uint16_t    ivrm_enable                 : 1;
+        uint16_t    wof_enable                  : 1;
+        uint16_t    dpll_dynamic_fmax_enable    : 1;
+        uint16_t    dpll_dynamic_fmin_enable    : 1;
+        uint16_t    dpll_droop_protect_enable   : 1;
+        uint16_t    reserved                    : 10;
+#else
+        uint16_t    reserved                    : 10;
+        uint16_t    dpll_droop_protect_enable   : 1;
+        uint16_t    dpll_dynamic_fmin_enable    : 1;
+        uint16_t    dpll_dynamic_fmax_enable    : 1;
+        uint16_t    wof_enable                  : 1;
+        uint16_t    ivrm_enable                 : 1;
+        uint16_t    resclk_enable               : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+
+} QuadManagerFlags;
+
+/// Resonant Clock Stepping Entry
+///
+typedef union
+{
+    uint16_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint16_t    sector_buffer   : 4;
+        uint16_t    spare1          : 1;
+        uint16_t    pulse_enable    : 1;
+        uint16_t    pulse_mode      : 2;
+        uint16_t    resonant_switch : 4;
+        uint16_t    spare4          : 4;
+#else
+        uint16_t    spare4          : 4;
+        uint16_t    resonant_switch : 4;
+        uint16_t    pulse_mode      : 2;
+        uint16_t    pulse_enable    : 1;
+        uint16_t    spare1          : 1;
+        uint16_t    sector_buffer   : 4;
+#endif // _BIG_ENDIAN
+    } fields;
+
+} ResonantClockingStepEntry;
+
+#define RESCLK_FREQ_REGIONS 8
+#define RESCLK_STEPS        64
+#define RESCLK_L3_STEPS     4
+
+typedef struct ResonantClockControl
+{
+    uint8_t resclk_freq[RESCLK_FREQ_REGIONS];    // Lower frequency of Resclk Regions
+
+    uint8_t resclk_index[RESCLK_FREQ_REGIONS];   // Index into value array for the
+    // respective Resclk Region
+
+    /// Array containing the transition steps
+    ResonantClockingStepEntry steparray[RESCLK_STEPS];
+
+    /// Delay between steps (in nanoseconds)
+    /// Maximum delay: 65.536us
+    uint16_t    step_delay_ns;
+
+    /// L3 Clock Stepping Array
+    uint8_t     l3_steparray[RESCLK_L3_STEPS];
+
+    /// Resonant Clock Voltage Threshold (in millivolts)
+    /// This value is used to choose the appropriate L3 clock region setting.
+    uint16_t l3_threshold_mv;
+
+} ResonantClockingSetup;
+
+// #W data points (version 2)
+typedef struct
+{
+    uint16_t ivdd_tdp_ac_current_10ma;
+    uint16_t ivdd_tdp_dc_current_10ma;
+    uint8_t  vdm_overvold_small_thresholds;
+    uint8_t  vdm_large_extreme_thresholds;
+    uint8_t  vdm_small_frequency_drop;
+    uint8_t  vdm_large_frequency_drop;
+    uint16_t vdm_spare;
+} poundw_entry_t;
+
+typedef struct
+{
+    uint16_t r_package_common;
+    uint16_t r_quad;
+    uint16_t r_core;
+    uint16_t r_quad_header;
+    uint16_t r_core_header;
+} resistance_entry_t;
+
+typedef struct
+{
+    poundw_entry_t poundw_nominal;
+    poundw_entry_t poundw_powersave;
+    poundw_entry_t poundw_turbo;
+    poundw_entry_t poundw_ultraturbo;
+    resistance_entry_t resistance_data;
+    uint64_t reserved1;
+    uint16_t reserved2;
+} PoundW_data;
+/// VDM/Droop Parameter Block
+///
+typedef struct
+{
+    uint8_t  vid_compare_override_mv_enable;
+    uint8_t  vid_compare_override_mv[VPD_PV_POINTS];
+    uint8_t  vdm_response;
+
+    // For the following *_enable fields, bits are defined to indicate
+    // which of the respective *override* array entries are valid.
+    // bit 0: UltraTurbo; bit 1: Turbo; bit 2: Nominal; bit 3: PowSave
+    uint8_t  droop_small_override_enable;
+    uint8_t  droop_large_override_enable;
+    uint8_t  droop_extreme_override_enable;
+    uint8_t  overvolt_override_enable;
+    uint16_t fmin_override_khz_enable;
+    uint16_t fmax_override_khz_enable;
+
+    // The respecitve *_enable above indicate which index values are valid
+    uint8_t  droop_small_override[VPD_PV_POINTS];
+    uint8_t  droop_large_override[VPD_PV_POINTS];
+    uint8_t  droop_extreme_override[VPD_PV_POINTS];
+    uint8_t  overvolt_override[VPD_PV_POINTS];
+    uint16_t fmin_override_khz[VPD_PV_POINTS];
+    uint16_t fmax_override_khz[VPD_PV_POINTS];
+
+    /// Pad structure to 8-byte alignment
+    /// @todo pad once fully structure is complete.
+    // uint8_t pad[1];
+
+} VDMParmBlock;
+
+
+/// The layout of the data created by the Pstate table creation firmware for
+/// comsumption by the Pstate GPE.  This data will reside in the Quad
+/// Power Management Region (QPMR).
+///
+
+/// Standard options controlling Pstate setup procedures
+
+/// System Power Distribution Paramenters
+///
+/// Parameters set by system design that influence the power distribution
+/// for a rail to the processor module.  This values are typically set in the
+/// system machine readable workbook and are used in the generation of the
+/// Global Pstate Table.  This values are carried in the Pstate SuperStructure
+/// for use and/or reference by OCC firmware (eg the WOF algorithm)
+
+
+/// IVRM Parameter Block
+///
+/// @todo Major work item.  Largely will seed the CME Quad Manager to perform
+/// iVRM voltage calculations
+
+#define IVRM_ARRAY_SIZE 64
+typedef struct iVRMInfo
+{
+
+    /// Pwidth from 0.03125 to 1.96875 in 1/32 increments at Vin=Vin_Max
+    uint8_t strength_lookup[IVRM_ARRAY_SIZE];   // Each entry is a six bit value, right justified
+
+    /// Scaling factor for the Vin_Adder calculation.
+    uint8_t vin_multiplier[IVRM_ARRAY_SIZE];     // Each entry is from 0 to 255.
+
+    /// Vin_Max used in Vin_Adder calculation (in millivolts)
+    uint16_t    vin_max_mv;
+
+    /// Delay between steps (in nanoseconds)
+    /// Maximum delay: 65.536us
+    uint16_t    step_delay_ns;
+
+    /// Stabilization delay once target voltage has been reached (in nanoseconds)
+    /// Maximum delay: 65.536us
+    uint16_t    stablization_delay_ns;
+
+    /// Deadzone (in millivolts)
+    /// Maximum: 255mV.  If this value is 0, 50mV is assumed.
+    uint8_t    deadzone_mv;
+
+    /// Pad to 8B
+    uint8_t    pad;
+
+} IvrmParmBlock;
+
+
+/// The layout of the data created by the Pstate table creation firmware for
+/// comsumption by the CME Quad Manager.  This data will reside in the Core
+/// Power Management Region (CPMR).
+///
+typedef struct
+{
+
+    /// Magic Number
+    uint64_t magic;     // the last byte of this number the structure's version.
+
+    // QM Flags
+    QuadManagerFlags qmflags;
+
+    /// Operating points
+    ///
+    /// VPD operating points are stored without load-line correction.  Frequencies
+    /// are in MHz, voltages are specified in units of 5mV, and currents are
+    /// in units of 500mA.
+    VpdOperatingPoint operating_points[VPD_PV_POINTS];
+
+    /// Loadlines and Distribution values for the VDD rail
+    SysPowerDistParms vdd_sysparm;
+
+    /// External Biases
+    ///
+    /// Biases applied to the VPD operating points prior to load-line correction
+    /// in setting the external voltages.  This is used to recompute the Vin voltage
+    /// based on the Global Actual Pstate .
+    /// Values in 0.5%
+    VpdBias ext_biases[VPD_PV_POINTS];
+
+    /// Internal Biases
+    ///
+    /// Biases applied to the VPD operating points that are used for interpolation
+    /// in setting the internal voltages (eg Vout to the iVRMs) as part of the
+    /// Local Actual Pstate.
+    /// Values in 0.5%
+    VpdBias int_biases[VPD_PV_POINTS];
+
+    /// IVRM Data
+    IvrmParmBlock ivrm;
+
+    /// Resonant Clock Grid Management Setup
+    ResonantClockingSetup resclk;
+
+    /// VDM Data
+    VDMParmBlock vdm;
+
+} LocalPstateParmBlock;
+
+#ifdef __cplusplus
+} // end extern C
+#endif
+#endif    /* __ASSEMBLER__ */
+#endif    /* __P9_PSTATES_CME_H__ */
diff --git a/src/include/p9_pstates_common.h b/src/include/p9_pstates_common.h
index 4ccabc3..003021c 100644
--- a/src/include/p9_pstates_common.h
+++ b/src/include/p9_pstates_common.h
@@ -35,13 +35,13 @@
 #ifndef __P9_PSTATES_COMMON_H__
 #define __P9_PSTATES_COMMON_H__
 
-/// The minimum Pstate (knowing the increasing Pstates numbers represent
+/// The maximum Pstate (knowing the increasing Pstates numbers represent
 /// decreasing frequency)
-#define PSTATE_MIN 255
+#define PSTATE_MAX 255
 
-/// The maximum Pstate (knowing the increasing Pstates numbers represent
+/// The minimum Pstate (knowing the increasing Pstates numbers represent
 /// decreasing frequency)
-#define PSTATE_MAX 0
+#define PSTATE_MIN 0
 
 /// The minimum \e legal DPLL frequency code
 ///
@@ -83,35 +83,65 @@
 #define IVID_STEP_UV 4000
 
 /// Maximum number of Quads (4 cores plus associated caches)
-#define MAX_QUADS 6
+#define MAXIMUM_QUADS 6
 
 // Constants associated with VRM stepping
 // @todo Determine what is needed here (eg Attribute mapping) and if any constants
 // are warrented
 
-/// VPD #V Operating Points
+/// VPD #V Data from keyword (eg VPD order)
 #define VPD_PV_POINTS 4
-#define VPD_PV_ORDER_STR {"PowerSave ", "Nominal   ", "Turbo     ", "UltraTurbo"}
-#define POWERSAVE   1
-#define NOMINAL     0
+#define VPD_PV_POWERSAVE   1
+#define VPD_PV_NOMINAL     0
+#define VPD_PV_TURBO       2
+#define VPD_PV_ULTRA       3
+#define VPD_PV_ORDER {VPD_PV_POWERSAVE, VPD_PV_NOMINAL, VPD_PV_TURBO, VPD_PV_ULTRA}
+#define VPD_PV_ORDER_STR {"Nominal   ","PowerSave ", "Turbo     ", "UltraTurbo"}
+
+/// VPD #V Operating Points (eg Natureal order)
+#define POWERSAVE   0
+#define NOMINAL     1
 #define TURBO       2
 #define ULTRA       3
 #define POWERBUS    4
-#define VPD_PV_ORDER {POWERSAVE, NOMINAL, TURBO, ULTRA}
+#define PV_OP_ORDER {POWERSAVE, NOMINAL, TURBO, ULTRA}
+#define PV_OP_ORDER_STR {"PowerSave ", "Nominal   ","Turbo     ", "UltraTurbo"}
+
+#define VPD_PV_CORE_FREQ_MHZ    0
+#define VPD_PV_VDD_MV           1
+#define VPD_PV_IDD_100MA        2
+#define VPD_PV_VCS_MV           3
+#define VPD_PV_ICS_100MA        4
+#define VPD_PV_PB_FREQ_MHZ      0
+#define VPD_PV_VDN_MV           1
+#define VPD_PV_IDN_100MA        2
+
 #define VPD_NUM_SLOPES_SET  2
 #define VPD_SLOPES_RAW      0
 #define VPD_SLOPES_BIASED   1
 #define VPD_NUM_SLOPES_REGION       3
-#define REGION_POWERSAVE_NOMINAL    1
-#define REGION_NOMINAL_TURBO        0
+#define REGION_POWERSAVE_NOMINAL    0
+#define REGION_NOMINAL_TURBO        1
 #define REGION_TURBO_ULTRA          2
 
+// Different points considered for calculating slopes
+#define NUM_VPD_PTS_SET             4
+#define VPD_PT_SET_RAW              0
+#define VPD_PT_SET_SYSP             1
+#define VPD_PT_SET_BIASED           2
+#define VPD_PT_SET_BIASED_SYSP      3
+#define VPD_PT_SET_ORDER {VPD_PT_SET_RAW, VPD_PT_SET_SYSP, VPD_PT_SET_BIASED, VPD_PT_SET_BIASED_SYSP}
+#define VPD_PT_SET_ORDER_STR {"Raw          ", "SysParam       ","Biased        ", "Biased/SysParam"}
+
+#define EVID_SLOPE_FP_SHIFT         13
+
 
 /// IDDQ readings,
 #define IDDQ_MEASUREMENTS 6
 #define MEASUREMENT_ELEMENTS  6    // Number of Quads for P9
 #define IDDQ_READINGS_PER_IQ 2
-#define IDDQ_ARRAY_VOLTAGES {0.60, 0.70, 0.80, 0.90, 1.00, 1.10}
+#define IDDQ_ARRAY_VOLTAGES     { 0.60 ,  0.70 ,  0.80 ,  0.90 ,  1.00 ,  1.10}
+#define IDDQ_ARRAY_VOLTAGES_STR {"0.60", "0.70", "0.80", "0.90", "1.00", "1.10"}
 
 /// WOF Items
 #define NUM_ACTIVE_CORES 24
@@ -151,6 +181,7 @@
 #define LPST_GPST_WARNING        0x00477902
 #define LPST_INCR_CLIP_ERROR     0x00477903
 
+#ifndef __ASSEMBLER__
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -179,15 +210,13 @@ typedef uint16_t VidAVS;
 ///
 typedef struct
 {
-
     uint32_t vdd_mv;
     uint32_t vcs_mv;
     uint32_t idd_100ma;
     uint32_t ics_100ma;
     uint32_t frequency_mhz;
     uint8_t  pstate;        // Pstate of this VpdOperating
-    uint8_t  pad[3];
-
+    uint8_t  pad[3];        // Alignment padding
 } VpdOperatingPoint;
 
 /// VPD Biases.
@@ -234,77 +263,147 @@ typedef struct
 
 } SysPowerDistParms;
 
+
+//
+// WOF Voltage, Frequency Ratio Tables
 //
-/// UltraTurbo Segment VIDs by Core Count
+
+// VFRT Header
+
 typedef struct
 {
 
-    /// Number of Segment Pstates
-    uint8_t     ut_segment_pstates;
+    /// Magic Number
+    ///   Set to ASCII  "VT"
+    uint16_t magic_number;
+
+    /// Indicator
+    ///   Space for generation tools to be anything unique necessary to ID this
+    ///    VFRT
+    uint16_t indicator;
+
+    union
+    {
+        uint8_t value;
+        struct
+        {
+            uint8_t type    : 4;
+            uint8_t version : 4;
+        } fields;
+    } typever;
+
+    uint8_t reserved;
+
+    union
+    {
+        uint16_t value;
+        struct
+        {
+#ifdef _BIG_ENDIAN
+            uint16_t reserved: 4;
+            uint16_t vdn_id  : 4;
+            uint16_t vdd_id  : 4;
+            uint16_t qa_id   : 4;
+#else
+            uint16_t qa_id   : 4;
+            uint16_t vdd_id  : 4;
+            uint16_t vdn_id  : 4;
+            uint16_t reserved: 4;
+#endif // _BIG_ENDIAN
+
+        } fields;
+    } ids;
+
+} VFRTHeader_t;
+
+// WOF Tables Header
 
-    /// Maximum number of core possibly active
-    uint8_t     ut_max_cores;
+typedef struct
+{
 
-    /// VDD VID modification
-    ///      1 core active  = offset 0
-    ///      2 cores active = offset 1
-    ///         ...
-    ///      12 cores active = offset 11
-    uint8_t ut_segment_vdd_vid[MAX_UT_PSTATES][NUM_ACTIVE_CORES];
+    /// Magic Number
+    ///   Set to ASCII  "VFRT___x" where x is the version of the VFRT structure
+    uint64_t magic_number;
 
-    /// VCS VID modification
-    ///      1 core active  = offset 0
-    ///      2 cores active = offset 1
-    ///         ...
-    ///      12 cores active = offset 11
-    uint8_t ut_segment_vcs_vid[MAX_UT_PSTATES][NUM_ACTIVE_CORES];
+    /// VFRT Size
+    ///    Length, in bytes, of a VFRT
+    uint8_t vfrt_size;
 
-} VIDModificationTable;
+    /// VFRT Data Size
+    ///    Length, in bytes, of the data field.
+    uint8_t vfrt_data_size;
 
-/// Workload Optimized Frequency (WOF) Elements
-///
-/// Structure defining various control elements needed by the WOF algorithm
-/// firmware running on the OCC.
-///
-typedef struct
-{
+    uint8_t reserved;
 
-    /// WOF Enablement
-    uint8_t wof_enabled;
+    /// Quad Active Size
+    ///    Total number of Active Quads
+    uint8_t quads_active_size;
 
-    /// TDP<>RDP Current Factor
-    ///   Value read from ??? VPD
-    ///   Defines the scaling factor that converts current (amperage) value from
-    ///   the Thermal Design Point to the Regulator Design Point (RDP) as input
-    ///   to the Workload Optimization Frequency (WOF) OCC algorithm.
-    ///
-    ///   This is a ratio value and has a granularity of 0.01 decimal.  Data
-    ///   is held in hexidecimal (eg 1.22 is represented as 122 and then converted
-    ///   to hex 0x7A).
-    uint32_t tdp_rdp_factor;
+    /// Ceff Vdn Start
+    ///    CeffVdn value represented by index 0 (in percent)
+    uint8_t vdn_start;
 
-    /// UltraTurbo Segment VIDs by Core Count
-    VIDModificationTable ut_vid_mod;
+    /// Ceff Vdn Step
+    ///    CeffVdn step value for each CeffVdn index (in percent)
+    uint8_t vdn_step;
 
-    uint8_t pad[4];
+    /// Ceff Vdn Size
+    ///    Number of CeffVdn indexes
+    uint8_t vdn_size;
 
-} WOFElements;
+    /// Ceff Vdd Start
+    ///    CeffVdd value represented by index 0 (in percent)
+    uint8_t vdd_start;
+
+    /// Ceff Vdd Step
+    ///    CeffVdd step value for each CeffVdd index (in percent)
+    uint8_t vdd_step;
+
+    /// Ceff Vdd Size
+    ///    Number of CeffVdd indexes
+    uint8_t vdd_size;
+
+    /// Vratio Start
+    ///    Vratio value represented by index 0 (in percent)
+    uint8_t vratio_start;
+
+    /// Vratio Step
+    ///   Vratio step value for each CeffVdd index (in percent)
+    uint8_t vratio_step;
+
+    /// Vratio Size
+    ///    Number of Vratio indexes
+    uint8_t vratio_size;
+
+    /// Fratio Start
+    ///    Fratio value represented by index 0 (in percent)
+    uint8_t fratio_start;
+
+    /// Fratio Step
+    ///   Fratio step value for each CeffVdd index (in percent)
+    uint8_t fratio_step;
+
+    /// Fratio Size
+    ///    Number of Fratio indexes
+    uint8_t fratio_size;
+
+} WofTablesHeader_t;
 
-//
-// WOF Voltage, Frequency Ratio Tables
-//
 
 // VDN
 
 // Data is provided in 12ths (eg 12 core pairs on a 24 core chip)
 #define VFRT_VRATIO_SIZE 12
 
-// 100%/10% steps + 1 (for 0)
-#define VFRT_FRATIO_SIZE 11
+// 100%/10% steps
+#define VFRT_FRATIO_SIZE 10
 
-typedef uint16_t VFRT_Circuit_t;   // Holds a frequency in MHz
+// Holds a frequency that is 1000MHz + 16.667*VFRT_Circuit_t
+typedef uint8_t VFRT_Circuit_t;
 typedef Pstate   VFRT_Hcode_t;
 
+
+
 extern VFRT_Circuit_t VFRTCircuitTable[VFRT_FRATIO_SIZE][VFRT_FRATIO_SIZE];
 
 extern VFRT_Hcode_t   VFRTInputTable[VFRT_FRATIO_SIZE][VFRT_FRATIO_SIZE];
@@ -313,5 +412,5 @@ extern VFRT_Hcode_t   VFRTInputTable[VFRT_FRATIO_SIZE][VFRT_FRATIO_SIZE];
 #ifdef __cplusplus
 } // end extern C
 #endif
-
+#endif    /* __ASSEMBLER__ */
 #endif    /* __P9_PSTATES_COMMON_H__ */
diff --git a/src/include/p9_pstates_occ.h b/src/include/p9_pstates_occ.h
index e69e500..26b97eb 100644
--- a/src/include/p9_pstates_occ.h
+++ b/src/include/p9_pstates_occ.h
@@ -36,11 +36,22 @@
 #define __P9_PSTATES_OCC_H__
 
 #include <p9_pstates_common.h>
+#include <p9_pstates_pgpe.h>
 
+#ifndef __ASSEMBLER__
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+/// PstateParmsBlock Magic Number
+///
+/// This magic number identifies a particular version of the
+/// PstateParmsBlock and its substructures.  The version number should be
+/// kept up to date as changes are made to the layout or contents of the
+/// structure.
+
+#define OCC_PARMSBLOCK_MAGIC 0x4f43435050423030ull /* OCCPPB00 */
+
 /// IDDQ Reading Type
 /// Each entry is 2 bytes. The values are in 6.25mA units; this allow for a
 /// maximum value of 409.6A to be represented.
@@ -51,7 +62,7 @@ typedef uint16_t iddq_entry_t;
 /// Each entry is 1 byte. The values are in 0.5degC units; this allow for a
 /// maximum value of 127degC to be represented.
 ///
-typedef uint16_t avgtemp_entry_t;
+typedef uint8_t avgtemp_entry_t;
 
 /// Iddq Table
 ///
@@ -76,10 +87,10 @@ typedef struct
     uint8_t     good_caches_per_sort;
 
     /// Good Normal Cores
-    uint8_t     good_normal_cores[MAX_QUADS];
+    uint8_t     good_normal_cores[MAXIMUM_QUADS];
 
     /// Good Caches
-    uint8_t     good_caches[MAX_QUADS];
+    uint8_t     good_caches[MAXIMUM_QUADS];
 
     /// RDP to TDP Scaling Factor in 0.01% units
     uint16_t    rdp_to_tdp_scale_factor;
@@ -103,10 +114,10 @@ typedef struct
     iddq_entry_t ivdd_all_good_cores_off_good_caches_on[IDDQ_MEASUREMENTS];
 
     /// IVDD Quad 0 Good Cores ON, Caches ON; 6.25mA units
-    iddq_entry_t ivdd_quad_good_cores_on_good_caches_on[MAX_QUADS][IDDQ_MEASUREMENTS];
+    iddq_entry_t ivdd_quad_good_cores_on_good_caches_on[MAXIMUM_QUADS][IDDQ_MEASUREMENTS];
 
-    /// IVDDN ; 6.25mA units
-    iddq_entry_t ivdn;
+    /// IVDDN  6.25mA units
+    iddq_entry_t ivdn[IDDQ_MEASUREMENTS];
 
 
     /// IVDD ALL Good Cores ON, Caches ON; 6.25mA units
@@ -119,11 +130,14 @@ typedef struct
     avgtemp_entry_t avgtemp_all_good_cores_off[IDDQ_MEASUREMENTS];
 
     /// avgtemp Quad 0 Good Cores ON, Caches ON; 6.25mA units
-    avgtemp_entry_t avgtemp_quad_good_cores_on[MAX_QUADS][IDDQ_MEASUREMENTS];
+    avgtemp_entry_t avgtemp_quad_good_cores_on[MAXIMUM_QUADS][IDDQ_MEASUREMENTS];
 
     /// avgtempN ; 6.25mA units
     avgtemp_entry_t avgtemp_vdn;
 
+    /// spare (per MVPD documentation
+    uint8_t spare_1[43];
+
 } IddqTable;
 
 
@@ -132,6 +146,9 @@ typedef struct
 /// comsumption by the OCC firmware.  This data will reside in the Quad
 /// Power Management Region (QPMR).
 ///
+/// This structure is aligned to 128B to allow for easy downloading using the
+/// OCC block copy engine
+///
 typedef struct
 {
 
@@ -168,13 +185,12 @@ typedef struct
     // Minimum Pstate;  Maximum is always 0.
     uint32_t pstate_min;    // Comes from PowerSave #V point after biases
 
-    // TODO: Temporary hack untill interface is finalized.
-    uint8_t pad[88];               // total size = 0xE00, devisible by 128
-} OCCPstateParmBlock;
-
+    /// Nest frequency in Mhz. This is used by FIT interrupt
+    uint32_t nest_frequency_mhz;
+} __attribute__((aligned(128))) OCCPstateParmBlock;
 
 #ifdef __cplusplus
 } // end extern C
 #endif
-
+#endif    /* __ASSEMBLER__ */
 #endif    /* __P9_PSTATES_OCC_H__ */
diff --git a/src/include/p9_pstates_pgpe.h b/src/include/p9_pstates_pgpe.h
new file mode 100644
index 0000000..f523328
--- /dev/null
+++ b/src/include/p9_pstates_pgpe.h
@@ -0,0 +1,256 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/include/p9_pstates_pgpe.h $                               */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/// @file  p9_pstates_pgpe.h
+/// @brief Pstate structures and support routines for PGPE Hcode
+///
+// *HWP HW Owner        : Rahul Batra <rbatra@us.ibm.com>
+// *HWP HW Owner        : Michael Floyd <mfloyd@us.ibm.com>
+// *HWP Team            : PM
+// *HWP Level           : 1
+// *HWP Consumed by     : PGPE:HS
+
+
+#ifndef __P9_PSTATES_PGPE_H__
+#define __P9_PSTATES_PGPE_H__
+
+#include <p9_pstates_common.h>
+#include <p9_pstates_cmeqm.h>
+
+/// PstateParmsBlock Magic Number
+///
+/// This magic number identifies a particular version of the
+/// PstateParmsBlock and its substructures.  The version number should be
+/// kept up to date as changes are made to the layout or contents of the
+/// structure.
+
+#define PSTATE_PARMSBLOCK_MAGIC 0x5053544154453030ull /* PSTATE00 */
+
+#ifndef __ASSEMBLER__
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+/// Standard options controlling Pstate setup and installation procedures
+typedef struct
+{
+
+    /// Option flags; See \ref pstate_options
+    uint32_t options;
+
+    /// Pad structure to 8 bytes.  Could also be used for other options later.
+    uint32_t pad;
+
+} PGPEOptions;
+
+/// UltraTurbo Segment VIDs by Core Count
+typedef struct
+{
+
+    /// Number of Segment Pstates
+    uint8_t     ut_segment_pstates;
+
+    /// Maximum number of core possibly active
+    uint8_t     ut_max_cores;
+
+    /// VDD VID modification
+    ///      1 core active  = offset 0
+    ///      2 cores active = offset 1
+    ///         ...
+    ///      12 cores active = offset 11
+    uint8_t ut_segment_vdd_vid[MAX_UT_PSTATES][NUM_ACTIVE_CORES];
+
+    /// VCS VID modification
+    ///      1 core active  = offset 0
+    ///      2 cores active = offset 1
+    ///         ...
+    ///      12 cores active = offset 11
+    uint8_t ut_segment_vcs_vid[MAX_UT_PSTATES][NUM_ACTIVE_CORES];
+
+} VIDModificationTable;
+
+/// Workload Optimized Frequency (WOF) Elements
+///
+/// Structure defining various control elements needed by the WOF algorithm
+/// firmware running on the OCC.
+///
+typedef struct
+{
+
+    /// WOF Enablement
+    uint8_t wof_enabled;
+
+    /// TDP<>RDP Current Factor
+    ///   Value read from ??? VPD
+    ///   Defines the scaling factor that converts current (amperage) value from
+    ///   the Thermal Design Point to the Regulator Design Point (RDP) as input
+    ///   to the Workload Optimization Frequency (WOF) OCC algorithm.
+    ///
+    ///   This is a ratio value and has a granularity of 0.01 decimal.  Data
+    ///   is held in hexidecimal (eg 1.22 is represented as 122 and then converted
+    ///   to hex 0x7A).
+    uint32_t tdp_rdp_factor;
+
+    /// UltraTurbo Segment VIDs by Core Count
+    VIDModificationTable ut_vid_mod;
+
+} WOFElements;
+
+
+/// Global Pstate Parameter Block
+///
+/// The GlobalPstateParameterBlock is an abstraction of a set of voltage/frequency
+/// operating points along with hardware limits.  Besides the hardware global
+/// Pstate table, the abstract table contains enough extra information to make
+/// it the self-contained source for setting up and managing voltage and
+/// frequency in either Hardware or Firmware Pstate mode.
+///
+/// When installed in PMC, Global Pstate table indices are adjusted such that
+/// the defined Pstates begin with table entry 0. The table need not be full -
+/// the \a pmin and \a entries fields define the minimum and maximum Pstates
+/// represented in the table.  However at least 1 entry must be defined to
+/// create a legal table.
+///
+/// Note that Global Pstate table structures to be mapped into PMC hardware
+/// must be 1KB-aligned.  This requirement is fullfilled by ensuring that
+/// instances of this structure are 1KB-aligned.
+typedef struct
+{
+
+
+    /// Magic Number
+    uint64_t magic;     // the last byte of this number the structure's version.
+
+    /// Pstate options
+    ///
+    /// The options are included as part of the GlobalPstateTable so that they
+    /// are available to upon PGPE initialization.
+    PGPEOptions options;
+
+    /// The frequency associated with Pstate[0] in KHz
+    uint32_t reference_frequency_khz;
+
+    /// The frequency step in KHz
+    uint32_t frequency_step_khz;
+
+    /// Operating points
+    ///
+    /// VPD operating points are stored without load-line correction.  Frequencies
+    /// are in MHz, voltages are specified in units of 5mV, and currents are
+    /// in units of 500mA.
+    VpdOperatingPoint operating_points[VPD_PV_POINTS];
+
+    /// Biases
+    ///
+    /// Biases applied to the VPD operating points prior to load-line correction
+    /// in setting the external voltages.
+    /// Values in 0.5%
+    VpdBias ext_biases[VPD_PV_POINTS];
+
+    /// Loadlines and Distribution values for the VDD rail
+    SysPowerDistParms vdd_sysparm;
+
+    /// Loadlines and Distribution values for the VCS rail
+    SysPowerDistParms vcs_sysparm;
+
+    /// Loadlines and Distribution values for the VDN rail
+    SysPowerDistParms vdn_sysparm;
+
+    /// The "Safe" Voltage
+    ///
+    /// A voltage to be used when safe-mode is activated
+    /// @todo Need to detail this out yet.
+    uint32_t safe_voltage_mv;
+
+    /// The "Safe" Frequency
+    ///
+    /// A voltage to be used when safe-mode is activated
+    /// @todo Need to detail this out yet.
+    uint32_t safe_frequency_khz;
+
+    /// The exponent of the exponential encoding of Pstate stepping delay
+    uint8_t vrm_stepdelay_range;
+
+    /// The significand of the exponential encoding of Pstate stepping delay
+    uint8_t vrm_stepdelay_value;
+
+    /// VDM Data
+    VDMParmBlock vdm;
+
+    /// The following are needed to generated the Pstate Table to HOMER.
+
+    /// Internal Biases
+    ///
+    /// Biases applied to the VPD operating points that are used for interpolation
+    /// in setting the internal voltages (eg Vout to the iVRMs) as part of the
+    /// Local Actual Pstate.
+    /// Values in 0.5%
+    VpdBias int_biases[VPD_PV_POINTS];
+
+    /// IVRM Data
+    IvrmParmBlock ivrm;
+
+    /// Resonant Clock Grid Management Setup
+    ResonantClockingSetup resclk;
+
+    /// Time b/w ext VRM detects write voltage cmd and when voltage begins to move
+    uint32_t ext_vrm_transition_start_ns;
+
+    /// Transition rate for an increasing VDD voltage excursion
+    uint32_t ext_vrm_transition_rate_inc_uv_per_us;
+
+    /// Transition rate for an decreasing VDD voltage excursion
+    uint32_t ext_vrm_transition_rate_dec_uv_per_us;
+
+    /// Delay to account for VDD rail setting
+    uint32_t ext_vrm_stabilization_time_us;
+
+    /// External VRM transition step size
+    uint32_t ext_vrm_step_size_mv;
+
+    /// Nest frequency in Mhz. This is used by FIT interrupt
+    uint32_t nest_frequency_mhz;
+
+    /// Precalculated Pstate-Voltage Slopes
+    uint16_t PsVSlopes[VPD_NUM_SLOPES_SET][VPD_NUM_SLOPES_REGION];
+
+    /// Precalculated Voltage-Pstates Slopes
+    uint16_t VPsSlopes[VPD_NUM_SLOPES_SET][VPD_NUM_SLOPES_REGION];
+
+    /// All operating points
+    VpdOperatingPoint operating_points_set[NUM_VPD_PTS_SET][VPD_PV_POINTS];
+
+    // @todo DPLL Droop Settings.  These need communication to SGPE for STOP
+
+} GlobalPstateParmBlock;
+
+
+#ifdef __cplusplus
+} // end extern C
+#endif
+#endif    /* __ASSEMBLER__ */
+#endif    /* __P9_PSTATES_PGPE_H__ */
diff --git a/src/include/pstate_pgpe_occ_api.h b/src/include/pstate_pgpe_occ_api.h
index e1c18f9..6768617 100644
--- a/src/include/pstate_pgpe_occ_api.h
+++ b/src/include/pstate_pgpe_occ_api.h
@@ -1,19 +1,25 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h $         */
+/* $Source: src/include/pstate_pgpe_occ_api.h $                           */
 /*                                                                        */
-/* IBM CONFIDENTIAL                                                       */
+/* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* EKB Project                                                            */
-/*                                                                        */
-/* COPYRIGHT 2015,2017                                                    */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
-/* The source code for this program is not published or otherwise         */
-/* divested of its trade secrets, irrespective of what has been           */
-/* deposited with the U.S. Copyright Office.                              */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
 /// @file  p9_pstates_pgpe_occ_api.h
@@ -53,9 +59,6 @@ enum MESSAGE_ID_IPI2HI
 //
 // Return Codes
 //
-//\todo
-//Get feedback from Martha and Greg on these return codes
-//
 #define PGPE_RC_SUCCESS                         0x01
 #define PGPE_WOF_RC_NOT_ENABLED                 0x10
 #define PGPE_RC_PSTATES_DISABLED                0x11
@@ -101,8 +104,8 @@ typedef struct ipcmsg_start_stop
 typedef struct ipcmsg_clip_update
 {
     ipcmsg_base_t   msg_cb;
-    uint8_t         ps_val_clip_min[MAX_QUADS];
-    uint8_t         ps_val_clip_max[MAX_QUADS];
+    uint8_t         ps_val_clip_min[MAXIMUM_QUADS];
+    uint8_t         ps_val_clip_max[MAXIMUM_QUADS];
     uint8_t         pad[2];
 } ipcmsg_clip_update_t;
 
@@ -111,7 +114,7 @@ typedef struct ipcmsg_set_pmcr
 {
     ipcmsg_base_t   msg_cb;
     uint8_t         pad[6];
-    uint64_t        pmcr[MAX_QUADS];
+    uint64_t        pmcr[MAXIMUM_QUADS];
 } ipcmsg_set_pmcr_t;
 
 
@@ -269,10 +272,10 @@ typedef union quad_state0
         uint64_t quad1_pstate             : 8;  // Pstate of Quad 1; 0xFF indicates EQ is off
         uint64_t quad2_pstate             : 8;  // Pstate of Quad 2; 0xFF indicates EQ is off
         uint64_t quad3_pstate             : 8;  // Pstate of Quad 3; 0xFF indicates EQ is off
-        uint64_t core_poweron_state       : 16; // bit vector: 0:core0, 1:core1, ..., 15:core15
-        uint64_t ivrm_state               : 4;  // ivrm state: bit vector 0:quad0, 1:quad1, 2:quad2, 3;quad3
-        uint64_t ivrm_state_rsvd          : 4;
-        uint64_t external_vrm_setpoint    : 8;  // set point in mV
+        uint64_t active_cores             : 16; // bit vector: 0:core0, 1:core1, ..., 15:core15
+    uint64_t ivrm_state               :
+        8;  // ivrm state: bit vector 0:quad0, 1:quad1, 2:quad2, 3;quad3, 4: quad4, 5: quad5, 6-7:reserved
+        uint64_t reserved                 : 8;  // reserved for future use
     } fields;
 } quad_state0_t;
 
@@ -288,15 +291,47 @@ typedef union quad_state1
     {
         uint64_t quad4_pstate             : 8;  // Pstate of Quad 4; 0xFF indicates EQ is off
         uint64_t quad5_pstate             : 8;  // Pstate of Quad 5; 0xFF indicates EQ is off
-        uint64_t reserved                 : 16;
-        uint64_t ivrm_state               : 2;  // ivrm state: bit vector 0:quad4, 1:quad5
-        uint64_t ivrm_state_rsvd          : 6;
-        uint64_t core_poweron_state       : 8;  // bit vector: 0:core16, 1:core17, ..., 7:core23
-        uint64_t requested_active_quad    : 8;
-        uint64_t external_vrm_setpoint    : 8;  // set point in mV
+        uint64_t reserved0                : 16;
+        uint64_t active_cores             : 16; // bit vector: 0:core16, 1:core17, ..., 7:core23
+    uint64_t ivrm_state               :
+        8;  // ivrm state: bit vector 0:quad0, 1:quad1, 2:quad2, 3;quad3, 4: quad4, 5: quad5, 6-7:reserved
+        uint64_t reserved1                : 8;  // reserved for future use
     } fields;
 } quad_state1_t;
 
+typedef union pgpe_wof_state
+{
+    uint64_t value;
+    struct
+    {
+        uint32_t high_order;
+        uint32_t low_order;
+    } words;
+    struct
+    {
+        uint64_t reserved0              : 8;
+        uint64_t fclip_ps               : 8;
+        uint64_t vclip_mv               : 16;
+        uint64_t fratio                 : 16;
+        uint64_t vratio                 : 16;
+    } fields;
+} pgpe_wof_state_t;
+
+typedef union requested_active_quads
+{
+    uint64_t value;
+    struct
+    {
+        uint32_t high_order;
+        uint32_t low_order;
+    } words;
+    struct
+    {
+        uint64_t reserved                   : 56;
+        uint64_t requested_active_quads     : 8;
+    } fields;
+} requested_active_quads_t;
+
 // End Quad State
 // -----------------------------------------------------------------------------
 
@@ -315,6 +350,12 @@ typedef struct
     /// Actual Pstate 1 - Quads 4, 5
     quad_state1_t       quad_pstate_1;
 
+    ///PGPE WOF State
+    pgpe_wof_state_t    pgpe_wof_state;
+
+    ///Requested Active Quads
+    requested_active_quads_t    req_active_quads;
+
     /// FFDC Address list
     Hcode_FFDC_list_t   ffdc_list;