PGPE init updates

Change-Id: I0140184371619983fb38b27199f241efe7f30f16
RTC: 169886
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37770
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>

1 files changed, 82 insertions, 80 deletions

diff --git a/src/include/occhw_irq_config.h b/src/include/occhw_irq_config.h
index 2a157ab..44e99dc 100644
--- a/src/include/occhw_irq_config.h
+++ b/src/include/occhw_irq_config.h
@@ -33,7 +33,7 @@
 /// Designate an instance (GPE 0-3 or 405) to own the routing registers
 /// 0-3 -> GPE, 4 -> 405
 #ifndef OCCHW_IRQ_ROUTE_OWNER
-#define OCCHW_IRQ_ROUTE_OWNER 0
+    #define OCCHW_IRQ_ROUTE_OWNER 4
 #endif
 
 /// This macro should be defined in the pk_app_cfg.h file for external interrupts
@@ -41,20 +41,20 @@
 /// interrupts owned by this instance will have the default configuration and be
 /// masked.
 #ifndef OCCHW_EXT_IRQS_CONFIG
-#define OCCHW_EXT_IRQS_CONFIG
+    #define OCCHW_EXT_IRQS_CONFIG
 #endif
 
 #ifndef __ASSEMBLER__
-/// These globals are statically initialized elsewhere
-extern uint64_t g_ext_irqs_routeA;
-extern uint64_t g_ext_irqs_routeB;
-extern uint64_t g_ext_irqs_routeC;
-extern uint64_t g_ext_irqs_type;
-extern uint64_t g_ext_irqs_owned;
-extern uint64_t g_ext_irqs_polarity;
-extern uint64_t g_ext_irqs_enable;
+    /// These globals are statically initialized elsewhere
+    extern uint64_t g_ext_irqs_routeA;
+    extern uint64_t g_ext_irqs_routeB;
+    extern uint64_t g_ext_irqs_routeC;
+    extern uint64_t g_ext_irqs_type;
+    extern uint64_t g_ext_irqs_owned;
+    extern uint64_t g_ext_irqs_polarity;
+    extern uint64_t g_ext_irqs_enable;
 
-#define OCCHW_IRQ_OWNED(irq) ((OCCHW_IRQ_MASK64(irq) & g_ext_irqs_owned) != 0) 
+    #define OCCHW_IRQ_OWNED(irq) ((OCCHW_IRQ_MASK64(irq) & g_ext_irqs_owned) != 0)
 
 #endif
 
@@ -67,70 +67,70 @@ extern uint64_t g_ext_irqs_enable;
 /// Default interrupt routing table
 #ifndef OCCHW_IRQ_ROUTES
 #define OCCHW_IRQ_ROUTES \
-OCCHW_IRQ_DEBUGGER                      OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_TRACE_TRIGGER                 OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_OCC_ERROR                     OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_PBA_ERROR                     OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_SRT_ERROR                     OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_GPE0_HALT                     OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_GPE1_HALT                     OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_GPE2_HALT                     OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_GPE3_HALT                     OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_PPC405_HALT                   OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_OCB_ERROR                     OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_SPIPSS_ERROR                  OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_CHECK_STOP_PPC405             OCCHW_IRQ_TARGET_ID_405_NONCRIT \
-OCCHW_IRQ_CHECK_STOP_GPE0               OCCHW_IRQ_TARGET_ID_GPE0 \
-OCCHW_IRQ_CHECK_STOP_GPE1               OCCHW_IRQ_TARGET_ID_GPE1 \
-OCCHW_IRQ_CHECK_STOP_GPE2               OCCHW_IRQ_TARGET_ID_GPE2 \
-OCCHW_IRQ_CHECK_STOP_GPE3               OCCHW_IRQ_TARGET_ID_GPE3 \
-OCCHW_IRQ_OCC_MALF_ALERT                OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_ADU_MALF_ALERT                OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_EXTERNAL_TRAP                 OCCHW_IRQ_TARGET_ID_405_NONCRIT \
-OCCHW_IRQ_IVRM_PVREF_ERROR              OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_OCC_TIMER0                    OCCHW_IRQ_TARGET_ID_405_NONCRIT \
-OCCHW_IRQ_OCC_TIMER1                    OCCHW_IRQ_TARGET_ID_405_NONCRIT \
-OCCHW_IRQ_HALT_PSTATES                  OCCHW_IRQ_TARGET_ID_GPE3 \
-OCCHW_IRQ_IPI_SCOM                      OCCHW_IRQ_TARGET_ID_GPE3 \
-OCCHW_IRQ_IPI0_HI_PRIORITY              OCCHW_IRQ_TARGET_ID_GPE0 \
-OCCHW_IRQ_IPI1_HI_PRIORITY              OCCHW_IRQ_TARGET_ID_GPE1 \
-OCCHW_IRQ_IPI2_HI_PRIORITY              OCCHW_IRQ_TARGET_ID_GPE2 \
-OCCHW_IRQ_IPI3_HI_PRIORITY              OCCHW_IRQ_TARGET_ID_GPE3 \
-OCCHW_IRQ_IPI4_HI_PRIORITY              OCCHW_IRQ_TARGET_ID_405_CRIT \
-OCCHW_IRQ_ADCFSM_ONGOING                OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_RESERVED_31                   OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_PBAX_OCC_SEND                 OCCHW_IRQ_TARGET_ID_405_NONCRIT \
-OCCHW_IRQ_PBAX_OCC_PUSH0                OCCHW_IRQ_TARGET_ID_405_NONCRIT \
-OCCHW_IRQ_PBAX_OCC_PUSH1                OCCHW_IRQ_TARGET_ID_405_NONCRIT \
-OCCHW_IRQ_PBA_BCDE_ATTN                 OCCHW_IRQ_TARGET_ID_405_NONCRIT \
-OCCHW_IRQ_PBA_BCUE_ATTN                 OCCHW_IRQ_TARGET_ID_405_NONCRIT \
-OCCHW_IRQ_STRM0_PULL                    OCCHW_IRQ_TARGET_ID_405_NONCRIT \
-OCCHW_IRQ_STRM0_PUSH                    OCCHW_IRQ_TARGET_ID_405_NONCRIT \
-OCCHW_IRQ_STRM1_PULL                    OCCHW_IRQ_TARGET_ID_405_NONCRIT \
-OCCHW_IRQ_STRM1_PUSH                    OCCHW_IRQ_TARGET_ID_405_NONCRIT \
-OCCHW_IRQ_STRM2_PULL                    OCCHW_IRQ_TARGET_ID_405_NONCRIT \
-OCCHW_IRQ_STRM2_PUSH                    OCCHW_IRQ_TARGET_ID_405_NONCRIT \
-OCCHW_IRQ_STRM3_PULL                    OCCHW_IRQ_TARGET_ID_405_NONCRIT \
-OCCHW_IRQ_STRM3_PUSH                    OCCHW_IRQ_TARGET_ID_405_NONCRIT \
-OCCHW_IRQ_PMC_PCB_INTR_TYPE0_PENDING    OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_PMC_PCB_INTR_TYPE1_PENDING    OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_PMC_PCB_INTR_TYPE2_PENDING    OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_PMC_PCB_INTR_TYPE3_PENDING    OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_PMC_PCB_INTR_TYPE4_PENDING    OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_PMC_PCB_INTR_TYPE5_PENDING    OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_PMC_PCB_INTR_TYPE6_PENDING    OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_PMC_PCB_INTR_TYPE7_PENDING    OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_PMC_O2S_0A_ONGOING            OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_PMC_O2S_0B_ONGOING            OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_PMC_O2S_1A_ONGOING            OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_PMC_O2S_1B_ONGOING            OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_PSSBRIDGE_ONGOING             OCCHW_IRQ_TARGET_ID_NONE \
-OCCHW_IRQ_IPI0_LO_PRIORITY              OCCHW_IRQ_TARGET_ID_GPE0 \
-OCCHW_IRQ_IPI1_LO_PRIORITY              OCCHW_IRQ_TARGET_ID_GPE1 \
-OCCHW_IRQ_IPI2_LO_PRIORITY              OCCHW_IRQ_TARGET_ID_GPE2 \
-OCCHW_IRQ_IPI3_LO_PRIORITY              OCCHW_IRQ_TARGET_ID_GPE3 \
-OCCHW_IRQ_IPI4_LO_PRIORITY              OCCHW_IRQ_TARGET_ID_405_NONCRIT \
-OCCHW_IRQ_RESERVED_63                   OCCHW_IRQ_TARGET_ID_NONE
+    OCCHW_IRQ_DEBUGGER                      OCCHW_IRQ_TARGET_ID_NONE \
+    OCCHW_IRQ_TRACE_TRIGGER                 OCCHW_IRQ_TARGET_ID_NONE \
+    OCCHW_IRQ_OCC_ERROR                     OCCHW_IRQ_TARGET_ID_GPE2\
+    OCCHW_IRQ_PBA_ERROR                     OCCHW_IRQ_TARGET_ID_NONE \
+    OCCHW_IRQ_SRT_ERROR                     OCCHW_IRQ_TARGET_ID_NONE \
+    OCCHW_IRQ_GPE0_HALT                     OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_GPE1_HALT                     OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_GPE2_HALT                     OCCHW_IRQ_TARGET_ID_GPE3 \
+    OCCHW_IRQ_GPE3_HALT                     OCCHW_IRQ_TARGET_ID_GPE2 \
+    OCCHW_IRQ_PPC405_HALT                   OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_OCB_ERROR                     OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_SPIPSS_ERROR                  OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_CHECK_STOP_PPC405             OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_CHECK_STOP_GPE0               OCCHW_IRQ_TARGET_ID_GPE0 \
+    OCCHW_IRQ_CHECK_STOP_GPE1               OCCHW_IRQ_TARGET_ID_GPE1 \
+    OCCHW_IRQ_CHECK_STOP_GPE2               OCCHW_IRQ_TARGET_ID_GPE2 \
+    OCCHW_IRQ_CHECK_STOP_GPE3               OCCHW_IRQ_TARGET_ID_GPE3 \
+    OCCHW_IRQ_OCC_MALF_ALERT                OCCHW_IRQ_TARGET_ID_NONE \
+    OCCHW_IRQ_ADU_MALF_ALERT                OCCHW_IRQ_TARGET_ID_NONE \
+    OCCHW_IRQ_EXTERNAL_TRAP                 OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_IVRM_PVREF_ERROR              OCCHW_IRQ_TARGET_ID_NONE \
+    OCCHW_IRQ_OCC_TIMER0                    OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_OCC_TIMER1                    OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_HALT_PSTATES                  OCCHW_IRQ_TARGET_ID_NONE \
+    OCCHW_IRQ_IPI_SCOM                      OCCHW_IRQ_TARGET_ID_GPE1 \
+    OCCHW_IRQ_IPI0_HI_PRIORITY              OCCHW_IRQ_TARGET_ID_GPE0 \
+    OCCHW_IRQ_IPI1_HI_PRIORITY              OCCHW_IRQ_TARGET_ID_GPE1 \
+    OCCHW_IRQ_IPI2_HI_PRIORITY              OCCHW_IRQ_TARGET_ID_GPE2 \
+    OCCHW_IRQ_IPI3_HI_PRIORITY              OCCHW_IRQ_TARGET_ID_GPE3 \
+    OCCHW_IRQ_IPI4_HI_PRIORITY              OCCHW_IRQ_TARGET_ID_405_CRIT \
+    OCCHW_IRQ_ADCFSM_ONGOING                OCCHW_IRQ_TARGET_ID_NONE \
+    OCCHW_IRQ_RESERVED_31                   OCCHW_IRQ_TARGET_ID_NONE \
+    OCCHW_IRQ_PBAX_OCC_SEND                 OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_PBAX_OCC_PUSH0                OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_PBAX_OCC_PUSH1                OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_PBA_BCDE_ATTN                 OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_PBA_BCUE_ATTN                 OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_STRM0_PULL                    OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_STRM0_PUSH                    OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_STRM1_PULL                    OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_STRM1_PUSH                    OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_STRM2_PULL                    OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_STRM2_PUSH                    OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_STRM3_PULL                    OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_STRM3_PUSH                    OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_PMC_PCB_INTR_TYPE0_PENDING    OCCHW_IRQ_TARGET_ID_NONE \
+    OCCHW_IRQ_PMC_PCB_INTR_TYPE1_PENDING    OCCHW_IRQ_TARGET_ID_GPE2 \
+    OCCHW_IRQ_PMC_PCB_INTR_TYPE2_PENDING    OCCHW_IRQ_TARGET_ID_GPE3 \
+    OCCHW_IRQ_PMC_PCB_INTR_TYPE3_PENDING    OCCHW_IRQ_TARGET_ID_GPE3 \
+    OCCHW_IRQ_PMC_PCB_INTR_TYPE4_PENDING    OCCHW_IRQ_TARGET_ID_GPE2 \
+    OCCHW_IRQ_PMC_PCB_INTR_TYPE5_PENDING    OCCHW_IRQ_TARGET_ID_NONE \
+    OCCHW_IRQ_PMC_PCB_INTR_TYPE6_PENDING    OCCHW_IRQ_TARGET_ID_GPE3 \
+    OCCHW_IRQ_PMC_PCB_INTR_TYPE7_PENDING    OCCHW_IRQ_TARGET_ID_NONE \
+    OCCHW_IRQ_PMC_O2S_0A_ONGOING            OCCHW_IRQ_TARGET_ID_NONE \
+    OCCHW_IRQ_PMC_O2S_0B_ONGOING            OCCHW_IRQ_TARGET_ID_NONE \
+    OCCHW_IRQ_PMC_O2S_1A_ONGOING            OCCHW_IRQ_TARGET_ID_NONE \
+    OCCHW_IRQ_PMC_O2S_1B_ONGOING            OCCHW_IRQ_TARGET_ID_NONE \
+    OCCHW_IRQ_PSSBRIDGE_ONGOING             OCCHW_IRQ_TARGET_ID_NONE \
+    OCCHW_IRQ_IPI0_LO_PRIORITY              OCCHW_IRQ_TARGET_ID_GPE0 \
+    OCCHW_IRQ_IPI1_LO_PRIORITY              OCCHW_IRQ_TARGET_ID_GPE1 \
+    OCCHW_IRQ_IPI2_LO_PRIORITY              OCCHW_IRQ_TARGET_ID_GPE2 \
+    OCCHW_IRQ_IPI3_LO_PRIORITY              OCCHW_IRQ_TARGET_ID_GPE3 \
+    OCCHW_IRQ_IPI4_LO_PRIORITY              OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_RESERVED_63                   OCCHW_IRQ_TARGET_ID_NONE
 #endif
 
 // convenience macros for retrieving the IPI IRQ numbers for an OCC instance
@@ -139,6 +139,7 @@ OCCHW_IRQ_RESERVED_63                   OCCHW_IRQ_TARGET_ID_NONE
 #define OCCHW_IPI_HI_IRQ(instance_id) (OCCHW_IRQ_IPI0_HI_PRIORITY + instance_id)
 
 #ifdef __ASSEMBLER__
+// *INDENT-OFF*
 /// These macros aid in the initialization of the external interrupt globals.  I would
 /// prefer to use CPP macros, but they don't support recursive macros which I use to
 /// convert the variable number of interrupts that a processor can control into static
@@ -167,7 +168,7 @@ OCCHW_IRQ_RESERVED_63                   OCCHW_IRQ_TARGET_ID_NONE
             .if (( \irq_num < 0 ) || ( \irq_num > (OCCHW_IRQS - 1)))
                 .error "###### .occhw_irq_config: invalid irq number \irq_num ######"
             .elseif ((.ext_irqs_owned & (1 << ( OCCHW_IRQS - 1 - \irq_num ))) == 0 )
-                .error "###### .occhw_irq_config: Attempt to configure unowned irq number \irq_num ######" 
+                .error "###### .occhw_irq_config: Attempt to configure unowned irq number \irq_num ######"
             .elseif (.ext_irqs_defd & (1 << ( OCCHW_IRQS - 1 - \irq_num )))
                 .error "###### .occhw_irq_config: duplicate definition for irq \irq_num ######"
             .else
@@ -175,19 +176,19 @@ OCCHW_IRQ_RESERVED_63                   OCCHW_IRQ_TARGET_ID_NONE
             .endif
 
             .if (( \irq_type < 0 ) || ( \irq_type > 1 ))
-                .error "###### .occhw_irq_config: invalid/unspecified irq type \irq_type for irq \irq_num ######" 
+                .error "###### .occhw_irq_config: invalid/unspecified irq type \irq_type for irq \irq_num ######"
             .else
                 .ext_irqs_type = .ext_irqs_type | ( \irq_type << ( OCCHW_IRQS - 1 - \irq_num ))
             .endif
 
             .if (( \irq_polarity < 0 ) || ( \irq_polarity > 1 ))
-                .error "###### .occhw_irq_config: invalid/unspecified irq polarity ( \irq_polarity ) for irq \irq_num ######" 
+                .error "###### .occhw_irq_config: invalid/unspecified irq polarity ( \irq_polarity ) for irq \irq_num ######"
             .else
                 .ext_irqs_polarity = .ext_irqs_polarity | ( \irq_polarity << ( OCCHW_IRQS - 1 - \irq_num ))
             .endif
 
             .if (( \irq_mask < 0 ) || ( \irq_mask > 1 ))
-                .error "###### .occhw_irq_config: invalid/unspecified irq mask ( \irq_mask ) for irq \irq_num ######" 
+                .error "###### .occhw_irq_config: invalid/unspecified irq mask ( \irq_mask ) for irq \irq_num ######"
             .else
                 .ext_irqs_enable = .ext_irqs_enable | ( \irq_mask << ( OCCHW_IRQS - 1 - \irq_num ))
             .endif
@@ -270,6 +271,7 @@ OCCHW_IRQ_RESERVED_63                   OCCHW_IRQ_TARGET_ID_NONE
         .occhw_irq_config APPCFG_EXT_IRQS_CONFIG
     .endm
 
+// *INDENT-ON*
 #endif /*__ASSEMBLER__*/
 
-#endif /*__OCCHW_IRQ_CONFIG_H__*/ 
+#endif /*__OCCHW_IRQ_CONFIG_H__*/