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path: root/drivers/ddr/fsl/ddr4_dimm_params.c
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* driver/ddr/fsl: Fix driver to support empty first slotYork Sun2015-04-231-1/+2
| | | | | | | | CS0 was not allowed to be empty by u-boot driver in the past to simplify the driver. This may be inconvenient for some debugging. This patch lifts the restrictions. Controller interleaving still requires CS0 populated. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add support for multiple DDR clocksYork Sun2015-02-241-4/+4
| | | | | | | | | Controller number is passed for function calls to support individual DDR clock, depending on SoC implementation. It is backward compatible with exising platforms. Multiple clocks have been verifyed on LS2085A emulator. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add workaround for faulty SPDYork Sun2014-12-051-0/+22
| | | | | | | Some UDIMMs have faulty SPD with wrong mapping for DQ[36-39]. Using raw card spec in case this error is detected. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr: Restruct driver to allow standalone memory spaceYork Sun2014-09-251-6/+6
| | | | | | | | | | U-boot has been initializing DDR for the main memory. The presumption is the memory stays as a big continuous block, either linear or interleaved. This change is to support putting some DDR controllers to separated space without counting into main memory. The standalone memory controller could use different number of DIMM slots. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add DDR4 support to Freescale DDR driverYork Sun2014-04-221-0/+300
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun <yorksun@freescale.com>
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