summaryrefslogtreecommitdiffstats
path: root/arch/x86/cpu
Commit message (Expand)AuthorAgeFilesLines
* x86: ivybridge: Enable the MRC cacheBin Meng2015-10-211-8/+2
* x86: ivybridge: Measure the MRC code execution timeSimon Glass2015-10-211-0/+3
* x86: ivybridge: Fix car_uninit() to correctly set run stateSimon Glass2015-10-211-1/+1
* x86: ivybridge: Check the RTC return valueSimon Glass2015-10-211-3/+10
* x86: ivybridge: Use 'ret' instead of 'rcode'Simon Glass2015-10-211-8/+8
* x86: chromebook_link: Enable the debug UARTSimon Glass2015-10-211-0/+7
* x86: Init the debug UART if enabledSimon Glass2015-10-211-8/+3
* x86: Pass correct cpu_index to ap_init()Bin Meng2015-10-211-2/+2
* x86: quark: Implement mrc cacheBin Meng2015-10-212-7/+64
* x86: ivybridge: Correct two typos for MRCBin Meng2015-10-211-2/+2
* x86: baytrail: Issue full system reset in reset_cpu()Bin Meng2015-10-211-0/+6
* x86: baytrail: Save mrc cache to spi flashBin Meng2015-10-211-0/+19
* x86: Use struct mrc_region to describe a mrc regionBin Meng2015-10-211-1/+1
* x86: ivybridge: Use APIs provided in the mrccache libBin Meng2015-10-211-108/+4
* x86: Move mrccache.[c|h] to a common placeBin Meng2015-10-213-159/+1
* x86: Initialize GDT entry 1 to be the 32-bit CS as wellBin Meng2015-10-211-1/+6
* x86: Allow disabling IGD on Intel QueensbayBin Meng2015-10-212-0/+27
* x86: ivybridge: Remove the dead codes that programs pci bridgeBin Meng2015-10-211-32/+0
* x86: quark: Configure MTRR to enable cacheBin Meng2015-09-162-0/+67
* x86: quark: Initialize thermal sensor properlyBin Meng2015-09-161-0/+40
* x86: quark: Lock HMBOUND register before jumping to kernelBin Meng2015-09-161-0/+3
* x86: quark: Convert to use clrbits, setbits, clrsetbits macrosBin Meng2015-09-161-51/+21
* x86: quark: Add PCIe/USB static register programming after memory initBin Meng2015-09-161-0/+64
* x86: Convert to use driver model eth on quark/galileoBin Meng2015-09-161-19/+0
* x86: quark: Add USB PHY initialization supportBin Meng2015-09-091-0/+41
* x86: Convert to use driver model pci on quark/galileoBin Meng2015-09-093-76/+0
* x86: Enable PCIe controller on quark/galileoBin Meng2015-09-091-0/+63
* x86: quark: Avoid chicken and egg problemBin Meng2015-09-091-15/+15
* x86: quark: Optimize MRC execution timeBin Meng2015-09-091-22/+22
* x86: coreboot: Convert to use more dm driversBin Meng2015-09-091-6/+0
* x86: Add DSDT table for supporting ACPI on QEMUSaket Sinha2015-08-267-1/+712
* x86: Add ACPI table support to QEMUSaket Sinha2015-08-262-0/+177
* x86: baytrail: Remove the fsp_init_phase_pci() callBin Meng2015-08-261-7/+1
* x86: queensbay: Move unprotect_spi_flash() to arch_misc_init()Bin Meng2015-08-261-2/+2
* x86: fsp: Add comments about U-Boot entering start.S twiceBin Meng2015-08-261-2/+4
* x86: fsp: Enlarge the size of malloc() pool before relocationBin Meng2015-08-261-0/+8
* x86: coreboot: Allow >=4GiB memory bank sizeBin Meng2015-08-261-5/+4
* x86: Remove calculate_relocation_address()Bin Meng2015-08-261-8/+1
* x86: coreboot: Correctly report E820 typesBin Meng2015-08-261-2/+13
* x86: Return -1 when reading a PCI config register failsSimon Glass2015-08-141-3/+6
* x86: Set APs' req_seq to the reg number from device treeBin Meng2015-08-141-0/+7
* x86: Show the un-relocated IP address in exceptionsSimon Glass2015-08-141-0/+2
* x86: Switch to using generic global_data setupSimon Glass2015-08-142-83/+16
* x86: Move the GDT into global_dataSimon Glass2015-08-141-4/+5
* x86: baytrail: Support running as an EFI payloadSimon Glass2015-08-141-0/+2
* x86: baytrail: Tidy up interrupt and FSP initSimon Glass2015-08-141-1/+8
* x86: Allow pirq_init() to return an errorSimon Glass2015-08-145-18/+15
* x86: Tidy up the PIRQ routing code a littleSimon Glass2015-08-141-28/+13
* x86: baytrail: Configure FSP UPD from device treeAndrew Bradford2015-08-141-30/+132
* x86: Enable debug UART for MinnowmaxSimon Glass2015-08-061-0/+9
OpenPOWER on IntegriCloud