summaryrefslogtreecommitdiffstats
path: root/arch/x86/cpu
Commit message (Expand)AuthorAgeFilesLines
* x86: Update microcode for secondary CPUsSimon Glass2016-03-173-2/+7
* x86: ivybridge: Show microcode version for each coreSimon Glass2016-03-171-1/+2
* x86: Record the CPU details when starting each coreSimon Glass2016-03-172-1/+11
* x86: Move common MRC Kconfig options to the common fileSimon Glass2016-03-171-26/+1
* x86: Move Intel Management Engine code to a common placeSimon Glass2016-03-176-35/+25
* x86: Rename PORT_RESET to IO_PORT_RESETSimon Glass2016-03-172-4/+4
* x86: Move common CPU code to its own placeSimon Glass2016-03-173-74/+118
* x86: Move common LPC code to its own placeSimon Glass2016-03-174-83/+107
* x86: Add the root-complex block to common intel registersSimon Glass2016-03-172-2/+5
* x86: Create a common header for Intel register accessSimon Glass2016-03-174-3/+7
* x86: Move microcode code to a common locationSimon Glass2016-03-175-4/+8
* x86: Move cache-as-RAM code into a common locationSimon Glass2016-03-174-1/+8
* x86: cpu: Add functions to return the family and steppingSimon Glass2016-03-171-0/+10
* x86: Add comments to the SIPI vectorSimon Glass2016-03-171-0/+1
* x86: Tidy up mp_init to reduce duplicationSimon Glass2016-03-171-53/+26
* x86: Add some more common MSR indexesSimon Glass2016-03-171-2/+3
* x86: cpu: Make the vendor table constSimon Glass2016-03-171-1/+1
* x86: Change write_acpi_tables() signature a little bitBin Meng2016-03-171-3/+2
* x86: Move asm/arch-coreboot/tables.h to a common placeBin Meng2016-03-172-2/+0
* dm: Use uclass_first_device_err() where it is usefulSimon Glass2016-03-145-19/+11
* x86: Add Intel Cougar Canyon 2 boardBin Meng2016-02-211-0/+4
* x86: ivybridge: bd82x6x: Support FSP enabled configurationBin Meng2016-02-212-1/+5
* x86: ivybridge: Add FSP supportBin Meng2016-02-214-0/+79
* x86: fix memalign() parameter orderStephen Warren2016-02-211-1/+1
* Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-stagingTom Rini2016-02-081-1/+1
|\
| * Use correct spelling of "U-Boot"Bin Meng2016-02-061-1/+1
* | x86: quark: Use Quark's own PCI config APIsBin Meng2016-02-051-2/+3
* | x86: pci: Drop legacy PCI APIsBin Meng2016-02-051-53/+0
* | x86: pci: Use DM PCI APIs in pci_assign_irqs()Bin Meng2016-02-051-3/+3
* | x86: qemu: Convert to use DM PCI APIBin Meng2016-02-051-17/+17
* | x86: tnc: Remove IGD and SDVO devices from driver modelBin Meng2016-02-051-0/+36
* | x86: tnc: Use DM PCI API in disable_igd()Bin Meng2016-02-051-3/+19
* | x86: tnc: Change disable_igd() to have a return valueBin Meng2016-02-051-3/+7
* | x86: irq: Convert to use DM PCI APIBin Meng2016-02-052-4/+4
* | x86: irq: Move irq_router to a per driver privBin Meng2016-02-051-36/+37
* | x86: irq: Get irq_router's bdf via dm_pci_get_bdf()Bin Meng2016-02-051-8/+1
* | x86: pch: Implement get_gpio_base opBin Meng2016-02-051-0/+33
* | dm: pch: Rename get_sbase op to get_spi_baseBin Meng2016-02-051-2/+2
* | dm: pch: Remove pch_get_version opBin Meng2016-02-051-6/+0
* | x86: quark: Drop unprotect_spi_flash()Bin Meng2016-02-051-17/+0
* | x86: tnc: Drop unprotect_spi_flash()Bin Meng2016-02-051-16/+0
|/
* x86: qemu: add the ability to load and link ACPI tables from QEMUMiao Yan2016-01-282-0/+255
* x86: qemu: setup PM IO base for ACPI in southbridgeMiao Yan2016-01-282-0/+36
* x86: qemu: re-structure qemu_fwcfg_list_firmware()Miao Yan2016-01-281-14/+49
* x86: baytrail: Add option to disable the internal UART to setup_early_uart()Stefan Roese2016-01-281-3/+7
* x86: ivybridge: Use syscon for the GMA deviceSimon Glass2016-01-243-12/+11
* x86: Set up a shared syscon numbering schemaSimon Glass2016-01-242-4/+5
* x86: ivybridge: Drop the SMM-locking codeSimon Glass2016-01-241-57/+0
* x86: ivybridge: Drop XHCI supportSimon Glass2016-01-242-33/+0
* x86: ivybridge: Drop special EHCI initSimon Glass2016-01-243-33/+0
OpenPOWER on IntegriCloud