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| author | Simon Glass <sjg@chromium.org> | 2016-03-11 22:06:55 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-03-17 10:27:24 +0800 |
| commit | 06d336cca284cc767a095ce40afca79b4aa0ecb0 (patch) | |
| tree | 4ffb6481ff02ed6f29d1767fd05c2d186aa3d9ff /arch/x86/cpu | |
| parent | 9e66506d33eac67bfa814ccba1c9ccd06bb5b107 (diff) | |
| download | talos-obmc-uboot-06d336cca284cc767a095ce40afca79b4aa0ecb0.tar.gz talos-obmc-uboot-06d336cca284cc767a095ce40afca79b4aa0ecb0.zip | |
x86: Create a common header for Intel register access
There are several blocks of registers that are accessed from all over the
code on Intel CPUs. These don't currently have their own driver and it is
not clear whether having a driver makes sense.
An example is the Memory Controller Hub (MCH). We map it to a known location
on some Intel chips (mostly those without FSP - Firmware Support Package).
Add a new header file for these registers, and move MCH into it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/cpu')
| -rw-r--r-- | arch/x86/cpu/ivybridge/cpu.c | 1 | ||||
| -rw-r--r-- | arch/x86/cpu/ivybridge/gma.c | 1 | ||||
| -rw-r--r-- | arch/x86/cpu/ivybridge/northbridge.c | 5 | ||||
| -rw-r--r-- | arch/x86/cpu/ivybridge/sdram.c | 3 |
4 files changed, 7 insertions, 3 deletions
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index f0e733bc33..796771c021 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -17,6 +17,7 @@ #include <fdtdec.h> #include <pch.h> #include <asm/cpu.h> +#include <asm/intel_regs.h> #include <asm/io.h> #include <asm/lapic.h> #include <asm/microcode.h> diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c index 91a57f9847..37e2e6ead8 100644 --- a/arch/x86/cpu/ivybridge/gma.c +++ b/arch/x86/cpu/ivybridge/gma.c @@ -12,6 +12,7 @@ #include <errno.h> #include <fdtdec.h> #include <pci_rom.h> +#include <asm/intel_regs.h> #include <asm/io.h> #include <asm/mtrr.h> #include <asm/pci.h> diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index a066607a18..f7e0bc3f18 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -12,6 +12,7 @@ #include <asm/msr.h> #include <asm/acpi.h> #include <asm/cpu.h> +#include <asm/intel_regs.h> #include <asm/io.h> #include <asm/pci.h> #include <asm/processor.h> @@ -167,8 +168,8 @@ static void sandybridge_setup_northbridge_bars(struct udevice *dev) debug("Setting up static registers\n"); dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1); dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1); - dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1); + dm_pci_write_config32(dev, MCHBAR + 4, (0LL + MCH_BASE_ADDRESS) >> 32); /* 64MB - busses 0-63 */ dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); dm_pci_write_config32(dev, PCIEXBAR + 4, diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 0ebcc2c257..f7dd61f045 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -23,6 +23,7 @@ #include <asm/processor.h> #include <asm/gpio.h> #include <asm/global_data.h> +#include <asm/intel_regs.h> #include <asm/mrccache.h> #include <asm/mtrr.h> #include <asm/pci.h> @@ -682,7 +683,7 @@ int dram_init(void) { struct pei_data pei_data __aligned(8) = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = MCH_BASE_ADDRESS, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_PCIE_ECAM_BASE, |
