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* | | arm: include: Import unified.h from Linux kernelMarek Vasut2016-06-022-0/+130
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import unified.h from Linux kernel 4.4.6 , commit 0d1912303e54ed1b2a371be0bba51c384dd57326 . This header file contains macros used in libgcc functions in Linux kernel on ARM and will be needed for the libgcc sync. Since unified.h defines the W(instr) macro, we must drop this from the macro from memcpy.S , otherwise this triggers a warning about symbol redefinition. In order to keep the changes to unified.h to the minimum, tweak arch/arm/lib/Makefile such that it defines the CONFIG_ARM_ASM_UNIFIED macro, which places .syntax unified into all of the assembler files. This is mandatory. Moreover, for Thumb2 build, define CONFIG_THUMB2_KERNEL macro if and only if Thumb2 build is enabled. This macro is checked by unified.h and toggles between ARM and Thumb2 variant of the instructions in the assembler source files. Finally, this patch defines __LINUX_ARM_ARCH__=N macro based on the new CONFIG_SYS_ARM_ARCH Kconfig option. This macro selects between more optimal and more dense codepaths which work on armv5 and newer and less optimal codepaths which work on armv4 and possible armv3m. Tegra2 needs the same special handling as it does in arch/arm/Makefile to cater for the arm720t boot core. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2016-05-272-0/+70
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| * | rockchip: rk3288: grf: Define GRF_SOC_CON1 and GRF_SOC_CON3Sjoerd Simons2016-05-271-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | Add definitions for GRF_SOC_CON1 and GRF_SOC_CON3 which contain various GMAC related fields. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288: Add clock support for the gmac ethernet interfaceSjoerd Simons2016-05-271-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | Setup the clocks for the gmac ethernet interface. This assumes the mac clock is fed by an external clock which is common on RK3288 based devices. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | ARM: AM33xx: Add support for Clock SynthesizerLokesh Vutla2016-05-271-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CDCE913 and CDCEL913 devices are modular PLL-based, low cost, high performance , programmable clock synthesizers. They generate upto 3 output clocks from a single input frequency. Each output can be programmed for any clock-frequency. Adding support for the same. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | board: AM335x-ICEv2: Add DDR dataLokesh Vutla2016-05-271-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | AM335x ICEv2 contains a 2Gbit(128Mx16) of DDR3 SDRAM(MT41J128M16JT-125), capable of running at 400MHz. Adding this specific DDR configuration details running at 400MHz. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: omap-common: Add device type to CPU stringDaniel Allred2016-05-272-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the CPU string output so that the device type is now included as part of the CPU string that is printed as the SPL or u-boot comes up. This update adds a suffix of the form "-GP" or "-HS" for production devices, so that general purpose (GP) and high security (HS) can be distiguished. Applies to all OMAP5 variants. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Madan Srinivas <madans@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | arm: meson: implement calls to secure monitorBeniamino Galvani2016-05-271-0/+12
| | | | | | | | | | | | | | | | | | Implement calls to secure monitor to read the MAC address from e-fuse. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
* | | arm: add initial support for Amlogic Meson and ODROID-C2Beniamino Galvani2016-05-271-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds platform code for the Amlogic Meson GXBaby (S905) SoC and a board definition for ODROID-C2. This initial submission only supports UART and Ethernet (through the existing Designware driver). DTS files are the ones submitted to Linux arm-soc for 4.7 [1]. [1] https://patchwork.ozlabs.org/patch/603583/ Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | arm: implement generic PSCI reset call for armv8Beniamino Galvani2016-05-272-1/+18
|/ / | | | | | | | | | | | | | | | | Add a psci_system_reset() which calls the SYSTEM_RESET function of PSCI 0.2 and can be used by boards that support it to implement reset_cpu(). Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sunxi: Increase SPL header size to 64 bytes to avoid code corruptionSiarhei Siamashka2016-05-251-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current SPL header, created by the 'mksunxiboot' tool, has size 32 bytes. But the code in the boot ROM stores the information about the boot media at the offset 0x28 before passing control to the SPL. For example, when booting from the SD card, the magic number written by the boot ROM is 0. And when booting from the SPI flash, the magic number is 3. NAND and eMMC probably have their own special magic numbers too. Currently the corrupted byte is a part of one of the instructions in the reset vectors table: b reset ldr pc, _undefined_instruction ldr pc, _software_interrupt <- Corruption happens here ldr pc, _prefetch_abort ldr pc, _data_abort ldr pc, _not_used ldr pc, _irq ldr pc, _fiq In practice this does not cause any visible problems, but it's still better to fix it. As a bonus, the reported boot media type can be later used in the 'spl_boot_device' function, but this is out of the scope of this patch. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-05-246-10/+34
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| * | driver/ddr/fsl: Add workaround for erratum A-010165Shengzhou Liu2016-05-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | During DDR-2133 operation, the transmit data eye margins determined during the memory controller initialization may be sub-optimal, set DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | arch/arm, arch/powerpc: add # of SEC engines on the SOCAlex Porosanu2016-05-182-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SOCs, specifically the ones in the C29x familiy can have multiple security engines. This patch adds a system configuration define which indicates the maximum number of SEC engines that can be found on a SoC. Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | arch/arm: add SEC JR0 offsetAlex Porosanu2016-05-185-10/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale PPC SoCs do not hard-code security engine's Job Ring 0 address, rather a define is used. This patch adds the same functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts) Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | driver/ddr/fsl: Add workaround for erratum A-009801Shengzhou Liu2016-05-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The initial training for the DDRC may provide results that are not optimized. The workaround provides better read timing margins. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/ls1043: Add workaround for DDR erratum A-008850Shengzhou Liu2016-05-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-05-241-0/+12
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: drivers/net/zynq_gem.c
| * | | ARM: omap5: add platform specific ethernet phy modes configurationsMugunthan V N2016-05-241-0/+12
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | Add platforms specific phy mode configuration bits to be used to configure phy mode in control module. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | ARM64: zynqmp: Add SPL support supportMichal Simek2016-05-241-0/+2
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support RAM and MMC boot mode in SPL also with SPL_FIT images. In MMC boot mode two boot options are available: 1) Boot flow with ATF(EL3) and full U-Boot(EL2): aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin mkimage -A arm64 -O linux -T kernel -C none -a 0xfffe5000 -e 0xfffe5000 -d bl31.bin atf.ub cp spl/boot.bin <sdcard fat partition> cp atf.ub <sdcard fat partition> cp u-boot.bin <sdcard fat partition> 2) Boot flow with full U-Boot(EL3): cp spl/boot.bin <sdcard> cp u-boot*.img <sdcard> 3) emmc boot mode dd if=/dev/zero of=sd.img bs=1024 count=1024 parted sd.img mktable msdos parted sd.img mkpart p fat32 0% 100% kpartx -a sd.img mkfs.vfat /dev/mapper/loop0p1 mount /dev/mapper/loop0p1 /mnt/ cp spl/boot.bin /mnt cp u-boot.img /mnt cp u-boot.bin /mnt cp atf.ub /mnt umount /dev/mapper/loop0p1 kpartx -d sd.img cp sd.img /tftpboot/ and program it via u-boot tftpb 10000 sd.img mmcinfo mmc write 10000 0 $filesize mmc rescan mmc part ls mmc 0 psu_init() function contains low level SoC setup generated for every HW design by Xilinx design tools. xil_io.h is only supporting file to fix all dependencies from tools. The same solution was used on Xilinx Zynq. The patch also change CONFIG_SYS_INIT_SP_ADDR to the end of OCM which stays at the same location all the time. Bootrom expects starting address to be at 0xfffc0000 that's why this address is SPL_TEXT_BASE. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2016-05-171-1/+1
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| * | dm: scsi: Rename CONFIG_CMD_SCSI to CONFIG_SCSISimon Glass2016-05-171-1/+1
| |/ | | | | | | | | | | | | | | This option currently enables both the command and the SCSI functionality. Rename the existing option to CONFIG_SCSI since most of the code relates to the feature. Signed-off-by: Simon Glass <sjg@chromium.org>
* | imx: iomux-v3: fix UART input selectsStefan Agner2016-05-171-4/+4
| | | | | | | | | | | | | | | | | | | | | | Several UART input selects are missing. The fourth input select for UART2_TX_DATA_ALT0 is actually also missing in the documentation. (at least in Rev. B of the i.MX 7Dual Reference Manual). However, when looking at the tables of other input selects, it is very natural that there must be an input select for the UART2_TX_DATA_ALT0 pad. The Colibri iMX7 also uses that pad for UART2 RX (in DTE mode), and it was required to set that particular input select register to get a working UART2.
* | imx: mx6: mx6sl_pins: add GPIO variant for SD1_DAT5Eric Nelson2016-05-171-0/+1
|/ | | | | | | This patch adds the IOMUX setting for using SD1_DAT5 as GPIO5:9. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Peng Fan <van.freenix@gmail.com>
* arm/arm64: Move barrier instructions into separate headerAndre Przywara2016-05-122-20/+45
| | | | | | | | | | | | | | | | Commit bfb33f0bc45b ("sunxi: mctl_mem_matches: Add missing memory barrier") broke compilation for the Pine64, as dram_helper.c now includes <asm/armv7.h>, which does not compile on arm64. Fix this by moving all barrier instructions into a separate header file, which can easily be shared between arm and arm64. Also extend the inline assembly to take the "sy" argument, which is optional for ARMv7, but mandatory for v8. This fixes compilation for 64-bit sunxi boards (Pine64). Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* ARM: tegra: enable GPU node by compatible valueStephen Warren2016-05-041-1/+1
| | | | | | | | | | | | | | | | | | | In current Linux kernel Tegra DT files, 64-bit addresses are represented in unit addresses as a pair of comma-separated 32-bit values. Apparently this is no longer the correct representation for simple busses, and the unit address should be represented as a single 64-bit value. If this is changed in the DTs, arm/arm/mach-tegra/board2.c:ft_system_setup() will no longer be able to find and enable the GPU node, since it looks up the node by name. Fix that function to enable nodes based on their compatible value rather than their node name. This will work no matter what the node name is, i.e for DTs both before and after any rename operation. Cc: Thierry Reding <treding@nvidia.com> Cc: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: DRA7: Add ABB setup for all domainsNishanth Menon2016-04-252-0/+12
| | | | | | | | | | | | | ABB should be initialized for all required domains voltage domain for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If we do not do this, kernel configuring just the frequency using the default boot loader configured voltage can fail on many corner lot units and has been hard to debug. This specifically is a concern with DRA7 generation of SoCs since other than VDD_MPU, all other domains are only permitted to setup the voltages to required OPP only at boot. Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: OMAP5: Enable ABB configuration for MM voltage domainNishanth Menon2016-04-252-0/+5
| | | | | | | | | | Since we setup the voltage and frequency for the MM domain, we *must* setup the ABB configuration needed for the domain as well. If we do not do this, kernel configuring just the frequency using the default boot loader configured voltage can fail on many corner lot units. Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: OMAP5/DRA7: Move ABB TXDONE mask to voltage structureNishanth Menon2016-04-251-0/+2
| | | | | | | | | | | ABB TX_DONE mask will vary depending on ABB module. For example, 3630 never had ABB on IVA domain, while OMAP5 does use ABB on MM domain, DRA7 has it on all domains with the exception of CORE, RTC. Hence, move the txdone mask definition over to structure describing voltage domain. Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: OMAP5/DRA7: Get rid of control_std_fuse_opp_vdd_mpu_2Nishanth Menon2016-04-251-1/+0
| | | | | | | | | | | | | This information is already available under vcores->volts.efuse.reg. There is no reason for duplicating the information since AVS Class 0 definitions are common for OMAP5 and DRA7 and defined with STD_FUSE_OPP_* macros. This allows a central location of defining the ABB and voltage definitions especially since they are reused. This also makes it simpler to prevent mistakes involved when changing the boot OPP for the device. Signed-off-by: Nishanth Menon <nm@ti.com>
* configs: Re-sync with cmd/KconfigTom Rini2016-04-252-3/+0
| | | | | | | Update the config.h and defconfig files for the commands that 8e3c036 converted over to Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
* configs: Re-sync almost all of cmd/KconfigTom Rini2016-04-251-1/+0
| | | | | | | | This syncs up the current cmd/Kconfig and include/configs/ files with the only exception being CMD_NAND. Due to how we have used this historically we need to take further care here when converting. Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-04-252-0/+10
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| * MX6UL: Add definition for UART6 base addressFabio Estevam2016-04-191-0/+1
| | | | | | | | | | | | Define the UART6_BASE_ADDR for MX6UL. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * imx: mx6: Fix procedure to switch the parent of LDB_DI_CLKAkshay Bhat2016-04-191-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is generated, and the LVDS display will hang when the ipu_di_clk is sourced from ldb_di_clk. To fix the problem, both the new and current parent of the ldb_di_clk should be disabled before the switch. This patch ensures that correct steps are followed when ldb_di_clk parent is switched in the beginning of boot. This patch was ported from the 3.10.17 NXP kernel http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_3.10.17_1.0.1_ga&id=eecbe9a52587cf9eec30132fb9b8a6761f3a1e6d NXP errata number: ERR009219, EB821 Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
* | ARM: AM43xx: Fix BOOT_DEVICE_USB IDLokesh Vutla2016-04-181-1/+2
|/ | | | | | | | | commit 62c5674ea136a ("omap: SPL boot devices cleanup and completion") cleans up the boot device ids for amx3xx soc. But mistakenly updates wrong device IDs for AM43xx USB. Fixing the same here. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-04-133-3/+5
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| * arm: mx6: Add UART8 base address for i.MX6ULStefan Roese2016-03-261-0/+1
| | | | | | | | | | | | | | | | | | Add the base address for the i.MX6UL so that this UART can be used. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * mx27: 16-bit wide watchdog registersLeonid Iziumtsev2016-03-251-3/+3
| | | | | | | | | | | | | | Make the watchdog registers 16-bit wide, as they are according to TRM. Signed-off-by: Leonid Iziumtsev <leonid.iziumtsev@se.atlascopco.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * Merge branch 'next'Stefano Babic2016-03-201-0/+1
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| | * mx7: Distinguish between dual and solo versionsFabio Estevam2016-03-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Read the number of cores in the fuses to distinguish between the dual and solo versions. Tested on a mx7d sabresd and on a mx7solo warp7. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* | | am33xx changed BOOT_DEVICE_SPI to correct valueVogt, Christof2016-04-111-1/+1
| | | | | | | | | | | | | | | | | | | | | Changed BOOT_DEVICE Code for SPI on AM33xx. According AM335x reference manual page 4960 (SPRUH73L-October 2011-Revised February 2015) Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | arm: add missing writes[bwql], reads[bwql].Purna Chandra Mandal2016-04-101-0/+7
| | | | | | | | | | | | | | | | | | | | | ARM defines __raw_writes[bwql], __raw_reads[bwql] in arch io.h but not the writes[bwql], reads[bwql] needed by some drivers. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-04-066-23/+23
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| * | | armv8: LS2080A: Consolidate LS2080A and LS2085AYork Sun2016-04-065-16/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | | arm: ls102xa: Fix order of CSU indexes in ns_access.hVincent Siles2016-04-061-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch aims to fix the order of CSU slave index for the LS1021a board. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com> Reviewed-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: LSCH2 early and final mmu needs matching NS attributeEd Swarthout2016-04-061-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When switching between the early and final mmu tables, the stack will get corrupted if the Non-Secure attribute is different. For ls1043a, this issue is currently masked because flush_dcache_all is called before the switch when CONFIG_SYS_DPAA_FMAN is defined. Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | | spi: kirkwood_spi: Add support for multiple chip-selects on MVEBUStefan Roese2016-04-061-5/+12
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently only chip-select 0 is supported by the kirkwood SPI driver. The Armada XP / 38x SoCs also use this driver and support multiple chip selects. This patch adds support for multiple CS on MVEBU. The register definitions are restructured a bit with this patch. Grouping them to the corresponding registers. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | | sunxi: Add support for Allwinner A64 SoCsSiarhei Siamashka2016-04-014-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner A64 SoC is used in the Pine64. This patch adds all bits necessary to compile U-Boot for it running in AArch64 mode. Unfortunately SPL is not ready yet due to legal problems, so we need to boot using the binary boot0 for now. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> [agraf: remove SPL code, move to AArch64] Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | sunxi: clk: Fix USB PHY clock macros for A83TChen-Yu Tsai2016-03-311-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | The A83T has 3 PHYs, the last one being HSIC, which has 2 clocks. Also there is only 1 OHCI. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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