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| author | Akshay Bhat <akshay.bhat@timesys.com> | 2016-04-12 18:13:56 -0400 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-04-19 16:05:12 +0200 |
| commit | 90d7cc42b31251548b3cfb0e65a266020159784d (patch) | |
| tree | f303b4c7d6f76602b577b3a0acacac679035bcc1 /arch/arm/include | |
| parent | 0297bd1106bc59f46ba4401bb50a0cdc9afc9faa (diff) | |
| download | talos-obmc-uboot-90d7cc42b31251548b3cfb0e65a266020159784d.tar.gz talos-obmc-uboot-90d7cc42b31251548b3cfb0e65a266020159784d.zip | |
imx: mx6: Fix procedure to switch the parent of LDB_DI_CLK
Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree,
the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the
ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is
generated, and the LVDS display will hang when the ipu_di_clk is sourced from
ldb_di_clk.
To fix the problem, both the new and current parent of the ldb_di_clk should
be disabled before the switch. This patch ensures that correct steps are
followed when ldb_di_clk parent is switched in the beginning of boot.
This patch was ported from the 3.10.17 NXP kernel
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_3.10.17_1.0.1_ga&id=eecbe9a52587cf9eec30132fb9b8a6761f3a1e6d
NXP errata number: ERR009219, EB821
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/clock.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 14505239e8..82f9f92b83 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -42,6 +42,14 @@ enum mxc_clock { MXC_I2C_CLK, }; +enum ldb_di_clock { + MXC_PLL5_CLK = 0, + MXC_PLL2_PFD0_CLK, + MXC_PLL2_PFD2_CLK, + MXC_MMDC_CH1_CLK, + MXC_PLL3_SW_CLK, +}; + enum enet_freq { ENET_25MHZ, ENET_50MHZ, @@ -70,4 +78,5 @@ int enable_lcdif_clock(u32 base_addr); void enable_qspi_clk(int qspi_num); void enable_thermal_clk(void); void mxs_set_lcdclk(u32 base_addr, u32 freq); +void select_ldb_di_clock_source(enum ldb_di_clock clk); #endif /* __ASM_ARCH_CLOCK_H */ |
