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* | arm64: Allow exceptions to returnAlexander Graf2016-03-151-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Our current arm64 exception handlers all panic and never return to the exception triggering code. But if any handler wanted to continue execution after fixups, it would need help from the exception handling code to restore all registers. This patch implements that help. With this code, exception handlers on aarch64 can successfully return to the place the exception happened (or somewhere else if they modify elr). Signed-off-by: Alexander Graf <agraf@suse.de>
* | efi_loader: Add runtime servicesAlexander Graf2016-03-152-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After booting has finished, EFI allows firmware to still interact with the OS using the "runtime services". These callbacks live in a separate address space, since they are available long after U-Boot has been overwritten by the OS. This patch adds enough framework for arbitrary code inside of U-Boot to become a runtime service with the right section attributes set. For now, we don't make use of it yet though. We could maybe in the future map U-boot environment variables to EFI variables here. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | arm64: Only allow dcache disabled in SPL buildsAlexander Graf2016-03-151-0/+9
| | | | | | | | | | | | | | | | | | Now that we have an easy way to describe memory regions and enable the MMU, there really shouldn't be anything holding people back from running with caches enabled on AArch64. To make sure people catch early if they're missing on the caching fun, give them a compile error. Signed-off-by: Alexander Graf <agraf@suse.de>
* | arm64: Remove non-full-va map codeAlexander Graf2016-03-152-95/+32
| | | | | | | | | | | | | | | | | | | | | | By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de>
* | zymqmp: Replace home grown mmu code with generic table approachAlexander Graf2016-03-151-169/+48
| | | | | | | | | | | | | | Now that we have nice table driven page table creating code that gives us everything we need, move to that. Signed-off-by: Alexander Graf <agraf@suse.de>
* | thunderx: Move mmu table into board fileAlexander Graf2016-03-151-5/+3
| | | | | | | | | | | | | | | | | | The MMU range table can vary depending on things we may only find out at runtime. While the very simple ThunderX variant does not change, other boards will, so move the definition from a static entry in a header file to the board file. Signed-off-by: Alexander Graf <agraf@suse.de>
* | arm64: Make full va map code more dynamicAlexander Graf2016-03-152-55/+452
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de>
* | arm64: Disable TTBR1 maps in EL1Alexander Graf2016-03-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | When running in EL1, AArch64 knows two page table maps. One with addresses that start with all zeros (TTBR0) and one with addresses that start with all ones (TTBR1). In U-Boot we don't care about the high up maps, so just disable them to ensure we don't walk an invalid page table by accident. Reported-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* | thunderx: Calculate TCR dynamicallyAlexander Graf2016-03-151-1/+58
| | | | | | | | | | | | | | | | Based on the memory map we can determine a lot of hard coded fields of TCR, like the maximum VA and max PA we want to support. Calculate those dynamically to reduce the chance for pit falls. Signed-off-by: Alexander Graf <agraf@suse.de>
* | omap4: Check warm reset for reboot mode validityPaul Kocialkowski2016-03-151-0/+4
| | | | | | | | | | | | | | Since the SAR registers are filled with garbage on cold reset, this checks for a warm reset to assert the validity of reboot mode. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | omap4: Reboot mode supportPaul Kocialkowski2016-03-151-0/+41
| | | | | | | | | | | | | | | | | | | | Reboot mode is written to SAR memory before reboot in the form of a string. This mechanism is supported on OMAP4 by various TI kernels. It is up to each board to make use of this mechanism or not. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | omap4: Properly enable USB PHY clocksPaul Kocialkowski2016-03-152-0/+5
| | | | | | | | | | | | | | This correctly enables the USB PHY clocks, by enabling CM_ALWON_USBPHY_CLKCTRL and correctly setting CM_L3INIT_USBPHY_CLKCTRL's value. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | omap-common: clocks-common: Setup USB DPLL when MUSB is in usePaul Kocialkowski2016-03-151-2/+4
| | | | | | | | | | | | | | | | On (at least) OMAP4, the USB DPLL is required to be setup for the internal PHY to work properly. The internal PHY is used by default with the MUSB USB OTG controller. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | Amazon Kindle Fire (first generation) codename kc1 supportPaul Kocialkowski2016-03-151-0/+4
| | | | | | | | | | | | | | | | | | | | The Amazon Kindle Fire (first generation) codename kc1 is a tablet that was released by Amazon back in 2011. It is using an OMAP4430 SoC GP version, which allows running U-Boot and the U-Boot SPL from the ground up. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | omap4: Move i2c clocks enable to enable_basic_clocksPaul Kocialkowski2016-03-151-4/+4
| | | | | | | | | | | | | | I2C is often enabled withing the U-Boot SPL, thus those clocks are required to be enabled early (especially when the bootrom doesn't enable them for us). Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | omap4: Remove duplicate CM_L3INIT_USBPHY_CLKCTRL reference and whitespacePaul Kocialkowski2016-03-151-2/+1
| | | | | | | | | | | | | | This removes a duplicate reference to CM_L3INIT_USBPHY_CLKCTRLin enable_basic_uboot_clocks. Also, a doubled whitespace is removed. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | omap-common: Remove deprecated arch_cpu_init codePaul Kocialkowski2016-03-151-13/+0
| | | | | | | | | | | | | | save_omap_boot_params is called from spl_board_init in the SPL context. Thus, there is no reason to duplicate that call on arch_cpu_init. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | omap-common: Rename set_muxconf_regs_essential to set_muxconf_regsPaul Kocialkowski2016-03-151-2/+2
| | | | | | | | | | | | | | There is no distinction between essential and non-essential mux configuration, so it doesn't make sense to have an "essential" prefix. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | omap4: Export jedec sdram timingsPaul Kocialkowski2016-03-151-1/+1
| | | | | | | | | | | | | | Individual boards might provide their own emif_get_device_timings function and use the jedec timings in their own way, hence those have to be exported. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | omap4: Export elpidia sdram timingsPaul Kocialkowski2016-03-151-1/+1
| | | | | | | | | | | | | | Individual boards might provide their own emif_get_device_timings function and use the elpidia timings in their own way, hence those have to be exported. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | omap4: Export elpidia sdram device detailsPaul Kocialkowski2016-03-151-2/+2
| | | | | | | | | | | | | | | | | | Individual boards might provide their own emif_get_device_details function and use elpidia device details in their own way, hence those have to be exported. This also wraps existing definitions with the proper ifdef logic. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | omap3: Use a define for reboot reason offsetPaul Kocialkowski2016-03-151-3/+5
| | | | | | | | | | | | | | | | This introduces a define for the offset to the reboot reason, rather than hardcoding it. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* | omap3: String-based reboot mode handlingPaul Kocialkowski2016-03-151-4/+10
| | | | | | | | | | | | | | | | This switches reboot mode handling to a string-based interface, that allows more flexibility to set a common interface with the next generations of OMAP devices. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2016-03-151-1/+12
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| * | imx: mx6: hdmi: handle overflow conditionPeng Fan2016-03-141-1/+12
| |/ | | | | | | | | | | | | | | | | | | | | | | If HDMI_IH_FC_STAT2_OVERFLOW_MASK is set, we need to do TMDS software reset and write to clear fc_invidconf register. We need minimum 3 times to write to clear the fc_invidconf register, so choose 5 loops here. Signed-off-by: Peng Fan <van.freenix@gmail.com> Signed-off-by: Sandor Yu <sandor.yu@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
* | arm64: define _image_binary_end to fix SPL_OF_CONTROLMasahiro Yamada2016-03-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To make SPL_OF_CONTROL work on ARM64 SoCs, _image_binary_end must be defined in the linker script. LD spl/u-boot-spl lib/built-in.o: In function `fdtdec_setup': lib/fdtdec.c:1186: undefined reference to `_image_binary_end' lib/fdtdec.c:1186: undefined reference to `_image_binary_end' make[1]: *** [spl/u-boot-spl] Error 1 make: *** [spl/u-boot-spl] Error 2 Note: CONFIG_SPL_SEPARATE_BSS must be defined as well on ARM64 SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA7: Move emif settings to board specific filesLokesh Vutla2016-03-141-147/+2
| | | | | | | | | | | | | | | | | | | | The newer versions of DRA7 boards has EEPROM populated with DDR size specified in it. Moving DRA7 specific emif related settings to board files so that emif settings can be identified based on EEPROM. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: DRA7: Enable EEPROM supportLokesh Vutla2016-03-141-0/+1
| | | | | | | | | | | | | | | | Enable EEPROM support for DRA74-evm. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: Various: Future-proof serial platdataAdam Ford2016-03-142-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few boards still use ns16550_platdata structures, but assume the structure is going to be in a specific order. By explicitly naming each entry, this should also help 'future-proof' in the event the structure changes. Tested on the Logic PD Torpedo + Wireless. I only changed a handful of devices that used the same syntax as the Logic board. Appologies if I missed one or stepped on toes. Thanks to Derald Woods and Alexander Graf. Signed-off-by: Adam Ford <aford173@gmail.com> V6: Add fix to arch/arm/cpu/armv7/am33xx/board.c V5: Add fix to arch/arm/cpu/arm926ejs/lpc32xx/devices.c V4: Fix subject heading V3: Remove reg_offset out in all the structs. It was reverted out, and and if it did exist, it would get initialized to 0 by default. V2: I hastily copy-pasted the boards without looking at the UART number. This addresses 3 boards that use UART3 and not UART1. Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | ARM: OMAP4+: Allow arch specfic code to use early DMLokesh Vutla2016-03-141-9/+21
| | | | | | | | | | | | | | | | | | | | | | Early system initialization is being done before initf_dm is being called in U-Boot. Then system will fail to boot if any of the DM enabled driver is being called in this system initialization code. So, rearrange the code a bit so that DM enabled drivers can be called during early system initialization. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA7: emif: Enable interleaving for higher address spaceLokesh Vutla2016-03-141-0/+2
| | | | | | | | | | | | | | | | Given that DRA7/OMAP5 SoCs can support more than 2GB of memory, enable interleaving for this higher memory to increase performance. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA7: emif: Check for enable bits before updating leveling outputLokesh Vutla2016-03-142-24/+48
| | | | | | | | | | | | | | | | | | Read and write leveling can be enabled independently. Check for these enable bits before updating the read and write leveling output values. This will allow to use the combination of software and hardware leveling. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA7: emif: Fix DDR init sequence during warm resetLokesh Vutla2016-03-141-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit (20fae0a - ARM: DRA7: DDR: Enable SR in Power Management Control) enables Self refresh mode by default and during warm reset the EMIF contents are preserved. After warm reset EMIF sees that it is idle and puts DDR in self-refresh. When in SR, leveling operations cannot be done as DDR can only accept SR exit command, so its hanging during warm reset. In order to fix this reset the power management control register before EMIF initialization if it is a warm reset. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA7: emif: Fix updating of refresh ctrl shadowLokesh Vutla2016-03-141-1/+5
| | | | | | | | | | | | | | | | On DRA7, refresh ctrl shadow should be updated with the final value. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | board: ti: AM57xx: Add detection logic for AM57xx-evmKipisz, Steven2016-03-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current AM57xx evm supports both BeagleBoard-X15 (http://beagleboard.org/x15) and AM57xx EVM (http://www.ti.com/tool/tmdxevm5728). The AM572x EValuation Module(EVM) provides an affordable platform to quickly start evaluation of Sitara. ARM Cortex-A15 AM57x Processors (AM5728, AM5726, AM5718, AM5716) and accelerate development for HMI, machine vision, networking, medical imaging and many other industrial applications. This EVM is based on the same BeagleBoard-X15 Chassis and adds mPCIe, mSATA, LCD, touchscreen, Camera, push button and TI's wlink8 offering. Since the EEPROM contents are compatible between the BeagleBoard-X15 and the AM57xx-evm, we add support for the detection logic to enable support for various user programmable scripting capability. NOTE: U-boot configuration is currently a superset of AM57xx evm and BeagleBoard-X15 and no additional configuration tweaking is needed. This change also sets up the stage for future support of TI AM57xx EVMs to the same base bootloader build. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: OMAP4/5: Add generic board detection hookKipisz, Steven2016-03-141-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many TI EVMs have capability to store relevant board information such as DDR description in EEPROM. Further many pad configuration variations can occur as part of revision changes in the platform. In-order to support these at runtime, we for a board detection hook which is available for override from board files that may desire to do so. NOTE: All TI EVMs are capable of detecting board information based on early clocks that are configured. However, in case of additional needs this can be achieved within the override logic from within the board file. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: OMAP4/5: Centralize early clock initializationKipisz, Steven2016-03-142-4/+20
|/ | | | | | | | | | | | | | | | | | | | | | | | | | Early clock initialization is currently done in two stages for OMAP4/5 SoCs. The first stage is the initialization of console clocks and then we initialize basic clocks for functionality necessary for SoC initialization and basic board functionality. By splitting up prcm_init and centralizing this clock initialization, we setup the code for follow on patches that can do board specific initialization such as board detection which will depend on these basic clocks. As part of this change, since the early clock initialization is centralized, we no longer need to expose the console clock initialization. NOTE: we change the sequence slightly by initializing console clocks timer after the io settings are complete, but this is not expected to have any functioanlity impact since we setup the basic IO drive strength initialization as part of do_io_settings. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap3: Use raw SPL by default for mmc1Alexander Graf2016-03-081-2/+0
| | | | | | | | | | | Now that we fall back to the FS code path when we don't find u-boot at the raw sector offset, there is no good reason to not default to raw boot. With this patch, I can successfully boot u-boot from a raw sector offset on beagle-xm. Signed-off-by: Alexander Graf <agraf@suse.de>
* sniper: Various minor cleanups, missing Kconfig configs and reorganisationPaul Kocialkowski2016-02-291-1/+1
| | | | | | | | This introduces some minor cleanups, regarding aspects such as board name, code and headers organization as well as deprecated and missing config options. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: start.S: fix typoYuichiro Goto2016-02-297-7/+7
| | | | | | Fix typo in comment about position of 'A' bit in several start.S. Signed-off-by: Yuichiro Goto <goto.yuichiro@espark.co.jp>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-02-243-0/+74
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| * armv7: ls102xa: Move smmu and stream id initialization into the common soc codeAlison Wang2016-02-241-0/+48
| | | | | | | | | | | | | | | | The initialization for smmu and stream id is moved into the common soc code. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/fsl-layerscape: fdt: add fixup for Fman ucodeQianyu Gong2016-02-241-0/+7
| | | | | | | | | | | | | | Add fdt fixup to insert Fman firmware into the device tree. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/ls1043a: Implement workaround for erratum A009660Mingkai Hu2016-02-241-0/+19
| | | | | | | | | | | | | | | | | | Memory controller performance is not optimal with default internal target queue register value, write required value for optimal DDR performance. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | sunxi: H3: Add support for the host usb-physJelle van der Waa2016-02-231-7/+28
|/ | | | | | | | Add support for phy 1-3. Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> [hdegoede@redhat.com: use setclrbits_le32 instead of read-modify-write] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-02-213-3/+177
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| * imx: mx7d: isolate resources to domain 0 for A7 corePeng Fan2016-02-211-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current design, if any peripheral was assigned to both A7 and M4, it will receive ipg_stop or ipg_wait when any of the 2 platforms enter low power mode. We will have a risk that, if A7 enter wait, M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait asserted same time. Also if M4 enters stop mode, A7 will have no chance to access the peripheral. There are 26 peripherals affected by this IC issue: SIM2(sim2/emvsim2) SIM1(sim1/emvsim1) UART1/UART2/UART3/UART4/UART5/UART6/UART7 SAI1/SAI2/SAI3 WDOG1/WDOG2/WDOG3/WDOG4 GPT1/GPT2/GPT3/GPT4 PWM1/PWM2/PWM3/PWM4 ENET1/ENET2 Software Workaround: The solution is to set the peripherals to Domain0 by A core, since A core in Domain0. The peripherals which will be used by M4, will be set to Domain1 by M4. For example, A core set WDOG4 to domain0, but when M4 boots up, M4 will set WDOG4 to domain1, because M4 will use WDOG4. So the peripherals are not shared by them. This way requires the uboot implemented the RDC driver and set the 26 IPs above to domain 0 only. M4 image will set the M4 to domain 1 and set peripheral which it will use to domain 1. This patch enables the CONFIG_IMX_RDC and CONFIG_IMX_BOOTAUX for i.MX7D SABRESD board, and setup the 26 IP resources to domain 0. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx7: implement functions to boot auxiliary corePeng Fan2016-02-211-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up. arch_auxiliary_core_check_up is used to check whether M4 is running or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will use the pc and stack which is set in arch_auxiliary_core_up to set R15 and R13 register and boot. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx6: implement functions to boot auxiliary corePeng Fan2016-02-211-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up. arch_auxiliary_core_check_up is used to check whether M4 is running or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will use the pc and stack which is set in arch_auxiliary_core_up to set R15 and R13 register and boot. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx7d: clock support for RDCPeng Fan2016-02-211-0/+6
| | | | | | | | | | | | If CONFIG_IMX_RDC is enabled, enable clock for RDC and SEMAPHORE. Signed-off-by: Peng Fan <peng.fan@nxp.com>
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