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* ARM: uniphier: refactor LED functionMasahiro Yamada2015-09-259-128/+96
| | | | | | | | | | The macro, led_write(), is now only used in C sources. There is no more reason to keep the tricky assembly macro. Replace it with a new C function led_puts(). Also, rename board.h to micro-support-card.h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove useless wrapper functionsMasahiro Yamada2015-09-253-17/+10
| | | | | | | | | | The wrapper functions, uniphier_board_*, are just making function calls complex. Remove them. Also, use empty inline functions in case CONFIG_MICRO_SUPPORT_CARD is disabled, so that prototype checking works. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove unused header fileMasahiro Yamada2015-09-251-24/+0
| | | | | | | This has been unused since commit f4e190e317b8 ("ARM: uniphier: enable SPL_OF_CONTROL"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: parse device tree to determine DRAM base and sizeMasahiro Yamada2015-09-253-26/+48
| | | | | | | Device tree specifies the available memory ranges in its "/memory" node. Use it to simplify the CONFIG defines. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove ifdef CONFIG_{SOC} conditionals from sg-regs.hMasahiro Yamada2015-09-2511-119/+109
| | | | | | | To achieve the complete run-time configuration by device trees, ifdef conditionals in header files are not preferable. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: change the external bus address mappingMasahiro Yamada2015-09-255-20/+25
| | | | | | | | | | | | | | | | In UniPhier SoCs before ProXstream2 and PH1-LD6b, two address spaces 0x00000000 - 0x0fffffff 0x40000000 - 0x4fffffff are both mapped to the external bus (also called system bus), so either was OK. In the newest two SoCs, the former (0x00000000 - 0x0fffffff) is assigned for the serial NOR interface. Going forward, use the latter for the external bus. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: uniphier: enable setexpr commandMasahiro Yamada2015-09-254-4/+0
| | | | | | | This command will be used in the next commit to calculate base-offseted addresses. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: drop DCC micro support card supportMasahiro Yamada2015-09-2516-311/+29
| | | | | | | | | | Historically (for compatibility with very old platforms), two different types of micro support cards have been used with the UniPhier SoC development boards. It has been painful to maintain both. Having one of them is enough. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: uniphier: drop ad-hoc input enable settingsMasahiro Yamada2015-09-257-51/+7
| | | | | | | | | | These input enable settings are handled by the pinctrl drivers. Because the external bus pins are input-enabled by default, on-board devices such as LED still work fine even with this delayed input enabling. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: drop ad-hoc early pin-muxing settingsMasahiro Yamada2015-09-256-82/+7
| | | | | | | | | As the UniPhier serial driver had already switched to Drive Model and the pinctrl drivers are now enabled, these pin-muxing settings are properly handled by the pinctrl drivers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: uniphier: enable PINCTRL and SPL_PINCTRLMasahiro Yamada2015-09-253-0/+6
| | | | | | Now, UniPhier SoCs are ready to enable pinctrl drivers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: prepare device trees to use pinctrl in SPLMasahiro Yamada2015-09-254-4/+60
| | | | | | | | | | | | | | | Add "u-boot,dm-pre-reloc" for device nodes we want in SPL DTB (spl/u-boot-spl.dtb). The "soc" node (this is simple-bus node) also needs the property to bind the pinctrl node located under it. I am collecting this U-Boot specific hack to the bottom of board DTS rather than inserting "u-boot,dm-pre-reloc" into SoC DTSI. My goal is to sync DTSI with Linux for easier maintenance. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: uniphier: increase CONFIG_SYS_MALLOC_F_LEN to bind all nodesMasahiro Yamada2015-09-253-0/+3
| | | | | | | | | | | | | | | | | | In the next commit, I will add "u-boot,dm-pre-reloc" to the "soc" (simple-bus) nodes in UniPhier device trees. But, before that, CONFIG_SYS_MALLOC_F_LEN must be increased. Adding "u-boot,dm-pre-reloc" to a simple-bus node causes it to bind all of its child nodes. (See simple_bus_post_bind() function) Actually, I want only UART0 and pinctrl to be bound in SPL and before relocation in U-boot proper. But, with "u-boot,dm-pre-reloc" in the simple-bus node, all the other unwanted nodes are also bound. The default value for CONFIG_SYS_MALLOC_F_LEN, 0x400, is not enough for that. Increase the pre-reloc malloc size to 0x2000, hoping the root cause will be fixed later. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: enable simple-bus driver for SPLMasahiro Yamada2015-09-253-0/+3
| | | | | | | | | In UniPhier device trees, pinctrl device nodes are located under the simple-bus (AMBA). This is needed to bind pinctrl devices in SPL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: add UniPhier PH1-LD6b pinctrl driverMasahiro Yamada2015-09-253-0/+140
| | | | | | Add pin configuration and pinmux support for UniPhier PH1-LD6b SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: add UniPhier ProXstream2 pinctrl driverMasahiro Yamada2015-09-253-0/+147
| | | | | | | Add pin configuration and pinmux support for UniPhier ProXstream2 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: add UniPhier PH1-Pro5 pinctrl driverMasahiro Yamada2015-09-253-0/+151
| | | | | | Add pin configuration and pinmux support for UniPhier PH1-Pro5 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: add UniPhier PH1-sLD8 pinctrl driverMasahiro Yamada2015-09-253-0/+148
| | | | | | Add pin configuration and pinmux support for UniPhier PH1-sLD8 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: add UniPhier PH1-Pro4 pinctrl driverMasahiro Yamada2015-09-253-0/+137
| | | | | | Add pin configuration and pinmux support for UniPhier PH1-Pro4 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: add UniPhier PH1-LD4 pinctrl driverMasahiro Yamada2015-09-253-0/+141
| | | | | | Add pin configuration and pinmux support for UniPhier PH1-LD4 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: add UniPhier pinctrl core supportMasahiro Yamada2015-09-236-0/+278
| | | | | | | The core support for the pinctrl drivers for all the UniPhier SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pinctrl: move dm_scan_fdt_node() out of pinctrl uclassMasahiro Yamada2015-09-192-6/+17
| | | | | | | | | | | | | | | | | | | | | Commit c5acf4a2b3c6 ("pinctrl: Add the concept of peripheral IDs") added some additional change that was not mentioned in the git-log. That commit added dm_scan_fdt_node() in the pinctrl uclass binding. It should be handled by the simple-bus driver or the low-level driver, not by the pinctrl framework. I guess Simon's motivation was to bind GPIO banks located under the Rockchip pinctrl device. It is true some chips have sub-devices under their pinctrl devices, but it is basically SoC-specific matter. This commit partly reverts commit c5acf4a2b3c6 to keep the only pinctrl-generic features in the uclass. The dm_scan_fdt_node() should be called from the rk3288_pinctrl driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-x86Tom Rini2015-09-1711-70/+400
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| * x86: quark: Configure MTRR to enable cacheBin Meng2015-09-163-0/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs are accessed indirectly via the message port and not the traditional MSR mechanism. Only UC, WT and WB cache types are supported. We configure all the fixed range MTRRs with common values (VGA RAM as UC, others as WB) and 3 variable range MTRRs for ROM/eSRAM/RAM as WB, which significantly improves the boot time performance. With this commit, it takes only 2 seconds for U-Boot to boot to shell on Intel Galileo board. Previously it took about 6 seconds. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * x86: doc: Add DMI to the TODO listBin Meng2015-09-161-0/+2
| | | | | | | | | | | | | | | | Desktop Management Interface (DMI) is not supported by U-Boot now. Add it to the TODO list. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: doc: Document some porting hints about Intel QuarkBin Meng2015-09-161-0/+24
| | | | | | | | | | | | | | | | Document porting considerations for Intel Quark based board, including MRC parameters and PCIe initialization. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: galileo: Add PCIe root port IRQ routingBin Meng2015-09-161-0/+12
| | | | | | | | | | | | | | | | Now we have enabled PCIe root port on Quark SoC, add its PIRQ routing information in the device tree as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Initialize thermal sensor properlyBin Meng2015-09-162-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Thermal sensor on Quark SoC needs to be properly initialized per Quark firmware writer guide, otherwise when booting Linux kernel, it triggers system shutdown because of wrong temperature in the thermal sensor is detected by the kernel driver (see below): [ 5.119819] thermal_sys: Critical temperature reached(206 C),shutting down [ 5.128997] Failed to start orderly shutdown: forcing the issue [ 5.135495] Emergency Sync complete Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Lock HMBOUND register before jumping to kernelBin Meng2015-09-162-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When Linux kernel boots, it hangs at: [ 0.829408] Intel Quark side-band driver registered This happens when Quark kernel Isolated Memory Region (IMR) driver tries to lock an IMR register to protect kernel's text and rodata sections. However in order to have IMR function correctly, HMBOUND register must be locked otherwise the system just hangs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Convert to use clrbits, setbits, clrsetbits macrosBin Meng2015-09-161-51/+21
| | | | | | | | | | | | | | Change existing codes to use clrbits, setbits, clrsetbits macros. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Add clrbits, setbits, clrsetbits macros for message port accessBin Meng2015-09-161-0/+31
| | | | | | | | | | | | | | | | | | On Intel Quark, lots of registers on the message port need be programmed. Add handy clrbits, setbits, clrsetbits macros for message port access. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: galileo: Enable random mac address for QuarkBin Meng2015-09-161-0/+1
| | | | | | | | | | | | | | | | | | | | Not like other Intel Ethernet controllers (e.g.: E1000), Intel Quark SoC integrated designware Ethernet controller does not have a chipset defined way to store/restore mac address. Enable random mac address so that we can use Ethernet even without 'ethaddr'. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Add PCIe/USB static register programming after memory initBin Meng2015-09-163-0/+87
| | | | | | | | | | | | | | | | | | This adds static register programming for PCIe and USB after memory init as required by Quark firmware writer guide. Although not doing this did not cause any malfunction, just do it for safety. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Convert to use driver model eth on quark/galileoBin Meng2015-09-162-20/+1
| | | | | | | | | | | | | | | | Convert to use DM version of Designware ethernet driver on Intel quark/galileo. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * net: designware: Add support to PCI designware devicesBin Meng2015-09-161-0/+42
| | | | | | | | | | | | | | | | The Designware ethernet controller is also seen on PCI bus, e.g. on Intel Quark SoC. Add this support in the DM version driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: pci: Add an inline API to test if a device is on a PCI busBin Meng2015-09-162-2/+13
| | | | | | | | | | | | | | | | Introduce device_is_on_pci_bus() which can be utilized by driver to test if a device is on a PCI bus. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-dmTom Rini2015-09-171-0/+1
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| * | dts: do not cut down pinctrl-0 and pinctrl-names for SPL full-pinctrlMasahiro Yamada2015-09-161-0/+1
| |/ | | | | | | | | | | | | | | These properties are necessary to use full-featured pinctrl drivers in SPL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* | ARM: tegra114: Clear IDDQ when enabling PLLCThierry Reding2015-09-162-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Enabling a PLL while IDDQ is high. The Linux kernel checks for this condition and warns about it verbosely, so while this seems to work fine, fix it up according to the programming guidelines provided in the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup Sequence"). The Tegra114 TRM doesn't contain this information, but the programming of PLLC is the same on Tegra114 and Tegra124. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra124: Clear IDDQ when enabling PLLCThierry Reding2015-09-162-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Enabling a PLL while IDDQ is high. The Linux kernel checks for this condition and warns about it verbosely, so while this seems to work fine, fix it up according to the programming guidelines provided in the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup Sequence"). Reported-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: Add Tegra20 SPI device nodesMirza Krak2015-09-161-0/+57
| | | | | | | | | | | | | | Add the device tree node for the SPI controllers found on Tegra20 SOCs. Signed-off-by: Mirza Krak <mirza.krak@hostmobility.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | p2571: Remove hard-coded counter frequencyThierry Reding2015-09-161-2/+0
| | | | | | | | | | | | | | | | | | | | | | The counter frequency is derived from clk_m on Tegra, but that clock can be configured by the primary bootloader to run at the same frequency as the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most typically 19.2 MHz). Remove the hard-coded frequency and allow the timer setup code to query the correct value at runtime. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | p2371: Remove hard-coded counter frequencyThierry Reding2015-09-161-3/+0
| | | | | | | | | | | | | | | | | | | | | | The counter frequency is derived from clk_m on Tegra, but that clock can be configured by the primary bootloader to run at the same frequency as the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most typically 19.2 MHz). Remove the hard-coded frequency and allow the timer setup code to query the correct value at runtime. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | e2220-1170: Remove hard-coded counter frequencyThierry Reding2015-09-161-3/+0
| | | | | | | | | | | | | | | | | | | | | | The counter frequency is derived from clk_m on Tegra, but that clock can be configured by the primary bootloader to run at the same frequency as the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most typically 19.2 MHz). Remove the hard-coded frequency and allow the timer setup code to query the correct value at runtime. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: clk_m is the architected timer source clockThierry Reding2015-09-163-10/+8
| | | | | | | | | | | | | | | | | | | | | | While clk_m and the oscillator run at the same frequencies on Tegra114 and Tegra124, clk_m is the proper source for the architected timer. On more recent Tegra generations, Tegra210 and later, both the oscillator and clk_m can run at different frequencies. clk_m will be divided down from the oscillator. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: Implement clk_mThierry Reding2015-09-168-2/+31
| | | | | | | | | | | | | | | | | | | | On currently supported SoCs, clk_m always runs at the same frequency as the oscillator input. However newer SoC generations such as Tegra210 no longer have that restriction. Prepare for that by separating clk_m from the oscillator clock and allow SoC code to override the clk_m rate. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | armv8: Make COUNTER_FREQUENCY optionalThierry Reding2015-09-161-0/+2
| | | | | | | | | | | | | | | | | | | | Some platforms have the means to determine the counter frequency at runtime, so give them an opportunity to do so. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: replace V_PROMPT define with kconfigStephen Warren2015-09-168-4/+4
| | | | | | | | | | | | | | | | | | Commit 181bd9dc61d2 "kconfig: add config option for shell prompt" replaced define V_PROMPT with Kconfig option SYS_PROMPT. This crossed with patches adding Tegra T210 boards. Migrate the boards to the new scheme. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: fix PLLP frequency calc on T210Stephen Warren2015-09-161-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AFAIK, for all PLLs on all Tegra SoCs, the primary PLL output frequency is (input * m) / (n * p). However, PLLP's primary output (pllP_out0) on T210 is the VCO output, and divp is not applied. pllP_out2 does have divp applied. All other pllP_outN are divided down from pllP_out0. We only support pllP_out0 in U-Boot at the time of writing. Fix clock_get_rate() to handle this special case. This corrects the returned rate for PLLP to be 408MHz rather than 204MHz. In turn, this causes high enough dividers to be calculated for the various peripheral clocks that feed off of PLLP. Without this, some peripherals failed to operate correctly. For instance, one of my SD cards worked perfectly but an older (presumably slower) card could not be read. Note that prior to commit 722e000ccd72 "Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.", the calculated PLL frequency was 816MHz since the wrong values were being extracted from the PLLP divider register. This caused overly large peripheral dividers to be calculated, which while wrong, didn't cause any correctness issues; things simply ran slower than they could. Reported-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: fix COUNTER_FREQUENCY for T210Stephen Warren2015-09-164-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While T210 boards all have 38.4MHz crystals, per the TRM, the only supported configuration is to divide the crystal frequency by 2 to generate clk_m, which is what feeds the ARM generic timers amongst other things. Fix the value of COUNTER_FREQUENCY to reflect this divide-by-2. When I queried the 19.2 value in Tom's original T210 patches, I wasn't aware of this extra divide-by-2, and didn't notice any effect from the incorrect value, since its only used if U-Boot is booted in EL3, whereas I'm booting it in EL2. Reported-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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