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| author | Bin Meng <bmeng.cn@gmail.com> | 2015-09-11 03:24:35 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-09-16 19:53:52 -0600 |
| commit | 8b7ee66cec950899eace0caf729cf2100155020a (patch) | |
| tree | 9e348dac0955a92aca1ff0e89f6d0cf0316056e4 | |
| parent | 1e0f226362ffd2bd8c1a238af1d1b21ea86d3111 (diff) | |
| download | talos-obmc-uboot-8b7ee66cec950899eace0caf729cf2100155020a.tar.gz talos-obmc-uboot-8b7ee66cec950899eace0caf729cf2100155020a.zip | |
net: designware: Add support to PCI designware devices
The Designware ethernet controller is also seen on PCI bus, e.g.
on Intel Quark SoC. Add this support in the DM version driver.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
| -rw-r--r-- | drivers/net/designware.c | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/drivers/net/designware.c b/drivers/net/designware.c index ae78d21db6..6433896eec 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -14,6 +14,7 @@ #include <errno.h> #include <miiphy.h> #include <malloc.h> +#include <pci.h> #include <linux/compiler.h> #include <linux/err.h> #include <asm/io.h> @@ -558,6 +559,22 @@ static int designware_eth_write_hwaddr(struct udevice *dev) return _dw_write_hwaddr(priv, pdata->enetaddr); } +static int designware_eth_bind(struct udevice *dev) +{ +#ifdef CONFIG_DM_PCI + static int num_cards; + char name[20]; + + /* Create a unique device name for PCI type devices */ + if (device_is_on_pci_bus(dev)) { + sprintf(name, "eth_designware#%u", num_cards++); + device_set_name(dev, name); + } +#endif + + return 0; +} + static int designware_eth_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); @@ -565,6 +582,23 @@ static int designware_eth_probe(struct udevice *dev) u32 iobase = pdata->iobase; int ret; +#ifdef CONFIG_DM_PCI + /* + * If we are on PCI bus, either directly attached to a PCI root port, + * or via a PCI bridge, fill in platdata before we probe the hardware. + */ + if (device_is_on_pci_bus(dev)) { + pci_dev_t bdf = pci_get_bdf(dev); + + dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); + iobase &= PCI_BASE_ADDRESS_MEM_MASK; + iobase = pci_mem_to_phys(bdf, iobase); + + pdata->iobase = iobase; + pdata->phy_interface = PHY_INTERFACE_MODE_RMII; + } +#endif + debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); priv->mac_regs_p = (struct eth_mac_regs *)iobase; priv->dma_regs_p = (struct eth_dma_regs *)(iobase + DW_DMA_BASE_OFFSET); @@ -617,10 +651,18 @@ U_BOOT_DRIVER(eth_designware) = { .id = UCLASS_ETH, .of_match = designware_eth_ids, .ofdata_to_platdata = designware_eth_ofdata_to_platdata, + .bind = designware_eth_bind, .probe = designware_eth_probe, .ops = &designware_eth_ops, .priv_auto_alloc_size = sizeof(struct dw_eth_dev), .platdata_auto_alloc_size = sizeof(struct eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; + +static struct pci_device_id supported[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) }, + { } +}; + +U_BOOT_PCI_DEVICE(eth_designware, supported); #endif |
