diff options
Diffstat (limited to 'board')
51 files changed, 631 insertions, 808 deletions
diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds index c76728a7fb..ef4a25bc3c 100644 --- a/board/actux1/u-boot.lds +++ b/board/actux1/u-boot.lds @@ -61,6 +61,9 @@ SECTIONS } . = ALIGN (4); + + __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*) @@ -74,17 +77,23 @@ SECTIONS _end = .; +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + .bss_start __rel_dyn_start (OVERLAY) : { KEEP(*(.__bss_start)); + __bss_base = .; } - .bss __bss_start (OVERLAY) : { + .bss __bss_base (OVERLAY) : { *(.bss*) . = ALIGN(4); - __bss_end = .; + __bss_limit = .; } - .bss_end __bss_end (OVERLAY) : { - KEEP(*(__bss_end)); + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); } /DISCARD/ : { *(.dynstr*) } diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds index 984f70e510..00ad8b71cd 100644 --- a/board/actux2/u-boot.lds +++ b/board/actux2/u-boot.lds @@ -61,6 +61,9 @@ SECTIONS } . = ALIGN (4); + + __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*) @@ -74,17 +77,23 @@ SECTIONS _end = .; +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + .bss_start __rel_dyn_start (OVERLAY) : { KEEP(*(.__bss_start)); + __bss_base = .; } - .bss __bss_start (OVERLAY) : { + .bss __bss_base (OVERLAY) : { *(.bss*) . = ALIGN(4); - __bss_end = .; + __bss_limit = .; } - .bss_end __bss_end (OVERLAY) : { - KEEP(*(__bss_end)); + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); } /DISCARD/ : { *(.dynstr*) } diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds index fc48cf03fd..44b990ee7f 100644 --- a/board/actux3/u-boot.lds +++ b/board/actux3/u-boot.lds @@ -61,6 +61,9 @@ SECTIONS } . = ALIGN (4); + + __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*) @@ -74,17 +77,23 @@ SECTIONS _end = .; +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + .bss_start __rel_dyn_start (OVERLAY) : { KEEP(*(.__bss_start)); + __bss_base = .; } - .bss __bss_start (OVERLAY) : { + .bss __bss_base (OVERLAY) : { *(.bss*) . = ALIGN(4); - __bss_end = .; + __bss_limit = .; } - .bss_end __bss_end (OVERLAY) : { - KEEP(*(__bss_end)); + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); } /DISCARD/ : { *(.dynstr*) } diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds index dd9d52db4b..1daa1b3b90 100644 --- a/board/ait/cam_enc_4xx/u-boot-spl.lds +++ b/board/ait/cam_enc_4xx/u-boot-spl.lds @@ -25,7 +25,7 @@ */ MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ - LENGTH = CONFIG_SPL_MAX_SIZE } + LENGTH = CONFIG_SPL_MAX_FOOTPRINT } OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) @@ -38,7 +38,7 @@ SECTIONS .text : { __start = .; - arch/arm/cpu/arm926ejs/start.o (.text) + arch/arm/cpu/arm926ejs/start.o (.text*) *(.text*) } >.sram diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 229c237839..cc071d6d38 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -304,6 +304,9 @@ int board_mmc_init(bd_t *bis) usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[1].max_bus_width = 4; + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { switch (index) { case 0: @@ -328,11 +331,6 @@ int board_mmc_init(bd_t *bis) } #endif -u32 get_board_rev(void) -{ - return 0x63000; -} - #ifdef CONFIG_MXC_SPI iomux_v3_cfg_t const ecspi1_pads[] = { /* SS1 */ diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds index bc34fb5819..b1b8701811 100644 --- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds +++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds @@ -25,7 +25,7 @@ */ MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ - LENGTH = CONFIG_SPL_MAX_SIZE } + LENGTH = CONFIG_SPL_MAX_FOOTPRINT } OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) @@ -38,7 +38,7 @@ SECTIONS .text : { __start = .; - arch/arm/cpu/arm926ejs/start.o (.text) + arch/arm/cpu/arm926ejs/start.o (.text*) *(.text*) } >.sram diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds index 2557830f94..596a9e08ea 100644 --- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds +++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds @@ -34,15 +34,15 @@ SECTIONS . = ALIGN(4); .text : { - arch/arm/cpu/arm926ejs/start.o (.text) - arch/arm/cpu/arm926ejs/davinci/libdavinci.o (.text) - drivers/mtd/nand/libnand.o (.text) + arch/arm/cpu/arm926ejs/start.o (.text*) + arch/arm/cpu/arm926ejs/davinci/libdavinci.o (.text*) + drivers/mtd/nand/libnand.o (.text*) *(.text*) } . = ALIGN(4); - .rodata : { *(.rodata) } + .rodata : { *(.rodata*) } . = ALIGN(4); .data : { @@ -58,6 +58,7 @@ SECTIONS } . = ALIGN(4); + __image_copy_end = .; __rel_dyn_start = .; __rel_dyn_end = .; __dynsym_start = .; diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds index b13d3e1ec3..6d4b1875c5 100644 --- a/board/dvlhost/u-boot.lds +++ b/board/dvlhost/u-boot.lds @@ -61,6 +61,9 @@ SECTIONS } . = ALIGN (4); + + __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*) @@ -74,17 +77,23 @@ SECTIONS _end = .; +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + .bss_start __rel_dyn_start (OVERLAY) : { KEEP(*(.__bss_start)); + __bss_base = .; } - .bss __bss_start (OVERLAY) : { + .bss __bss_base (OVERLAY) : { *(.bss*) . = ALIGN(4); - __bss_end = .; + __bss_limit = .; } - .bss_end __bss_end (OVERLAY) : { - KEEP(*(__bss_end)); + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); } /DISCARD/ : { *(.dynstr*) } diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds index 264c4e80ad..4969960001 100644 --- a/board/freescale/mx31ads/u-boot.lds +++ b/board/freescale/mx31ads/u-boot.lds @@ -37,23 +37,23 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - arch/arm/cpu/arm1136/start.o (.text) - board/freescale/mx31ads/libmx31ads.o (.text) - arch/arm/lib/libarm.o (.text) - net/libnet.o (.text) - drivers/mtd/libmtd.o (.text) + arch/arm/cpu/arm1136/start.o (.text*) + board/freescale/mx31ads/libmx31ads.o (.text*) + arch/arm/lib/libarm.o (.text*) + net/libnet.o (.text*) + drivers/mtd/libmtd.o (.text*) . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o(.text) + common/env_embedded.o(.text*) - *(.text) + *(.text*) } . = ALIGN(4); - .rodata : { *(.rodata) } + .rodata : { *(.rodata*) } . = ALIGN(4); .data : { - *(.data) + *(.data*) } . = ALIGN(4); @@ -80,17 +80,23 @@ SECTIONS _end = .; +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + .bss_start __rel_dyn_start (OVERLAY) : { KEEP(*(.__bss_start)); + __bss_base = .; } - .bss __bss_start (OVERLAY) : { + .bss __bss_base (OVERLAY) : { *(.bss*) . = ALIGN(4); - __bss_end = .; + __bss_limit = .; } - .bss_end __bss_end (OVERLAY) : { - KEEP(*(__bss_end)); + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); } /DISCARD/ : { *(.bss*) } diff --git a/board/freescale/mx31pdk/Makefile b/board/freescale/mx31pdk/Makefile index 5b7cafd9f6..b91072285a 100644 --- a/board/freescale/mx31pdk/Makefile +++ b/board/freescale/mx31pdk/Makefile @@ -27,6 +27,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +ifdef CONFIG_SPL_BUILD +SOBJS := lowlevel_init.o +endif COBJS := mx31pdk.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/freescale/mx31pdk/config.mk b/board/freescale/mx31pdk/config.mk deleted file mode 100644 index de2c6429c5..0000000000 --- a/board/freescale/mx31pdk/config.mk +++ /dev/null @@ -1,5 +0,0 @@ -ifdef CONFIG_NAND_SPL -CONFIG_SYS_TEXT_BASE = 0x87ec0000 -else -CONFIG_SYS_TEXT_BASE = 0x87f00000 -endif diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index 895396cd62..49158bd90d 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -36,6 +36,14 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong bootflag) +{ + relocate_code(CONFIG_SPL_TEXT_BASE); + asm volatile("ldr pc, =nand_boot"); +} +#endif + int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c index 2fc8570f23..8d433a3d86 100644 --- a/board/freescale/mx53ard/mx53ard.c +++ b/board/freescale/mx53ard/mx53ard.c @@ -58,6 +58,71 @@ void dram_init_banksize(void) gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; } +#ifdef CONFIG_NAND_MXC +static void setup_iomux_nand(void) +{ + u32 i, reg; + #define M4IF_GENP_WEIM_MM_MASK 0x00000001 + #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000 + + reg = __raw_readl(M4IF_BASE_ADDR + 0xc); + reg &= ~M4IF_GENP_WEIM_MM_MASK; + __raw_writel(reg, M4IF_BASE_ADDR + 0xc); + for (i = 0x4; i < 0x94; i += 0x18) { + reg = __raw_readl(WEIM_BASE_ADDR + i); + reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK; + __raw_writel(reg, WEIM_BASE_ADDR + i); + } + + mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_CS1, PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_RB0, PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU); + mxc_request_iomux(MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_CLE, PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_ALE, PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B, PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU); + mxc_request_iomux(MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B, PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B, PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA0, PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA1, PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA2, PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA3, PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA4, PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA5, PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA6, PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA7, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA7, PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); +} +#else +static void setup_iomux_nand(void) +{ +} +#endif + static void setup_iomux_uart(void) { /* UART1 RXD */ @@ -277,6 +342,7 @@ static void weim_cs1_settings(void) int board_early_init_f(void) { + setup_iomux_nand(); setup_iomux_uart(); return 0; } diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 91cc0073bd..aec3286e25 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -26,6 +26,7 @@ #include <asm/errno.h> #include <asm/gpio.h> #include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> #include <mmc.h> #include <fsl_esdhc.h> #include <miiphy.h> @@ -216,6 +217,23 @@ int board_init(void) return 0; } +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + return 0; +} + int checkboard(void) { int rev = mx6sabre_rev(); diff --git a/board/freescale/mx6qsabrelite/README b/board/freescale/mx6qsabrelite/README index 6f2f5343de..12a9c856cf 100644 --- a/board/freescale/mx6qsabrelite/README +++ b/board/freescale/mx6qsabrelite/README @@ -40,7 +40,7 @@ enter the following commands: MX6Q SABRELITE U-Boot > mmc dev 0 MX6Q SABRELITE U-Boot > mmc read 0x10800000 0 200 - MX6Q SABRELITE U-Boot > sf probe 1 + MX6Q SABRELITE U-Boot > sf probe MX6Q SABRELITE U-Boot > sf erase 0 0x40000 MX6Q SABRELITE U-Boot > sf write 0x10800000 0 0x40000 @@ -63,7 +63,7 @@ https://wiki.linaro.org/Boards/MX6QSabreLite To build U-Boot for the SabreLite board: make mx6qsabrelite_config - make u-boot.imx + make To copy the resulting u-boot.imx to the SD card: diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 5b69a6d2de..9f9cac82c4 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -274,6 +274,9 @@ int board_mmc_init(bd_t *bis) usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[1].max_bus_width = 4; + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { switch (index) { case 0: @@ -298,11 +301,6 @@ int board_mmc_init(bd_t *bis) } #endif -u32 get_board_rev(void) -{ - return 0x63000 ; -} - #ifdef CONFIG_MXC_SPI iomux_v3_cfg_t const ecspi1_pads[] = { /* SS1 */ diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c b/board/freescale/mx6qsabresd/mx6qsabresd.c index 2b3926aaf3..0d7cb9efd0 100644 --- a/board/freescale/mx6qsabresd/mx6qsabresd.c +++ b/board/freescale/mx6qsabresd/mx6qsabresd.c @@ -26,10 +26,12 @@ #include <asm/errno.h> #include <asm/gpio.h> #include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> #include <mmc.h> #include <fsl_esdhc.h> #include <miiphy.h> #include <netdev.h> + DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ @@ -145,21 +147,34 @@ struct fsl_esdhc_cfg usdhc_cfg[3] = { int board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; switch (cfg->esdhc_base) { case USDHC2_BASE_ADDR: - return !gpio_get_value(USDHC2_CD_GPIO); + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; case USDHC3_BASE_ADDR: - return !gpio_get_value(USDHC3_CD_GPIO); - default: - return 1; /* eMMC/uSDHC4 is always present */ + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + case USDHC4_BASE_ADDR: + ret = 1; /* eMMC/uSDHC4 is always present */ + break; } + + return ret; } int board_mmc_init(bd_t *bis) { int i; + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 SD2 + * mmc1 SD3 + * mmc2 eMMC + */ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: @@ -239,11 +254,6 @@ int board_eth_init(bd_t *bis) return 0; } -u32 get_board_rev(void) -{ - return 0x63000; -} - int board_early_init_f(void) { setup_iomux_uart(); @@ -259,6 +269,26 @@ int board_init(void) return 0; } +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + /* 8 bit bus width */ + {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + return 0; +} + int checkboard(void) { puts("Board: MX6Q-SabreSD\n"); diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 2bac916576..0d4679dfb9 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -24,7 +24,7 @@ #include <twl4030.h> #include <netdev.h> #include <asm/gpio.h> -#include <asm/arch/omap_gpmc.h> +#include <asm/omap_gpmc.h> #include <asm/io.h> #include <asm/arch/mem.h> #include <asm/arch/mmc_host_def.h> diff --git a/board/karo/tx25/Makefile b/board/karo/tx25/Makefile index 9617fa5288..c26bf36b55 100644 --- a/board/karo/tx25/Makefile +++ b/board/karo/tx25/Makefile @@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := tx25.o +ifdef CONFIG_SPL_BUILD SOBJS := lowlevel_init.o +endif +COBJS := tx25.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/karo/tx25/config.mk b/board/karo/tx25/config.mk deleted file mode 100644 index 18b288392c..0000000000 --- a/board/karo/tx25/config.mk +++ /dev/null @@ -1,5 +0,0 @@ -ifdef CONFIG_NAND_SPL -CONFIG_SYS_TEXT_BASE = 0x810c0000 -else -CONFIG_SYS_TEXT_BASE = 0x81200000 -endif diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c index 362f00a173..85719a0204 100644 --- a/board/karo/tx25/tx25.c +++ b/board/karo/tx25/tx25.c @@ -33,6 +33,14 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong bootflag) +{ + relocate_code(CONFIG_SPL_TEXT_BASE); + asm volatile("ldr pc, =nand_boot"); +} +#endif + #ifdef CONFIG_FEC_MXC #define GPIO_FEC_RESET_B IMX_GPIO_NR(4, 7) #define GPIO_FEC_ENABLE_B IMX_GPIO_NR(4, 9) diff --git a/board/overo/overo.c b/board/overo/overo.c index 8690450fa8..c10c44c606 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -37,7 +37,7 @@ #include <asm/arch/mux.h> #include <asm/arch/mem.h> #include <asm/arch/sys_proto.h> -#include <asm/arch/omap_gpmc.h> +#include <asm/omap_gpmc.h> #include <asm/gpio.h> #include <asm/mach-types.h> #include "overo.h" diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index 1708ac2acd..43d7b6e15a 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -104,7 +104,8 @@ static struct emif_regs ddr3_emif_reg_data = { .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2, .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3, .zq_config = MT41J256M8HX15E_ZQ_CFG, - .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY, + .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY | + PHY_EN_DYN_PWRDN, }; #endif diff --git a/board/samsung/dts/exynos5250-smdk5250.dts b/board/samsung/dts/exynos5250-smdk5250.dts index 1c2d52d622..8da973b305 100644 --- a/board/samsung/dts/exynos5250-smdk5250.dts +++ b/board/samsung/dts/exynos5250-smdk5250.dts @@ -79,4 +79,44 @@ samsung,slope = <274761730>; samsung,dc-value = <25>; }; + + fimd@14400000 { + samsung,vl-freq = <60>; + samsung,vl-col = <2560>; + samsung,vl-row = <1600>; + samsung,vl-width = <2560>; + samsung,vl-height = <1600>; + + samsung,vl-clkp; + samsung,vl-dp; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <32>; + samsung,vl-hbpd = <80>; + samsung,vl-hfpd = <48>; + samsung,vl-vspw = <6>; + samsung,vl-vbpd = <37>; + samsung,vl-vfpd = <3>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,winid = <3>; + samsung,interface-mode = <1>; + samsung,dp-enabled = <1>; + samsung,dual-lcd-enabled = <0>; + }; + + dp@145b0000 { + samsung,lt-status = <0>; + + samsung,master-mode = <0>; + samsung,bist-mode = <0>; + samsung,bist-pattern = <0>; + samsung,h-sync-polarity = <0>; + samsung,v-sync-polarity = <0>; + samsung,interlaced = <0>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + }; }; diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c index c009ae579a..5b9e82fdf7 100644 --- a/board/samsung/smdk5250/clock_init.c +++ b/board/samsung/smdk5250/clock_init.c @@ -434,10 +434,10 @@ void system_clock_init() val = readl(&clk->mux_stat_core1); } while ((val | MUX_MPLL_SEL_MASK) != val); - clrbits_le32(&clk->src_core1, MUX_CPLL_SEL_MASK); - clrbits_le32(&clk->src_core1, MUX_EPLL_SEL_MASK); - clrbits_le32(&clk->src_core1, MUX_VPLL_SEL_MASK); - clrbits_le32(&clk->src_core1, MUX_GPLL_SEL_MASK); + clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK); + clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK); + clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK); + clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK); tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK | MUX_GPLL_SEL_MASK; do { @@ -494,35 +494,35 @@ void system_clock_init() val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv, arm_clk_ratio->apll_sdiv); writel(val, &clk->apll_con0); - while (readl(&clk->apll_con0) & APLL_CON0_LOCKED) + while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0) ; /* Set MPLL */ writel(MPLL_CON1_VAL, &clk->mpll_con1); val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); writel(val, &clk->mpll_con0); - while (readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) + while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0) ; /* Set BPLL */ writel(BPLL_CON1_VAL, &clk->bpll_con1); val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv); writel(val, &clk->bpll_con0); - while (readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) + while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0) ; /* Set CPLL */ writel(CPLL_CON1_VAL, &clk->cpll_con1); val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); writel(val, &clk->cpll_con0); - while (readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) + while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0) ; /* Set GPLL */ writel(GPLL_CON1_VAL, &clk->gpll_con1); val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv); writel(val, &clk->gpll_con0); - while (readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) + while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0) ; /* Set EPLL */ @@ -530,7 +530,7 @@ void system_clock_init() writel(EPLL_CON1_VAL, &clk->epll_con1); val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); writel(val, &clk->epll_con0); - while (readl(&clk->epll_con0) & EPLL_CON0_LOCKED) + while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0) ; /* Set VPLL */ @@ -538,7 +538,7 @@ void system_clock_init() writel(VPLL_CON1_VAL, &clk->vpll_con1); val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); writel(val, &clk->vpll_con0); - while (readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) + while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0) ; writel(CLK_SRC_CORE0_VAL, &clk->src_core0); diff --git a/board/samsung/smdk5250/setup.h b/board/samsung/smdk5250/setup.h index a15960121c..34d8bc31f4 100644 --- a/board/samsung/smdk5250/setup.h +++ b/board/samsung/smdk5250/setup.h @@ -343,7 +343,7 @@ #define TOP2_VAL 0x0110000 /* CLK_SRC_PERIC0 */ -#define PWM_SEL 0 +#define PWM_SEL 6 #define UART3_SEL 6 #define UART2_SEL 6 #define UART1_SEL 6 diff --git a/board/samsung/smdk5250/smdk5250-uboot-spl.lds b/board/samsung/smdk5250/smdk5250-uboot-spl.lds index 4c8baaa9db..c0a7602089 100644 --- a/board/samsung/smdk5250/smdk5250-uboot-spl.lds +++ b/board/samsung/smdk5250/smdk5250-uboot-spl.lds @@ -26,7 +26,7 @@ */ MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \ - LENGTH = CONFIG_SPL_MAX_SIZE } + LENGTH = CONFIG_SPL_MAX_FOOTPRINT } OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) @@ -37,7 +37,7 @@ SECTIONS .text : { __start = .; - arch/arm/cpu/armv7/start.o (.text) + arch/arm/cpu/armv7/start.o (.text*) *(.text*) } >.sram . = ALIGN(4); diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c index 217c6df301..8b09e1de42 100644 --- a/board/samsung/smdk5250/smdk5250.c +++ b/board/samsung/smdk5250/smdk5250.c @@ -312,9 +312,10 @@ int board_eth_init(bd_t *bis) u32 smc_bw_conf, smc_bc_conf; struct fdt_sromc config; fdt_addr_t base_addr; - int node; #ifdef CONFIG_OF_CONTROL + int node; + node = decode_sromc(gd->fdt_blob, &config); if (node < 0) { debug("%s: Could not find sromc configuration\n", __func__); @@ -454,7 +455,7 @@ int board_early_init_f(void) #endif #ifdef CONFIG_LCD -void cfg_lcd_gpio(void) +void exynos_cfg_lcd_gpio(void) { struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); @@ -471,6 +472,12 @@ void cfg_lcd_gpio(void) s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3)); } +void exynos_set_dp_phy(unsigned int onoff) +{ + set_dp_phy_ctrl(onoff); +} + +#ifndef CONFIG_OF_CONTROL vidinfo_t panel_info = { .vl_freq = 60, .vl_col = 2560, @@ -494,10 +501,6 @@ vidinfo_t panel_info = { .vl_cmd_allow_len = 0xf, .win_id = 3, - .cfg_gpio = cfg_lcd_gpio, - .backlight_on = NULL, - .lcd_power_on = NULL, - .reset_lcd = NULL, .dual_lcd_enabled = 0, .init_delay = 0, @@ -537,14 +540,16 @@ static struct edp_device_info edp_info = { }; static struct exynos_dp_platform_data dp_platform_data = { - .phy_enable = set_dp_phy_ctrl, .edp_dev_info = &edp_info, }; +#endif void init_panel_info(vidinfo_t *vid) { +#ifndef CONFIG_OF_CONTROL vid->rgb_mode = MODE_RGB_P, exynos_set_dp_platform_data(&dp_platform_data); +#endif } #endif diff --git a/board/samsung/smdk6400/.gitignore b/board/samsung/smdk6400/.gitignore deleted file mode 100644 index 25ab492c50..0000000000 --- a/board/samsung/smdk6400/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -# -# Generated files -# - -/config.tmp diff --git a/board/samsung/smdk6400/Makefile b/board/samsung/smdk6400/Makefile deleted file mode 100644 index 0d3e63b769..0000000000 --- a/board/samsung/smdk6400/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2008 -# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := smdk6400.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(SOBJS) $(OBJS) - $(call cmd_link_o_target, $(SOBJS) $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/samsung/smdk6400/config.mk b/board/samsung/smdk6400/config.mk deleted file mode 100644 index 6f04c2f568..0000000000 --- a/board/samsung/smdk6400/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> -# -# (C) Copyright 2008 -# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> -# -# SAMSUNG SMDK6400 board with mDirac3 (ARM1176) cpu -# -# see http://www.samsung.com/ for more information on SAMSUNG - -# On SMDK6400 we use the 64 MB SDRAM bank at -# -# 0x50000000 to 0x58000000 -# -# Linux-Kernel is expected to be at 0x50008000, entry 0x50008000 -# -# we load ourselves to 0x57e00000 without MMU -# with MMU, load address is changed to 0xc7e00000 -# -# download area is 0x5000c000 - -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - -ifndef CONFIG_NAND_SPL -CONFIG_SYS_TEXT_BASE = $(RAM_TEXT) -else -CONFIG_SYS_TEXT_BASE = 0 -endif diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S deleted file mode 100644 index f7ce176945..0000000000 --- a/board/samsung/smdk6400/lowlevel_init.S +++ /dev/null @@ -1,323 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Modified for the Samsung SMDK2410 by - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include <config.h> -#include <version.h> - -#include <asm/arch/s3c6400.h> - -#ifdef CONFIG_SERIAL1 -#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET) -#elif defined(CONFIG_SERIAL2) -#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART1_OFFSET) -#else -#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART2_OFFSET) -#endif - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - - .globl lowlevel_init -lowlevel_init: - mov r12, lr - - /* LED on only #8 */ - ldr r0, =ELFIN_GPIO_BASE - ldr r1, =0x55540000 - str r1, [r0, #GPNCON_OFFSET] - - ldr r1, =0x55555555 - str r1, [r0, #GPNPUD_OFFSET] - - ldr r1, =0xf000 - str r1, [r0, #GPNDAT_OFFSET] - - /* Disable Watchdog */ - ldr r0, =0x7e000000 @0x7e004000 - orr r0, r0, #0x4000 - mov r1, #0 - str r1, [r0] - - /* External interrupt pending clear */ - ldr r0, =(ELFIN_GPIO_BASE+EINTPEND_OFFSET) /*EINTPEND*/ - ldr r1, [r0] - str r1, [r0] - - ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000 - ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000 - - /* Disable all interrupts (VIC0 and VIC1) */ - mvn r3, #0x0 - str r3, [r0, #oINTMSK] - str r3, [r1, #oINTMSK] - - /* Set all interrupts as IRQ */ - mov r3, #0x0 - str r3, [r0, #oINTMOD] - str r3, [r1, #oINTMOD] - - /* Pending Interrupt Clear */ - mov r3, #0x0 - str r3, [r0, #oVECTADDR] - str r3, [r1, #oVECTADDR] - - /* init system clock */ - bl system_clock_init - -#ifndef CONFIG_NAND_SPL - /* for UART */ - bl uart_asm_init -#endif - -#ifdef CONFIG_BOOT_NAND - /* simple init for NAND */ - bl nand_asm_init -#endif - - /* Memory subsystem address 0x7e00f120 */ - ldr r0, =ELFIN_MEM_SYS_CFG - - /* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */ - mov r1, #S3C64XX_MEM_SYS_CFG_NAND - str r1, [r0] - - bl mem_ctrl_asm_init - -/* Wakeup support. Don't know if it's going to be used, untested. */ - ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) - ldr r1, [r0] - bic r1, r1, #0xfffffff7 - cmp r1, #0x8 - beq wakeup_reset - -1: - mov lr, r12 - mov pc, lr - -wakeup_reset: - - /* Clear wakeup status register */ - ldr r0, =(ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET) - ldr r1, [r0] - str r1, [r0] - - /* LED test */ - ldr r0, =ELFIN_GPIO_BASE - ldr r1, =0x3000 - str r1, [r0, #GPNDAT_OFFSET] - - /* Load return address and jump to kernel */ - ldr r0, =(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) - /* r1 = physical address of s3c6400_cpu_resume function */ - ldr r1, [r0] - /* Jump to kernel (sleep-s3c6400.S) */ - mov pc, r1 - nop - nop -/* - * system_clock_init: Initialize core clock and bus clock. - * void system_clock_init(void) - */ -system_clock_init: - ldr r0, =ELFIN_CLOCK_POWER_BASE /* 0x7e00f000 */ - -#ifdef CONFIG_SYNC_MODE - ldr r1, [r0, #OTHERS_OFFSET] - mov r2, #0x40 - orr r1, r1, r2 - str r1, [r0, #OTHERS_OFFSET] - - nop - nop - nop - nop - nop - - ldr r2, =0x80 - orr r1, r1, r2 - str r1, [r0, #OTHERS_OFFSET] - -check_syncack: - ldr r1, [r0, #OTHERS_OFFSET] - ldr r2, =0xf00 - and r1, r1, r2 - cmp r1, #0xf00 - bne check_syncack -#else /* ASYNC Mode */ - nop - nop - nop - nop - nop - - /* - * This was unconditional in original Samsung sources, but it doesn't - * seem to make much sense on S3C6400. - */ -#ifndef CONFIG_S3C6400 - ldr r1, [r0, #OTHERS_OFFSET] - bic r1, r1, #0xC0 - orr r1, r1, #0x40 - str r1, [r0, #OTHERS_OFFSET] - -wait_for_async: - ldr r1, [r0, #OTHERS_OFFSET] - and r1, r1, #0xf00 - cmp r1, #0x0 - bne wait_for_async -#endif - - ldr r1, [r0, #OTHERS_OFFSET] - bic r1, r1, #0x40 - str r1, [r0, #OTHERS_OFFSET] -#endif - - mov r1, #0xff00 - orr r1, r1, #0xff - str r1, [r0, #APLL_LOCK_OFFSET] - str r1, [r0, #MPLL_LOCK_OFFSET] - - /* Set Clock Divider */ - ldr r1, [r0, #CLK_DIV0_OFFSET] - bic r1, r1, #0x30000 - bic r1, r1, #0xff00 - bic r1, r1, #0xff - ldr r2, =CLK_DIV_VAL - orr r1, r1, r2 - str r1, [r0, #CLK_DIV0_OFFSET] - - ldr r1, =APLL_VAL - str r1, [r0, #APLL_CON_OFFSET] - ldr r1, =MPLL_VAL - str r1, [r0, #MPLL_CON_OFFSET] - - /* FOUT of EPLL is 96MHz */ - ldr r1, =0x200203 - str r1, [r0, #EPLL_CON0_OFFSET] - ldr r1, =0x0 - str r1, [r0, #EPLL_CON1_OFFSET] - - /* APLL, MPLL, EPLL select to Fout */ - ldr r1, [r0, #CLK_SRC_OFFSET] - orr r1, r1, #0x7 - str r1, [r0, #CLK_SRC_OFFSET] - - /* wait at least 200us to stablize all clock */ - mov r1, #0x10000 -1: subs r1, r1, #1 - bne 1b - - /* Synchronization for VIC port */ -#if defined(CONFIG_SYNC_MODE) - ldr r1, [r0, #OTHERS_OFFSET] - orr r1, r1, #0x20 - str r1, [r0, #OTHERS_OFFSET] -#elif !defined(CONFIG_S3C6400) - /* According to 661558um_S3C6400X_rev10.pdf 0x20 is reserved */ - ldr r1, [r0, #OTHERS_OFFSET] - bic r1, r1, #0x20 - str r1, [r0, #OTHERS_OFFSET] -#endif - mov pc, lr - - -#ifndef CONFIG_NAND_SPL -/* - * uart_asm_init: Initialize UART's pins - */ -uart_asm_init: - /* set GPIO to enable UART */ - ldr r0, =ELFIN_GPIO_BASE - ldr r1, =0x220022 - str r1, [r0, #GPACON_OFFSET] - mov pc, lr -#endif - -#ifdef CONFIG_BOOT_NAND -/* - * NAND Interface init for SMDK6400 - */ -nand_asm_init: - ldr r0, =ELFIN_NAND_BASE - ldr r1, [r0, #NFCONF_OFFSET] - orr r1, r1, #0x70 - orr r1, r1, #0x7700 - str r1, [r0, #NFCONF_OFFSET] - - ldr r1, [r0, #NFCONT_OFFSET] - orr r1, r1, #0x07 - str r1, [r0, #NFCONT_OFFSET] - - mov pc, lr -#endif - -#ifdef CONFIG_ENABLE_MMU -/* - * MMU Table for SMDK6400 - */ - - /* form a first-level section entry */ -.macro FL_SECTION_ENTRY base,ap,d,c,b - .word (\base << 20) | (\ap << 10) | \ - (\d << 5) | (1<<4) | (\c << 3) | (\b << 2) | (1<<1) -.endm - -.section .mmudata, "a" - .align 14 - /* the following alignment creates the mmu table at address 0x4000. */ - .globl mmu_table -mmu_table: - .set __base, 0 - /* 1:1 mapping for debugging */ - .rept 0xA00 - FL_SECTION_ENTRY __base, 3, 0, 0, 0 - .set __base, __base + 1 - .endr - - /* access is not allowed. */ - .rept 0xC00 - 0xA00 - .word 0x00000000 - .endr - - /* 128MB for SDRAM 0xC0000000 -> 0x50000000 */ - .set __base, 0x500 - .rept 0xC80 - 0xC00 - FL_SECTION_ENTRY __base, 3, 0, 1, 1 - .set __base, __base + 1 - .endr - - /* access is not allowed. */ - .rept 0x1000 - 0xc80 - .word 0x00000000 - .endr -#endif diff --git a/board/samsung/smdk6400/smdk6400.c b/board/samsung/smdk6400/smdk6400.c deleted file mode 100644 index c40d1f9b49..0000000000 --- a/board/samsung/smdk6400/smdk6400.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <netdev.h> -#include <asm/arch/s3c6400.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -#define CS8900_Tacs 0x0 /* 0clk address set-up */ -#define CS8900_Tcos 0x4 /* 4clk chip selection set-up */ -#define CS8900_Tacc 0xE /* 14clk access cycle */ -#define CS8900_Tcoh 0x1 /* 1clk chip selection hold */ -#define CS8900_Tah 0x4 /* 4clk address holding time */ -#define CS8900_Tacp 0x6 /* 6clk page mode access cycle */ -#define CS8900_PMC 0x0 /* normal(1data)page mode configuration */ - -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b" - : "=r" (loops) : "0" (loops)); -} - -/* - * Miscellaneous platform dependent initialisations - */ - -static void cs8900_pre_init(void) -{ - SROM_BW_REG &= ~(0xf << 4); - SROM_BW_REG |= (1 << 7) | (1 << 6) | (1 << 4); - SROM_BC1_REG = ((CS8900_Tacs << 28) + (CS8900_Tcos << 24) + - (CS8900_Tacc << 16) + (CS8900_Tcoh << 12) + - (CS8900_Tah << 8) + (CS8900_Tacp << 4) + CS8900_PMC); -} - -int board_init(void) -{ - cs8900_pre_init(); - - /* NOR-flash in SROM0 */ - - /* Enable WAIT */ - SROM_BW_REG |= 4 | 8 | 1; - - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); - - return 0; -} - -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - printf("Board: SMDK6400\n"); - return 0; -} -#endif - -#ifdef CONFIG_ENABLE_MMU -ulong virt_to_phy_smdk6400(ulong addr) -{ - if ((0xc0000000 <= addr) && (addr < 0xc8000000)) - return addr - 0xc0000000 + 0x50000000; - else - printf("do not support this address : %08lx\n", addr); - - return addr; -} -#endif - -ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info) -{ - if (banknum == 0) { /* non-CFI boot flash */ - info->portwidth = FLASH_CFI_16BIT; - info->chipwidth = FLASH_CFI_BY16; - info->interface = FLASH_CFI_X16; - return 1; - } else - return 0; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_CS8900 - rc = cs8900_initialize(0, CONFIG_CS8900_BASE); -#endif - return rc; -} -#endif diff --git a/board/samsung/smdk6400/smdk6400_nand_spl.c b/board/samsung/smdk6400/smdk6400_nand_spl.c deleted file mode 100644 index a02328497d..0000000000 --- a/board/samsung/smdk6400/smdk6400_nand_spl.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -void board_init_f(unsigned long bootflag) -{ - relocate_code(CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL, - CONFIG_SYS_TEXT_BASE); -} diff --git a/board/samsung/smdk6400/u-boot-nand.lds b/board/samsung/smdk6400/u-boot-nand.lds deleted file mode 100644 index 64c650d2e9..0000000000 --- a/board/samsung/smdk6400/u-boot-nand.lds +++ /dev/null @@ -1,86 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/arm1176/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - - . = align(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = align(4); - .mmudata : { *(.mmudata) } - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 920764664c..e20fb3d2e3 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -635,7 +635,7 @@ int board_early_init_f(void) return 0; } -static void lcd_reset(void) +void exynos_reset_lcd(void) { struct exynos4_gpio_part2 *gpio2 = (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); @@ -755,10 +755,6 @@ vidinfo_t panel_info = { .vl_cmd_allow_len = 0xf, .win_id = 3, - .cfg_gpio = NULL, - .backlight_on = NULL, - .lcd_power_on = NULL, /* lcd_power_on in mipi dsi driver */ - .reset_lcd = lcd_reset, .dual_lcd_enabled = 0, .init_delay = 0, diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index e742707f79..9b2770f9d1 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -384,7 +384,7 @@ static void init_pmic_lcd(void) puts("LCD pmic initialisation error!\n"); } -static void lcd_cfg_gpio(void) +void exynos_cfg_lcd_gpio(void) { unsigned int i, f3_end = 4; @@ -423,7 +423,7 @@ static void lcd_cfg_gpio(void) spi_init(); } -static void reset_lcd(void) +void exynos_reset_lcd(void) { s5p_gpio_set_value(&gpio2->y4, 5, 1); udelay(10000); @@ -433,7 +433,7 @@ static void reset_lcd(void) udelay(100); } -static void lcd_power_on(void) +void exynos_lcd_power_on(void) { struct pmic *p = pmic_get("MAX8998_PMIC"); @@ -471,10 +471,6 @@ vidinfo_t panel_info = { .vl_cmd_allow_len = 0xf, .win_id = 0, - .cfg_gpio = lcd_cfg_gpio, - .backlight_on = NULL, - .lcd_power_on = lcd_power_on, - .reset_lcd = reset_lcd, .dual_lcd_enabled = 0, .init_delay = 0, @@ -484,6 +480,16 @@ vidinfo_t panel_info = { .mipi_enabled = 0, }; +void exynos_cfg_ldo(void) +{ + ld9040_cfg_ldo(); +} + +void exynos_enable_ldo(unsigned int onoff) +{ + ld9040_enable_ldo(onoff); +} + void init_panel_info(vidinfo_t *vid) { vid->logo_on = 1; @@ -498,9 +504,6 @@ void init_panel_info(vidinfo_t *vid) vid->pclk_name = 1; /* MPLL */ vid->sclk_div = 1; - vid->cfg_ldo = ld9040_cfg_ldo; - vid->enable_ldo = ld9040_enable_ldo; - setenv("lcdinfo", "lcd=ld9040"); } diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 12620bb69c..b371376bc7 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -379,7 +379,7 @@ void s_init(void) config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); else if (board_is_bone_lt()) - config_ddr(303, MT41K256M16HA125E_IOCTRL_VALUE, + config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE, &ddr3_beagleblack_data, &ddr3_beagleblack_cmd_ctrl_data, &ddr3_beagleblack_emif_reg_data, 0); diff --git a/board/ti/omap2420h4/config.mk b/board/ti/omap2420h4/config.mk index ca5ebdf96a..e5dff69a15 100644 --- a/board/ti/omap2420h4/config.mk +++ b/board/ti/omap2420h4/config.mk @@ -14,7 +14,7 @@ # (mem base + reserved) # For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80e80000 +#CONFIG_SYS_TEXT_BASE = 0x80e80000 # Used with full SRAM boot. # This is either with a GP system or a signed boot image. @@ -24,5 +24,5 @@ CONFIG_SYS_TEXT_BASE = 0x80e80000 # Handy to get symbols to debug ROM version. #CONFIG_SYS_TEXT_BASE = 0x0 -#CONFIG_SYS_TEXT_BASE = 0x08000000 +CONFIG_SYS_TEXT_BASE = 0x08000000 #CONFIG_SYS_TEXT_BASE = 0x04000000 diff --git a/board/ti/omap2420h4/mem.c b/board/ti/omap2420h4/mem.c index c8b4186dc8..ba3f12aded 100644 --- a/board/ti/omap2420h4/mem.c +++ b/board/ti/omap2420h4/mem.c @@ -200,19 +200,6 @@ void do_sdrc_init(u32 offset, u32 early) __asm__ __volatile__("": : :"memory"); /* limit compiler scope */ - /* u-boot is compiled to run in DDR or SRAM at 8xxxxxxx or 4xxxxxxx. - * If we are running in flash prior to relocation and we use data - * here which is not pc relative we need to get the address correct. - * We need to find the current flash mapping to dress up the initial - * pointer load. As long as this is const data we should be ok. - */ - if((early) && running_in_flash()){ - sdata = (sdrc_data_t *)(((u32)sdata & 0x0003FFFF) | get_gpmc0_base()); - /* NOR internal boot offset is 0x4000 from xloader signature */ - if(running_from_internal_boot()) - sdata = (sdrc_data_t *)((u32)sdata + 0x4000); - } - if (!early && (((mtype = get_mem_type()) == DDR_COMBO)||(mtype == DDR_STACKED))) { if(mtype == DDR_COMBO){ pmask = BIT2;/* combo part has a shared CKE signal, can't use feature */ diff --git a/board/ti/omap2420h4/omap2420h4.c b/board/ti/omap2420h4/omap2420h4.c index 188e4acc09..532e989bac 100644 --- a/board/ti/omap2420h4/omap2420h4.c +++ b/board/ti/omap2420h4/omap2420h4.c @@ -190,10 +190,10 @@ void ether_init (void) * Routine: dram_init * Description: sets uboots idea of sdram size **********************************************/ -int dram_init (void) +int dram_init(void) { unsigned int size0=0,size1=0; - u32 mtype, btype, rev; + u32 mtype, btype; u8 chg_on = 0x5; /* enable charge of back up battery */ u8 vmode_on = 0x8C; #define NOT_EARLY 0 @@ -202,7 +202,6 @@ int dram_init (void) btype = get_board_type(); mtype = get_mem_type(); - rev = get_cpu_rev(); display_board_info(btype); if (btype == BOARD_H4_MENELAUS){ @@ -217,15 +216,28 @@ int dram_init (void) size0 = get_sdr_cs_size(SDRC_CS0_OSET); size1 = get_sdr_cs_size(SDRC_CS1_OSET); - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = size0; + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, size0 + size1); + + return 0; +} + +void dram_init_banksize(void) +{ + unsigned int size0, size1; + u32 rev; + + rev = get_cpu_rev(); + size0 = get_sdr_cs_size(SDRC_CS0_OSET); + size1 = get_sdr_cs_size(SDRC_CS1_OSET); + if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */ gd->bd->bi_dram[1].start = PHYS_SDRAM_2; else /* ES2 and above can remap at 32MB granularity */ gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0; gd->bd->bi_dram[1].size = size1; - return 0; + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; } /********************************************************** diff --git a/board/ti/omap5912osk/config.mk b/board/ti/omap5912osk/config.mk index 0ed7d8a6a7..5b8d952ba6 100644 --- a/board/ti/omap5912osk/config.mk +++ b/board/ti/omap5912osk/config.mk @@ -14,17 +14,17 @@ # TI OSK board with OMAP5912 (ARM925EJS) cpu # see http://www.ti.com/ for more information on Texas Instruments # -# OSK has 1 bank of 256 MB SDRAM +# OSK has 1 bank of 32 MB SDRAM # Physical Address: -# 1000'0000 to 2000'0000 +# 1000'0000 to 1200'0000 # # # Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 # (mem base + reserved) # -# we load ourself to 1108'0000 +# When running from RAM use address 1108'0000, otherwise when +# booting from NOR flash link to address 0000'0000. # -# - -CONFIG_SYS_TEXT_BASE = 0x11080000 +CONFIG_SYS_TEXT_BASE = 0x00000000 +#CONFIG_SYS_TEXT_BASE = 0x11080000 diff --git a/board/ti/omap5912osk/lowlevel_init.S b/board/ti/omap5912osk/lowlevel_init.S index e60161ebaf..ca7361e05a 100644 --- a/board/ti/omap5912osk/lowlevel_init.S +++ b/board/ti/omap5912osk/lowlevel_init.S @@ -306,6 +306,23 @@ common_tc: ldr r1, VAL_MPU_CNTL_TIMER str r1, [r0] + /* + * Setup a temporary stack + */ + ldr sp, SRAM_STACK + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ + + /* + * Save the old lr(passed in ip) and the current lr to stack + */ + push {ip, lr} + + /* + * go setup pll, mux, memory + */ + bl s_init + pop {ip, pc} + /* back to arch calling code */ mov pc, lr @@ -470,6 +487,9 @@ VAL_ARM_IDLECT2: VAL_ARM_IDLECT3: .word 0x00000015 +SRAM_STACK: + .word CONFIG_SYS_INIT_SP_ADDR + /* command values */ .equ CMD_SDRAM_NOP, 0x00000000 .equ CMD_SDRAM_PRECHARGE, 0x00000001 diff --git a/board/ti/omap5912osk/omap5912osk.c b/board/ti/omap5912osk/omap5912osk.c index fac683a7e6..95140719aa 100644 --- a/board/ti/omap5912osk/omap5912osk.c +++ b/board/ti/omap5912osk/omap5912osk.c @@ -66,6 +66,14 @@ int board_init (void) /* adress of boot parameters */ gd->bd->bi_boot_params = 0x10000100; + flash__init(); + ether__init(); + + return 0; +} + +void s_init(void) +{ /* Configure MUX settings */ set_muxconf_regs (); peripheral_power_enable (); @@ -75,10 +83,6 @@ int board_init (void) * ... rkw ... */ icache_enable (); - - flash__init (); - ether__init (); - return 0; } /****************************** @@ -128,14 +132,19 @@ void ether__init (void) Routine: Description: ******************************/ -int dram_init (void) +int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); return 0; } +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; +} + /****************************************************** Routine: set_muxconf_regs Description: Setting up the configuration Mux registers diff --git a/board/ti/omap5_evm/Makefile b/board/ti/omap5_uevm/Makefile index fa81d64bee..fa81d64bee 100644 --- a/board/ti/omap5_evm/Makefile +++ b/board/ti/omap5_uevm/Makefile diff --git a/board/ti/omap5_evm/evm.c b/board/ti/omap5_uevm/evm.c index 55337c09d5..55337c09d5 100644 --- a/board/ti/omap5_evm/evm.c +++ b/board/ti/omap5_uevm/evm.c diff --git a/board/ti/omap5_evm/mux_data.h b/board/ti/omap5_uevm/mux_data.h index a82795dc13..a82795dc13 100644 --- a/board/ti/omap5_evm/mux_data.h +++ b/board/ti/omap5_uevm/mux_data.h diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds index dc437d1f23..61d1154aff 100644 --- a/board/vpac270/u-boot-spl.lds +++ b/board/vpac270/u-boot-spl.lds @@ -54,11 +54,13 @@ SECTIONS . = ALIGN(4); .data : { - *(.data) + *(.data*) } . = ALIGN(4); + __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*) @@ -76,7 +78,7 @@ SECTIONS .bss __rel_dyn_start (OVERLAY) : { __bss_start = .; - *(.bss) + *(.bss*) . = ALIGN(4); __bss_end = .; } diff --git a/board/wandboard/Makefile b/board/wandboard/Makefile new file mode 100644 index 0000000000..014ea6c1f9 --- /dev/null +++ b/board/wandboard/Makefile @@ -0,0 +1,29 @@ +# +# (C) Copyright 2013 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := wandboard.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/wandboard/README b/board/wandboard/README new file mode 100644 index 0000000000..e0b0b33020 --- /dev/null +++ b/board/wandboard/README @@ -0,0 +1,40 @@ +U-Boot for Wandboard +-------------------- + +This file contains information for the port of U-Boot to the Wandboard. + +Wandboard is a development board that has two variants: one version based +on mx6 dual lite and another one based on mx6 solo. + +For more details about Wandboard, please refer to: +http://www.wandboard.org/ + +Building U-boot for Wandboard +----------------------------- + +To build U-Boot for the Wandboard Dual Lite version: + +$ make wanboard_dl_config +$ make + +To build U-Boot for the Wandboard Solo version: + +$ make wanboard_solo_config +$ make + +Flashing U-boot into the SD card +-------------------------------- + +- After the 'make' command completes, the generated 'u-boot.imx' binary must be +flashed into the SD card; + +$ sudo dd if=u-boot.imx of=/dev/mmcblk0 bs=512 seek=2; sync + +(Note - the SD card node may vary, so adjust this as needed). + +- Insert the SD card into the slot located in the bottom of the board (same side +as the mx6 processor) + +- Connect the serial cable to the host PC + +- Power up the board and U-boot messages will appear in the serial console. diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c new file mode 100644 index 0000000000..ac7b89aaec --- /dev/null +++ b/board/wandboard/wandboard.c @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/io.h> +#include <asm/sizes.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <mmc.h> +#include <miiphy.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define ETH_PHY_RESET IMX_GPIO_NR(3, 29) + +int dram_init(void) +{ + gd->ram_size = CONFIG_DDR_MB * SZ_1M; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* AR8031 PHY Reset */ + MX6_PAD_EIM_D29__GPIO_3_29 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + + /* Reset AR8031 PHY */ + gpio_direction_output(ETH_PHY_RESET, 0); + udelay(500); + gpio_set_value(ETH_PHY_RESET, 1); +} + +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC3_BASE_ADDR}, +}; + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].max_bus_width = 4; + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + +static int mx6_rgmii_rework(struct phy_device *phydev) +{ + unsigned short val; + + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + mx6_rgmii_rework(phydev); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_enet(); + + ret = cpu_eth_init(bis); + if (ret) + printf("FEC MXC: %s:failed\n", __func__); + + return 0; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: Wandboard\n"); + + return 0; +} |
