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-rw-r--r--board/siemens/draco/Kconfig16
-rw-r--r--board/siemens/draco/MAINTAINERS1
-rw-r--r--board/siemens/draco/board.c84
-rw-r--r--board/siemens/draco/mux.c2
4 files changed, 100 insertions, 3 deletions
diff --git a/board/siemens/draco/Kconfig b/board/siemens/draco/Kconfig
index 819d187087..a699c7d46f 100644
--- a/board/siemens/draco/Kconfig
+++ b/board/siemens/draco/Kconfig
@@ -45,3 +45,19 @@ config SYS_CONFIG_NAME
default "rastaban"
endif
+
+if TARGET_ETAMIN
+
+config SYS_BOARD
+ default "draco"
+
+config SYS_VENDOR
+ default "siemens"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "etamin"
+
+endif
diff --git a/board/siemens/draco/MAINTAINERS b/board/siemens/draco/MAINTAINERS
index 484dd739c1..e9107f08bf 100644
--- a/board/siemens/draco/MAINTAINERS
+++ b/board/siemens/draco/MAINTAINERS
@@ -4,6 +4,7 @@ S: Maintained
F: board/siemens/draco/
F: include/configs/draco.h
F: configs/draco_defconfig
+F: configs/etamin_defconfig
F: include/configs/thuban.h
F: configs/thuban_defconfig
F: include/configs/rastaban.h
diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c
index 988c12ac7c..d8869a09dd 100644
--- a/board/siemens/draco/board.c
+++ b/board/siemens/draco/board.c
@@ -24,6 +24,7 @@
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
@@ -33,6 +34,7 @@
#include <watchdog.h>
#include "board.h"
#include "../common/factoryset.h"
+#include <nand.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -40,6 +42,7 @@ DECLARE_GLOBAL_DATA_PTR;
static struct draco_baseboard_id __attribute__((section(".data"))) settings;
#if DDR_PLL_FREQ == 303
+#if !defined(CONFIG_TARGET_ETAMIN)
/* Default@303MHz-i0 */
const struct ddr3_data ddr3_default = {
0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
@@ -48,6 +51,16 @@ const struct ddr3_data ddr3_default = {
"default name @303MHz \0",
"default marking \0",
};
+#else
+/* etamin board */
+const struct ddr3_data ddr3_default = {
+ 0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F,
+ 0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2,
+ 0x0000093B, 0x0000018A,
+ "test-etamin \0",
+ "generic-8Gbit \0",
+};
+#endif
#elif DDR_PLL_FREQ == 400
/* Default@400MHz-i0 */
const struct ddr3_data ddr3_default = {
@@ -105,6 +118,40 @@ static void print_chip_data(void)
}
#endif /* CONFIG_SPL_BUILD */
+#define AM335X_NAND_ECC_MASK 0x0f
+#define AM335X_NAND_ECC_TYPE_16 0x02
+
+static int ecc_type;
+
+struct am335x_nand_geometry {
+ u32 magic;
+ u8 nand_geo_addr;
+ u8 nand_geo_page;
+ u8 nand_bus;
+};
+
+static int draco_read_nand_geometry(void)
+{
+ struct am335x_nand_geometry geo;
+
+ /* Read NAND geometry */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2,
+ (uchar *)&geo, sizeof(struct am335x_nand_geometry))) {
+ printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n");
+ return -EIO;
+ }
+ if (geo.magic != 0xa657b310) {
+ printf("%s: bad magic: %x\n", __func__, geo.magic);
+ return -EFAULT;
+ }
+ if ((geo.nand_bus & AM335X_NAND_ECC_MASK) == AM335X_NAND_ECC_TYPE_16)
+ ecc_type = 16;
+ else
+ ecc_type = 8;
+
+ return 0;
+}
+
/*
* Read header information from EEPROM into global structure.
*/
@@ -147,6 +194,8 @@ static int read_eeprom(void)
printf("Warning: No chip data in eeprom\n");
print_ddr3_timings();
+
+ return draco_read_nand_geometry();
#endif
return 0;
}
@@ -174,6 +223,7 @@ struct ctrl_ioregs draco_ddr3_ioregs = {
draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
settings.ddr3.emif_ddr_phy_ctlr_1;
draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
+ draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000;
draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
@@ -207,7 +257,18 @@ static void spl_siemens_board_init(void)
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
- omap_nand_switch_ecc(1, 8);
+ int ret;
+
+ ret = draco_read_nand_geometry();
+ if (ret != 0)
+ return ret;
+
+ nand_curr_device = 0;
+ omap_nand_switch_ecc(1, ecc_type);
+#ifdef CONFIG_TARGET_ETAMIN
+ nand_curr_device = 1;
+ omap_nand_switch_ecc(1, ecc_type);
+#endif
#ifdef CONFIG_FACTORYSET
/* Set ASN in environment*/
if (factory_dat.asn[0] != 0) {
@@ -283,7 +344,7 @@ int board_eth_init(bd_t *bis)
}
static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
- char *const argv[])
+ char *const argv[])
{
/* Reset SMSC LAN9303 switch for default configuration */
gpio_request(GPIO_LAN9303_NRST, "nRST");
@@ -303,4 +364,23 @@ U_BOOT_CMD(
#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
+#ifdef CONFIG_NAND_CS_INIT
+/* GPMC definitions for second nand cs1 */
+static const u32 gpmc_nand_config[] = {
+ ETAMIN_NAND_GPMC_CONFIG1,
+ ETAMIN_NAND_GPMC_CONFIG2,
+ ETAMIN_NAND_GPMC_CONFIG3,
+ ETAMIN_NAND_GPMC_CONFIG4,
+ ETAMIN_NAND_GPMC_CONFIG5,
+ ETAMIN_NAND_GPMC_CONFIG6,
+ /*CONFIG7- computed as params */
+};
+
+static void board_nand_cs_init(void)
+{
+ enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1],
+ 0x18000000, GPMC_SIZE_16M);
+}
+#endif
+
#include "../common/board.c"
diff --git a/board/siemens/draco/mux.c b/board/siemens/draco/mux.c
index dbcc80b61f..38a484eb43 100644
--- a/board/siemens/draco/mux.c
+++ b/board/siemens/draco/mux.c
@@ -51,6 +51,7 @@ static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_csn1), MODE(0) | PULLUDEN | PULLUP_EN}, /* NAND_CS1 */
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
@@ -68,7 +69,6 @@ static struct module_pin_mux gpios_pin_mux[] = {
{OFFSET(mmc0_dat1), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y3 GPIO2_28*/
{OFFSET(mmc0_dat2), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y7 GPIO2_27*/
/* Triacs initial HW Rev */
- {OFFSET(gpmc_csn1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_30 Y0 */
{OFFSET(gpmc_be1n), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_28 Y1 */
{OFFSET(gpmc_csn2), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_31 Y2 */
{OFFSET(lcd_data15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_11 Y3 */
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