diff options
Diffstat (limited to 'board/freescale/ls1043ardb')
-rw-r--r-- | board/freescale/ls1043ardb/README | 37 | ||||
-rw-r--r-- | board/freescale/ls1043ardb/cpld.c | 26 | ||||
-rw-r--r-- | board/freescale/ls1043ardb/cpld.h | 1 | ||||
-rw-r--r-- | board/freescale/ls1043ardb/ddr.c | 2 | ||||
-rw-r--r-- | board/freescale/ls1043ardb/ddr.h | 9 | ||||
-rw-r--r-- | board/freescale/ls1043ardb/ls1043ardb.c | 21 |
6 files changed, 41 insertions, 55 deletions
diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README index 0556e73b3a..709ddbbef3 100644 --- a/board/freescale/ls1043ardb/README +++ b/board/freescale/ls1043ardb/README @@ -8,41 +8,8 @@ debugging environment. The LS1043A RDB is lead-free and RoHS-compliant. LS1043A SoC Overview -------------------- -The LS1043A integrated multicore processor combines four ARM Cortex-A53 -processor cores with datapath acceleration optimized for L2/3 packet -processing, single pass security offload and robust traffic management -and quality of service. - -The LS1043A SoC includes the following function and features: - - Four 64-bit ARM Cortex-A53 CPUs - - 1 MB unified L2 Cache - - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving - support - - Data Path Acceleration Architecture (DPAA) incorporating acceleration the - the following functions: - - Packet parsing, classification, and distribution (FMan) - - Queue management for scheduling, packet sequencing, and congestion - management (QMan) - - Hardware buffer management for buffer allocation and de-allocation (BMan) - - Cryptography acceleration (SEC) - - Ethernet interfaces by FMan - - Up to 1 x XFI supporting 10G interface - - Up to 1 x QSGMII - - Up to 4 x SGMII supporting 1000Mbps - - Up to 2 x SGMII supporting 2500Mbps - - Up to 2 x RGMII supporting 1000Mbps - - High-speed peripheral interfaces - - Three PCIe 2.0 controllers, one supporting x4 operation - - One serial ATA (SATA 3.0) controllers - - Additional peripheral interfaces - - Three high-speed USB 3.0 controllers with integrated PHY - - Enhanced secure digital host controller (eSDXC/eMMC) - - Quad Serial Peripheral Interface (QSPI) Controller - - Serial peripheral interface (SPI) controller - - Four I2C controllers - - Two DUARTs - - Integrated flash controller supporting NAND and NOR flash - - QorIQ platform's trust architecture 2.1 +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A +SoC overview. LS1043ARDB board Overview ----------------------- diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c index 78c28246a8..c6452830ed 100644 --- a/board/freescale/ls1043ardb/cpld.c +++ b/board/freescale/ls1043ardb/cpld.c @@ -28,10 +28,18 @@ void cpld_write(unsigned int reg, u8 value) /* Set the boot bank to the alternate bank */ void cpld_set_altbank(void) { + u16 reg = CPLD_CFG_RCW_SRC_NOR; u8 reg4 = CPLD_READ(soft_mux_on); + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); u8 reg7 = CPLD_READ(vbank); - CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL); + cpld_rev_bit(®5); + + CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6); reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK; CPLD_WRITE(vbank, reg7); @@ -42,7 +50,21 @@ void cpld_set_altbank(void) /* Set the boot bank to the default bank */ void cpld_set_defbank(void) { - CPLD_WRITE(global_rst, 1); + u16 reg = CPLD_CFG_RCW_SRC_NOR; + u8 reg4 = CPLD_READ(soft_mux_on); + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); + + cpld_rev_bit(®5); + + CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6); + + CPLD_WRITE(vbank, 0); + + CPLD_WRITE(system_rst, 1); } void cpld_set_nand(void) diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h index bd59c0e5d5..cb175b56fa 100644 --- a/board/freescale/ls1043ardb/cpld.h +++ b/board/freescale/ls1043ardb/cpld.h @@ -40,6 +40,7 @@ void cpld_rev_bit(unsigned char *value); #define CPLD_SW_MUX_BANK_SEL 0x40 #define CPLD_BANK_SEL_MASK 0x07 #define CPLD_BANK_SEL_ALTBANK 0x04 +#define CPLD_CFG_RCW_SRC_NOR 0x025 #define CPLD_CFG_RCW_SRC_NAND 0x106 #define CPLD_CFG_RCW_SRC_SD 0x040 #endif diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 11bc0f24d9..1e2fd2ed0c 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -177,6 +177,8 @@ phys_size_t initdram(int board_type) #else dram_size = fsl_ddr_sdram_size(); #endif + erratum_a008850_post(); + #ifdef CONFIG_FSL_DEEP_SLEEP fsl_dp_ddr_restore(); #endif diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h index b17eb80885..a77ddf3d24 100644 --- a/board/freescale/ls1043ardb/ddr.h +++ b/board/freescale/ls1043ardb/ddr.h @@ -6,6 +6,9 @@ #ifndef __DDR_H__ #define __DDR_H__ + +extern void erratum_a008850_post(void); + struct board_specific_parameters { u32 n_ranks; u32 datarate_mhz_high; @@ -31,9 +34,9 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ #ifdef CONFIG_SYS_FSL_DDR4 - {1, 1666, 0, 6, 7, 0x07090800, 0x00000000,}, - {1, 1900, 0, 6, 7, 0x07090800, 0x00000000,}, - {1, 2200, 0, 6, 7, 0x07090800, 0x00000000,}, + {1, 1666, 0, 12, 7, 0x07090800, 0x00000000,}, + {1, 1900, 0, 12, 7, 0x07090800, 0x00000000,}, + {1, 2200, 0, 12, 7, 0x07090800, 0x00000000,}, #endif {} }; diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index ec5fdbfe27..14365207da 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -19,7 +19,6 @@ #include <fsl_csu.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> -#include <environment.h> #include <fsl_sec.h> #include "cpld.h" #ifdef CONFIG_U_QE @@ -31,12 +30,12 @@ DECLARE_GLOBAL_DATA_PTR; int checkboard(void) { - static const char *freq[3] = {"100.00MHZ", "156.25MHZ"}; + static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; #ifndef CONFIG_SD_BOOT u8 cfg_rcw_src1, cfg_rcw_src2; - u32 cfg_rcw_src; + u16 cfg_rcw_src; #endif - u32 sd1refclk_sel; + u8 sd1refclk_sel; printf("Board: LS1043ARDB, boot from "); @@ -83,22 +82,12 @@ int board_early_init_f(void) int board_init(void) { - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - - /* - * Set CCI-400 control override register to enable barrier - * transaction - */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; #ifdef CONFIG_FSL_IFC init_final_memctl_regs(); #endif -#ifdef CONFIG_ENV_IS_NOWHERE - gd->env_addr = (ulong)&default_environment[0]; -#endif - #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); #endif @@ -106,6 +95,8 @@ int board_init(void) #ifdef CONFIG_U_QE u_qe_init(); #endif + /* invert AQR105 IRQ pins polarity */ + out_be32(&scfg->intpcr, AQR105_IRQ_MASK); return 0; } |