diff options
| author | wdenk <wdenk> | 2003-07-14 22:13:32 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2003-07-14 22:13:32 +0000 |
| commit | 8564acf936726c5568d71e4fa93a0ae9814e0d07 (patch) | |
| tree | 05fa981555adf1d333970f3d52d0683008fe3cfb /include/mpc8260.h | |
| parent | 5702923e23238df6c6f62d53f73863462ae62f4e (diff) | |
| download | talos-obmc-uboot-8564acf936726c5568d71e4fa93a0ae9814e0d07.tar.gz talos-obmc-uboot-8564acf936726c5568d71e4fa93a0ae9814e0d07.zip | |
* Patches by Yuli Barcohen, 13 Jul 2003:
- Correct flash and JFFS2 support for MPC8260ADS
- fix PVR values and clock generation for PowerQUICC II family
(8270/8275/8280)
* Patch by Bernhard Kuhn, 08 Jul 2003:
- add support for M68K targets
* Patch by Ken Chou, 3 Jul:
- Fix PCI config table for A3000
- Fix iobase for natsemi.c
(PCI_BASE_ADDRESS_0 is the IO base register for DP83815)
* Allow to enable "slow" POST routines by key press on power-on
* Fix temperature dependend switching of LCD backlight on LWMON
* Tweak output format for LWMON
Diffstat (limited to 'include/mpc8260.h')
| -rw-r--r-- | include/mpc8260.h | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/include/mpc8260.h b/include/mpc8260.h index 1b67c2b977..8bddd6a60e 100644 --- a/include/mpc8260.h +++ b/include/mpc8260.h @@ -300,14 +300,15 @@ /*----------------------------------------------------------------------- * SCMR - System Clock Mode Register 9-9 */ -#define SCMR_CORECNF_MSK 0x1f000000 /* Core Configuration Mask */ +#define SCMR_CORECNF_MSK 0x1f000000 /* Core Configuration Mask */ #define SCMR_CORECNF_SHIFT 24 -#define SCMR_BUSDF_MSK 0x00f00000 /* 60x Bus Division Factor Mask */ -#define SCMR_BUSDF_SHIFT 20 -#define SCMR_CPMDF_MSK 0x000f0000 /* CPM Division Factor Mask */ -#define SCMR_CPMDF_SHIFT 16 -#define SCMR_PLLDF 0x00001000 /* PLL Pre-divider Value */ -#define SCMR_PLLMF_MSK 0x00000fff /* PLL Multiplication Factor Mask*/ +#define SCMR_BUSDF_MSK 0x00f00000 /* 60x Bus Division Factor Mask */ +#define SCMR_BUSDF_SHIFT 20 +#define SCMR_CPMDF_MSK 0x000f0000 /* CPM Division Factor Mask */ +#define SCMR_CPMDF_SHIFT 16 +#define SCMR_PLLDF 0x00001000 /* PLL Pre-divider Value */ +#define SCMR_PLLMF_MSK 0x00000fff /* PLL Multiplication Factor Mask*/ +#define SCMR_PLLMF_MSKH7 0x0000000f /* for HiP7 processors */ #define SCMR_PLLMF_SHIFT 0 |
