* Patches by Yuli Barcohen, 13 Jul 2003:

  - Correct flash and JFFS2 support for MPC8260ADS
  - fix PVR values and clock generation for PowerQUICC II family
    (8270/8275/8280)

* Patch by Bernhard Kuhn, 08 Jul 2003:
  - add support for M68K targets

* Patch by Ken Chou, 3 Jul:
  - Fix PCI config table for A3000
  - Fix iobase for natsemi.c
    (PCI_BASE_ADDRESS_0 is the IO base register for DP83815)

* Allow to enable "slow" POST routines by key press on power-on
* Fix temperature dependend switching of LCD backlight on LWMON
* Tweak output format for LWMON

13 files changed, 164 insertions, 105 deletions

diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index 19c7fd8c02..6a0261c90a 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -73,6 +73,7 @@ typedef	struct	global_data {
 #ifdef CONFIG_POST
 	unsigned long	post_log_word;  /* Record POST activities */
 	unsigned long	post_init_f_time;  /* When post_init_f started */
+	unsigned long	post_hotkeys_latch; /* If the post hotkeys pressed */
 #endif
 #ifdef CONFIG_BOARD_TYPES
 	unsigned long	board_type;
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 8835139c81..726102da26 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -524,8 +524,15 @@
 #define	PVR_860		PVR_821
 #define	PVR_7400       	0x000C0000
 #define	PVR_8240	0x00810100
-#define	PVR_8260	PVR_8240
 
+/*
+ * PowerQUICC II family processors report different PVR values depending
+ * on silicon process (HiP3, HiP4, HiP7, etc.)
+ */
+#define PVR_8260        PVR_8240
+#define PVR_8260_HIP3   0x00810101
+#define PVR_8260_HIP4   0x80811014
+#define PVR_8260_HIP7   0x80822011
 
 /* I am just adding a single entry for 8260 boards.  I think we may be
  * able to combine mbx, fads, rpxlite, bseip, and classic into a single
diff --git a/include/configs/A3000.h b/include/configs/A3000.h
index b25e48cf89..ca9592c23b 100644
--- a/include/configs/A3000.h
+++ b/include/configs/A3000.h
@@ -114,6 +114,8 @@
 #define PCI_ENET1_MEMADDR		0x81000000
 #define PCI_ENET2_IOADDR		0x82000000
 #define PCI_ENET2_MEMADDR		0x82000000
+#define PCI_ENET3_IOADDR		0x83000000
+#define PCI_ENET3_MEMADDR		0x83000000
 
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h
index c41e542e12..401591db94 100644
--- a/include/configs/MPC8260ADS.h
+++ b/include/configs/MPC8260ADS.h
@@ -206,6 +206,14 @@
 #define CFG_FLASH_SIZE		8
 #define CFG_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)    */
 #define CFG_FLASH_WRITE_TOUT	5	/* Timeout for Flash Write (in ms)    */
+#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CFG_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
+
+#define CFG_JFFS2_FIRST_SECTOR  1
+#define CFG_JFFS2_LAST_SECTOR   27
+#define CFG_JFFS2_SORT_FRAGMENTS
+#define CFG_JFFS_CUSTOM_PART
 
 /* this is stuff came out of the Motorola docs */
 #define CFG_DEFAULT_IMMR	0x0F010000
diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h
index 926d63a668..7f2c8a4746 100644
--- a/include/configs/RRvision.h
+++ b/include/configs/RRvision.h
@@ -100,13 +100,13 @@
 #define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
 
-#if 1
+#ifndef CONFIG_LCD
 #define CONFIG_VIDEO		1	/* To enable the video initialization */
 
 /* Video related */
 #define CONFIG_VIDEO_LOGO			1	/* Show the logo */
-#define CONFIG_VIDEO_ENCODER_AD7176		1	/* Enable this encoder */
-#define CONFIG_VIDEO_ENCODER_AD7176_ADDR	0x2A	/* ALSB to ground */
+#define CONFIG_VIDEO_ENCODER_AD7179		1	/* Enable this encoder */
+#define CONFIG_VIDEO_ENCODER_AD7179_ADDR	0x2A	/* ALSB to ground */
 #endif
 
 /* enable I2C and select the hardware/software driver */
@@ -344,6 +344,7 @@
  *-----------------------------------------------------------------------
  *
  */
+/*#define	CFG_DER	0x2002000F*/
 #define CFG_DER	0
 
 /*
diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h
index 5de846c0f7..d427d80adb 100644
--- a/include/configs/lwmon.h
+++ b/include/configs/lwmon.h
@@ -579,6 +579,6 @@
 #define CONFIG_MODEM_SUPPORT	1	/* enable modem initialization stuff */
 #undef CONFIG_MODEM_SUPPORT_DEBUG
 
-#define	CONFIG_MODEM_KEY_MAGIC	"3C+3F"	/* hold down these keys to enable modem */
-
+#define	CONFIG_MODEM_KEY_MAGIC	"3C+3F"	/* press F3 + F6 keys to enable modem */
+#define	CONFIG_POST_KEY_MAGIC	"3C+3E"	/* press F3 + F5 keys to force POST */
 #endif	/* __CONFIG_H */
diff --git a/include/image.h b/include/image.h
index 4413a1dc64..155617eba8 100644
--- a/include/image.h
+++ b/include/image.h
@@ -63,6 +63,7 @@
 #define IH_CPU_SH		9	/* SuperH	*/
 #define IH_CPU_SPARC		10	/* Sparc	*/
 #define IH_CPU_SPARC64		11	/* Sparc 64 Bit */
+#define	IH_CPU_M68K		12	/* M68K		*/
 
 /*
  * Image Types
diff --git a/include/mpc8260.h b/include/mpc8260.h
index 1b67c2b977..8bddd6a60e 100644
--- a/include/mpc8260.h
+++ b/include/mpc8260.h
@@ -300,14 +300,15 @@
 /*-----------------------------------------------------------------------
  * SCMR - System Clock Mode Register					 9-9
  */
-#define SCMR_CORECNF_MSK 0x1f000000	/* Core Configuration Mask	*/
+#define SCMR_CORECNF_MSK   0x1f000000	/* Core Configuration Mask	*/
 #define SCMR_CORECNF_SHIFT 24
-#define SCMR_BUSDF_MSK	0x00f00000	/* 60x Bus Division Factor Mask	*/
-#define SCMR_BUSDF_SHIFT 20
-#define SCMR_CPMDF_MSK	0x000f0000	/* CPM Division Factor Mask	*/
-#define SCMR_CPMDF_SHIFT 16
-#define SCMR_PLLDF	0x00001000	/* PLL Pre-divider Value	*/
-#define SCMR_PLLMF_MSK	0x00000fff	/* PLL Multiplication Factor Mask*/
+#define SCMR_BUSDF_MSK	   0x00f00000	/* 60x Bus Division Factor Mask	*/
+#define SCMR_BUSDF_SHIFT   20
+#define SCMR_CPMDF_MSK	   0x000f0000	/* CPM Division Factor Mask	*/
+#define SCMR_CPMDF_SHIFT   16
+#define SCMR_PLLDF	   0x00001000	/* PLL Pre-divider Value	*/
+#define SCMR_PLLMF_MSK	   0x00000fff	/* PLL Multiplication Factor Mask*/
+#define SCMR_PLLMF_MSKH7   0x0000000f	/* for HiP7 processors */
 #define SCMR_PLLMF_SHIFT 0
 
 
diff --git a/include/post.h b/include/post.h
index 8f8f1853f7..0f6366868b 100644
--- a/include/post.h
+++ b/include/post.h
@@ -30,8 +30,8 @@
 #ifdef CONFIG_POST
 
 #define POST_POWERON		0x01	/* test runs on power-on booting */
-#define POST_POWERNORMAL	0x02	/* test runs on normal booting */
-#define POST_POWERFAIL		0x04	/* test runs on power-fail booting */
+#define POST_NORMAL		0x02	/* test runs on normal booting */
+#define POST_SLOWTEST		0x04	/* test is slow, enabled by key press */
 #define POST_POWERTEST		0x08	/* test runs after watchdog reset */
 
 #define POST_ROM		0x0100	/* test runs in ROM */
@@ -41,9 +41,9 @@
 #define POST_PREREL             0x1000  /* test runs before relocation */
 
 #define POST_MEM		(POST_RAM | POST_ROM)
-#define POST_ALWAYS		(POST_POWERNORMAL | \
-				 POST_POWERFAIL	  | \
-				 POST_MANUAL	  | \
+#define POST_ALWAYS		(POST_NORMAL	| \
+				 POST_SLOWTEST	| \
+				 POST_MANUAL	| \
 				 POST_POWERON	)
 
 #ifndef	__ASSEMBLY__
@@ -71,6 +71,7 @@ unsigned long post_time_ms (unsigned long base);
 
 extern struct post_test post_list[];
 extern unsigned int post_list_size;
+extern int post_hotkeys_pressed(gd_t *);
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/include/version.h b/include/version.h
index 9d0dbb3cb4..b8632eca0e 100644
--- a/include/version.h
+++ b/include/version.h
@@ -24,6 +24,6 @@
 #ifndef	__VERSION_H__
 #define	__VERSION_H__
 
-#define	U_BOOT_VERSION	"U-Boot 0.4.2"
+#define	U_BOOT_VERSION	"U-Boot 0.4.3"
 
 #endif	/* __VERSION_H__ */
diff --git a/include/video_ad7176.h b/include/video_ad7176.h
index 5b8b010312..92ddcb7d2c 100644
--- a/include/video_ad7176.h
+++ b/include/video_ad7176.h
@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -26,21 +26,21 @@
 
 #define VIDEO_ENCODER_NAME	"Analog Devices AD7176"
 
-#define VIDEO_ENCODER_I2C_RATE	100000	/* Max rate is 100Khz	*/
+#define VIDEO_ENCODER_I2C_RATE	100000	/* Max rate is 100 kHz		*/
 #define VIDEO_ENCODER_CB_Y_CR_Y		/* Use CB Y CR Y format...	*/
 
-#define VIDEO_MODE_YUYV		/* The only mode supported by this encoder	*/
-#undef  VIDEO_MODE_RGB
+#define VIDEO_MODE_YUYV		/* The only mode supported by this encoder */
+#undef	VIDEO_MODE_RGB
 #define VIDEO_MODE_BPP		16
 
-#ifdef  VIDEO_MODE_PAL
+#ifdef	VIDEO_MODE_PAL
 #define VIDEO_ACTIVE_COLS	720
 #define VIDEO_ACTIVE_ROWS	576
 #define VIDEO_VISIBLE_COLS	640
 #define VIDEO_VISIBLE_ROWS	480
 #endif
 
-#ifdef 	VIDEO_MODE_NTSC
+#ifdef	VIDEO_MODE_NTSC
 #define VIDEO_ACTIVE_COLS	720
 #define VIDEO_ACTIVE_ROWS	525
 #define VIDEO_VISIBLE_COLS	640
@@ -54,7 +54,7 @@ static unsigned char video_encoder_data[] = {
 					0x82,
 #else
 					0x02, /* Mode Register 1	*/
-#endif
+#endif	/* VIDEO_DEBUG_COLORBARS */
 					0x16, /* Subcarrier Freq 0	*/
 					0x7c, /* Subcarrier Freq 1	*/
 					0xf0, /* Subcarrier Freq 2	*/
@@ -81,7 +81,7 @@ static unsigned char video_encoder_data[] = {
 					0x82,
 #else
 					0x02, /* Mode Register 1 (2)	*/
-#endif
+#endif	/* VIDEO_DEBUG_COLORBARS */
 					0xcb, /* Subcarrier Freq 0	*/
 					0x8a, /* Subcarrier Freq 1	*/
 					0x09, /* Subcarrier Freq 2	*/
diff --git a/include/video_ad7177.h b/include/video_ad7177.h
index 3f35f335d5..de3863d089 100644
--- a/include/video_ad7177.h
+++ b/include/video_ad7177.h
@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -24,25 +24,25 @@
 #ifndef _VIDEO_AD7177_H_
 #define _VIDEO_AD7177_H_
 
-/*#define VIDEO_DEBUG_DISABLE_COLORS	0 */
+/* #define VIDEO_DEBUG_DISABLE_COLORS	0 */
 
 #define VIDEO_ENCODER_NAME	"Analog Devices AD7177"
 
-#define VIDEO_ENCODER_I2C_RATE	100000	/* Max rate is 100Khz */
-#define VIDEO_ENCODER_CB_Y_CR_Y		/* Use CB Y CR Y format... */
+#define VIDEO_ENCODER_I2C_RATE	100000	/* Max rate is 100 kHz		*/
+#define VIDEO_ENCODER_CB_Y_CR_Y		/* Use CB Y CR Y format...	*/
 
 #define VIDEO_MODE_YUYV		/* The only mode supported by this encoder */
-#undef  VIDEO_MODE_RGB
+#undef	VIDEO_MODE_RGB
 #define VIDEO_MODE_BPP		16
 
-#ifdef  VIDEO_MODE_PAL
+#ifdef	VIDEO_MODE_PAL
 #define VIDEO_ACTIVE_COLS	720
 #define VIDEO_ACTIVE_ROWS	576
 #define VIDEO_VISIBLE_COLS	640
 #define VIDEO_VISIBLE_ROWS	480
 #endif
 
-#ifdef 	VIDEO_MODE_NTSC
+#ifdef	VIDEO_MODE_NTSC
 #define VIDEO_ACTIVE_COLS	720
 #define VIDEO_ACTIVE_ROWS	525
 #define VIDEO_VISIBLE_COLS	640
@@ -52,97 +52,98 @@
 static unsigned char
     video_encoder_data[] = {
 #ifdef VIDEO_MODE_NTSC
-					0x04, /* Mode Register 0 */
+					0x04, /* Mode Register 0	*/
 #ifdef VIDEO_DEBUG_COLORBARS
 					0xc2,
 #else
-					0x42, /* Mode Register 1 */
-#endif
-					0x16, /* Subcarrier Freq 0 */
-					0x7c, /* Subcarrier Freq 1 */
-					0xf0, /* Subcarrier Freq 2 */
-					0x21, /* Subcarrier Freq 3 */
-					0x00, /* Subcarrier phase */
-					0x02, /* Timing Register 0 */
-					0x00, /* Extended Captioning 0 */
-					0x00, /* Extended Captioning 1 */
-					0x00, /* Closed Captioning 0 */
-					0x00, /* Closed Captioning 1 */
-					0x00, /* Timing Register 1 */
-					0x08, /* Mode Register 2 */
-					0x00, /* Pedestal Register 0 */
-					0x00, /* Pedestal Register 1 */
-					0x00, /* Pedestal Register 2 */
-					0x00, /* Pedestal Register 3 */
-					0x08 /* Mode Register 3 */
+					0x42, /* Mode Register 1	*/
+#endif	/* VIDEO_DEBUG_COLORBARS */
+					0x16, /* Subcarrier Freq 0	*/
+					0x7c, /* Subcarrier Freq 1	*/
+					0xf0, /* Subcarrier Freq 2	*/
+					0x21, /* Subcarrier Freq 3	*/
+					0x00, /* Subcarrier phase	*/
+					0x02, /* Timing Register 0	*/
+					0x00, /* Extended Captioning 0	*/
+					0x00, /* Extended Captioning 1	*/
+					0x00, /* Closed Captioning 0	*/
+					0x00, /* Closed Captioning 1	*/
+					0x00, /* Timing Register 1	*/
+					0x08, /* Mode Register 2	*/
+					0x00, /* Pedestal Register 0	*/
+					0x00, /* Pedestal Register 1	*/
+					0x00, /* Pedestal Register 2	*/
+					0x00, /* Pedestal Register 3	*/
+					0x08, /* Mode Register 3	*/
+
+#endif	/* VIDEO_MODE_NTSC */
 
-#endif
 #ifdef VIDEO_MODE_PAL
 #ifdef VIDEO_MODE_RGB_OUT
 
-					0x69, /* Mode Register 0 */
+					0x69, /* Mode Register 0	*/
 #ifdef VIDEO_DEBUG_COLORBARS
-					0xc0, /* Mode Register 1 (c0) */
+					0xc0, /* Mode Register 1 (c0)	*/
 #else
-					0x40, /* Mode Register 1 (c0) */
-#endif
-					0xcb, /* Subcarrier Freq 0 */
-					0x8a, /* Subcarrier Freq 1 */
-					0x09, /* Subcarrier Freq 2 */
-					0x2a, /* Subcarrier Freq 3 */
-					0x00, /* Subcarrier phase */
-					0x02, /* Timing Register 0 */
-					0x00, /* Extended Captioning 0 */
-					0x00, /* Extended Captioning 1 */
-					0x00, /* Closed Captioning 0 */
-					0x00, /* Closed Captioning 1 */
-					0x00, /* Timing Register 1 */
-					0x28, /* Mode Register 2 */
-					0x00, /* Pedestal Register 0 */
-					0x00, /* Pedestal Register 1 */
-					0x00, /* Pedestal Register 2 */
-					0x00, /* Pedestal Register 3 */
-					0x08  /* Mode Register 3 */
+					0x40, /* Mode Register 1 (c0)	*/
+#endif	/* VIDEO_DEBUG_COLORBARS */
+					0xcb, /* Subcarrier Freq 0	*/
+					0x8a, /* Subcarrier Freq 1	*/
+					0x09, /* Subcarrier Freq 2	*/
+					0x2a, /* Subcarrier Freq 3	*/
+					0x00, /* Subcarrier phase	*/
+					0x02, /* Timing Register 0	*/
+					0x00, /* Extended Captioning 0	*/
+					0x00, /* Extended Captioning 1	*/
+					0x00, /* Closed Captioning 0	*/
+					0x00, /* Closed Captioning 1	*/
+					0x00, /* Timing Register 1	*/
+					0x28, /* Mode Register 2	*/
+					0x00, /* Pedestal Register 0	*/
+					0x00, /* Pedestal Register 1	*/
+					0x00, /* Pedestal Register 2	*/
+					0x00, /* Pedestal Register 3	*/
+					0x08, /* Mode Register 3	*/
 
-#else
+#else	/* ! VIDEO_MODE_RGB_OUT */
 
 					0x09, /* Mode Register 0 (was 01) */
 #ifdef VIDEO_DEBUG_COLORBARS
-					0xd8,	/* */
+					0xd8, /*			*/
 #else
 					0x59, /* Mode Register 1 (was 58) */
-#endif
-					0xcb, /* Subcarrier Freq 0 */
-					0x8a, /* Subcarrier Freq 1 */
-					0x09, /* Subcarrier Freq 2 */
-					0x2a, /* Subcarrier Freq 3 */
-					0x00, /* Subcarrier phase */
+#endif	/* VIDEO_DEBUG_COLORBARS */
+					0xcb, /* Subcarrier Freq 0	*/
+					0x8a, /* Subcarrier Freq 1	*/
+					0x09, /* Subcarrier Freq 2	*/
+					0x2a, /* Subcarrier Freq 3	*/
+					0x00, /* Subcarrier phase	*/
 					0x02, /* Timing Register 0 (was a) */
-					0x00, /* Extended Captioning 0 */
-					0x00, /* Extended Captioning 1 */
-					0x00, /* Closed Captioning 0 */
-					0x00, /* Closed Captioning 1 */
-					0x00, /* Timing Register 1 */
+					0x00, /* Extended Captioning 0	*/
+					0x00, /* Extended Captioning 1	*/
+					0x00, /* Closed Captioning 0	*/
+					0x00, /* Closed Captioning 1	*/
+					0x00, /* Timing Register 1	*/
 #ifdef VIDEO_DEBUG_LOWPOWER
 #ifdef VIDEO_DEBUG_DISABLE_COLORS
-					0x98, /* Mode Register 2 */
-#else
-					0x88, /* Mode Register 2 */
-#endif
+					0x98, /* Mode Register 2	*/
 #else
+					0x88, /* Mode Register 2	*/
+#endif	/* VIDEO_DEBUG_DISABLE_COLORS */
+#else	/* ! VIDEO_DEBUG_LOWPOWER */
 #ifdef VIDEO_DEBUG_DISABLE_COLORS
-					0x18, /* Mode Register 2 */
+					0x18, /* Mode Register 2	*/
 #else
-					0x08, /* Mode Register 2 */
-#endif
-#endif
-					0x00, /* Pedestal Register 0 */
-					0x00, /* Pedestal Register 1 */
-					0x00, /* Pedestal Register 2 */
-					0x00, /* Pedestal Register 3 */
-					0x08  /* Mode Register 3 */
-#endif
-#endif
+					0x08, /* Mode Register 2	*/
+#endif	/* VIDEO_DEBUG_DISABLE_COLORS */
+#endif	/* VIDEO_DEBUG_LOWPOWER */
+					0x00, /* Pedestal Register 0	*/
+					0x00, /* Pedestal Register 1	*/
+					0x00, /* Pedestal Register 2	*/
+					0x00, /* Pedestal Register 3	*/
+					0x08  /* Mode Register 3	*/
+#endif	/* VIDEO_MODE_RGB_OUT */
+#endif	/* VIDEO_MODE_PAL */
     } ;
 
-#endif
+#endif	/* _VIDEO_AD7177_H_ */
diff --git a/include/video_ad7179.h b/include/video_ad7179.h
new file mode 100644
index 0000000000..4510d39784
--- /dev/null
+++ b/include/video_ad7179.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2003 Wolfgang Grandegger <wg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _VIDEO_AD7179_H_
+#define _VIDEO_AD7179_H_
+
+/* 
+ * The video encoder data are board specific now!
+ */
+
+#if defined(CONFIG_RRVISION)
+#include "../board/RRvision/video_ad7179.h"
+#else
+#error "Please provide a board-specific video_ad7179.h"
+#endif
+
+#endif /* _VIDEO_AD7179_H_ */