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| author | Grzegorz Bernacki <gjb@semihalf.com> | 2007-09-07 18:20:23 +0200 |
|---|---|---|
| committer | Rafal Jaworowski <raj@semihalf.com> | 2007-09-07 18:20:23 +0200 |
| commit | 7f1913938984ef6c6a46cb53e003719196d9c5de (patch) | |
| tree | 127789e73caeb3464c9941c1f96440031b1e3f6c /include/configs/katmai.h | |
| parent | 15ee4734e4e08003d73d9ead3ca80e2a0672e427 (diff) | |
| download | talos-obmc-uboot-7f1913938984ef6c6a46cb53e003719196d9c5de.tar.gz talos-obmc-uboot-7f1913938984ef6c6a46cb53e003719196d9c5de.zip | |
[PPC440SPe] Improve PCIe configuration space access
- correct configuration space mapping
- correct bus numbering
- better access to config space
Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the
first device on the first bus. We now allow to configure up to 16 buses;
also, scanning for devices behind the PCIe-PCIe bridge is supported, so
peripheral devices farther in hierarchy can be identified.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Diffstat (limited to 'include/configs/katmai.h')
| -rw-r--r-- | include/configs/katmai.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/include/configs/katmai.h b/include/configs/katmai.h index b6d0f519a8..7834e39084 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -66,11 +66,11 @@ #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ #define CFG_PCIE0_CFGBASE 0xc0000000 -#define CFG_PCIE0_XCFGBASE 0xc0000400 -#define CFG_PCIE1_CFGBASE 0xc0001000 -#define CFG_PCIE1_XCFGBASE 0xc0001400 -#define CFG_PCIE2_CFGBASE 0xc0002000 -#define CFG_PCIE2_XCFGBASE 0xc0002400 +#define CFG_PCIE1_CFGBASE 0xc1000000 +#define CFG_PCIE2_CFGBASE 0xc2000000 +#define CFG_PCIE0_XCFGBASE 0xc3000000 +#define CFG_PCIE1_XCFGBASE 0xc3001000 +#define CFG_PCIE2_XCFGBASE 0xc3002000 /* System RAM mapped to PCI space */ #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE |
