From 7f1913938984ef6c6a46cb53e003719196d9c5de Mon Sep 17 00:00:00 2001 From: Grzegorz Bernacki Date: Fri, 7 Sep 2007 18:20:23 +0200 Subject: [PPC440SPe] Improve PCIe configuration space access - correct configuration space mapping - correct bus numbering - better access to config space Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the first device on the first bus. We now allow to configure up to 16 buses; also, scanning for devices behind the PCIe-PCIe bridge is supported, so peripheral devices farther in hierarchy can be identified. Signed-off-by: Grzegorz Bernacki --- include/configs/katmai.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'include/configs/katmai.h') diff --git a/include/configs/katmai.h b/include/configs/katmai.h index b6d0f519a8..7834e39084 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -66,11 +66,11 @@ #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ #define CFG_PCIE0_CFGBASE 0xc0000000 -#define CFG_PCIE0_XCFGBASE 0xc0000400 -#define CFG_PCIE1_CFGBASE 0xc0001000 -#define CFG_PCIE1_XCFGBASE 0xc0001400 -#define CFG_PCIE2_CFGBASE 0xc0002000 -#define CFG_PCIE2_XCFGBASE 0xc0002400 +#define CFG_PCIE1_CFGBASE 0xc1000000 +#define CFG_PCIE2_CFGBASE 0xc2000000 +#define CFG_PCIE0_XCFGBASE 0xc3000000 +#define CFG_PCIE1_XCFGBASE 0xc3001000 +#define CFG_PCIE2_XCFGBASE 0xc3002000 /* System RAM mapped to PCI space */ #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE -- cgit v1.2.1