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| author | Kumar Gala <galak@kernel.crashing.org> | 2010-12-17 07:01:00 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-01-14 01:32:20 -0600 |
| commit | 4d5723da57344cc8f41324fb18b039fb2ce83428 (patch) | |
| tree | bc6ac0dae2cb951c42135a8fb010ca4649160c5d /include/configs/P2020DS.h | |
| parent | 18ea5551307866af06eb7628ec05b1959212efa0 (diff) | |
| download | talos-obmc-uboot-4d5723da57344cc8f41324fb18b039fb2ce83428.tar.gz talos-obmc-uboot-4d5723da57344cc8f41324fb18b039fb2ce83428.zip | |
powerpc/85xx: Rework P2020DS pci_init_board to use common FSL PCIe code
Remove duplicated code in P2020DS board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/P2020DS.h')
| -rw-r--r-- | include/configs/P2020DS.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 0af21528d9..24f2498d07 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -394,6 +394,7 @@ */ /* controller 3, Slot 1, tgtid 3, Base address b000 */ +#define CONFIG_SYS_PCIE3_NAME "Slot 1" #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 @@ -413,6 +414,7 @@ #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 2, direct to uli, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_NAME "ULI" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 @@ -432,6 +434,7 @@ #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 2, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_NAME "Slot 2" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
