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| author | Tom Rini <trini@ti.com> | 2012-09-25 12:23:55 -0700 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2012-09-25 12:23:55 -0700 |
| commit | 5675b509165b67465a20e5cf71e07f40b449ef0c (patch) | |
| tree | 9886f3e8fa8734ec9f8d9cb484fcaa87ff70203f /drivers/misc | |
| parent | ee1f4caaa2a3f79d692155eec8a4c7289d60e106 (diff) | |
| parent | d69dba367aed051663d0ee1ece013c8232bfa9f5 (diff) | |
| download | talos-obmc-uboot-5675b509165b67465a20e5cf71e07f40b449ef0c.tar.gz talos-obmc-uboot-5675b509165b67465a20e5cf71e07f40b449ef0c.zip | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'drivers/misc')
| -rw-r--r-- | drivers/misc/fsl_law.c | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index a7d04b7ea3..223cd5d65c 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -275,5 +275,59 @@ void init_laws(void) law_table[i].size, law_table[i].trgt_id); } +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE + /* check RCW to get which port is used for boot */ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 bootloc = in_be32(&gur->rcwsr[6]); + /* + * in SRIO or PCIE boot we need to set specail LAWs for + * SRIO or PCIE interfaces. + */ + switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) { + case 0x0: /* boot from PCIE1 */ + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_PCIE_1); + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_PCIE_1); + break; + case 0x1: /* boot from PCIE2 */ + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_PCIE_2); + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_PCIE_2); + break; + case 0x2: /* boot from PCIE3 */ + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_PCIE_3); + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_PCIE_3); + break; + case 0x8: /* boot from SRIO1 */ + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_RIO_1); + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_RIO_1); + break; + case 0x9: /* boot from SRIO2 */ + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_RIO_2); + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_RIO_2); + break; + default: + break; + } +#endif + return ; } |
