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| author | Stefano Babic <sbabic@denx.de> | 2016-06-18 10:24:54 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-06-18 10:25:13 +0200 |
| commit | dc557e9a1fe00ca9d884bd88feef5bebf23fede4 (patch) | |
| tree | ec09fdf8f7c4c44e30f4b38b7459a2cbbb71d094 /board/freescale/ls1043ardb/README | |
| parent | d2ba7a6adcef6e6f8c4418c7b0caf9d7ab98a6d4 (diff) | |
| parent | 6b3943f1b04be60f147ee540fbd72c4c7ea89f80 (diff) | |
| download | talos-obmc-uboot-dc557e9a1fe00ca9d884bd88feef5bebf23fede4.tar.gz talos-obmc-uboot-dc557e9a1fe00ca9d884bd88feef5bebf23fede4.zip | |
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'board/freescale/ls1043ardb/README')
| -rw-r--r-- | board/freescale/ls1043ardb/README | 37 |
1 files changed, 2 insertions, 35 deletions
diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README index 0556e73b3a..709ddbbef3 100644 --- a/board/freescale/ls1043ardb/README +++ b/board/freescale/ls1043ardb/README @@ -8,41 +8,8 @@ debugging environment. The LS1043A RDB is lead-free and RoHS-compliant. LS1043A SoC Overview -------------------- -The LS1043A integrated multicore processor combines four ARM Cortex-A53 -processor cores with datapath acceleration optimized for L2/3 packet -processing, single pass security offload and robust traffic management -and quality of service. - -The LS1043A SoC includes the following function and features: - - Four 64-bit ARM Cortex-A53 CPUs - - 1 MB unified L2 Cache - - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving - support - - Data Path Acceleration Architecture (DPAA) incorporating acceleration the - the following functions: - - Packet parsing, classification, and distribution (FMan) - - Queue management for scheduling, packet sequencing, and congestion - management (QMan) - - Hardware buffer management for buffer allocation and de-allocation (BMan) - - Cryptography acceleration (SEC) - - Ethernet interfaces by FMan - - Up to 1 x XFI supporting 10G interface - - Up to 1 x QSGMII - - Up to 4 x SGMII supporting 1000Mbps - - Up to 2 x SGMII supporting 2500Mbps - - Up to 2 x RGMII supporting 1000Mbps - - High-speed peripheral interfaces - - Three PCIe 2.0 controllers, one supporting x4 operation - - One serial ATA (SATA 3.0) controllers - - Additional peripheral interfaces - - Three high-speed USB 3.0 controllers with integrated PHY - - Enhanced secure digital host controller (eSDXC/eMMC) - - Quad Serial Peripheral Interface (QSPI) Controller - - Serial peripheral interface (SPI) controller - - Four I2C controllers - - Two DUARTs - - Integrated flash controller supporting NAND and NOR flash - - QorIQ platform's trust architecture 2.1 +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A +SoC overview. LS1043ARDB board Overview ----------------------- |
