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| author | Bin Meng <bmeng.cn@gmail.com> | 2015-09-14 00:07:41 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-09-16 19:53:53 -0600 |
| commit | c6d4705f41d4e45e8cecc6e08b0b89df1ffe57ef (patch) | |
| tree | 85ef8dec9348cc1e33f4cf0daa4082c0cae2520e /arch/x86/cpu/quark/dram.c | |
| parent | 0993fc026b5003cfc7da9abe8a3fddbd26c7ee44 (diff) | |
| download | talos-obmc-uboot-c6d4705f41d4e45e8cecc6e08b0b89df1ffe57ef.tar.gz talos-obmc-uboot-c6d4705f41d4e45e8cecc6e08b0b89df1ffe57ef.zip | |
x86: quark: Configure MTRR to enable cache
Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
are accessed indirectly via the message port and not the traditional
MSR mechanism. Only UC, WT and WB cache types are supported.
We configure all the fixed range MTRRs with common values (VGA RAM
as UC, others as WB) and 3 variable range MTRRs for ROM/eSRAM/RAM as
WB, which significantly improves the boot time performance.
With this commit, it takes only 2 seconds for U-Boot to boot to shell
on Intel Galileo board. Previously it took about 6 seconds.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/quark/dram.c')
| -rw-r--r-- | arch/x86/cpu/quark/dram.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c index 9cac846c69..1b89376387 100644 --- a/arch/x86/cpu/quark/dram.c +++ b/arch/x86/cpu/quark/dram.c @@ -7,8 +7,10 @@ #include <common.h> #include <errno.h> #include <fdtdec.h> +#include <asm/mtrr.h> #include <asm/post.h> #include <asm/arch/mrc.h> +#include <asm/arch/msg_port.h> #include <asm/arch/quark.h> DECLARE_GLOBAL_DATA_PTR; @@ -111,6 +113,14 @@ int dram_init(void) gd->ram_size = mrc_params.mem_size; post_code(POST_DRAM); + /* variable range MTRR#2: RAM area */ + disable_caches(); + msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_RAM), + 0 | MTRR_TYPE_WRBACK); + msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_RAM), + (~(gd->ram_size - 1)) | MTRR_PHYS_MASK_VALID); + enable_caches(); + return 0; } |
