From c6d4705f41d4e45e8cecc6e08b0b89df1ffe57ef Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 14 Sep 2015 00:07:41 -0700 Subject: x86: quark: Configure MTRR to enable cache Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs are accessed indirectly via the message port and not the traditional MSR mechanism. Only UC, WT and WB cache types are supported. We configure all the fixed range MTRRs with common values (VGA RAM as UC, others as WB) and 3 variable range MTRRs for ROM/eSRAM/RAM as WB, which significantly improves the boot time performance. With this commit, it takes only 2 seconds for U-Boot to boot to shell on Intel Galileo board. Previously it took about 6 seconds. Signed-off-by: Bin Meng Acked-by: Simon Glass Tested-by: Simon Glass --- arch/x86/cpu/quark/dram.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/x86/cpu/quark/dram.c') diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c index 9cac846c69..1b89376387 100644 --- a/arch/x86/cpu/quark/dram.c +++ b/arch/x86/cpu/quark/dram.c @@ -7,8 +7,10 @@ #include #include #include +#include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -111,6 +113,14 @@ int dram_init(void) gd->ram_size = mrc_params.mem_size; post_code(POST_DRAM); + /* variable range MTRR#2: RAM area */ + disable_caches(); + msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_RAM), + 0 | MTRR_TYPE_WRBACK); + msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_RAM), + (~(gd->ram_size - 1)) | MTRR_PHYS_MASK_VALID); + enable_caches(); + return 0; } -- cgit v1.2.1