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author | Lokesh Vutla <lokeshvutla@ti.com> | 2015-07-28 14:16:48 +0530 |
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committer | Tom Rini <trini@konsulko.com> | 2015-08-12 20:47:55 -0400 |
commit | fe772ebd285b4c442a2406419c49a4c7e829d83a (patch) | |
tree | ad6986280bb64fe2448e9431e2b194761644a0fc /arch/arm/mach-keystone/include/mach/clock_defs.h | |
parent | 7531122e5ca64fd1d5b9a1feffa25bc812a627a6 (diff) | |
download | talos-obmc-uboot-fe772ebd285b4c442a2406419c49a4c7e829d83a.tar.gz talos-obmc-uboot-fe772ebd285b4c442a2406419c49a4c7e829d83a.zip |
ARM: keystone2: Use common definition for clk_get_rate
Since all the clocks are defined common, and has the same logic to get
the frequencies, use a common definition for for clk_get_rate().
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/mach-keystone/include/mach/clock_defs.h')
-rw-r--r-- | arch/arm/mach-keystone/include/mach/clock_defs.h | 32 |
1 files changed, 0 insertions, 32 deletions
diff --git a/arch/arm/mach-keystone/include/mach/clock_defs.h b/arch/arm/mach-keystone/include/mach/clock_defs.h index 1c9dc3e745..8ad371f43d 100644 --- a/arch/arm/mach-keystone/include/mach/clock_defs.h +++ b/arch/arm/mach-keystone/include/mach/clock_defs.h @@ -69,38 +69,6 @@ static struct pllctl_regs *pllctl_regs[] = { #define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1) -#define PLLCTL_BYPASS BIT(23) -#define PLL_PLLRST BIT(14) -#define PLLCTL_PAPLL BIT(13) -#define PLLCTL_CLKMODE BIT(8) -#define PLLCTL_PLLSELB BIT(7) -#define PLLCTL_ENSAT BIT(6) -#define PLLCTL_PLLENSRC BIT(5) -#define PLLCTL_PLLDIS BIT(4) -#define PLLCTL_PLLRST BIT(3) -#define PLLCTL_PLLPWRDN BIT(1) -#define PLLCTL_PLLEN BIT(0) -#define PLLSTAT_GO BIT(0) - -#define MAIN_ENSAT_OFFSET 6 - -#define PLLDIV_ENABLE BIT(15) - -#define PLL_DIV_MASK 0x3f -#define PLL_MULT_MASK 0x1fff -#define PLL_MULT_SHIFT 6 -#define PLLM_MULT_HI_MASK 0x7f -#define PLLM_MULT_HI_SHIFT 12 -#define PLLM_MULT_HI_SMASK (PLLM_MULT_HI_MASK << PLLM_MULT_HI_SHIFT) -#define PLLM_MULT_LO_MASK 0x3f -#define PLL_CLKOD_MASK 0xf -#define PLL_CLKOD_SHIFT 19 -#define PLL_CLKOD_SMASK (PLL_CLKOD_MASK << PLL_CLKOD_SHIFT) -#define PLL_BWADJ_LO_MASK 0xff -#define PLL_BWADJ_LO_SHIFT 24 -#define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT) -#define PLL_BWADJ_HI_MASK 0xf - /* PLLCTL Bits */ #define PLLCTL_PLLENSRC_SHIF 5 #define PLLCTL_PLLENSRC_MASK BIT(5) |