ARM: keystone2: Use common definition for clk_get_rate

Since all the clocks are defined common, and has the same logic to get
the frequencies, use a common definition for for clk_get_rate().

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

5 files changed, 23 insertions, 98 deletions

diff --git a/arch/arm/mach-keystone/include/mach/clock-k2e.h b/arch/arm/mach-keystone/include/mach/clock-k2e.h
index e66ad692da..4618560dd8 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2e.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2e.h
@@ -10,27 +10,6 @@
 #ifndef __ASM_ARCH_CLOCK_K2E_H
 #define __ASM_ARCH_CLOCK_K2E_H
 
-#define CLK_LIST(CLK)\
-	CLK(0, core_pll_clk)\
-	CLK(1, pass_pll_clk)\
-	CLK(2, ddr3_pll_clk)\
-	CLK(3, sys_clk0_clk)\
-	CLK(4, sys_clk0_1_clk)\
-	CLK(5, sys_clk0_2_clk)\
-	CLK(6, sys_clk0_3_clk)\
-	CLK(7, sys_clk0_4_clk)\
-	CLK(8, sys_clk0_6_clk)\
-	CLK(9, sys_clk0_8_clk)\
-	CLK(10, sys_clk0_12_clk)\
-	CLK(11, sys_clk0_24_clk)\
-	CLK(12, sys_clk1_clk)\
-	CLK(13, sys_clk1_3_clk)\
-	CLK(14, sys_clk1_4_clk)\
-	CLK(15, sys_clk1_6_clk)\
-	CLK(16, sys_clk1_12_clk)\
-	CLK(17, sys_clk2_clk)\
-	CLK(18, sys_clk3_clk)
-
 #define PLLSET_CMD_LIST	"<pa|ddr3>"
 
 #define KS2_CLK1_6	sys_clk0_6_clk
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2hk.h b/arch/arm/mach-keystone/include/mach/clock-k2hk.h
index 775a9cb418..b8f3e76291 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2hk.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2hk.h
@@ -10,29 +10,6 @@
 #ifndef __ASM_ARCH_CLOCK_K2HK_H
 #define __ASM_ARCH_CLOCK_K2HK_H
 
-#define CLK_LIST(CLK)\
-	CLK(0, core_pll_clk)\
-	CLK(1, pass_pll_clk)\
-	CLK(2, tetris_pll_clk)\
-	CLK(3, ddr3a_pll_clk)\
-	CLK(4, ddr3b_pll_clk)\
-	CLK(5, sys_clk0_clk)\
-	CLK(6, sys_clk0_1_clk)\
-	CLK(7, sys_clk0_2_clk)\
-	CLK(8, sys_clk0_3_clk)\
-	CLK(9, sys_clk0_4_clk)\
-	CLK(10, sys_clk0_6_clk)\
-	CLK(11, sys_clk0_8_clk)\
-	CLK(12, sys_clk0_12_clk)\
-	CLK(13, sys_clk0_24_clk)\
-	CLK(14, sys_clk1_clk)\
-	CLK(15, sys_clk1_3_clk)\
-	CLK(16, sys_clk1_4_clk)\
-	CLK(17, sys_clk1_6_clk)\
-	CLK(18, sys_clk1_12_clk)\
-	CLK(19, sys_clk2_clk)\
-	CLK(20, sys_clk3_clk)
-
 #define PLLSET_CMD_LIST		"<pa|arm|ddr3a|ddr3b>"
 
 #define KS2_CLK1_6 sys_clk0_6_clk
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2l.h b/arch/arm/mach-keystone/include/mach/clock-k2l.h
index 485746dea2..8772a7dcb1 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2l.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2l.h
@@ -10,28 +10,6 @@
 #ifndef __ASM_ARCH_CLOCK_K2L_H
 #define __ASM_ARCH_CLOCK_K2L_H
 
-#define CLK_LIST(CLK)\
-	CLK(0, core_pll_clk)\
-	CLK(1, pass_pll_clk)\
-	CLK(2, tetris_pll_clk)\
-	CLK(3, ddr3_pll_clk)\
-	CLK(4, sys_clk0_clk)\
-	CLK(5, sys_clk0_1_clk)\
-	CLK(6, sys_clk0_2_clk)\
-	CLK(7, sys_clk0_3_clk)\
-	CLK(8, sys_clk0_4_clk)\
-	CLK(9, sys_clk0_6_clk)\
-	CLK(10, sys_clk0_8_clk)\
-	CLK(11, sys_clk0_12_clk)\
-	CLK(12, sys_clk0_24_clk)\
-	CLK(13, sys_clk1_clk)\
-	CLK(14, sys_clk1_3_clk)\
-	CLK(15, sys_clk1_4_clk)\
-	CLK(16, sys_clk1_6_clk)\
-	CLK(17, sys_clk1_12_clk)\
-	CLK(18, sys_clk2_clk)\
-	CLK(19, sys_clk3_clk)\
-
 #define PLLSET_CMD_LIST	"<pa|arm|ddr3>"
 
 #define KS2_CLK1_6	sys_clk0_6_clk
diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h
index d0bcee7281..ddc5f8e501 100644
--- a/arch/arm/mach-keystone/include/mach/clock.h
+++ b/arch/arm/mach-keystone/include/mach/clock.h
@@ -27,6 +27,29 @@
 #define CORE_PLL MAIN_PLL
 #define DDR3_PLL DDR3A_PLL
 
+#define CLK_LIST(CLK)\
+	CLK(0, core_pll_clk)\
+	CLK(1, pass_pll_clk)\
+	CLK(2, tetris_pll_clk)\
+	CLK(3, ddr3a_pll_clk)\
+	CLK(4, ddr3b_pll_clk)\
+	CLK(5, sys_clk0_clk)\
+	CLK(6, sys_clk0_1_clk)\
+	CLK(7, sys_clk0_2_clk)\
+	CLK(8, sys_clk0_3_clk)\
+	CLK(9, sys_clk0_4_clk)\
+	CLK(10, sys_clk0_6_clk)\
+	CLK(11, sys_clk0_8_clk)\
+	CLK(12, sys_clk0_12_clk)\
+	CLK(13, sys_clk0_24_clk)\
+	CLK(14, sys_clk1_clk)\
+	CLK(15, sys_clk1_3_clk)\
+	CLK(16, sys_clk1_4_clk)\
+	CLK(17, sys_clk1_6_clk)\
+	CLK(18, sys_clk1_12_clk)\
+	CLK(19, sys_clk2_clk)\
+	CLK(20, sys_clk3_clk)
+
 #include <asm/types.h>
 
 #define GENERATE_ENUM(NUM, ENUM) ENUM = NUM,
diff --git a/arch/arm/mach-keystone/include/mach/clock_defs.h b/arch/arm/mach-keystone/include/mach/clock_defs.h
index 1c9dc3e745..8ad371f43d 100644
--- a/arch/arm/mach-keystone/include/mach/clock_defs.h
+++ b/arch/arm/mach-keystone/include/mach/clock_defs.h
@@ -69,38 +69,6 @@ static struct pllctl_regs *pllctl_regs[] = {
 
 #define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1)
 
-#define PLLCTL_BYPASS           BIT(23)
-#define PLL_PLLRST              BIT(14)
-#define PLLCTL_PAPLL            BIT(13)
-#define PLLCTL_CLKMODE          BIT(8)
-#define PLLCTL_PLLSELB          BIT(7)
-#define PLLCTL_ENSAT            BIT(6)
-#define PLLCTL_PLLENSRC         BIT(5)
-#define PLLCTL_PLLDIS           BIT(4)
-#define PLLCTL_PLLRST           BIT(3)
-#define PLLCTL_PLLPWRDN         BIT(1)
-#define PLLCTL_PLLEN            BIT(0)
-#define PLLSTAT_GO              BIT(0)
-
-#define MAIN_ENSAT_OFFSET       6
-
-#define PLLDIV_ENABLE           BIT(15)
-
-#define PLL_DIV_MASK            0x3f
-#define PLL_MULT_MASK           0x1fff
-#define PLL_MULT_SHIFT          6
-#define PLLM_MULT_HI_MASK       0x7f
-#define PLLM_MULT_HI_SHIFT      12
-#define PLLM_MULT_HI_SMASK      (PLLM_MULT_HI_MASK << PLLM_MULT_HI_SHIFT)
-#define PLLM_MULT_LO_MASK       0x3f
-#define PLL_CLKOD_MASK          0xf
-#define PLL_CLKOD_SHIFT         19
-#define PLL_CLKOD_SMASK         (PLL_CLKOD_MASK << PLL_CLKOD_SHIFT)
-#define PLL_BWADJ_LO_MASK       0xff
-#define PLL_BWADJ_LO_SHIFT      24
-#define PLL_BWADJ_LO_SMASK      (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT)
-#define PLL_BWADJ_HI_MASK       0xf
-
 /* PLLCTL Bits */
 #define PLLCTL_PLLENSRC_SHIF	5
 #define PLLCTL_PLLENSRC_MASK	BIT(5)