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| author | Rajeshwari Shinde <rajeshwari.s@samsung.com> | 2012-07-03 20:02:58 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 14:58:23 +0200 |
| commit | 10bc1a7f49b2efec3eddca18949d28ad053f40bb (patch) | |
| tree | 4cffef2e3598c26d5194befa20fd1f3e42cfc722 /arch/arm/include/asm/arch-exynos | |
| parent | 6071bcaec1cbbdd2679f9abdd36dfe16114bc315 (diff) | |
| download | talos-obmc-uboot-10bc1a7f49b2efec3eddca18949d28ad053f40bb.tar.gz talos-obmc-uboot-10bc1a7f49b2efec3eddca18949d28ad053f40bb.zip | |
EXYNOS5: CLOCK: Add BPLL support
This patch adds support for BPLL clock.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/include/asm/arch-exynos')
| -rw-r--r-- | arch/arm/include/asm/arch-exynos/clk.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-exynos/clock.h | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 72dc655ec1..552902573f 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -27,6 +27,7 @@ #define EPLL 2 #define HPLL 3 #define VPLL 4 +#define BPLL 5 unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index bf41c1959f..fce38efbb2 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -599,4 +599,6 @@ struct exynos5_clock { #define MPLL_FOUT_SEL_SHIFT 4 #define MPLL_FOUT_SEL_MASK 0x1 +#define BPLL_FOUT_SEL_SHIFT 0 +#define BPLL_FOUT_SEL_MASK 0x1 #endif |
