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| author | Rajeshwari Shinde <rajeshwari.s@samsung.com> | 2012-07-03 20:02:57 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 14:58:23 +0200 |
| commit | 6071bcaec1cbbdd2679f9abdd36dfe16114bc315 (patch) | |
| tree | 142468c8d25f58f06e357b947298461c28a04dfa /arch/arm/include/asm/arch-exynos | |
| parent | 87f2e079dbbe517003bd2c3910ae2512ab27a6f5 (diff) | |
| download | talos-obmc-uboot-6071bcaec1cbbdd2679f9abdd36dfe16114bc315.tar.gz talos-obmc-uboot-6071bcaec1cbbdd2679f9abdd36dfe16114bc315.zip | |
EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0
MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/include/asm/arch-exynos')
| -rw-r--r-- | arch/arm/include/asm/arch-exynos/clock.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index 90271f1a48..bf41c1959f 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -596,4 +596,7 @@ struct exynos5_clock { unsigned char res123[0xf5d8]; }; #endif + +#define MPLL_FOUT_SEL_SHIFT 4 +#define MPLL_FOUT_SEL_MASK 0x1 #endif |
