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path: root/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
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* drm/i915/selftests: Live tests emit requests and so require rpmChris Wilson2018-09-201-0/+2
* drm/i915/selftests: Replace opencoded clflush with drm_clflush_virt_rangeChris Wilson2018-07-301-21/+17
* drm/i915/selftests: Provide full mb() around clflushChris Wilson2018-07-061-3/+18
* drm/i915: Start returning an error from i915_vma_move_to_active()Chris Wilson2018-07-061-2/+2
* drm/i915: Refactor export_fence() after i915_vma_move_to_active()Chris Wilson2018-07-061-4/+0
* drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUALChris Wilson2018-07-061-2/+2
* drm/i915/selftests: Skip using the GPU if wedgedChris Wilson2018-07-061-1/+9
* drm/i915: Make closing request flush mandatoryChris Wilson2018-06-141-2/+2
* drm/i915: Rename drm_i915_gem_request to i915_requestChris Wilson2018-02-211-4/+4
* drm/i915/selftests: Markup __iomem for igt_gem_coherencyChris Wilson2017-11-151-8/+8
* drm/i915: Don't use MI_STORE_DWORD_IMM on Sandybridge/vcsChris Wilson2017-08-181-1/+1
* drm/i915: Treat WC a separate cache domainChris Wilson2017-04-121-8/+2
* drm/i915: Combine write_domain flushes to a single functionChris Wilson2017-04-121-2/+2
* drm/i915: Silence compiler warning for seltests/i915_gem_coherencyChris Wilson2017-02-141-1/+1
* drm/i915: Emit to ringbuffer directlyTvrtko Ursulin2017-02-141-16/+17
* drm/i915: Test coherency of and barriers between cache domainsChris Wilson2017-02-131-0/+384
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