Commit message (Expand) | Author | Age | Files | Lines | |
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* | RISC-V: Add _TIF_NEED_RESCHED check for kernel thread when CONFIG_PREEMPT=y | Vincent Chen | 2019-01-23 | 1 | -1/+17 |
* | riscv: add audit support | David Abdurachmanov | 2019-01-07 | 1 | -2/+2 |
* | RISC-V: SMP cleanup and new features | Palmer Dabbelt | 2018-10-22 | 1 | -1/+0 |
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| * | RISC-V: No need to pass scause as arg to do_IRQ() | Anup Patel | 2018-10-22 | 1 | -1/+0 |
* | | Extract FPU context operations from entry.S | Alan Kao | 2018-10-22 | 1 | -87/+0 |
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* | RISC-V: implement low-level interrupt handling | Christoph Hellwig | 2018-08-13 | 1 | -2/+2 |
* | RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler | Palmer Dabbelt | 2018-03-14 | 1 | -4/+3 |
* | RISC-V: Enable IRQ during exception handling | zongbox@gmail.com | 2018-02-20 | 1 | -2/+3 |
* | riscv: disable SUM in the exception handler | Christoph Hellwig | 2018-01-30 | 1 | -3/+6 |
* | riscv: rename SR_* constants to match the spec | Christoph Hellwig | 2018-01-07 | 1 | -4/+4 |
* | RISC-V: Task implementation | Palmer Dabbelt | 2017-09-26 | 1 | -0/+464 |