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path: root/arch/riscv/kernel/entry.S
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* RISC-V: Add _TIF_NEED_RESCHED check for kernel thread when CONFIG_PREEMPT=yVincent Chen2019-01-231-1/+17
* riscv: add audit supportDavid Abdurachmanov2019-01-071-2/+2
* RISC-V: SMP cleanup and new featuresPalmer Dabbelt2018-10-221-1/+0
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| * RISC-V: No need to pass scause as arg to do_IRQ()Anup Patel2018-10-221-1/+0
* | Extract FPU context operations from entry.SAlan Kao2018-10-221-87/+0
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* RISC-V: implement low-level interrupt handlingChristoph Hellwig2018-08-131-2/+2
* RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handlerPalmer Dabbelt2018-03-141-4/+3
* RISC-V: Enable IRQ during exception handlingzongbox@gmail.com2018-02-201-2/+3
* riscv: disable SUM in the exception handlerChristoph Hellwig2018-01-301-3/+6
* riscv: rename SR_* constants to match the specChristoph Hellwig2018-01-071-4/+4
* RISC-V: Task implementationPalmer Dabbelt2017-09-261-0/+464
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