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path: root/arch/arm/mm/proc-v7-2level.S
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* ARM: spectre-v2: harden branch predictor on context switchesRussell King2018-05-311-6/+0
*-. Merge branches 'arnd-fixes', 'clk', 'misc', 'v7' and 'fixes' into for-nextRussell King2015-06-121-5/+7
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| | * ARM: redo TTBR setup code for LPAERussell King2015-06-011-3/+3
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| * ARM: 8353/1: mm: Fix Cortex-A8 erratum 430973 segfaults for bootloaders and m...Tony Lindgren2015-05-081-2/+4
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* ARM: proc-v7: avoid errata 430973 workaround for non-Cortex A8 CPUsRussell King2015-04-141-4/+8
* ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+Russell King2014-07-181-2/+2
* ARM: 7954/1: mm: remove remaining domain support from ARMv6Will Deacon2014-02-101-7/+0
* ARM: 7784/1: mm: ensure SMP alternates assemble to exactly 4 bytes with Thumb-2Will Deacon2013-07-221-1/+1
* arm: delete __cpuinit/__CPUINIT usage from all ARM usersPaul Gortmaker2013-07-141-4/+0
* ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP insteadWill Deacon2013-04-031-1/+2
* ARM: 7650/1: mm: replace direct access to mm->context.id with new macroBen Dooks2013-02-161-1/+1
* ARM: mm: introduce present, faulting entries for PAGE_NONEWill Deacon2012-11-091-0/+4
* ARM: mm: introduce L_PTE_VALID for page table entriesWill Deacon2012-11-091-1/+1
* ARM: mm: don't use the access flag permissions mechanism for classic MMUWill Deacon2012-11-091-2/+2
* ARM: 7445/1: mm: update CONTEXTIDR register to contain PID of current processWill Deacon2012-07-091-0/+5
* ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on ASID-capable CPUsCatalin Marinas2012-04-171-3/+0
* ARM: Use TTBR1 instead of reserved context IDWill Deacon2012-04-171-6/+4
* ARM: LPAE: Factor out classic-MMU specific code into proc-v7-2level.SCatalin Marinas2011-12-081-0/+171
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