diff options
| -rw-r--r-- | drivers/media/video/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/media/video/cx231xx/Kconfig | 50 | ||||
| -rw-r--r-- | drivers/media/video/cx231xx/Makefile | 7 | ||||
| -rw-r--r-- | drivers/media/video/cx231xx/cx231xx-audio.c | 14 | ||||
| -rw-r--r-- | drivers/media/video/cx231xx/cx231xx-avcore.c | 305 | ||||
| -rw-r--r-- | drivers/media/video/cx231xx/cx231xx-cards.c | 248 | ||||
| -rw-r--r-- | drivers/media/video/cx231xx/cx231xx-conf-reg.h | 299 | ||||
| -rw-r--r-- | drivers/media/video/cx231xx/cx231xx-core.c | 13 | ||||
| -rw-r--r-- | drivers/media/video/cx231xx/cx231xx-i2c.c | 12 | ||||
| -rw-r--r-- | drivers/media/video/cx231xx/cx231xx-pcb-cfg.c | 793 | ||||
| -rw-r--r-- | drivers/media/video/cx231xx/cx231xx-pcb-cfg.h | 235 | ||||
| -rw-r--r-- | drivers/media/video/cx231xx/cx231xx-reg.h | 934 | ||||
| -rw-r--r-- | drivers/media/video/cx231xx/cx231xx-video.c | 8 | ||||
| -rw-r--r-- | drivers/media/video/cx231xx/cx231xx.h | 14 |
14 files changed, 1963 insertions, 971 deletions
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig index 159229fc838d..9d48da2fb013 100644 --- a/drivers/media/video/Kconfig +++ b/drivers/media/video/Kconfig @@ -807,6 +807,8 @@ source "drivers/media/video/hdpvr/Kconfig" source "drivers/media/video/em28xx/Kconfig" +source "drivers/media/video/cx231xx/Kconfig" + source "drivers/media/video/usbvision/Kconfig" source "drivers/media/video/usbvideo/Kconfig" diff --git a/drivers/media/video/cx231xx/Kconfig b/drivers/media/video/cx231xx/Kconfig index 0f0e2b9d9853..7a6700fb0376 100644 --- a/drivers/media/video/cx231xx/Kconfig +++ b/drivers/media/video/cx231xx/Kconfig @@ -1,35 +1,35 @@ config VIDEO_CX231XX - tristate "Conexant cx231xx USB video capture support" - depends on VIDEO_DEV && I2C && INPUT - select VIDEO_TUNER - select VIDEO_TVEEPROM - select VIDEO_IR - select VIDEOBUF_VMALLOC - select VIDEO_CX25840 - select VIDEO_CX231XX_ALSA + tristate "Conexant cx231xx USB video capture support" + depends on VIDEO_DEV && I2C && INPUT + select VIDEO_TUNER + select VIDEO_TVEEPROM + select VIDEO_IR + select VIDEOBUF_VMALLOC + select VIDEO_CX25840 + select VIDEO_CX231XX_ALSA - ---help--- - This is a video4linux driver for Conexant 231xx USB based TV cards. + ---help--- + This is a video4linux driver for Conexant 231xx USB based TV cards. - To compile this driver as a module, choose M here: the - module will be called cx231xx + To compile this driver as a module, choose M here: the + module will be called cx231xx config VIDEO_CX231XX_ALSA tristate "Conexant Cx231xx ALSA audio module" - depends on VIDEO_CX231XX && SND - select SND_PCM + depends on VIDEO_CX231XX && SND + select SND_PCM - ---help--- - This is an ALSA driver for Cx231xx USB based TV cards. + ---help--- + This is an ALSA driver for Cx231xx USB based TV cards. - To compile this driver as a module, choose M here: the - module will be called cx231xx-alsa + To compile this driver as a module, choose M here: the + module will be called cx231xx-alsa config VIDEO_CX231XX_DVB - tristate "DVB/ATSC Support for Cx231xx based TV cards" - depends on VIDEO_CX231XX && DVB_CORE - select VIDEOBUF_DVB - select MEDIA_TUNER_XC5000 if !DVB_FE_CUSTOMIZE - ---help--- - This adds support for DVB cards based on the - Conexant cx231xx chips. + tristate "DVB/ATSC Support for Cx231xx based TV cards" + depends on VIDEO_CX231XX && DVB_CORE + select VIDEOBUF_DVB + select MEDIA_TUNER_XC5000 if !DVB_FE_CUSTOMISE + ---help--- + This adds support for DVB cards based on the + Conexant cx231xx chips. diff --git a/drivers/media/video/cx231xx/Makefile b/drivers/media/video/cx231xx/Makefile index 2590a09f3442..1dad93619934 100644 --- a/drivers/media/video/cx231xx/Makefile +++ b/drivers/media/video/cx231xx/Makefile @@ -1,11 +1,8 @@ cx231xx-objs := cx231xx-video.o cx231xx-i2c.o cx231xx-cards.o cx231xx-core.o \ - cx231xx-avcore.o cx231xx-pcb-config.o cx231xx-vbi.o - -cx231xx-alsa-objs := cx231xx-audio.o - + cx231xx-avcore.o cx231xx-pcb-cfg.o cx231xx-vbi.o obj-$(CONFIG_VIDEO_CX231XX) += cx231xx.o -obj-$(CONFIG_VIDEO_CX231XX_ALSA) += cx231xx-alsa.o +obj-$(CONFIG_VIDEO_CX231XX_ALSA) += cx231xx-audio.o obj-$(CONFIG_VIDEO_CX231XX_DVB) += cx231xx-dvb.o EXTRA_CFLAGS += -Idrivers/media/video diff --git a/drivers/media/video/cx231xx/cx231xx-audio.c b/drivers/media/video/cx231xx/cx231xx-audio.c index 044edbc2d844..0027b906f614 100644 --- a/drivers/media/video/cx231xx/cx231xx-audio.c +++ b/drivers/media/video/cx231xx/cx231xx-audio.c @@ -38,16 +38,15 @@ #include <sound/control.h> #include <media/v4l2-common.h> #include "cx231xx.h" -#include "cx231xx-pcb-config.h" static int debug; module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "activates debug info"); #define dprintk(fmt, arg...) do { \ - if (debug) \ - printk(KERN_INFO "cx231xx-audio %s: " fmt, \ - __func__, ##arg); \ + if (debug) \ + printk(KERN_INFO "cx231xx-audio %s: " fmt, \ + __func__, ##arg); \ } while (0) static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; @@ -262,9 +261,10 @@ static int snd_pcm_alloc_vmalloc_buffer(struct snd_pcm_substream *subs, } static struct snd_pcm_hardware snd_cx231xx_hw_capture = { - .info = SNDRV_PCM_INFO_BLOCK_TRANSFER | - SNDRV_PCM_INFO_MMAP | - SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP_VALID, + .info = SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_MMAP_VALID, .formats = SNDRV_PCM_FMTBIT_S16_LE, diff --git a/drivers/media/video/cx231xx/cx231xx-avcore.c b/drivers/media/video/cx231xx/cx231xx-avcore.c index 8bbe518f4837..226299d62d7e 100644 --- a/drivers/media/video/cx231xx/cx231xx-avcore.c +++ b/drivers/media/video/cx231xx/cx231xx-avcore.c @@ -41,7 +41,7 @@ /****************************************************************************** * C O L I B R I - B L O C K C O N T R O L functions * - ********************************************************************* ********/ + ******************************************************************************/ int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count) { int status = 0; @@ -53,29 +53,44 @@ int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count) temp = (u8) (ref_count & 0xff); status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE2, 2, temp, 1); + if (status < 0) + return status; status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE2, 2, &colibri_power_status, 1); + if (status < 0) + return status; temp = (u8) ((ref_count & 0x300) >> 8); temp |= 0x40; status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE1, 2, temp, 1); + if (status < 0) + return status; + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PLL2, 2, 0x0f, 1); + if (status < 0) + return status; /* enable pll */ while (colibri_power_status != 0x18) { status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, 0x18, 1); + if (status < 0) { + cx231xx_info( + ": Init Super Block failed in send cmd\n"); + break; + } + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, &colibri_power_status, 1); colibri_power_status &= 0xff; if (status < 0) { cx231xx_info( - ": Init Super Block failed in send/receive cmds\n"); + ": Init Super Block failed in receive cmd\n"); break; } i++; @@ -93,6 +108,9 @@ int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count) /* start tuning filter */ status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE3, 2, 0x40, 1); + if (status < 0) + return status; + msleep(5); /* exit tuning */ @@ -188,7 +206,10 @@ int cx231xx_colibri_setup_AFE_for_baseband(struct cx231xx *dev) } /* - we have 3 channel + The Analog Front End in Cx231xx has 3 channels. These + channels are used to share between different inputs + like tuner, s-video and composite inputs. + channel 1 ----- pin 1 to pin4(in reg is 1-4) channel 2 ----- pin 5 to pin8(in reg is 5-8) channel 3 ----- pin 9 to pin 12(in reg is 9-11) @@ -242,6 +263,11 @@ int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode) { int status = 0; + /* + * FIXME: We need to implement the AFE code for LOW IF and for HI IF. + * Currently, only baseband works. + */ + switch (mode) { case AFE_MODE_LOW_IF: /* SetupAFEforLowIF(); */ @@ -270,8 +296,8 @@ int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode) return status; } -/* For power saving in the EVK */ -int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) +int cx231xx_colibri_update_power_control(struct cx231xx *dev, + enum AV_MODE avmode) { u32 colibri_power_status = 0; int status = 0; @@ -279,14 +305,16 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) switch (dev->model) { case CX231XX_BOARD_CNXT_RDE_250: case CX231XX_BOARD_CNXT_RDU_250: - if (avmode == POLARIS_AVMODE_ANALOGT_TV) { - while (colibri_power_status != 0x18) { + while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS | + FLD_PWRDN_ENABLE_PLL)) { status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, - 0x18, 1); - status = cx231xx_read_i2c_data(dev, + FLD_PWRDN_TUNING_BIAS | + FLD_PWRDN_ENABLE_PLL, + 1); + status |= cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, &colibri_power_status, @@ -299,11 +327,11 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1); @@ -312,32 +340,36 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH1, 2, 0x70, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, 0x70, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH3, 2, 0x70, 1); - status = cx231xx_read_i2c_data(dev, + status |= cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, &colibri_power_status, 1); - colibri_power_status |= 0x07; - status = cx231xx_write_i2c_data(dev, + colibri_power_status |= FLD_PWRDN_PD_BANDGAP | + FLD_PWRDN_PD_BIAS | + FLD_PWRDN_PD_TUNECK; + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, colibri_power_status, 1); } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { - - while (colibri_power_status != 0x18) { + while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS | + FLD_PWRDN_ENABLE_PLL)) { status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, - 0x18, 1); - status = cx231xx_read_i2c_data(dev, + FLD_PWRDN_TUNING_BIAS | + FLD_PWRDN_ENABLE_PLL, + 1); + status |= cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, &colibri_power_status, @@ -346,15 +378,15 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) break; } - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1); @@ -365,12 +397,15 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) break; default: if (avmode == POLARIS_AVMODE_ANALOGT_TV) { - while (colibri_power_status != 0x18) { + while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS | + FLD_PWRDN_ENABLE_PLL)) { status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, - 0x18, 1); - status = cx231xx_read_i2c_data(dev, + FLD_PWRDN_TUNING_BIAS | + FLD_PWRDN_ENABLE_PLL, + 1); + status |= cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, &colibri_power_status, @@ -379,15 +414,15 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) break; } - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH1, 2, 0x40, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, 0x40, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1); @@ -396,33 +431,38 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH1, 2, 0x70, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, 0x70, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH3, 2, 0x70, 1); - status = cx231xx_read_i2c_data(dev, + status |= cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, &colibri_power_status, 1); - colibri_power_status |= 0x07; - status = cx231xx_write_i2c_data(dev, + colibri_power_status |= FLD_PWRDN_PD_BANDGAP | + FLD_PWRDN_PD_BIAS | + FLD_PWRDN_PD_TUNECK; + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, colibri_power_status, 1); } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { - while (colibri_power_status != 0x18) { + while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS | + FLD_PWRDN_ENABLE_PLL)) { status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, - 0x18, 1); - status = cx231xx_read_i2c_data(dev, + FLD_PWRDN_TUNING_BIAS | + FLD_PWRDN_ENABLE_PLL, + 1); + status |= cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, &colibri_power_status, @@ -431,15 +471,15 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) break; } - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH3, 2, 0x40, 1); @@ -500,7 +540,7 @@ int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input) /****************************************************************************** * V I D E O / A U D I O D E C O D E R C O N T R O L functions * - ******************************************++**********************************/ + ******************************************************************************/ int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) { int status = 0; @@ -839,7 +879,7 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, DFE_CTRL1, 2, value, 4); - /* Wait 15 ms */ + /* Wait until AGC locks up */ msleep(1); /* Disable the auto-VGA enable AGC */ @@ -940,8 +980,7 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) DFE_CTRL3, 2, 0xCD3F0280, 4); - if (dev->norm & (V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | - V4L2_STD_PAL_M)) { + if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) { cx231xx_info("do_mode_ctrl_overrides NTSC\n"); /* Move the close caption lines out of active video, @@ -967,11 +1006,9 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) FLD_HBLANK_CNT, cx231xx_set_field (FLD_HBLANK_CNT, 0x79)); - } else if (dev->norm & (V4L2_STD_PAL_B | V4L2_STD_PAL_G | - V4L2_STD_PAL_D | V4L2_STD_PAL_I | - V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { - cx231xx_info("do_mode_ctrl_overrides PAL\n"); - status = cx231xx_read_modify_write_i2c_dword(dev, + } else if (dev->norm & V4L2_STD_SECAM) { + cx231xx_info("do_mode_ctrl_overrides SECAM\n"); + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, VERT_TIM_CTRL, FLD_VBLANK_CNT, 0x24); @@ -982,12 +1019,9 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) FLD_HBLANK_CNT, cx231xx_set_field (FLD_HBLANK_CNT, 0x85)); - } else if (dev->norm & (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | - V4L2_STD_SECAM_G | V4L2_STD_SECAM_K | - V4L2_STD_SECAM_K1 | V4L2_STD_SECAM_L | - V4L2_STD_SECAM_LC)) { - cx231xx_info("do_mode_ctrl_overrides SECAM\n"); - status = cx231xx_read_modify_write_i2c_dword(dev, + } else { + cx231xx_info("do_mode_ctrl_overrides PAL\n"); + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, VERT_TIM_CTRL, FLD_VBLANK_CNT, 0x24); @@ -1276,13 +1310,8 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); - } else { - switch (standard) { - case V4L2_STD_NTSC_M: /* 75 IRE Setup */ - case V4L2_STD_NTSC_M_JP:/* Japan, 0 IRE Setup */ - case V4L2_STD_PAL_M: - case V4L2_STD_PAL_N: - case V4L2_STD_PAL_Nc: + } else if (standard != DIF_USE_BASEBAND) { + if (standard & V4L2_STD_MN) { /* lo if big signal */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, @@ -1304,10 +1333,8 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AUD_IO_CTRL, 0, 31, 0x00000003); - break; - - case V4L2_STD_PAL_B: - case V4L2_STD_PAL_G: + } else if ((standard == V4L2_STD_PAL_I) | + (standard & V4L2_STD_SECAM)) { /* C2HH setup */ /* lo if big signal */ status = cx231xx_reg_mask_write(dev, @@ -1321,22 +1348,13 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, /* IF_MODE */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); + AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); /* no inv */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); - break; - - case V4L2_STD_PAL_D: - case V4L2_STD_PAL_I: - case V4L2_STD_SECAM_L: - case V4L2_STD_SECAM_LC: - case V4L2_STD_SECAM_B: - case V4L2_STD_SECAM_D: - case V4L2_STD_SECAM_G: - case V4L2_STD_SECAM_K: - case V4L2_STD_SECAM_K1: + } else { + /* default PAL BG */ /* C2HH setup */ /* lo if big signal */ status = cx231xx_reg_mask_write(dev, @@ -1350,17 +1368,11 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, /* IF_MODE */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); + AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); /* no inv */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); - break; - - case DIF_USE_BASEBAND: - default: - /* do nothing to config C2HH for baseband */ - break; } } @@ -1406,54 +1418,6 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_MISC_CTRL, 2, dif_misc_ctrl_value, 4); - - } else if (standard & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) { - - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_PLL_CTRL, 0, 31, 0x6503bc0c); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_PLL_CTRL1, 0, 31, 0xbd038c85); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_PLL_CTRL2, 0, 31, 0x1db4640a); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_PLL_CTRL3, 0, 31, 0x00008800); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_AGC_IF_REF, 0, 31, 0x444C1380); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_AGC_IF_INT_CURRENT, 0, 31, - 0x26001700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_AGC_RF_CURRENT, 0, 31, - 0x00002660); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_VIDEO_AGC_CTRL, 0, 31, - 0x72500800); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_VID_AUD_OVERRIDE, 0, 31, - 0x27000100); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_COMP_FLT_CTRL, 0, 31, - 0x00A653A8); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_SRC_PHASE_INC, 0, 31, - 0x1befbf06); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_SRC_GAIN_CONTROL, 0, 31, - 0x000035e8); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_RPT_VARIANCE, 0, 31, 0x00000000); - /* Save the Spec Inversion value */ - dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; - dif_misc_ctrl_value |= 0x3a013F11; - } else if (standard & V4L2_STD_PAL_D) { status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); @@ -1499,9 +1463,7 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) /* Save the Spec Inversion value */ dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value |= 0x3a023F11; - } else if (standard & V4L2_STD_PAL_I) { - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, @@ -1546,7 +1508,6 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) /* Save the Spec Inversion value */ dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value |= 0x3a033F11; - } else if (standard & V4L2_STD_PAL_M) { /* improved Low Frequency Phase Noise */ status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, @@ -1584,13 +1545,10 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SOFT_RST_CTRL_REVB, 2, 0x00000000, 4); - /* Save the Spec Inversion value */ dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value |= 0x3A0A3F10; - } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { - /* improved Low Frequency Phase Noise */ status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL, 2, 0xFF01FF0C, 4); @@ -1626,14 +1584,12 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SOFT_RST_CTRL_REVB, 2, 0x00000000, 4); - /* Save the Spec Inversion value */ dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value = 0x3A093F10; - } else if (standard & - (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | - V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) { + (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | + V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) { status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); @@ -1680,9 +1636,7 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) /* Save the Spec Inversion value */ dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value |= 0x3a023F11; - } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) { - /* Is it SECAM_L1? */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); @@ -1730,7 +1684,7 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value |= 0x3a023F11; - } else { + } else if (standard & V4L2_STD_NTSC_M) { /* V4L2_STD_NTSC_M (75 IRE Setup) Or V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */ @@ -1783,7 +1737,52 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) /* Save the Spec Inversion value */ dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value |= 0x3a003F10; - + } else { + /* default PAL BG */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL, 0, 31, 0x6503bc0c); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL1, 0, 31, 0xbd038c85); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL2, 0, 31, 0x1db4640a); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL3, 0, 31, 0x00008800); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_IF_REF, 0, 31, 0x444C1380); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_IF_INT_CURRENT, 0, 31, + 0x26001700); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_RF_CURRENT, 0, 31, + 0x00002660); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_VIDEO_AGC_CTRL, 0, 31, + 0x72500800); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_VID_AUD_OVERRIDE, 0, 31, + 0x27000100); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_COMP_FLT_CTRL, 0, 31, + 0x00A653A8); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_SRC_PHASE_INC, 0, 31, + 0x1befbf06); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_SRC_GAIN_CONTROL, 0, 31, + 0x000035e8); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_RPT_VARIANCE, 0, 31, 0x00000000); + /* Save the Spec Inversion value */ + dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; + dif_misc_ctrl_value |= 0x3a013F11; } /* The AGC values should be the same for all standards, @@ -1826,7 +1825,8 @@ int cx231xx_tuner_post_channel_change(struct cx231xx *dev) int status = 0; u32 dwval; - /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for SECAM */ + /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for + * SECAM L/B/D standards */ status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_IF_REF, 2, &dwval, 4); dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); @@ -1864,7 +1864,8 @@ int cx231xx_flatiron_initialize(struct cx231xx *dev) return status; } -int cx231xx_flatiron_update_power_control(struct cx231xx *dev, AV_MODE avmode) +int cx231xx_flatiron_update_power_control(struct cx231xx *dev, + enum AV_MODE avmode) { int status = 0; u32 value = 0; @@ -1908,7 +1909,7 @@ int cx231xx_flatiron_set_audio_input(struct cx231xx *dev, u8 audio_input) /****************************************************************************** * P O W E R C O N T R O L functions * ******************************************************************************/ -int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) +int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode) { u8 value[4] = { 0, 0, 0, 0 }; u32 tmp = 0; @@ -2211,7 +2212,7 @@ int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type) if (dev->udev->speed == USB_SPEED_HIGH) { switch (media_type) { - case 81: /* audio */ + case 81: /* audio */ cx231xx_info("%s: Audio enter HANC\n", __func__); status = cx231xx_mode_register(dev, TS_MODE_REG, 0x9300); @@ -2390,7 +2391,7 @@ int cx231xx_set_gpio_direction(struct cx231xx *dev, } /* -* SetGpioPinLogicValue +* cx231xx_set_gpio_value * Sets the value of the GPIO pin to Logic high or low. The Pin under * reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!! * diff --git a/drivers/media/video/cx231xx/cx231xx-cards.c b/drivers/media/video/cx231xx/cx231xx-cards.c index f18d0c11de7d..c12bb62021a9 100644 --- a/drivers/media/video/cx231xx/cx231xx-cards.c +++ b/drivers/media/video/cx231xx/cx231xx-cards.c @@ -61,127 +61,108 @@ static struct cx231xx_reg_seq RDE250_XCV_TUNER[] = { * Board definitions */ struct cx231xx_board cx231xx_boards[] = { - [CX231XX_BOARD_UNKNOWN] = { - .name = "Unknown CX231xx video grabber", - .tuner_type = TUNER_ABSENT, - .input = {{ - .type = CX231XX_VMUX_TELEVISION, - .vmux = CX231XX_VIN_3_1, - .amux = CX231XX_AMUX_VIDEO, - .gpio = 0, - }, { - .type = - CX231XX_VMUX_COMPOSITE1, - .vmux = CX231XX_VIN_2_1, - .amux = CX231XX_AMUX_LINE_IN, - .gpio = 0, - }, { - .type = - CX231XX_VMUX_SVIDEO, - .vmux = - CX231XX_VIN_1_1 | - (CX231XX_VIN_1_2 << 8) | - CX25840_SVIDEO_ON, - .amux = - CX231XX_AMUX_LINE_IN, - .gpio = 0, - } }, - }, - + .name = "Unknown CX231xx video grabber", + .tuner_type = TUNER_ABSENT, + .input = {{ + .type = CX231XX_VMUX_TELEVISION, + .vmux = CX231XX_VIN_3_1, + .amux = CX231XX_AMUX_VIDEO, + .gpio = 0, + }, { + .type = CX231XX_VMUX_COMPOSITE1, + .vmux = CX231XX_VIN_2_1, + .amux = CX231XX_AMUX_LINE_IN, + .gpio = 0, + }, { + .type = CX231XX_VMUX_SVIDEO, + .vmux = CX231XX_VIN_1_1 | + (CX231XX_VIN_1_2 << 8) | + CX25840_SVIDEO_ON, + .amux = CX231XX_AMUX_LINE_IN, + .gpio = 0, + } + }, + }, [CX231XX_BOARD_CNXT_RDE_250] = { - .name = "Conexant Hybrid TV - RDE250", - .valid = CX231XX_BOARD_VALIDATED, - .tuner_type = TUNER_XC5000, - .tuner_addr = 0x61, - .tuner_gpio = RDE250_XCV_TUNER, - .tuner_sif_gpio = 0x05, - .tuner_scl_gpio = 0x1a, - .tuner_sda_gpio = 0x1b, - .decoder = CX231XX_AVDECODER, - .demod_xfer_mode = 0, - .ctl_pin_status_mask = 0xFFFFFFC4, - .agc_analog_digital_select_gpio = 0x0c, - .gpio_pin_status_mask = 0x4001000, - .tuner_i2c_master = 1, - .demod_i2c_master = 2, - .has_dvb = 1, - .demod_addr = 0x02, - .norm = V4L2_STD_PAL, - - .input = {{ - .type = - CX231XX_VMUX_TELEVISION, - .vmux = CX231XX_VIN_3_1, - .amux = CX231XX_AMUX_VIDEO, - .gpio = 0, - }, { - .type = - CX231XX_VMUX_COMPOSITE1, - .vmux = CX231XX_VIN_2_1, - .amux = - CX231XX_AMUX_LINE_IN, - .gpio = 0, - }, { - .type = - CX231XX_VMUX_SVIDEO, - .vmux = - CX231XX_VIN_1_1 | - (CX231XX_VIN_1_2 << - 8) | - CX25840_SVIDEO_ON, - .amux = - CX231XX_AMUX_LINE_IN, - .gpio = 0, - } }, - }, + .name = "Conexant Hybrid TV - RDE250", + .tuner_type = TUNER_XC5000, + .tuner_addr = 0x61, + .tuner_gpio = RDE250_XCV_TUNER, + .tuner_sif_gpio = 0x05, + .tuner_scl_gpio = 0x1a, + .tuner_sda_gpio = 0x1b, + .decoder = CX231XX_AVDECODER, + .demod_xfer_mode = 0, + .ctl_pin_status_mask = 0xFFFFFFC4, + .agc_analog_digital_select_gpio = 0x0c, + .gpio_pin_status_mask = 0x4001000, + .tuner_i2c_master = 1, + .demod_i2c_master = 2, + .has_dvb = 1, + .demod_addr = 0x02, + .norm = V4L2_STD_PAL, + + .input = {{ + .type = CX231XX_VMUX_TELEVISION, + .vmux = CX231XX_VIN_3_1, + .amux = CX231XX_AMUX_VIDEO, + .gpio = 0, + }, { + .type = CX231XX_VMUX_COMPOSITE1, + .vmux = CX231XX_VIN_2_1, + .amux = CX231XX_AMUX_LINE_IN, + .gpio = 0, + }, { + .type = CX231XX_VMUX_SVIDEO, + .vmux = CX231XX_VIN_1_1 | + (CX231XX_VIN_1_2 << 8) | + CX25840_SVIDEO_ON, + .amux = CX231XX_AMUX_LINE_IN, + .gpio = 0, + } + }, + }, [CX231XX_BOARD_CNXT_RDU_250] = { - .name = "Conexant Hybrid TV - RDU250", - .valid = CX231XX_BOARD_VALIDATED, - .tuner_type = TUNER_XC5000, - .tuner_addr = 0x61, - .tuner_gpio = RDE250_XCV_TUNER, - .tuner_sif_gpio = 0x05, - .tuner_scl_gpio = 0x1a, - .tuner_sda_gpio = 0x1b, - .decoder = CX231XX_AVDECODER, - .demod_xfer_mode = 0, - .ctl_pin_status_mask = 0xFFFFFFC4, - .agc_analog_digital_select_gpio = 0x0c, - .gpio_pin_status_mask = 0x4001000, - .tuner_i2c_master = 1, - .demod_i2c_master = 2, - .has_dvb = 1, - .demod_addr = 0x32, - .norm = V4L2_STD_NTSC, - - .input = {{ - .type = - CX231XX_VMUX_TELEVISION, - .vmux = CX231XX_VIN_3_1, - .amux = CX231XX_AMUX_VIDEO, - .gpio = 0, - }, { - .type = - CX231XX_VMUX_COMPOSITE1, - .vmux = CX231XX_VIN_2_1, - .amux = - CX231XX_AMUX_LINE_IN, - .gpio = 0, - }, { - .type = - CX231XX_VMUX_SVIDEO, - .vmux = - CX231XX_VIN_1_1 | - (CX231XX_VIN_1_2 << - 8) | - CX25840_SVIDEO_ON, - .amux = - CX231XX_AMUX_LINE_IN, - .gpio = 0, - } }, - }, + .name = "Conexant Hybrid TV - RDU250", + .tuner_type = TUNER_XC5000, + .tuner_addr = 0x61, + .tuner_gpio = RDE250_XCV_TUNER, + .tuner_sif_gpio = 0x05, + .tuner_scl_gpio = 0x1a, + .tuner_sda_gpio = 0x1b, + .decoder = CX231XX_AVDECODER, + .demod_xfer_mode = 0, + .ctl_pin_status_mask = 0xFFFFFFC4, + .agc_analog_digital_select_gpio = 0x0c, + .gpio_pin_status_mask = 0x4001000, + .tuner_i2c_master = 1, + .demod_i2c_master = 2, + .has_dvb = 1, + .demod_addr = 0x32, + .norm = V4L2_STD_NTSC, + + .input = {{ + .type = CX231XX_VMUX_TELEVISION, + .vmux = CX231XX_VIN_3_1, + .amux = CX231XX_AMUX_VIDEO, + .gpio = 0, + }, { + .type = CX231XX_VMUX_COMPOSITE1, + .vmux = CX231XX_VIN_2_1, + .amux = CX231XX_AMUX_LINE_IN, + .gpio = 0, + }, { + .type = CX231XX_VMUX_SVIDEO, + .vmux = CX231XX_VIN_1_1 | + (CX231XX_VIN_1_2 << 8) | + CX25840_SVIDEO_ON, + .amux = CX231XX_AMUX_LINE_IN, + .gpio = 0, + } + }, + }, }; const unsigned int cx231xx_bcount = ARRAY_SIZE(cx231xx_boards); @@ -243,25 +224,11 @@ void cx231xx_pre_card_setup(struct cx231xx *dev) cx231xx_info("Identified as %s (card=%d)\n", dev->board.name, dev->model); - /* Do card specific if any */ - switch (dev->model) { - case CX231XX_BOARD_CNXT_RDE_250: - /* do card specific GPIO settings if required */ - cx231xx_info("Precard: Board is Conexnat RDE 250\n"); - /* set the direction for GPIO pins */ - cx231xx_set_gpio_direction(dev, dev->board.tuner_gpio->bit, 1); - cx231xx_set_gpio_value(dev, dev->board.tuner_gpio->bit, 1); - cx231xx_set_gpio_direction(dev, dev->board.tuner_sif_gpio, 1); - break; - case CX231XX_BOARD_CNXT_RDU_250: - /* do card specific GPIO settings if required */ - cx231xx_info("Precard: Board is Conexnat RDU 250\n"); - /* set the direction for GPIO pins */ - cx231xx_set_gpio_direction(dev, dev->board.tuner_gpio->bit, 1); - cx231xx_set_gpio_value(dev, dev->board.tuner_gpio->bit, 1); - cx231xx_set_gpio_direction(dev, dev->board.tuner_sif_gpio, 1); - break; - } + cx231xx_info("Precard: Board is %s\n", dev->board.name); + /* set the direction for GPIO pins */ + cx231xx_set_gpio_direction(dev, dev->board.tuner_gpio->bit, 1); + cx231xx_set_gpio_value(dev, dev->board.tuner_gpio->bit, 1); + cx231xx_set_gpio_direction(dev, dev->board.tuner_sif_gpio, 1); /* request some modules if any required */ @@ -362,15 +329,6 @@ void cx231xx_card_setup(struct cx231xx *dev) break; } - if (dev->board.valid == CX231XX_BOARD_NOT_VALIDATED) { - cx231xx_errdev("\n\n"); - cx231xx_errdev("The support for this board weren't " - "valid yet.\n"); - cx231xx_errdev("Please send a report of having this working\n"); - cx231xx_errdev("not to V4L mailing list (and/or to other " - "addresses)\n\n"); - } - /* request some modules */ if (dev->board.decoder == CX231XX_AVDECODER) { cx231xx_info(": Requesting cx25840 module\n"); diff --git a/drivers/media/video/cx231xx/cx231xx-conf-reg.h b/drivers/media/video/cx231xx/cx231xx-conf-reg.h index a65f99ba109b..a6f398a175c5 100644 --- a/drivers/media/video/cx231xx/cx231xx-conf-reg.h +++ b/drivers/media/video/cx231xx/cx231xx-conf-reg.h @@ -42,30 +42,30 @@ #define PWR_CTL_EN 0x74 /* Polaris Endpoints capture mask for register EP_MODE_SET */ -#define ENABLE_EP1 0x01 /* Bit[0]=1 */ -#define ENABLE_EP2 0x02 /* Bit[1]=1 */ -#define ENABLE_EP3 0x04 /* Bit[2]=1 */ -#define ENABLE_EP4 0x08 /* Bit[3]=1 */ -#define ENABLE_EP5 0x10 /* Bit[4]=1 */ -#define ENABLE_EP6 0x20 /* Bit[5]=1 */ +#define ENABLE_EP1 0x01 /* Bit[0]=1 */ +#define ENABLE_EP2 0x02 /* Bit[1]=1 */ +#define ENABLE_EP3 0x04 /* Bit[2]=1 */ +#define ENABLE_EP4 0x08 /* Bit[3]=1 */ +#define ENABLE_EP5 0x10 /* Bit[4]=1 */ +#define ENABLE_EP6 0x20 /* Bit[5]=1 */ /* Bit definition for register PWR_CTL_EN */ #define PWR_MODE_MASK 0x17f -#define PWR_AV_EN 0x08 /* bit3 */ -#define PWR_ISO_EN 0x40 /* bit6 */ -#define PWR_AV_MODE 0x30 /* bit4,5 */ -#define PWR_TUNER_EN 0x04 /* bit2 */ -#define PWR_DEMOD_EN 0x02 /* bit1 */ -#define I2C_DEMOD_EN 0x01 /* bit0 */ -#define PWR_RESETOUT_EN 0x100 /* bit8 */ - -typedef enum { - POLARIS_AVMODE_DEFAULT = 0, - POLARIS_AVMODE_DIGITAL = 0x10, - POLARIS_AVMODE_ANALOGT_TV = 0x20, - POLARIS_AVMODE_ENXTERNAL_AV = 0x30, - -} AV_MODE; +#define PWR_AV_EN 0x08 /* bit3 */ +#define PWR_ISO_EN 0x40 /* bit6 */ +#define PWR_AV_MODE 0x30 /* bit4,5 */ +#define PWR_TUNER_EN 0x04 /* bit2 */ +#define PWR_DEMOD_EN 0x02 /* bit1 */ +#define I2C_DEMOD_EN 0x01 /* bit0 */ +#define PWR_RESETOUT_EN 0x100 /* bit8 */ + +enum AV_MODE{ + POLARIS_AVMODE_DEFAULT = 0, + POLARIS_AVMODE_DIGITAL = 0x10, + POLARIS_AVMODE_ANALOGT_TV = 0x20, + POLARIS_AVMODE_ENXTERNAL_AV = 0x30, + +}; /* Colibri Registers */ @@ -91,6 +91,13 @@ typedef enum { #define ADC_COM_BIAS3 0x0e #define TESTBUS_CTRL 0x12 +#define FLD_PWRDN_TUNING_BIAS 0x10 +#define FLD_PWRDN_ENABLE_PLL 0x08 +#define FLD_PWRDN_PD_BANDGAP 0x04 +#define FLD_PWRDN_PD_BIAS 0x02 +#define FLD_PWRDN_PD_TUNECK 0x01 + + #define ADC_STATUS_CH1 0x20 #define ADC_STATUS_CH2 0x40 #define ADC_STATUS_CH3 0x60 @@ -126,7 +133,7 @@ typedef enum { #define ADC_INPUT_CH1 0x28 #define ADC_INPUT_CH2 0x48 #define ADC_INPUT_CH3 0x68 -#define INPUT_SEL_MASK 0x30 /* [5:4] in_sel */ +#define INPUT_SEL_MASK 0x30 /* [5:4] in_sel */ #define ADC_NTF_PRECLMP_EN_CH1 0x29 #define ADC_NTF_PRECLMP_EN_CH2 0x49 @@ -150,128 +157,128 @@ typedef enum { #define DIRECT_IF_REVB_BASE 0x00300 /*****************************************************************************/ -#define DIF_PLL_FREQ_WORD (DIRECT_IF_REVB_BASE + 0x00000000) /* Reg Size 32 */ +#define DIF_PLL_FREQ_WORD (DIRECT_IF_REVB_BASE + 0x00000000) /*****************************************************************************/ #define FLD_DIF_PLL_LOCK 0x80000000 /* Reserved [30:29] */ #define FLD_DIF_PLL_FREE_RUN 0x10000000 -#define FLD_DIF_PLL_FREQ 0x0FFFFFFF +#define FLD_DIF_PLL_FREQ 0x0fffffff /*****************************************************************************/ -#define DIF_PLL_CTRL (DIRECT_IF_REVB_BASE + 0x00000004) /* Reg Size 32 */ +#define DIF_PLL_CTRL (DIRECT_IF_REVB_BASE + 0x00000004) /*****************************************************************************/ -#define FLD_DIF_KD_PD 0xFF000000 +#define FLD_DIF_KD_PD 0xff000000 /* Reserved [23:20] */ -#define FLD_DIF_KDS_PD 0x000F0000 -#define FLD_DIF_KI_PD 0x0000FF00 +#define FLD_DIF_KDS_PD 0x000f0000 +#define FLD_DIF_KI_PD 0x0000ff00 /* Reserved [7:4] */ -#define FLD_DIF_KIS_PD 0x0000000F +#define FLD_DIF_KIS_PD 0x0000000f /*****************************************************************************/ -#define DIF_PLL_CTRL1 (DIRECT_IF_REVB_BASE + 0x00000008) /* Reg Size 32 */ +#define DIF_PLL_CTRL1 (DIRECT_IF_REVB_BASE + 0x00000008) /*****************************************************************************/ -#define FLD_DIF_KD_FD 0xFF000000 +#define FLD_DIF_KD_FD 0xff000000 /* Reserved [23:20] */ -#define FLD_DIF_KDS_FD 0x000F0000 -#define FLD_DIF_KI_FD 0x0000FF00 -#define FLD_DIF_SIG_PROP_SZ 0x000000F0 -#define FLD_DIF_KIS_FD 0x0000000F +#define FLD_DIF_KDS_FD 0x000f0000 +#define FLD_DIF_KI_FD 0x0000ff00 +#define FLD_DIF_SIG_PROP_SZ 0x000000f0 +#define FLD_DIF_KIS_FD 0x0000000f /*****************************************************************************/ -#define DIF_PLL_CTRL2 (DIRECT_IF_REVB_BASE + 0x0000000C) /* Reg Size 32 */ +#define DIF_PLL_CTRL2 (DIRECT_IF_REVB_BASE + 0x0000000c) /*****************************************************************************/ -#define FLD_DIF_PLL_AGC_REF 0xFFF00000 -#define FLD_DIF_PLL_AGC_KI 0x000F0000 +#define FLD_DIF_PLL_AGC_REF 0xfff00000 +#define FLD_DIF_PLL_AGC_KI 0x000f0000 /* Reserved [15] */ #define FLD_DIF_FREQ_LIMIT 0x00007000 -#define FLD_DIF_K_FD 0x00000F00 -#define FLD_DIF_DOWNSMPL_FD 0x000000FF +#define FLD_DIF_K_FD 0x00000f00 +#define FLD_DIF_DOWNSMPL_FD 0x000000ff /*****************************************************************************/ -#define DIF_PLL_CTRL3 (DIRECT_IF_REVB_BASE + 0x00000010) /* Reg Size 32 */ +#define DIF_PLL_CTRL3 (DIRECT_IF_REVB_BASE + 0x00000010) /*****************************************************************************/ /* Reserved [31:16] */ #define FLD_DIF_PLL_AGC_EN 0x00008000 /* Reserved [14:12] */ -#define FLD_DIF_PLL_MAN_GAIN 0x00000FFF +#define FLD_DIF_PLL_MAN_GAIN 0x00000fff /*****************************************************************************/ -#define DIF_AGC_IF_REF (DIRECT_IF_REVB_BASE + 0x00000014) /* Reg Size 32 */ +#define DIF_AGC_IF_REF (DIRECT_IF_REVB_BASE + 0x00000014) /*****************************************************************************/ -#define FLD_DIF_K_AGC_RF 0xF0000000 -#define FLD_DIF_K_AGC_IF 0x0F000000 -#define FLD_DIF_K_AGC_INT 0x00F00000 +#define FLD_DIF_K_AGC_RF 0xf0000000 +#define FLD_DIF_K_AGC_IF 0x0f000000 +#define FLD_DIF_K_AGC_INT 0x00f00000 /* Reserved [19:12] */ -#define FLD_DIF_IF_REF 0x00000FFF +#define FLD_DIF_IF_REF 0x00000fff /*****************************************************************************/ -#define DIF_AGC_CTRL_IF (DIRECT_IF_REVB_BASE + 0x00000018) /* Reg Size 32 */ +#define DIF_AGC_CTRL_IF (DIRECT_IF_REVB_BASE + 0x00000018) /*****************************************************************************/ -#define FLD_DIF_IF_MAX 0xFF000000 -#define FLD_DIF_IF_MIN 0x00FF0000 -#define FLD_DIF_IF_AGC 0x0000FFFF +#define FLD_DIF_IF_MAX 0xff000000 +#define FLD_DIF_IF_MIN 0x00ff0000 +#define FLD_DIF_IF_AGC 0x0000ffff /*****************************************************************************/ -#define DIF_AGC_CTRL_INT (DIRECT_IF_REVB_BASE + 0x0000001C) /* Reg Size 32 */ +#define DIF_AGC_CTRL_INT (DIRECT_IF_REVB_BASE + 0x0000001c) /*****************************************************************************/ -#define FLD_DIF_INT_MAX 0xFF000000 -#define FLD_DIF_INT_MIN 0x00FF0000 -#define FLD_DIF_INT_AGC 0x0000FFFF +#define FLD_DIF_INT_MAX 0xff000000 +#define FLD_DIF_INT_MIN 0x00ff0000 +#define FLD_DIF_INT_AGC 0x0000ffff /*****************************************************************************/ -#define DIF_AGC_CTRL_RF (DIRECT_IF_REVB_BASE + 0x00000020) /* Reg Size 32 */ +#define DIF_AGC_CTRL_RF (DIRECT_IF_REVB_BASE + 0x00000020) /*****************************************************************************/ -#define FLD_DIF_RF_MAX 0xFF000000 -#define FLD_DIF_RF_MIN 0x00FF0000 -#define FLD_DIF_RF_AGC 0x0000FFFF +#define FLD_DIF_RF_MAX 0xff000000 +#define FLD_DIF_RF_MIN 0x00ff0000 +#define FLD_DIF_RF_AGC 0x0000ffff /*****************************************************************************/ -#define DIF_AGC_IF_INT_CURRENT (DIRECT_IF_REVB_BASE + 0x00000024) /* Reg Size 32 */ +#define DIF_AGC_IF_INT_CURRENT (DIRECT_IF_REVB_BASE + 0x00000024) /*****************************************************************************/ -#define FLD_DIF_IF_AGC_IN 0xFFFF0000 -#define FLD_DIF_INT_AGC_IN 0x0000FFFF +#define FLD_DIF_IF_AGC_IN 0xffff0000 +#define FLD_DIF_INT_AGC_IN 0x0000ffff /*****************************************************************************/ -#define DIF_AGC_RF_CURRENT (DIRECT_IF_REVB_BASE + 0x00000028) /* Reg Size 32 */ +#define DIF_AGC_RF_CURRENT (DIRECT_IF_REVB_BASE + 0x00000028) /*****************************************************************************/ /* Reserved [31:16] */ -#define FLD_DIF_RF_AGC_IN 0x0000FFFF +#define FLD_DIF_RF_AGC_IN 0x0000ffff /*****************************************************************************/ -#define DIF_VIDEO_AGC_CTRL (DIRECT_IF_REVB_BASE + 0x0000002C) /* Reg Size 32 */ +#define DIF_VIDEO_AGC_CTRL (DIRECT_IF_REVB_BASE + 0x0000002c) /*****************************************************************************/ -#define FLD_DIF_AFD 0xC0000000 +#define FLD_DIF_AFD 0xc0000000 #define FLD_DIF_K_VID_AGC 0x30000000 -#define FLD_DIF_LINE_LENGTH 0x0FFF0000 -#define FLD_DIF_AGC_GAIN 0x0000FFFF +#define FLD_DIF_LINE_LENGTH 0x0fff0000 +#define FLD_DIF_AGC_GAIN 0x0000ffff /*****************************************************************************/ -#define DIF_VID_AUD_OVERRIDE (DIRECT_IF_REVB_BASE + 0x00000030) /* Reg Size 32 */ +#define DIF_VID_AUD_OVERRIDE (DIRECT_IF_REVB_BASE + 0x00000030) /*****************************************************************************/ #define FLD_DIF_AUDIO_AGC_OVERRIDE 0x80000000 /* Reserved [30:30] */ -#define FLD_DIF_AUDIO_MAN_GAIN 0x3F000000 +#define FLD_DIF_AUDIO_MAN_GAIN 0x3f000000 /* Reserved [23:17] */ #define FLD_DIF_VID_AGC_OVERRIDE 0x00010000 -#define FLD_DIF_VID_MAN_GAIN 0x0000FFFF +#define FLD_DIF_VID_MAN_GAIN 0x0000ffff /*****************************************************************************/ -#define DIF_AV_SEP_CTRL (DIRECT_IF_REVB_BASE + 0x00000034) /* Reg Size 32 */ +#define DIF_AV_SEP_CTRL (DIRECT_IF_REVB_BASE + 0x00000034) /*****************************************************************************/ -#define FLD_DIF_LPF_FREQ 0xC0000000 -#define FLD_DIF_AV_PHASE_INC 0x3F000000 -#define FLD_DIF_AUDIO_FREQ 0x00FFFFFF +#define FLD_DIF_LPF_FREQ 0xc0000000 +#define FLD_DIF_AV_PHASE_INC 0x3f000000 +#define FLD_DIF_AUDIO_FREQ 0x00ffffff /*****************************************************************************/ -#define DIF_COMP_FLT_CTRL (DIRECT_IF_REVB_BASE + 0x00000038) /* Reg Size 32 */ +#define DIF_COMP_FLT_CTRL (DIRECT_IF_REVB_BASE + 0x00000038) /*****************************************************************************/ /* Reserved [31:24] */ -#define FLD_DIF_IIR23_R2 0x00FF0000 -#define FLD_DIF_IIR23_R1 0x0000FF00 -#define FLD_DIF_IIR1_R1 0x000000FF +#define FLD_DIF_IIR23_R2 0x00ff0000 +#define FLD_DIF_IIR23_R1 0x0000ff00 +#define FLD_DIF_IIR1_R1 0x000000ff /*****************************************************************************/ -#define DIF_MISC_CTRL (DIRECT_IF_REVB_BASE + 0x0000003C) /* Reg Size 32 */ +#define DIF_MISC_CTRL (DIRECT_IF_REVB_BASE + 0x0000003c) /*****************************************************************************/ #define FLD_DIF_DIF_BYPASS 0x80000000 #define FLD_DIF_FM_NYQ_GAIN 0x40000000 @@ -289,184 +296,184 @@ typedef enum { /* Reserved [18] */ #define FLD_DIF_IF_FREQ 0x00030000 /* Reserved [15:14] */ -#define FLD_DIF_TIP_OFFSET 0x00003F00 +#define FLD_DIF_TIP_OFFSET 0x00003f00 /* Reserved [7:5] */ #define FLD_DIF_DITHER_ENA 0x00000010 /* Reserved [3:1] */ #define FLD_DIF_RF_IF_LOCK 0x00000001 /*****************************************************************************/ -#define DIF_SRC_PHASE_INC (DIRECT_IF_REVB_BASE + 0x00000040) /* Reg Size 32 */ +#define DIF_SRC_PHASE_INC (DIRECT_IF_REVB_BASE + 0x00000040) /*****************************************************************************/ /* Reserved [31:29] */ -#define FLD_DIF_PHASE_INC 0x1FFFFFFF +#define FLD_DIF_PHASE_INC 0x1fffffff /*****************************************************************************/ -#define DIF_SRC_GAIN_CONTROL (DIRECT_IF_REVB_BASE + 0x00000044) /* Reg Size 32 */ +#define DIF_SRC_GAIN_CONTROL (DIRECT_IF_REVB_BASE + 0x00000044) /*****************************************************************************/ /* Reserved [31:16] */ -#define FLD_DIF_SRC_KI 0x0000FF00 -#define FLD_DIF_SRC_KD 0x000000FF +#define FLD_DIF_SRC_KI 0x0000ff00 +#define FLD_DIF_SRC_KD 0x000000ff /*****************************************************************************/ -#define DIF_BPF_COEFF01 (DIRECT_IF_REVB_BASE + 0x00000048) /* Reg Size 32 */ +#define DIF_BPF_COEFF01 (DIRECT_IF_REVB_BASE + 0x00000048) /*****************************************************************************/ /* Reserved [31:19] */ #define FLD_DIF_BPF_COEFF_0 0x00070000 /* Reserved [15:4] */ -#define FLD_DIF_BPF_COEFF_1 0x0000000F +#define FLD_DIF_BPF_COEFF_1 0x0000000f /*****************************************************************************/ -#define DIF_BPF_COEFF23 (DIRECT_IF_REVB_BASE + 0x0000004c) /* Reg Size 32 */ +#define DIF_BPF_COEFF23 (DIRECT_IF_REVB_BASE + 0x0000004c) /*****************************************************************************/ /* Reserved [31:22] */ -#define FLD_DIF_BPF_COEFF_2 0x003F0000 +#define FLD_DIF_BPF_COEFF_2 0x003f0000 /* Reserved [15:7] */ -#define FLD_DIF_BPF_COEFF_3 0x0000007F +#define FLD_DIF_BPF_COEFF_3 0x0000007f /*****************************************************************************/ -#define DIF_BPF_COEFF45 (DIRECT_IF_REVB_BASE + 0x00000050) /* Reg Size 32 */ +#define DIF_BPF_COEFF45 (DIRECT_IF_REVB_BASE + 0x00000050) /*****************************************************************************/ /* Reserved [31:24] */ -#define FLD_DIF_BPF_COEFF_4 0x00FF0000 +#define FLD_DIF_BPF_COEFF_4 0x00ff0000 /* Reserved [15:8] */ -#define FLD_DIF_BPF_COEFF_5 0x000000FF +#define FLD_DIF_BPF_COEFF_5 0x000000ff /*****************************************************************************/ -#define DIF_BPF_COEFF67 (DIRECT_IF_REVB_BASE + 0x00000054) /* Reg Size 32 */ +#define DIF_BPF_COEFF67 (DIRECT_IF_REVB_BASE + 0x00000054) /*****************************************************************************/ /* Reserved [31:25] */ -#define FLD_DIF_BPF_COEFF_6 0x01FF0000 +#define FLD_DIF_BPF_COEFF_6 0x01ff0000 /* Reserved [15:9] */ -#define FLD_DIF_BPF_COEFF_7 0x000001FF +#define FLD_DIF_BPF_COEFF_7 0x000001ff /*****************************************************************************/ -#define DIF_BPF_COEFF89 (DIRECT_IF_REVB_BASE + 0x00000058) /* Reg Size 32 */ +#define DIF_BPF_COEFF89 (DIRECT_IF_REVB_BASE + 0x00000058) /*****************************************************************************/ /* Reserved [31:26] */ -#define FLD_DIF_BPF_COEFF_8 0x03FF0000 +#define FLD_DIF_BPF_COEFF_8 0x03ff0000 /* Reserved [15:10] */ -#define FLD_DIF_BPF_COEFF_9 0x000003FF +#define FLD_DIF_BPF_COEFF_9 0x000003ff /*****************************************************************************/ -#define DIF_BPF_COEFF1011 (DIRECT_IF_REVB_BASE + 0x0000005C) /* Reg Size 32 */ +#define DIF_BPF_COEFF1011 (DIRECT_IF_REVB_BASE + 0x0000005c) /*****************************************************************************/ /* Reserved [31:27] */ -#define FLD_DIF_BPF_COEFF_10 0x07FF0000 +#define FLD_DIF_BPF_COEFF_10 0x07ff0000 /* Reserved [15:11] */ -#define FLD_DIF_BPF_COEFF_11 0x000007FF +#define FLD_DIF_BPF_COEFF_11 0x000007ff /*****************************************************************************/ -#define DIF_BPF_COEFF1213 (DIRECT_IF_REVB_BASE + 0x00000060) /* Reg Size 32 */ +#define DIF_BPF_COEFF1213 (DIRECT_IF_REVB_BASE + 0x00000060) /*****************************************************************************/ /* Reserved [31:27] */ -#define FLD_DIF_BPF_COEFF_12 0x07FF0000 +#define FLD_DIF_BPF_COEFF_12 0x07ff0000 /* Reserved [15:12] */ -#define FLD_DIF_BPF_COEFF_13 0x00000FFF +#define FLD_DIF_BPF_COEFF_13 0x00000fff /*****************************************************************************/ -#define DIF_BPF_COEFF1415 (DIRECT_IF_REVB_BASE + 0x00000064) /* Reg Size 32 */ +#define DIF_BPF_COEFF1415 (DIRECT_IF_REVB_BASE + 0x00000064) /*****************************************************************************/ /* Reserved [31:28] */ -#define FLD_DIF_BPF_COEFF_14 0x0FFF0000 +#define FLD_DIF_BPF_COEFF_14 0x0fff0000 /* Reserved [15:12] */ -#define FLD_DIF_BPF_COEFF_15 0x00000FFF +#define FLD_DIF_BPF_COEFF_15 0x00000fff /*****************************************************************************/ -#define DIF_BPF_COEFF1617 (DIRECT_IF_REVB_BASE + 0x00000068) /* Reg Size 32 */ +#define DIF_BPF_COEFF1617 (DIRECT_IF_REVB_BASE + 0x00000068) /*****************************************************************************/ /* Reserved [31:29] */ -#define FLD_DIF_BPF_COEFF_16 0x1FFF0000 +#define FLD_DIF_BPF_COEFF_16 0x1fff0000 /* Reserved [15:13] */ -#define FLD_DIF_BPF_COEFF_17 0x00001FFF +#define FLD_DIF_BPF_COEFF_17 0x00001fff /*****************************************************************************/ -#define DIF_BPF_COEFF1819 (DIRECT_IF_REVB_BASE + 0x0000006C) /* Reg Size 32 */ +#define DIF_BPF_COEFF1819 (DIRECT_IF_REVB_BASE + 0x0000006c) /*****************************************************************************/ /* Reserved [31:29] */ -#define FLD_DIF_BPF_COEFF_18 0x1FFF0000 +#define FLD_DIF_BPF_COEFF_18 0x1fff0000 /* Reserved [15:13] */ -#define FLD_DIF_BPF_COEFF_19 0x00001FFF +#define FLD_DIF_BPF_COEFF_19 0x00001fff /*****************************************************************************/ -#define DIF_BPF_COEFF2021 (DIRECT_IF_REVB_BASE + 0x00000070) /* Reg Size 32 */ +#define DIF_BPF_COEFF2021 (DIRECT_IF_REVB_BASE + 0x00000070) /*****************************************************************************/ /* Reserved [31:29] */ -#define FLD_DIF_BPF_COEFF_20 0x1FFF0000 +#define FLD_DIF_BPF_COEFF_20 0x1fff0000 /* Reserved [15:14] */ -#define FLD_DIF_BPF_COEFF_21 0x00003FFF +#define FLD_DIF_BPF_COEFF_21 0x00003fff /*****************************************************************************/ -#define DIF_BPF_COEFF2223 (DIRECT_IF_REVB_BASE + 0x00000074) /* Reg Size 32 */ +#define DIF_BPF_COEFF2223 (DIRECT_IF_REVB_BASE + 0x00000074) /*****************************************************************************/ /* Reserved [31:30] */ -#define FLD_DIF_BPF_COEFF_22 0x3FFF0000 +#define FLD_DIF_BPF_COEFF_22 0x3fff0000 /* Reserved [15:14] */ -#define FLD_DIF_BPF_COEFF_23 0x00003FFF +#define FLD_DIF_BPF_COEFF_23 0x00003fff /*****************************************************************************/ -#define DIF_BPF_COEFF2425 (DIRECT_IF_REVB_BASE + 0x00000078) /* Reg Size 32 */ +#define DIF_BPF_COEFF2425 (DIRECT_IF_REVB_BASE + 0x00000078) /*****************************************************************************/ /* Reserved [31:30] */ -#define FLD_DIF_BPF_COEFF_24 0x3FFF0000 +#define FLD_DIF_BPF_COEFF_24 0x3fff0000 /* Reserved [15:14] */ -#define FLD_DIF_BPF_COEFF_25 0x00003FFF +#define FLD_DIF_BPF_COEFF_25 0x00003fff /*****************************************************************************/ -#define DIF_BPF_COEFF2627 (DIRECT_IF_REVB_BASE + 0x0000007C) /* Reg Size 32 */ +#define DIF_BPF_COEFF2627 (DIRECT_IF_REVB_BASE + 0x0000007c) /*****************************************************************************/ /* Reserved [31:30] */ -#define FLD_DIF_BPF_COEFF_26 0x3FFF0000 +#define FLD_DIF_BPF_COEFF_26 0x3fff0000 /* Reserved [15:14] */ -#define FLD_DIF_BPF_COEFF_27 0x00003FFF +#define FLD_DIF_BPF_COEFF_27 0x00003fff /*****************************************************************************/ -#define DIF_BPF_COEFF2829 (DIRECT_IF_REVB_BASE + 0x00000080) /* Reg Size 32 */ +#define DIF_BPF_COEFF2829 (DIRECT_IF_REVB_BASE + 0x00000080) /*****************************************************************************/ /* Reserved [31:30] */ -#define FLD_DIF_BPF_COEFF_28 0x3FFF0000 +#define FLD_DIF_BPF_COEFF_28 0x3fff0000 /* Reserved [15:14] */ -#define FLD_DIF_BPF_COEFF_29 0x00003FFF +#define FLD_DIF_BPF_COEFF_29 0x00003fff /*****************************************************************************/ -#define DIF_BPF_COEFF3031 (DIRECT_IF_REVB_BASE + 0x00000084) /* Reg Size 32 */ +#define DIF_BPF_COEFF3031 (DIRECT_IF_REVB_BASE + 0x00000084) /*****************************************************************************/ /* Reserved [31:30] */ -#define FLD_DIF_BPF_COEFF_30 0x3FFF0000 +#define FLD_DIF_BPF_COEFF_30 0x3fff0000 /* Reserved [15:14] */ -#define FLD_DIF_BPF_COEFF_31 0x00003FFF +#define FLD_DIF_BPF_COEFF_31 0x00003fff /*****************************************************************************/ -#define DIF_BPF_COEFF3233 (DIRECT_IF_REVB_BASE + 0x00000088) /* Reg Size 32 */ +#define DIF_BPF_COEFF3233 (DIRECT_IF_REVB_BASE + 0x00000088) /*****************************************************************************/ /* Reserved [31:30] */ -#define FLD_DIF_BPF_COEFF_32 0x3FFF0000 +#define FLD_DIF_BPF_COEFF_32 0x3fff0000 /* Reserved [15:14] */ -#define FLD_DIF_BPF_COEFF_33 0x00003FFF +#define FLD_DIF_BPF_COEFF_33 0x00003fff /*****************************************************************************/ -#define DIF_BPF_COEFF3435 (DIRECT_IF_REVB_BASE + 0x0000008C) /* Reg Size 32 */ +#define DIF_BPF_COEFF3435 (DIRECT_IF_REVB_BASE + 0x0000008c) /*****************************************************************************/ /* Reserved [31:30] */ -#define FLD_DIF_BPF_COEFF_34 0x3FFF0000 +#define FLD_DIF_BPF_COEFF_34 0x3fff0000 /* Reserved [15:14] */ -#define FLD_DIF_BPF_COEFF_35 0x00003FFF +#define FLD_DIF_BPF_COEFF_35 0x00003fff /*****************************************************************************/ -#define DIF_BPF_COEFF36 (DIRECT_IF_REVB_BASE + 0x00000090) /* Reg Size 32 */ +#define DIF_BPF_COEFF36 (DIRECT_IF_REVB_BASE + 0x00000090) /*****************************************************************************/ /* Reserved [31:30] */ -#define FLD_DIF_BPF_COEFF_36 0x3FFF0000 +#define FLD_DIF_BPF_COEFF_36 0x3fff0000 /* Reserved [15:0] */ /*****************************************************************************/ -#define DIF_RPT_VARIANCE (DIRECT_IF_REVB_BASE + 0x00000094) /* Reg Size 32 */ +#define DIF_RPT_VARIANCE (DIRECT_IF_REVB_BASE + 0x00000094) /*****************************************************************************/ /* Reserved [31:20] */ -#define FLD_DIF_RPT_VARIANCE 0x000FFFFF +#define FLD_DIF_RPT_VARIANCE 0x000fffff /*****************************************************************************/ -#define DIF_SOFT_RST_CTRL_REVB (DIRECT_IF_REVB_BASE + 0x00000098) /* Reg Size 32 */ +#define DIF_SOFT_RST_CTRL_REVB (DIRECT_IF_REVB_BASE + 0x00000098) /*****************************************************************************/ /* Reserved [31:8] */ #define FLD_DIF_DIF_SOFT_RST 0x00000080 @@ -479,9 +486,9 @@ typedef enum { #define FLD_DIF_PLL_RST_MSK 0x00000001 /*****************************************************************************/ -#define DIF_PLL_FREQ_ERR (DIRECT_IF_REVB_BASE + 0x0000009C) /* Reg Size 32 */ +#define DIF_PLL_FREQ_ERR (DIRECT_IF_REVB_BASE + 0x0000009c) /*****************************************************************************/ /* Reserved [31:25] */ -#define FLD_DIF_CTL_IP 0x01FFFFFF +#define FLD_DIF_CTL_IP 0x01ffffff #endif diff --git a/drivers/media/video/cx231xx/cx231xx-core.c b/drivers/media/video/cx231xx/cx231xx-core.c index 2dda863dd3c4..80deffee984a 100644 --- a/drivers/media/video/cx231xx/cx231xx-core.c +++ b/drivers/media/video/cx231xx/cx231xx-core.c @@ -54,7 +54,6 @@ static int alt = CX231XX_PINOUT; module_param(alt, int, 0644); MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint"); -/* FIXME */ #define cx231xx_isocdbg(fmt, arg...) do {\ if (core_debug) \ printk(KERN_INFO "%s %s :"fmt, \ @@ -308,7 +307,7 @@ int cx231xx_read_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg, reg & 0xff, reg >> 8, len & 0xff, len >> 8); } - /* mutex_lock(&dev->ctrl_urb_lock); */ + mutex_lock(&dev->ctrl_urb_lock); ret = usb_control_msg(dev->udev, pipe, req, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, val, reg, dev->urb_buf, len, HZ); @@ -321,7 +320,7 @@ int cx231xx_read_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg, if (len) memcpy(buf, dev->urb_buf, len); - /* mutex_unlock(&dev->ctrl_urb_lock); */ + mutex_unlock(&dev->ctrl_urb_lock); if (reg_debug) { int byte; @@ -369,13 +368,13 @@ int cx231xx_send_vendor_cmd(struct cx231xx *dev, cx231xx_isocdbg("\n"); } - /* mutex_lock(&dev->ctrl_urb_lock); */ + mutex_lock(&dev->ctrl_urb_lock); ret = usb_control_msg(dev->udev, pipe, ven_req->bRequest, ven_req-> direction | USB_TYPE_VENDOR | USB_RECIP_DEVICE, ven_req->wValue, ven_req->wIndex, ven_req->pBuff, ven_req->wLength, HZ); - /* mutex_unlock(&dev->ctrl_urb_lock); */ + mutex_unlock(&dev->ctrl_urb_lock); return ret; } @@ -432,12 +431,12 @@ int cx231xx_write_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg, char *buf, cx231xx_isocdbg("\n"); } - /* mutex_lock(&dev->ctrl_urb_lock); */ + mutex_lock(&dev->ctrl_urb_lock); memcpy(dev->urb_buf, buf, len); ret = usb_control_msg(dev->udev, pipe, req, USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, val, reg, dev->urb_buf, len, HZ); - /* mutex_unlock(&dev->ctrl_urb_lock); */ + mutex_unlock(&dev->ctrl_urb_lock); return ret; } diff --git a/drivers/media/video/cx231xx/cx231xx-i2c.c b/drivers/media/video/cx231xx/cx231xx-i2c.c index 1af87579ab49..4489126c48c1 100644 --- a/drivers/media/video/cx231xx/cx231xx-i2c.c +++ b/drivers/media/video/cx231xx/cx231xx-i2c.c @@ -42,8 +42,8 @@ MODULE_PARM_DESC(i2c_debug, "enable debug messages [i2c]"); #define dprintk1(lvl, fmt, args...) \ do { \ if (i2c_debug >= lvl) { \ - printk(fmt, ##args); \ - } \ + printk(fmt, ##args); \ + } \ } while (0) #define dprintk2(lvl, fmt, args...) \ @@ -77,13 +77,10 @@ int cx231xx_i2c_send_bytes(struct i2c_adapter *i2c_adap, size = msg->len; if (size == 2) { /* register write sub addr */ - - /* Just writing sub address will cause problem to XC5000 - So ignore the request */ + /* Just writing sub address will cause problem + * to XC5000. So ignore the request */ return 0; - } else if (size == 4) { /* register write with sub addr */ - if (msg->len >= 2) saddr = msg->buf[0] << 8 | msg->buf[1]; else if (msg->len == 1) @@ -117,7 +114,6 @@ int cx231xx_i2c_send_bytes(struct i2c_adapter *i2c_adap, msg->buf, msg->len); } - } /* special case for Xc5000 tuner case */ diff --git a/drivers/media/video/cx231xx/cx231xx-pcb-cfg.c b/drivers/media/video/cx231xx/cx231xx-pcb-cfg.c new file mode 100644 index 000000000000..c00f51eae0ac --- /dev/null +++ b/drivers/media/video/cx231xx/cx231xx-pcb-cfg.c @@ -0,0 +1,793 @@ +/* + cx231xx-pcb-config.c - driver for Conexant + Cx23100/101/102 USB video capture devices + + Copyright (C) 2008 <srinivasa.deevi at conexant dot com> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "cx231xx.h" +#include "cx231xx-conf-reg.h" + +/******************************************************************************/ + +struct pcb_config cx231xx_Scenario[] = { + { + INDEX_SELFPOWER_DIGITAL_ONLY, /* index */ + USB_SELF_POWER, /* power_type */ + 0, /* speed , not decide yet */ + MOD_DIGITAL, /* mode */ + SOURCE_TS_BDA, /* ts1_source, digital tv only */ + NOT_SUPPORTED, /* ts2_source */ + NOT_SUPPORTED, /* analog source */ + + 0, /* digital_index */ + 0, /* analog index */ + 0, /* dif_index */ + 0, /* external_index */ + + 1, /* only one configuration */ + { + { + 0, /* config index */ + { + 0, /* interrupt ep index */ + 1, /* ts1 index */ + NOT_SUPPORTED, /* TS2 index */ + NOT_SUPPORTED, /* AUDIO */ + NOT_SUPPORTED, /* VIDEO */ + NOT_SUPPORTED, /* VANC */ + NOT_SUPPORTED, /* HANC */ + NOT_SUPPORTED /* ir_index */ + } + , + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + } + , + /* full-speed config */ + { + { + 0, /* config index */ + { + 0, /* interrupt ep index */ + 1, /* ts1 index */ + NOT_SUPPORTED, /* TS2 index */ + NOT_SUPPORTED, /* AUDIO */ + NOT_SUPPORTED, /* VIDEO */ + NOT_SUPPORTED, /* VANC */ + NOT_SUPPORTED, /* HANC */ + NOT_SUPPORTED /* ir_index */ + } + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + } + } + , + + { + INDEX_SELFPOWER_DUAL_DIGITAL, /* index */ + USB_SELF_POWER, /* power_type */ + 0, /* speed , not decide yet */ + MOD_DIGITAL, /* mode */ + SOURCE_TS_BDA, /* ts1_source, digital tv only */ + 0, /* ts2_source,need update from register */ + NOT_SUPPORTED, /* analog source */ + 0, /* digital_index */ + 0, /* analog index */ + 0, /* dif_index */ + 0, /* external_index */ + + 1, /* only one configuration */ + { + { + 0, /* config index */ + { + 0, /* interrupt ep index */ + 1, /* ts1 index */ + 2, /* TS2 index */ + NOT_SUPPORTED, /* AUDIO */ + NOT_SUPPORTED, /* VIDEO */ + NOT_SUPPORTED, /* VANC */ + NOT_SUPPORTED, /* HANC */ + NOT_SUPPORTED /* ir_index */ + } + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + } + , + /* full-speed */ + { + { + 0, /* config index */ + { + 0, /* interrupt ep index */ + 1, /* ts1 index */ + 2, /* TS2 index */ + NOT_SUPPORTED, /* AUDIO */ + NOT_SUPPORTED, /* VIDEO */ + NOT_SUPPORTED, /* VANC */ + NOT_SUPPORTED, /* HANC */ + NOT_SUPPORTED /* ir_index */ + } + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + } + } + , + + { + INDEX_SELFPOWER_ANALOG_ONLY, /* index */ + USB_SELF_POWER, /* power_type */ + 0, /* speed , not decide yet */ + MOD_ANALOG | MOD_DIF | MOD_EXTERNAL, /* mode ,analog tv only */ + NOT_SUPPORTED, /* ts1_source, NOT SUPPORT */ + NOT_SUPPORTED, /* ts2_source,NOT SUPPORT */ + 0, /* analog source, need update */ + + 0, /* digital_index */ + 0, /* analog index */ + 0, /* dif_index */ + 0, /* external_index */ + + 1, /* only one configuration */ + { + { + 0, /* config index */ + { + 0, /* interrupt ep index */ + NOT_SUPPORTED, /* ts1 index */ + NOT_SUPPORTED, /* TS2 index */ + 1, /* AUDIO */ + 2, /* VIDEO */ + 3, /* VANC */ + 4, /* HANC */ + NOT_SUPPORTED /* ir_index */ + } + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + } + , + /* full-speed */ + { + { + 0, /* config index */ + { + 0, /* interrupt ep index */ + NOT_SUPPORTED, /* ts1 index */ + NOT_SUPPORTED, /* TS2 index */ + 1, /* AUDIO */ + 2, /* VIDEO */ + NOT_SUPPORTED, /* VANC */ + NOT_SUPPORTED, /* HANC */ + NOT_SUPPORTED /* ir_index */ + } + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + } + } + , + + { + INDEX_SELFPOWER_DUAL, /* index */ + USB_SELF_POWER, /* power_type */ + 0, /* speed , not decide yet */ + /* mode ,analog tv and digital path */ + MOD_ANALOG | MOD_DIF | MOD_DIGITAL | MOD_EXTERNAL, + 0, /* ts1_source,will update in register */ + NOT_SUPPORTED, /* ts2_source,NOT SUPPORT */ + 0, /* analog source need update */ + 0, /* digital_index */ + 0, /* analog index */ + 0, /* dif_index */ + 0, /* external_index */ + 1, /* only one configuration */ + { + { + 0, /* config index */ + { + 0, /* interrupt ep index */ + 1, /* ts1 index */ + NOT_SUPPORTED, /* TS2 index */ + 2, /* AUDIO */ + 3, /* VIDEO */ + 4, /* VANC */ + 5, /* HANC */ + NOT_SUPPORTED /* ir_index */ + } + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + } + , + /* full-speed */ + { + { + 0, /* config index */ + { + 0, /* interrupt ep index */ + 1, /* ts1 index */ + NOT_SUPPORTED, /* TS2 index */ + 2, /* AUDIO */ + 3, /* VIDEO */ + NOT_SUPPORTED, /* VANC */ + NOT_SUPPORTED, /* HANC */ + NOT_SUPPORTED /* ir_index */ + } + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + } + } + , + + { + INDEX_SELFPOWER_TRIPLE, /* index */ + USB_SELF_POWER, /* power_type */ + 0, /* speed , not decide yet */ + /* mode ,analog tv and digital path */ + MOD_ANALOG | MOD_DIF | MOD_DIGITAL | MOD_EXTERNAL, + 0, /* ts1_source, update in register */ + 0, /* ts2_source,update in register */ + 0, /* analog source, need update */ + + 0, /* digital_index */ + 0, /* analog index */ + 0, /* dif_index */ + 0, /* external_index */ + 1, /* only one configuration */ + { + { + 0, /* config index */ + { + 0, /* interrupt ep index */ + 1, /* ts1 index */ + 2, /* TS2 index */ + 3, /* AUDIO */ + 4, /* VIDEO */ + 5, /* VANC */ + 6, /* HANC */ + NOT_SUPPORTED /* ir_index */ + } + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + } + , + /* full-speed */ + { + { + 0, /* config index */ + { + 0, /* interrupt ep index */ + 1, /* ts1 index */ + 2, /* TS2 index */ + 3, /* AUDIO */ + 4, /* VIDEO */ + NOT_SUPPORTED, /* VANC */ + NOT_SUPPORTED, /* HANC */ + NOT_SUPPORTED /* ir_index */ + } + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + } + } + , + + { + INDEX_SELFPOWER_COMPRESSOR, /* index */ + USB_SELF_POWER, /* power_type */ + 0, /* speed , not decide yet */ + /* mode ,analog tv AND DIGITAL path */ + MOD_ANALOG | MOD_DIF | MOD_DIGITAL | MOD_EXTERNAL, + NOT_SUPPORTED, /* ts1_source, disable */ + SOURCE_TS_BDA, /* ts2_source */ + 0, /* analog source,need update */ + 0, /* digital_index */ + 0, /* analog index */ + 0, /* dif_index */ + 0, /* external_index */ + 1, /* only one configuration */ + { + { + 0, /* config index */ + { + 0, /* interrupt ep index */ + NOT_SUPPORTED, /* ts1 index */ + 1, /* TS2 index */ + 2, /* AUDIO */ + 3, /* VIDEO */ + 4, /* VANC */ + 5, /* HANC */ + NOT_SUPPORTED /* ir_index */ + } + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + } + , + /* full-speed */ + { + { + 0, /* config index */ + { + 0, /* interrupt ep index */ + NOT_SUPPORTED, /* ts1 index */ + 1, /* TS2 index */ + 2, /* AUDIO */ + 3, /* VIDEO */ + NOT_SUPPORTED, /* VANC */ + NOT_SUPPORTED, /* HANC */ + NOT_SUPPORTED /* ir_index */ + } + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + } + } + , + + { + INDEX_BUSPOWER_DIGITAL_ONLY, /* index */ + USB_BUS_POWER, /* power_type */ + 0, /* speed , not decide yet */ + MOD_DIGITAL, /* mode ,analog tv AND DIGITAL path */ + SOURCE_TS_BDA, /* ts1_source, disable */ + NOT_SUPPORTED, /* ts2_source */ + NOT_SUPPORTED, /* analog source */ + + 0, /* digital_index */ + 0, /* analog index */ + 0, /* dif_index */ + 0, /* external_index */ + + 1, /* only one configuration */ + { + { + 0, /* config index */ + { + 0, /* interrupt ep index = 2 */ + 1, /* ts1 index */ + NOT_SUPPORTED, /* TS2 index */ + NOT_SUPPORTED, /* AUDIO */ + NOT_SUPPORTED, /* VIDEO */ + NOT_SUPPORTED, /* VANC */ + NOT_SUPPORTED, /* HANC */ + NOT_SUPPORTED /* ir_index */ + } + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + } + , + /* full-speed */ + { + { + 0, /* config index */ + { + 0, /* interrupt ep index = 2 */ + 1, /* ts1 index */ + NOT_SUPPORTED, /* TS2 index */ + NOT_SUPPORTED, /* AUDIO */ + NOT_SUPPORTED, /* VIDEO */ + NOT_SUPPORTED, /* VANC */ + NOT_SUPPORTED, /* HANC */ + NOT_SUPPORTED /* ir_index */ + } + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + } + } + , + { + INDEX_BUSPOWER_ANALOG_ONLY, /* index */ + USB_BUS_POWER, /* power_type */ + 0, /* speed , not decide yet */ + MOD_ANALOG, /* mode ,analog tv AND DIGITAL path */ + NOT_SUPPORTED, /* ts1_source, disable */ + NOT_SUPPORTED, /* ts2_source */ + SOURCE_ANALOG, /* analog source--analog */ + 0, /* digital_index */ + 0, /* analog index */ + 0, /* dif_index */ + 0, /* external_index */ + 1, /* only one configuration */ + { + { + 0, /* config index */ + { + 0, /* interrupt ep index */ + NOT_SUPPORTED, /* ts1 index */ + NOT_SUPPORTED, /* TS2 index */ + 1, /* AUDIO */ + 2, /* VIDEO */ + 3, /* VANC */ + 4, /* HANC */ + NOT_SUPPORTED /* ir_index */ + } + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + } + , + { /* full-speed */ + { + 0, /* config index */ + { + 0, /* interrupt ep index */ + NOT_SUPPORTED, /* ts1 index */ + NOT_SUPPORTED, /* TS2 index */ + 1, /* AUDIO */ + 2, /* VIDEO */ + NOT_SUPPORTED, /* VANC */ + NOT_SUPPORTED, /* HANC */ + NOT_SUPPORTED /* ir_index */ + } + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + } + } + , + { + INDEX_BUSPOWER_DIF_ONLY, /* index */ + USB_BUS_POWER, /* power_type */ + 0, /* speed , not decide yet */ + /* mode ,analog tv AND DIGITAL path */ + MOD_DIF | MOD_ANALOG | MOD_DIGITAL | MOD_EXTERNAL, + SOURCE_TS_BDA, /* ts1_source, disable */ + NOT_SUPPORTED, /* ts2_source */ + SOURCE_DIF | SOURCE_ANALOG | SOURCE_EXTERNAL, /* analog source, dif */ + 0, /* digital_index */ + 0, /* analog index */ + 0, /* dif_index */ + 0, /* external_index */ + 1, /* only one configuration */ + { + { + 0, /* config index */ + { + 0, /* interrupt ep index */ + 1, /* ts1 index */ + NOT_SUPPORTED, /* TS2 index */ + 2, /* AUDIO */ + 3, /* VIDEO */ + 4, /* VANC */ + 5, /* HANC */ + NOT_SUPPORTED /* ir_index */ + } + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + } + , + { /* full speed */ + { + 0, /* config index */ + { + 0, /* interrupt ep index */ + 1, /* ts1 index */ + NOT_SUPPORTED, /* TS2 index */ + 2, /* AUDIO */ + 3, /* VIDEO */ + NOT_SUPPORTED, /* VANC */ + NOT_SUPPORTED, /* HANC */ + NOT_SUPPORTED /* ir_index */ + } + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + , + {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED, + NOT_SUPPORTED} + } + } + } + , + +}; + +/*****************************************************************/ + +u32 initialize_cx231xx(struct cx231xx *dev) +{ + u32 config_info = 0; + struct pcb_config *p_pcb_info; + u8 usb_speed = 1; /* from register,1--HS, 0--FS */ + u8 data[4] = { 0, 0, 0, 0 }; + u32 ts1_source = 0; + u32 ts2_source = 0; + u32 analog_source = 0; + u8 tmp = 0; + u8 _current_scenario_idx = 0xff; + + cx231xx_info("PcbConfig::initialize \n"); + + ts1_source = SOURCE_TS_BDA; + ts2_source = SOURCE_TS_BDA; + + /* read board config register to find out which + pcb config it is related to */ + cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT, data, 4); + + config_info = *((u32 *) data); + cx231xx_info("SC(0x00) register = 0x%x\n", config_info); + usb_speed = (u8) (config_info & 0x1); + + /* Verify this device belongs to Bus power or Self power device */ + if (config_info & BUS_POWER) { /* bus-power */ + switch (config_info & BUSPOWER_MASK) { + case TS1_PORT | BUS_POWER: + cx231xx_Scenario[INDEX_BUSPOWER_DIGITAL_ONLY].speed = + usb_speed; + p_pcb_info = + &cx231xx_Scenario[INDEX_BUSPOWER_DIGITAL_ONLY]; + _current_scenario_idx = INDEX_BUSPOWER_DIGITAL_ONLY; + break; + case AVDEC_ENABLE | BUS_POWER: + cx231xx_Scenario[INDEX_BUSPOWER_ANALOG_ONLY].speed = + usb_speed; + p_pcb_info = + &cx231xx_Scenario[INDEX_BUSPOWER_ANALOG_ONLY]; + _current_scenario_idx = INDEX_BUSPOWER_ANALOG_ONLY; + break; + case AVDEC_ENABLE | BUS_POWER | TS1_PORT: + cx231xx_Scenario[INDEX_BUSPOWER_DIF_ONLY].speed = + usb_speed; + p_pcb_info = &cx231xx_Scenario[INDEX_BUSPOWER_DIF_ONLY]; + _current_scenario_idx = INDEX_BUSPOWER_DIF_ONLY; + break; + default: + cx231xx_info("bad config in buspower!!!!\n"); + cx231xx_info("config_info=%x\n", + (config_info & BUSPOWER_MASK)); + return 1; + } + } else { /* self-power */ + + switch (config_info & SELFPOWER_MASK) { + case TS1_PORT | SELF_POWER: + cx231xx_Scenario[INDEX_SELFPOWER_DIGITAL_ONLY].speed = + usb_speed; + p_pcb_info = + &cx231xx_Scenario[INDEX_SELFPOWER_DIGITAL_ONLY]; + _current_scenario_idx = INDEX_SELFPOWER_DIGITAL_ONLY; + break; + case TS1_TS2_PORT | SELF_POWER: + cx231xx_Scenario[INDEX_SELFPOWER_DUAL_DIGITAL].speed = + usb_speed; + cx231xx_Scenario[INDEX_SELFPOWER_DUAL_DIGITAL]. + ts2_source = ts2_source; + p_pcb_info = + &cx231xx_Scenario[INDEX_SELFPOWER_DUAL_DIGITAL]; + _current_scenario_idx = INDEX_SELFPOWER_DUAL_DIGITAL; + break; + case AVDEC_ENABLE | SELF_POWER: + cx231xx_Scenario[INDEX_SELFPOWER_ANALOG_ONLY].speed = + usb_speed; + cx231xx_Scenario[INDEX_SELFPOWER_ANALOG_ONLY]. + analog_source = analog_source; + p_pcb_info = + &cx231xx_Scenario[INDEX_SELFPOWER_ANALOG_ONLY]; + _current_scenario_idx = INDEX_SELFPOWER_ANALOG_ONLY; + break; + case AVDEC_ENABLE | TS1_PORT | SELF_POWER: + cx231xx_Scenario[INDEX_SELFPOWER_DUAL].speed = + usb_speed; + cx231xx_Scenario[INDEX_SELFPOWER_DUAL].ts1_source = + ts1_source; + cx231xx_Scenario[INDEX_SELFPOWER_DUAL].analog_source = + analog_source; + p_pcb_info = &cx231xx_Scenario[INDEX_SELFPOWER_DUAL]; + _current_scenario_idx = INDEX_SELFPOWER_DUAL; + break; + case AVDEC_ENABLE | TS1_TS2_PORT | SELF_POWER: + cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE].speed = + usb_speed; + cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE].ts1_source = + ts1_source; + cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE].ts2_source = + ts2_source; + cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE].analog_source = + analog_source; + p_pcb_info = &cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE]; + _current_scenario_idx = INDEX_SELFPOWER_TRIPLE; + break; + case AVDEC_ENABLE | TS1VIP_TS2_PORT | SELF_POWER: + cx231xx_Scenario[INDEX_SELFPOWER_COMPRESSOR].speed = + usb_speed; + cx231xx_Scenario[INDEX_SELFPOWER_COMPRESSOR]. + analog_source = analog_source; + p_pcb_info = + &cx231xx_Scenario[INDEX_SELFPOWER_COMPRESSOR]; + _current_scenario_idx = INDEX_SELFPOWER_COMPRESSOR; + break; + default: + cx231xx_info("bad senario!!!!!\n"); + cx231xx_info("config_info=%x\n", + (config_info & SELFPOWER_MASK)); + return 1; + } + } + + dev->current_scenario_idx = _current_scenario_idx; + + memcpy(&dev->current_pcb_config, p_pcb_info, + sizeof(struct pcb_config)); + + /*******************************************************************/ + tmp = (dev->current_pcb_config.index) + 1; + + cx231xx_info("scenario %d\n", tmp); + cx231xx_info("type=%x\n", dev->current_pcb_config.type); + cx231xx_info("mode=%x\n", dev->current_pcb_config.mode); + cx231xx_info("speed=%x\n", dev->current_pcb_config.speed); + cx231xx_info("ts1_source=%x\n", dev->current_pcb_config.ts1_source); + cx231xx_info("ts2_source=%x\n", dev->current_pcb_config.ts2_source); + cx231xx_info("analog_source=%x\n", + dev->current_pcb_config.analog_source); + /*******************************************************************/ + + return 0; +} diff --git a/drivers/media/video/cx231xx/cx231xx-pcb-cfg.h b/drivers/media/video/cx231xx/cx231xx-pcb-cfg.h new file mode 100644 index 000000000000..86fec113f5c5 --- /dev/null +++ b/drivers/media/video/cx231xx/cx231xx-pcb-cfg.h @@ -0,0 +1,235 @@ +/* + cx231xx-pcb-cfg.h - driver for Conexant + Cx23100/101/102 USB video capture devices + + Copyright (C) 2008 <srinivasa.deevi at conexant dot com> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _PCB_CONFIG_H_ +#define _PCB_CONFIG_H_ + +#include <linux/init.h> +#include <linux/module.h> + +/*************************************************************************** + * Class Information * +***************************************************************************/ +#define CLASS_DEFAULT 0xFF + +enum VENDOR_REQUEST_TYPE { + /* Set/Get I2C */ + VRT_SET_I2C0 = 0x0, + VRT_SET_I2C1 = 0x1, + VRT_SET_I2C2 = 0x2, + VRT_GET_I2C0 = 0x4, + VRT_GET_I2C1 = 0x5, + VRT_GET_I2C2 = 0x6, + + /* Set/Get GPIO */ + VRT_SET_GPIO = 0x8, + VRT_GET_GPIO = 0x9, + + /* Set/Get GPIE */ + VRT_SET_GPIE = 0xA, + VRT_GET_GPIE = 0xB, + + /* Set/Get Register Control/Status */ + VRT_SET_REGISTER = 0xC, + VRT_GET_REGISTER = 0xD, + + /* Get Extended Compat ID Descriptor */ + VRT_GET_EXTCID_DESC = 0xFF, +}; + +enum BYTE_ENABLE_MASK { + ENABLE_ONE_BYTE = 0x1, + ENABLE_TWE_BYTE = 0x3, + ENABLE_THREE_BYTE = 0x7, + ENABLE_FOUR_BYTE = 0xF, +}; + +#define SPEED_MASK 0x1 +enum USB_SPEED{ + FULL_SPEED = 0x0, /* 0: full speed */ + HIGH_SPEED = 0x1 /* 1: high speed */ +}; + +enum _true_false{ + FALSE = 0, + TRUE = 1 +}; + +#define TS_MASK 0x6 +enum TS_PORT{ + NO_TS_PORT = 0x0, /* 2'b00: Neither port used. PCB not a Hybrid, + only offers Analog TV or Video */ + TS1_PORT = 0x4, /* 2'b10: TS1 Input (Hybrid mode : + Digital or External Analog/Compressed source) */ + TS1_TS2_PORT = 0x6, /* 2'b11: TS1 & TS2 Inputs + (Dual inputs from Digital and/or + External Analog/Compressed sources) */ + TS1_EXT_CLOCK = 0x6, /* 2'b11: TS1 & TS2 as selector + to external clock */ + TS1VIP_TS2_PORT = 0x2 /* 2'b01: TS1 used as 656/VIP Output, + TS2 Input (from Compressor) */ +}; + +#define EAVP_MASK 0x8 +enum EAV_PRESENT{ + NO_EXTERNAL_AV = 0x0, /* 0: No External A/V inputs + (no need for Flatiron), + Analog Tuner must be present */ + EXTERNAL_AV = 0x8 /* 1: External A/V inputs + present (requires Flatiron) */ +}; + +#define ATM_MASK 0x30 +enum AT_MODE{ + DIF_TUNER = 0x30, /* 2'b11: IF Tuner (requires use of DIF) */ + BASEBAND_SOUND = 0x20, /* 2'b10: Baseband Composite & + Sound-IF Signals present */ + NO_TUNER = 0x10 /* 2'b0x: No Analog Tuner present */ +}; + +#define PWR_SEL_MASK 0x40 +enum POWE_TYPE{ + SELF_POWER = 0x0, /* 0: self power */ + BUS_POWER = 0x40 /* 1: bus power */ +}; + +enum USB_POWE_TYPE{ + USB_SELF_POWER = 0, + USB_BUS_POWER +}; + +#define BO_0_MASK 0x80 +enum AVDEC_STATUS{ + AVDEC_DISABLE = 0x0, /* 0: A/V Decoder Disabled */ + AVDEC_ENABLE = 0x80 /* 1: A/V Decoder Enabled */ +}; + +#define BO_1_MASK 0x100 +enum HAMMERHEAD__STATUS{ + HAMMERHEAD_ONLY = 0x0, /* 0:Hammerhead Only */ + HAMMERHEAD_SC = 0x100 /* 1:Hammerhead and SC */ +}; + +#define BUSPOWER_MASK 0xC4 /* for Polaris spec 0.8 */ +#define SELFPOWER_MASK 0x86 + +/***************************************************************************/ +#define NOT_DECIDE_YET 0xFE +#define NOT_SUPPORTED 0xFF + +/*************************************************************************** + * for mod field use * +***************************************************************************/ +#define MOD_DIGITAL 0x1 +#define MOD_ANALOG 0x2 +#define MOD_DIF 0x4 +#define MOD_EXTERNAL 0x8 +#define CAP_ALL_MOD 0x0f + +/*************************************************************************** + * source define * +***************************************************************************/ +#define SOURCE_DIGITAL 0x1 +#define SOURCE_ANALOG 0x2 +#define SOURCE_DIF 0x4 +#define SOURCE_EXTERNAL 0x8 +#define SOURCE_TS_BDA 0x10 +#define SOURCE_TS_ENCODE 0x20 +#define SOURCE_TS_EXTERNAL 0x40 + +/*************************************************************************** + * interface information define * +***************************************************************************/ +struct INTERFACE_INFO { + u8 interrupt_index; + u8 ts1_index; + u8 ts2_index; + u8 audio_index; + u8 video_index; + u8 vanc_index; /* VBI */ + u8 hanc_index; /* Sliced CC */ + u8 ir_index; +}; + +enum INDEX_INTERFACE_INFO{ + INDEX_INTERRUPT = 0x0, + INDEX_TS1, + INDEX_TS2, + INDEX_AUDIO, + INDEX_VIDEO, + INDEX_VANC, + INDEX_HANC, + INDEX_IR, +}; + +/*************************************************************************** + * configuration information define * +***************************************************************************/ +struct CONFIG_INFO { + u8 config_index; + struct INTERFACE_INFO interface_info; +}; + +struct pcb_config { + u8 index; + u8 type; /* bus power or self power, + self power--0, bus_power--1 */ + u8 speed; /* usb speed, 2.0--1, 1.1--0 */ + u8 mode; /* digital , anlog, dif or external A/V */ + u32 ts1_source; /* three source -- BDA,External,encode */ + u32 ts2_source; + u32 analog_source; + u8 digital_index; /* bus-power used */ + u8 analog_index; /* bus-power used */ + u8 dif_index; /* bus-power used */ + u8 external_index; /* bus-power used */ + u8 config_num; /* current config num, 0,1,2, + for self-power, always 0 */ + struct CONFIG_INFO hs_config_info[3]; + struct CONFIG_INFO fs_config_info[3]; +}; + +enum INDEX_PCB_CONFIG{ + INDEX_SELFPOWER_DIGITAL_ONLY = 0x0, + INDEX_SELFPOWER_DUAL_DIGITAL, + INDEX_SELFPOWER_ANALOG_ONLY, + INDEX_SELFPOWER_DUAL, + INDEX_SELFPOWER_TRIPLE, + INDEX_SELFPOWER_COMPRESSOR, + INDEX_BUSPOWER_DIGITAL_ONLY, + INDEX_BUSPOWER_ANALOG_ONLY, + INDEX_BUSPOWER_DIF_ONLY, + INDEX_BUSPOWER_EXTERNAL_ONLY, + INDEX_BUSPOWER_EXTERNAL_ANALOG, + INDEX_BUSPOWER_EXTERNAL_DIF, + INDEX_BUSPOWER_EXTERNAL_DIGITAL, + INDEX_BUSPOWER_DIGITAL_ANALOG, + INDEX_BUSPOWER_DIGITAL_DIF, + INDEX_BUSPOWER_DIGITAL_ANALOG_EXTERNAL, + INDEX_BUSPOWER_DIGITAL_DIF_EXTERNAL, +}; + +/***************************************************************************/ +struct cx231xx; + +u32 initialize_cx231xx(struct cx231xx *p_dev); + +#endif diff --git a/drivers/media/video/cx231xx/cx231xx-reg.h b/drivers/media/video/cx231xx/cx231xx-reg.h index d2d325b21d4f..750c5d37d569 100644 --- a/drivers/media/video/cx231xx/cx231xx-reg.h +++ b/drivers/media/video/cx231xx/cx231xx-reg.h @@ -1,6 +1,6 @@ /* cx231xx-reg.h - driver for Conexant Cx23100/101/102 - USB video capture devices + USB video capture devices Copyright (C) 2008 <srinivasa.deevi at conexant dot com> @@ -23,31 +23,31 @@ #define _CX231XX_REG_H /***************************************************************************** - * VBI codes * + * VBI codes * *****************************************************************************/ -#define SAV_ACTIVE_VIDEO_FIELD1 0x80 -#define EAV_ACTIVE_VIDEO_FIELD1 0x90 +#define SAV_ACTIVE_VIDEO_FIELD1 0x80 +#define EAV_ACTIVE_VIDEO_FIELD1 0x90 -#define SAV_ACTIVE_VIDEO_FIELD2 0xC0 -#define EAV_ACTIVE_VIDEO_FIELD2 0xD0 +#define SAV_ACTIVE_VIDEO_FIELD2 0xc0 +#define EAV_ACTIVE_VIDEO_FIELD2 0xd0 -#define SAV_VBLANK_FIELD1 0xA0 -#define EAV_VBLANK_FIELD1 0xB0 +#define SAV_VBLANK_FIELD1 0xa0 +#define EAV_VBLANK_FIELD1 0xb0 -#define SAV_VBLANK_FIELD2 0xE0 -#define EAV_VBLANK_FIELD2 0xF0 +#define SAV_VBLANK_FIELD2 0xe0 +#define EAV_VBLANK_FIELD2 0xf0 -#define SAV_VBI_FIELD1 0x20 -#define EAV_VBI_FIELD1 0x30 +#define SAV_VBI_FIELD1 0x20 +#define EAV_VBI_FIELD1 0x30 -#define SAV_VBI_FIELD2 0x60 -#define EAV_VBI_FIELD2 0x70 +#define SAV_VBI_FIELD2 0x60 +#define EAV_VBI_FIELD2 0x70 /*****************************************************************************/ /* Audio ADC Registers */ -#define CH_PWR_CTRL1 0x0000000E -#define CH_PWR_CTRL2 0x0000000F +#define CH_PWR_CTRL1 0x0000000e +#define CH_PWR_CTRL2 0x0000000f /*****************************************************************************/ #define HOST_REG1 0x000 @@ -74,11 +74,11 @@ #define TS1_PIN_CTL1 0x8 /*****************************************************************************/ -#define FLD_CLK_IN_EN 0x80 -#define FLD_XTAL_CTRL 0x70 -#define FLD_BB_CLK_MODE 0x0C -#define FLD_REF_DIV_PLL 0x02 -#define FLD_REF_SEL_PLL1 0x01 +#define FLD_CLK_IN_EN 0x80 +#define FLD_XTAL_CTRL 0x70 +#define FLD_BB_CLK_MODE 0x0C +#define FLD_REF_DIV_PLL 0x02 +#define FLD_REF_SEL_PLL1 0x01 /*****************************************************************************/ #define CHIP_CTRL 0x100 @@ -89,16 +89,16 @@ #define FLD_DUAL_MODE_ADC2 0x00040000 #define FLD_SIF_EN 0x00020000 #define FLD_SOFT_RST 0x00010000 -#define FLD_DEVICE_ID 0x0000FFFF +#define FLD_DEVICE_ID 0x0000ffff /*****************************************************************************/ #define AFE_CTRL 0x104 #define AFE_CTRL_C2HH_SRC_CTRL 0x104 -#define FLD_DIF_OUT_SEL 0xC0000000 -#define FLD_AUX_PLL_CLK_ALT_SEL 0x3C000000 +#define FLD_DIF_OUT_SEL 0xc0000000 +#define FLD_AUX_PLL_CLK_ALT_SEL 0x3c000000 #define FLD_UV_ORDER_MODE 0x02000000 #define FLD_FUNC_MODE 0x01800000 -#define FLD_ROT1_PHASE_CTL 0x007F8000 +#define FLD_ROT1_PHASE_CTL 0x007f8000 #define FLD_AUD_IN_SEL 0x00004000 #define FLD_LUMA_IN_SEL 0x00002000 #define FLD_CHROMA_IN_SEL 0x00001000 @@ -118,16 +118,16 @@ /*****************************************************************************/ #define DC_CTRL1 0x108 /* reserve [31:30] */ -#define FLD_CLAMP_LVL_CH1 0x3FFF8000 -#define FLD_CLAMP_LVL_CH2 0x00007FFF +#define FLD_CLAMP_LVL_CH1 0x3fff8000 +#define FLD_CLAMP_LVL_CH2 0x00007fff /*****************************************************************************/ /*****************************************************************************/ #define DC_CTRL2 0x10c /* reserve [31:28] */ -#define FLD_CLAMP_LVL_CH3 0x00FFFE00 -#define FLD_CLAMP_WIND_LENTH 0x000001E0 -#define FLD_C2HH_SAT_MIN 0x0000001E +#define FLD_CLAMP_LVL_CH3 0x00fffe00 +#define FLD_CLAMP_WIND_LENTH 0x000001e0 +#define FLD_C2HH_SAT_MIN 0x0000001e #define FLD_FLT_BYP_SEL 0x00000001 /*****************************************************************************/ @@ -135,25 +135,25 @@ #define DC_CTRL3 0x110 /* reserve [31:16] */ #define FLD_ERR_GAIN_CTL 0x00070000 -#define FLD_LPF_MIN 0x0000FFFF +#define FLD_LPF_MIN 0x0000ffff /*****************************************************************************/ /*****************************************************************************/ #define DC_CTRL4 0x114 /* reserve [31:31] */ -#define FLD_INTG_CH1 0x7FFFFFFF +#define FLD_INTG_CH1 0x7fffffff /*****************************************************************************/ /*****************************************************************************/ #define DC_CTRL5 0x118 /* reserve [31:31] */ -#define FLD_INTG_CH2 0x7FFFFFFF +#define FLD_INTG_CH2 0x7fffffff /*****************************************************************************/ /*****************************************************************************/ #define DC_CTRL6 0x11c /* reserve [31:31] */ -#define FLD_INTG_CH3 0x7FFFFFFF +#define FLD_INTG_CH3 0x7fffffff /*****************************************************************************/ /*****************************************************************************/ @@ -182,30 +182,30 @@ #define FLD_I2S_PORT_DIR 0x00000080 #define FLD_I2S_OUT_SRC 0x00000040 #define FLD_AUD_CHAN3_SRC 0x00000030 -#define FLD_AUD_CHAN2_SRC 0x0000000C +#define FLD_AUD_CHAN2_SRC 0x0000000c #define FLD_AUD_CHAN1_SRC 0x00000003 /*****************************************************************************/ #define AUD_LOCK1 0x128 -#define FLD_AUD_LOCK_KI_SHIFT 0xC0000000 +#define FLD_AUD_LOCK_KI_SHIFT 0xc0000000 #define FLD_AUD_LOCK_KD_SHIFT 0x30000000 /* Reserved [27:25] */ #define FLD_EN_AV_LOCK 0x01000000 -#define FLD_VID_COUNT 0x00FFFFFF +#define FLD_VID_COUNT 0x00ffffff /*****************************************************************************/ -#define AUD_LOCK2 0x12C -#define FLD_AUD_LOCK_KI_MULT 0xF0000000 +#define AUD_LOCK2 0x12c +#define FLD_AUD_LOCK_KI_MULT 0xf0000000 #define FLD_AUD_LOCK_KD_MULT 0x0F000000 /* Reserved [23:22] */ #define FLD_AUD_LOCK_FREQ_SHIFT 0x00300000 -#define FLD_AUD_COUNT 0x000FFFFF +#define FLD_AUD_COUNT 0x000fffff /*****************************************************************************/ #define AFE_DIAG_CTRL1 0x134 /* Reserved [31:16] */ -#define FLD_CUV_DLY_LENGTH 0x0000FF00 -#define FLD_YC_DLY_LENGTH 0x000000FF +#define FLD_CUV_DLY_LENGTH 0x0000ff00 +#define FLD_YC_DLY_LENGTH 0x000000ff /*****************************************************************************/ /* Poalris redefine */ @@ -218,18 +218,18 @@ #define FLD_COL_CLAMP_DIS_CH2 0x00200000 #define FLD_COL_CLAMP_DIS_CH3 0x00100000 -#define TEST_CTRL1 0x144 +#define TEST_CTRL1 0x144 /* Reserved [31:29] */ -#define FLD_LBIST_EN 0x10000000 +#define FLD_LBIST_EN 0x10000000 /* Reserved [27:10] */ -#define FLD_FI_BIST_INTR_R 0x0000200 -#define FLD_FI_BIST_INTR_L 0x0000100 -#define FLD_BIST_FAIL_AUD_PLL 0x0000080 -#define FLD_BIST_INTR_AUD_PLL 0x0000040 -#define FLD_BIST_FAIL_VID_PLL 0x0000020 -#define FLD_BIST_INTR_VID_PLL 0x0000010 +#define FLD_FI_BIST_INTR_R 0x0000200 +#define FLD_FI_BIST_INTR_L 0x0000100 +#define FLD_BIST_FAIL_AUD_PLL 0x0000080 +#define FLD_BIST_INTR_AUD_PLL 0x0000040 +#define FLD_BIST_FAIL_VID_PLL 0x0000020 +#define FLD_BIST_INTR_VID_PLL 0x0000010 /* Reserved [3:1] */ -#define FLD_CIR_TEST_DIS 0x00000001 +#define FLD_CIR_TEST_DIS 0x00000001 /*****************************************************************************/ #define TEST_CTRL2 0x148 @@ -237,7 +237,7 @@ #define FLD_ISO_CTL_SEL 0x40000000 #define FLD_ISO_CTL_EN 0x20000000 #define FLD_BIST_DEBUGZ 0x10000000 -#define FLD_AUD_BIST_TEST_H 0x0F000000 +#define FLD_AUD_BIST_TEST_H 0x0f000000 /* Reserved [23:22] */ #define FLD_FLTRN_BIST_TEST_H 0x00020000 #define FLD_VID_BIST_TEST_H 0x00010000 @@ -248,11 +248,11 @@ /* Reserved [11:0] */ /*****************************************************************************/ -#define BIST_STAT 0x14C -#define FLD_AUD_BIST_FAIL_H 0xFFF00000 +#define BIST_STAT 0x14c +#define FLD_AUD_BIST_FAIL_H 0xfff00000 #define FLD_FLTRN_BIST_FAIL_H 0x00180000 #define FLD_VID_BIST_FAIL_H 0x00070000 -#define FLD_AUD_BIST_TST_DONE 0x0000FFF0 +#define FLD_AUD_BIST_TST_DONE 0x0000fff0 #define FLD_FLTRN_BIST_TST_DONE 0x00000008 #define FLD_VID_BIST_TST_DONE 0x00000007 @@ -266,7 +266,7 @@ #define FLD_AFD_FORCE_PAL 0x04000000 #define FLD_AFD_PALM_SEL 0x03000000 #define FLD_CKILL_MODE 0x00300000 -#define FLD_COMB_NOTCH_MODE 0x00c00000 /* bit[19:18] */ +#define FLD_COMB_NOTCH_MODE 0x00c00000 /* bit[19:18] */ #define FLD_CLR_LOCK_STAT 0x00020000 #define FLD_FAST_LOCK_MD 0x00010000 #define FLD_WCEN 0x00008000 @@ -280,11 +280,11 @@ #define FLD_AFD_PAL_SEL 0x00000040 #define FLD_ACFG_DIS 0x00000020 #define FLD_SQ_PIXEL 0x00000010 -#define FLD_VID_FMT_SEL 0x0000000F +#define FLD_VID_FMT_SEL 0x0000000f /*****************************************************************************/ #define OUT_CTRL1 0x404 -#define FLD_POLAR 0x7F000000 +#define FLD_POLAR 0x7f000000 /* Reserved [23] */ #define FLD_RND_MODE 0x00600000 #define FLD_VIPCLAMP_EN 0x00100000 @@ -292,7 +292,7 @@ #define FLD_VIP_OPT_AL 0x00040000 #define FLD_IDID0_SOURCE 0x00020000 #define FLD_DCMODE 0x00010000 -#define FLD_CLK_GATING 0x0000C000 +#define FLD_CLK_GATING 0x0000c000 #define FLD_CLK_INVERT 0x00002000 #define FLD_HSFMT 0x00001000 #define FLD_VALIDFMT 0x00000800 @@ -309,20 +309,20 @@ /*****************************************************************************/ #define OUT_CTRL2 0x408 -#define FLD_AUD_GRP 0xC0000000 +#define FLD_AUD_GRP 0xc0000000 #define FLD_SAMPLE_RATE 0x30000000 #define FLD_AUD_ANC_EN 0x08000000 #define FLD_EN_C 0x04000000 #define FLD_EN_B 0x02000000 #define FLD_EN_A 0x01000000 /* Reserved [23:20] */ -#define FLD_IDID1_LSB 0x000C0000 +#define FLD_IDID1_LSB 0x000c0000 #define FLD_IDID0_LSB 0x00030000 -#define FLD_IDID1_MSB 0x0000FF00 -#define FLD_IDID0_MSB 0x000000FF +#define FLD_IDID1_MSB 0x0000ff00 +#define FLD_IDID0_MSB 0x000000ff /*****************************************************************************/ -#define GEN_STAT 0x40C +#define GEN_STAT 0x40c #define FLD_VCR_DETECT 0x00800000 #define FLD_SPECIAL_PLAY_N 0x00400000 #define FLD_VPRES 0x00200000 @@ -335,7 +335,7 @@ #define FLD_SRC_FIFO_UFLOW 0x00004000 #define FLD_SRC_FIFO_OFLOW 0x00002000 #define FLD_FIELD 0x00001000 -#define FLD_AFD_FMT_STAT 0x00000F00 +#define FLD_AFD_FMT_STAT 0x00000f00 #define FLD_MV_TYPE2_PAIR 0x00000080 #define FLD_MV_T3CS 0x00000040 #define FLD_MV_CS 0x00000020 @@ -383,27 +383,27 @@ #define BRIGHTNESS_CTRL_BYTE 0x414 #define CONTRAST_CTRL_BYTE 0x415 #define LUMA_CTRL_BYTE_3 0x416 -#define FLD_LUMA_CORE_SEL 0x00C00000 +#define FLD_LUMA_CORE_SEL 0x00c00000 #define FLD_RANGE 0x00300000 /* Reserved [19] */ #define FLD_PEAK_EN 0x00040000 #define FLD_PEAK_SEL 0x00030000 -#define FLD_CNTRST 0x0000FF00 -#define FLD_BRITE 0x000000FF +#define FLD_CNTRST 0x0000ff00 +#define FLD_BRITE 0x000000ff /*****************************************************************************/ #define HSCALE_CTRL 0x418 #define FLD_HFILT 0x03000000 -#define FLD_HSCALE 0x00FFFFFF +#define FLD_HSCALE 0x00ffffff /*****************************************************************************/ -#define VSCALE_CTRL 0x41C +#define VSCALE_CTRL 0x41c #define FLD_LINE_AVG_DIS 0x01000000 /* Reserved [23:20] */ #define FLD_VS_INTRLACE 0x00080000 #define FLD_VFILT 0x00070000 /* Reserved [15:13] */ -#define FLD_VSCALE 0x00001FFF +#define FLD_VSCALE 0x00001fff /*****************************************************************************/ #define CHROMA_CTRL 0x420 @@ -411,76 +411,76 @@ #define VSAT_CTRL_BYTE 0x421 #define HUE_CTRL_BYTE 0x422 #define FLD_C_LPF_EN 0x20000000 -#define FLD_CHR_DELAY 0x1C000000 +#define FLD_CHR_DELAY 0x1c000000 #define FLD_C_CORE_SEL 0x03000000 -#define FLD_HUE 0x00FF0000 -#define FLD_VSAT 0x0000FF00 -#define FLD_USAT 0x000000FF +#define FLD_HUE 0x00ff0000 +#define FLD_VSAT 0x0000ff00 +#define FLD_USAT 0x000000ff /*****************************************************************************/ #define VBI_LINE_CTRL1 0x424 -#define FLD_VBI_MD_LINE4 0xFF000000 -#define FLD_VBI_MD_LINE3 0x00FF0000 -#define FLD_VBI_MD_LINE2 0x0000FF00 -#define FLD_VBI_MD_LINE1 0x000000FF +#define FLD_VBI_MD_LINE4 0xff000000 +#define FLD_VBI_MD_LINE3 0x00ff0000 +#define FLD_VBI_MD_LINE2 0x0000ff00 +#define FLD_VBI_MD_LINE1 0x000000ff /*****************************************************************************/ #define VBI_LINE_CTRL2 0x428 -#define FLD_VBI_MD_LINE8 0xFF000000 -#define FLD_VBI_MD_LINE7 0x00FF0000 -#define FLD_VBI_MD_LINE6 0x0000FF00 -#define FLD_VBI_MD_LINE5 0x000000FF +#define FLD_VBI_MD_LINE8 0xff000000 +#define FLD_VBI_MD_LINE7 0x00ff0000 +#define FLD_VBI_MD_LINE6 0x0000ff00 +#define FLD_VBI_MD_LINE5 0x000000ff /*****************************************************************************/ -#define VBI_LINE_CTRL3 0x42C -#define FLD_VBI_MD_LINE12 0xFF000000 -#define FLD_VBI_MD_LINE11 0x00FF0000 -#define FLD_VBI_MD_LINE10 0x0000FF00 -#define FLD_VBI_MD_LINE9 0x000000FF +#define VBI_LINE_CTRL3 0x42c +#define FLD_VBI_MD_LINE12 0xff000000 +#define FLD_VBI_MD_LINE11 0x00ff0000 +#define FLD_VBI_MD_LINE10 0x0000ff00 +#define FLD_VBI_MD_LINE9 0x000000ff /*****************************************************************************/ #define VBI_LINE_CTRL4 0x430 -#define FLD_VBI_MD_LINE16 0xFF000000 -#define FLD_VBI_MD_LINE15 0x00FF0000 -#define FLD_VBI_MD_LINE14 0x0000FF00 -#define FLD_VBI_MD_LINE13 0x000000FF +#define FLD_VBI_MD_LINE16 0xff000000 +#define FLD_VBI_MD_LINE15 0x00ff0000 +#define FLD_VBI_MD_LINE14 0x0000ff00 +#define FLD_VBI_MD_LINE13 0x000000ff /*****************************************************************************/ #define VBI_LINE_CTRL5 0x434 -#define FLD_VBI_MD_LINE17 0x000000FF +#define FLD_VBI_MD_LINE17 0x000000ff /*****************************************************************************/ #define VBI_FC_CFG 0x438 -#define FLD_FC_ALT2 0xFF000000 -#define FLD_FC_ALT1 0x00FF0000 -#define FLD_FC_ALT2_TYPE 0x0000F000 -#define FLD_FC_ALT1_TYPE 0x00000F00 +#define FLD_FC_ALT2 0xff000000 +#define FLD_FC_ALT1 0x00ff0000 +#define FLD_FC_ALT2_TYPE 0x0000f000 +#define FLD_FC_ALT1_TYPE 0x00000f00 /* Reserved [7:1] */ #define FLD_FC_SEARCH_MODE 0x00000001 /*****************************************************************************/ -#define VBI_MISC_CFG1 0x43C -#define FLD_TTX_PKTADRU 0xFFF00000 -#define FLD_TTX_PKTADRL 0x000FFF00 +#define VBI_MISC_CFG1 0x43c +#define FLD_TTX_PKTADRU 0xfff00000 +#define FLD_TTX_PKTADRL 0x000fff00 /* Reserved [7:6] */ #define FLD_MOJI_PACK_DIS 0x00000020 #define FLD_VPS_DEC_DIS 0x00000010 -#define FLD_CRI_MARG_SCALE 0x0000000C +#define FLD_CRI_MARG_SCALE 0x0000000c #define FLD_EDGE_RESYNC_EN 0x00000002 #define FLD_ADAPT_SLICE_DIS 0x00000001 /*****************************************************************************/ #define VBI_MISC_CFG2 0x440 -#define FLD_HAMMING_TYPE 0x0F000000 +#define FLD_HAMMING_TYPE 0x0f000000 /* Reserved [23:20] */ #define FLD_WSS_FIFO_RST 0x00080000 #define FLD_GS2_FIFO_RST 0x00040000 #define FLD_GS1_FIFO_RST 0x00020000 #define FLD_CC_FIFO_RST 0x00010000 /* Reserved [15:12] */ -#define FLD_VBI3_SDID 0x00000F00 -#define FLD_VBI2_SDID 0x000000F0 -#define FLD_VBI1_SDID 0x0000000F +#define FLD_VBI3_SDID 0x00000f00 +#define FLD_VBI2_SDID 0x000000f0 +#define FLD_VBI1_SDID 0x0000000f /*****************************************************************************/ #define VBI_PAY1 0x444 @@ -491,95 +491,95 @@ /*****************************************************************************/ #define VBI_PAY2 0x448 -#define FLD_WSS_FIFO_DAT 0xFF000000 -#define FLD_WSS_STAT 0x00FF0000 -#define FLD_GS2_FIFO_DAT 0x0000FF00 -#define FLD_GS2_STAT 0x000000FF +#define FLD_WSS_FIFO_DAT 0xff000000 +#define FLD_WSS_STAT 0x00ff0000 +#define FLD_GS2_FIFO_DAT 0x0000ff00 +#define FLD_GS2_STAT 0x000000ff /*****************************************************************************/ -#define VBI_CUST1_CFG1 0x44C +#define VBI_CUST1_CFG1 0x44c /* Reserved [31] */ -#define FLD_VBI1_CRIWIN 0x7F000000 -#define FLD_VBI1_SLICE_DIST 0x00F00000 -#define FLD_VBI1_BITINC 0x000FFF00 -#define FLD_VBI1_HDELAY 0x000000FF +#define FLD_VBI1_CRIWIN 0x7f000000 +#define FLD_VBI1_SLICE_DIST 0x00f00000 +#define FLD_VBI1_BITINC 0x000fff00 +#define FLD_VBI1_HDELAY 0x000000ff /*****************************************************************************/ #define VBI_CUST1_CFG2 0x450 -#define FLD_VBI1_FC_LENGTH 0x1F000000 -#define FLD_VBI1_FRAME_CODE 0x00FFFFFF +#define FLD_VBI1_FC_LENGTH 0x1f000000 +#define FLD_VBI1_FRAME_CODE 0x00ffffff /*****************************************************************************/ #define VBI_CUST1_CFG3 0x454 #define FLD_VBI1_HAM_EN 0x80000000 #define FLD_VBI1_FIFO_MODE 0x70000000 -#define FLD_VBI1_FORMAT_TYPE 0x0F000000 -#define FLD_VBI1_PAYLD_LENGTH 0x00FF0000 -#define FLD_VBI1_CRI_LENGTH 0x0000F000 -#define FLD_VBI1_CRI_MARGIN 0x00000F00 -#define FLD_VBI1_CRI_TIME 0x000000FF +#define FLD_VBI1_FORMAT_TYPE 0x0f000000 +#define FLD_VBI1_PAYLD_LENGTH 0x00ff0000 +#define FLD_VBI1_CRI_LENGTH 0x0000f000 +#define FLD_VBI1_CRI_MARGIN 0x00000f00 +#define FLD_VBI1_CRI_TIME 0x000000ff /*****************************************************************************/ #define VBI_CUST2_CFG1 0x458 /* Reserved [31] */ -#define FLD_VBI2_CRIWIN 0x7F000000 -#define FLD_VBI2_SLICE_DIST 0x00F00000 -#define FLD_VBI2_BITINC 0x000FFF00 -#define FLD_VBI2_HDELAY 0x000000FF +#define FLD_VBI2_CRIWIN 0x7f000000 +#define FLD_VBI2_SLICE_DIST 0x00f00000 +#define FLD_VBI2_BITINC 0x000fff00 +#define FLD_VBI2_HDELAY 0x000000ff /*****************************************************************************/ -#define VBI_CUST2_CFG2 0x45C -#define FLD_VBI2_FC_LENGTH 0x1F000000 -#define FLD_VBI2_FRAME_CODE 0x00FFFFFF +#define VBI_CUST2_CFG2 0x45c +#define FLD_VBI2_FC_LENGTH 0x1f000000 +#define FLD_VBI2_FRAME_CODE 0x00ffffff /*****************************************************************************/ #define VBI_CUST2_CFG3 0x460 #define FLD_VBI2_HAM_EN 0x80000000 #define FLD_VBI2_FIFO_MODE 0x70000000 -#define FLD_VBI2_FORMAT_TYPE 0x0F000000 -#define FLD_VBI2_PAYLD_LENGTH 0x00FF0000 -#define FLD_VBI2_CRI_LENGTH 0x0000F000 -#define FLD_VBI2_CRI_MARGIN 0x00000F00 -#define FLD_VBI2_CRI_TIME 0x000000FF +#define FLD_VBI2_FORMAT_TYPE 0x0f000000 +#define FLD_VBI2_PAYLD_LENGTH 0x00ff0000 +#define FLD_VBI2_CRI_LENGTH 0x0000f000 +#define FLD_VBI2_CRI_MARGIN 0x00000f00 +#define FLD_VBI2_CRI_TIME 0x000000ff /*****************************************************************************/ #define VBI_CUST3_CFG1 0x464 /* Reserved [31] */ -#define FLD_VBI3_CRIWIN 0x7F000000 -#define FLD_VBI3_SLICE_DIST 0x00F00000 -#define FLD_VBI3_BITINC 0x000FFF00 -#define FLD_VBI3_HDELAY 0x000000FF +#define FLD_VBI3_CRIWIN 0x7f000000 +#define FLD_VBI3_SLICE_DIST 0x00f00000 +#define FLD_VBI3_BITINC 0x000fff00 +#define FLD_VBI3_HDELAY 0x000000ff /*****************************************************************************/ #define VBI_CUST3_CFG2 0x468 -#define FLD_VBI3_FC_LENGTH 0x1F000000 -#define FLD_VBI3_FRAME_CODE 0x00FFFFFF +#define FLD_VBI3_FC_LENGTH 0x1f000000 +#define FLD_VBI3_FRAME_CODE 0x00ffffff /*****************************************************************************/ -#define VBI_CUST3_CFG3 0x46C +#define VBI_CUST3_CFG3 0x46c #define FLD_VBI3_HAM_EN 0x80000000 #define FLD_VBI3_FIFO_MODE 0x70000000 -#define FLD_VBI3_FORMAT_TYPE 0x0F000000 -#define FLD_VBI3_PAYLD_LENGTH 0x00FF0000 -#define FLD_VBI3_CRI_LENGTH 0x0000F000 -#define FLD_VBI3_CRI_MARGIN 0x00000F00 -#define FLD_VBI3_CRI_TIME 0x000000FF +#define FLD_VBI3_FORMAT_TYPE 0x0f000000 +#define FLD_VBI3_PAYLD_LENGTH 0x00ff0000 +#define FLD_VBI3_CRI_LENGTH 0x0000f000 +#define FLD_VBI3_CRI_MARGIN 0x00000f00 +#define FLD_VBI3_CRI_TIME 0x000000ff /*****************************************************************************/ #define HORIZ_TIM_CTRL 0x470 -#define FLD_BGDEL_CNT 0xFF000000 +#define FLD_BGDEL_CNT 0xff000000 /* Reserved [23:22] */ -#define FLD_HACTIVE_CNT 0x003FF000 +#define FLD_HACTIVE_CNT 0x003ff000 /* Reserved [11:10] */ -#define FLD_HBLANK_CNT 0x000003FF +#define FLD_HBLANK_CNT 0x000003ff /*****************************************************************************/ #define VERT_TIM_CTRL 0x474 -#define FLD_V656BLANK_CNT 0xFF000000 +#define FLD_V656BLANK_CNT 0xff000000 /* Reserved [23:22] */ -#define FLD_VACTIVE_CNT 0x003FF000 +#define FLD_VACTIVE_CNT 0x003ff000 /* Reserved [11:10] */ -#define FLD_VBLANK_CNT 0x000003FF +#define FLD_VBLANK_CNT 0x000003ff /*****************************************************************************/ #define SRC_COMB_CFG 0x478 @@ -591,36 +591,36 @@ #define FLD_LCOMB_3LN_EN 0x04000000 #define FLD_LCOMB_2LN_EN 0x02000000 #define FLD_LCOMB_3D_EN 0x01000000 -#define FLD_LUMA_LPF_SEL 0x00C00000 +#define FLD_LUMA_LPF_SEL 0x00c00000 #define FLD_UV_LPF_SEL 0x00300000 -#define FLD_BLEND_SLOPE 0x000F0000 +#define FLD_BLEND_SLOPE 0x000f0000 #define FLD_CCOMB_REDUCE_EN 0x00008000 /* Reserved [14:10] */ -#define FLD_SRC_DECIM_RATIO 0x000003FF +#define FLD_SRC_DECIM_RATIO 0x000003ff /*****************************************************************************/ -#define CHROMA_VBIOFF_CFG 0x47C -#define FLD_VBI_VOFFSET 0x1F000000 +#define CHROMA_VBIOFF_CFG 0x47c +#define FLD_VBI_VOFFSET 0x1f000000 /* Reserved [23:20] */ -#define FLD_SC_STEP 0x000FFFFF +#define FLD_SC_STEP 0x000fffff /*****************************************************************************/ #define FIELD_COUNT 0x480 -#define FLD_FIELD_COUNT_FLD 0x000003FF +#define FLD_FIELD_COUNT_FLD 0x000003ff /*****************************************************************************/ #define MISC_TIM_CTRL 0x484 -#define FLD_DEBOUNCE_COUNT 0xC0000000 +#define FLD_DEBOUNCE_COUNT 0xc0000000 #define FLD_VT_LINE_CNT_HYST 0x30000000 /* Reserved [27] */ -#define FLD_AFD_STAT 0x07FF0000 +#define FLD_AFD_STAT 0x07ff0000 #define FLD_VPRES_VERT_EN 0x00008000 /* Reserved [14:12] */ #define FLD_HR32 0x00000800 #define FLD_TDALGN 0x00000400 #define FLD_TDFIELD 0x00000200 /* Reserved [8:6] */ -#define FLD_TEMPDEC 0x0000003F +#define FLD_TEMPDEC 0x0000003f /*****************************************************************************/ #define DFE_CTRL1 0x488 @@ -632,33 +632,33 @@ #define FLD_CLAMP_LEVEL 0x07000000 /* Reserved [23:22] */ #define FLD_CLAMP_SKIP_CNT 0x00300000 -#define FLD_AGC_GAIN 0x000FFF00 +#define FLD_AGC_GAIN 0x000fff00 /* Reserved [7:6] */ -#define FLD_VGA_GAIN 0x0000003F +#define FLD_VGA_GAIN 0x0000003f /*****************************************************************************/ -#define DFE_CTRL2 0x48C -#define FLD_VGA_ACQUIRE_RANGE 0x00FF0000 -#define FLD_VGA_TRACK_RANGE 0x0000FF00 -#define FLD_VGA_SYNC 0x000000FF +#define DFE_CTRL2 0x48c +#define FLD_VGA_ACQUIRE_RANGE 0x00ff0000 +#define FLD_VGA_TRACK_RANGE 0x0000ff00 +#define FLD_VGA_SYNC 0x000000ff /*****************************************************************************/ #define DFE_CTRL3 0x490 -#define FLD_BP_PERCENT 0xFF000000 -#define FLD_DFT_THRESHOLD 0x00FF0000 +#define FLD_BP_PERCENT 0xff000000 +#define FLD_DFT_THRESHOLD 0x00ff0000 /* Reserved [15:12] */ #define FLD_SYNC_WIDTH_SEL 0x00000600 #define FLD_BP_LOOP_GAIN 0x00000300 -#define FLD_SYNC_LOOP_GAIN 0x000000C0 +#define FLD_SYNC_LOOP_GAIN 0x000000c0 /* Reserved [5:4] */ -#define FLD_AGC_LOOP_GAIN 0x0000000C +#define FLD_AGC_LOOP_GAIN 0x0000000c #define FLD_DCC_LOOP_GAIN 0x00000003 /*****************************************************************************/ #define PLL_CTRL 0x494 -#define FLD_PLL_KD 0xFF000000 -#define FLD_PLL_KI 0x00FF0000 -#define FLD_PLL_MAX_OFFSET 0x0000FFFF +#define FLD_PLL_KD 0xff000000 +#define FLD_PLL_KI 0x00ff0000 +#define FLD_PLL_MAX_OFFSET 0x0000ffff /*****************************************************************************/ #define HTL_CTRL 0x498 @@ -667,29 +667,29 @@ #define FLD_MAN_FAST_LOCK 0x00040000 #define FLD_HTL_15K_EN 0x00020000 #define FLD_HTL_500K_EN 0x00010000 -#define FLD_HTL_KD 0x0000FF00 -#define FLD_HTL_KI 0x000000FF +#define FLD_HTL_KD 0x0000ff00 +#define FLD_HTL_KI 0x000000ff /*****************************************************************************/ -#define COMB_CTRL 0x49C -#define FLD_COMB_PHASE_LIMIT 0xFF000000 -#define FLD_CCOMB_ERR_LIMIT 0x00FF0000 -#define FLD_LUMA_THRESHOLD 0x0000FF00 -#define FLD_LCOMB_ERR_LIMIT 0x000000FF +#define COMB_CTRL 0x49c +#define FLD_COMB_PHASE_LIMIT 0xff000000 +#define FLD_CCOMB_ERR_LIMIT 0x00ff0000 +#define FLD_LUMA_THRESHOLD 0x0000ff00 +#define FLD_LCOMB_ERR_LIMIT 0x000000ff /*****************************************************************************/ -#define CRUSH_CTRL 0x4A0 +#define CRUSH_CTRL 0x4a0 #define FLD_WTW_EN 0x00400000 #define FLD_CRUSH_FREQ 0x00200000 #define FLD_MAJ_SEL_EN 0x00100000 -#define FLD_MAJ_SEL 0x000C0000 +#define FLD_MAJ_SEL 0x000c0000 /* Reserved [17:15] */ -#define FLD_SYNC_TIP_REDUCE 0x00007E00 +#define FLD_SYNC_TIP_REDUCE 0x00007e00 /* Reserved [8:6] */ -#define FLD_SYNC_TIP_INC 0x0000003F +#define FLD_SYNC_TIP_INC 0x0000003f /*****************************************************************************/ -#define SOFT_RST_CTRL 0x4A4 +#define SOFT_RST_CTRL 0x4a4 #define FLD_VD_SOFT_RST 0x00008000 /* Reserved [14:12] */ #define FLD_REG_RST_MSK 0x00000800 @@ -706,22 +706,22 @@ /* Reserved [0] */ /*****************************************************************************/ -#define MV_DT_CTRL1 0x4A8 +#define MV_DT_CTRL1 0x4a8 /* Reserved [31:29] */ -#define FLD_PSP_STOP_LINE 0x1F000000 +#define FLD_PSP_STOP_LINE 0x1f000000 /* Reserved [23:21] */ -#define FLD_PSP_STRT_LINE 0x001F0000 +#define FLD_PSP_STRT_LINE 0x001f0000 /* Reserved [15] */ -#define FLD_PSP_LLIMW 0x00007F00 +#define FLD_PSP_LLIMW 0x00007f00 /* Reserved [7] */ -#define FLD_PSP_ULIMW 0x0000007F +#define FLD_PSP_ULIMW 0x0000007f /*****************************************************************************/ -#define MV_DT_CTRL2 0x4AC -#define FLD_CS_STOPWIN 0xFF000000 -#define FLD_CS_STRTWIN 0x00FF0000 -#define FLD_CS_WIDTH 0x0000FF00 -#define FLD_PSP_SPEC_VAL 0x000000FF +#define MV_DT_CTRL2 0x4aC +#define FLD_CS_STOPWIN 0xff000000 +#define FLD_CS_STRTWIN 0x00ff0000 +#define FLD_CS_WIDTH 0x0000ff00 +#define FLD_PSP_SPEC_VAL 0x000000ff /*****************************************************************************/ #define MV_DT_CTRL3 0x4B0 @@ -733,47 +733,47 @@ #define FLD_CS_ATHRESH_SEL 0x04000000 #define FLD_PSP_SPEC_SEL 0x02000000 #define FLD_PSP_LINES_SEL 0x01000000 -#define FLD_FIELD_CNT 0x00F00000 -#define FLD_CS_TYPE2_CNT 0x000FC000 -#define FLD_CS_LINE_CNT 0x00003F00 -#define FLD_CS_ATHRESH_LEV 0x000000FF +#define FLD_FIELD_CNT 0x00f00000 +#define FLD_CS_TYPE2_CNT 0x000fc000 +#define FLD_CS_LINE_CNT 0x00003f00 +#define FLD_CS_ATHRESH_LEV 0x000000ff /*****************************************************************************/ -#define CHIP_VERSION 0x4B4 +#define CHIP_VERSION 0x4b4 /* Cx231xx redefine */ -#define VERSION 0x4B4 -#define FLD_REV_ID 0x000000FF +#define VERSION 0x4b4 +#define FLD_REV_ID 0x000000ff /*****************************************************************************/ -#define MISC_DIAG_CTRL 0x4B8 +#define MISC_DIAG_CTRL 0x4b8 /* Reserved [31:24] */ -#define FLD_SC_CONVERGE_THRESH 0x00FF0000 -#define FLD_CCOMB_ERR_LIMIT_3D 0x0000FF00 -#define FLD_LCOMB_ERR_LIMIT_3D 0x000000FF +#define FLD_SC_CONVERGE_THRESH 0x00ff0000 +#define FLD_CCOMB_ERR_LIMIT_3D 0x0000ff00 +#define FLD_LCOMB_ERR_LIMIT_3D 0x000000ff /*****************************************************************************/ -#define VBI_PASS_CTRL 0x4BC +#define VBI_PASS_CTRL 0x4bc #define FLD_VBI_PASS_MD 0x00200000 #define FLD_VBI_SETUP_DIS 0x00100000 -#define FLD_PASS_LINE_CTRL 0x000FFFFF +#define FLD_PASS_LINE_CTRL 0x000fffff /*****************************************************************************/ /* Cx231xx redefine */ #define VCR_DET_CTRL 0x4c0 #define FLD_EN_FIELD_PHASE_DET 0x80000000 #define FLD_EN_HEAD_SW_DET 0x40000000 -#define FLD_FIELD_PHASE_LENGTH 0x01FF0000 +#define FLD_FIELD_PHASE_LENGTH 0x01ff0000 /* Reserved [29:25] */ -#define FLD_FIELD_PHASE_DELAY 0x0000FF00 -#define FLD_FIELD_PHASE_LIMIT 0x000000F0 -#define FLD_HEAD_SW_DET_LIMIT 0x0000000F +#define FLD_FIELD_PHASE_DELAY 0x0000ff00 +#define FLD_FIELD_PHASE_LIMIT 0x000000f0 +#define FLD_HEAD_SW_DET_LIMIT 0x0000000f /*****************************************************************************/ #define DL_CTL 0x800 -#define DL_CTL_ADDRESS_LOW 0x800 /* Byte 1 in DL_CTL */ -#define DL_CTL_ADDRESS_HIGH 0x801 /* Byte 2 in DL_CTL */ -#define DL_CTL_DATA 0x802 /* Byte 3 in DL_CTL */ -#define DL_CTL_CONTROL 0x803 /* Byte 4 in DL_CTL */ +#define DL_CTL_ADDRESS_LOW 0x800 /* Byte 1 in DL_CTL */ +#define DL_CTL_ADDRESS_HIGH 0x801 /* Byte 2 in DL_CTL */ +#define DL_CTL_DATA 0x802 /* Byte 3 in DL_CTL */ +#define DL_CTL_CONTROL 0x803 /* Byte 4 in DL_CTL */ /* Reserved [31:5] */ #define FLD_START_8051 0x10000000 #define FLD_DL_ENABLE 0x08000000 @@ -782,28 +782,28 @@ /*****************************************************************************/ #define STD_DET_STATUS 0x804 -#define FLD_SPARE_STATUS1 0xFF000000 -#define FLD_SPARE_STATUS0 0x00FF0000 -#define FLD_MOD_DET_STATUS1 0x0000FF00 -#define FLD_MOD_DET_STATUS0 0x000000FF +#define FLD_SPARE_STATUS1 0xff000000 +#define FLD_SPARE_STATUS0 0x00ff0000 +#define FLD_MOD_DET_STATUS1 0x0000ff00 +#define FLD_MOD_DET_STATUS0 0x000000ff /*****************************************************************************/ #define AUD_BUILD_NUM 0x806 #define AUD_VER_NUM 0x807 #define STD_DET_CTL 0x808 -#define STD_DET_CTL_AUD_CTL 0x808 /* Byte 1 in STD_DET_CTL */ -#define STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */ -#define FLD_SPARE_CTL0 0xFF000000 +#define STD_DET_CTL_AUD_CTL 0x808 /* Byte 1 in STD_DET_CTL */ +#define STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */ +#define FLD_SPARE_CTL0 0xff000000 #define FLD_DIS_DBX 0x00800000 #define FLD_DIS_BTSC 0x00400000 #define FLD_DIS_NICAM_A2 0x00200000 #define FLD_VIDEO_PRESENT 0x00100000 -#define FLD_DW8051_VIDEO_FORMAT 0x000F0000 -#define FLD_PREF_DEC_MODE 0x0000FF00 -#define FLD_AUD_CONFIG 0x000000FF +#define FLD_DW8051_VIDEO_FORMAT 0x000f0000 +#define FLD_PREF_DEC_MODE 0x0000ff00 +#define FLD_AUD_CONFIG 0x000000ff /*****************************************************************************/ -#define DW8051_INT 0x80C +#define DW8051_INT 0x80c #define FLD_VIDEO_PRESENT_CHANGE 0x80000000 #define FLD_VIDEO_CHANGE 0x40000000 #define FLD_RDS_READY 0x20000000 @@ -854,7 +854,7 @@ #define FLD_FC_INT_DIS 0x00040000 #define FLD_AMC_INT_DIS 0x00020000 #define FLD_AC97_INT_DIS 0x00010000 -#define FLD_REV_NUM 0x0000FF00 +#define FLD_REV_NUM 0x0000ff00 /* Reserved [7:5] */ #define FLD_DBX_SOFT_RESET_REG 0x00000010 #define FLD_AD_SOFT_RESET_REG 0x00000008 @@ -866,14 +866,14 @@ #define AAGC_CTL 0x814 #define FLD_AFE_12DB_EN 0x80000000 #define FLD_AAGC_DEFAULT_EN 0x40000000 -#define FLD_AAGC_DEFAULT 0x3F000000 +#define FLD_AAGC_DEFAULT 0x3f000000 /* Reserved [23] */ #define FLD_AAGC_GAIN 0x00600000 -#define FLD_AAGC_TH 0x001F0000 +#define FLD_AAGC_TH 0x001f0000 /* Reserved [15:14] */ -#define FLD_AAGC_HYST2 0x00003F00 +#define FLD_AAGC_HYST2 0x00003f00 /* Reserved [7:6] */ -#define FLD_AAGC_HYST1 0x0000003F +#define FLD_AAGC_HYST1 0x0000003f /*****************************************************************************/ #define IF_SRC_CTL 0x818 @@ -881,16 +881,16 @@ /* Reserved [30:25] */ #define FLD_IF_SRC_MODE 0x01000000 /* Reserved [23:18] */ -#define FLD_IF_SRC_PHASE_INC 0x0001FFFF +#define FLD_IF_SRC_PHASE_INC 0x0001ffff /*****************************************************************************/ -#define ANALOG_DEMOD_CTL 0x81C -#define FLD_ROT1_PHACC_PROG 0xFFFF0000 +#define ANALOG_DEMOD_CTL 0x81c +#define FLD_ROT1_PHACC_PROG 0xffff0000 /* Reserved [15] */ #define FLD_FM1_DELAY_FIX 0x00007000 -#define FLD_PDF4_SHIFT 0x00000C00 +#define FLD_PDF4_SHIFT 0x00000c00 #define FLD_PDF3_SHIFT 0x00000300 -#define FLD_PDF2_SHIFT 0x000000C0 +#define FLD_PDF2_SHIFT 0x000000c0 #define FLD_PDF1_SHIFT 0x00000030 #define FLD_FMBYPASS_MODE2 0x00000008 #define FLD_FMBYPASS_MODE1 0x00000004 @@ -899,19 +899,19 @@ /*****************************************************************************/ #define ROT_FREQ_CTL 0x820 -#define FLD_ROT3_PHACC_PROG 0xFFFF0000 -#define FLD_ROT2_PHACC_PROG 0x0000FFFF +#define FLD_ROT3_PHACC_PROG 0xffff0000 +#define FLD_ROT2_PHACC_PROG 0x0000ffff /*****************************************************************************/ #define FM_CTL 0x824 -#define FLD_FM2_DC_FB_SHIFT 0xF0000000 -#define FLD_FM2_DC_INT_SHIFT 0x0F000000 +#define FLD_FM2_DC_FB_SHIFT 0xf0000000 +#define FLD_FM2_DC_INT_SHIFT 0x0f000000 #define FLD_FM2_AFC_RESET 0x00800000 #define FLD_FM2_DC_PASS_IN 0x00400000 #define FLD_FM2_DAGC_SHIFT 0x00380000 #define FLD_FM2_CORDIC_SHIFT 0x00070000 -#define FLD_FM1_DC_FB_SHIFT 0x0000F000 -#define FLD_FM1_DC_INT_SHIFT 0x00000F00 +#define FLD_FM1_DC_FB_SHIFT 0x0000f000 +#define FLD_FM1_DC_INT_SHIFT 0x00000f00 #define FLD_FM1_AFC_RESET 0x00000080 #define FLD_FM1_DC_PASS_IN 0x00000040 #define FLD_FM1_DAGC_SHIFT 0x00000038 @@ -921,29 +921,29 @@ #define LPF_PDF_CTL 0x828 /* Reserved [31:30] */ #define FLD_LPF32_SHIFT1 0x30000000 -#define FLD_LPF32_SHIFT2 0x0C000000 +#define FLD_LPF32_SHIFT2 0x0c000000 #define FLD_LPF160_SHIFTA 0x03000000 -#define FLD_LPF160_SHIFTB 0x00C00000 +#define FLD_LPF160_SHIFTB 0x00c00000 #define FLD_LPF160_SHIFTC 0x00300000 -#define FLD_LPF32_COEF_SEL2 0x000C0000 +#define FLD_LPF32_COEF_SEL2 0x000c0000 #define FLD_LPF32_COEF_SEL1 0x00030000 -#define FLD_LPF160_COEF_SELC 0x0000C000 +#define FLD_LPF160_COEF_SELC 0x0000c000 #define FLD_LPF160_COEF_SELB 0x00003000 -#define FLD_LPF160_COEF_SELA 0x00000C00 +#define FLD_LPF160_COEF_SELA 0x00000c00 #define FLD_LPF160_IN_EN_REG 0x00000300 -#define FLD_PDF4_PDF_SEL 0x000000C0 +#define FLD_PDF4_PDF_SEL 0x000000c0 #define FLD_PDF3_PDF_SEL 0x00000030 -#define FLD_PDF2_PDF_SEL 0x0000000C +#define FLD_PDF2_PDF_SEL 0x0000000c #define FLD_PDF1_PDF_SEL 0x00000003 /*****************************************************************************/ -#define DFT1_CTL1 0x82C -#define FLD_DFT1_DWELL 0xFFFF0000 -#define FLD_DFT1_FREQ 0x0000FFFF +#define DFT1_CTL1 0x82c +#define FLD_DFT1_DWELL 0xffff0000 +#define FLD_DFT1_FREQ 0x0000ffff /*****************************************************************************/ #define DFT1_CTL2 0x830 -#define FLD_DFT1_THRESHOLD 0xFFFFFF00 +#define FLD_DFT1_THRESHOLD 0xffffff00 #define FLD_DFT1_CMP_CTL 0x00000080 #define FLD_DFT1_AVG 0x00000070 /* Reserved [3:1] */ @@ -953,16 +953,16 @@ #define DFT1_STATUS 0x834 #define FLD_DFT1_DONE 0x80000000 #define FLD_DFT1_TH_CMP_STAT 0x40000000 -#define FLD_DFT1_RESULT 0x3FFFFFFF +#define FLD_DFT1_RESULT 0x3fffffff /*****************************************************************************/ #define DFT2_CTL1 0x838 -#define FLD_DFT2_DWELL 0xFFFF0000 -#define FLD_DFT2_FREQ 0x0000FFFF +#define FLD_DFT2_DWELL 0xffff0000 +#define FLD_DFT2_FREQ 0x0000ffff /*****************************************************************************/ #define DFT2_CTL2 0x83C -#define FLD_DFT2_THRESHOLD 0xFFFFFF00 +#define FLD_DFT2_THRESHOLD 0xffffff00 #define FLD_DFT2_CMP_CTL 0x00000080 #define FLD_DFT2_AVG 0x00000070 /* Reserved [3:1] */ @@ -972,35 +972,35 @@ #define DFT2_STATUS 0x840 #define FLD_DFT2_DONE 0x80000000 #define FLD_DFT2_TH_CMP_STAT 0x40000000 -#define FLD_DFT2_RESULT 0x3FFFFFFF +#define FLD_DFT2_RESULT 0x3fffffff /*****************************************************************************/ #define DFT3_CTL1 0x844 -#define FLD_DFT3_DWELL 0xFFFF0000 -#define FLD_DFT3_FREQ 0x0000FFFF +#define FLD_DFT3_DWELL 0xffff0000 +#define FLD_DFT3_FREQ 0x0000ffff /*****************************************************************************/ #define DFT3_CTL2 0x848 -#define FLD_DFT3_THRESHOLD 0xFFFFFF00 +#define FLD_DFT3_THRESHOLD 0xffffff00 #define FLD_DFT3_CMP_CTL 0x00000080 #define FLD_DFT3_AVG 0x00000070 /* Reserved [3:1] */ #define FLD_DFT3_START 0x00000001 /*****************************************************************************/ -#define DFT3_STATUS 0x84C +#define DFT3_STATUS 0x84c #define FLD_DFT3_DONE 0x80000000 #define FLD_DFT3_TH_CMP_STAT 0x40000000 -#define FLD_DFT3_RESULT 0x3FFFFFFF +#define FLD_DFT3_RESULT 0x3fffffff /*****************************************************************************/ #define DFT4_CTL1 0x850 -#define FLD_DFT4_DWELL 0xFFFF0000 -#define FLD_DFT4_FREQ 0x0000FFFF +#define FLD_DFT4_DWELL 0xffff0000 +#define FLD_DFT4_FREQ 0x0000ffff /*****************************************************************************/ #define DFT4_CTL2 0x854 -#define FLD_DFT4_THRESHOLD 0xFFFFFF00 +#define FLD_DFT4_THRESHOLD 0xffffff00 #define FLD_DFT4_CMP_CTL 0x00000080 #define FLD_DFT4_AVG 0x00000070 /* Reserved [3:1] */ @@ -1010,19 +1010,19 @@ #define DFT4_STATUS 0x858 #define FLD_DFT4_DONE 0x80000000 #define FLD_DFT4_TH_CMP_STAT 0x40000000 -#define FLD_DFT4_RESULT 0x3FFFFFFF +#define FLD_DFT4_RESULT 0x3fffffff /*****************************************************************************/ -#define AM_MTS_DET 0x85C +#define AM_MTS_DET 0x85c #define FLD_AM_MTS_MODE 0x80000000 /* Reserved [30:26] */ #define FLD_AM_SUB 0x02000000 #define FLD_AM_GAIN_EN 0x01000000 /* Reserved [23:16] */ -#define FLD_AMMTS_GAIN_SCALE 0x0000E000 +#define FLD_AMMTS_GAIN_SCALE 0x0000e000 #define FLD_MTS_PDF_SHIFT 0x00001800 #define FLD_AM_REG_GAIN 0x00000700 -#define FLD_AGC_REF 0x000000FF +#define FLD_AGC_REF 0x000000ff /*****************************************************************************/ #define ANALOG_MUX_CTL 0x860 @@ -1044,9 +1044,9 @@ #define FLD_MUX7_SEL 0x00000800 #define FLD_MUX6_SEL 0x00000600 #define FLD_MUX5_SEL 0x00000100 -#define FLD_MUX4_SEL 0x000000C0 +#define FLD_MUX4_SEL 0x000000c0 #define FLD_MUX3_SEL 0x00000030 -#define FLD_MUX2_SEL 0x0000000C +#define FLD_MUX2_SEL 0x0000000c #define FLD_MUX1_SEL 0x00000003 /*****************************************************************************/ @@ -1057,48 +1057,48 @@ #define FLD_PLL_STATUS 0x07000000 #define FLD_BANDWIDTH_SELECT 0x00030000 #define FLD_PLL_SHIFT_REG 0x00007000 -#define FLD_PHASE_SHIFT 0x000007FF +#define FLD_PHASE_SHIFT 0x000007ff /*****************************************************************************/ /* Cx231xx redefine */ #define DPLL_CTRL2 0x868 #define DIG_PLL_CTL2 0x868 -#define FLD_PLL_UNLOCK_THR 0xFF000000 -#define FLD_PLL_LOCK_THR 0x00FF0000 +#define FLD_PLL_UNLOCK_THR 0xff000000 +#define FLD_PLL_LOCK_THR 0x00ff0000 /* Reserved [15:8] */ -#define FLD_AM_PDF_SEL2 0x000000C0 +#define FLD_AM_PDF_SEL2 0x000000c0 #define FLD_AM_PDF_SEL1 0x00000030 -#define FLD_DPLL_FSM_CTRL 0x0000000C +#define FLD_DPLL_FSM_CTRL 0x0000000c /* Reserved [1] */ #define FLD_PLL_PILOT_DET 0x00000001 /*****************************************************************************/ /* Cx231xx redefine */ -#define DPLL_CTRL3 0x86C -#define DIG_PLL_CTL3 0x86C +#define DPLL_CTRL3 0x86c +#define DIG_PLL_CTL3 0x86c #define FLD_DISABLE_LOOP 0x01000000 -#define FLD_A1_DS1_SEL 0x000C0000 +#define FLD_A1_DS1_SEL 0x000c0000 #define FLD_A1_DS2_SEL 0x00030000 -#define FLD_A1_KI 0x0000FF00 -#define FLD_A1_KD 0x000000FF +#define FLD_A1_KI 0x0000ff00 +#define FLD_A1_KD 0x000000ff /*****************************************************************************/ /* Cx231xx redefine */ #define DPLL_CTRL4 0x870 #define DIG_PLL_CTL4 0x870 -#define FLD_A2_DS1_SEL 0x000C0000 +#define FLD_A2_DS1_SEL 0x000c0000 #define FLD_A2_DS2_SEL 0x00030000 -#define FLD_A2_KI 0x0000FF00 -#define FLD_A2_KD 0x000000FF +#define FLD_A2_KI 0x0000ff00 +#define FLD_A2_KD 0x000000ff /*****************************************************************************/ /* Cx231xx redefine */ #define DPLL_CTRL5 0x874 #define DIG_PLL_CTL5 0x874 -#define FLD_TRK_DS1_SEL 0x000C0000 +#define FLD_TRK_DS1_SEL 0x000c0000 #define FLD_TRK_DS2_SEL 0x00030000 -#define FLD_TRK_KI 0x0000FF00 -#define FLD_TRK_KD 0x000000FF +#define FLD_TRK_KI 0x0000ff00 +#define FLD_TRK_KD 0x000000ff /*****************************************************************************/ #define DEEMPH_GAIN_CTL 0x878 @@ -1107,10 +1107,10 @@ /*****************************************************************************/ /* Cx231xx redefine */ -#define DEEMPH_COEFF1 0x87C -#define DEEMPH_COEF1 0x87C -#define FLD_DEEMPH_B0 0xFFFF0000 -#define FLD_DEEMPH_A0 0x0000FFFF +#define DEEMPH_COEFF1 0x87c +#define DEEMPH_COEF1 0x87c +#define FLD_DEEMPH_B0 0xffff0000 +#define FLD_DEEMPH_A0 0x0000ffff /*****************************************************************************/ /* Cx231xx redefine */ @@ -1121,281 +1121,281 @@ /*****************************************************************************/ #define DBX1_CTL1 0x884 -#define FLD_DBX1_WBE_GAIN 0xFFFF0000 -#define FLD_DBX1_IN_GAIN 0x0000FFFF +#define FLD_DBX1_WBE_GAIN 0xffff0000 +#define FLD_DBX1_IN_GAIN 0x0000ffff /*****************************************************************************/ #define DBX1_CTL2 0x888 -#define FLD_DBX1_SE_BYPASS 0xFFFF0000 -#define FLD_DBX1_SE_GAIN 0x0000FFFF +#define FLD_DBX1_SE_BYPASS 0xffff0000 +#define FLD_DBX1_SE_GAIN 0x0000ffff /*****************************************************************************/ #define DBX1_RMS_SE 0x88C -#define FLD_DBX1_RMS_WBE 0xFFFF0000 -#define FLD_DBX1_RMS_SE_FLD 0x0000FFFF +#define FLD_DBX1_RMS_WBE 0xffff0000 +#define FLD_DBX1_RMS_SE_FLD 0x0000ffff /*****************************************************************************/ #define DBX2_CTL1 0x890 -#define FLD_DBX2_WBE_GAIN 0xFFFF0000 -#define FLD_DBX2_IN_GAIN 0x0000FFFF +#define FLD_DBX2_WBE_GAIN 0xffff0000 +#define FLD_DBX2_IN_GAIN 0x0000ffff /*****************************************************************************/ #define DBX2_CTL2 0x894 -#define FLD_DBX2_SE_BYPASS 0xFFFF0000 -#define FLD_DBX2_SE_GAIN 0x0000FFFF +#define FLD_DBX2_SE_BYPASS 0xffff0000 +#define FLD_DBX2_SE_GAIN 0x0000ffff /*****************************************************************************/ #define DBX2_RMS_SE 0x898 -#define FLD_DBX2_RMS_WBE 0xFFFF0000 -#define FLD_DBX2_RMS_SE_FLD 0x0000FFFF +#define FLD_DBX2_RMS_WBE 0xffff0000 +#define FLD_DBX2_RMS_SE_FLD 0x0000ffff /*****************************************************************************/ -#define AM_FM_DIFF 0x89C +#define AM_FM_DIFF 0x89c /* Reserved [31] */ -#define FLD_FM_DIFF_OUT 0x7FFF0000 +#define FLD_FM_DIFF_OUT 0x7fff0000 /* Reserved [15] */ -#define FLD_AM_DIFF_OUT 0x00007FFF +#define FLD_AM_DIFF_OUT 0x00007fff /*****************************************************************************/ -#define NICAM_FAW 0x8A0 -#define FLD_FAWDETWINEND 0xFC000000 -#define FLD_FAWDETWINSTR 0x03FF0000 +#define NICAM_FAW 0x8a0 +#define FLD_FAWDETWINEND 0xFc000000 +#define FLD_FAWDETWINSTR 0x03ff0000 /* Reserved [15:12] */ -#define FLD_FAWDETTHRSHLD3 0x00000F00 -#define FLD_FAWDETTHRSHLD2 0x000000F0 -#define FLD_FAWDETTHRSHLD1 0x0000000F +#define FLD_FAWDETTHRSHLD3 0x00000f00 +#define FLD_FAWDETTHRSHLD2 0x000000f0 +#define FLD_FAWDETTHRSHLD1 0x0000000f /*****************************************************************************/ /* Cx231xx redefine */ -#define DEEMPH_GAIN 0x8A4 -#define NICAM_DEEMPHGAIN 0x8A4 +#define DEEMPH_GAIN 0x8a4 +#define NICAM_DEEMPHGAIN 0x8a4 /* Reserved [31:18] */ -#define FLD_DEEMPHGAIN 0x0003FFFF +#define FLD_DEEMPHGAIN 0x0003ffff /*****************************************************************************/ /* Cx231xx redefine */ -#define DEEMPH_NUMER1 0x8A8 -#define NICAM_DEEMPHNUMER1 0x8A8 +#define DEEMPH_NUMER1 0x8a8 +#define NICAM_DEEMPHNUMER1 0x8a8 /* Reserved [31:18] */ -#define FLD_DEEMPHNUMER1 0x0003FFFF +#define FLD_DEEMPHNUMER1 0x0003ffff /*****************************************************************************/ /* Cx231xx redefine */ -#define DEEMPH_NUMER2 0x8AC -#define NICAM_DEEMPHNUMER2 0x8AC +#define DEEMPH_NUMER2 0x8ac +#define NICAM_DEEMPHNUMER2 0x8ac /* Reserved [31:18] */ -#define FLD_DEEMPHNUMER2 0x0003FFFF +#define FLD_DEEMPHNUMER2 0x0003ffff /*****************************************************************************/ /* Cx231xx redefine */ -#define DEEMPH_DENOM1 0x8B0 -#define NICAM_DEEMPHDENOM1 0x8B0 +#define DEEMPH_DENOM1 0x8b0 +#define NICAM_DEEMPHDENOM1 0x8b0 /* Reserved [31:18] */ -#define FLD_DEEMPHDENOM1 0x0003FFFF +#define FLD_DEEMPHDENOM1 0x0003ffff /*****************************************************************************/ /* Cx231xx redefine */ -#define DEEMPH_DENOM2 0x8B4 -#define NICAM_DEEMPHDENOM2 0x8B4 +#define DEEMPH_DENOM2 0x8b4 +#define NICAM_DEEMPHDENOM2 0x8b4 /* Reserved [31:18] */ -#define FLD_DEEMPHDENOM2 0x0003FFFF +#define FLD_DEEMPHDENOM2 0x0003ffff /*****************************************************************************/ #define NICAM_ERRLOG_CTL1 0x8B8 /* Reserved [31:28] */ -#define FLD_ERRINTRPTTHSHLD1 0x0FFF0000 +#define FLD_ERRINTRPTTHSHLD1 0x0fff0000 /* Reserved [15:12] */ -#define FLD_ERRLOGPERIOD 0x00000FFF +#define FLD_ERRLOGPERIOD 0x00000fff /*****************************************************************************/ -#define NICAM_ERRLOG_CTL2 0x8BC +#define NICAM_ERRLOG_CTL2 0x8bc /* Reserved [31:28] */ -#define FLD_ERRINTRPTTHSHLD3 0x0FFF0000 +#define FLD_ERRINTRPTTHSHLD3 0x0fff0000 /* Reserved [15:12] */ -#define FLD_ERRINTRPTTHSHLD2 0x00000FFF +#define FLD_ERRINTRPTTHSHLD2 0x00000fff /*****************************************************************************/ -#define NICAM_ERRLOG_STS1 0x8C0 +#define NICAM_ERRLOG_STS1 0x8c0 /* Reserved [31:28] */ -#define FLD_ERRLOG2 0x0FFF0000 +#define FLD_ERRLOG2 0x0fff0000 /* Reserved [15:12] */ -#define FLD_ERRLOG1 0x00000FFF +#define FLD_ERRLOG1 0x00000fff /*****************************************************************************/ -#define NICAM_ERRLOG_STS2 0x8C4 +#define NICAM_ERRLOG_STS2 0x8c4 /* Reserved [31:12] */ -#define FLD_ERRLOG3 0x00000FFF +#define FLD_ERRLOG3 0x00000fff /*****************************************************************************/ -#define NICAM_STATUS 0x8C8 +#define NICAM_STATUS 0x8c8 /* Reserved [31:20] */ -#define FLD_NICAM_CIB 0x000C0000 +#define FLD_NICAM_CIB 0x000c0000 #define FLD_NICAM_LOCK_STAT 0x00020000 #define FLD_NICAM_MUTE 0x00010000 -#define FLD_NICAMADDIT_DATA 0x0000FFE0 -#define FLD_NICAMCNTRL 0x0000001F +#define FLD_NICAMADDIT_DATA 0x0000ffe0 +#define FLD_NICAMCNTRL 0x0000001f /*****************************************************************************/ -#define DEMATRIX_CTL 0x8CC -#define FLD_AC97_IN_SHIFT 0xF0000000 -#define FLD_I2S_IN_SHIFT 0x0F000000 -#define FLD_DEMATRIX_SEL_CTL 0x00FF0000 +#define DEMATRIX_CTL 0x8cc +#define FLD_AC97_IN_SHIFT 0xf0000000 +#define FLD_I2S_IN_SHIFT 0x0f000000 +#define FLD_DEMATRIX_SEL_CTL 0x00ff0000 /* Reserved [15:11] */ #define FLD_DMTRX_BYPASS 0x00000400 #define FLD_DEMATRIX_MODE 0x00000300 /* Reserved [7:6] */ #define FLD_PH_DBX_SEL 0x00000020 #define FLD_PH_CH_SEL 0x00000010 -#define FLD_PHASE_FIX 0x0000000F +#define FLD_PHASE_FIX 0x0000000f /*****************************************************************************/ -#define PATH1_CTL1 0x8D0 +#define PATH1_CTL1 0x8d0 /* Reserved [31:29] */ -#define FLD_PATH1_MUTE_CTL 0x1F000000 +#define FLD_PATH1_MUTE_CTL 0x1f000000 /* Reserved [23:22] */ #define FLD_PATH1_AVC_CG 0x00300000 -#define FLD_PATH1_AVC_RT 0x000F0000 -#define FLD_PATH1_AVC_AT 0x0000F000 +#define FLD_PATH1_AVC_RT 0x000f0000 +#define FLD_PATH1_AVC_AT 0x0000f000 #define FLD_PATH1_AVC_STEREO 0x00000800 #define FLD_PATH1_AVC_CR 0x00000700 -#define FLD_PATH1_AVC_RMS_CON 0x000000F0 -#define FLD_PATH1_SEL_CTL 0x0000000F +#define FLD_PATH1_AVC_RMS_CON 0x000000f0 +#define FLD_PATH1_SEL_CTL 0x0000000f /*****************************************************************************/ -#define PATH1_VOL_CTL 0x8D4 -#define FLD_PATH1_AVC_THRESHOLD 0x7FFF0000 +#define PATH1_VOL_CTL 0x8d4 +#define FLD_PATH1_AVC_THRESHOLD 0x7fff0000 #define FLD_PATH1_BAL_LEFT 0x00008000 -#define FLD_PATH1_BAL_LEVEL 0x00007F00 -#define FLD_PATH1_VOLUME 0x000000FF +#define FLD_PATH1_BAL_LEVEL 0x00007f00 +#define FLD_PATH1_VOLUME 0x000000ff /*****************************************************************************/ -#define PATH1_EQ_CTL 0x8D8 +#define PATH1_EQ_CTL 0x8d8 /* Reserved [31:30] */ -#define FLD_PATH1_EQ_TREBLE_VOL 0x3F000000 +#define FLD_PATH1_EQ_TREBLE_VOL 0x3f000000 /* Reserved [23:22] */ -#define FLD_PATH1_EQ_MID_VOL 0x003F0000 +#define FLD_PATH1_EQ_MID_VOL 0x003f0000 /* Reserved [15:14] */ -#define FLD_PATH1_EQ_BASS_VOL 0x00003F00 +#define FLD_PATH1_EQ_BASS_VOL 0x00003f00 /* Reserved [7:1] */ #define FLD_PATH1_EQ_BAND_SEL 0x00000001 /*****************************************************************************/ -#define PATH1_SC_CTL 0x8DC -#define FLD_PATH1_SC_THRESHOLD 0x7FFF0000 -#define FLD_PATH1_SC_RT 0x0000F000 -#define FLD_PATH1_SC_AT 0x00000F00 +#define PATH1_SC_CTL 0x8dc +#define FLD_PATH1_SC_THRESHOLD 0x7fff0000 +#define FLD_PATH1_SC_RT 0x0000f000 +#define FLD_PATH1_SC_AT 0x00000f00 #define FLD_PATH1_SC_STEREO 0x00000080 #define FLD_PATH1_SC_CR 0x00000070 -#define FLD_PATH1_SC_RMS_CON 0x0000000F +#define FLD_PATH1_SC_RMS_CON 0x0000000f /*****************************************************************************/ -#define PATH2_CTL1 0x8E0 +#define PATH2_CTL1 0x8e0 /* Reserved [31:26] */ #define FLD_PATH2_MUTE_CTL 0x03000000 /* Reserved [23:22] */ #define FLD_PATH2_AVC_CG 0x00300000 -#define FLD_PATH2_AVC_RT 0x000F0000 -#define FLD_PATH2_AVC_AT 0x0000F000 +#define FLD_PATH2_AVC_RT 0x000f0000 +#define FLD_PATH2_AVC_AT 0x0000f000 #define FLD_PATH2_AVC_STEREO 0x00000800 #define FLD_PATH2_AVC_CR 0x00000700 -#define FLD_PATH2_AVC_RMS_CON 0x000000F0 -#define FLD_PATH2_SEL_CTL 0x0000000F +#define FLD_PATH2_AVC_RMS_CON 0x000000f0 +#define FLD_PATH2_SEL_CTL 0x0000000f /*****************************************************************************/ -#define PATH2_VOL_CTL 0x8E4 -#define FLD_PATH2_AVC_THRESHOLD 0xFFFF0000 +#define PATH2_VOL_CTL 0x8e4 +#define FLD_PATH2_AVC_THRESHOLD 0xffff0000 #define FLD_PATH2_BAL_LEFT 0x00008000 -#define FLD_PATH2_BAL_LEVEL 0x00007F00 -#define FLD_PATH2_VOLUME 0x000000FF +#define FLD_PATH2_BAL_LEVEL 0x00007f00 +#define FLD_PATH2_VOLUME 0x000000ff /*****************************************************************************/ -#define PATH2_EQ_CTL 0x8E8 +#define PATH2_EQ_CTL 0x8e8 /* Reserved [31:30] */ -#define FLD_PATH2_EQ_TREBLE_VOL 0x3F000000 +#define FLD_PATH2_EQ_TREBLE_VOL 0x3f000000 /* Reserved [23:22] */ -#define FLD_PATH2_EQ_MID_VOL 0x003F0000 +#define FLD_PATH2_EQ_MID_VOL 0x003f0000 /* Reserved [15:14] */ -#define FLD_PATH2_EQ_BASS_VOL 0x00003F00 +#define FLD_PATH2_EQ_BASS_VOL 0x00003f00 /* Reserved [7:1] */ #define FLD_PATH2_EQ_BAND_SEL 0x00000001 /*****************************************************************************/ -#define PATH2_SC_CTL 0x8EC -#define FLD_PATH2_SC_THRESHOLD 0xFFFF0000 -#define FLD_PATH2_SC_RT 0x0000F000 -#define FLD_PATH2_SC_AT 0x00000F00 +#define PATH2_SC_CTL 0x8eC +#define FLD_PATH2_SC_THRESHOLD 0xffff0000 +#define FLD_PATH2_SC_RT 0x0000f000 +#define FLD_PATH2_SC_AT 0x00000f00 #define FLD_PATH2_SC_STEREO 0x00000080 #define FLD_PATH2_SC_CR 0x00000070 -#define FLD_PATH2_SC_RMS_CON 0x0000000F +#define FLD_PATH2_SC_RMS_CON 0x0000000f /*****************************************************************************/ -#define SRC_CTL 0x8F0 -#define FLD_SRC_STATUS 0xFFFFFF00 -#define FLD_FIFO_LF_EN 0x000000FC +#define SRC_CTL 0x8f0 +#define FLD_SRC_STATUS 0xffffff00 +#define FLD_FIFO_LF_EN 0x000000fc #define FLD_BYPASS_LI 0x00000002 #define FLD_BYPASS_PF 0x00000001 /*****************************************************************************/ -#define SRC_LF_COEF 0x8F4 -#define FLD_LOOP_FILTER_COEF2 0xFFFF0000 -#define FLD_LOOP_FILTER_COEF1 0x0000FFFF +#define SRC_LF_COEF 0x8f4 +#define FLD_LOOP_FILTER_COEF2 0xffff0000 +#define FLD_LOOP_FILTER_COEF1 0x0000ffff /*****************************************************************************/ -#define SRC1_CTL 0x8F8 +#define SRC1_CTL 0x8f8 /* Reserved [31:28] */ -#define FLD_SRC1_FIFO_RD_TH 0x0F000000 +#define FLD_SRC1_FIFO_RD_TH 0x0f000000 /* Reserved [23:18] */ -#define FLD_SRC1_PHASE_INC 0x0003FFFF +#define FLD_SRC1_PHASE_INC 0x0003ffff /*****************************************************************************/ -#define SRC2_CTL 0x8FC +#define SRC2_CTL 0x8fc /* Reserved [31:28] */ -#define FLD_SRC2_FIFO_RD_TH 0x0F000000 +#define FLD_SRC2_FIFO_RD_TH 0x0f000000 /* Reserved [23:18] */ -#define FLD_SRC2_PHASE_INC 0x0003FFFF +#define FLD_SRC2_PHASE_INC 0x0003ffff /*****************************************************************************/ #define SRC3_CTL 0x900 /* Reserved [31:28] */ -#define FLD_SRC3_FIFO_RD_TH 0x0F000000 +#define FLD_SRC3_FIFO_RD_TH 0x0f000000 /* Reserved [23:18] */ -#define FLD_SRC3_PHASE_INC 0x0003FFFF +#define FLD_SRC3_PHASE_INC 0x0003ffff /*****************************************************************************/ #define SRC4_CTL 0x904 /* Reserved [31:28] */ -#define FLD_SRC4_FIFO_RD_TH 0x0F000000 +#define FLD_SRC4_FIFO_RD_TH 0x0f000000 /* Reserved [23:18] */ -#define FLD_SRC4_PHASE_INC 0x0003FFFF +#define FLD_SRC4_PHASE_INC 0x0003ffff /*****************************************************************************/ #define SRC5_CTL 0x908 /* Reserved [31:28] */ -#define FLD_SRC5_FIFO_RD_TH 0x0F000000 +#define FLD_SRC5_FIFO_RD_TH 0x0f000000 /* Reserved [23:18] */ -#define FLD_SRC5_PHASE_INC 0x0003FFFF +#define FLD_SRC5_PHASE_INC 0x0003ffff /*****************************************************************************/ -#define SRC6_CTL 0x90C +#define SRC6_CTL 0x90c /* Reserved [31:28] */ -#define FLD_SRC6_FIFO_RD_TH 0x0F000000 +#define FLD_SRC6_FIFO_RD_TH 0x0f000000 /* Reserved [23:18] */ -#define FLD_SRC6_PHASE_INC 0x0003FFFF +#define FLD_SRC6_PHASE_INC 0x0003ffff /*****************************************************************************/ #define BAND_OUT_SEL 0x910 -#define FLD_SRC6_IN_SEL 0xC0000000 +#define FLD_SRC6_IN_SEL 0xc0000000 #define FLD_SRC6_CLK_SEL 0x30000000 -#define FLD_SRC5_IN_SEL 0x0C000000 +#define FLD_SRC5_IN_SEL 0x0c000000 #define FLD_SRC5_CLK_SEL 0x03000000 -#define FLD_SRC4_IN_SEL 0x00C00000 +#define FLD_SRC4_IN_SEL 0x00c00000 #define FLD_SRC4_CLK_SEL 0x00300000 -#define FLD_SRC3_IN_SEL 0x000C0000 +#define FLD_SRC3_IN_SEL 0x000c0000 #define FLD_SRC3_CLK_SEL 0x00030000 -#define FLD_BASEBAND_BYPASS_CTL 0x0000FF00 -#define FLD_AC97_SRC_SEL 0x000000C0 +#define FLD_BASEBAND_BYPASS_CTL 0x0000ff00 +#define FLD_AC97_SRC_SEL 0x000000c0 #define FLD_I2S_SRC_SEL 0x00000030 -#define FLD_PARALLEL2_SRC_SEL 0x0000000C +#define FLD_PARALLEL2_SRC_SEL 0x0000000c #define FLD_PARALLEL1_SRC_SEL 0x00000003 /*****************************************************************************/ @@ -1407,7 +1407,7 @@ #define FLD_I2S_IN_SONY_MODE 0x00000080 #define FLD_I2S_IN_RIGHT_JUST 0x00000040 #define FLD_I2S_IN_WS_SEL 0x00000020 -#define FLD_I2S_IN_BCN_DEL 0x0000001F +#define FLD_I2S_IN_BCN_DEL 0x0000001f /*****************************************************************************/ #define I2S_OUT_CTL 0x918 @@ -1418,10 +1418,10 @@ #define FLD_I2S_OUT_SONY_MODE 0x00000080 #define FLD_I2S_OUT_RIGHT_JUST 0x00000040 #define FLD_I2S_OUT_WS_SEL 0x00000020 -#define FLD_I2S_OUT_BCN_DEL 0x0000001F +#define FLD_I2S_OUT_BCN_DEL 0x0000001f /*****************************************************************************/ -#define AC97_CTL 0x91C +#define AC97_CTL 0x91c /* Reserved [31:26] */ #define FLD_AC97_UP2X_BW20K 0x02000000 #define FLD_AC97_UP2X_BYPASS 0x01000000 @@ -1433,20 +1433,20 @@ #define FLD_AC97_SHUTDOWN 0x00000001 /* Cx231xx redefine */ -#define QPSK_IAGC_CTL1 0x94c -#define QPSK_IAGC_CTL2 0x950 -#define QPSK_FEPR_FREQ 0x954 -#define QPSK_BTL_CTL1 0x958 -#define QPSK_BTL_CTL2 0x95c -#define QPSK_CTL_CTL1 0x960 -#define QPSK_CTL_CTL2 0x964 -#define QPSK_MF_FAGC_CTL 0x968 -#define QPSK_EQ_CTL 0x96c -#define QPSK_LOCK_CTL 0x970 - -/*****************************************************************************/ -#define FM1_DFT_CTL 0x9A8 -#define FLD_FM1_DFT_THRESHOLD 0xFFFF0000 +#define QPSK_IAGC_CTL1 0x94c +#define QPSK_IAGC_CTL2 0x950 +#define QPSK_FEPR_FREQ 0x954 +#define QPSK_BTL_CTL1 0x958 +#define QPSK_BTL_CTL2 0x95c +#define QPSK_CTL_CTL1 0x960 +#define QPSK_CTL_CTL2 0x964 +#define QPSK_MF_FAGC_CTL 0x968 +#define QPSK_EQ_CTL 0x96c +#define QPSK_LOCK_CTL 0x970 + +/*****************************************************************************/ +#define FM1_DFT_CTL 0x9a8 +#define FLD_FM1_DFT_THRESHOLD 0xffff0000 /* Reserved [15:8] */ #define FLD_FM1_DFT_CMP_CTL 0x00000080 #define FLD_FM1_DFT_AVG 0x00000070 @@ -1454,15 +1454,15 @@ #define FLD_FM1_DFT_START 0x00000001 /*****************************************************************************/ -#define FM1_DFT_STATUS 0x9AC +#define FM1_DFT_STATUS 0x9ac #define FLD_FM1_DFT_DONE 0x80000000 /* Reserved [30:19] */ #define FLD_FM_DFT_TH_CMP 0x00040000 -#define FLD_FM1_DFT 0x0003FFFF +#define FLD_FM1_DFT 0x0003ffff /*****************************************************************************/ -#define FM2_DFT_CTL 0x9B0 -#define FLD_FM2_DFT_THRESHOLD 0xFFFF0000 +#define FM2_DFT_CTL 0x9b0 +#define FLD_FM2_DFT_THRESHOLD 0xffff0000 /* Reserved [15:8] */ #define FLD_FM2_DFT_CMP_CTL 0x00000080 #define FLD_FM2_DFT_AVG 0x00000070 @@ -1470,52 +1470,52 @@ #define FLD_FM2_DFT_START 0x00000001 /*****************************************************************************/ -#define FM2_DFT_STATUS 0x9B4 +#define FM2_DFT_STATUS 0x9b4 #define FLD_FM2_DFT_DONE 0x80000000 /* Reserved [30:19] */ #define FLD_FM2_DFT_TH_CMP_STAT 0x00040000 -#define FLD_FM2_DFT 0x0003FFFF +#define FLD_FM2_DFT 0x0003ffff /*****************************************************************************/ /* Cx231xx redefine */ -#define AAGC_STATUS_REG 0x9B8 -#define AAGC_STATUS 0x9B8 +#define AAGC_STATUS_REG 0x9b8 +#define AAGC_STATUS 0x9b8 /* Reserved [31:27] */ #define FLD_FM2_DAGC_OUT 0x07000000 /* Reserved [23:19] */ #define FLD_FM1_DAGC_OUT 0x00070000 /* Reserved [15:6] */ -#define FLD_AFE_VGA_OUT 0x0000003F +#define FLD_AFE_VGA_OUT 0x0000003f /*****************************************************************************/ -#define MTS_GAIN_STATUS 0x9BC +#define MTS_GAIN_STATUS 0x9bc /* Reserved [31:14] */ -#define FLD_MTS_GAIN 0x00003FFF +#define FLD_MTS_GAIN 0x00003fff -#define RDS_OUT 0x9C0 -#define FLD_RDS_Q 0xFFFF0000 -#define FLD_RDS_I 0x0000FFFF +#define RDS_OUT 0x9c0 +#define FLD_RDS_Q 0xffff0000 +#define FLD_RDS_I 0x0000ffff /*****************************************************************************/ -#define AUTOCONFIG_REG 0x9C4 +#define AUTOCONFIG_REG 0x9c4 /* Reserved [31:4] */ -#define FLD_AUTOCONFIG_MODE 0x0000000F +#define FLD_AUTOCONFIG_MODE 0x0000000f -#define FM_AFC 0x9C8 -#define FLD_FM2_AFC 0xFFFF0000 -#define FLD_FM1_AFC 0x0000FFFF +#define FM_AFC 0x9c8 +#define FLD_FM2_AFC 0xffff0000 +#define FLD_FM1_AFC 0x0000ffff /*****************************************************************************/ /* Cx231xx redefine */ -#define NEW_SPARE 0x9CC -#define NEW_SPARE_REG 0x9CC +#define NEW_SPARE 0x9cc +#define NEW_SPARE_REG 0x9cc /*****************************************************************************/ -#define DBX_ADJ 0x9D0 +#define DBX_ADJ 0x9d0 /* Reserved [31:28] */ -#define FLD_DBX2_ADJ 0x0FFF0000 +#define FLD_DBX2_ADJ 0x0fff0000 /* Reserved [15:12] */ -#define FLD_DBX1_ADJ 0x00000FFF +#define FLD_DBX1_ADJ 0x00000fff #define VID_FMT_AUTO 0 #define VID_FMT_NTSC_M 1 @@ -1529,18 +1529,18 @@ #define VID_FMT_SECAM 12 #define VID_FMT_SECAM_60 13 -#define INPUT_MODE_CVBS_0 0 /* INPUT_MODE_VALUE(0) */ -#define INPUT_MODE_YC_1 1 /* INPUT_MODE_VALUE(1) */ -#define INPUT_MODE_YC2_2 2 /* INPUT_MODE_VALUE(2) */ -#define INPUT_MODE_YUV_3 3 /* INPUT_MODE_VALUE(3) */ +#define INPUT_MODE_CVBS_0 0 /* INPUT_MODE_VALUE(0) */ +#define INPUT_MODE_YC_1 1 /* INPUT_MODE_VALUE(1) */ +#define INPUT_MODE_YC2_2 2 /* INPUT_MODE_VALUE(2) */ +#define INPUT_MODE_YUV_3 3 /* INPUT_MODE_VALUE(3) */ -#define LUMA_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */ -#define LUMA_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */ -#define LUMA_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */ +#define LUMA_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */ +#define LUMA_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */ +#define LUMA_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */ -#define UV_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */ -#define UV_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */ -#define UV_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */ +#define UV_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */ +#define UV_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */ +#define UV_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */ #define TWO_TAP_FILT 0 #define THREE_TAP_FILT 1 @@ -1557,8 +1557,8 @@ #define OUT_MODE_VIP11 2 #define OUT_MODE_VIP20 3 -#define PHASE_INC_49MHZ 0x0DF22 -#define PHASE_INC_56MHZ 0x0FA5B +#define PHASE_INC_49MHZ 0x0df22 +#define PHASE_INC_56MHZ 0x0fa5b #define PHASE_INC_28MHZ 0x010000 #endif diff --git a/drivers/media/video/cx231xx/cx231xx-video.c b/drivers/media/video/cx231xx/cx231xx-video.c index fc7260a71e8e..606f80129ffb 100644 --- a/drivers/media/video/cx231xx/cx231xx-video.c +++ b/drivers/media/video/cx231xx/cx231xx-video.c @@ -1655,10 +1655,12 @@ static int vidioc_querycap(struct file *file, void *priv, cap->capabilities = V4L2_CAP_VBI_CAPTURE | #if 0 - V4L2_CAP_SLICED_VBI_CAPTURE | + V4L2_CAP_SLICED_VBI_CAPTURE | #endif - V4L2_CAP_VIDEO_CAPTURE | - V4L2_CAP_AUDIO | V4L2_CAP_READWRITE | V4L2_CAP_STREAMING; + V4L2_CAP_VIDEO_CAPTURE | + V4L2_CAP_AUDIO | + V4L2_CAP_READWRITE | + V4L2_CAP_STREAMING; if (dev->tuner_type != TUNER_ABSENT) cap->capabilities |= V4L2_CAP_TUNER; diff --git a/drivers/media/video/cx231xx/cx231xx.h b/drivers/media/video/cx231xx/cx231xx.h index f6e34a6de783..7c2a162f5c41 100644 --- a/drivers/media/video/cx231xx/cx231xx.h +++ b/drivers/media/video/cx231xx/cx231xx.h @@ -35,7 +35,7 @@ #endif #include "cx231xx-reg.h" -#include "cx231xx-pcb-config.h" +#include "cx231xx-pcb-cfg.h" #include "cx231xx-conf-reg.h" #define DRIVER_NAME "cx231xx" @@ -389,7 +389,7 @@ struct cx231xx_i2c_xfer_data { u8 *p_buffer; /* pointer to the buffer */ }; -struct VENDOR_REQUEST_IN{ +struct VENDOR_REQUEST_IN { u8 bRequest; u16 wValue; u16 wIndex; @@ -407,7 +407,7 @@ struct cx231xx_ctrl { u32 shift; }; -enum TRANSFER_TYPE{ +enum TRANSFER_TYPE { Raw_Video = 0, Audio, Vbi, /* VANC */ @@ -581,12 +581,14 @@ int cx231xx_colibri_init_channels(struct cx231xx *dev); int cx231xx_colibri_setup_AFE_for_baseband(struct cx231xx *dev); int cx231xx_colibri_set_input_mux(struct cx231xx *dev, u32 input_mux); int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode); -int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode); +int cx231xx_colibri_update_power_control(struct cx231xx *dev, + enum AV_MODE avmode); int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input); /* flatiron related functions */ int cx231xx_flatiron_initialize(struct cx231xx *dev); -int cx231xx_flatiron_update_power_control(struct cx231xx *dev, AV_MODE avmode); +int cx231xx_flatiron_update_power_control(struct cx231xx *dev, + enum AV_MODE avmode); int cx231xx_flatiron_set_audio_input(struct cx231xx *dev, u8 audio_input); /* DIF related functions */ @@ -692,7 +694,7 @@ int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask); int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type); /* Power control functions */ -int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode); +int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode); int cx231xx_power_suspend(struct cx231xx *dev); /* chip specific control functions */ |
