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96 files changed, 15323 insertions, 957 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt new file mode 100644 index 000000000000..6540ca56be5e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt @@ -0,0 +1,98 @@ +Broadcom Cygnus GPIO/PINCONF Controller + +Required properties: + +- compatible: + Must be "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or + "brcm,cygnus-crmu-gpio" + +- reg: + Define the base and range of the I/O address space that contains the Cygnus +GPIO/PINCONF controller registers + +- #gpio-cells: + Must be two. The first cell is the GPIO pin number (within the +controller's pin space) and the second cell is used for the following: + bit[0]: polarity (0 for active high and 1 for active low) + +- gpio-controller: + Specifies that the node is a GPIO controller + +Optional properties: + +- interrupts: + Interrupt ID + +- interrupt-controller: + Specifies that the node is an interrupt controller + +- pinmux: + Specifies the phandle to the IOMUX device, where pins can be individually +muxed to GPIO + +Supported generic PINCONF properties in child nodes: + +- pins: + The list of pins (within the controller's own pin space) that properties +in the node apply to. Pin names are "gpio-<pin>" + +- bias-disable: + Disable pin bias + +- bias-pull-up: + Enable internal pull up resistor + +- bias-pull-down: + Enable internal pull down resistor + +- drive-strength: + Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA) + +Example: + gpio_ccm: gpio@1800a000 { + compatible = "brcm,cygnus-ccm-gpio"; + reg = <0x1800a000 0x50>, + <0x0301d164 0x20>; + #gpio-cells = <2>; + gpio-controller; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + + touch_pins: touch_pins { + pwr: pwr { + pins = "gpio-0"; + drive-strength = <16>; + }; + + event: event { + pins = "gpio-1"; + bias-pull-up; + }; + }; + }; + + gpio_asiu: gpio@180a5000 { + compatible = "brcm,cygnus-asiu-gpio"; + reg = <0x180a5000 0x668>; + #gpio-cells = <2>; + gpio-controller; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + }; + + /* + * Touchscreen that uses the CCM GPIO 0 and 1 + */ + tsc { + ... + ... + gpio-pwr = <&gpio_ccm 0 0>; + gpio-event = <&gpio_ccm 1 0>; + }; + + /* Bluetooth that uses the ASIU GPIO 5, with polarity inverted */ + bluetooth { + ... + ... + bcm,rfkill-bank-sel = <&gpio_asiu 5 1> + } diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-pinmux.txt new file mode 100644 index 000000000000..3600d5c6c4d7 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-pinmux.txt @@ -0,0 +1,132 @@ +Broadcom Cygnus IOMUX Controller + +The Cygnus IOMUX controller supports group based mux configuration. In +addition, certain pins can be muxed to GPIO function individually. + +Required properties: + +- compatible: + Must be "brcm,cygnus-pinmux" + +- reg: + Define the base and range of the I/O address space that contains the Cygnus +IOMUX registers + +Properties in subnodes: + +- function: + The mux function to select + +- groups: + The list of groups to select with a given function + +For more details, refer to +Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + +For example: + + pinmux: pinmux@0x0301d0c8 { + compatible = "brcm,cygnus-pinmux"; + reg = <0x0301d0c8 0x1b0>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_default>; + + i2s0_default: i2s0_default { + mux { + function = "i2s0"; + groups = "i2s0_0_grp", "i2s0_1_grp"; + }; + }; + }; + +List of supported functions and groups in Cygnus: + +"i2s0": "i2s0_0_grp", "i2s0_1_grp" + +"i2s1": "i2s1_0_grp", "i2s1_1_grp" + +"i2s2": "i2s2_0_grp", "i2s2_1_grp", "i2s2_2_grp", "i2s2_3_grp", "i2s2_4_grp" + +"spdif": "spdif_grp" + +"pwm0": "pwm0_grp" + +"pwm1": "pwm1_grp" + +"pwm2": "pwm2_grp" + +"pwm3": "pwm3_grp" + +"pwm4": "pwm4_grp" + +"pwm5": "pwm5_grp" + +"key": "key0_grp", "key1_grp", "key2_grp", "key3_grp", "key4_grp", "key5_grp", +"key6_grp", "key7_grp", "key8_grp", "key9_grp", "key10_grp", "key11_grp", +"key12_grp", "key13_grp", "key14_grp", "key15_grp" + +"audio_dte": "audio_dte0_grp", "audio_dte1_grp", "audio_dte2_grp", "audio_dte3_grp" + +"smart_card0": "smart_card0_grp", "smart_card0_fcb_grp" + +"smart_card1": "smart_card1_grp", "smart_card1_fcb_grp" + +"spi0": "spi0_grp" + +"spi1": "spi1_grp" + +"spi2": "spi2_grp" + +"spi3": "spi3_grp" + +"spi4": "spi4_0_grp", "spi4_1_grp" + +"spi5": "spi5_grp" + +"sw_led0": "sw_led0_0_grp", "sw_led0_1_grp" + +"sw_led1": "sw_led1_grp" + +"sw_led2": "sw_led2_0_grp", "sw_led2_1_grp" + +"d1w": "d1w_grp" + +"lcd": "lcd_grp" + +"sram": "sram_0_grp", "sram_1_grp" + +"uart0": "uart0_grp" + +"uart1": "uart1_grp", "uart1_dte_grp" + +"uart2": "uart2_grp" + +"uart3": "uart3_grp" + +"uart4": "uart4_grp" + +"qspi": "qspi_0_grp", "qspi_1_grp" + +"nand": "nand_grp" + +"sdio0": "sdio0_grp", "sdio0_cd_grp", "sdio0_mmc_grp" + +"sdio1": "sdio1_data_0_grp", "sdio1_data_1_grp", "sdio1_cd_grp", +"sdio1_led_grp", "sdio1_mmc_grp" + +"can0": "can0_grp" + +"can1": "can1_grp" + +"cam": "cam_led_grp", "cam_0_grp", "cam_1_grp" + +"bsc1": "bsc1_grp" + +"pcie_clkreq": "pcie_clkreq_grp" + +"usb0_oc": "usb0_oc_grp" + +"usb1_oc": "usb1_oc_grp" + +"usb2_oc": "usb2_oc_grp" diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt new file mode 100644 index 000000000000..5b1a9dc004f4 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -0,0 +1,78 @@ +* Marvell Armada 39x SoC pinctrl driver for mpp + +Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding +part and usage. + +Required properties: +- compatible: "marvell,88f6920-pinctrl", "marvell,88f6928-pinctrl" + depending on the specific variant of the SoC being used. +- reg: register specifier of MPP registers + +Available mpp pins/groups and functions: +Note: brackets (x) are not part of the mpp name for marvell,function and given +only for more detailed description in this document. + +name pins functions +================================================================================ +mpp0 0 gpio, ua0(rxd) +mpp1 1 gpio, ua0(txd) +mpp2 2 gpio, i2c0(sck) +mpp3 3 gpio, i2c0(sda) +mpp4 4 gpio, ua1(txd), ua0(rts), smi(mdc) +mpp5 5 gpio, ua1(rxd), ua0(cts), smi(mdio) +mpp6 6 gpio, dev(cs3), xsmi(mdio) +mpp7 7 gpio, dev(ad9), xsmi(mdc) +mpp8 8 gpio, dev(ad10), ptp(trig) +mpp9 9 gpio, dev(ad11), ptp(clk) +mpp10 10 gpio, dev(ad12), ptp(event) +mpp11 11 gpio, dev(ad13), led(clk) +mpp12 12 gpio, pcie0(rstout), dev(ad14), led(stb) +mpp13 13 gpio, dev(ad15), led(data) +mpp14 14 gpio, m(vtt), dev(wen1), ua1(txd) +mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck) +mpp16 16 gpio, m(decc), spi0(miso), i2c1(sda) +mpp17 17 gpio, ua1(rxd), spi0(sck), smi(mdio) +mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck) +mpp19 19 gpio, sata1(present) [1], ua0(cts), ua1(rxd), i2c2(sda) +mpp20 20 gpio, sata0(present) [1], ua0(rts), ua1(txd), smi(mdc) +mpp21 21 gpio, spi0(cs1), sata0(present) [1], sd(cmd), dev(bootcs), ge(rxd0) +mpp22 22 gpio, spi0(mosi), dev(ad0) +mpp23 23 gpio, spi0(sck), dev(ad2) +mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd(d4), dev(readyn) +mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd(d5), dev(cs0) +mpp26 26 gpio, spi0(cs2), i2c1(sck), sd(d6), dev(cs1) +mpp27 27 gpio, spi0(cs3), i2c1(sda), sd(d7), dev(cs2), ge(txclkout) +mpp28 28 gpio, sd(clk), dev(ad5), ge(txd0) +mpp29 29 gpio, dev(ale0), ge(txd1) +mpp30 30 gpio, dev(oen), ge(txd2) +mpp31 31 gpio, dev(ale1), ge(txd3) +mpp32 32 gpio, dev(wen0), ge(txctl) +mpp33 33 gpio, m(decc), dev(ad3) +mpp34 34 gpio, dev(ad1) +mpp35 35 gpio, ref(clk), dev(a1) +mpp36 36 gpio, dev(a0) +mpp37 37 gpio, sd(d3), dev(ad8), ge(rxclk) +mpp38 38 gpio, ref(clk), sd(d0), dev(ad4), ge(rxd1) +mpp39 39 gpio, i2c1(sck), ua0(cts), sd(d1), dev(a2), ge(rxd2) +mpp40 40 gpio, i2c1(sda), ua0(rts), sd(d2), dev(ad6), ge(rxd3) +mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burstn), nd(rbn0), ge(rxctl) +mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) +mpp43 43 gpio, pcie0(clkreq), m(vtt), m(decc), spi1(cs2), dev(clkout), nd(rbn1) +mpp44 44 gpio, sata0(present) [1], sata1(present) [1], led(clk) +mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd) +mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb) +mpp47 47 gpio, sata0(present) [1], sata1(present) [1], led(data) +mpp48 48 gpio, sata0(present) [1], m(vtt), tdm(pclk) [1], audio(mclk) [1], sd(d4), pcie0(clkreq), ua1(txd) +mpp49 49 gpio, tdm(fsync) [1], audio(lrclk) [1], sd(d5), ua2(rxd) +mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd(cmd), ua2(rxd) +mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], m(decc), ua2(txd) +mpp52 52 gpio, pcie0(rstout), tdm(intn) [1], audio(sdi) [1], sd(d6), i2c3(sck) +mpp53 53 gpio, sata1(present) [1], sata0(present) [1], tdm(rstn) [1], audio(bclk) [1], sd(d7), i2c3(sda) +mpp54 54 gpio, sata0(present) [1], sata1(present) [1], pcie0(rstout), sd(d3), ua3(txd) +mpp55 55 gpio, ua1(cts), spi1(cs1), sd(d0), ua1(rxd), ua3(rxd) +mpp56 56 gpio, ua1(rts), m(decc), spi1(mosi), ua1(txd) +mpp57 57 gpio, spi1(sck), sd(clk), ua1(txd) +mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd(d1), ua1(rxd) +mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd(d2) + +[1]: only available on 88F6928 diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt index 17e7240c6998..3f6a524cc5ff 100644 --- a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt @@ -1,7 +1,7 @@ == Amlogic Meson pinmux controller == Required properties for the root node: - - compatible: "amlogic,meson8-pinctrl" + - compatible: "amlogic,meson8-pinctrl" or "amlogic,meson8b-pinctrl" - reg: address and size of registers controlling irq functionality === GPIO sub-nodes === diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt new file mode 100644 index 000000000000..a62d82d5fbe9 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt @@ -0,0 +1,166 @@ +NVIDIA Tegra210 pinmux controller + +Required properties: +- compatible: "nvidia,tegra210-pinmux" +- reg: Should contain a list of base address and size pairs for: + - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control) + - second entry: The PINMUX_AUX_* registers (pinmux) + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Tegra's pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, tristate, drive strength, etc. + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function or tristate parameter. For this +reason, even seemingly boolean values are actually tristates in this binding: +unspecified, off, or on. Unspecified is represented as an absent property, +and off/on are represented as integer values 0 and 1. + +See the TRM to determine which properties and values apply to each pin/group. +Macro values for property values are defined in +include/dt-binding/pinctrl/pinctrl-tegra.h. + +Required subnode-properties: +- nvidia,pins : An array of strings. Each string contains the name of a pin or + group. Valid values for these names are listed below. + +Optional subnode-properties: +- nvidia,function: A string containing the name of the function to mux to the + pin or group. +- nvidia,pull: Integer, representing the pull-down/up to apply to the pin. + 0: none, 1: down, 2: up. +- nvidia,tristate: Integer. + 0: drive, 1: tristate. +- nvidia,enable-input: Integer. Enable the pin's input path. + enable :TEGRA_PIN_ENABLE0 and + disable or output only: TEGRA_PIN_DISABLE. +- nvidia,open-drain: Integer. + enable: TEGRA_PIN_ENABLE. + disable: TEGRA_PIN_DISABLE. +- nvidia,lock: Integer. Lock the pin configuration against further changes + until reset. + enable: TEGRA_PIN_ENABLE. + disable: TEGRA_PIN_DISABLE. +- nvidia,io-hv: Integer. Select high-voltage receivers. + normal: TEGRA_PIN_DISABLE + high: TEGRA_PIN_ENABLE +- nvidia,high-speed-mode: Integer. Enable high speed mode the pins. + normal: TEGRA_PIN_DISABLE + high: TEGRA_PIN_ENABLE +- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input. + normal: TEGRA_PIN_DISABLE + high: TEGRA_PIN_ENABLE +- nvidia,drive-type: Integer. Valid range 0...3. +- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest. + The range of valid values depends on the pingroup. See "CAL_DRVDN" in the + Tegra TRM. +- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest. + The range of valid values depends on the pingroup. See "CAL_DRVUP" in the + Tegra TRM. +- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is + fastest. The range of valid values depends on the pingroup. See + "DRVDN_SLWR" in the Tegra TRM. +- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is + fastest. The range of valid values depends on the pingroup. See + "DRVUP_SLWF" in the Tegra TRM. + +Valid values for pin and group names (nvidia,pin) are: + + Mux groups: + + These correspond to Tegra PINMUX_AUX_* (pinmux) registers. Any property + that exists in those registers may be set for the following pin names. + + In Tegra210, many pins also have a dedicated APB_MISC_GP_*_PADCTRL + register. Where that is true, and property that exists in that register + may also be set on the following pin names. + + als_prox_int_px3, ap_ready_pv5, ap_wake_bt_ph3, ap_wake_nfc_ph7, + aud_mclk_pbb0, batt_bcl, bt_rst_ph4, bt_wake_ap_ph5, button_home_py1, + button_power_on_px5, button_slide_sw_py0, button_vol_down_px7, + button_vol_up_px6, cam1_mclk_ps0, cam1_pwdn_ps7, cam1_strobe_pt1, + cam2_mclk_ps1, cam2_pwdn_pt0, cam_af_en_ps5, cam_flash_en_ps6, + cam_i2c_scl_ps2, cam_i2c_sda_ps3, cam_rst_ps4cam_rst_ps4, clk_32k_in, + clk_32k_out_py5, clk_req, core_pwr_req, cpu_pwr_req, dap1_din_pb1, + dap1_dout_pb2, dap1_fs_pb0, dap1_sclk_pb3, dap2_din_paa2, dap2_dout_paa3, + dap2_fs_paa0, dap2_sclk_paa1, dap4_din_pj5, dap4_dout_pj6, dap4_fs_pj4, + dap4_sclk_pj7, dmic1_clk_pe0, dmic1_dat_pe1, dmic2_clk_pe2, dmic2_dat_pe3, + dmic3_clk_pe4, dmic3_dat_pe5, dp_hpd0_pcc6, dvfs_clk_pbb2, dvfs_pwm_pbb1, + gen1_i2c_scl_pj1, gen1_i2c_sda_pj0, gen2_i2c_scl_pj2, gen2_i2c_sda_pj3, + gen3_i2c_scl_pf0, gen3_i2c_sda_pf1, gpio_x1_aud_pbb3, gpio_x3_aud_pbb4, + gps_en_pi2, gps_rst_pi3, hdmi_cec_pcc0, hdmi_int_dp_hpd_pcc1, jtag_rtck, + lcd_bl_en_pv1, lcd_bl_pwm_pv0, lcd_gpio1_pv3, lcd_gpio2_pv4, lcd_rst_pv2, + lcd_te_py2, modem_wake_ap_px0, motion_int_px2, nfc_en_pi0, nfc_int_pi1, + pa6, pcc7, pe6, pe7, pex_l0_clkreq_n_pa1, pex_l0_rst_n_pa0, + pex_l1_clkreq_n_pa4, pex_l1_rst_n_pa3, pex_wake_n_pa2, ph6, pk0, pk1, pk2, + pk3, pk4, pk5, pk6, pk7, pl0, pl1, pwr_i2c_scl_py3, pwr_i2c_sda_py4, + pwr_int_n, pz0, pz1, pz2, pz3, pz4, pz5, qspi_cs_n_pee1, qspi_io0_pee2, + qspi_io1_pee3, qspi_io2_pee4, qspi_io3_pee5, qspi_sck_pee0, + sata_led_active_pa5, sdmmc1_clk_pm0, sdmmc1_cmd_pm1, sdmmc1_dat0_pm5, + sdmmc1_dat1_pm4, sdmmc1_dat2_pm3, sdmmc1_dat3_pm2, sdmmc3_clk_pp0, + sdmmc3_cmd_pp1, sdmmc3_dat0_pp5, sdmmc3_dat1_pp4, sdmmc3_dat2_pp3, + sdmmc3_dat3_pp2, shutdown, spdif_in_pcc3, spdif_out_pcc2, spi1_cs0_pc3, + spi1_cs1_pc4, spi1_miso_pc1, spi1_mosi_pc0, spi1_sck_pc2, spi2_cs0_pb7, + spi2_cs1_pdd0, spi2_miso_pb5, spi2_mosi_pb4, spi2_sck_pb6, spi4_cs0_pc6, + spi4_miso_pd0, spi4_mosi_pc7, spi4_sck_pc5, temp_alert_px4, touch_clk_pv7, + touch_int_px1, touch_rst_pv6, uart1_cts_pu3, uart1_rts_pu2, uart1_rx_pu1, + uart1_tx_pu0, uart2_cts_pg3, uart2_rts_pg2, uart2_rx_pg1, uart2_tx_pg0, + uart3_cts_pd4, uart3_rts_pd3, uart3_rx_pd2, uart3_tx_pd1, uart4_cts_pi7, + uart4_rts_pi6, uart4_rx_pi5, uart4_tx_pi4, usb_vbus_en0_pcc4, + usb_vbus_en1_pcc5, wifi_en_ph0, wifi_rst_ph1, wifi_wake_ap_ph2 + + Drive groups: + + These correspond to the Tegra APB_MISC_GP_*_PADCTRL (pad control) + registers. Note that where one of these registers controls a single pin + for which a PINMUX_AUX_* exists, see the list above for the pin name to + use when configuring the pinmux. + + pa6, pcc7, pe6, pe7, ph6, pk0, pk1, pk2, pk3, pk4, pk5, pk6, pk7, pl0, pl1, + pz0, pz1, pz2, pz3, pz4, pz5, sdmmc1, sdmmc2, sdmmc3, sdmmc4 + +Valid values for nvidia,functions are: + + aud, bcl, blink, ccla, cec, cldvfs, clk, core, cpu, displaya, displayb, + dmic1, dmic2, dmic3, dp, dtv, extperiph3, i2c1, i2c2, i2c3, i2cpmu, i2cvi, + i2s1, i2s2, i2s3, i2s4a, i2s4b, i2s5a, i2s5b, iqc0, iqc1, jtag, pe, pe0, + pe1, pmi, pwm0, pwm1, pwm2, pwm3, qspi, rsvd0, rsvd1, rsvd2, rsvd3, sata, + sdmmc1, sdmmc3, shutdown, soc, sor0, sor1, spdif, spi1, spi2, spi3, spi4, + sys, touch, uart, uarta, uartb, uartc, uartd, usb, vgp1, vgp2, vgp3, vgp4, + vgp5, vgp6, vimclk, vimclk2 + +Example: + + pinmux: pinmux@70000800 { + compatible = "nvidia,tegra210-pinmux"; + reg = <0x0 0x700008d4 0x0 0x2a8>, /* Pad control registers */ + <0x0 0x70003000 0x0 0x1000>; /* Mux registers */ + + pinctrl-names = "boot"; + pinctrl-0 = <&state_boot>; + + state_boot: pinmux { + gen1_i2c_scl_pj1 { + nvidia,pins = "gen1_i2c_scl_pj1", + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,io-hv = <TEGRA_PIN_ENABLE>; + }; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt index 47d84b6ee91b..b73c96d24f59 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt @@ -38,7 +38,7 @@ property exists to define the pin configuration. Each state may also be assigned a name. When names are used, another property exists to map from those names to the integer IDs. -Each client device's own binding determines the set of states the must be +Each client device's own binding determines the set of states that must be defined in its device tree node, and whether to define the set of state IDs that must be provided, or whether to define the set of state names that must be provided. @@ -133,16 +133,27 @@ pin multiplexing nodes: function - the mux function to select groups - the list of groups to select with this function + (either this or "pins" must be specified) +pins - the list of pins to select with this function (either + this or "groups" must be specified) Example: state_0_node_a { - function = "uart0"; - groups = "u0rxtx", "u0rtscts"; + uart0 { + function = "uart0"; + groups = "u0rxtx", "u0rtscts"; + }; }; state_1_node_a { - function = "spi0"; - groups = "spi0pins"; + spi0 { + function = "spi0"; + groups = "spi0pins"; + }; +}; +state_2_node_a { + function = "i2c0"; + pins = "mfio29", "mfio30"; }; == Generic pin configuration node content == @@ -188,16 +199,22 @@ slew-rate - set the slew rate For example: state_0_node_a { - pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ - bias-pull-up; + cts_rxd { + pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ + bias-pull-up; + }; }; state_1_node_a { - pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */ - output-high; + rts_txd { + pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */ + output-high; + }; }; state_2_node_a { - group = "foo-group"; - bias-pull-up; + foo { + group = "foo-group"; + bias-pull-up; + }; }; Some of the generic properties take arguments. For those that do, the diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt new file mode 100644 index 000000000000..5868a0f7255d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt @@ -0,0 +1,145 @@ +* Mediatek MT65XX Pin Controller + +The Mediatek's Pin controller is used to control SoC pins. + +Required properties: +- compatible: value should be either of the following. + (a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl. +- mediatek,pctl-regmap: Should be a phandle of the syscfg node. +- pins-are-numbered: Specify the subnodes are using numbered pinmux to + specify pins. +- gpio-controller : Marks the device node as a gpio controller. +- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + + Eg: <&pio 6 0> + <[phandle of the gpio controller node] + [line number within the gpio controller] + [flags]> + + Values for gpio specifier: + - Line number: is a value between 0 to 202. + - Flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>. + Only the following flags are supported: + 0 - GPIO_ACTIVE_HIGH + 1 - GPIO_ACTIVE_LOW +- reg: physicall address base for EINT registers +- interrupt-controller: Marks the device node as an interrupt controller +- #interrupt-cells: Should be two. +- interrupts : The interrupt outputs from the controller. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices. + +Subnode format +A pinctrl node should contain at least one subnodes representing the +pinctrl groups available on the machine. Each subnode will list the +pins it needs, and how they should be configured, with regard to muxer +configuration, pullups, drive strength, input enable/disable and input schmitt. + + node { + pinmux = <PIN_NUMBER_PINMUX>; + GENERIC_PINCONFIG; + }; + +Required properties: +- pinmux: integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are defined + as macros in boot/dts/<soc>-pinfunc.h directly. + +Optional properties: +- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable, + bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, output-high, + input-schmitt-enable, input-schmitt-disable and drive-strength are valid. + + Some special pins have extra pull up strength, there are R0 and R1 pull-up + resistors available, but for user, it's only need to set R1R0 as 00, 01, 10 or 11. + So when config bias-pull-up, it support arguments for those special pins. + Some macros have been defined for this usage, such as MTK_PUPD_SET_R1R0_00. + See dt-bindings/pinctrl/mt65xx.h. + + When config drive-strength, it can support some arguments, such as + MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h. + +Examples: + +#include "mt8135-pinfunc.h" + +... +{ + syscfg_pctl_a: syscfg_pctl_a@10005000 { + compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + + syscfg_pctl_b: syscfg_pctl_b@1020C020 { + compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon"; + reg = <0 0x1020C020 0 0x1000>; + }; + + pinctrl@01c20800 { + compatible = "mediatek,mt8135-pinctrl"; + reg = <0 0x1000B000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + + i2c0_pins_a: i2c0@0 { + pins1 { + pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>, + <MT8135_PIN_101_SCL0__FUNC_SCL0>; + bias-disable; + }; + }; + + i2c1_pins_a: i2c1@0 { + pins { + pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>, + <MT8135_PIN_196_SCL1__FUNC_SCL1>; + bias-pull-up = <55>; + }; + }; + + i2c2_pins_a: i2c2@0 { + pins1 { + pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>; + bias-pull-down; + }; + + pins2 { + pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>; + bias-pull-up; + }; + }; + + i2c3_pins_a: i2c3@0 { + pins1 { + pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>, + <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>; + bias-pull-up = <55>; + }; + + pins2 { + pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>, + <MT8135_PIN_36_SDA3__FUNC_SDA3>; + output-low; + bias-pull-up = <55>; + }; + + pins3 { + pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>, + <MT8135_PIN_60_JTDI__FUNC_JTDI>; + drive-strength = <32>; + }; + }; + + ... + } +}; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt index 7ed08048516a..1ae63c0acd40 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt @@ -10,6 +10,7 @@ PMIC's from Qualcomm. "qcom,pm8018-gpio" "qcom,pm8038-gpio" "qcom,pm8058-gpio" + "qcom,pm8916-gpio" "qcom,pm8917-gpio" "qcom,pm8921-gpio" "qcom,pm8941-gpio" @@ -74,6 +75,7 @@ to specify in a pin configuration subnode: gpio1-gpio6 for pm8018 gpio1-gpio12 for pm8038 gpio1-gpio40 for pm8058 + gpio1-gpio4 for pm8916 gpio1-gpio38 for pm8917 gpio1-gpio44 for pm8921 gpio1-gpio36 for pm8941 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt index 854774b194ed..ed19991aad35 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt @@ -8,6 +8,7 @@ of PMIC's from Qualcomm. Value type: <string> Definition: Should contain one of: "qcom,pm8841-mpp", + "qcom,pm8916-mpp", "qcom,pm8941-mpp", "qcom,pma8084-mpp", @@ -67,6 +68,7 @@ to specify in a pin configuration subnode: Definition: List of MPP pins affected by the properties specified in this subnode. Valid pins are: mpp1-mpp4 for pm8841 + mpp1-mpp4 for pm8916 mpp1-mpp8 for pm8941 mpp1-mpp4 for pma8084 diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt index b8f2147b96dd..a9b47163bb5d 100644 --- a/Documentation/pinctrl.txt +++ b/Documentation/pinctrl.txt @@ -72,7 +72,6 @@ static struct pinctrl_desc foo_desc = { .name = "foo", .pins = foo_pins, .npins = ARRAY_SIZE(foo_pins), - .maxpin = 63, .owner = THIS_MODULE, }; @@ -164,8 +163,8 @@ static const char *foo_get_group_name(struct pinctrl_dev *pctldev, } static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, - unsigned ** const pins, - unsigned * const num_pins) + const unsigned **pins, + unsigned *num_pins) { *pins = (unsigned *) foo_groups[selector].pins; *num_pins = foo_groups[selector].num_pins; @@ -570,9 +569,8 @@ is possible to perform the requested mux setting, poke the hardware so that this happens. Pinmux drivers are required to supply a few callback functions, some are -optional. Usually the enable() and disable() functions are implemented, -writing values into some certain registers to activate a certain mux setting -for a certain pin. +optional. Usually the set_mux() function is implemented, writing values into +some certain registers to activate a certain mux setting for a certain pin. A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4 into some register named MUX to select a certain function with a certain @@ -683,12 +681,12 @@ static const struct foo_pmx_func foo_functions[] = { }, }; -int foo_get_functions_count(struct pinctrl_dev *pctldev) +static int foo_get_functions_count(struct pinctrl_dev *pctldev) { return ARRAY_SIZE(foo_functions); } -const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector) +static const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector) { return foo_functions[selector].name; } @@ -702,7 +700,7 @@ static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector, return 0; } -int foo_set_mux(struct pinctrl_dev *pctldev, unsigned selector, +static int foo_set_mux(struct pinctrl_dev *pctldev, unsigned selector, unsigned group) { u8 regbit = (1 << selector + group); @@ -711,7 +709,7 @@ int foo_set_mux(struct pinctrl_dev *pctldev, unsigned selector, return 0; } -struct pinmux_ops foo_pmxops = { +static struct pinmux_ops foo_pmxops = { .get_functions_count = foo_get_functions_count, .get_function_name = foo_get_fname, .get_function_groups = foo_get_groups, @@ -1266,7 +1264,7 @@ The semantics of the pinctrl APIs are: Usually the pin control core handled the get/put pair and call out to the device drivers bookkeeping operations, like checking available functions and -the associated pins, whereas the enable/disable pass on to the pin controller +the associated pins, whereas select_state pass on to the pin controller driver which takes care of activating and/or deactivating the mux setting by quickly poking some registers. @@ -1363,8 +1361,9 @@ function, but with different named in the mapping as described under "Advanced mapping" above. So that for an SPI device, we have two states named "pos-A" and "pos-B". -This snippet first muxes the function in the pins defined by group A, enables -it, disables and releases it, and muxes it in on the pins defined by group B: +This snippet first initializes a state object for both groups (in foo_probe()), +then muxes the function in the pins defined by group A, and finally muxes it in +on the pins defined by group B: #include <linux/pinctrl/consumer.h> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index ee9f44ad7f02..c6f299ba25cb 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -67,23 +67,20 @@ config PINCTRL_AT91 help Say Y here to enable the at91 pinctrl driver -config PINCTRL_BCM2835 - bool - select PINMUX - select PINCONF - -config PINCTRL_BCM281XX - bool "Broadcom BCM281xx pinctrl driver" - depends on OF && (ARCH_BCM_MOBILE || COMPILE_TEST) - select PINMUX +config PINCTRL_AMD + bool "AMD GPIO pin control" + depends on GPIOLIB + select GPIOLIB_IRQCHIP select PINCONF select GENERIC_PINCONF - select REGMAP_MMIO help - Say Y here to support Broadcom BCM281xx pinctrl driver, which is used - for the BCM281xx SoC family, including BCM11130, BCM11140, BCM11351, - BCM28145, and BCM28155 SoCs. This driver requires the pinctrl - framework. GPIO is provided by a separate GPIO driver. + driver for memory mapped GPIO functionality on AMD platforms + (x86 or arm).Most pins are usually muxed to some other + functionality by firmware,so only a small amount is available + for gpio use. + + Requires ACPI/FDT device enumeration code to set up a platform + device. config PINCTRL_LANTIQ bool @@ -154,6 +151,10 @@ config PINCTRL_TEGRA124 bool select PINCTRL_TEGRA +config PINCTRL_TEGRA210 + bool + select PINCTRL_TEGRA + config PINCTRL_TEGRA_XUSB def_bool y if ARCH_TEGRA select GENERIC_PHY @@ -207,6 +208,7 @@ config PINCTRL_ZYNQ help This selectes the pinctrl driver for Xilinx Zynq. +source "drivers/pinctrl/bcm/Kconfig" source "drivers/pinctrl/berlin/Kconfig" source "drivers/pinctrl/freescale/Kconfig" source "drivers/pinctrl/intel/Kconfig" @@ -218,6 +220,7 @@ source "drivers/pinctrl/sh-pfc/Kconfig" source "drivers/pinctrl/spear/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" source "drivers/pinctrl/vt8500/Kconfig" +source "drivers/pinctrl/mediatek/Kconfig" config PINCTRL_XWAY bool diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 0475206dd600..6eadf04a33b3 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -14,8 +14,7 @@ obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o -obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o -obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o +obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o obj-$(CONFIG_PINCTRL_MESON) += meson/ obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o @@ -27,6 +26,7 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o obj-$(CONFIG_PINCTRL_TEGRA124) += pinctrl-tegra124.o +obj-$(CONFIG_PINCTRL_TEGRA210) += pinctrl-tegra210.o obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o @@ -38,6 +38,7 @@ obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o +obj-$(CONFIG_ARCH_BCM) += bcm/ obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-y += freescale/ obj-$(CONFIG_X86) += intel/ @@ -49,3 +50,4 @@ obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/ obj-$(CONFIG_PLAT_SPEAR) += spear/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_ARCH_VT8500) += vt8500/ +obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig new file mode 100644 index 000000000000..cd11d4d9ad58 --- /dev/null +++ b/drivers/pinctrl/bcm/Kconfig @@ -0,0 +1,56 @@ +# +# Broadcom pinctrl drivers +# + +config PINCTRL_BCM281XX + bool "Broadcom BCM281xx pinctrl driver" + depends on OF && (ARCH_BCM_MOBILE || COMPILE_TEST) + select PINMUX + select PINCONF + select GENERIC_PINCONF + select REGMAP_MMIO + help + Say Y here to support Broadcom BCM281xx pinctrl driver, which is used + for the BCM281xx SoC family, including BCM11130, BCM11140, BCM11351, + BCM28145, and BCM28155 SoCs. This driver requires the pinctrl + framework. GPIO is provided by a separate GPIO driver. + +config PINCTRL_BCM2835 + bool + select PINMUX + select PINCONF + +config PINCTRL_CYGNUS_GPIO + bool "Broadcom Cygnus GPIO (with PINCONF) driver" + depends on OF_GPIO && ARCH_BCM_CYGNUS + select GPIOLIB_IRQCHIP + select PINCONF + select GENERIC_PINCONF + default ARCH_BCM_CYGNUS + help + Say yes here to enable the Broadcom Cygnus GPIO driver. + + The Broadcom Cygnus SoC has 3 GPIO controllers including the ASIU + GPIO controller (ASIU), the chipCommonG GPIO controller (CCM), and + the always-ON GPIO controller (CRMU/AON). All 3 GPIO controllers are + supported by this driver. + + All 3 Cygnus GPIO controllers support basic PINCONF functions such + as bias pull up, pull down, and drive strength configurations, when + these pins are muxed to GPIO. + + Pins from the ASIU GPIO can be individually muxed to GPIO function, + through interaction with the Cygnus IOMUX controller. + +config PINCTRL_CYGNUS_MUX + bool "Broadcom Cygnus IOMUX driver" + depends on (ARCH_BCM_CYGNUS || COMPILE_TEST) + select PINMUX + select GENERIC_PINCONF + default ARCH_BCM_CYGNUS + help + Say yes here to enable the Broadcom Cygnus IOMUX driver. + + The Broadcom Cygnus IOMUX driver supports group based IOMUX + configuration, with the exception that certain individual pins + can be overrided to GPIO function diff --git a/drivers/pinctrl/bcm/Makefile b/drivers/pinctrl/bcm/Makefile new file mode 100644 index 000000000000..2b2f70ee804c --- /dev/null +++ b/drivers/pinctrl/bcm/Makefile @@ -0,0 +1,6 @@ +# Broadcom pinctrl support + +obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o +obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o +obj-$(CONFIG_PINCTRL_CYGNUS_GPIO) += pinctrl-cygnus-gpio.o +obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o diff --git a/drivers/pinctrl/pinctrl-bcm281xx.c b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c index b88cfe5ed55a..9641f1c7617e 100644 --- a/drivers/pinctrl/pinctrl-bcm281xx.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c @@ -21,8 +21,8 @@ #include <linux/pinctrl/pinconf-generic.h> #include <linux/regmap.h> #include <linux/slab.h> -#include "core.h" -#include "pinctrl-utils.h" +#include "../core.h" +#include "../pinctrl-utils.h" /* BCM281XX Pin Control Registers Definitions */ diff --git a/drivers/pinctrl/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index 9aa8a3f10b10..8d908e3f42c3 100644 --- a/drivers/pinctrl/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -403,15 +403,7 @@ static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id) gpio = (32 * bank) + offset; type = pc->irq_type[gpio]; - /* ack edge triggered IRQs immediately */ - if (!(type & IRQ_TYPE_LEVEL_MASK)) - bcm2835_gpio_set_bit(pc, GPEDS0, gpio); - generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio)); - - /* ack level triggered IRQ after handling them */ - if (type & IRQ_TYPE_LEVEL_MASK) - bcm2835_gpio_set_bit(pc, GPEDS0, gpio); } return events ? IRQ_HANDLED : IRQ_NONE; } @@ -591,16 +583,32 @@ static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type) else ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type); + if (type & IRQ_TYPE_EDGE_BOTH) + __irq_set_handler_locked(data->irq, handle_edge_irq); + else + __irq_set_handler_locked(data->irq, handle_level_irq); + spin_unlock_irqrestore(&pc->irq_lock[bank], flags); return ret; } +static void bcm2835_gpio_irq_ack(struct irq_data *data) +{ + struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data); + unsigned gpio = irqd_to_hwirq(data); + + bcm2835_gpio_set_bit(pc, GPEDS0, gpio); +} + static struct irq_chip bcm2835_gpio_irq_chip = { .name = MODULE_NAME, .irq_enable = bcm2835_gpio_irq_enable, .irq_disable = bcm2835_gpio_irq_disable, .irq_set_type = bcm2835_gpio_irq_set_type, + .irq_ack = bcm2835_gpio_irq_ack, + .irq_mask = bcm2835_gpio_irq_disable, + .irq_unmask = bcm2835_gpio_irq_enable, }; static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev) @@ -977,7 +985,7 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) int irq = irq_create_mapping(pc->irq_domain, i); irq_set_lockdep_class(irq, &gpio_lock_class); irq_set_chip_and_handler(irq, &bcm2835_gpio_irq_chip, - handle_simple_irq); + handle_level_irq); irq_set_chip_data(irq, pc); set_irq_flags(irq, IRQF_VALID); } @@ -1051,7 +1059,7 @@ static int bcm2835_pinctrl_remove(struct platform_device *pdev) return 0; } -static struct of_device_id bcm2835_pinctrl_match[] = { +static const struct of_device_id bcm2835_pinctrl_match[] = { { .compatible = "brcm,bcm2835-gpio" }, {} }; diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c new file mode 100644 index 000000000000..4ad5c1a996e3 --- /dev/null +++ b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c @@ -0,0 +1,907 @@ +/* + * Copyright (C) 2014-2015 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * This file contains the Broadcom Cygnus GPIO driver that supports 3 + * GPIO controllers on Cygnus including the ASIU GPIO controller, the + * chipCommonG GPIO controller, and the always-on GPIO controller. Basic + * PINCONF such as bias pull up/down, and drive strength are also supported + * in this driver. + * + * Pins from the ASIU GPIO can be individually muxed to GPIO function, + * through the interaction with the Cygnus IOMUX controller + */ + +#include <linux/kernel.h> +#include <linux/slab.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/ioport.h> +#include <linux/of_device.h> +#include <linux/of_irq.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> + +#include "../pinctrl-utils.h" + +#define CYGNUS_GPIO_DATA_IN_OFFSET 0x00 +#define CYGNUS_GPIO_DATA_OUT_OFFSET 0x04 +#define CYGNUS_GPIO_OUT_EN_OFFSET 0x08 +#define CYGNUS_GPIO_IN_TYPE_OFFSET 0x0c +#define CYGNUS_GPIO_INT_DE_OFFSET 0x10 +#define CYGNUS_GPIO_INT_EDGE_OFFSET 0x14 +#define CYGNUS_GPIO_INT_MSK_OFFSET 0x18 +#define CYGNUS_GPIO_INT_STAT_OFFSET 0x1c +#define CYGNUS_GPIO_INT_MSTAT_OFFSET 0x20 +#define CYGNUS_GPIO_INT_CLR_OFFSET 0x24 +#define CYGNUS_GPIO_PAD_RES_OFFSET 0x34 +#define CYGNUS_GPIO_RES_EN_OFFSET 0x38 + +/* drive strength control for ASIU GPIO */ +#define CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58 + +/* drive strength control for CCM/CRMU (AON) GPIO */ +#define CYGNUS_GPIO_DRV0_CTRL_OFFSET 0x00 + +#define GPIO_BANK_SIZE 0x200 +#define NGPIOS_PER_BANK 32 +#define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK) + +#define CYGNUS_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg)) +#define CYGNUS_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK) + +#define GPIO_DRV_STRENGTH_BIT_SHIFT 20 +#define GPIO_DRV_STRENGTH_BITS 3 +#define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1) + +/* + * Cygnus GPIO core + * + * @dev: pointer to device + * @base: I/O register base for Cygnus GPIO controller + * @io_ctrl: I/O register base for certain type of Cygnus GPIO controller that + * has the PINCONF support implemented outside of the GPIO block + * @lock: lock to protect access to I/O registers + * @gc: GPIO chip + * @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs + * @pinmux_is_supported: flag to indicate this GPIO controller contains pins + * that can be individually muxed to GPIO + * @pctl: pointer to pinctrl_dev + * @pctldesc: pinctrl descriptor + */ +struct cygnus_gpio { + struct device *dev; + + void __iomem *base; + void __iomem *io_ctrl; + + spinlock_t lock; + + struct gpio_chip gc; + unsigned num_banks; + + bool pinmux_is_supported; + + struct pinctrl_dev *pctl; + struct pinctrl_desc pctldesc; +}; + +static inline struct cygnus_gpio *to_cygnus_gpio(struct gpio_chip *gc) +{ + return container_of(gc, struct cygnus_gpio, gc); +} + +/* + * Mapping from PINCONF pins to GPIO pins is 1-to-1 + */ +static inline unsigned cygnus_pin_to_gpio(unsigned pin) +{ + return pin; +} + +/** + * cygnus_set_bit - set or clear one bit (corresponding to the GPIO pin) in a + * Cygnus GPIO register + * + * @cygnus_gpio: Cygnus GPIO device + * @reg: register offset + * @gpio: GPIO pin + * @set: set or clear + */ +static inline void cygnus_set_bit(struct cygnus_gpio *chip, unsigned int reg, + unsigned gpio, bool set) +{ + unsigned int offset = CYGNUS_GPIO_REG(gpio, reg); + unsigned int shift = CYGNUS_GPIO_SHIFT(gpio); + u32 val; + + val = readl(chip->base + offset); + if (set) + val |= BIT(shift); + else + val &= ~BIT(shift); + writel(val, chip->base + offset); +} + +static inline bool cygnus_get_bit(struct cygnus_gpio *chip, unsigned int reg, + unsigned gpio) +{ + unsigned int offset = CYGNUS_GPIO_REG(gpio, reg); + unsigned int shift = CYGNUS_GPIO_SHIFT(gpio); + + return !!(readl(chip->base + offset) & BIT(shift)); +} + +static void cygnus_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct irq_chip *irq_chip = irq_desc_get_chip(desc); + int i, bit; + + chained_irq_enter(irq_chip, desc); + + /* go through the entire GPIO banks and handle all interrupts */ + for (i = 0; i < chip->num_banks; i++) { + unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) + + CYGNUS_GPIO_INT_MSTAT_OFFSET); + + for_each_set_bit(bit, &val, NGPIOS_PER_BANK) { + unsigned pin = NGPIOS_PER_BANK * i + bit; + int child_irq = irq_find_mapping(gc->irqdomain, pin); + + /* + * Clear the interrupt before invoking the + * handler, so we do not leave any window + */ + writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) + + CYGNUS_GPIO_INT_CLR_OFFSET); + + generic_handle_irq(child_irq); + } + } + + chained_irq_exit(irq_chip, desc); +} + + +static void cygnus_gpio_irq_ack(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct cygnus_gpio *chip = to_cygnus_gpio(gc); + unsigned gpio = d->hwirq; + unsigned int offset = CYGNUS_GPIO_REG(gpio, + CYGNUS_GPIO_INT_CLR_OFFSET); + unsigned int shift = CYGNUS_GPIO_SHIFT(gpio); + u32 val = BIT(shift); + + writel(val, chip->base + offset); +} + +/** + * cygnus_gpio_irq_set_mask - mask/unmask a GPIO interrupt + * + * @d: IRQ chip data + * @unmask: mask/unmask GPIO interrupt + */ +static void cygnus_gpio_irq_set_mask(struct irq_data *d, bool unmask) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct cygnus_gpio *chip = to_cygnus_gpio(gc); + unsigned gpio = d->hwirq; + + cygnus_set_bit(chip, CYGNUS_GPIO_INT_MSK_OFFSET, gpio, unmask); +} + +static void cygnus_gpio_irq_mask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct cygnus_gpio *chip = to_cygnus_gpio(gc); + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + cygnus_gpio_irq_set_mask(d, false); + spin_unlock_irqrestore(&chip->lock, flags); +} + +static void cygnus_gpio_irq_unmask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct cygnus_gpio *chip = to_cygnus_gpio(gc); + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + cygnus_gpio_irq_set_mask(d, true); + spin_unlock_irqrestore(&chip->lock, flags); +} + +static int cygnus_gpio_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct cygnus_gpio *chip = to_cygnus_gpio(gc); + unsigned gpio = d->hwirq; + bool level_triggered = false; + bool dual_edge = false; + bool rising_or_high = false; + unsigned long flags; + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_RISING: + rising_or_high = true; + break; + + case IRQ_TYPE_EDGE_FALLING: + break; + + case IRQ_TYPE_EDGE_BOTH: + dual_edge = true; + break; + + case IRQ_TYPE_LEVEL_HIGH: + level_triggered = true; + rising_or_high = true; + break; + + case IRQ_TYPE_LEVEL_LOW: + level_triggered = true; + break; + + default: + dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n", + type); + return -EINVAL; + } + + spin_lock_irqsave(&chip->lock, flags); + cygnus_set_bit(chip, CYGNUS_GPIO_IN_TYPE_OFFSET, gpio, + level_triggered); + cygnus_set_bit(chip, CYGNUS_GPIO_INT_DE_OFFSET, gpio, dual_edge); + cygnus_set_bit(chip, CYGNUS_GPIO_INT_EDGE_OFFSET, gpio, + rising_or_high); + spin_unlock_irqrestore(&chip->lock, flags); + + dev_dbg(chip->dev, + "gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n", + gpio, level_triggered, dual_edge, rising_or_high); + + return 0; +} + +static struct irq_chip cygnus_gpio_irq_chip = { + .name = "bcm-cygnus-gpio", + .irq_ack = cygnus_gpio_irq_ack, + .irq_mask = cygnus_gpio_irq_mask, + .irq_unmask = cygnus_gpio_irq_unmask, + .irq_set_type = cygnus_gpio_irq_set_type, +}; + +/* + * Request the Cygnus IOMUX pinmux controller to mux individual pins to GPIO + */ +static int cygnus_gpio_request(struct gpio_chip *gc, unsigned offset) +{ + struct cygnus_gpio *chip = to_cygnus_gpio(gc); + unsigned gpio = gc->base + offset; + + /* not all Cygnus GPIO pins can be muxed individually */ + if (!chip->pinmux_is_supported) + return 0; + + return pinctrl_request_gpio(gpio); +} + +static void cygnus_gpio_free(struct gpio_chip *gc, unsigned offset) +{ + struct cygnus_gpio *chip = to_cygnus_gpio(gc); + unsigned gpio = gc->base + offset; + + if (!chip->pinmux_is_supported) + return; + + pinctrl_free_gpio(gpio); +} + +static int cygnus_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) +{ + struct cygnus_gpio *chip = to_cygnus_gpio(gc); + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + cygnus_set_bit(chip, CYGNUS_GPIO_OUT_EN_OFFSET, gpio, false); + spin_unlock_irqrestore(&chip->lock, flags); + + dev_dbg(chip->dev, "gpio:%u set input\n", gpio); + + return 0; +} + +static int cygnus_gpio_direction_output(struct gpio_chip *gc, unsigned gpio, + int val) +{ + struct cygnus_gpio *chip = to_cygnus_gpio(gc); + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + cygnus_set_bit(chip, CYGNUS_GPIO_OUT_EN_OFFSET, gpio, true); + cygnus_set_bit(chip, CYGNUS_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); + spin_unlock_irqrestore(&chip->lock, flags); + + dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val); + + return 0; +} + +static void cygnus_gpio_set(struct gpio_chip *gc, unsigned gpio, int val) +{ + struct cygnus_gpio *chip = to_cygnus_gpio(gc); + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + cygnus_set_bit(chip, CYGNUS_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); + spin_unlock_irqrestore(&chip->lock, flags); + + dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val); +} + +static int cygnus_gpio_get(struct gpio_chip *gc, unsigned gpio) +{ + struct cygnus_gpio *chip = to_cygnus_gpio(gc); + unsigned int offset = CYGNUS_GPIO_REG(gpio, + CYGNUS_GPIO_DATA_IN_OFFSET); + unsigned int shift = CYGNUS_GPIO_SHIFT(gpio); + + return !!(readl(chip->base + offset) & BIT(shift)); +} + +static int cygnus_get_groups_count(struct pinctrl_dev *pctldev) +{ + return 1; +} + +/* + * Only one group: "gpio_grp", since this local pinctrl device only performs + * GPIO specific PINCONF configurations + */ +static const char *cygnus_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return "gpio_grp"; +} + +static const struct pinctrl_ops cygnus_pctrl_ops = { + .get_groups_count = cygnus_get_groups_count, + .get_group_name = cygnus_get_group_name, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int cygnus_gpio_set_pull(struct cygnus_gpio *chip, unsigned gpio, + bool disable, bool pull_up) +{ + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + + if (disable) { + cygnus_set_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio, false); + } else { + cygnus_set_bit(chip, CYGNUS_GPIO_PAD_RES_OFFSET, gpio, + pull_up); + cygnus_set_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio, true); + } + + spin_unlock_irqrestore(&chip->lock, flags); + + dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up); + + return 0; +} + +static void cygnus_gpio_get_pull(struct cygnus_gpio *chip, unsigned gpio, + bool *disable, bool *pull_up) +{ + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + *disable = !cygnus_get_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio); + *pull_up = cygnus_get_bit(chip, CYGNUS_GPIO_PAD_RES_OFFSET, gpio); + spin_unlock_irqrestore(&chip->lock, flags); +} + +static int cygnus_gpio_set_strength(struct cygnus_gpio *chip, unsigned gpio, + unsigned strength) +{ + void __iomem *base; + unsigned int i, offset, shift; + u32 val; + unsigned long flags; + + /* make sure drive strength is supported */ + if (strength < 2 || strength > 16 || (strength % 2)) + return -ENOTSUPP; + + if (chip->io_ctrl) { + base = chip->io_ctrl; + offset = CYGNUS_GPIO_DRV0_CTRL_OFFSET; + } else { + base = chip->base; + offset = CYGNUS_GPIO_REG(gpio, + CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET); + } + + shift = CYGNUS_GPIO_SHIFT(gpio); + + dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio, + strength); + + spin_lock_irqsave(&chip->lock, flags); + strength = (strength / 2) - 1; + for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) { + val = readl(base + offset); + val &= ~BIT(shift); + val |= ((strength >> i) & 0x1) << shift; + writel(val, base + offset); + offset += 4; + } + spin_unlock_irqrestore(&chip->lock, flags); + + return 0; +} + +static int cygnus_gpio_get_strength(struct cygnus_gpio *chip, unsigned gpio, + u16 *strength) +{ + void __iomem *base; + unsigned int i, offset, shift; + u32 val; + unsigned long flags; + + if (chip->io_ctrl) { + base = chip->io_ctrl; + offset = CYGNUS_GPIO_DRV0_CTRL_OFFSET; + } else { + base = chip->base; + offset = CYGNUS_GPIO_REG(gpio, + CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET); + } + + shift = CYGNUS_GPIO_SHIFT(gpio); + + spin_lock_irqsave(&chip->lock, flags); + *strength = 0; + for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) { + val = readl(base + offset) & BIT(shift); + val >>= shift; + *strength += (val << i); + offset += 4; + } + + /* convert to mA */ + *strength = (*strength + 1) * 2; + spin_unlock_irqrestore(&chip->lock, flags); + + return 0; +} + +static int cygnus_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *config) +{ + struct cygnus_gpio *chip = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + unsigned gpio = cygnus_pin_to_gpio(pin); + u16 arg; + bool disable, pull_up; + int ret; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + cygnus_gpio_get_pull(chip, gpio, &disable, &pull_up); + if (disable) + return 0; + else + return -EINVAL; + + case PIN_CONFIG_BIAS_PULL_UP: + cygnus_gpio_get_pull(chip, gpio, &disable, &pull_up); + if (!disable && pull_up) + return 0; + else + return -EINVAL; + + case PIN_CONFIG_BIAS_PULL_DOWN: + cygnus_gpio_get_pull(chip, gpio, &disable, &pull_up); + if (!disable && !pull_up) + return 0; + else + return -EINVAL; + + case PIN_CONFIG_DRIVE_STRENGTH: + ret = cygnus_gpio_get_strength(chip, gpio, &arg); + if (ret) + return ret; + else + *config = pinconf_to_config_packed(param, arg); + + return 0; + + default: + return -ENOTSUPP; + } + + return -ENOTSUPP; +} + +static int cygnus_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *configs, unsigned num_configs) +{ + struct cygnus_gpio *chip = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param; + u16 arg; + unsigned i, gpio = cygnus_pin_to_gpio(pin); + int ret = -ENOTSUPP; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + ret = cygnus_gpio_set_pull(chip, gpio, true, false); + if (ret < 0) + goto out; + break; + + case PIN_CONFIG_BIAS_PULL_UP: + ret = cygnus_gpio_set_pull(chip, gpio, false, true); + if (ret < 0) + goto out; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + ret = cygnus_gpio_set_pull(chip, gpio, false, false); + if (ret < 0) + goto out; + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + ret = cygnus_gpio_set_strength(chip, gpio, arg); + if (ret < 0) + goto out; + break; + + default: + dev_err(chip->dev, "invalid configuration\n"); + return -ENOTSUPP; + } + } /* for each config */ + +out: + return ret; +} + +static const struct pinconf_ops cygnus_pconf_ops = { + .is_generic = true, + .pin_config_get = cygnus_pin_config_get, + .pin_config_set = cygnus_pin_config_set, +}; + +/* + * Map a GPIO in the local gpio_chip pin space to a pin in the Cygnus IOMUX + * pinctrl pin space + */ +struct cygnus_gpio_pin_range { + unsigned offset; + unsigned pin_base; + unsigned num_pins; +}; + +#define CYGNUS_PINRANGE(o, p, n) { .offset = o, .pin_base = p, .num_pins = n } + +/* + * Pin mapping table for mapping local GPIO pins to Cygnus IOMUX pinctrl pins + */ +static const struct cygnus_gpio_pin_range cygnus_gpio_pintable[] = { + CYGNUS_PINRANGE(0, 42, 1), + CYGNUS_PINRANGE(1, 44, 3), + CYGNUS_PINRANGE(4, 48, 1), + CYGNUS_PINRANGE(5, 50, 3), + CYGNUS_PINRANGE(8, 126, 1), + CYGNUS_PINRANGE(9, 155, 1), + CYGNUS_PINRANGE(10, 152, 1), + CYGNUS_PINRANGE(11, 154, 1), + CYGNUS_PINRANGE(12, 153, 1), + CYGNUS_PINRANGE(13, 127, 3), + CYGNUS_PINRANGE(16, 140, 1), + CYGNUS_PINRANGE(17, 145, 7), + CYGNUS_PINRANGE(24, 130, 10), + CYGNUS_PINRANGE(34, 141, 4), + CYGNUS_PINRANGE(38, 54, 1), + CYGNUS_PINRANGE(39, 56, 3), + CYGNUS_PINRANGE(42, 60, 3), + CYGNUS_PINRANGE(45, 64, 3), + CYGNUS_PINRANGE(48, 68, 2), + CYGNUS_PINRANGE(50, 84, 6), + CYGNUS_PINRANGE(56, 94, 6), + CYGNUS_PINRANGE(62, 72, 1), + CYGNUS_PINRANGE(63, 70, 1), + CYGNUS_PINRANGE(64, 80, 1), + CYGNUS_PINRANGE(65, 74, 3), + CYGNUS_PINRANGE(68, 78, 1), + CYGNUS_PINRANGE(69, 82, 1), + CYGNUS_PINRANGE(70, 156, 17), + CYGNUS_PINRANGE(87, 104, 12), + CYGNUS_PINRANGE(99, 102, 2), + CYGNUS_PINRANGE(101, 90, 4), + CYGNUS_PINRANGE(105, 116, 10), + CYGNUS_PINRANGE(123, 11, 1), + CYGNUS_PINRANGE(124, 38, 4), + CYGNUS_PINRANGE(128, 43, 1), + CYGNUS_PINRANGE(129, 47, 1), + CYGNUS_PINRANGE(130, 49, 1), + CYGNUS_PINRANGE(131, 53, 1), + CYGNUS_PINRANGE(132, 55, 1), + CYGNUS_PINRANGE(133, 59, 1), + CYGNUS_PINRANGE(134, 63, 1), + CYGNUS_PINRANGE(135, 67, 1), + CYGNUS_PINRANGE(136, 71, 1), + CYGNUS_PINRANGE(137, 73, 1), + CYGNUS_PINRANGE(138, 77, 1), + CYGNUS_PINRANGE(139, 79, 1), + CYGNUS_PINRANGE(140, 81, 1), + CYGNUS_PINRANGE(141, 83, 1), + CYGNUS_PINRANGE(142, 10, 1) +}; + +/* + * The Cygnus IOMUX controller mainly supports group based mux configuration, + * but certain pins can be muxed to GPIO individually. Only the ASIU GPIO + * controller can support this, so it's an optional configuration + * + * Return -ENODEV means no support and that's fine + */ +static int cygnus_gpio_pinmux_add_range(struct cygnus_gpio *chip) +{ + struct device_node *node = chip->dev->of_node; + struct device_node *pinmux_node; + struct platform_device *pinmux_pdev; + struct gpio_chip *gc = &chip->gc; + int i, ret = 0; + + /* parse DT to find the phandle to the pinmux controller */ + pinmux_node = of_parse_phandle(node, "pinmux", 0); + if (!pinmux_node) + return -ENODEV; + + pinmux_pdev = of_find_device_by_node(pinmux_node); + /* no longer need the pinmux node */ + of_node_put(pinmux_node); + if (!pinmux_pdev) { + dev_err(chip->dev, "failed to get pinmux device\n"); + return -EINVAL; + } + + /* now need to create the mapping between local GPIO and PINMUX pins */ + for (i = 0; i < ARRAY_SIZE(cygnus_gpio_pintable); i++) { + ret = gpiochip_add_pin_range(gc, dev_name(&pinmux_pdev->dev), + cygnus_gpio_pintable[i].offset, + cygnus_gpio_pintable[i].pin_base, + cygnus_gpio_pintable[i].num_pins); + if (ret) { + dev_err(chip->dev, "unable to add GPIO pin range\n"); + goto err_put_device; + } + } + + chip->pinmux_is_supported = true; + + /* no need for pinmux_pdev device reference anymore */ + put_device(&pinmux_pdev->dev); + return 0; + +err_put_device: + put_device(&pinmux_pdev->dev); + gpiochip_remove_pin_ranges(gc); + return ret; +} + +/* + * Cygnus GPIO controller supports some PINCONF related configurations such as + * pull up, pull down, and drive strength, when the pin is configured to GPIO + * + * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the + * local GPIO pins + */ +static int cygnus_gpio_register_pinconf(struct cygnus_gpio *chip) +{ + struct pinctrl_desc *pctldesc = &chip->pctldesc; + struct pinctrl_pin_desc *pins; + struct gpio_chip *gc = &chip->gc; + int i; + + pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + + for (i = 0; i < gc->ngpio; i++) { + pins[i].number = i; + pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL, + "gpio-%d", i); + if (!pins[i].name) + return -ENOMEM; + } + + pctldesc->name = dev_name(chip->dev); + pctldesc->pctlops = &cygnus_pctrl_ops; + pctldesc->pins = pins; + pctldesc->npins = gc->ngpio; + pctldesc->confops = &cygnus_pconf_ops; + + chip->pctl = pinctrl_register(pctldesc, chip->dev, chip); + if (!chip->pctl) { + dev_err(chip->dev, "unable to register pinctrl device\n"); + return -EINVAL; + } + + return 0; +} + +static void cygnus_gpio_unregister_pinconf(struct cygnus_gpio *chip) +{ + if (chip->pctl) + pinctrl_unregister(chip->pctl); +} + +struct cygnus_gpio_data { + unsigned num_gpios; +}; + +static const struct cygnus_gpio_data cygnus_cmm_gpio_data = { + .num_gpios = 24, +}; + +static const struct cygnus_gpio_data cygnus_asiu_gpio_data = { + .num_gpios = 146, +}; + +static const struct cygnus_gpio_data cygnus_crmu_gpio_data = { + .num_gpios = 6, +}; + +static const struct of_device_id cygnus_gpio_of_match[] = { + { + .compatible = "brcm,cygnus-ccm-gpio", + .data = &cygnus_cmm_gpio_data, + }, + { + .compatible = "brcm,cygnus-asiu-gpio", + .data = &cygnus_asiu_gpio_data, + }, + { + .compatible = "brcm,cygnus-crmu-gpio", + .data = &cygnus_crmu_gpio_data, + } +}; + +static int cygnus_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *res; + struct cygnus_gpio *chip; + struct gpio_chip *gc; + u32 ngpios; + int irq, ret; + const struct of_device_id *match; + const struct cygnus_gpio_data *gpio_data; + + match = of_match_device(cygnus_gpio_of_match, dev); + if (!match) + return -ENODEV; + gpio_data = match->data; + ngpios = gpio_data->num_gpios; + + chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + chip->dev = dev; + platform_set_drvdata(pdev, chip); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + chip->base = devm_ioremap_resource(dev, res); + if (IS_ERR(chip->base)) { + dev_err(dev, "unable to map I/O memory\n"); + return PTR_ERR(chip->base); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res) { + chip->io_ctrl = devm_ioremap_resource(dev, res); + if (IS_ERR(chip->io_ctrl)) { + dev_err(dev, "unable to map I/O memory\n"); + return PTR_ERR(chip->io_ctrl); + } + } + + spin_lock_init(&chip->lock); + + gc = &chip->gc; + gc->base = -1; + gc->ngpio = ngpios; + chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK; + gc->label = dev_name(dev); + gc->dev = dev; + gc->of_node = dev->of_node; + gc->request = cygnus_gpio_request; + gc->free = cygnus_gpio_free; + gc->direction_input = cygnus_gpio_direction_input; + gc->direction_output = cygnus_gpio_direction_output; + gc->set = cygnus_gpio_set; + gc->get = cygnus_gpio_get; + + ret = gpiochip_add(gc); + if (ret < 0) { + dev_err(dev, "unable to add GPIO chip\n"); + return ret; + } + + ret = cygnus_gpio_pinmux_add_range(chip); + if (ret && ret != -ENODEV) { + dev_err(dev, "unable to add GPIO pin range\n"); + goto err_rm_gpiochip; + } + + ret = cygnus_gpio_register_pinconf(chip); + if (ret) { + dev_err(dev, "unable to register pinconf\n"); + goto err_rm_gpiochip; + } + + /* optional GPIO interrupt support */ + irq = platform_get_irq(pdev, 0); + if (irq) { + ret = gpiochip_irqchip_add(gc, &cygnus_gpio_irq_chip, 0, + handle_simple_irq, IRQ_TYPE_NONE); + if (ret) { + dev_err(dev, "no GPIO irqchip\n"); + goto err_unregister_pinconf; + } + + gpiochip_set_chained_irqchip(gc, &cygnus_gpio_irq_chip, irq, + cygnus_gpio_irq_handler); + } + + return 0; + +err_unregister_pinconf: + cygnus_gpio_unregister_pinconf(chip); + +err_rm_gpiochip: + gpiochip_remove(gc); + + return ret; +} + +static struct platform_driver cygnus_gpio_driver = { + .driver = { + .name = "cygnus-gpio", + .of_match_table = cygnus_gpio_of_match, + }, + .probe = cygnus_gpio_probe, +}; + +static int __init cygnus_gpio_init(void) +{ + return platform_driver_probe(&cygnus_gpio_driver, cygnus_gpio_probe); +} +arch_initcall_sync(cygnus_gpio_init); diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c b/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c new file mode 100644 index 000000000000..f9a9283caf81 --- /dev/null +++ b/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c @@ -0,0 +1,1022 @@ +/* Copyright (C) 2014-2015 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * This file contains the Cygnus IOMUX driver that supports group based PINMUX + * configuration. Although PINMUX configuration is mainly group based, the + * Cygnus IOMUX controller allows certain pins to be individually muxed to GPIO + * function, and therefore be controlled by the Cygnus ASIU GPIO controller + */ + +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/slab.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include "../core.h" +#include "../pinctrl-utils.h" + +#define CYGNUS_NUM_IOMUX_REGS 8 +#define CYGNUS_NUM_MUX_PER_REG 8 +#define CYGNUS_NUM_IOMUX (CYGNUS_NUM_IOMUX_REGS * \ + CYGNUS_NUM_MUX_PER_REG) + +/* + * Cygnus IOMUX register description + * + * @offset: register offset for mux configuration of a group + * @shift: bit shift for mux configuration of a group + * @alt: alternate function to set to + */ +struct cygnus_mux { + unsigned int offset; + unsigned int shift; + unsigned int alt; +}; + +/* + * Keep track of Cygnus IOMUX configuration and prevent double configuration + * + * @cygnus_mux: Cygnus IOMUX register description + * @is_configured: flag to indicate whether a mux setting has already been + * configured + */ +struct cygnus_mux_log { + struct cygnus_mux mux; + bool is_configured; +}; + +/* + * Group based IOMUX configuration + * + * @name: name of the group + * @pins: array of pins used by this group + * @num_pins: total number of pins used by this group + * @mux: Cygnus group based IOMUX configuration + */ +struct cygnus_pin_group { + const char *name; + const unsigned *pins; + unsigned num_pins; + struct cygnus_mux mux; +}; + +/* + * Cygnus mux function and supported pin groups + * + * @name: name of the function + * @groups: array of groups that can be supported by this function + * @num_groups: total number of groups that can be supported by this function + */ +struct cygnus_pin_function { + const char *name; + const char * const *groups; + unsigned num_groups; +}; + +/* + * Cygnus IOMUX pinctrl core + * + * @pctl: pointer to pinctrl_dev + * @dev: pointer to device + * @base0: first I/O register base of the Cygnus IOMUX controller + * @base1: second I/O register base + * @groups: pointer to array of groups + * @num_groups: total number of groups + * @functions: pointer to array of functions + * @num_functions: total number of functions + * @mux_log: pointer to the array of mux logs + * @lock: lock to protect register access + */ +struct cygnus_pinctrl { + struct pinctrl_dev *pctl; + struct device *dev; + void __iomem *base0; + void __iomem *base1; + + const struct cygnus_pin_group *groups; + unsigned num_groups; + + const struct cygnus_pin_function *functions; + unsigned num_functions; + + struct cygnus_mux_log *mux_log; + + spinlock_t lock; +}; + +/* + * Certain pins can be individually muxed to GPIO function + * + * @is_supported: flag to indicate GPIO mux is supported for this pin + * @offset: register offset for GPIO mux override of a pin + * @shift: bit shift for GPIO mux override of a pin + */ +struct cygnus_gpio_mux { + int is_supported; + unsigned int offset; + unsigned int shift; +}; + +/* + * Description of a pin in Cygnus + * + * @pin: pin number + * @name: pin name + * @gpio_mux: GPIO override related information + */ +struct cygnus_pin { + unsigned pin; + char *name; + struct cygnus_gpio_mux gpio_mux; +}; + +#define CYGNUS_PIN_DESC(p, n, i, o, s) \ +{ \ + .pin = p, \ + .name = n, \ + .gpio_mux = { \ + .is_supported = i, \ + .offset = o, \ + .shift = s, \ + }, \ +} + +/* + * List of pins in Cygnus + */ +static struct cygnus_pin cygnus_pins[] = { + CYGNUS_PIN_DESC(0, "ext_device_reset_n", 0, 0, 0), + CYGNUS_PIN_DESC(1, "chip_mode0", 0, 0, 0), + CYGNUS_PIN_DESC(2, "chip_mode1", 0, 0, 0), + CYGNUS_PIN_DESC(3, "chip_mode2", 0, 0, 0), + CYGNUS_PIN_DESC(4, "chip_mode3", 0, 0, 0), + CYGNUS_PIN_DESC(5, "chip_mode4", 0, 0, 0), + CYGNUS_PIN_DESC(6, "bsc0_scl", 0, 0, 0), + CYGNUS_PIN_DESC(7, "bsc0_sda", 0, 0, 0), + CYGNUS_PIN_DESC(8, "bsc1_scl", 0, 0, 0), + CYGNUS_PIN_DESC(9, "bsc1_sda", 0, 0, 0), + CYGNUS_PIN_DESC(10, "d1w_dq", 1, 0x28, 0), + CYGNUS_PIN_DESC(11, "d1wowstz_l", 1, 0x4, 28), + CYGNUS_PIN_DESC(12, "gpio0", 0, 0, 0), + CYGNUS_PIN_DESC(13, "gpio1", 0, 0, 0), + CYGNUS_PIN_DESC(14, "gpio2", 0, 0, 0), + CYGNUS_PIN_DESC(15, "gpio3", 0, 0, 0), + CYGNUS_PIN_DESC(16, "gpio4", 0, 0, 0), + CYGNUS_PIN_DESC(17, "gpio5", 0, 0, 0), + CYGNUS_PIN_DESC(18, "gpio6", 0, 0, 0), + CYGNUS_PIN_DESC(19, "gpio7", 0, 0, 0), + CYGNUS_PIN_DESC(20, "gpio8", 0, 0, 0), + CYGNUS_PIN_DESC(21, "gpio9", 0, 0, 0), + CYGNUS_PIN_DESC(22, "gpio10", 0, 0, 0), + CYGNUS_PIN_DESC(23, "gpio11", 0, 0, 0), + CYGNUS_PIN_DESC(24, "gpio12", 0, 0, 0), + CYGNUS_PIN_DESC(25, "gpio13", 0, 0, 0), + CYGNUS_PIN_DESC(26, "gpio14", 0, 0, 0), + CYGNUS_PIN_DESC(27, "gpio15", 0, 0, 0), + CYGNUS_PIN_DESC(28, "gpio16", 0, 0, 0), + CYGNUS_PIN_DESC(29, "gpio17", 0, 0, 0), + CYGNUS_PIN_DESC(30, "gpio18", 0, 0, 0), + CYGNUS_PIN_DESC(31, "gpio19", 0, 0, 0), + CYGNUS_PIN_DESC(32, "gpio20", 0, 0, 0), + CYGNUS_PIN_DESC(33, "gpio21", 0, 0, 0), + CYGNUS_PIN_DESC(34, "gpio22", 0, 0, 0), + CYGNUS_PIN_DESC(35, "gpio23", 0, 0, 0), + CYGNUS_PIN_DESC(36, "mdc", 0, 0, 0), + CYGNUS_PIN_DESC(37, "mdio", 0, 0, 0), + CYGNUS_PIN_DESC(38, "pwm0", 1, 0x10, 30), + CYGNUS_PIN_DESC(39, "pwm1", 1, 0x10, 28), + CYGNUS_PIN_DESC(40, "pwm2", 1, 0x10, 26), + CYGNUS_PIN_DESC(41, "pwm3", 1, 0x10, 24), + CYGNUS_PIN_DESC(42, "sc0_clk", 1, 0x10, 22), + CYGNUS_PIN_DESC(43, "sc0_cmdvcc_l", 1, 0x10, 20), + CYGNUS_PIN_DESC(44, "sc0_detect", 1, 0x10, 18), + CYGNUS_PIN_DESC(45, "sc0_fcb", 1, 0x10, 16), + CYGNUS_PIN_DESC(46, "sc0_io", 1, 0x10, 14), + CYGNUS_PIN_DESC(47, "sc0_rst_l", 1, 0x10, 12), + CYGNUS_PIN_DESC(48, "sc1_clk", 1, 0x10, 10), + CYGNUS_PIN_DESC(49, "sc1_cmdvcc_l", 1, 0x10, 8), + CYGNUS_PIN_DESC(50, "sc1_detect", 1, 0x10, 6), + CYGNUS_PIN_DESC(51, "sc1_fcb", 1, 0x10, 4), + CYGNUS_PIN_DESC(52, "sc1_io", 1, 0x10, 2), + CYGNUS_PIN_DESC(53, "sc1_rst_l", 1, 0x10, 0), + CYGNUS_PIN_DESC(54, "spi0_clk", 1, 0x18, 10), + CYGNUS_PIN_DESC(55, "spi0_mosi", 1, 0x18, 6), + CYGNUS_PIN_DESC(56, "spi0_miso", 1, 0x18, 8), + CYGNUS_PIN_DESC(57, "spi0_ss", 1, 0x18, 4), + CYGNUS_PIN_DESC(58, "spi1_clk", 1, 0x18, 2), + CYGNUS_PIN_DESC(59, "spi1_mosi", 1, 0x1c, 30), + CYGNUS_PIN_DESC(60, "spi1_miso", 1, 0x18, 0), + CYGNUS_PIN_DESC(61, "spi1_ss", 1, 0x1c, 28), + CYGNUS_PIN_DESC(62, "spi2_clk", 1, 0x1c, 26), + CYGNUS_PIN_DESC(63, "spi2_mosi", 1, 0x1c, 22), + CYGNUS_PIN_DESC(64, "spi2_miso", 1, 0x1c, 24), + CYGNUS_PIN_DESC(65, "spi2_ss", 1, 0x1c, 20), + CYGNUS_PIN_DESC(66, "spi3_clk", 1, 0x1c, 18), + CYGNUS_PIN_DESC(67, "spi3_mosi", 1, 0x1c, 14), + CYGNUS_PIN_DESC(68, "spi3_miso", 1, 0x1c, 16), + CYGNUS_PIN_DESC(69, "spi3_ss", 1, 0x1c, 12), + CYGNUS_PIN_DESC(70, "uart0_cts", 1, 0x1c, 10), + CYGNUS_PIN_DESC(71, "uart0_rts", 1, 0x1c, 8), + CYGNUS_PIN_DESC(72, "uart0_rx", 1, 0x1c, 6), + CYGNUS_PIN_DESC(73, "uart0_tx", 1, 0x1c, 4), + CYGNUS_PIN_DESC(74, "uart1_cts", 1, 0x1c, 2), + CYGNUS_PIN_DESC(75, "uart1_dcd", 1, 0x1c, 0), + CYGNUS_PIN_DESC(76, "uart1_dsr", 1, 0x20, 14), + CYGNUS_PIN_DESC(77, "uart1_dtr", 1, 0x20, 12), + CYGNUS_PIN_DESC(78, "uart1_ri", 1, 0x20, 10), + CYGNUS_PIN_DESC(79, "uart1_rts", 1, 0x20, 8), + CYGNUS_PIN_DESC(80, "uart1_rx", 1, 0x20, 6), + CYGNUS_PIN_DESC(81, "uart1_tx", 1, 0x20, 4), + CYGNUS_PIN_DESC(82, "uart3_rx", 1, 0x20, 2), + CYGNUS_PIN_DESC(83, "uart3_tx", 1, 0x20, 0), + CYGNUS_PIN_DESC(84, "sdio1_clk_sdcard", 1, 0x14, 6), + CYGNUS_PIN_DESC(85, "sdio1_cmd", 1, 0x14, 4), + CYGNUS_PIN_DESC(86, "sdio1_data0", 1, 0x14, 2), + CYGNUS_PIN_DESC(87, "sdio1_data1", 1, 0x14, 0), + CYGNUS_PIN_DESC(88, "sdio1_data2", 1, 0x18, 30), + CYGNUS_PIN_DESC(89, "sdio1_data3", 1, 0x18, 28), + CYGNUS_PIN_DESC(90, "sdio1_wp_n", 1, 0x18, 24), + CYGNUS_PIN_DESC(91, "sdio1_card_rst", 1, 0x14, 10), + CYGNUS_PIN_DESC(92, "sdio1_led_on", 1, 0x18, 26), + CYGNUS_PIN_DESC(93, "sdio1_cd", 1, 0x14, 8), + CYGNUS_PIN_DESC(94, "sdio0_clk_sdcard", 1, 0x14, 26), + CYGNUS_PIN_DESC(95, "sdio0_cmd", 1, 0x14, 24), + CYGNUS_PIN_DESC(96, "sdio0_data0", 1, 0x14, 22), + CYGNUS_PIN_DESC(97, "sdio0_data1", 1, 0x14, 20), + CYGNUS_PIN_DESC(98, "sdio0_data2", 1, 0x14, 18), + CYGNUS_PIN_DESC(99, "sdio0_data3", 1, 0x14, 16), + CYGNUS_PIN_DESC(100, "sdio0_wp_n", 1, 0x14, 12), + CYGNUS_PIN_DESC(101, "sdio0_card_rst", 1, 0x14, 30), + CYGNUS_PIN_DESC(102, "sdio0_led_on", 1, 0x14, 14), + CYGNUS_PIN_DESC(103, "sdio0_cd", 1, 0x14, 28), + CYGNUS_PIN_DESC(104, "sflash_clk", 1, 0x18, 22), + CYGNUS_PIN_DESC(105, "sflash_cs_l", 1, 0x18, 20), + CYGNUS_PIN_DESC(106, "sflash_mosi", 1, 0x18, 14), + CYGNUS_PIN_DESC(107, "sflash_miso", 1, 0x18, 16), + CYGNUS_PIN_DESC(108, "sflash_wp_n", 1, 0x18, 12), + CYGNUS_PIN_DESC(109, "sflash_hold_n", 1, 0x18, 18), + CYGNUS_PIN_DESC(110, "nand_ale", 1, 0xc, 30), + CYGNUS_PIN_DESC(111, "nand_ce0_l", 1, 0xc, 28), + CYGNUS_PIN_DESC(112, "nand_ce1_l", 1, 0xc, 26), + CYGNUS_PIN_DESC(113, "nand_cle", 1, 0xc, 24), + CYGNUS_PIN_DESC(114, "nand_dq0", 1, 0xc, 22), + CYGNUS_PIN_DESC(115, "nand_dq1", 1, 0xc, 20), + CYGNUS_PIN_DESC(116, "nand_dq2", 1, 0xc, 18), + CYGNUS_PIN_DESC(117, "nand_dq3", 1, 0xc, 16), + CYGNUS_PIN_DESC(118, "nand_dq4", 1, 0xc, 14), + CYGNUS_PIN_DESC(119, "nand_dq5", 1, 0xc, 12), + CYGNUS_PIN_DESC(120, "nand_dq6", 1, 0xc, 10), + CYGNUS_PIN_DESC(121, "nand_dq7", 1, 0xc, 8), + CYGNUS_PIN_DESC(122, "nand_rb_l", 1, 0xc, 6), + CYGNUS_PIN_DESC(123, "nand_re_l", 1, 0xc, 4), + CYGNUS_PIN_DESC(124, "nand_we_l", 1, 0xc, 2), + CYGNUS_PIN_DESC(125, "nand_wp_l", 1, 0xc, 0), + CYGNUS_PIN_DESC(126, "lcd_clac", 1, 0x4, 26), + CYGNUS_PIN_DESC(127, "lcd_clcp", 1, 0x4, 24), + CYGNUS_PIN_DESC(128, "lcd_cld0", 1, 0x4, 22), + CYGNUS_PIN_DESC(129, "lcd_cld1", 1, 0x4, 0), + CYGNUS_PIN_DESC(130, "lcd_cld10", 1, 0x4, 20), + CYGNUS_PIN_DESC(131, "lcd_cld11", 1, 0x4, 18), + CYGNUS_PIN_DESC(132, "lcd_cld12", 1, 0x4, 16), + CYGNUS_PIN_DESC(133, "lcd_cld13", 1, 0x4, 14), + CYGNUS_PIN_DESC(134, "lcd_cld14", 1, 0x4, 12), + CYGNUS_PIN_DESC(135, "lcd_cld15", 1, 0x4, 10), + CYGNUS_PIN_DESC(136, "lcd_cld16", 1, 0x4, 8), + CYGNUS_PIN_DESC(137, "lcd_cld17", 1, 0x4, 6), + CYGNUS_PIN_DESC(138, "lcd_cld18", 1, 0x4, 4), + CYGNUS_PIN_DESC(139, "lcd_cld19", 1, 0x4, 2), + CYGNUS_PIN_DESC(140, "lcd_cld2", 1, 0x8, 22), + CYGNUS_PIN_DESC(141, "lcd_cld20", 1, 0x8, 30), + CYGNUS_PIN_DESC(142, "lcd_cld21", 1, 0x8, 28), + CYGNUS_PIN_DESC(143, "lcd_cld22", 1, 0x8, 26), + CYGNUS_PIN_DESC(144, "lcd_cld23", 1, 0x8, 24), + CYGNUS_PIN_DESC(145, "lcd_cld3", 1, 0x8, 20), + CYGNUS_PIN_DESC(146, "lcd_cld4", 1, 0x8, 18), + CYGNUS_PIN_DESC(147, "lcd_cld5", 1, 0x8, 16), + CYGNUS_PIN_DESC(148, "lcd_cld6", 1, 0x8, 14), + CYGNUS_PIN_DESC(149, "lcd_cld7", 1, 0x8, 12), + CYGNUS_PIN_DESC(150, "lcd_cld8", 1, 0x8, 10), + CYGNUS_PIN_DESC(151, "lcd_cld9", 1, 0x8, 8), + CYGNUS_PIN_DESC(152, "lcd_clfp", 1, 0x8, 6), + CYGNUS_PIN_DESC(153, "lcd_clle", 1, 0x8, 4), + CYGNUS_PIN_DESC(154, "lcd_cllp", 1, 0x8, 2), + CYGNUS_PIN_DESC(155, "lcd_clpower", 1, 0x8, 0), + CYGNUS_PIN_DESC(156, "camera_vsync", 1, 0x4, 30), + CYGNUS_PIN_DESC(157, "camera_trigger", 1, 0x0, 0), + CYGNUS_PIN_DESC(158, "camera_strobe", 1, 0x0, 2), + CYGNUS_PIN_DESC(159, "camera_standby", 1, 0x0, 4), + CYGNUS_PIN_DESC(160, "camera_reset_n", 1, 0x0, 6), + CYGNUS_PIN_DESC(161, "camera_pixdata9", 1, 0x0, 8), + CYGNUS_PIN_DESC(162, "camera_pixdata8", 1, 0x0, 10), + CYGNUS_PIN_DESC(163, "camera_pixdata7", 1, 0x0, 12), + CYGNUS_PIN_DESC(164, "camera_pixdata6", 1, 0x0, 14), + CYGNUS_PIN_DESC(165, "camera_pixdata5", 1, 0x0, 16), + CYGNUS_PIN_DESC(166, "camera_pixdata4", 1, 0x0, 18), + CYGNUS_PIN_DESC(167, "camera_pixdata3", 1, 0x0, 20), + CYGNUS_PIN_DESC(168, "camera_pixdata2", 1, 0x0, 22), + CYGNUS_PIN_DESC(169, "camera_pixdata1", 1, 0x0, 24), + CYGNUS_PIN_DESC(170, "camera_pixdata0", 1, 0x0, 26), + CYGNUS_PIN_DESC(171, "camera_pixclk", 1, 0x0, 28), + CYGNUS_PIN_DESC(172, "camera_hsync", 1, 0x0, 30), + CYGNUS_PIN_DESC(173, "camera_pll_ref_clk", 0, 0, 0), + CYGNUS_PIN_DESC(174, "usb_id_indication", 0, 0, 0), + CYGNUS_PIN_DESC(175, "usb_vbus_indication", 0, 0, 0), + CYGNUS_PIN_DESC(176, "gpio0_3p3", 0, 0, 0), + CYGNUS_PIN_DESC(177, "gpio1_3p3", 0, 0, 0), + CYGNUS_PIN_DESC(178, "gpio2_3p3", 0, 0, 0), + CYGNUS_PIN_DESC(179, "gpio3_3p3", 0, 0, 0), +}; + +/* + * List of groups of pins + */ +static const unsigned bsc1_pins[] = { 8, 9 }; +static const unsigned pcie_clkreq_pins[] = { 8, 9 }; + +static const unsigned i2s2_0_pins[] = { 12 }; +static const unsigned i2s2_1_pins[] = { 13 }; +static const unsigned i2s2_2_pins[] = { 14 }; +static const unsigned i2s2_3_pins[] = { 15 }; +static const unsigned i2s2_4_pins[] = { 16 }; + +static const unsigned pwm4_pins[] = { 17 }; +static const unsigned pwm5_pins[] = { 18 }; + +static const unsigned key0_pins[] = { 20 }; +static const unsigned key1_pins[] = { 21 }; +static const unsigned key2_pins[] = { 22 }; +static const unsigned key3_pins[] = { 23 }; +static const unsigned key4_pins[] = { 24 }; +static const unsigned key5_pins[] = { 25 }; + +static const unsigned key6_pins[] = { 26 }; +static const unsigned audio_dte0_pins[] = { 26 }; + +static const unsigned key7_pins[] = { 27 }; +static const unsigned audio_dte1_pins[] = { 27 }; + +static const unsigned key8_pins[] = { 28 }; +static const unsigned key9_pins[] = { 29 }; +static const unsigned key10_pins[] = { 30 }; +static const unsigned key11_pins[] = { 31 }; +static const unsigned key12_pins[] = { 32 }; +static const unsigned key13_pins[] = { 33 }; + +static const unsigned key14_pins[] = { 34 }; +static const unsigned audio_dte2_pins[] = { 34 }; + +static const unsigned key15_pins[] = { 35 }; +static const unsigned audio_dte3_pins[] = { 35 }; + +static const unsigned pwm0_pins[] = { 38 }; +static const unsigned pwm1_pins[] = { 39 }; +static const unsigned pwm2_pins[] = { 40 }; +static const unsigned pwm3_pins[] = { 41 }; + +static const unsigned sdio0_pins[] = { 94, 95, 96, 97, 98, 99 }; + +static const unsigned smart_card0_pins[] = { 42, 43, 44, 46, 47 }; +static const unsigned i2s0_0_pins[] = { 42, 43, 44, 46 }; +static const unsigned spdif_pins[] = { 47 }; + +static const unsigned smart_card1_pins[] = { 48, 49, 50, 52, 53 }; +static const unsigned i2s1_0_pins[] = { 48, 49, 50, 52 }; + +static const unsigned spi0_pins[] = { 54, 55, 56, 57 }; + +static const unsigned spi1_pins[] = { 58, 59, 60, 61 }; + +static const unsigned spi2_pins[] = { 62, 63, 64, 65 }; + +static const unsigned spi3_pins[] = { 66, 67, 68, 69 }; +static const unsigned sw_led0_0_pins[] = { 66, 67, 68, 69 }; + +static const unsigned d1w_pins[] = { 10, 11 }; +static const unsigned uart4_pins[] = { 10, 11 }; +static const unsigned sw_led2_0_pins[] = { 10, 11 }; + +static const unsigned lcd_pins[] = { 126, 127, 128, 129, 130, 131, 132, 133, + 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, + 148, 149, 150, 151, 152, 153, 154, 155 }; +static const unsigned sram_0_pins[] = { 126, 127, 128, 129, 130, 131, 132, 133, + 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, + 148, 149, 150, 151, 152, 153, 154, 155 }; +static const unsigned spi5_pins[] = { 141, 142, 143, 144 }; + +static const unsigned uart0_pins[] = { 70, 71, 72, 73 }; +static const unsigned sw_led0_1_pins[] = { 70, 71, 72, 73 }; + +static const unsigned uart1_dte_pins[] = { 75, 76, 77, 78 }; +static const unsigned uart2_pins[] = { 75, 76, 77, 78 }; + +static const unsigned uart1_pins[] = { 74, 79, 80, 81 }; + +static const unsigned uart3_pins[] = { 82, 83 }; + +static const unsigned qspi_0_pins[] = { 104, 105, 106, 107 }; + +static const unsigned nand_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117, + 118, 119, 120, 121, 122, 123, 124, 125 }; + +static const unsigned sdio0_cd_pins[] = { 103 }; + +static const unsigned sdio0_mmc_pins[] = { 100, 101, 102 }; + +static const unsigned sdio1_data_0_pins[] = { 86, 87 }; +static const unsigned can0_pins[] = { 86, 87 }; +static const unsigned spi4_0_pins[] = { 86, 87 }; + +static const unsigned sdio1_data_1_pins[] = { 88, 89 }; +static const unsigned can1_pins[] = { 88, 89 }; +static const unsigned spi4_1_pins[] = { 88, 89 }; + +static const unsigned sdio1_cd_pins[] = { 93 }; + +static const unsigned sdio1_led_pins[] = { 84, 85 }; +static const unsigned sw_led2_1_pins[] = { 84, 85 }; + +static const unsigned sdio1_mmc_pins[] = { 90, 91, 92 }; + +static const unsigned cam_led_pins[] = { 156, 157, 158, 159, 160 }; +static const unsigned sw_led1_pins[] = { 156, 157, 158, 159 }; + +static const unsigned cam_0_pins[] = { 169, 170, 171, 169, 170 }; + +static const unsigned cam_1_pins[] = { 161, 162, 163, 164, 165, 166, 167, + 168 }; +static const unsigned sram_1_pins[] = { 161, 162, 163, 164, 165, 166, 167, + 168 }; + +static const unsigned qspi_1_pins[] = { 108, 109 }; + +static const unsigned smart_card0_fcb_pins[] = { 45 }; +static const unsigned i2s0_1_pins[] = { 45 }; + +static const unsigned smart_card1_fcb_pins[] = { 51 }; +static const unsigned i2s1_1_pins[] = { 51 }; + +static const unsigned gpio0_3p3_pins[] = { 176 }; +static const unsigned usb0_oc_pins[] = { 176 }; + +static const unsigned gpio1_3p3_pins[] = { 177 }; +static const unsigned usb1_oc_pins[] = { 177 }; + +static const unsigned gpio2_3p3_pins[] = { 178 }; +static const unsigned usb2_oc_pins[] = { 178 }; + +#define CYGNUS_PIN_GROUP(group_name, off, sh, al) \ +{ \ + .name = __stringify(group_name) "_grp", \ + .pins = group_name ## _pins, \ + .num_pins = ARRAY_SIZE(group_name ## _pins), \ + .mux = { \ + .offset = off, \ + .shift = sh, \ + .alt = al, \ + } \ +} + +/* + * List of Cygnus pin groups + */ +static const struct cygnus_pin_group cygnus_pin_groups[] = { + CYGNUS_PIN_GROUP(i2s2_0, 0x0, 0, 2), + CYGNUS_PIN_GROUP(i2s2_1, 0x0, 4, 2), + CYGNUS_PIN_GROUP(i2s2_2, 0x0, 8, 2), + CYGNUS_PIN_GROUP(i2s2_3, 0x0, 12, 2), + CYGNUS_PIN_GROUP(i2s2_4, 0x0, 16, 2), + CYGNUS_PIN_GROUP(pwm4, 0x0, 20, 0), + CYGNUS_PIN_GROUP(pwm5, 0x0, 24, 2), + CYGNUS_PIN_GROUP(key0, 0x4, 0, 1), + CYGNUS_PIN_GROUP(key1, 0x4, 4, 1), + CYGNUS_PIN_GROUP(key2, 0x4, 8, 1), + CYGNUS_PIN_GROUP(key3, 0x4, 12, 1), + CYGNUS_PIN_GROUP(key4, 0x4, 16, 1), + CYGNUS_PIN_GROUP(key5, 0x4, 20, 1), + CYGNUS_PIN_GROUP(key6, 0x4, 24, 1), + CYGNUS_PIN_GROUP(audio_dte0, 0x4, 24, 2), + CYGNUS_PIN_GROUP(key7, 0x4, 28, 1), + CYGNUS_PIN_GROUP(audio_dte1, 0x4, 28, 2), + CYGNUS_PIN_GROUP(key8, 0x8, 0, 1), + CYGNUS_PIN_GROUP(key9, 0x8, 4, 1), + CYGNUS_PIN_GROUP(key10, 0x8, 8, 1), + CYGNUS_PIN_GROUP(key11, 0x8, 12, 1), + CYGNUS_PIN_GROUP(key12, 0x8, 16, 1), + CYGNUS_PIN_GROUP(key13, 0x8, 20, 1), + CYGNUS_PIN_GROUP(key14, 0x8, 24, 1), + CYGNUS_PIN_GROUP(audio_dte2, 0x8, 24, 2), + CYGNUS_PIN_GROUP(key15, 0x8, 28, 1), + CYGNUS_PIN_GROUP(audio_dte3, 0x8, 28, 2), + CYGNUS_PIN_GROUP(pwm0, 0xc, 0, 0), + CYGNUS_PIN_GROUP(pwm1, 0xc, 4, 0), + CYGNUS_PIN_GROUP(pwm2, 0xc, 8, 0), + CYGNUS_PIN_GROUP(pwm3, 0xc, 12, 0), + CYGNUS_PIN_GROUP(sdio0, 0xc, 16, 0), + CYGNUS_PIN_GROUP(smart_card0, 0xc, 20, 0), + CYGNUS_PIN_GROUP(i2s0_0, 0xc, 20, 1), + CYGNUS_PIN_GROUP(spdif, 0xc, 20, 1), + CYGNUS_PIN_GROUP(smart_card1, 0xc, 24, 0), + CYGNUS_PIN_GROUP(i2s1_0, 0xc, 24, 1), + CYGNUS_PIN_GROUP(spi0, 0x10, 0, 0), + CYGNUS_PIN_GROUP(spi1, 0x10, 4, 0), + CYGNUS_PIN_GROUP(spi2, 0x10, 8, 0), + CYGNUS_PIN_GROUP(spi3, 0x10, 12, 0), + CYGNUS_PIN_GROUP(sw_led0_0, 0x10, 12, 2), + CYGNUS_PIN_GROUP(d1w, 0x10, 16, 0), + CYGNUS_PIN_GROUP(uart4, 0x10, 16, 1), + CYGNUS_PIN_GROUP(sw_led2_0, 0x10, 16, 2), + CYGNUS_PIN_GROUP(lcd, 0x10, 20, 0), + CYGNUS_PIN_GROUP(sram_0, 0x10, 20, 1), + CYGNUS_PIN_GROUP(spi5, 0x10, 20, 2), + CYGNUS_PIN_GROUP(uart0, 0x14, 0, 0), + CYGNUS_PIN_GROUP(sw_led0_1, 0x14, 0, 2), + CYGNUS_PIN_GROUP(uart1_dte, 0x14, 4, 0), + CYGNUS_PIN_GROUP(uart2, 0x14, 4, 1), + CYGNUS_PIN_GROUP(uart1, 0x14, 8, 0), + CYGNUS_PIN_GROUP(uart3, 0x14, 12, 0), + CYGNUS_PIN_GROUP(qspi_0, 0x14, 16, 0), + CYGNUS_PIN_GROUP(nand, 0x14, 20, 0), + CYGNUS_PIN_GROUP(sdio0_cd, 0x18, 0, 0), + CYGNUS_PIN_GROUP(sdio0_mmc, 0x18, 4, 0), + CYGNUS_PIN_GROUP(sdio1_data_0, 0x18, 8, 0), + CYGNUS_PIN_GROUP(can0, 0x18, 8, 1), + CYGNUS_PIN_GROUP(spi4_0, 0x18, 8, 2), + CYGNUS_PIN_GROUP(sdio1_data_1, 0x18, 12, 0), + CYGNUS_PIN_GROUP(can1, 0x18, 12, 1), + CYGNUS_PIN_GROUP(spi4_1, 0x18, 12, 2), + CYGNUS_PIN_GROUP(sdio1_cd, 0x18, 16, 0), + CYGNUS_PIN_GROUP(sdio1_led, 0x18, 20, 0), + CYGNUS_PIN_GROUP(sw_led2_1, 0x18, 20, 2), + CYGNUS_PIN_GROUP(sdio1_mmc, 0x18, 24, 0), + CYGNUS_PIN_GROUP(cam_led, 0x1c, 0, 0), + CYGNUS_PIN_GROUP(sw_led1, 0x1c, 0, 1), + CYGNUS_PIN_GROUP(cam_0, 0x1c, 4, 0), + CYGNUS_PIN_GROUP(cam_1, 0x1c, 8, 0), + CYGNUS_PIN_GROUP(sram_1, 0x1c, 8, 1), + CYGNUS_PIN_GROUP(qspi_1, 0x1c, 12, 0), + CYGNUS_PIN_GROUP(bsc1, 0x1c, 16, 0), + CYGNUS_PIN_GROUP(pcie_clkreq, 0x1c, 16, 1), + CYGNUS_PIN_GROUP(smart_card0_fcb, 0x20, 0, 0), + CYGNUS_PIN_GROUP(i2s0_1, 0x20, 0, 1), + CYGNUS_PIN_GROUP(smart_card1_fcb, 0x20, 4, 0), + CYGNUS_PIN_GROUP(i2s1_1, 0x20, 4, 1), + CYGNUS_PIN_GROUP(gpio0_3p3, 0x28, 0, 0), + CYGNUS_PIN_GROUP(usb0_oc, 0x28, 0, 1), + CYGNUS_PIN_GROUP(gpio1_3p3, 0x28, 4, 0), + CYGNUS_PIN_GROUP(usb1_oc, 0x28, 4, 1), + CYGNUS_PIN_GROUP(gpio2_3p3, 0x28, 8, 0), + CYGNUS_PIN_GROUP(usb2_oc, 0x28, 8, 1), +}; + +/* + * List of groups supported by functions + */ +static const char * const i2s0_grps[] = { "i2s0_0_grp", "i2s0_1_grp" }; +static const char * const i2s1_grps[] = { "i2s1_0_grp", "i2s1_1_grp" }; +static const char * const i2s2_grps[] = { "i2s2_0_grp", "i2s2_1_grp", + "i2s2_2_grp", "i2s2_3_grp", "i2s2_4_grp" }; +static const char * const spdif_grps[] = { "spdif_grp" }; +static const char * const pwm0_grps[] = { "pwm0_grp" }; +static const char * const pwm1_grps[] = { "pwm1_grp" }; +static const char * const pwm2_grps[] = { "pwm2_grp" }; +static const char * const pwm3_grps[] = { "pwm3_grp" }; +static const char * const pwm4_grps[] = { "pwm4_grp" }; +static const char * const pwm5_grps[] = { "pwm5_grp" }; +static const char * const key_grps[] = { "key0_grp", "key1_grp", "key2_grp", + "key3_grp", "key4_grp", "key5_grp", "key6_grp", "key7_grp", "key8_grp", + "key9_grp", "key10_grp", "key11_grp", "key12_grp", "key13_grp", + "key14_grp", "key15_grp" }; +static const char * const audio_dte_grps[] = { "audio_dte0_grp", + "audio_dte1_grp", "audio_dte2_grp", "audio_dte3_grp" }; +static const char * const smart_card0_grps[] = { "smart_card0_grp", + "smart_card0_fcb_grp" }; +static const char * const smart_card1_grps[] = { "smart_card1_grp", + "smart_card1_fcb_grp" }; +static const char * const spi0_grps[] = { "spi0_grp" }; +static const char * const spi1_grps[] = { "spi1_grp" }; +static const char * const spi2_grps[] = { "spi2_grp" }; +static const char * const spi3_grps[] = { "spi3_grp" }; +static const char * const spi4_grps[] = { "spi4_0_grp", "spi4_1_grp" }; +static const char * const spi5_grps[] = { "spi5_grp" }; + +static const char * const sw_led0_grps[] = { "sw_led0_0_grp", + "sw_led0_1_grp" }; +static const char * const sw_led1_grps[] = { "sw_led1_grp" }; +static const char * const sw_led2_grps[] = { "sw_led2_0_grp", + "sw_led2_1_grp" }; +static const char * const d1w_grps[] = { "d1w_grp" }; +static const char * const lcd_grps[] = { "lcd_grp" }; +static const char * const sram_grps[] = { "sram_0_grp", "sram_1_grp" }; + +static const char * const uart0_grps[] = { "uart0_grp" }; +static const char * const uart1_grps[] = { "uart1_grp", "uart1_dte_grp" }; +static const char * const uart2_grps[] = { "uart2_grp" }; +static const char * const uart3_grps[] = { "uart3_grp" }; +static const char * const uart4_grps[] = { "uart4_grp" }; +static const char * const qspi_grps[] = { "qspi_0_grp", "qspi_1_grp" }; +static const char * const nand_grps[] = { "nand_grp" }; +static const char * const sdio0_grps[] = { "sdio0_grp", "sdio0_cd_grp", + "sdio0_mmc_grp" }; +static const char * const sdio1_grps[] = { "sdio1_data_0_grp", + "sdio1_data_1_grp", "sdio1_cd_grp", "sdio1_led_grp", "sdio1_mmc_grp" }; +static const char * const can0_grps[] = { "can0_grp" }; +static const char * const can1_grps[] = { "can1_grp" }; +static const char * const cam_grps[] = { "cam_led_grp", "cam_0_grp", + "cam_1_grp" }; +static const char * const bsc1_grps[] = { "bsc1_grp" }; +static const char * const pcie_clkreq_grps[] = { "pcie_clkreq_grp" }; +static const char * const usb0_oc_grps[] = { "usb0_oc_grp" }; +static const char * const usb1_oc_grps[] = { "usb1_oc_grp" }; +static const char * const usb2_oc_grps[] = { "usb2_oc_grp" }; + +#define CYGNUS_PIN_FUNCTION(func) \ +{ \ + .name = #func, \ + .groups = func ## _grps, \ + .num_groups = ARRAY_SIZE(func ## _grps), \ +} + +/* + * List of supported functions in Cygnus + */ +static const struct cygnus_pin_function cygnus_pin_functions[] = { + CYGNUS_PIN_FUNCTION(i2s0), + CYGNUS_PIN_FUNCTION(i2s1), + CYGNUS_PIN_FUNCTION(i2s2), + CYGNUS_PIN_FUNCTION(spdif), + CYGNUS_PIN_FUNCTION(pwm0), + CYGNUS_PIN_FUNCTION(pwm1), + CYGNUS_PIN_FUNCTION(pwm2), + CYGNUS_PIN_FUNCTION(pwm3), + CYGNUS_PIN_FUNCTION(pwm4), + CYGNUS_PIN_FUNCTION(pwm5), + CYGNUS_PIN_FUNCTION(key), + CYGNUS_PIN_FUNCTION(audio_dte), + CYGNUS_PIN_FUNCTION(smart_card0), + CYGNUS_PIN_FUNCTION(smart_card1), + CYGNUS_PIN_FUNCTION(spi0), + CYGNUS_PIN_FUNCTION(spi1), + CYGNUS_PIN_FUNCTION(spi2), + CYGNUS_PIN_FUNCTION(spi3), + CYGNUS_PIN_FUNCTION(spi4), + CYGNUS_PIN_FUNCTION(spi5), + CYGNUS_PIN_FUNCTION(sw_led0), + CYGNUS_PIN_FUNCTION(sw_led1), + CYGNUS_PIN_FUNCTION(sw_led2), + CYGNUS_PIN_FUNCTION(d1w), + CYGNUS_PIN_FUNCTION(lcd), + CYGNUS_PIN_FUNCTION(sram), + CYGNUS_PIN_FUNCTION(uart0), + CYGNUS_PIN_FUNCTION(uart1), + CYGNUS_PIN_FUNCTION(uart2), + CYGNUS_PIN_FUNCTION(uart3), + CYGNUS_PIN_FUNCTION(uart4), + CYGNUS_PIN_FUNCTION(qspi), + CYGNUS_PIN_FUNCTION(nand), + CYGNUS_PIN_FUNCTION(sdio0), + CYGNUS_PIN_FUNCTION(sdio1), + CYGNUS_PIN_FUNCTION(can0), + CYGNUS_PIN_FUNCTION(can1), + CYGNUS_PIN_FUNCTION(cam), + CYGNUS_PIN_FUNCTION(bsc1), + CYGNUS_PIN_FUNCTION(pcie_clkreq), + CYGNUS_PIN_FUNCTION(usb0_oc), + CYGNUS_PIN_FUNCTION(usb1_oc), + CYGNUS_PIN_FUNCTION(usb2_oc), +}; + +static int cygnus_get_groups_count(struct pinctrl_dev *pctrl_dev) +{ + struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + + return pinctrl->num_groups; +} + +static const char *cygnus_get_group_name(struct pinctrl_dev *pctrl_dev, + unsigned selector) +{ + struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + + return pinctrl->groups[selector].name; +} + +static int cygnus_get_group_pins(struct pinctrl_dev *pctrl_dev, + unsigned selector, const unsigned **pins, + unsigned *num_pins) +{ + struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + + *pins = pinctrl->groups[selector].pins; + *num_pins = pinctrl->groups[selector].num_pins; + + return 0; +} + +static void cygnus_pin_dbg_show(struct pinctrl_dev *pctrl_dev, + struct seq_file *s, unsigned offset) +{ + seq_printf(s, " %s", dev_name(pctrl_dev->dev)); +} + +static const struct pinctrl_ops cygnus_pinctrl_ops = { + .get_groups_count = cygnus_get_groups_count, + .get_group_name = cygnus_get_group_name, + .get_group_pins = cygnus_get_group_pins, + .pin_dbg_show = cygnus_pin_dbg_show, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int cygnus_get_functions_count(struct pinctrl_dev *pctrl_dev) +{ + struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + + return pinctrl->num_functions; +} + +static const char *cygnus_get_function_name(struct pinctrl_dev *pctrl_dev, + unsigned selector) +{ + struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + + return pinctrl->functions[selector].name; +} + +static int cygnus_get_function_groups(struct pinctrl_dev *pctrl_dev, + unsigned selector, + const char * const **groups, + unsigned * const num_groups) +{ + struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + + *groups = pinctrl->functions[selector].groups; + *num_groups = pinctrl->functions[selector].num_groups; + + return 0; +} + +static int cygnus_pinmux_set(struct cygnus_pinctrl *pinctrl, + const struct cygnus_pin_function *func, + const struct cygnus_pin_group *grp, + struct cygnus_mux_log *mux_log) +{ + const struct cygnus_mux *mux = &grp->mux; + int i; + u32 val, mask = 0x7; + unsigned long flags; + + for (i = 0; i < CYGNUS_NUM_IOMUX; i++) { + if (mux->offset != mux_log[i].mux.offset || + mux->shift != mux_log[i].mux.shift) + continue; + + /* match found if we reach here */ + + /* if this is a new configuration, just do it! */ + if (!mux_log[i].is_configured) + break; + + /* + * IOMUX has been configured previously and one is trying to + * configure it to a different function + */ + if (mux_log[i].mux.alt != mux->alt) { + dev_err(pinctrl->dev, + "double configuration error detected!\n"); + dev_err(pinctrl->dev, "func:%s grp:%s\n", + func->name, grp->name); + return -EINVAL; + } else { + /* + * One tries to configure it to the same function. + * Just quit and don't bother + */ + return 0; + } + } + + mux_log[i].mux.alt = mux->alt; + mux_log[i].is_configured = true; + + spin_lock_irqsave(&pinctrl->lock, flags); + + val = readl(pinctrl->base0 + grp->mux.offset); + val &= ~(mask << grp->mux.shift); + val |= grp->mux.alt << grp->mux.shift; + writel(val, pinctrl->base0 + grp->mux.offset); + + spin_unlock_irqrestore(&pinctrl->lock, flags); + + return 0; +} + +static int cygnus_pinmux_set_mux(struct pinctrl_dev *pctrl_dev, + unsigned func_select, unsigned grp_select) +{ + struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + const struct cygnus_pin_function *func = + &pinctrl->functions[func_select]; + const struct cygnus_pin_group *grp = &pinctrl->groups[grp_select]; + + dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n", + func_select, func->name, grp_select, grp->name); + + dev_dbg(pctrl_dev->dev, "offset:0x%08x shift:%u alt:%u\n", + grp->mux.offset, grp->mux.shift, grp->mux.alt); + + return cygnus_pinmux_set(pinctrl, func, grp, pinctrl->mux_log); +} + +static int cygnus_gpio_request_enable(struct pinctrl_dev *pctrl_dev, + struct pinctrl_gpio_range *range, + unsigned pin) +{ + struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + const struct cygnus_gpio_mux *mux = pctrl_dev->desc->pins[pin].drv_data; + u32 val; + unsigned long flags; + + /* not all pins support GPIO pinmux override */ + if (!mux->is_supported) + return -ENOTSUPP; + + spin_lock_irqsave(&pinctrl->lock, flags); + + val = readl(pinctrl->base1 + mux->offset); + val |= 0x3 << mux->shift; + writel(val, pinctrl->base1 + mux->offset); + + spin_unlock_irqrestore(&pinctrl->lock, flags); + + dev_dbg(pctrl_dev->dev, + "gpio request enable pin=%u offset=0x%x shift=%u\n", + pin, mux->offset, mux->shift); + + return 0; +} + +static void cygnus_gpio_disable_free(struct pinctrl_dev *pctrl_dev, + struct pinctrl_gpio_range *range, + unsigned pin) +{ + struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + struct cygnus_gpio_mux *mux = pctrl_dev->desc->pins[pin].drv_data; + u32 val; + unsigned long flags; + + if (!mux->is_supported) + return; + + spin_lock_irqsave(&pinctrl->lock, flags); + + val = readl(pinctrl->base1 + mux->offset); + val &= ~(0x3 << mux->shift); + writel(val, pinctrl->base1 + mux->offset); + + spin_unlock_irqrestore(&pinctrl->lock, flags); + + dev_err(pctrl_dev->dev, + "gpio disable free pin=%u offset=0x%x shift=%u\n", + pin, mux->offset, mux->shift); +} + +static const struct pinmux_ops cygnus_pinmux_ops = { + .get_functions_count = cygnus_get_functions_count, + .get_function_name = cygnus_get_function_name, + .get_function_groups = cygnus_get_function_groups, + .set_mux = cygnus_pinmux_set_mux, + .gpio_request_enable = cygnus_gpio_request_enable, + .gpio_disable_free = cygnus_gpio_disable_free, +}; + +static struct pinctrl_desc cygnus_pinctrl_desc = { + .name = "cygnus-pinmux", + .pctlops = &cygnus_pinctrl_ops, + .pmxops = &cygnus_pinmux_ops, +}; + +static int cygnus_mux_log_init(struct cygnus_pinctrl *pinctrl) +{ + struct cygnus_mux_log *log; + unsigned int i, j; + + pinctrl->mux_log = devm_kcalloc(pinctrl->dev, CYGNUS_NUM_IOMUX, + sizeof(struct cygnus_mux_log), + GFP_KERNEL); + if (!pinctrl->mux_log) + return -ENOMEM; + + log = pinctrl->mux_log; + for (i = 0; i < CYGNUS_NUM_IOMUX_REGS; i++) { + for (j = 0; j < CYGNUS_NUM_MUX_PER_REG; j++) { + log = &pinctrl->mux_log[i * CYGNUS_NUM_MUX_PER_REG + + j]; + log->mux.offset = i * 4; + log->mux.shift = j * 4; + log->mux.alt = 0; + log->is_configured = false; + } + } + + return 0; +} + +static int cygnus_pinmux_probe(struct platform_device *pdev) +{ + struct cygnus_pinctrl *pinctrl; + struct resource *res; + int i, ret; + struct pinctrl_pin_desc *pins; + unsigned num_pins = ARRAY_SIZE(cygnus_pins); + + pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL); + if (!pinctrl) + return -ENOMEM; + + pinctrl->dev = &pdev->dev; + platform_set_drvdata(pdev, pinctrl); + spin_lock_init(&pinctrl->lock); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pinctrl->base0 = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pinctrl->base0)) { + dev_err(&pdev->dev, "unable to map I/O space\n"); + return PTR_ERR(pinctrl->base0); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + pinctrl->base1 = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pinctrl->base1)) { + dev_err(&pdev->dev, "unable to map I/O space\n"); + return PTR_ERR(pinctrl->base1); + } + + ret = cygnus_mux_log_init(pinctrl); + if (ret) { + dev_err(&pdev->dev, "unable to initialize IOMUX log\n"); + return ret; + } + + pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + + for (i = 0; i < num_pins; i++) { + pins[i].number = cygnus_pins[i].pin; + pins[i].name = cygnus_pins[i].name; + pins[i].drv_data = &cygnus_pins[i].gpio_mux; + } + + pinctrl->groups = cygnus_pin_groups; + pinctrl->num_groups = ARRAY_SIZE(cygnus_pin_groups); + pinctrl->functions = cygnus_pin_functions; + pinctrl->num_functions = ARRAY_SIZE(cygnus_pin_functions); + cygnus_pinctrl_desc.pins = pins; + cygnus_pinctrl_desc.npins = num_pins; + + pinctrl->pctl = pinctrl_register(&cygnus_pinctrl_desc, &pdev->dev, + pinctrl); + if (!pinctrl->pctl) { + dev_err(&pdev->dev, "unable to register Cygnus IOMUX pinctrl\n"); + return -EINVAL; + } + + return 0; +} + +static const struct of_device_id cygnus_pinmux_of_match[] = { + { .compatible = "brcm,cygnus-pinmux" }, + { } +}; + +static struct platform_driver cygnus_pinmux_driver = { + .driver = { + .name = "cygnus-pinmux", + .of_match_table = cygnus_pinmux_of_match, + .suppress_bind_attrs = true, + }, + .probe = cygnus_pinmux_probe, +}; + +static int __init cygnus_pinmux_init(void) +{ + return platform_driver_register(&cygnus_pinmux_driver); +} +arch_initcall(cygnus_pinmux_init); + +MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>"); +MODULE_DESCRIPTION("Broadcom Cygnus IOMUX driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 448f10986c28..e261f1cf85c6 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -542,10 +542,13 @@ static int imx_pinctrl_parse_groups(struct device_node *np, struct imx_pin_reg *pin_reg; struct imx_pin *pin = &grp->pins[i]; - if (info->flags & SHARE_MUX_CONF_REG) + if (info->flags & SHARE_MUX_CONF_REG) { conf_reg = mux_reg; - else + } else { conf_reg = be32_to_cpu(*list++); + if (!conf_reg) + conf_reg = -1; + } pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4; pin_reg = &info->pin_regs[pin_id]; @@ -645,7 +648,7 @@ int imx_pinctrl_probe(struct platform_device *pdev, { struct imx_pinctrl *ipctl; struct resource *res; - int ret; + int ret, i; if (!info || !info->pins || !info->npins) { dev_err(&pdev->dev, "wrong pinctrl info\n"); @@ -662,7 +665,11 @@ int imx_pinctrl_probe(struct platform_device *pdev, info->npins, GFP_KERNEL); if (!info->pin_regs) return -ENOMEM; - memset(info->pin_regs, 0xff, sizeof(*info->pin_regs) * info->npins); + + for (i = 0; i < info->npins; i++) { + info->pin_regs[i].mux_reg = -1; + info->pin_regs[i].conf_reg = -1; + } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ipctl->base = devm_ioremap_resource(&pdev->dev, res); diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c b/drivers/pinctrl/freescale/pinctrl-vf610.c index fc86276892fd..37a037543d29 100644 --- a/drivers/pinctrl/freescale/pinctrl-vf610.c +++ b/drivers/pinctrl/freescale/pinctrl-vf610.c @@ -302,7 +302,7 @@ static struct imx_pinctrl_soc_info vf610_pinctrl_info = { .flags = SHARE_MUX_CONF_REG, }; -static struct of_device_id vf610_pinctrl_of_match[] = { +static const struct of_device_id vf610_pinctrl_of_match[] = { { .compatible = "fsl,vf610-iomuxc", }, { /* sentinel */ } }; diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index b801d869e91c..fe5e07db0a95 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -25,3 +25,20 @@ config PINCTRL_CHERRYVIEW help Cherryview/Braswell pinctrl driver provides an interface that allows configuring of SoC pins and using them as GPIOs. + +config PINCTRL_INTEL + tristate + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIOLIB_IRQCHIP + +config PINCTRL_SUNRISEPOINT + tristate "Intel Sunrisepoint pinctrl and GPIO driver" + depends on ACPI + select PINCTRL_INTEL + help + Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver + provides an interface that allows configuring of PCH pins and + using them as GPIOs. diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile index 4c210e4139e2..fee756e1255b 100644 --- a/drivers/pinctrl/intel/Makefile +++ b/drivers/pinctrl/intel/Makefile @@ -2,3 +2,5 @@ obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o +obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o +obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c new file mode 100644 index 000000000000..00768e53deec --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -0,0 +1,1149 @@ +/* + * Intel pinctrl/GPIO core driver. + * + * Copyright (C) 2015, Intel Corporation + * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> + * Mika Westerberg <mika.westerberg@linux.intel.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/acpi.h> +#include <linux/gpio.h> +#include <linux/gpio/driver.h> +#include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> + +#include "pinctrl-intel.h" + +/* Maximum number of pads in each group */ +#define NPADS_IN_GPP 24 + +/* Offset from regs */ +#define PADBAR 0x00c +#define GPI_IS 0x100 +#define GPI_GPE_STS 0x140 +#define GPI_GPE_EN 0x160 + +#define PADOWN_BITS 4 +#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) +#define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p)) + +/* Offset from pad_regs */ +#define PADCFG0 0x000 +#define PADCFG0_RXEVCFG_SHIFT 25 +#define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT) +#define PADCFG0_RXEVCFG_LEVEL 0 +#define PADCFG0_RXEVCFG_EDGE 1 +#define PADCFG0_RXEVCFG_DISABLED 2 +#define PADCFG0_RXEVCFG_EDGE_BOTH 3 +#define PADCFG0_RXINV BIT(23) +#define PADCFG0_GPIROUTIOXAPIC BIT(20) +#define PADCFG0_GPIROUTSCI BIT(19) +#define PADCFG0_GPIROUTSMI BIT(18) +#define PADCFG0_GPIROUTNMI BIT(17) +#define PADCFG0_PMODE_SHIFT 10 +#define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT) +#define PADCFG0_GPIORXDIS BIT(9) +#define PADCFG0_GPIOTXDIS BIT(8) +#define PADCFG0_GPIORXSTATE BIT(1) +#define PADCFG0_GPIOTXSTATE BIT(0) + +#define PADCFG1 0x004 +#define PADCFG1_TERM_UP BIT(13) +#define PADCFG1_TERM_SHIFT 10 +#define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT) +#define PADCFG1_TERM_20K 4 +#define PADCFG1_TERM_2K 3 +#define PADCFG1_TERM_5K 2 +#define PADCFG1_TERM_1K 1 + +struct intel_pad_context { + u32 padcfg0; + u32 padcfg1; +}; + +struct intel_community_context { + u32 *intmask; +}; + +struct intel_pinctrl_context { + struct intel_pad_context *pads; + struct intel_community_context *communities; +}; + +/** + * struct intel_pinctrl - Intel pinctrl private structure + * @dev: Pointer to the device structure + * @lock: Lock to serialize register access + * @pctldesc: Pin controller description + * @pctldev: Pointer to the pin controller device + * @chip: GPIO chip in this pin controller + * @soc: SoC/PCH specific pin configuration data + * @communities: All communities in this pin controller + * @ncommunities: Number of communities in this pin controller + * @context: Configuration saved over system sleep + */ +struct intel_pinctrl { + struct device *dev; + spinlock_t lock; + struct pinctrl_desc pctldesc; + struct pinctrl_dev *pctldev; + struct gpio_chip chip; + const struct intel_pinctrl_soc_data *soc; + struct intel_community *communities; + size_t ncommunities; + struct intel_pinctrl_context context; +}; + +#define gpiochip_to_pinctrl(c) container_of(c, struct intel_pinctrl, chip) +#define pin_to_padno(c, p) ((p) - (c)->pin_base) + +static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, + unsigned pin) +{ + struct intel_community *community; + int i; + + for (i = 0; i < pctrl->ncommunities; i++) { + community = &pctrl->communities[i]; + if (pin >= community->pin_base && + pin < community->pin_base + community->npins) + return community; + } + + dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); + return NULL; +} + +static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin, + unsigned reg) +{ + const struct intel_community *community; + unsigned padno; + + community = intel_get_community(pctrl, pin); + if (!community) + return NULL; + + padno = pin_to_padno(community, pin); + return community->pad_regs + reg + padno * 8; +} + +static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin) +{ + const struct intel_community *community; + unsigned padno, gpp, gpp_offset, offset; + void __iomem *padown; + + community = intel_get_community(pctrl, pin); + if (!community) + return false; + if (!community->padown_offset) + return true; + + padno = pin_to_padno(community, pin); + gpp = padno / NPADS_IN_GPP; + gpp_offset = padno % NPADS_IN_GPP; + offset = community->padown_offset + gpp * 16 + (gpp_offset / 8) * 4; + padown = community->regs + offset; + + return !(readl(padown) & PADOWN_MASK(padno)); +} + +static bool intel_pad_reserved_for_acpi(struct intel_pinctrl *pctrl, + unsigned pin) +{ + const struct intel_community *community; + unsigned padno, gpp, offset; + void __iomem *hostown; + + community = intel_get_community(pctrl, pin); + if (!community) + return true; + if (!community->hostown_offset) + return false; + + padno = pin_to_padno(community, pin); + gpp = padno / NPADS_IN_GPP; + offset = community->hostown_offset + gpp * 4; + hostown = community->regs + offset; + + return !(readl(hostown) & BIT(padno % NPADS_IN_GPP)); +} + +static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) +{ + struct intel_community *community; + unsigned padno, gpp, offset; + u32 value; + + community = intel_get_community(pctrl, pin); + if (!community) + return true; + if (!community->padcfglock_offset) + return false; + + padno = pin_to_padno(community, pin); + gpp = padno / NPADS_IN_GPP; + + /* + * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, + * the pad is considered unlocked. Any other case means that it is + * either fully or partially locked and we don't touch it. + */ + offset = community->padcfglock_offset + gpp * 8; + value = readl(community->regs + offset); + if (value & BIT(pin % NPADS_IN_GPP)) + return true; + + offset = community->padcfglock_offset + 4 + gpp * 8; + value = readl(community->regs + offset); + if (value & BIT(pin % NPADS_IN_GPP)) + return true; + + return false; +} + +static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin) +{ + return intel_pad_owned_by_host(pctrl, pin) && + !intel_pad_reserved_for_acpi(pctrl, pin) && + !intel_pad_locked(pctrl, pin); +} + +static int intel_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->soc->ngroups; +} + +static const char *intel_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->soc->groups[group].name; +} + +static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, + const unsigned **pins, unsigned *npins) +{ + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *pins = pctrl->soc->groups[group].pins; + *npins = pctrl->soc->groups[group].npins; + return 0; +} + +static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + unsigned pin) +{ + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + u32 cfg0, cfg1, mode; + bool locked, acpi; + + if (!intel_pad_owned_by_host(pctrl, pin)) { + seq_puts(s, "not available"); + return; + } + + cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); + cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); + + mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; + if (!mode) + seq_puts(s, "GPIO "); + else + seq_printf(s, "mode %d ", mode); + + seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); + + locked = intel_pad_locked(pctrl, pin); + acpi = intel_pad_reserved_for_acpi(pctrl, pin); + + if (locked || acpi) { + seq_puts(s, " ["); + if (locked) { + seq_puts(s, "LOCKED"); + if (acpi) + seq_puts(s, ", "); + } + if (acpi) + seq_puts(s, "ACPI"); + seq_puts(s, "]"); + } +} + +static const struct pinctrl_ops intel_pinctrl_ops = { + .get_groups_count = intel_get_groups_count, + .get_group_name = intel_get_group_name, + .get_group_pins = intel_get_group_pins, + .pin_dbg_show = intel_pin_dbg_show, +}; + +static int intel_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->soc->nfunctions; +} + +static const char *intel_get_function_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->soc->functions[function].name; +} + +static int intel_get_function_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const ngroups) +{ + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pctrl->soc->functions[function].groups; + *ngroups = pctrl->soc->functions[function].ngroups; + return 0; +} + +static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, + unsigned group) +{ + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct intel_pingroup *grp = &pctrl->soc->groups[group]; + unsigned long flags; + int i; + + spin_lock_irqsave(&pctrl->lock, flags); + + /* + * All pins in the groups needs to be accessible and writable + * before we can enable the mux for this group. + */ + for (i = 0; i < grp->npins; i++) { + if (!intel_pad_usable(pctrl, grp->pins[i])) { + spin_unlock_irqrestore(&pctrl->lock, flags); + return -EBUSY; + } + } + + /* Now enable the mux setting for each pin in the group */ + for (i = 0; i < grp->npins; i++) { + void __iomem *padcfg0; + u32 value; + + padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0); + value = readl(padcfg0); + + value &= ~PADCFG0_PMODE_MASK; + value |= grp->mode << PADCFG0_PMODE_SHIFT; + + writel(value, padcfg0); + } + + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned pin) +{ + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + void __iomem *padcfg0; + unsigned long flags; + u32 value; + + spin_lock_irqsave(&pctrl->lock, flags); + + if (!intel_pad_usable(pctrl, pin)) { + spin_unlock_irqrestore(&pctrl->lock, flags); + return -EBUSY; + } + + padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); + /* Put the pad into GPIO mode */ + value = readl(padcfg0) & ~PADCFG0_PMODE_MASK; + /* Disable SCI/SMI/NMI generation */ + value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); + value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); + /* Disable TX buffer and enable RX (this will be input) */ + value &= ~PADCFG0_GPIORXDIS; + value |= PADCFG0_GPIOTXDIS; + writel(value, padcfg0); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned pin, bool input) +{ + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + void __iomem *padcfg0; + unsigned long flags; + u32 value; + + spin_lock_irqsave(&pctrl->lock, flags); + + padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); + + value = readl(padcfg0); + if (input) + value |= PADCFG0_GPIOTXDIS; + else + value &= ~PADCFG0_GPIOTXDIS; + writel(value, padcfg0); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static const struct pinmux_ops intel_pinmux_ops = { + .get_functions_count = intel_get_functions_count, + .get_function_name = intel_get_function_name, + .get_function_groups = intel_get_function_groups, + .set_mux = intel_pinmux_set_mux, + .gpio_request_enable = intel_gpio_request_enable, + .gpio_set_direction = intel_gpio_set_direction, +}; + +static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *config) +{ + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + u32 value, term; + u16 arg = 0; + + if (!intel_pad_owned_by_host(pctrl, pin)) + return -ENOTSUPP; + + value = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); + term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if (term) + return -EINVAL; + break; + + case PIN_CONFIG_BIAS_PULL_UP: + if (!term || !(value & PADCFG1_TERM_UP)) + return -EINVAL; + + switch (term) { + case PADCFG1_TERM_1K: + arg = 1000; + break; + case PADCFG1_TERM_2K: + arg = 2000; + break; + case PADCFG1_TERM_5K: + arg = 5000; + break; + case PADCFG1_TERM_20K: + arg = 20000; + break; + } + + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + if (!term || value & PADCFG1_TERM_UP) + return -EINVAL; + + switch (term) { + case PADCFG1_TERM_5K: + arg = 5000; + break; + case PADCFG1_TERM_20K: + arg = 20000; + break; + } + + break; + + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return 0; +} + +static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin, + unsigned long config) +{ + unsigned param = pinconf_to_config_param(config); + unsigned arg = pinconf_to_config_argument(config); + void __iomem *padcfg1; + unsigned long flags; + int ret = 0; + u32 value; + + spin_lock_irqsave(&pctrl->lock, flags); + + padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); + value = readl(padcfg1); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); + break; + + case PIN_CONFIG_BIAS_PULL_UP: + value &= ~PADCFG1_TERM_MASK; + + value |= PADCFG1_TERM_UP; + + switch (arg) { + case 20000: + value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; + break; + case 5000: + value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; + break; + case 2000: + value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT; + break; + case 1000: + value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; + break; + default: + ret = -EINVAL; + } + + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK); + + switch (arg) { + case 20000: + value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; + break; + case 5000: + value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; + break; + default: + ret = -EINVAL; + } + + break; + } + + if (!ret) + writel(value, padcfg1); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + return ret; +} + +static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *configs, unsigned nconfigs) +{ + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + int i, ret; + + if (!intel_pad_usable(pctrl, pin)) + return -ENOTSUPP; + + for (i = 0; i < nconfigs; i++) { + switch (pinconf_to_config_param(configs[i])) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + ret = intel_config_set_pull(pctrl, pin, configs[i]); + if (ret) + return ret; + break; + + default: + return -ENOTSUPP; + } + } + + return 0; +} + +static const struct pinconf_ops intel_pinconf_ops = { + .is_generic = true, + .pin_config_get = intel_config_get, + .pin_config_set = intel_config_set, +}; + +static const struct pinctrl_desc intel_pinctrl_desc = { + .pctlops = &intel_pinctrl_ops, + .pmxops = &intel_pinmux_ops, + .confops = &intel_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int intel_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_request_gpio(chip->base + offset); +} + +static void intel_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + pinctrl_free_gpio(chip->base + offset); +} + +static int intel_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(chip); + void __iomem *reg; + + reg = intel_get_padcfg(pctrl, offset, PADCFG0); + if (!reg) + return -EINVAL; + + return !!(readl(reg) & PADCFG0_GPIORXSTATE); +} + +static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(chip); + void __iomem *reg; + + reg = intel_get_padcfg(pctrl, offset, PADCFG0); + if (reg) { + unsigned long flags; + u32 padcfg0; + + spin_lock_irqsave(&pctrl->lock, flags); + padcfg0 = readl(reg); + if (value) + padcfg0 |= PADCFG0_GPIOTXSTATE; + else + padcfg0 &= ~PADCFG0_GPIOTXSTATE; + writel(padcfg0, reg); + spin_unlock_irqrestore(&pctrl->lock, flags); + } +} + +static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_gpio_direction_input(chip->base + offset); +} + +static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, + int value) +{ + intel_gpio_set(chip, offset, value); + return pinctrl_gpio_direction_output(chip->base + offset); +} + +static const struct gpio_chip intel_gpio_chip = { + .owner = THIS_MODULE, + .request = intel_gpio_request, + .free = intel_gpio_free, + .direction_input = intel_gpio_direction_input, + .direction_output = intel_gpio_direction_output, + .get = intel_gpio_get, + .set = intel_gpio_set, +}; + +static void intel_gpio_irq_ack(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc); + const struct intel_community *community; + unsigned pin = irqd_to_hwirq(d); + + spin_lock(&pctrl->lock); + + community = intel_get_community(pctrl, pin); + if (community) { + unsigned padno = pin_to_padno(community, pin); + unsigned gpp_offset = padno % NPADS_IN_GPP; + unsigned gpp = padno / NPADS_IN_GPP; + + writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); + } + + spin_unlock(&pctrl->lock); +} + +static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc); + const struct intel_community *community; + unsigned pin = irqd_to_hwirq(d); + unsigned long flags; + + spin_lock_irqsave(&pctrl->lock, flags); + + community = intel_get_community(pctrl, pin); + if (community) { + unsigned padno = pin_to_padno(community, pin); + unsigned gpp_offset = padno % NPADS_IN_GPP; + unsigned gpp = padno / NPADS_IN_GPP; + void __iomem *reg; + u32 value; + + reg = community->regs + community->ie_offset + gpp * 4; + value = readl(reg); + if (mask) + value &= ~BIT(gpp_offset); + else + value |= BIT(gpp_offset); + writel(value, reg); + } + + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static void intel_gpio_irq_mask(struct irq_data *d) +{ + intel_gpio_irq_mask_unmask(d, true); +} + +static void intel_gpio_irq_unmask(struct irq_data *d) +{ + intel_gpio_irq_mask_unmask(d, false); +} + +static int intel_gpio_irq_type(struct irq_data *d, unsigned type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc); + unsigned pin = irqd_to_hwirq(d); + unsigned long flags; + void __iomem *reg; + u32 value; + + reg = intel_get_padcfg(pctrl, pin, PADCFG0); + if (!reg) + return -EINVAL; + + spin_lock_irqsave(&pctrl->lock, flags); + + value = readl(reg); + + value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); + + if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { + value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT; + } else if (type & IRQ_TYPE_EDGE_FALLING) { + value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; + value |= PADCFG0_RXINV; + } else if (type & IRQ_TYPE_EDGE_RISING) { + value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; + } else if (type & IRQ_TYPE_LEVEL_LOW) { + value |= PADCFG0_RXINV; + } else { + value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT; + } + + writel(value, reg); + + if (type & IRQ_TYPE_EDGE_BOTH) + __irq_set_handler_locked(d->irq, handle_edge_irq); + else if (type & IRQ_TYPE_LEVEL_MASK) + __irq_set_handler_locked(d->irq, handle_level_irq); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc); + const struct intel_community *community; + unsigned pin = irqd_to_hwirq(d); + unsigned padno, gpp, gpp_offset; + u32 gpe_en; + + community = intel_get_community(pctrl, pin); + if (!community) + return -EINVAL; + + padno = pin_to_padno(community, pin); + gpp = padno / NPADS_IN_GPP; + gpp_offset = padno % NPADS_IN_GPP; + + /* Clear the existing wake status */ + writel(BIT(gpp_offset), community->regs + GPI_GPE_STS + gpp * 4); + + /* + * The controller will generate wake when GPE of the corresponding + * pad is enabled and it is not routed to SCI (GPIROUTSCI is not + * set). + */ + gpe_en = readl(community->regs + GPI_GPE_EN + gpp * 4); + if (on) + gpe_en |= BIT(gpp_offset); + else + gpe_en &= ~BIT(gpp_offset); + writel(gpe_en, community->regs + GPI_GPE_EN + gpp * 4); + + dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); + return 0; +} + +static void intel_gpio_community_irq_handler(struct gpio_chip *gc, + const struct intel_community *community) +{ + int gpp; + + for (gpp = 0; gpp < community->ngpps; gpp++) { + unsigned long pending, enabled, gpp_offset; + + pending = readl(community->regs + GPI_IS + gpp * 4); + enabled = readl(community->regs + community->ie_offset + + gpp * 4); + + /* Only interrupts that are enabled */ + pending &= enabled; + + for_each_set_bit(gpp_offset, &pending, NPADS_IN_GPP) { + unsigned padno, irq; + + /* + * The last group in community can have less pins + * than NPADS_IN_GPP. + */ + padno = gpp_offset + gpp * NPADS_IN_GPP; + if (padno >= community->npins) + break; + + irq = irq_find_mapping(gc->irqdomain, + community->pin_base + padno); + generic_handle_irq(irq); + } + } +} + +static void intel_gpio_irq_handler(unsigned irq, struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc); + struct irq_chip *chip = irq_get_chip(irq); + int i; + + chained_irq_enter(chip, desc); + + /* Need to check all communities for pending interrupts */ + for (i = 0; i < pctrl->ncommunities; i++) + intel_gpio_community_irq_handler(gc, &pctrl->communities[i]); + + chained_irq_exit(chip, desc); +} + +static struct irq_chip intel_gpio_irqchip = { + .name = "intel-gpio", + .irq_ack = intel_gpio_irq_ack, + .irq_mask = intel_gpio_irq_mask, + .irq_unmask = intel_gpio_irq_unmask, + .irq_set_type = intel_gpio_irq_type, + .irq_set_wake = intel_gpio_irq_wake, +}; + +static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) +{ + size_t i; + + for (i = 0; i < pctrl->ncommunities; i++) { + const struct intel_community *community; + void __iomem *base; + unsigned gpp; + + community = &pctrl->communities[i]; + base = community->regs; + + for (gpp = 0; gpp < community->ngpps; gpp++) { + /* Mask and clear all interrupts */ + writel(0, base + community->ie_offset + gpp * 4); + writel(0xffff, base + GPI_IS + gpp * 4); + } + } +} + +static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) +{ + int ret; + + pctrl->chip = intel_gpio_chip; + + pctrl->chip.ngpio = pctrl->soc->npins; + pctrl->chip.label = dev_name(pctrl->dev); + pctrl->chip.dev = pctrl->dev; + pctrl->chip.base = -1; + + ret = gpiochip_add(&pctrl->chip); + if (ret) { + dev_err(pctrl->dev, "failed to register gpiochip\n"); + return ret; + } + + ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), + 0, 0, pctrl->soc->npins); + if (ret) { + dev_err(pctrl->dev, "failed to add GPIO pin range\n"); + gpiochip_remove(&pctrl->chip); + return ret; + } + + ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0, + handle_simple_irq, IRQ_TYPE_NONE); + if (ret) { + dev_err(pctrl->dev, "failed to add irqchip\n"); + gpiochip_remove(&pctrl->chip); + return ret; + } + + gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq, + intel_gpio_irq_handler); + return 0; +} + +static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) +{ +#ifdef CONFIG_PM_SLEEP + const struct intel_pinctrl_soc_data *soc = pctrl->soc; + struct intel_community_context *communities; + struct intel_pad_context *pads; + int i; + + pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); + if (!pads) + return -ENOMEM; + + communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, + sizeof(*communities), GFP_KERNEL); + if (!communities) + return -ENOMEM; + + + for (i = 0; i < pctrl->ncommunities; i++) { + struct intel_community *community = &pctrl->communities[i]; + u32 *intmask; + + intmask = devm_kcalloc(pctrl->dev, community->ngpps, + sizeof(*intmask), GFP_KERNEL); + if (!intmask) + return -ENOMEM; + + communities[i].intmask = intmask; + } + + pctrl->context.pads = pads; + pctrl->context.communities = communities; +#endif + + return 0; +} + +int intel_pinctrl_probe(struct platform_device *pdev, + const struct intel_pinctrl_soc_data *soc_data) +{ + struct intel_pinctrl *pctrl; + int i, ret, irq; + + if (!soc_data) + return -EINVAL; + + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->dev = &pdev->dev; + pctrl->soc = soc_data; + spin_lock_init(&pctrl->lock); + + /* + * Make a copy of the communities which we can use to hold pointers + * to the registers. + */ + pctrl->ncommunities = pctrl->soc->ncommunities; + pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities, + sizeof(*pctrl->communities), GFP_KERNEL); + if (!pctrl->communities) + return -ENOMEM; + + for (i = 0; i < pctrl->ncommunities; i++) { + struct intel_community *community = &pctrl->communities[i]; + struct resource *res; + void __iomem *regs; + u32 padbar; + + *community = pctrl->soc->communities[i]; + + res = platform_get_resource(pdev, IORESOURCE_MEM, + community->barno); + regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + /* Read offset of the pad configuration registers */ + padbar = readl(regs + PADBAR); + + community->regs = regs; + community->pad_regs = regs + padbar; + community->ngpps = DIV_ROUND_UP(community->npins, NPADS_IN_GPP); + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "failed to get interrupt number\n"); + return irq; + } + + ret = intel_pinctrl_pm_init(pctrl); + if (ret) + return ret; + + pctrl->pctldesc = intel_pinctrl_desc; + pctrl->pctldesc.name = dev_name(&pdev->dev); + pctrl->pctldesc.pins = pctrl->soc->pins; + pctrl->pctldesc.npins = pctrl->soc->npins; + + pctrl->pctldev = pinctrl_register(&pctrl->pctldesc, &pdev->dev, pctrl); + if (!pctrl->pctldev) { + dev_err(&pdev->dev, "failed to register pinctrl driver\n"); + return -ENODEV; + } + + ret = intel_gpio_probe(pctrl, irq); + if (ret) { + pinctrl_unregister(pctrl->pctldev); + return ret; + } + + platform_set_drvdata(pdev, pctrl); + + return 0; +} +EXPORT_SYMBOL_GPL(intel_pinctrl_probe); + +int intel_pinctrl_remove(struct platform_device *pdev) +{ + struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); + + gpiochip_remove(&pctrl->chip); + pinctrl_unregister(pctrl->pctldev); + + return 0; +} +EXPORT_SYMBOL_GPL(intel_pinctrl_remove); + +#ifdef CONFIG_PM_SLEEP +int intel_pinctrl_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); + struct intel_community_context *communities; + struct intel_pad_context *pads; + int i; + + pads = pctrl->context.pads; + for (i = 0; i < pctrl->soc->npins; i++) { + const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; + u32 val; + + if (!intel_pad_usable(pctrl, desc->number)) + continue; + + val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); + pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; + val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); + pads[i].padcfg1 = val; + } + + communities = pctrl->context.communities; + for (i = 0; i < pctrl->ncommunities; i++) { + struct intel_community *community = &pctrl->communities[i]; + void __iomem *base; + unsigned gpp; + + base = community->regs + community->ie_offset; + for (gpp = 0; gpp < community->ngpps; gpp++) + communities[i].intmask[gpp] = readl(base + gpp * 4); + } + + return 0; +} +EXPORT_SYMBOL_GPL(intel_pinctrl_suspend); + +int intel_pinctrl_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); + const struct intel_community_context *communities; + const struct intel_pad_context *pads; + int i; + + /* Mask all interrupts */ + intel_gpio_irq_init(pctrl); + + pads = pctrl->context.pads; + for (i = 0; i < pctrl->soc->npins; i++) { + const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; + void __iomem *padcfg; + u32 val; + + if (!intel_pad_usable(pctrl, desc->number)) + continue; + + padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0); + val = readl(padcfg) & ~PADCFG0_GPIORXSTATE; + if (val != pads[i].padcfg0) { + writel(pads[i].padcfg0, padcfg); + dev_dbg(dev, "restored pin %u padcfg0 %#08x\n", + desc->number, readl(padcfg)); + } + + padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1); + val = readl(padcfg); + if (val != pads[i].padcfg1) { + writel(pads[i].padcfg1, padcfg); + dev_dbg(dev, "restored pin %u padcfg1 %#08x\n", + desc->number, readl(padcfg)); + } + } + + communities = pctrl->context.communities; + for (i = 0; i < pctrl->ncommunities; i++) { + struct intel_community *community = &pctrl->communities[i]; + void __iomem *base; + unsigned gpp; + + base = community->regs + community->ie_offset; + for (gpp = 0; gpp < community->ngpps; gpp++) { + writel(communities[i].intmask[gpp], base + gpp * 4); + dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp, + readl(base + gpp * 4)); + } + } + + return 0; +} +EXPORT_SYMBOL_GPL(intel_pinctrl_resume); +#endif + +MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); +MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); +MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h new file mode 100644 index 000000000000..4ec8b572a288 --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -0,0 +1,128 @@ +/* + * Core pinctrl/GPIO driver for Intel GPIO controllers + * + * Copyright (C) 2015, Intel Corporation + * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> + * Mika Westerberg <mika.westerberg@linux.intel.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef PINCTRL_INTEL_H +#define PINCTRL_INTEL_H + +struct pinctrl_pin_desc; +struct platform_device; +struct device; + +/** + * struct intel_pingroup - Description about group of pins + * @name: Name of the groups + * @pins: All pins in this group + * @npins: Number of pins in this groups + * @mode: Native mode in which the group is muxed out @pins + */ +struct intel_pingroup { + const char *name; + const unsigned *pins; + size_t npins; + unsigned short mode; +}; + +/** + * struct intel_function - Description about a function + * @name: Name of the function + * @groups: An array of groups for this function + * @ngroups: Number of groups in @groups + */ +struct intel_function { + const char *name; + const char * const *groups; + size_t ngroups; +}; + +/** + * struct intel_community - Intel pin community description + * @barno: MMIO BAR number where registers for this community reside + * @padown_offset: Register offset of PAD_OWN register from @regs. If %0 + * then there is no support for owner. + * @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then + * locking is not supported. + * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it + * is assumed that the host owns the pin (rather than + * ACPI). + * @ie_offset: Register offset of GPI_IE from @regs. + * @pin_base: Starting pin of pins in this community + * @npins: Number of pins in this community + * @regs: Community specific common registers (reserved for core driver) + * @pad_regs: Community specific pad registers (reserved for core driver) + * @ngpps: Number of groups (hw groups) in this community (reserved for + * core driver) + */ +struct intel_community { + unsigned barno; + unsigned padown_offset; + unsigned padcfglock_offset; + unsigned hostown_offset; + unsigned ie_offset; + unsigned pin_base; + size_t npins; + void __iomem *regs; + void __iomem *pad_regs; + size_t ngpps; +}; + +#define PIN_GROUP(n, p, m) \ + { \ + .name = (n), \ + .pins = (p), \ + .npins = ARRAY_SIZE((p)), \ + .mode = (m), \ + } + +#define FUNCTION(n, g) \ + { \ + .name = (n), \ + .groups = (g), \ + .ngroups = ARRAY_SIZE((g)), \ + } + +/** + * struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration + * @uid: ACPI _UID for the probe driver use if needed + * @pins: Array if pins this pinctrl controls + * @npins: Number of pins in the array + * @groups: Array of pin groups + * @ngroups: Number of groups in the array + * @functions: Array of functions + * @nfunctions: Number of functions in the array + * @communities: Array of communities this pinctrl handles + * @ncommunities: Number of communities in the array + * + * The @communities is used as a template by the core driver. It will make + * copy of all communities and fill in rest of the information. + */ +struct intel_pinctrl_soc_data { + const char *uid; + const struct pinctrl_pin_desc *pins; + size_t npins; + const struct intel_pingroup *groups; + size_t ngroups; + const struct intel_function *functions; + size_t nfunctions; + const struct intel_community *communities; + size_t ncommunities; +}; + +int intel_pinctrl_probe(struct platform_device *pdev, + const struct intel_pinctrl_soc_data *soc_data); +int intel_pinctrl_remove(struct platform_device *pdev); + +#ifdef CONFIG_PM_SLEEP +int intel_pinctrl_suspend(struct device *dev); +int intel_pinctrl_resume(struct device *dev); +#endif + +#endif /* PINCTRL_INTEL_H */ diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c new file mode 100644 index 000000000000..55d025dc89e8 --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c @@ -0,0 +1,336 @@ +/* + * Intel Sunrisepoint PCH pinctrl/GPIO driver + * + * Copyright (C) 2015, Intel Corporation + * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> + * Mika Westerberg <mika.westerberg@linux.intel.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/acpi.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-intel.h" + +#define SPT_PAD_OWN 0x020 +#define SPT_PADCFGLOCK 0x0a0 +#define SPT_HOSTSW_OWN 0x0d0 +#define SPT_GPI_IE 0x120 + +#define SPT_COMMUNITY(b, s, e) \ + { \ + .barno = (b), \ + .padown_offset = SPT_PAD_OWN, \ + .padcfglock_offset = SPT_PADCFGLOCK, \ + .hostown_offset = SPT_HOSTSW_OWN, \ + .ie_offset = SPT_GPI_IE, \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ + } + +/* Sunrisepoint-LP */ +static const struct pinctrl_pin_desc sptlp_pins[] = { + /* GPP_A */ + PINCTRL_PIN(0, "RCINB"), + PINCTRL_PIN(1, "LAD_0"), + PINCTRL_PIN(2, "LAD_1"), + PINCTRL_PIN(3, "LAD_2"), + PINCTRL_PIN(4, "LAD_3"), + PINCTRL_PIN(5, "LFRAMEB"), + PINCTRL_PIN(6, "SERIQ"), + PINCTRL_PIN(7, "PIRQAB"), + PINCTRL_PIN(8, "CLKRUNB"), + PINCTRL_PIN(9, "CLKOUT_LPC_0"), + PINCTRL_PIN(10, "CLKOUT_LPC_1"), + PINCTRL_PIN(11, "PMEB"), + PINCTRL_PIN(12, "BM_BUSYB"), + PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"), + PINCTRL_PIN(14, "SUS_STATB"), + PINCTRL_PIN(15, "SUSACKB"), + PINCTRL_PIN(16, "SD_1P8_SEL"), + PINCTRL_PIN(17, "SD_PWR_EN_B"), + PINCTRL_PIN(18, "ISH_GP_0"), + PINCTRL_PIN(19, "ISH_GP_1"), + PINCTRL_PIN(20, "ISH_GP_2"), + PINCTRL_PIN(21, "ISH_GP_3"), + PINCTRL_PIN(22, "ISH_GP_4"), + PINCTRL_PIN(23, "ISH_GP_5"), + /* GPP_B */ + PINCTRL_PIN(24, "CORE_VID_0"), + PINCTRL_PIN(25, "CORE_VID_1"), + PINCTRL_PIN(26, "VRALERTB"), + PINCTRL_PIN(27, "CPU_GP_2"), + PINCTRL_PIN(28, "CPU_GP_3"), + PINCTRL_PIN(29, "SRCCLKREQB_0"), + PINCTRL_PIN(30, "SRCCLKREQB_1"), + PINCTRL_PIN(31, "SRCCLKREQB_2"), + PINCTRL_PIN(32, "SRCCLKREQB_3"), + PINCTRL_PIN(33, "SRCCLKREQB_4"), + PINCTRL_PIN(34, "SRCCLKREQB_5"), + PINCTRL_PIN(35, "EXT_PWR_GATEB"), + PINCTRL_PIN(36, "SLP_S0B"), + PINCTRL_PIN(37, "PLTRSTB"), + PINCTRL_PIN(38, "SPKR"), + PINCTRL_PIN(39, "GSPI0_CSB"), + PINCTRL_PIN(40, "GSPI0_CLK"), + PINCTRL_PIN(41, "GSPI0_MISO"), + PINCTRL_PIN(42, "GSPI0_MOSI"), + PINCTRL_PIN(43, "GSPI1_CSB"), + PINCTRL_PIN(44, "GSPI1_CLK"), + PINCTRL_PIN(45, "GSPI1_MISO"), + PINCTRL_PIN(46, "GSPI1_MOSI"), + PINCTRL_PIN(47, "SML1ALERTB"), + /* GPP_C */ + PINCTRL_PIN(48, "SMBCLK"), + PINCTRL_PIN(49, "SMBDATA"), + PINCTRL_PIN(50, "SMBALERTB"), + PINCTRL_PIN(51, "SML0CLK"), + PINCTRL_PIN(52, "SML0DATA"), + PINCTRL_PIN(53, "SML0ALERTB"), + PINCTRL_PIN(54, "SML1CLK"), + PINCTRL_PIN(55, "SML1DATA"), + PINCTRL_PIN(56, "UART0_RXD"), + PINCTRL_PIN(57, "UART0_TXD"), + PINCTRL_PIN(58, "UART0_RTSB"), + PINCTRL_PIN(59, "UART0_CTSB"), + PINCTRL_PIN(60, "UART1_RXD"), + PINCTRL_PIN(61, "UART1_TXD"), + PINCTRL_PIN(62, "UART1_RTSB"), + PINCTRL_PIN(63, "UART1_CTSB"), + PINCTRL_PIN(64, "I2C0_SDA"), + PINCTRL_PIN(65, "I2C0_SCL"), + PINCTRL_PIN(66, "I2C1_SDA"), + PINCTRL_PIN(67, "I2C1_SCL"), + PINCTRL_PIN(68, "UART2_RXD"), + PINCTRL_PIN(69, "UART2_TXD"), + PINCTRL_PIN(70, "UART2_RTSB"), + PINCTRL_PIN(71, "UART2_CTSB"), + /* GPP_D */ + PINCTRL_PIN(72, "SPI1_CSB"), + PINCTRL_PIN(73, "SPI1_CLK"), + PINCTRL_PIN(74, "SPI1_MISO_IO_1"), + PINCTRL_PIN(75, "SPI1_MOSI_IO_0"), + PINCTRL_PIN(76, "FLASHTRIG"), + PINCTRL_PIN(77, "ISH_I2C0_SDA"), + PINCTRL_PIN(78, "ISH_I2C0_SCL"), + PINCTRL_PIN(79, "ISH_I2C1_SDA"), + PINCTRL_PIN(80, "ISH_I2C1_SCL"), + PINCTRL_PIN(81, "ISH_SPI_CSB"), + PINCTRL_PIN(82, "ISH_SPI_CLK"), + PINCTRL_PIN(83, "ISH_SPI_MISO"), + PINCTRL_PIN(84, "ISH_SPI_MOSI"), + PINCTRL_PIN(85, "ISH_UART0_RXD"), + PINCTRL_PIN(86, "ISH_UART0_TXD"), + PINCTRL_PIN(87, "ISH_UART0_RTSB"), + PINCTRL_PIN(88, "ISH_UART0_CTSB"), + PINCTRL_PIN(89, "DMIC_CLK_1"), + PINCTRL_PIN(90, "DMIC_DATA_1"), + PINCTRL_PIN(91, "DMIC_CLK_0"), + PINCTRL_PIN(92, "DMIC_DATA_0"), + PINCTRL_PIN(93, "SPI1_IO_2"), + PINCTRL_PIN(94, "SPI1_IO_3"), + PINCTRL_PIN(95, "SSP_MCLK"), + /* GPP_E */ + PINCTRL_PIN(96, "SATAXPCIE_0"), + PINCTRL_PIN(97, "SATAXPCIE_1"), + PINCTRL_PIN(98, "SATAXPCIE_2"), + PINCTRL_PIN(99, "CPU_GP_0"), + PINCTRL_PIN(100, "SATA_DEVSLP_0"), + PINCTRL_PIN(101, "SATA_DEVSLP_1"), + PINCTRL_PIN(102, "SATA_DEVSLP_2"), + PINCTRL_PIN(103, "CPU_GP_1"), + PINCTRL_PIN(104, "SATA_LEDB"), + PINCTRL_PIN(105, "USB2_OCB_0"), + PINCTRL_PIN(106, "USB2_OCB_1"), + PINCTRL_PIN(107, "USB2_OCB_2"), + PINCTRL_PIN(108, "USB2_OCB_3"), + PINCTRL_PIN(109, "DDSP_HPD_0"), + PINCTRL_PIN(110, "DDSP_HPD_1"), + PINCTRL_PIN(111, "DDSP_HPD_2"), + PINCTRL_PIN(112, "DDSP_HPD_3"), + PINCTRL_PIN(113, "EDP_HPD"), + PINCTRL_PIN(114, "DDPB_CTRLCLK"), + PINCTRL_PIN(115, "DDPB_CTRLDATA"), + PINCTRL_PIN(116, "DDPC_CTRLCLK"), + PINCTRL_PIN(117, "DDPC_CTRLDATA"), + PINCTRL_PIN(118, "DDPD_CTRLCLK"), + PINCTRL_PIN(119, "DDPD_CTRLDATA"), + /* GPP_F */ + PINCTRL_PIN(120, "SSP2_SCLK"), + PINCTRL_PIN(121, "SSP2_SFRM"), + PINCTRL_PIN(122, "SSP2_TXD"), + PINCTRL_PIN(123, "SSP2_RXD"), + PINCTRL_PIN(124, "I2C2_SDA"), + PINCTRL_PIN(125, "I2C2_SCL"), + PINCTRL_PIN(126, "I2C3_SDA"), + PINCTRL_PIN(127, "I2C3_SCL"), + PINCTRL_PIN(128, "I2C4_SDA"), + PINCTRL_PIN(129, "I2C4_SCL"), + PINCTRL_PIN(130, "I2C5_SDA"), + PINCTRL_PIN(131, "I2C5_SCL"), + PINCTRL_PIN(132, "EMMC_CMD"), + PINCTRL_PIN(133, "EMMC_DATA_0"), + PINCTRL_PIN(134, "EMMC_DATA_1"), + PINCTRL_PIN(135, "EMMC_DATA_2"), + PINCTRL_PIN(136, "EMMC_DATA_3"), + PINCTRL_PIN(137, "EMMC_DATA_4"), + PINCTRL_PIN(138, "EMMC_DATA_5"), + PINCTRL_PIN(139, "EMMC_DATA_6"), + PINCTRL_PIN(140, "EMMC_DATA_7"), + PINCTRL_PIN(141, "EMMC_RCLK"), + PINCTRL_PIN(142, "EMMC_CLK"), + PINCTRL_PIN(143, "GPP_F_23"), + /* GPP_G */ + PINCTRL_PIN(144, "SD_CMD"), + PINCTRL_PIN(145, "SD_DATA_0"), + PINCTRL_PIN(146, "SD_DATA_1"), + PINCTRL_PIN(147, "SD_DATA_2"), + PINCTRL_PIN(148, "SD_DATA_3"), + PINCTRL_PIN(149, "SD_CDB"), + PINCTRL_PIN(150, "SD_CLK"), + PINCTRL_PIN(151, "SD_WP"), +}; + +static const unsigned sptlp_spi0_pins[] = { 39, 40, 41, 42 }; +static const unsigned sptlp_spi1_pins[] = { 43, 44, 45, 46 }; +static const unsigned sptlp_uart0_pins[] = { 56, 57, 58, 59 }; +static const unsigned sptlp_uart1_pins[] = { 60, 61, 62, 63 }; +static const unsigned sptlp_uart2_pins[] = { 68, 69, 71, 71 }; +static const unsigned sptlp_i2c0_pins[] = { 64, 65 }; +static const unsigned sptlp_i2c1_pins[] = { 66, 67 }; +static const unsigned sptlp_i2c2_pins[] = { 124, 125 }; +static const unsigned sptlp_i2c3_pins[] = { 126, 127 }; +static const unsigned sptlp_i2c4_pins[] = { 128, 129 }; +static const unsigned sptlp_i2c4b_pins[] = { 85, 86 }; +static const unsigned sptlp_i2c5_pins[] = { 130, 131 }; +static const unsigned sptlp_ssp2_pins[] = { 120, 121, 122, 123 }; +static const unsigned sptlp_emmc_pins[] = { + 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, +}; +static const unsigned sptlp_sd_pins[] = { + 144, 145, 146, 147, 148, 149, 150, 151, +}; + +static const struct intel_pingroup sptlp_groups[] = { + PIN_GROUP("spi0_grp", sptlp_spi0_pins, 1), + PIN_GROUP("spi1_grp", sptlp_spi1_pins, 1), + PIN_GROUP("uart0_grp", sptlp_uart0_pins, 1), + PIN_GROUP("uart1_grp", sptlp_uart1_pins, 1), + PIN_GROUP("uart2_grp", sptlp_uart2_pins, 1), + PIN_GROUP("i2c0_grp", sptlp_i2c0_pins, 1), + PIN_GROUP("i2c1_grp", sptlp_i2c1_pins, 1), + PIN_GROUP("i2c2_grp", sptlp_i2c2_pins, 1), + PIN_GROUP("i2c3_grp", sptlp_i2c3_pins, 1), + PIN_GROUP("i2c4_grp", sptlp_i2c4_pins, 1), + PIN_GROUP("i2c4b_grp", sptlp_i2c4b_pins, 3), + PIN_GROUP("i2c5_grp", sptlp_i2c5_pins, 1), + PIN_GROUP("ssp2_grp", sptlp_ssp2_pins, 1), + PIN_GROUP("emmc_grp", sptlp_emmc_pins, 1), + PIN_GROUP("sd_grp", sptlp_sd_pins, 1), +}; + +static const char * const sptlp_spi0_groups[] = { "spi0_grp" }; +static const char * const sptlp_spi1_groups[] = { "spi0_grp" }; +static const char * const sptlp_uart0_groups[] = { "uart0_grp" }; +static const char * const sptlp_uart1_groups[] = { "uart1_grp" }; +static const char * const sptlp_uart2_groups[] = { "uart2_grp" }; +static const char * const sptlp_i2c0_groups[] = { "i2c0_grp" }; +static const char * const sptlp_i2c1_groups[] = { "i2c1_grp" }; +static const char * const sptlp_i2c2_groups[] = { "i2c2_grp" }; +static const char * const sptlp_i2c3_groups[] = { "i2c3_grp" }; +static const char * const sptlp_i2c4_groups[] = { "i2c4_grp", "i2c4b_grp" }; +static const char * const sptlp_i2c5_groups[] = { "i2c5_grp" }; +static const char * const sptlp_ssp2_groups[] = { "ssp2_grp" }; +static const char * const sptlp_emmc_groups[] = { "emmc_grp" }; +static const char * const sptlp_sd_groups[] = { "sd_grp" }; + +static const struct intel_function sptlp_functions[] = { + FUNCTION("spi0", sptlp_spi0_groups), + FUNCTION("spi1", sptlp_spi1_groups), + FUNCTION("uart0", sptlp_uart0_groups), + FUNCTION("uart1", sptlp_uart1_groups), + FUNCTION("uart2", sptlp_uart2_groups), + FUNCTION("i2c0", sptlp_i2c0_groups), + FUNCTION("i2c1", sptlp_i2c1_groups), + FUNCTION("i2c2", sptlp_i2c2_groups), + FUNCTION("i2c3", sptlp_i2c3_groups), + FUNCTION("i2c4", sptlp_i2c4_groups), + FUNCTION("i2c5", sptlp_i2c5_groups), + FUNCTION("ssp2", sptlp_ssp2_groups), + FUNCTION("emmc", sptlp_emmc_groups), + FUNCTION("sd", sptlp_sd_groups), +}; + +static const struct intel_community sptlp_communities[] = { + SPT_COMMUNITY(0, 0, 47), + SPT_COMMUNITY(1, 48, 119), + SPT_COMMUNITY(2, 120, 151), +}; + +static const struct intel_pinctrl_soc_data sptlp_soc_data = { + .pins = sptlp_pins, + .npins = ARRAY_SIZE(sptlp_pins), + .groups = sptlp_groups, + .ngroups = ARRAY_SIZE(sptlp_groups), + .functions = sptlp_functions, + .nfunctions = ARRAY_SIZE(sptlp_functions), + .communities = sptlp_communities, + .ncommunities = ARRAY_SIZE(sptlp_communities), +}; + +static const struct acpi_device_id spt_pinctrl_acpi_match[] = { + { "INT344B", (kernel_ulong_t)&sptlp_soc_data }, + { } +}; +MODULE_DEVICE_TABLE(acpi, spt_pinctrl_acpi_match); + +static int spt_pinctrl_probe(struct platform_device *pdev) +{ + const struct intel_pinctrl_soc_data *soc_data; + const struct acpi_device_id *id; + + id = acpi_match_device(spt_pinctrl_acpi_match, &pdev->dev); + if (!id || !id->driver_data) + return -ENODEV; + + soc_data = (const struct intel_pinctrl_soc_data *)id->driver_data; + return intel_pinctrl_probe(pdev, soc_data); +} + +static const struct dev_pm_ops spt_pinctrl_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend, + intel_pinctrl_resume) +}; + +static struct platform_driver spt_pinctrl_driver = { + .probe = spt_pinctrl_probe, + .remove = intel_pinctrl_remove, + .driver = { + .name = "sunrisepoint-pinctrl", + .acpi_match_table = spt_pinctrl_acpi_match, + .pm = &spt_pinctrl_pm_ops, + }, +}; + +static int __init spt_pinctrl_init(void) +{ + return platform_driver_register(&spt_pinctrl_driver); +} +subsys_initcall(spt_pinctrl_init); + +static void __exit spt_pinctrl_exit(void) +{ + platform_driver_unregister(&spt_pinctrl_driver); +} +module_exit(spt_pinctrl_exit); + +MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); +MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); +MODULE_DESCRIPTION("Intel Sunrisepoint PCH pinctrl/GPIO driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig new file mode 100644 index 000000000000..5983cf5b2c46 --- /dev/null +++ b/drivers/pinctrl/mediatek/Kconfig @@ -0,0 +1,23 @@ +if ARCH_MEDIATEK || COMPILE_TEST + +config PINCTRL_MTK_COMMON + bool + select PINMUX + select GENERIC_PINCONF + select GPIOLIB + select OF_GPIO + +# For ARMv7 SoCs +config PINCTRL_MT8135 + bool "Mediatek MT8135 pin control" if COMPILE_TEST && !MACH_MT8135 + default MACH_MT8135 + select PINCTRL_MTK_COMMON + +# For ARMv8 SoCs +config PINCTRL_MT8173 + bool "Mediatek MT8173 pin control" + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_COMMON + +endif diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile new file mode 100644 index 000000000000..d8606a2179cf --- /dev/null +++ b/drivers/pinctrl/mediatek/Makefile @@ -0,0 +1,6 @@ +# Core +obj-$(CONFIG_PINCTRL_MTK_COMMON) += pinctrl-mtk-common.o + +# SoC Drivers +obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o +obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c new file mode 100644 index 000000000000..f1e1e187ce96 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c @@ -0,0 +1,376 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/regmap.h> +#include <dt-bindings/pinctrl/mt65xx.h> + +#include "pinctrl-mtk-common.h" +#include "pinctrl-mtk-mt8135.h" + +#define DRV_BASE1 0x500 +#define DRV_BASE2 0x510 +#define PUPD_BASE1 0x400 +#define PUPD_BASE2 0x450 +#define R0_BASE1 0x4d0 +#define R1_BASE1 0x200 +#define R1_BASE2 0x250 + +struct mtk_spec_pull_set { + unsigned int pin; + unsigned int pupd_offset; + unsigned char pupd_bit; + unsigned int r0_offset; + unsigned char r0_bit; + unsigned int r1_offset; + unsigned char r1_bit; +}; + +#define SPEC_PULL(_pin, _pupd_offset, _pupd_bit, _r0_offset, \ + _r0_bit, _r1_offset, _r1_bit) \ + { \ + .pin = _pin, \ + .pupd_offset = _pupd_offset, \ + .pupd_bit = _pupd_bit, \ + .r0_offset = _r0_offset, \ + .r0_bit = _r0_bit, \ + .r1_offset = _r1_offset, \ + .r1_bit = _r1_bit, \ + } + +static const struct mtk_drv_group_desc mt8135_drv_grp[] = { + /* E8E4E2 2/4/6/8/10/12/14/16 */ + MTK_DRV_GRP(2, 16, 0, 2, 2), + /* E8E4 4/8/12/16 */ + MTK_DRV_GRP(4, 16, 1, 2, 4), + /* E4E2 2/4/6/8 */ + MTK_DRV_GRP(2, 8, 0, 1, 2), + /* E16E8E4 4/8/12/16/20/24/28/32 */ + MTK_DRV_GRP(4, 32, 0, 2, 4) +}; + +static const struct mtk_pin_drv_grp mt8135_pin_drv[] = { + MTK_PIN_DRV_GRP(0, DRV_BASE1, 0, 0), + MTK_PIN_DRV_GRP(1, DRV_BASE1, 0, 0), + MTK_PIN_DRV_GRP(2, DRV_BASE1, 0, 0), + MTK_PIN_DRV_GRP(3, DRV_BASE1, 0, 0), + MTK_PIN_DRV_GRP(4, DRV_BASE1, 4, 0), + MTK_PIN_DRV_GRP(5, DRV_BASE1, 8, 0), + MTK_PIN_DRV_GRP(6, DRV_BASE1, 0, 0), + MTK_PIN_DRV_GRP(7, DRV_BASE1, 0, 0), + MTK_PIN_DRV_GRP(8, DRV_BASE1, 0, 0), + MTK_PIN_DRV_GRP(9, DRV_BASE1, 0, 0), + + MTK_PIN_DRV_GRP(10, DRV_BASE1, 12, 1), + MTK_PIN_DRV_GRP(11, DRV_BASE1, 12, 1), + MTK_PIN_DRV_GRP(12, DRV_BASE1, 12, 1), + MTK_PIN_DRV_GRP(13, DRV_BASE1, 12, 1), + MTK_PIN_DRV_GRP(14, DRV_BASE1, 12, 1), + MTK_PIN_DRV_GRP(15, DRV_BASE1, 12, 1), + MTK_PIN_DRV_GRP(16, DRV_BASE1, 12, 1), + MTK_PIN_DRV_GRP(17, DRV_BASE1, 16, 1), + MTK_PIN_DRV_GRP(18, DRV_BASE1, 16, 1), + MTK_PIN_DRV_GRP(19, DRV_BASE1, 16, 1), + MTK_PIN_DRV_GRP(20, DRV_BASE1, 16, 1), + MTK_PIN_DRV_GRP(21, DRV_BASE1, 16, 1), + MTK_PIN_DRV_GRP(22, DRV_BASE1, 16, 1), + MTK_PIN_DRV_GRP(23, DRV_BASE1, 16, 1), + MTK_PIN_DRV_GRP(24, DRV_BASE1, 16, 1), + MTK_PIN_DRV_GRP(33, DRV_BASE1, 24, 1), + MTK_PIN_DRV_GRP(34, DRV_BASE2, 12, 2), + MTK_PIN_DRV_GRP(37, DRV_BASE2, 20, 1), + MTK_PIN_DRV_GRP(38, DRV_BASE2, 20, 1), + MTK_PIN_DRV_GRP(39, DRV_BASE2, 20, 1), + MTK_PIN_DRV_GRP(40, DRV_BASE2, 24, 1), + MTK_PIN_DRV_GRP(41, DRV_BASE2, 24, 1), + MTK_PIN_DRV_GRP(42, DRV_BASE2, 24, 1), + MTK_PIN_DRV_GRP(43, DRV_BASE2, 28, 1), + MTK_PIN_DRV_GRP(44, DRV_BASE2, 28, 1), + MTK_PIN_DRV_GRP(45, DRV_BASE2, 28, 1), + MTK_PIN_DRV_GRP(46, DRV_BASE2, 28, 1), + MTK_PIN_DRV_GRP(47, DRV_BASE2, 28, 1), + + MTK_PIN_DRV_GRP(49, DRV_BASE2+0x10, 0, 1), + MTK_PIN_DRV_GRP(50, DRV_BASE2+0x10, 4, 1), + MTK_PIN_DRV_GRP(51, DRV_BASE2+0x10, 8, 1), + MTK_PIN_DRV_GRP(52, DRV_BASE2+0x10, 12, 2), + MTK_PIN_DRV_GRP(53, DRV_BASE2+0x10, 16, 1), + MTK_PIN_DRV_GRP(54, DRV_BASE2+0x10, 20, 1), + MTK_PIN_DRV_GRP(55, DRV_BASE2+0x10, 24, 1), + MTK_PIN_DRV_GRP(56, DRV_BASE2+0x10, 28, 1), + + MTK_PIN_DRV_GRP(57, DRV_BASE2+0x20, 0, 1), + MTK_PIN_DRV_GRP(58, DRV_BASE2+0x20, 0, 1), + MTK_PIN_DRV_GRP(59, DRV_BASE2+0x20, 0, 1), + MTK_PIN_DRV_GRP(60, DRV_BASE2+0x20, 0, 1), + MTK_PIN_DRV_GRP(61, DRV_BASE2+0x20, 0, 1), + MTK_PIN_DRV_GRP(62, DRV_BASE2+0x20, 0, 1), + MTK_PIN_DRV_GRP(63, DRV_BASE2+0x20, 4, 1), + MTK_PIN_DRV_GRP(64, DRV_BASE2+0x20, 8, 1), + MTK_PIN_DRV_GRP(65, DRV_BASE2+0x20, 12, 1), + MTK_PIN_DRV_GRP(66, DRV_BASE2+0x20, 16, 1), + MTK_PIN_DRV_GRP(67, DRV_BASE2+0x20, 20, 1), + MTK_PIN_DRV_GRP(68, DRV_BASE2+0x20, 24, 1), + MTK_PIN_DRV_GRP(69, DRV_BASE2+0x20, 28, 1), + + MTK_PIN_DRV_GRP(70, DRV_BASE2+0x30, 0, 1), + MTK_PIN_DRV_GRP(71, DRV_BASE2+0x30, 4, 1), + MTK_PIN_DRV_GRP(72, DRV_BASE2+0x30, 8, 1), + MTK_PIN_DRV_GRP(73, DRV_BASE2+0x30, 12, 1), + MTK_PIN_DRV_GRP(74, DRV_BASE2+0x30, 16, 1), + MTK_PIN_DRV_GRP(75, DRV_BASE2+0x30, 20, 1), + MTK_PIN_DRV_GRP(76, DRV_BASE2+0x30, 24, 1), + MTK_PIN_DRV_GRP(77, DRV_BASE2+0x30, 28, 3), + MTK_PIN_DRV_GRP(78, DRV_BASE2+0x30, 28, 3), + + MTK_PIN_DRV_GRP(79, DRV_BASE2+0x40, 0, 3), + MTK_PIN_DRV_GRP(80, DRV_BASE2+0x40, 4, 3), + + MTK_PIN_DRV_GRP(81, DRV_BASE2+0x30, 28, 3), + MTK_PIN_DRV_GRP(82, DRV_BASE2+0x30, 28, 3), + + MTK_PIN_DRV_GRP(83, DRV_BASE2+0x40, 8, 3), + MTK_PIN_DRV_GRP(84, DRV_BASE2+0x40, 8, 3), + MTK_PIN_DRV_GRP(85, DRV_BASE2+0x40, 12, 3), + MTK_PIN_DRV_GRP(86, DRV_BASE2+0x40, 16, 3), + MTK_PIN_DRV_GRP(87, DRV_BASE2+0x40, 8, 3), + MTK_PIN_DRV_GRP(88, DRV_BASE2+0x40, 8, 3), + + MTK_PIN_DRV_GRP(89, DRV_BASE2+0x50, 12, 0), + MTK_PIN_DRV_GRP(90, DRV_BASE2+0x50, 12, 0), + MTK_PIN_DRV_GRP(91, DRV_BASE2+0x50, 12, 0), + MTK_PIN_DRV_GRP(92, DRV_BASE2+0x50, 12, 0), + MTK_PIN_DRV_GRP(93, DRV_BASE2+0x50, 12, 0), + MTK_PIN_DRV_GRP(94, DRV_BASE2+0x50, 12, 0), + MTK_PIN_DRV_GRP(95, DRV_BASE2+0x50, 12, 0), + + MTK_PIN_DRV_GRP(96, DRV_BASE1+0xb0, 28, 0), + + MTK_PIN_DRV_GRP(97, DRV_BASE2+0x50, 12, 0), + MTK_PIN_DRV_GRP(98, DRV_BASE2+0x50, 16, 0), + MTK_PIN_DRV_GRP(99, DRV_BASE2+0x50, 20, 1), + MTK_PIN_DRV_GRP(102, DRV_BASE2+0x50, 24, 1), + MTK_PIN_DRV_GRP(103, DRV_BASE2+0x50, 28, 1), + + + MTK_PIN_DRV_GRP(104, DRV_BASE2+0x60, 0, 1), + MTK_PIN_DRV_GRP(105, DRV_BASE2+0x60, 4, 1), + MTK_PIN_DRV_GRP(106, DRV_BASE2+0x60, 4, 1), + MTK_PIN_DRV_GRP(107, DRV_BASE2+0x60, 4, 1), + MTK_PIN_DRV_GRP(108, DRV_BASE2+0x60, 4, 1), + MTK_PIN_DRV_GRP(109, DRV_BASE2+0x60, 8, 2), + MTK_PIN_DRV_GRP(110, DRV_BASE2+0x60, 12, 2), + MTK_PIN_DRV_GRP(111, DRV_BASE2+0x60, 16, 2), + MTK_PIN_DRV_GRP(112, DRV_BASE2+0x60, 20, 2), + MTK_PIN_DRV_GRP(113, DRV_BASE2+0x60, 24, 2), + MTK_PIN_DRV_GRP(114, DRV_BASE2+0x60, 28, 2), + + MTK_PIN_DRV_GRP(115, DRV_BASE2+0x70, 0, 2), + MTK_PIN_DRV_GRP(116, DRV_BASE2+0x70, 4, 2), + MTK_PIN_DRV_GRP(117, DRV_BASE2+0x70, 8, 2), + MTK_PIN_DRV_GRP(118, DRV_BASE2+0x70, 12, 2), + MTK_PIN_DRV_GRP(119, DRV_BASE2+0x70, 16, 2), + MTK_PIN_DRV_GRP(120, DRV_BASE2+0x70, 20, 2), + + MTK_PIN_DRV_GRP(181, DRV_BASE1+0xa0, 12, 1), + MTK_PIN_DRV_GRP(182, DRV_BASE1+0xa0, 16, 1), + MTK_PIN_DRV_GRP(183, DRV_BASE1+0xa0, 20, 1), + MTK_PIN_DRV_GRP(184, DRV_BASE1+0xa0, 24, 1), + MTK_PIN_DRV_GRP(185, DRV_BASE1+0xa0, 28, 1), + + MTK_PIN_DRV_GRP(186, DRV_BASE1+0xb0, 0, 2), + MTK_PIN_DRV_GRP(187, DRV_BASE1+0xb0, 0, 2), + MTK_PIN_DRV_GRP(188, DRV_BASE1+0xb0, 0, 2), + MTK_PIN_DRV_GRP(189, DRV_BASE1+0xb0, 0, 2), + MTK_PIN_DRV_GRP(190, DRV_BASE1+0xb0, 4, 1), + MTK_PIN_DRV_GRP(191, DRV_BASE1+0xb0, 8, 1), + MTK_PIN_DRV_GRP(192, DRV_BASE1+0xb0, 12, 1), + + MTK_PIN_DRV_GRP(197, DRV_BASE1+0xb0, 16, 0), + MTK_PIN_DRV_GRP(198, DRV_BASE1+0xb0, 16, 0), + MTK_PIN_DRV_GRP(199, DRV_BASE1+0xb0, 20, 0), + MTK_PIN_DRV_GRP(200, DRV_BASE1+0xb0, 24, 0), + MTK_PIN_DRV_GRP(201, DRV_BASE1+0xb0, 16, 0), + MTK_PIN_DRV_GRP(202, DRV_BASE1+0xb0, 16, 0) +}; + +static const struct mtk_spec_pull_set spec_pupd[] = { + SPEC_PULL(0, PUPD_BASE1, 0, R0_BASE1, 9, R1_BASE1, 0), + SPEC_PULL(1, PUPD_BASE1, 1, R0_BASE1, 8, R1_BASE1, 1), + SPEC_PULL(2, PUPD_BASE1, 2, R0_BASE1, 7, R1_BASE1, 2), + SPEC_PULL(3, PUPD_BASE1, 3, R0_BASE1, 6, R1_BASE1, 3), + SPEC_PULL(4, PUPD_BASE1, 4, R0_BASE1, 1, R1_BASE1, 4), + SPEC_PULL(5, PUPD_BASE1, 5, R0_BASE1, 0, R1_BASE1, 5), + SPEC_PULL(6, PUPD_BASE1, 6, R0_BASE1, 5, R1_BASE1, 6), + SPEC_PULL(7, PUPD_BASE1, 7, R0_BASE1, 4, R1_BASE1, 7), + SPEC_PULL(8, PUPD_BASE1, 8, R0_BASE1, 3, R1_BASE1, 8), + SPEC_PULL(9, PUPD_BASE1, 9, R0_BASE1, 2, R1_BASE1, 9), + SPEC_PULL(89, PUPD_BASE2, 9, R0_BASE1, 18, R1_BASE2, 9), + SPEC_PULL(90, PUPD_BASE2, 10, R0_BASE1, 19, R1_BASE2, 10), + SPEC_PULL(91, PUPD_BASE2, 11, R0_BASE1, 23, R1_BASE2, 11), + SPEC_PULL(92, PUPD_BASE2, 12, R0_BASE1, 24, R1_BASE2, 12), + SPEC_PULL(93, PUPD_BASE2, 13, R0_BASE1, 25, R1_BASE2, 13), + SPEC_PULL(94, PUPD_BASE2, 14, R0_BASE1, 22, R1_BASE2, 14), + SPEC_PULL(95, PUPD_BASE2, 15, R0_BASE1, 20, R1_BASE2, 15), + SPEC_PULL(96, PUPD_BASE2+0x10, 0, R0_BASE1, 16, R1_BASE2+0x10, 0), + SPEC_PULL(97, PUPD_BASE2+0x10, 1, R0_BASE1, 21, R1_BASE2+0x10, 1), + SPEC_PULL(98, PUPD_BASE2+0x10, 2, R0_BASE1, 17, R1_BASE2+0x10, 2), + SPEC_PULL(197, PUPD_BASE1+0xc0, 5, R0_BASE1, 13, R1_BASE2+0xc0, 5), + SPEC_PULL(198, PUPD_BASE2+0xc0, 6, R0_BASE1, 14, R1_BASE2+0xc0, 6), + SPEC_PULL(199, PUPD_BASE2+0xc0, 7, R0_BASE1, 11, R1_BASE2+0xc0, 7), + SPEC_PULL(200, PUPD_BASE2+0xc0, 8, R0_BASE1, 10, R1_BASE2+0xc0, 8), + SPEC_PULL(201, PUPD_BASE2+0xc0, 9, R0_BASE1, 13, R1_BASE2+0xc0, 9), + SPEC_PULL(202, PUPD_BASE2+0xc0, 10, R0_BASE1, 12, R1_BASE2+0xc0, 10) +}; + +static int spec_pull_set(struct regmap *regmap, unsigned int pin, + unsigned char align, bool isup, unsigned int r1r0) +{ + unsigned int i; + unsigned int reg_pupd, reg_set_r0, reg_set_r1; + unsigned int reg_rst_r0, reg_rst_r1; + bool find = false; + + for (i = 0; i < ARRAY_SIZE(spec_pupd); i++) { + if (pin == spec_pupd[i].pin) { + find = true; + break; + } + } + + if (!find) + return -EINVAL; + + if (isup) + reg_pupd = spec_pupd[i].pupd_offset + align; + else + reg_pupd = spec_pupd[i].pupd_offset + (align << 1); + + regmap_write(regmap, reg_pupd, spec_pupd[i].pupd_bit); + + reg_set_r0 = spec_pupd[i].r0_offset + align; + reg_rst_r0 = spec_pupd[i].r0_offset + (align << 1); + reg_set_r1 = spec_pupd[i].r1_offset + align; + reg_rst_r1 = spec_pupd[i].r1_offset + (align << 1); + + switch (r1r0) { + case MTK_PUPD_SET_R1R0_00: + regmap_write(regmap, reg_rst_r0, spec_pupd[i].r0_bit); + regmap_write(regmap, reg_rst_r1, spec_pupd[i].r1_bit); + break; + case MTK_PUPD_SET_R1R0_01: + regmap_write(regmap, reg_set_r0, spec_pupd[i].r0_bit); + regmap_write(regmap, reg_rst_r1, spec_pupd[i].r1_bit); + break; + case MTK_PUPD_SET_R1R0_10: + regmap_write(regmap, reg_rst_r0, spec_pupd[i].r0_bit); + regmap_write(regmap, reg_set_r1, spec_pupd[i].r1_bit); + break; + case MTK_PUPD_SET_R1R0_11: + regmap_write(regmap, reg_set_r0, spec_pupd[i].r0_bit); + regmap_write(regmap, reg_set_r1, spec_pupd[i].r1_bit); + break; + default: + return -EINVAL; + } + + return 0; +} + +static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = { + .pins = mtk_pins_mt8135, + .npins = ARRAY_SIZE(mtk_pins_mt8135), + .grp_desc = mt8135_drv_grp, + .n_grp_cls = ARRAY_SIZE(mt8135_drv_grp), + .pin_drv_grp = mt8135_pin_drv, + .n_pin_drv_grps = ARRAY_SIZE(mt8135_pin_drv), + .spec_pull_set = spec_pull_set, + .dir_offset = 0x0000, + .ies_offset = 0x0100, + .pullen_offset = 0x0200, + .smt_offset = 0x0300, + .pullsel_offset = 0x0400, + .invser_offset = 0x0600, + .dout_offset = 0x0800, + .din_offset = 0x0A00, + .pinmux_offset = 0x0C00, + .type1_start = 34, + .type1_end = 149, + .port_shf = 4, + .port_mask = 0xf, + .port_align = 4, + .chip_type = MTK_CHIP_TYPE_BASE, + .eint_offsets = { + .name = "mt8135_eint", + .stat = 0x000, + .ack = 0x040, + .mask = 0x080, + .mask_set = 0x0c0, + .mask_clr = 0x100, + .sens = 0x140, + .sens_set = 0x180, + .sens_clr = 0x1c0, + .soft = 0x200, + .soft_set = 0x240, + .soft_clr = 0x280, + .pol = 0x300, + .pol_set = 0x340, + .pol_clr = 0x380, + .dom_en = 0x400, + .dbnc_ctrl = 0x500, + .dbnc_set = 0x600, + .dbnc_clr = 0x700, + .port_mask = 7, + .ports = 6, + }, + .ap_num = 192, + .db_cnt = 16, +}; + +static int mt8135_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_pctrl_init(pdev, &mt8135_pinctrl_data); +} + +static const struct of_device_id mt8135_pctrl_match[] = { + { + .compatible = "mediatek,mt8135-pinctrl", + }, + { } +}; +MODULE_DEVICE_TABLE(of, mt8135_pctrl_match); + +static struct platform_driver mtk_pinctrl_driver = { + .probe = mt8135_pinctrl_probe, + .driver = { + .name = "mediatek-mt8135-pinctrl", + .owner = THIS_MODULE, + .of_match_table = mt8135_pctrl_match, + }, +}; + +static int __init mtk_pinctrl_init(void) +{ + return platform_driver_register(&mtk_pinctrl_driver); +} + +module_init(mtk_pinctrl_init); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MediaTek Pinctrl Driver"); +MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c new file mode 100644 index 000000000000..412ea84836a1 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c @@ -0,0 +1,455 @@ +/* + * Copyright (c) 2014-2015 MediaTek Inc. + * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/regmap.h> +#include <dt-bindings/pinctrl/mt65xx.h> + +#include "pinctrl-mtk-common.h" +#include "pinctrl-mtk-mt8173.h" + +#define DRV_BASE 0xb00 + +/** + * struct mtk_pin_ies_smt_set - For special pins' ies and smt setting. + * @start: The start pin number of those special pins. + * @end: The end pin number of those special pins. + * @offset: The offset of special setting register. + * @bit: The bit of special setting register. + */ +struct mtk_pin_ies_smt_set { + unsigned int start; + unsigned int end; + unsigned int offset; + unsigned char bit; +}; + +#define MTK_PIN_IES_SMT_SET(_start, _end, _offset, _bit) \ + { \ + .start = _start, \ + .end = _end, \ + .bit = _bit, \ + .offset = _offset, \ + } + +/** + * struct mtk_pin_spec_pupd_set - For special pins' pull up/down setting. + * @pin: The pin number. + * @offset: The offset of special pull up/down setting register. + * @pupd_bit: The pull up/down bit in this register. + * @r0_bit: The r0 bit of pull resistor. + * @r1_bit: The r1 bit of pull resistor. + */ +struct mtk_pin_spec_pupd_set { + unsigned int pin; + unsigned int offset; + unsigned char pupd_bit; + unsigned char r1_bit; + unsigned char r0_bit; +}; + +#define MTK_PIN_PUPD_SPEC(_pin, _offset, _pupd, _r1, _r0) \ + { \ + .pin = _pin, \ + .offset = _offset, \ + .pupd_bit = _pupd, \ + .r1_bit = _r1, \ + .r0_bit = _r0, \ + } + +static const struct mtk_pin_spec_pupd_set mt8173_spec_pupd[] = { + MTK_PIN_PUPD_SPEC(119, 0xe00, 2, 1, 0), /* KROW0 */ + MTK_PIN_PUPD_SPEC(120, 0xe00, 6, 5, 4), /* KROW1 */ + MTK_PIN_PUPD_SPEC(121, 0xe00, 10, 9, 8), /* KROW2 */ + MTK_PIN_PUPD_SPEC(122, 0xe10, 2, 1, 0), /* KCOL0 */ + MTK_PIN_PUPD_SPEC(123, 0xe10, 6, 5, 4), /* KCOL1 */ + MTK_PIN_PUPD_SPEC(124, 0xe10, 10, 9, 8), /* KCOL2 */ + + MTK_PIN_PUPD_SPEC(67, 0xd10, 2, 1, 0), /* ms0 DS */ + MTK_PIN_PUPD_SPEC(68, 0xd00, 2, 1, 0), /* ms0 RST */ + MTK_PIN_PUPD_SPEC(66, 0xc10, 2, 1, 0), /* ms0 cmd */ + MTK_PIN_PUPD_SPEC(65, 0xc00, 2, 1, 0), /* ms0 clk */ + MTK_PIN_PUPD_SPEC(57, 0xc20, 2, 1, 0), /* ms0 data0 */ + MTK_PIN_PUPD_SPEC(58, 0xc20, 2, 1, 0), /* ms0 data1 */ + MTK_PIN_PUPD_SPEC(59, 0xc20, 2, 1, 0), /* ms0 data2 */ + MTK_PIN_PUPD_SPEC(60, 0xc20, 2, 1, 0), /* ms0 data3 */ + MTK_PIN_PUPD_SPEC(61, 0xc20, 2, 1, 0), /* ms0 data4 */ + MTK_PIN_PUPD_SPEC(62, 0xc20, 2, 1, 0), /* ms0 data5 */ + MTK_PIN_PUPD_SPEC(63, 0xc20, 2, 1, 0), /* ms0 data6 */ + MTK_PIN_PUPD_SPEC(64, 0xc20, 2, 1, 0), /* ms0 data7 */ + + MTK_PIN_PUPD_SPEC(78, 0xc50, 2, 1, 0), /* ms1 cmd */ + MTK_PIN_PUPD_SPEC(73, 0xd20, 2, 1, 0), /* ms1 dat0 */ + MTK_PIN_PUPD_SPEC(74, 0xd20, 6, 5, 4), /* ms1 dat1 */ + MTK_PIN_PUPD_SPEC(75, 0xd20, 10, 9, 8), /* ms1 dat2 */ + MTK_PIN_PUPD_SPEC(76, 0xd20, 14, 13, 12), /* ms1 dat3 */ + MTK_PIN_PUPD_SPEC(77, 0xc40, 2, 1, 0), /* ms1 clk */ + + MTK_PIN_PUPD_SPEC(100, 0xd40, 2, 1, 0), /* ms2 dat0 */ + MTK_PIN_PUPD_SPEC(101, 0xd40, 6, 5, 4), /* ms2 dat1 */ + MTK_PIN_PUPD_SPEC(102, 0xd40, 10, 9, 8), /* ms2 dat2 */ + MTK_PIN_PUPD_SPEC(103, 0xd40, 14, 13, 12), /* ms2 dat3 */ + MTK_PIN_PUPD_SPEC(104, 0xc80, 2, 1, 0), /* ms2 clk */ + MTK_PIN_PUPD_SPEC(105, 0xc90, 2, 1, 0), /* ms2 cmd */ + + MTK_PIN_PUPD_SPEC(22, 0xd60, 2, 1, 0), /* ms3 dat0 */ + MTK_PIN_PUPD_SPEC(23, 0xd60, 6, 5, 4), /* ms3 dat1 */ + MTK_PIN_PUPD_SPEC(24, 0xd60, 10, 9, 8), /* ms3 dat2 */ + MTK_PIN_PUPD_SPEC(25, 0xd60, 14, 13, 12), /* ms3 dat3 */ + MTK_PIN_PUPD_SPEC(26, 0xcc0, 2, 1, 0), /* ms3 clk */ + MTK_PIN_PUPD_SPEC(27, 0xcd0, 2, 1, 0) /* ms3 cmd */ +}; + +static int spec_pull_set(struct regmap *regmap, unsigned int pin, + unsigned char align, bool isup, unsigned int r1r0) +{ + unsigned int i; + unsigned int reg_pupd, reg_set, reg_rst; + unsigned int bit_pupd, bit_r0, bit_r1; + const struct mtk_pin_spec_pupd_set *spec_pupd_pin; + bool find = false; + + for (i = 0; i < ARRAY_SIZE(mt8173_spec_pupd); i++) { + if (pin == mt8173_spec_pupd[i].pin) { + find = true; + break; + } + } + + if (!find) + return -EINVAL; + + spec_pupd_pin = mt8173_spec_pupd + i; + reg_set = spec_pupd_pin->offset + align; + reg_rst = spec_pupd_pin->offset + (align << 1); + + if (isup) + reg_pupd = reg_rst; + else + reg_pupd = reg_set; + + bit_pupd = BIT(spec_pupd_pin->pupd_bit); + regmap_write(regmap, reg_pupd, bit_pupd); + + bit_r0 = BIT(spec_pupd_pin->r0_bit); + bit_r1 = BIT(spec_pupd_pin->r1_bit); + + switch (r1r0) { + case MTK_PUPD_SET_R1R0_00: + regmap_write(regmap, reg_rst, bit_r0); + regmap_write(regmap, reg_rst, bit_r1); + break; + case MTK_PUPD_SET_R1R0_01: + regmap_write(regmap, reg_set, bit_r0); + regmap_write(regmap, reg_rst, bit_r1); + break; + case MTK_PUPD_SET_R1R0_10: + regmap_write(regmap, reg_rst, bit_r0); + regmap_write(regmap, reg_set, bit_r1); + break; + case MTK_PUPD_SET_R1R0_11: + regmap_write(regmap, reg_set, bit_r0); + regmap_write(regmap, reg_set, bit_r1); + break; + default: + return -EINVAL; + } + + return 0; +} + +static const struct mtk_pin_ies_smt_set mt8173_ies_smt_set[] = { + MTK_PIN_IES_SMT_SET(0, 4, 0x930, 1), + MTK_PIN_IES_SMT_SET(5, 9, 0x930, 2), + MTK_PIN_IES_SMT_SET(10, 13, 0x930, 10), + MTK_PIN_IES_SMT_SET(14, 15, 0x940, 10), + MTK_PIN_IES_SMT_SET(16, 16, 0x930, 0), + MTK_PIN_IES_SMT_SET(17, 17, 0x950, 2), + MTK_PIN_IES_SMT_SET(18, 21, 0x940, 3), + MTK_PIN_IES_SMT_SET(29, 32, 0x930, 3), + MTK_PIN_IES_SMT_SET(33, 33, 0x930, 4), + MTK_PIN_IES_SMT_SET(34, 36, 0x930, 5), + MTK_PIN_IES_SMT_SET(37, 38, 0x930, 6), + MTK_PIN_IES_SMT_SET(39, 39, 0x930, 7), + MTK_PIN_IES_SMT_SET(40, 41, 0x930, 9), + MTK_PIN_IES_SMT_SET(42, 42, 0x940, 0), + MTK_PIN_IES_SMT_SET(43, 44, 0x930, 11), + MTK_PIN_IES_SMT_SET(45, 46, 0x930, 12), + MTK_PIN_IES_SMT_SET(57, 64, 0xc20, 13), + MTK_PIN_IES_SMT_SET(65, 65, 0xc10, 13), + MTK_PIN_IES_SMT_SET(66, 66, 0xc00, 13), + MTK_PIN_IES_SMT_SET(67, 67, 0xd10, 13), + MTK_PIN_IES_SMT_SET(68, 68, 0xd00, 13), + MTK_PIN_IES_SMT_SET(69, 72, 0x940, 14), + MTK_PIN_IES_SMT_SET(73, 76, 0xc60, 13), + MTK_PIN_IES_SMT_SET(77, 77, 0xc40, 13), + MTK_PIN_IES_SMT_SET(78, 78, 0xc50, 13), + MTK_PIN_IES_SMT_SET(79, 82, 0x940, 15), + MTK_PIN_IES_SMT_SET(83, 83, 0x950, 0), + MTK_PIN_IES_SMT_SET(84, 85, 0x950, 1), + MTK_PIN_IES_SMT_SET(86, 91, 0x950, 2), + MTK_PIN_IES_SMT_SET(92, 92, 0x930, 13), + MTK_PIN_IES_SMT_SET(93, 95, 0x930, 14), + MTK_PIN_IES_SMT_SET(96, 99, 0x930, 15), + MTK_PIN_IES_SMT_SET(100, 103, 0xca0, 13), + MTK_PIN_IES_SMT_SET(104, 104, 0xc80, 13), + MTK_PIN_IES_SMT_SET(105, 105, 0xc90, 13), + MTK_PIN_IES_SMT_SET(106, 107, 0x940, 4), + MTK_PIN_IES_SMT_SET(108, 112, 0x940, 1), + MTK_PIN_IES_SMT_SET(113, 116, 0x940, 2), + MTK_PIN_IES_SMT_SET(117, 118, 0x940, 5), + MTK_PIN_IES_SMT_SET(119, 124, 0x940, 6), + MTK_PIN_IES_SMT_SET(125, 126, 0x940, 7), + MTK_PIN_IES_SMT_SET(127, 127, 0x940, 0), + MTK_PIN_IES_SMT_SET(128, 128, 0x950, 8), + MTK_PIN_IES_SMT_SET(129, 130, 0x950, 9), + MTK_PIN_IES_SMT_SET(131, 132, 0x950, 8), + MTK_PIN_IES_SMT_SET(133, 134, 0x910, 8) +}; + +static int spec_ies_smt_set(struct regmap *regmap, unsigned int pin, + unsigned char align, int value) +{ + unsigned int i, reg_addr, bit; + bool find = false; + + for (i = 0; i < ARRAY_SIZE(mt8173_ies_smt_set); i++) { + if (pin >= mt8173_ies_smt_set[i].start && + pin <= mt8173_ies_smt_set[i].end) { + find = true; + break; + } + } + + if (!find) + return -EINVAL; + + if (value) + reg_addr = mt8173_ies_smt_set[i].offset + align; + else + reg_addr = mt8173_ies_smt_set[i].offset + (align << 1); + + bit = BIT(mt8173_ies_smt_set[i].bit); + regmap_write(regmap, reg_addr, bit); + return 0; +} + +static const struct mtk_drv_group_desc mt8173_drv_grp[] = { + /* 0E4E8SR 4/8/12/16 */ + MTK_DRV_GRP(4, 16, 1, 2, 4), + /* 0E2E4SR 2/4/6/8 */ + MTK_DRV_GRP(2, 8, 1, 2, 2), + /* E8E4E2 2/4/6/8/10/12/14/16 */ + MTK_DRV_GRP(2, 16, 0, 2, 2) +}; + +static const struct mtk_pin_drv_grp mt8173_pin_drv[] = { + MTK_PIN_DRV_GRP(0, DRV_BASE+0x20, 12, 0), + MTK_PIN_DRV_GRP(1, DRV_BASE+0x20, 12, 0), + MTK_PIN_DRV_GRP(2, DRV_BASE+0x20, 12, 0), + MTK_PIN_DRV_GRP(3, DRV_BASE+0x20, 12, 0), + MTK_PIN_DRV_GRP(4, DRV_BASE+0x20, 12, 0), + MTK_PIN_DRV_GRP(5, DRV_BASE+0x30, 0, 0), + MTK_PIN_DRV_GRP(6, DRV_BASE+0x30, 0, 0), + MTK_PIN_DRV_GRP(7, DRV_BASE+0x30, 0, 0), + MTK_PIN_DRV_GRP(8, DRV_BASE+0x30, 0, 0), + MTK_PIN_DRV_GRP(9, DRV_BASE+0x30, 0, 0), + MTK_PIN_DRV_GRP(10, DRV_BASE+0x30, 4, 1), + MTK_PIN_DRV_GRP(11, DRV_BASE+0x30, 4, 1), + MTK_PIN_DRV_GRP(12, DRV_BASE+0x30, 4, 1), + MTK_PIN_DRV_GRP(13, DRV_BASE+0x30, 4, 1), + MTK_PIN_DRV_GRP(14, DRV_BASE+0x40, 8, 1), + MTK_PIN_DRV_GRP(15, DRV_BASE+0x40, 8, 1), + MTK_PIN_DRV_GRP(16, DRV_BASE, 8, 1), + MTK_PIN_DRV_GRP(17, 0xce0, 8, 2), + MTK_PIN_DRV_GRP(22, 0xce0, 8, 2), + MTK_PIN_DRV_GRP(23, 0xce0, 8, 2), + MTK_PIN_DRV_GRP(24, 0xce0, 8, 2), + MTK_PIN_DRV_GRP(25, 0xce0, 8, 2), + MTK_PIN_DRV_GRP(26, 0xcc0, 8, 2), + MTK_PIN_DRV_GRP(27, 0xcd0, 8, 2), + MTK_PIN_DRV_GRP(28, 0xd70, 8, 2), + MTK_PIN_DRV_GRP(29, DRV_BASE+0x80, 12, 1), + MTK_PIN_DRV_GRP(30, DRV_BASE+0x80, 12, 1), + MTK_PIN_DRV_GRP(31, DRV_BASE+0x80, 12, 1), + MTK_PIN_DRV_GRP(32, DRV_BASE+0x80, 12, 1), + MTK_PIN_DRV_GRP(33, DRV_BASE+0x10, 12, 1), + MTK_PIN_DRV_GRP(34, DRV_BASE+0x10, 8, 1), + MTK_PIN_DRV_GRP(35, DRV_BASE+0x10, 8, 1), + MTK_PIN_DRV_GRP(36, DRV_BASE+0x10, 8, 1), + MTK_PIN_DRV_GRP(37, DRV_BASE+0x10, 4, 1), + MTK_PIN_DRV_GRP(38, DRV_BASE+0x10, 4, 1), + MTK_PIN_DRV_GRP(39, DRV_BASE+0x20, 0, 0), + MTK_PIN_DRV_GRP(40, DRV_BASE+0x20, 8, 0), + MTK_PIN_DRV_GRP(41, DRV_BASE+0x20, 8, 0), + MTK_PIN_DRV_GRP(42, DRV_BASE+0x50, 8, 1), + MTK_PIN_DRV_GRP(57, 0xc20, 8, 2), + MTK_PIN_DRV_GRP(58, 0xc20, 8, 2), + MTK_PIN_DRV_GRP(59, 0xc20, 8, 2), + MTK_PIN_DRV_GRP(60, 0xc20, 8, 2), + MTK_PIN_DRV_GRP(61, 0xc20, 8, 2), + MTK_PIN_DRV_GRP(62, 0xc20, 8, 2), + MTK_PIN_DRV_GRP(63, 0xc20, 8, 2), + MTK_PIN_DRV_GRP(64, 0xc20, 8, 2), + MTK_PIN_DRV_GRP(65, 0xc00, 8, 2), + MTK_PIN_DRV_GRP(66, 0xc10, 8, 2), + MTK_PIN_DRV_GRP(67, 0xd10, 8, 2), + MTK_PIN_DRV_GRP(68, 0xd00, 8, 2), + MTK_PIN_DRV_GRP(69, DRV_BASE+0x80, 0, 1), + MTK_PIN_DRV_GRP(70, DRV_BASE+0x80, 0, 1), + MTK_PIN_DRV_GRP(71, DRV_BASE+0x80, 0, 1), + MTK_PIN_DRV_GRP(72, DRV_BASE+0x80, 0, 1), + MTK_PIN_DRV_GRP(73, 0xc60, 8, 2), + MTK_PIN_DRV_GRP(74, 0xc60, 8, 2), + MTK_PIN_DRV_GRP(75, 0xc60, 8, 2), + MTK_PIN_DRV_GRP(76, 0xc60, 8, 2), + MTK_PIN_DRV_GRP(77, 0xc40, 8, 2), + MTK_PIN_DRV_GRP(78, 0xc50, 8, 2), + MTK_PIN_DRV_GRP(79, DRV_BASE+0x70, 12, 1), + MTK_PIN_DRV_GRP(80, DRV_BASE+0x70, 12, 1), + MTK_PIN_DRV_GRP(81, DRV_BASE+0x70, 12, 1), + MTK_PIN_DRV_GRP(82, DRV_BASE+0x70, 12, 1), + MTK_PIN_DRV_GRP(83, DRV_BASE, 4, 1), + MTK_PIN_DRV_GRP(84, DRV_BASE, 0, 1), + MTK_PIN_DRV_GRP(85, DRV_BASE, 0, 1), + MTK_PIN_DRV_GRP(85, DRV_BASE+0x60, 8, 1), + MTK_PIN_DRV_GRP(86, DRV_BASE+0x60, 8, 1), + MTK_PIN_DRV_GRP(87, DRV_BASE+0x60, 8, 1), + MTK_PIN_DRV_GRP(88, DRV_BASE+0x60, 8, 1), + MTK_PIN_DRV_GRP(89, DRV_BASE+0x60, 8, 1), + MTK_PIN_DRV_GRP(90, DRV_BASE+0x60, 8, 1), + MTK_PIN_DRV_GRP(91, DRV_BASE+0x60, 8, 1), + MTK_PIN_DRV_GRP(92, DRV_BASE+0x60, 4, 0), + MTK_PIN_DRV_GRP(93, DRV_BASE+0x60, 0, 0), + MTK_PIN_DRV_GRP(94, DRV_BASE+0x60, 0, 0), + MTK_PIN_DRV_GRP(95, DRV_BASE+0x60, 0, 0), + MTK_PIN_DRV_GRP(96, DRV_BASE+0x80, 8, 1), + MTK_PIN_DRV_GRP(97, DRV_BASE+0x80, 8, 1), + MTK_PIN_DRV_GRP(98, DRV_BASE+0x80, 8, 1), + MTK_PIN_DRV_GRP(99, DRV_BASE+0x80, 8, 1), + MTK_PIN_DRV_GRP(100, 0xca0, 8, 2), + MTK_PIN_DRV_GRP(101, 0xca0, 8, 2), + MTK_PIN_DRV_GRP(102, 0xca0, 8, 2), + MTK_PIN_DRV_GRP(103, 0xca0, 8, 2), + MTK_PIN_DRV_GRP(104, 0xc80, 8, 2), + MTK_PIN_DRV_GRP(105, 0xc90, 8, 2), + MTK_PIN_DRV_GRP(108, DRV_BASE+0x50, 0, 1), + MTK_PIN_DRV_GRP(109, DRV_BASE+0x50, 0, 1), + MTK_PIN_DRV_GRP(110, DRV_BASE+0x50, 0, 1), + MTK_PIN_DRV_GRP(111, DRV_BASE+0x50, 0, 1), + MTK_PIN_DRV_GRP(112, DRV_BASE+0x50, 0, 1), + MTK_PIN_DRV_GRP(113, DRV_BASE+0x80, 4, 1), + MTK_PIN_DRV_GRP(114, DRV_BASE+0x80, 4, 1), + MTK_PIN_DRV_GRP(115, DRV_BASE+0x80, 4, 1), + MTK_PIN_DRV_GRP(116, DRV_BASE+0x80, 4, 1), + MTK_PIN_DRV_GRP(117, DRV_BASE+0x90, 0, 1), + MTK_PIN_DRV_GRP(118, DRV_BASE+0x90, 0, 1), + MTK_PIN_DRV_GRP(119, DRV_BASE+0x50, 4, 1), + MTK_PIN_DRV_GRP(120, DRV_BASE+0x50, 4, 1), + MTK_PIN_DRV_GRP(121, DRV_BASE+0x50, 4, 1), + MTK_PIN_DRV_GRP(122, DRV_BASE+0x50, 4, 1), + MTK_PIN_DRV_GRP(123, DRV_BASE+0x50, 4, 1), + MTK_PIN_DRV_GRP(124, DRV_BASE+0x50, 4, 1), + MTK_PIN_DRV_GRP(125, DRV_BASE+0x30, 12, 1), + MTK_PIN_DRV_GRP(126, DRV_BASE+0x30, 12, 1), + MTK_PIN_DRV_GRP(127, DRV_BASE+0x50, 8, 1), + MTK_PIN_DRV_GRP(128, DRV_BASE+0x40, 0, 1), + MTK_PIN_DRV_GRP(129, DRV_BASE+0x40, 0, 1), + MTK_PIN_DRV_GRP(130, DRV_BASE+0x40, 0, 1), + MTK_PIN_DRV_GRP(131, DRV_BASE+0x40, 0, 1), + MTK_PIN_DRV_GRP(132, DRV_BASE+0x40, 0, 1) +}; + +static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = { + .pins = mtk_pins_mt8173, + .npins = ARRAY_SIZE(mtk_pins_mt8173), + .grp_desc = mt8173_drv_grp, + .n_grp_cls = ARRAY_SIZE(mt8173_drv_grp), + .pin_drv_grp = mt8173_pin_drv, + .n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv), + .spec_pull_set = spec_pull_set, + .spec_ies_smt_set = spec_ies_smt_set, + .dir_offset = 0x0000, + .pullen_offset = 0x0100, + .pullsel_offset = 0x0200, + .dout_offset = 0x0400, + .din_offset = 0x0500, + .pinmux_offset = 0x0600, + .type1_start = 135, + .type1_end = 135, + .port_shf = 4, + .port_mask = 0xf, + .port_align = 4, + .eint_offsets = { + .name = "mt8173_eint", + .stat = 0x000, + .ack = 0x040, + .mask = 0x080, + .mask_set = 0x0c0, + .mask_clr = 0x100, + .sens = 0x140, + .sens_set = 0x180, + .sens_clr = 0x1c0, + .soft = 0x200, + .soft_set = 0x240, + .soft_clr = 0x280, + .pol = 0x300, + .pol_set = 0x340, + .pol_clr = 0x380, + .dom_en = 0x400, + .dbnc_ctrl = 0x500, + .dbnc_set = 0x600, + .dbnc_clr = 0x700, + .port_mask = 7, + .ports = 6, + }, + .ap_num = 224, + .db_cnt = 16, +}; + +static int mt8173_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_pctrl_init(pdev, &mt8173_pinctrl_data); +} + +static const struct of_device_id mt8173_pctrl_match[] = { + { + .compatible = "mediatek,mt8173-pinctrl", + }, + { } +}; +MODULE_DEVICE_TABLE(of, mt8173_pctrl_match); + +static struct platform_driver mtk_pinctrl_driver = { + .probe = mt8173_pinctrl_probe, + .driver = { + .name = "mediatek-mt8173-pinctrl", + .of_match_table = mt8173_pctrl_match, + }, +}; + +static int __init mtk_pinctrl_init(void) +{ + return platform_driver_register(&mtk_pinctrl_driver); +} + +module_init(mtk_pinctrl_init); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek Pinctrl Driver"); +MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c new file mode 100644 index 000000000000..493294c0ebe6 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -0,0 +1,1257 @@ +/* + * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver. + * Copyright (c) 2014 MediaTek Inc. + * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/of_irq.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/bitops.h> +#include <linux/regmap.h> +#include <linux/mfd/syscon.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <dt-bindings/pinctrl/mt65xx.h> + +#include "../core.h" +#include "../pinconf.h" +#include "../pinctrl-utils.h" +#include "pinctrl-mtk-common.h" + +#define MAX_GPIO_MODE_PER_REG 5 +#define GPIO_MODE_BITS 3 + +static const char * const mtk_gpio_functions[] = { + "func0", "func1", "func2", "func3", + "func4", "func5", "func6", "func7", +}; + +/* + * There are two base address for pull related configuration + * in mt8135, and different GPIO pins use different base address. + * When pin number greater than type1_start and less than type1_end, + * should use the second base address. + */ +static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl, + unsigned long pin) +{ + if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end) + return pctl->regmap2; + return pctl->regmap1; +} + +static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin) +{ + /* Different SoC has different mask and port shift. */ + return ((pin >> 4) & pctl->devdata->port_mask) + << pctl->devdata->port_shf; +} + +static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned offset, + bool input) +{ + unsigned int reg_addr; + unsigned int bit; + struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; + bit = BIT(offset & 0xf); + + if (input) + /* Different SoC has different alignment offset. */ + reg_addr = CLR_ADDR(reg_addr, pctl); + else + reg_addr = SET_ADDR(reg_addr, pctl); + + regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); + return 0; +} + +static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + unsigned int reg_addr; + unsigned int bit; + struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); + + reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset; + bit = BIT(offset & 0xf); + + if (value) + reg_addr = SET_ADDR(reg_addr, pctl); + else + reg_addr = CLR_ADDR(reg_addr, pctl); + + regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); +} + +static void mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, + int value, enum pin_config_param param) +{ + unsigned int reg_addr, offset; + unsigned int bit; + int ret; + + /* + * Due to some pins are irregular, their input enable and smt + * control register are discontinuous, but they are mapping together. + * So we need this special handle. + */ + if (pctl->devdata->spec_ies_smt_set) { + ret = pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), + pin, pctl->devdata->port_align, value); + if (!ret) + return; + } + + bit = BIT(pin & 0xf); + + if (param == PIN_CONFIG_INPUT_ENABLE) + offset = pctl->devdata->ies_offset; + else + offset = pctl->devdata->smt_offset; + + if (value) + reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl); + else + reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl); + + regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit); +} + +static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin( + struct mtk_pinctrl *pctl, unsigned long pin) { + int i; + + for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) { + const struct mtk_pin_drv_grp *pin_drv = + pctl->devdata->pin_drv_grp + i; + if (pin == pin_drv->pin) + return pin_drv; + } + + return NULL; +} + +static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl, + unsigned int pin, unsigned char driving) +{ + const struct mtk_pin_drv_grp *pin_drv; + unsigned int val; + unsigned int bits, mask, shift; + const struct mtk_drv_group_desc *drv_grp; + + if (pin >= pctl->devdata->npins) + return -EINVAL; + + pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin); + if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls) + return -EINVAL; + + drv_grp = pctl->devdata->grp_desc + pin_drv->grp; + if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv + && !(driving % drv_grp->step)) { + val = driving / drv_grp->step - 1; + bits = drv_grp->high_bit - drv_grp->low_bit + 1; + mask = BIT(bits) - 1; + shift = pin_drv->bit + drv_grp->low_bit; + mask <<= shift; + val <<= shift; + return regmap_update_bits(mtk_get_regmap(pctl, pin), + pin_drv->offset, mask, val); + } + + return -EINVAL; +} + +static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, + unsigned int pin, bool enable, bool isup, unsigned int arg) +{ + unsigned int bit; + unsigned int reg_pullen, reg_pullsel; + int ret; + + /* Some pins' pull setting are very different, + * they have separate pull up/down bit, R0 and R1 + * resistor bit, so we need this special handle. + */ + if (pctl->devdata->spec_pull_set) { + ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin), + pin, pctl->devdata->port_align, isup, arg); + if (!ret) + return 0; + } + + /* For generic pull config, default arg value should be 0 or 1. */ + if (arg != 0 && arg != 1) { + dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n", + arg, pin); + return -EINVAL; + } + + bit = BIT(pin & 0xf); + if (enable) + reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) + + pctl->devdata->pullen_offset, pctl); + else + reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) + + pctl->devdata->pullen_offset, pctl); + + if (isup) + reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) + + pctl->devdata->pullsel_offset, pctl); + else + reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) + + pctl->devdata->pullsel_offset, pctl); + + regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit); + regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit); + return 0; +} + +static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev, + unsigned int pin, enum pin_config_param param, + enum pin_config_param arg) +{ + struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + mtk_pconf_set_pull_select(pctl, pin, false, false, arg); + break; + case PIN_CONFIG_BIAS_PULL_UP: + mtk_pconf_set_pull_select(pctl, pin, true, true, arg); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + mtk_pconf_set_pull_select(pctl, pin, true, false, arg); + break; + case PIN_CONFIG_INPUT_ENABLE: + mtk_pconf_set_ies_smt(pctl, pin, arg, param); + break; + case PIN_CONFIG_OUTPUT: + mtk_gpio_set(pctl->chip, pin, arg); + mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false); + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + mtk_pconf_set_ies_smt(pctl, pin, arg, param); + break; + case PIN_CONFIG_DRIVE_STRENGTH: + mtk_pconf_set_driving(pctl, pin, arg); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, + unsigned group, + unsigned long *config) +{ + struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *config = pctl->groups[group].config; + + return 0; +} + +static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, + unsigned long *configs, unsigned num_configs) +{ + struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct mtk_pinctrl_group *g = &pctl->groups[group]; + int i; + + for (i = 0; i < num_configs; i++) { + mtk_pconf_parse_conf(pctldev, g->pin, + pinconf_to_config_param(configs[i]), + pinconf_to_config_argument(configs[i])); + + g->config = configs[i]; + } + + return 0; +} + +static const struct pinconf_ops mtk_pconf_ops = { + .pin_config_group_get = mtk_pconf_group_get, + .pin_config_group_set = mtk_pconf_group_set, +}; + +static struct mtk_pinctrl_group * +mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin) +{ + int i; + + for (i = 0; i < pctl->ngroups; i++) { + struct mtk_pinctrl_group *grp = pctl->groups + i; + + if (grp->pin == pin) + return grp; + } + + return NULL; +} + +static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin( + struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum) +{ + const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num; + const struct mtk_desc_function *func = pin->functions; + + while (func && func->name) { + if (func->muxval == fnum) + return func; + func++; + } + + return NULL; +} + +static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl, + u32 pin_num, u32 fnum) +{ + int i; + + for (i = 0; i < pctl->devdata->npins; i++) { + const struct mtk_desc_pin *pin = pctl->devdata->pins + i; + + if (pin->pin.number == pin_num) { + const struct mtk_desc_function *func = + pin->functions; + + while (func && func->name) { + if (func->muxval == fnum) + return true; + func++; + } + + break; + } + } + + return false; +} + +static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl, + u32 pin, u32 fnum, struct mtk_pinctrl_group *grp, + struct pinctrl_map **map, unsigned *reserved_maps, + unsigned *num_maps) +{ + bool ret; + + if (*num_maps == *reserved_maps) + return -ENOSPC; + + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*num_maps].data.mux.group = grp->name; + + ret = mtk_pctrl_is_function_valid(pctl, pin, fnum); + if (!ret) { + dev_err(pctl->dev, "invalid function %d on pin %d .\n", + fnum, pin); + return -EINVAL; + } + + (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum]; + (*num_maps)++; + + return 0; +} + +static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *node, + struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps) +{ + struct property *pins; + u32 pinfunc, pin, func; + int num_pins, num_funcs, maps_per_pin; + unsigned long *configs; + unsigned int num_configs; + bool has_config = 0; + int i, err; + unsigned reserve = 0; + struct mtk_pinctrl_group *grp; + struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + pins = of_find_property(node, "pinmux", NULL); + if (!pins) { + dev_err(pctl->dev, "missing pins property in node %s .\n", + node->name); + return -EINVAL; + } + + err = pinconf_generic_parse_dt_config(node, pctldev, &configs, + &num_configs); + if (num_configs) + has_config = 1; + + num_pins = pins->length / sizeof(u32); + num_funcs = num_pins; + maps_per_pin = 0; + if (num_funcs) + maps_per_pin++; + if (has_config && num_pins >= 1) + maps_per_pin++; + + if (!num_pins || !maps_per_pin) + return -EINVAL; + + reserve = num_pins * maps_per_pin; + + err = pinctrl_utils_reserve_map(pctldev, map, + reserved_maps, num_maps, reserve); + if (err < 0) + goto fail; + + for (i = 0; i < num_pins; i++) { + err = of_property_read_u32_index(node, "pinmux", + i, &pinfunc); + if (err) + goto fail; + + pin = MTK_GET_PIN_NO(pinfunc); + func = MTK_GET_PIN_FUNC(pinfunc); + + if (pin >= pctl->devdata->npins || + func >= ARRAY_SIZE(mtk_gpio_functions)) { + dev_err(pctl->dev, "invalid pins value.\n"); + err = -EINVAL; + goto fail; + } + + grp = mtk_pctrl_find_group_by_pin(pctl, pin); + if (!grp) { + dev_err(pctl->dev, "unable to match pin %d to group\n", + pin); + return -EINVAL; + } + + err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, + reserved_maps, num_maps); + if (err < 0) + goto fail; + + if (has_config) { + err = pinctrl_utils_add_map_configs(pctldev, map, + reserved_maps, num_maps, grp->name, + configs, num_configs, + PIN_MAP_TYPE_CONFIGS_GROUP); + if (err < 0) + goto fail; + } + } + + return 0; + +fail: + return err; +} + +static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, unsigned *num_maps) +{ + struct device_node *np; + unsigned reserved_maps; + int ret; + + *map = NULL; + *num_maps = 0; + reserved_maps = 0; + + for_each_child_of_node(np_config, np) { + ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map, + &reserved_maps, num_maps); + if (ret < 0) { + pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); + return ret; + } + } + + return 0; +} + +static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->ngroups; +} + +static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->groups[group].name; +} + +static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *pins = (unsigned *)&pctl->groups[group].pin; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops mtk_pctrl_ops = { + .dt_node_to_map = mtk_pctrl_dt_node_to_map, + .dt_free_map = pinctrl_utils_dt_free_map, + .get_groups_count = mtk_pctrl_get_groups_count, + .get_group_name = mtk_pctrl_get_group_name, + .get_group_pins = mtk_pctrl_get_group_pins, +}; + +static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(mtk_gpio_functions); +} + +static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return mtk_gpio_functions[selector]; +} + +static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pctl->grp_names; + *num_groups = pctl->ngroups; + + return 0; +} + +static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev, + unsigned long pin, unsigned long mode) +{ + unsigned int reg_addr; + unsigned char bit; + unsigned int val; + unsigned int mask = (1L << GPIO_MODE_BITS) - 1; + struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf) + + pctl->devdata->pinmux_offset; + + bit = pin % MAX_GPIO_MODE_PER_REG; + mask <<= (GPIO_MODE_BITS * bit); + val = (mode << (GPIO_MODE_BITS * bit)); + return regmap_update_bits(mtk_get_regmap(pctl, pin), + reg_addr, mask, val); +} + +static const struct mtk_desc_pin * +mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num) +{ + int i; + const struct mtk_desc_pin *pin; + + for (i = 0; i < pctl->devdata->npins; i++) { + pin = pctl->devdata->pins + i; + if (pin->eint.eintnum == eint_num) + return pin; + } + + return NULL; +} + +static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + bool ret; + const struct mtk_desc_function *desc; + struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct mtk_pinctrl_group *g = pctl->groups + group; + + ret = mtk_pctrl_is_function_valid(pctl, g->pin, function); + if (!ret) { + dev_err(pctl->dev, "invaild function %d on group %d .\n", + function, group); + return -EINVAL; + } + + desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function); + if (!desc) + return -EINVAL; + mtk_pmx_set_mode(pctldev, g->pin, desc->muxval); + return 0; +} + +static const struct pinmux_ops mtk_pmx_ops = { + .get_functions_count = mtk_pmx_get_funcs_cnt, + .get_function_name = mtk_pmx_get_func_name, + .get_function_groups = mtk_pmx_get_func_groups, + .set_mux = mtk_pmx_set_mux, + .gpio_set_direction = mtk_pmx_gpio_set_direction, +}; + +static int mtk_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_request_gpio(chip->base + offset); +} + +static void mtk_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + pinctrl_free_gpio(chip->base + offset); +} + +static int mtk_gpio_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + return pinctrl_gpio_direction_input(chip->base + offset); +} + +static int mtk_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + mtk_gpio_set(chip, offset, value); + return pinctrl_gpio_direction_output(chip->base + offset); +} + +static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset) +{ + unsigned int reg_addr; + unsigned int bit; + unsigned int read_val = 0; + + struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); + + reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; + bit = BIT(offset & 0xf); + regmap_read(pctl->regmap1, reg_addr, &read_val); + return !!(read_val & bit); +} + +static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + unsigned int reg_addr; + unsigned int bit; + unsigned int read_val = 0; + struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); + + if (mtk_gpio_get_direction(chip, offset)) + reg_addr = mtk_get_port(pctl, offset) + + pctl->devdata->dout_offset; + else + reg_addr = mtk_get_port(pctl, offset) + + pctl->devdata->din_offset; + + bit = BIT(offset & 0xf); + regmap_read(pctl->regmap1, reg_addr, &read_val); + return !!(read_val & bit); +} + +static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + const struct mtk_desc_pin *pin; + struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); + int irq; + + pin = pctl->devdata->pins + offset; + if (pin->eint.eintnum == NO_EINT_SUPPORT) + return -EINVAL; + + irq = irq_find_mapping(pctl->domain, pin->eint.eintnum); + if (!irq) + return -EINVAL; + + return irq; +} + +static int mtk_pinctrl_irq_request_resources(struct irq_data *d) +{ + struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); + const struct mtk_desc_pin *pin; + int ret; + + pin = mtk_find_pin_by_eint_num(pctl, d->hwirq); + + if (!pin) { + dev_err(pctl->dev, "Can not find pin\n"); + return -EINVAL; + } + + ret = gpiochip_lock_as_irq(pctl->chip, pin->pin.number); + if (ret) { + dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", + irqd_to_hwirq(d)); + return ret; + } + + /* set mux to INT mode */ + mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux); + + return 0; +} + +static void mtk_pinctrl_irq_release_resources(struct irq_data *d) +{ + struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); + const struct mtk_desc_pin *pin; + + pin = mtk_find_pin_by_eint_num(pctl, d->hwirq); + + if (!pin) { + dev_err(pctl->dev, "Can not find pin\n"); + return; + } + + gpiochip_unlock_as_irq(pctl->chip, pin->pin.number); +} + +static void __iomem *mtk_eint_get_offset(struct mtk_pinctrl *pctl, + unsigned int eint_num, unsigned int offset) +{ + unsigned int eint_base = 0; + void __iomem *reg; + + if (eint_num >= pctl->devdata->ap_num) + eint_base = pctl->devdata->ap_num; + + reg = pctl->eint_reg_base + offset + ((eint_num - eint_base) / 32) * 4; + + return reg; +} + +/* + * mtk_can_en_debounce: Check the EINT number is able to enable debounce or not + * @eint_num: the EINT number to setmtk_pinctrl + */ +static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl *pctl, + unsigned int eint_num) +{ + unsigned int sens; + unsigned int bit = BIT(eint_num % 32); + const struct mtk_eint_offsets *eint_offsets = + &pctl->devdata->eint_offsets; + + void __iomem *reg = mtk_eint_get_offset(pctl, eint_num, + eint_offsets->sens); + + if (readl(reg) & bit) + sens = MT_LEVEL_SENSITIVE; + else + sens = MT_EDGE_SENSITIVE; + + if ((eint_num < pctl->devdata->db_cnt) && (sens != MT_EDGE_SENSITIVE)) + return 1; + else + return 0; +} + +/* + * mtk_eint_get_mask: To get the eint mask + * @eint_num: the EINT number to get + */ +static unsigned int mtk_eint_get_mask(struct mtk_pinctrl *pctl, + unsigned int eint_num) +{ + unsigned int bit = BIT(eint_num % 32); + const struct mtk_eint_offsets *eint_offsets = + &pctl->devdata->eint_offsets; + + void __iomem *reg = mtk_eint_get_offset(pctl, eint_num, + eint_offsets->mask); + + return !!(readl(reg) & bit); +} + +static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq) +{ + int start_level, curr_level; + unsigned int reg_offset; + const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets); + u32 mask = 1 << (hwirq & 0x1f); + u32 port = (hwirq >> 5) & eint_offsets->port_mask; + void __iomem *reg = pctl->eint_reg_base + (port << 2); + const struct mtk_desc_pin *pin; + + pin = mtk_find_pin_by_eint_num(pctl, hwirq); + curr_level = mtk_gpio_get(pctl->chip, pin->pin.number); + do { + start_level = curr_level; + if (start_level) + reg_offset = eint_offsets->pol_clr; + else + reg_offset = eint_offsets->pol_set; + writel(mask, reg + reg_offset); + + curr_level = mtk_gpio_get(pctl->chip, pin->pin.number); + } while (start_level != curr_level); + + return start_level; +} + +static void mtk_eint_mask(struct irq_data *d) +{ + struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); + const struct mtk_eint_offsets *eint_offsets = + &pctl->devdata->eint_offsets; + u32 mask = BIT(d->hwirq & 0x1f); + void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq, + eint_offsets->mask_set); + + writel(mask, reg); +} + +static void mtk_eint_unmask(struct irq_data *d) +{ + struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); + const struct mtk_eint_offsets *eint_offsets = + &pctl->devdata->eint_offsets; + u32 mask = BIT(d->hwirq & 0x1f); + void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq, + eint_offsets->mask_clr); + + writel(mask, reg); + + if (pctl->eint_dual_edges[d->hwirq]) + mtk_eint_flip_edge(pctl, d->hwirq); +} + +static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset, + unsigned debounce) +{ + struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); + int eint_num, virq, eint_offset; + unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, dbnc; + static const unsigned int dbnc_arr[] = {0 , 1, 16, 32, 64, 128, 256}; + const struct mtk_desc_pin *pin; + struct irq_data *d; + + pin = pctl->devdata->pins + offset; + if (pin->eint.eintnum == NO_EINT_SUPPORT) + return -EINVAL; + + eint_num = pin->eint.eintnum; + virq = irq_find_mapping(pctl->domain, eint_num); + eint_offset = (eint_num % 4) * 8; + d = irq_get_irq_data(virq); + + set_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_set; + clr_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_clr; + if (!mtk_eint_can_en_debounce(pctl, eint_num)) + return -ENOSYS; + + dbnc = ARRAY_SIZE(dbnc_arr); + for (i = 0; i < ARRAY_SIZE(dbnc_arr); i++) { + if (debounce <= dbnc_arr[i]) { + dbnc = i; + break; + } + } + + if (!mtk_eint_get_mask(pctl, eint_num)) { + mtk_eint_mask(d); + unmask = 1; + } + + clr_bit = 0xff << eint_offset; + writel(clr_bit, pctl->eint_reg_base + clr_offset); + + bit = ((dbnc << EINT_DBNC_SET_DBNC_BITS) | EINT_DBNC_SET_EN) << + eint_offset; + rst = EINT_DBNC_RST_BIT << eint_offset; + writel(rst | bit, pctl->eint_reg_base + set_offset); + + /* Delay a while (more than 2T) to wait for hw debounce counter reset + work correctly */ + udelay(1); + if (unmask == 1) + mtk_eint_unmask(d); + + return 0; +} + +static struct gpio_chip mtk_gpio_chip = { + .owner = THIS_MODULE, + .request = mtk_gpio_request, + .free = mtk_gpio_free, + .direction_input = mtk_gpio_direction_input, + .direction_output = mtk_gpio_direction_output, + .get = mtk_gpio_get, + .set = mtk_gpio_set, + .to_irq = mtk_gpio_to_irq, + .set_debounce = mtk_gpio_set_debounce, + .of_gpio_n_cells = 2, +}; + +static int mtk_eint_set_type(struct irq_data *d, + unsigned int type) +{ + struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); + const struct mtk_eint_offsets *eint_offsets = + &pctl->devdata->eint_offsets; + u32 mask = BIT(d->hwirq & 0x1f); + void __iomem *reg; + + if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) || + ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) { + dev_err(pctl->dev, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n", + d->irq, d->hwirq, type); + return -EINVAL; + } + + if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) + pctl->eint_dual_edges[d->hwirq] = 1; + else + pctl->eint_dual_edges[d->hwirq] = 0; + + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) { + reg = mtk_eint_get_offset(pctl, d->hwirq, + eint_offsets->pol_clr); + writel(mask, reg); + } else { + reg = mtk_eint_get_offset(pctl, d->hwirq, + eint_offsets->pol_set); + writel(mask, reg); + } + + if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { + reg = mtk_eint_get_offset(pctl, d->hwirq, + eint_offsets->sens_clr); + writel(mask, reg); + } else { + reg = mtk_eint_get_offset(pctl, d->hwirq, + eint_offsets->sens_set); + writel(mask, reg); + } + + if (pctl->eint_dual_edges[d->hwirq]) + mtk_eint_flip_edge(pctl, d->hwirq); + + return 0; +} + +static void mtk_eint_ack(struct irq_data *d) +{ + struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); + const struct mtk_eint_offsets *eint_offsets = + &pctl->devdata->eint_offsets; + u32 mask = BIT(d->hwirq & 0x1f); + void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq, + eint_offsets->ack); + + writel(mask, reg); +} + +static struct irq_chip mtk_pinctrl_irq_chip = { + .name = "mt-eint", + .irq_mask = mtk_eint_mask, + .irq_unmask = mtk_eint_unmask, + .irq_ack = mtk_eint_ack, + .irq_set_type = mtk_eint_set_type, + .irq_request_resources = mtk_pinctrl_irq_request_resources, + .irq_release_resources = mtk_pinctrl_irq_release_resources, +}; + +static unsigned int mtk_eint_init(struct mtk_pinctrl *pctl) +{ + const struct mtk_eint_offsets *eint_offsets = + &pctl->devdata->eint_offsets; + void __iomem *reg = pctl->eint_reg_base + eint_offsets->dom_en; + unsigned int i; + + for (i = 0; i < pctl->devdata->ap_num; i += 32) { + writel(0xffffffff, reg); + reg += 4; + } + return 0; +} + +static inline void +mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index) +{ + unsigned int rst, ctrl_offset; + unsigned int bit, dbnc; + const struct mtk_eint_offsets *eint_offsets = + &pctl->devdata->eint_offsets; + + ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_ctrl; + dbnc = readl(pctl->eint_reg_base + ctrl_offset); + bit = EINT_DBNC_SET_EN << ((index % 4) * 8); + if ((bit & dbnc) > 0) { + ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_set; + rst = EINT_DBNC_RST_BIT << ((index % 4) * 8); + writel(rst, pctl->eint_reg_base + ctrl_offset); + } +} + +static void mtk_eint_irq_handler(unsigned irq, struct irq_desc *desc) +{ + struct irq_chip *chip = irq_get_chip(irq); + struct mtk_pinctrl *pctl = irq_get_handler_data(irq); + unsigned int status, eint_num; + int offset, index, virq; + const struct mtk_eint_offsets *eint_offsets = + &pctl->devdata->eint_offsets; + void __iomem *reg = mtk_eint_get_offset(pctl, 0, eint_offsets->stat); + int dual_edges, start_level, curr_level; + const struct mtk_desc_pin *pin; + + chained_irq_enter(chip, desc); + for (eint_num = 0; eint_num < pctl->devdata->ap_num; eint_num += 32) { + status = readl(reg); + reg += 4; + while (status) { + offset = __ffs(status); + index = eint_num + offset; + virq = irq_find_mapping(pctl->domain, index); + status &= ~BIT(offset); + + dual_edges = pctl->eint_dual_edges[index]; + if (dual_edges) { + /* Clear soft-irq in case we raised it + last time */ + writel(BIT(offset), reg - eint_offsets->stat + + eint_offsets->soft_clr); + + pin = mtk_find_pin_by_eint_num(pctl, index); + start_level = mtk_gpio_get(pctl->chip, + pin->pin.number); + } + + generic_handle_irq(virq); + + if (dual_edges) { + curr_level = mtk_eint_flip_edge(pctl, index); + + /* If level changed, we might lost one edge + interrupt, raised it through soft-irq */ + if (start_level != curr_level) + writel(BIT(offset), reg - + eint_offsets->stat + + eint_offsets->soft_set); + } + + if (index < pctl->devdata->db_cnt) + mtk_eint_debounce_process(pctl , index); + } + } + chained_irq_exit(chip, desc); +} + +static int mtk_pctrl_build_state(struct platform_device *pdev) +{ + struct mtk_pinctrl *pctl = platform_get_drvdata(pdev); + int i; + + pctl->ngroups = pctl->devdata->npins; + + /* Allocate groups */ + pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, + sizeof(*pctl->groups), GFP_KERNEL); + if (!pctl->groups) + return -ENOMEM; + + /* We assume that one pin is one group, use pin name as group name. */ + pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, + sizeof(*pctl->grp_names), GFP_KERNEL); + if (!pctl->grp_names) + return -ENOMEM; + + for (i = 0; i < pctl->devdata->npins; i++) { + const struct mtk_desc_pin *pin = pctl->devdata->pins + i; + struct mtk_pinctrl_group *group = pctl->groups + i; + + group->name = pin->pin.name; + group->pin = pin->pin.number; + + pctl->grp_names[i] = pin->pin.name; + } + + return 0; +} + +static struct pinctrl_desc mtk_pctrl_desc = { + .confops = &mtk_pconf_ops, + .pctlops = &mtk_pctrl_ops, + .pmxops = &mtk_pmx_ops, +}; + +int mtk_pctrl_init(struct platform_device *pdev, + const struct mtk_pinctrl_devdata *data) +{ + struct pinctrl_pin_desc *pins; + struct mtk_pinctrl *pctl; + struct device_node *np = pdev->dev.of_node, *node; + struct property *prop; + struct resource *res; + int i, ret, irq; + + pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); + if (!pctl) + return -ENOMEM; + + platform_set_drvdata(pdev, pctl); + + prop = of_find_property(np, "pins-are-numbered", NULL); + if (!prop) { + dev_err(&pdev->dev, "only support pins-are-numbered format\n"); + return -EINVAL; + } + + node = of_parse_phandle(np, "mediatek,pctl-regmap", 0); + if (node) { + pctl->regmap1 = syscon_node_to_regmap(node); + if (IS_ERR(pctl->regmap1)) + return PTR_ERR(pctl->regmap1); + } + + /* Only 8135 has two base addr, other SoCs have only one. */ + node = of_parse_phandle(np, "mediatek,pctl-regmap", 1); + if (node) { + pctl->regmap2 = syscon_node_to_regmap(node); + if (IS_ERR(pctl->regmap2)) + return PTR_ERR(pctl->regmap2); + } + + pctl->devdata = data; + ret = mtk_pctrl_build_state(pdev); + if (ret) { + dev_err(&pdev->dev, "build state failed: %d\n", ret); + return -EINVAL; + } + + pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins), + GFP_KERNEL); + if (!pins) + return -ENOMEM; + + for (i = 0; i < pctl->devdata->npins; i++) + pins[i] = pctl->devdata->pins[i].pin; + mtk_pctrl_desc.name = dev_name(&pdev->dev); + mtk_pctrl_desc.owner = THIS_MODULE; + mtk_pctrl_desc.pins = pins; + mtk_pctrl_desc.npins = pctl->devdata->npins; + pctl->dev = &pdev->dev; + pctl->pctl_dev = pinctrl_register(&mtk_pctrl_desc, &pdev->dev, pctl); + if (!pctl->pctl_dev) { + dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); + return -EINVAL; + } + + pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); + if (!pctl->chip) { + ret = -ENOMEM; + goto pctrl_error; + } + + pctl->chip = &mtk_gpio_chip; + pctl->chip->ngpio = pctl->devdata->npins; + pctl->chip->label = dev_name(&pdev->dev); + pctl->chip->dev = &pdev->dev; + pctl->chip->base = 0; + + ret = gpiochip_add(pctl->chip); + if (ret) { + ret = -EINVAL; + goto pctrl_error; + } + + /* Register the GPIO to pin mappings. */ + ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), + 0, 0, pctl->devdata->npins); + if (ret) { + ret = -EINVAL; + goto chip_error; + } + + /* Get EINT register base from dts. */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Unable to get Pinctrl resource\n"); + ret = -EINVAL; + goto chip_error; + } + + pctl->eint_reg_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pctl->eint_reg_base)) { + ret = -EINVAL; + goto chip_error; + } + + pctl->eint_dual_edges = devm_kcalloc(&pdev->dev, pctl->devdata->ap_num, + sizeof(int), GFP_KERNEL); + if (!pctl->eint_dual_edges) { + ret = -ENOMEM; + goto chip_error; + } + + irq = irq_of_parse_and_map(np, 0); + if (!irq) { + dev_err(&pdev->dev, "couldn't parse and map irq\n"); + ret = -EINVAL; + goto chip_error; + } + + pctl->domain = irq_domain_add_linear(np, + pctl->devdata->ap_num, &irq_domain_simple_ops, NULL); + if (!pctl->domain) { + dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); + ret = -ENOMEM; + goto chip_error; + } + + mtk_eint_init(pctl); + for (i = 0; i < pctl->devdata->ap_num; i++) { + int virq = irq_create_mapping(pctl->domain, i); + + irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip, + handle_level_irq); + irq_set_chip_data(virq, pctl); + set_irq_flags(virq, IRQF_VALID); + }; + + irq_set_chained_handler(irq, mtk_eint_irq_handler); + irq_set_handler_data(irq, pctl); + set_irq_flags(irq, IRQF_VALID); + return 0; + +chip_error: + gpiochip_remove(pctl->chip); +pctrl_error: + pinctrl_unregister(pctl->pctl_dev); + return ret; +} + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MediaTek Pinctrl Driver"); +MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h new file mode 100644 index 000000000000..375771db9bd0 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __PINCTRL_MTK_COMMON_H +#define __PINCTRL_MTK_COMMON_H + +#include <linux/pinctrl/pinctrl.h> +#include <linux/regmap.h> + +#define NO_EINT_SUPPORT 255 +#define MTK_CHIP_TYPE_BASE 0 +#define MTK_CHIP_TYPE_PMIC 1 +#define MT_EDGE_SENSITIVE 0 +#define MT_LEVEL_SENSITIVE 1 +#define EINT_DBNC_SET_DBNC_BITS 4 +#define EINT_DBNC_RST_BIT (0x1 << 1) +#define EINT_DBNC_SET_EN (0x1 << 0) + +struct mtk_desc_function { + const char *name; + unsigned char muxval; +}; + +struct mtk_desc_eint { + unsigned char eintmux; + unsigned char eintnum; +}; + +struct mtk_desc_pin { + struct pinctrl_pin_desc pin; + const char *chip; + const struct mtk_desc_eint eint; + const struct mtk_desc_function *functions; +}; + +#define MTK_PIN(_pin, _pad, _chip, _eint, ...) \ + { \ + .pin = _pin, \ + .chip = _chip, \ + .eint = _eint, \ + .functions = (struct mtk_desc_function[]){ \ + __VA_ARGS__, { } }, \ + } + +#define MTK_EINT_FUNCTION(_eintmux, _eintnum) \ + { \ + .eintmux = _eintmux, \ + .eintnum = _eintnum, \ + } + +#define MTK_FUNCTION(_val, _name) \ + { \ + .muxval = _val, \ + .name = _name, \ + } + +#define SET_ADDR(x, y) (x + (y->devdata->port_align)) +#define CLR_ADDR(x, y) (x + (y->devdata->port_align << 1)) + +struct mtk_pinctrl_group { + const char *name; + unsigned long config; + unsigned pin; +}; + +/** + * struct mtk_drv_group_desc - Provide driving group data. + * @max_drv: The maximum current of this group. + * @min_drv: The minimum current of this group. + * @low_bit: The lowest bit of this group. + * @high_bit: The highest bit of this group. + * @step: The step current of this group. + */ +struct mtk_drv_group_desc { + unsigned char min_drv; + unsigned char max_drv; + unsigned char low_bit; + unsigned char high_bit; + unsigned char step; +}; + +#define MTK_DRV_GRP(_min, _max, _low, _high, _step) \ + { \ + .min_drv = _min, \ + .max_drv = _max, \ + .low_bit = _low, \ + .high_bit = _high, \ + .step = _step, \ + } + +/** + * struct mtk_pin_drv_grp - Provide each pin driving info. + * @pin: The pin number. + * @offset: The offset of driving register for this pin. + * @bit: The bit of driving register for this pin. + * @grp: The group for this pin belongs to. + */ +struct mtk_pin_drv_grp { + unsigned int pin; + unsigned int offset; + unsigned char bit; + unsigned char grp; +}; + +#define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ + { \ + .pin = _pin, \ + .offset = _offset, \ + .bit = _bit, \ + .grp = _grp, \ + } + +struct mtk_eint_offsets { + const char *name; + unsigned int stat; + unsigned int ack; + unsigned int mask; + unsigned int mask_set; + unsigned int mask_clr; + unsigned int sens; + unsigned int sens_set; + unsigned int sens_clr; + unsigned int soft; + unsigned int soft_set; + unsigned int soft_clr; + unsigned int pol; + unsigned int pol_set; + unsigned int pol_clr; + unsigned int dom_en; + unsigned int dbnc_ctrl; + unsigned int dbnc_set; + unsigned int dbnc_clr; + u8 port_mask; + u8 ports; +}; + +/** + * struct mtk_pinctrl_devdata - Provide HW GPIO related data. + * @pins: An array describing all pins the pin controller affects. + * @npins: The number of entries in @pins. + * + * @grp_desc: The driving group info. + * @pin_drv_grp: The driving group for all pins. + * @spec_pull_set: Each SoC may have special pins for pull up/down setting, + * these pins' pull setting are very different, they have separate pull + * up/down bit, R0 and R1 resistor bit, so they need special pull setting. + * If special setting is success, this should return 0, otherwise it should + * return non-zero value. + * @spec_ies_smt_set: Some pins are irregular, their input enable and smt + * control register are discontinuous, but they are mapping together. That + * means when user set smt, input enable is set at the same time. So they + * also need special control. If special control is success, this should + * return 0, otherwise return non-zero value. + * + * @dir_offset: The direction register offset. + * @pullen_offset: The pull-up/pull-down enable register offset. + * @pinmux_offset: The pinmux register offset. + * + * @type1_start: Some chips have two base addresses for pull select register, + * that means some pins use the first address and others use the second. This + * member record the start of pin number to use the second address. + * @type1_end: The end of pin number to use the second address. + * + * @port_shf: The shift between two registers. + * @port_mask: The mask of register. + * @port_align: Provide clear register and set register step. + */ +struct mtk_pinctrl_devdata { + const struct mtk_desc_pin *pins; + unsigned int npins; + const struct mtk_drv_group_desc *grp_desc; + unsigned int n_grp_cls; + const struct mtk_pin_drv_grp *pin_drv_grp; + unsigned int n_pin_drv_grps; + int (*spec_pull_set)(struct regmap *reg, unsigned int pin, + unsigned char align, bool isup, unsigned int arg); + int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin, + unsigned char align, int value); + unsigned int dir_offset; + unsigned int ies_offset; + unsigned int smt_offset; + unsigned int pullen_offset; + unsigned int pullsel_offset; + unsigned int drv_offset; + unsigned int invser_offset; + unsigned int dout_offset; + unsigned int din_offset; + unsigned int pinmux_offset; + unsigned short type1_start; + unsigned short type1_end; + unsigned char port_shf; + unsigned char port_mask; + unsigned char port_align; + unsigned char chip_type; + struct mtk_eint_offsets eint_offsets; + unsigned int ap_num; + unsigned int db_cnt; +}; + +struct mtk_pinctrl { + struct regmap *regmap1; + struct regmap *regmap2; + struct device *dev; + struct gpio_chip *chip; + struct mtk_pinctrl_group *groups; + unsigned ngroups; + const char **grp_names; + struct pinctrl_dev *pctl_dev; + const struct mtk_pinctrl_devdata *devdata; + void __iomem *eint_reg_base; + struct irq_domain *domain; + int *eint_dual_edges; +}; + +int mtk_pctrl_init(struct platform_device *pdev, + const struct mtk_pinctrl_devdata *data); + +#endif /* __PINCTRL_MTK_COMMON_H */ diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h new file mode 100644 index 000000000000..e17aedb73c8d --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h @@ -0,0 +1,2114 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __PINCTRL_MTK_MT8135_H +#define __PINCTRL_MTK_MT8135_H + +#include <linux/pinctrl/pinctrl.h> +#include "pinctrl-mtk-common.h" + +static const struct mtk_desc_pin mtk_pins_mt8135[] = { + MTK_PIN( + PINCTRL_PIN(0, "MSDC0_DAT7"), + "D21", "mt8135", + MTK_EINT_FUNCTION(2, 49), + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "MSDC0_DAT7"), + MTK_FUNCTION(2, "EINT49"), + MTK_FUNCTION(3, "I2SOUT_DAT"), + MTK_FUNCTION(4, "DAC_DAT_OUT"), + MTK_FUNCTION(5, "PCM1_DO"), + MTK_FUNCTION(6, "SPI1_MO"), + MTK_FUNCTION(7, "NALE") + ), + MTK_PIN( + PINCTRL_PIN(1, "MSDC0_DAT6"), + "D22", "mt8135", + MTK_EINT_FUNCTION(2, 48), + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "MSDC0_DAT6"), + MTK_FUNCTION(2, "EINT48"), + MTK_FUNCTION(3, "I2SIN_WS"), + MTK_FUNCTION(4, "DAC_WS"), + MTK_FUNCTION(5, "PCM1_WS"), + MTK_FUNCTION(6, "SPI1_CSN"), + MTK_FUNCTION(7, "NCLE") + ), + MTK_PIN( + PINCTRL_PIN(2, "MSDC0_DAT5"), + "E22", "mt8135", + MTK_EINT_FUNCTION(2, 47), + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "MSDC0_DAT5"), + MTK_FUNCTION(2, "EINT47"), + MTK_FUNCTION(3, "I2SIN_CK"), + MTK_FUNCTION(4, "DAC_CK"), + MTK_FUNCTION(5, "PCM1_CK"), + MTK_FUNCTION(6, "SPI1_CLK"), + MTK_FUNCTION(7, "NLD4") + ), + MTK_PIN( + PINCTRL_PIN(3, "MSDC0_DAT4"), + "F21", "mt8135", + MTK_EINT_FUNCTION(2, 46), + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "MSDC0_DAT4"), + MTK_FUNCTION(2, "EINT46"), + MTK_FUNCTION(3, "A_FUNC_CK"), + MTK_FUNCTION(6, "LSCE1B_2X"), + MTK_FUNCTION(7, "NLD5") + ), + MTK_PIN( + PINCTRL_PIN(4, "MSDC0_CMD"), + "F20", "mt8135", + MTK_EINT_FUNCTION(2, 41), + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "MSDC0_CMD"), + MTK_FUNCTION(2, "EINT41"), + MTK_FUNCTION(3, "A_FUNC_DOUT[0]"), + MTK_FUNCTION(5, "USB_TEST_IO[0]"), + MTK_FUNCTION(6, "LRSTB_2X"), + MTK_FUNCTION(7, "NRNB") + ), + MTK_PIN( + PINCTRL_PIN(5, "MSDC0_CLK"), + "G18", "mt8135", + MTK_EINT_FUNCTION(2, 40), + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "MSDC0_CLK"), + MTK_FUNCTION(2, "EINT40"), + MTK_FUNCTION(3, "A_FUNC_DOUT[1]"), + MTK_FUNCTION(5, "USB_TEST_IO[1]"), + MTK_FUNCTION(6, "LPTE"), + MTK_FUNCTION(7, "NREB") + ), + MTK_PIN( + PINCTRL_PIN(6, "MSDC0_DAT3"), + "G21", "mt8135", + MTK_EINT_FUNCTION(2, 45), + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "MSDC0_DAT3"), + MTK_FUNCTION(2, "EINT45"), + MTK_FUNCTION(3, "A_FUNC_DOUT[2]"), + MTK_FUNCTION(5, "USB_TEST_IO[2]"), + MTK_FUNCTION(6, "LSCE0B_2X"), + MTK_FUNCTION(7, "NLD7") + ), + MTK_PIN( + PINCTRL_PIN(7, "MSDC0_DAT2"), + "E21", "mt8135", + MTK_EINT_FUNCTION(2, 44), + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "MSDC0_DAT2"), + MTK_FUNCTION(2, "EINT44"), + MTK_FUNCTION(3, "A_FUNC_DOUT[3]"), + MTK_FUNCTION(5, "USB_TEST_IO[3]"), + MTK_FUNCTION(6, "LSA0_2X"), + MTK_FUNCTION(7, "NLD14") + ), + MTK_PIN( + PINCTRL_PIN(8, "MSDC0_DAT1"), + "E23", "mt8135", + MTK_EINT_FUNCTION(2, 43), + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "MSDC0_DAT1"), + MTK_FUNCTION(2, "EINT43"), + MTK_FUNCTION(5, "USB_TEST_IO[4]"), + MTK_FUNCTION(6, "LSCK_2X"), + MTK_FUNCTION(7, "NLD11") + ), + MTK_PIN( + PINCTRL_PIN(9, "MSDC0_DAT0"), + "F22", "mt8135", + MTK_EINT_FUNCTION(2, 42), + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "MSDC0_DAT0"), + MTK_FUNCTION(2, "EINT42"), + MTK_FUNCTION(5, "USB_TEST_IO[5]"), + MTK_FUNCTION(6, "LSDA_2X") + ), + MTK_PIN( + PINCTRL_PIN(10, "NCEB0"), + "G20", "mt8135", + MTK_EINT_FUNCTION(2, 139), + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "NCEB0"), + MTK_FUNCTION(2, "EINT139"), + MTK_FUNCTION(7, "TESTA_OUT4") + ), + MTK_PIN( + PINCTRL_PIN(11, "NCEB1"), + "L17", "mt8135", + MTK_EINT_FUNCTION(2, 140), + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "NCEB1"), + MTK_FUNCTION(2, "EINT140"), + MTK_FUNCTION(6, "USB_DRVVBUS"), + MTK_FUNCTION(7, "TESTA_OUT5") + ), + MTK_PIN( + PINCTRL_PIN(12, "NRNB"), + "G19", "mt8135", + MTK_EINT_FUNCTION(2, 141), + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "NRNB"), + MTK_FUNCTION(2, "EINT141"), + MTK_FUNCTION(3, "A_FUNC_DOUT[4]"), + MTK_FUNCTION(7, "TESTA_OUT6") + ), + MTK_PIN( + PINCTRL_PIN(13, "NCLE"), + "J18", "mt8135", + MTK_EINT_FUNCTION(2, 142), + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "NCLE"), + MTK_FUNCTION(2, "EINT142"), + MTK_FUNCTION(3, "A_FUNC_DOUT[5]"), + MTK_FUNCTION(4, "CM2PDN_1X"), + MTK_FUNCTION(6, "NALE"), + MTK_FUNCTION(7, "TESTA_OUT7") + ), + MTK_PIN( + PINCTRL_PIN(14, "NALE"), + "J19", "mt8135", + MTK_EINT_FUNCTION(2, 143), + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "NALE"), + MTK_FUNCTION(2, "EINT143"), + MTK_FUNCTION(3, "A_FUNC_DOUT[6]"), + MTK_FUNCTION(4, "CM2MCLK_1X"), + MTK_FUNCTION(5, "IRDA_RXD"), + MTK_FUNCTION(6, "NCLE"), + MTK_FUNCTION(7, "TESTA_OUT8") + ), + MTK_PIN( + PINCTRL_PIN(15, "NREB"), + "L18", "mt8135", + MTK_EINT_FUNCTION(2, 144), + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "NREB"), + MTK_FUNCTION(2, "EINT144"), + MTK_FUNCTION(3, "A_FUNC_DOUT[7]"), + MTK_FUNCTION(4, "CM2RST_1X"), + MTK_FUNCTION(5, "IRDA_TXD"), + MTK_FUNCTION(7, "TESTA_OUT9") + ), + MTK_PIN( + PINCTRL_PIN(16, "NWEB"), + "J20", "mt8135", + MTK_EINT_FUNCTION(2, 145), + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "NWEB"), + MTK_FUNCTION(2, "EINT145"), + MTK_FUNCTION(3, "A_FUNC_DIN[0]"), + MTK_FUNCTION(4, "CM2PCLK_1X"), + MTK_FUNCTION(5, "IRDA_PDN"), + MTK_FUNCTION(7, "TESTA_OUT10") + ), + MTK_PIN( + PINCTRL_PIN(17, "NLD0"), + "K21", "mt8135", + MTK_EINT_FUNCTION(2, 146), + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "NLD0"), + MTK_FUNCTION(2, "EINT146"), + MTK_FUNCTION(3, "A_FUNC_DIN[1]"), + MTK_FUNCTION(4, "CM2DAT_1X[0]"), + MTK_FUNCTION(5, "I2SIN_CK"), + MTK_FUNCTION(6, "DAC_CK"), + MTK_FUNCTION(7, "TESTA_OUT11") + ), + MTK_PIN( + PINCTRL_PIN(18, "NLD1"), + "K22", "mt8135", + MTK_EINT_FUNCTION(2, 147), + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "NLD1"), + MTK_FUNCTION(2, "EINT147"), + MTK_FUNCTION(3, "A_FUNC_DIN[2]"), + MTK_FUNCTION(4, "CM2DAT_1X[1]"), + MTK_FUNCTION(5, "I2SIN_WS"), + MTK_FUNCTION(6, "DAC_WS"), + MTK_FUNCTION(7, "TESTA_OUT12") + ), + MTK_PIN( + PINCTRL_PIN(19, "NLD2"), + "J21", "mt8135", + MTK_EINT_FUNCTION(2, 148), + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "NLD2"), + MTK_FUNCTION(2, "EINT148"), + MTK_FUNCTION(3, "A_FUNC_DIN[3]"), + MTK_FUNCTION(4, "CM2DAT_1X[2]"), + MTK_FUNCTION(5, "I2SOUT_DAT"), + MTK_FUNCTION(6, "DAC_DAT_OUT"), + MTK_FUNCTION(7, "TESTA_OUT13") + ), + MTK_PIN( + PINCTRL_PIN(20, "NLD3"), + "J23", "mt8135", + MTK_EINT_FUNCTION(2, 149), + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "NLD3"), + MTK_FUNCTION(2, "EINT149"), + MTK_FUNCTION(3, "A_FUNC_DIN[4]"), + MTK_FUNCTION(4, "CM2DAT_1X[3]"), + MTK_FUNCTION(7, "TESTA_OUT14") + ), + MTK_PIN( + PINCTRL_PIN(21, "NLD4"), + "J22", "mt8135", + MTK_EINT_FUNCTION(2, 150), + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "NLD4"), + MTK_FUNCTION(2, "EINT150"), + MTK_FUNCTION(3, "A_FUNC_DIN[5]"), + MTK_FUNCTION(4, "CM2DAT_1X[4]"), + MTK_FUNCTION(7, "TESTA_OUT15") + ), + MTK_PIN( + PINCTRL_PIN(22, "NLD5"), + "H21", "mt8135", + MTK_EINT_FUNCTION(2, 151), + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "NLD5"), + MTK_FUNCTION(2, "EINT151"), + MTK_FUNCTION(3, "A_FUNC_DIN[6]"), + MTK_FUNCTION(4, "CM2DAT_1X[5]"), + MTK_FUNCTION(7, "TESTA_OUT16") + ), + MTK_PIN( + PINCTRL_PIN(23, "NLD6"), + "H22", "mt8135", + MTK_EINT_FUNCTION(2, 152), + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "NLD6"), + MTK_FUNCTION(2, "EINT152"), + MTK_FUNCTION(3, "A_FUNC_DIN[7]"), + MTK_FUNCTION(4, "CM2DAT_1X[6]"), + MTK_FUNCTION(7, "TESTA_OUT17") + ), + MTK_PIN( + PINCTRL_PIN(24, "NLD7"), + "H20", "mt8135", + MTK_EINT_FUNCTION(2, 153), + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "NLD7"), + MTK_FUNCTION(2, "EINT153"), + MTK_FUNCTION(3, "A_FUNC_DIN[8]"), + MTK_FUNCTION(4, "CM2DAT_1X[7]"), + MTK_FUNCTION(7, "TESTA_OUT18") + ), + MTK_PIN( + PINCTRL_PIN(25, "NLD8"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 154), + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "NLD8"), + MTK_FUNCTION(2, "EINT154"), + MTK_FUNCTION(4, "CM2DAT_1X[8]") + ), + MTK_PIN( + PINCTRL_PIN(26, "NLD9"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 155), + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "NLD9"), + MTK_FUNCTION(2, "EINT155"), + MTK_FUNCTION(4, "CM2DAT_1X[9]"), + MTK_FUNCTION(5, "PWM1") + ), + MTK_PIN( + PINCTRL_PIN(27, "NLD10"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 156), + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "NLD10"), + MTK_FUNCTION(2, "EINT156"), + MTK_FUNCTION(4, "CM2VSYNC_1X"), + MTK_FUNCTION(5, "PWM2") + ), + MTK_PIN( + PINCTRL_PIN(28, "NLD11"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 157), + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "NLD11"), + MTK_FUNCTION(2, "EINT157"), + MTK_FUNCTION(4, "CM2HSYNC_1X"), + MTK_FUNCTION(5, "PWM3") + ), + MTK_PIN( + PINCTRL_PIN(29, "NLD12"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 158), + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "NLD12"), + MTK_FUNCTION(2, "EINT158"), + MTK_FUNCTION(3, "I2SIN_CK"), + MTK_FUNCTION(4, "DAC_CK"), + MTK_FUNCTION(5, "PCM1_CK") + ), + MTK_PIN( + PINCTRL_PIN(30, "NLD13"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 159), + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "NLD13"), + MTK_FUNCTION(2, "EINT159"), + MTK_FUNCTION(3, "I2SIN_WS"), + MTK_FUNCTION(4, "DAC_WS"), + MTK_FUNCTION(5, "PCM1_WS") + ), + MTK_PIN( + PINCTRL_PIN(31, "NLD14"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 160), + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "NLD14"), + MTK_FUNCTION(2, "EINT160"), + MTK_FUNCTION(3, "I2SOUT_DAT"), + MTK_FUNCTION(4, "DAC_DAT_OUT"), + MTK_FUNCTION(5, "PCM1_DO") + ), + MTK_PIN( + PINCTRL_PIN(32, "NLD15"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 161), + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "NLD15"), + MTK_FUNCTION(2, "EINT161"), + MTK_FUNCTION(3, "DISP_PWM"), + MTK_FUNCTION(4, "PWM4"), + MTK_FUNCTION(5, "PCM1_DI") + ), + MTK_PIN( + PINCTRL_PIN(33, "MSDC0_RSTB"), + "G22", "mt8135", + MTK_EINT_FUNCTION(2, 50), + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "MSDC0_RSTB"), + MTK_FUNCTION(2, "EINT50"), + MTK_FUNCTION(3, "I2SIN_DAT"), + MTK_FUNCTION(5, "PCM1_DI"), + MTK_FUNCTION(6, "SPI1_MI"), + MTK_FUNCTION(7, "NLD10") + ), + MTK_PIN( + PINCTRL_PIN(34, "IDDIG"), + "N17", "mt8135", + MTK_EINT_FUNCTION(2, 34), + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "IDDIG"), + MTK_FUNCTION(2, "EINT34") + ), + MTK_PIN( + PINCTRL_PIN(35, "SCL3"), + "L19", "mt8135", + MTK_EINT_FUNCTION(2, 96), + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "SCL3"), + MTK_FUNCTION(2, "EINT96"), + MTK_FUNCTION(3, "CLKM6"), + MTK_FUNCTION(4, "PWM6") + ), + MTK_PIN( + PINCTRL_PIN(36, "SDA3"), + "L20", "mt8135", + MTK_EINT_FUNCTION(2, 97), + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "SDA3"), + MTK_FUNCTION(2, "EINT97") + ), + MTK_PIN( + PINCTRL_PIN(37, "AUD_CLK_MOSI"), + "L21", "mt8135", + MTK_EINT_FUNCTION(4, 19), + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "AUD_CLK"), + MTK_FUNCTION(2, "ADC_CK"), + MTK_FUNCTION(3, " HDMI_SDATA0"), + MTK_FUNCTION(4, "EINT19"), + MTK_FUNCTION(5, "USB_TEST_IO[6]"), + MTK_FUNCTION(7, "TESTA_OUT19") + ), + MTK_PIN( + PINCTRL_PIN(38, "AUD_DAT_MOSI"), + "L23", "mt8135", + MTK_EINT_FUNCTION(4, 21), + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "AUD_DAT_MOSI"), + MTK_FUNCTION(2, "ADC_WS"), + MTK_FUNCTION(3, "AUD_DAT_MISO"), + MTK_FUNCTION(4, "EINT21"), + MTK_FUNCTION(5, "USB_TEST_IO[7]"), + MTK_FUNCTION(7, "TESTA_OUT20") + ), + MTK_PIN( + PINCTRL_PIN(39, "AUD_DAT_MISO"), + "L22", "mt8135", + MTK_EINT_FUNCTION(4, 20), + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "AUD_DAT_MISO"), + MTK_FUNCTION(2, "ADC_DAT_IN"), + MTK_FUNCTION(3, "AUD_DAT_MOSI"), + MTK_FUNCTION(4, "EINT20"), + MTK_FUNCTION(5, "USB_TEST_IO[8]"), + MTK_FUNCTION(7, "TESTA_OUT21") + ), + MTK_PIN( + PINCTRL_PIN(40, "DAC_CLK"), + "P21", "mt8135", + MTK_EINT_FUNCTION(2, 22), + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "DAC_CK"), + MTK_FUNCTION(2, "EINT22"), + MTK_FUNCTION(3, " HDMI_SDATA1"), + MTK_FUNCTION(5, "USB_TEST_IO[9]"), + MTK_FUNCTION(7, "TESTA_OUT22") + ), + MTK_PIN( + PINCTRL_PIN(41, "DAC_WS"), + "N18", "mt8135", + MTK_EINT_FUNCTION(2, 24), + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "DAC_WS"), + MTK_FUNCTION(2, "EINT24"), + MTK_FUNCTION(3, " HDMI_SDATA2"), + MTK_FUNCTION(5, "USB_TEST_IO[10]"), + MTK_FUNCTION(7, "TESTA_OUT23") + ), + MTK_PIN( + PINCTRL_PIN(42, "DAC_DAT_OUT"), + "N22", "mt8135", + MTK_EINT_FUNCTION(2, 23), + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "DAC_DAT_OUT"), + MTK_FUNCTION(2, "EINT23"), + MTK_FUNCTION(3, " HDMI_SDATA3"), + MTK_FUNCTION(5, "USB_TEST_IO[11]"), + MTK_FUNCTION(7, "TESTA_OUT24") + ), + MTK_PIN( + PINCTRL_PIN(43, "PWRAP_SPI0_MO"), + "M22", "mt8135", + MTK_EINT_FUNCTION(2, 29), + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "PWRAP_SPIDI"), + MTK_FUNCTION(2, "EINT29") + ), + MTK_PIN( + PINCTRL_PIN(44, "PWRAP_SPI0_MI"), + "P23", "mt8135", + MTK_EINT_FUNCTION(2, 28), + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "PWRAP_SPIDO"), + MTK_FUNCTION(2, "EINT28") + ), + MTK_PIN( + PINCTRL_PIN(45, "PWRAP_SPI0_CSN"), + "M21", "mt8135", + MTK_EINT_FUNCTION(2, 27), + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "PWRAP_SPICS_B_I"), + MTK_FUNCTION(2, "EINT27") + ), + MTK_PIN( + PINCTRL_PIN(46, "PWRAP_SPI0_CLK"), + "P22", "mt8135", + MTK_EINT_FUNCTION(2, 26), + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "PWRAP_SPICK_I"), + MTK_FUNCTION(2, "EINT26") + ), + MTK_PIN( + PINCTRL_PIN(47, "PWRAP_EVENT"), + "M23", "mt8135", + MTK_EINT_FUNCTION(2, 25), + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "PWRAP_EVENT_IN"), + MTK_FUNCTION(2, "EINT25"), + MTK_FUNCTION(7, "TESTA_OUT2") + ), + MTK_PIN( + PINCTRL_PIN(48, "RTC32K_CK"), + "N20", "mt8135", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "RTC32K_CK") + ), + MTK_PIN( + PINCTRL_PIN(49, "WATCHDOG"), + "R22", "mt8135", + MTK_EINT_FUNCTION(2, 36), + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "WATCHDOG"), + MTK_FUNCTION(2, "EINT36") + ), + MTK_PIN( + PINCTRL_PIN(50, "SRCLKENA"), + "T22", "mt8135", + MTK_EINT_FUNCTION(2, 38), + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "SRCLKENA"), + MTK_FUNCTION(2, "EINT38") + ), + MTK_PIN( + PINCTRL_PIN(51, "SRCVOLTEN"), + "T23", "mt8135", + MTK_EINT_FUNCTION(2, 37), + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "SRCVOLTEN"), + MTK_FUNCTION(2, "EINT37") + ), + MTK_PIN( + PINCTRL_PIN(52, "EINT0"), + "T21", "mt8135", + MTK_EINT_FUNCTION(1, 0), + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "EINT0"), + MTK_FUNCTION(2, "PWM1"), + MTK_FUNCTION(3, "CLKM0"), + MTK_FUNCTION(4, " SPDIF_OUT"), + MTK_FUNCTION(5, "USB_TEST_IO[12]"), + MTK_FUNCTION(7, "USB_SCL") + ), + MTK_PIN( + PINCTRL_PIN(53, "URXD2"), + "R18", "mt8135", + MTK_EINT_FUNCTION(2, 83), + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "URXD2"), + MTK_FUNCTION(2, "EINT83"), + MTK_FUNCTION(4, " HDMI_LRCK"), + MTK_FUNCTION(5, "CLKM3"), + MTK_FUNCTION(7, "UTXD2") + ), + MTK_PIN( + PINCTRL_PIN(54, "UTXD2"), + "R17", "mt8135", + MTK_EINT_FUNCTION(2, 82), + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "UTXD2"), + MTK_FUNCTION(2, "EINT82"), + MTK_FUNCTION(4, " HDMI_BCK_OUT"), + MTK_FUNCTION(5, "CLKM2"), + MTK_FUNCTION(7, "URXD2") + ), + MTK_PIN( + PINCTRL_PIN(55, "UCTS2"), + "R20", "mt8135", + MTK_EINT_FUNCTION(2, 84), + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "UCTS2"), + MTK_FUNCTION(2, "EINT84"), + MTK_FUNCTION(5, "PWM1"), + MTK_FUNCTION(7, "URTS2") + ), + MTK_PIN( + PINCTRL_PIN(56, "URTS2"), + "R19", "mt8135", + MTK_EINT_FUNCTION(2, 85), + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "URTS2"), + MTK_FUNCTION(2, "EINT85"), + MTK_FUNCTION(5, "PWM2"), + MTK_FUNCTION(7, "UCTS2") + ), + MTK_PIN( + PINCTRL_PIN(57, "JTCK"), + "V17", "mt8135", + MTK_EINT_FUNCTION(2, 188), + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "JTCK"), + MTK_FUNCTION(2, "EINT188"), + MTK_FUNCTION(3, "DSP1_ICK") + ), + MTK_PIN( + PINCTRL_PIN(58, "JTDO"), + "T16", "mt8135", + MTK_EINT_FUNCTION(2, 190), + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "JTDO"), + MTK_FUNCTION(2, "EINT190"), + MTK_FUNCTION(3, "DSP2_IMS") + ), + MTK_PIN( + PINCTRL_PIN(59, "JTRST_B"), + "T19", "mt8135", + MTK_EINT_FUNCTION(2, 0), + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "JTRST_B"), + MTK_FUNCTION(2, "EINT0"), + MTK_FUNCTION(3, "DSP2_ICK") + ), + MTK_PIN( + PINCTRL_PIN(60, "JTDI"), + "T18", "mt8135", + MTK_EINT_FUNCTION(2, 189), + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "JTDI"), + MTK_FUNCTION(2, "EINT189"), + MTK_FUNCTION(3, "DSP1_IMS") + ), + MTK_PIN( + PINCTRL_PIN(61, "JRTCK"), + "T20", "mt8135", + MTK_EINT_FUNCTION(2, 187), + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "JRTCK"), + MTK_FUNCTION(2, "EINT187"), + MTK_FUNCTION(3, "DSP1_ID") + ), + MTK_PIN( + PINCTRL_PIN(62, "JTMS"), + "T17", "mt8135", + MTK_EINT_FUNCTION(2, 191), + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "JTMS"), + MTK_FUNCTION(2, "EINT191"), + MTK_FUNCTION(3, "DSP2_ID") + ), + MTK_PIN( + PINCTRL_PIN(63, "MSDC1_INSI"), + "V18", "mt8135", + MTK_EINT_FUNCTION(1, 15), + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "MSDC1_INSI"), + MTK_FUNCTION(3, "SCL5"), + MTK_FUNCTION(4, "PWM6"), + MTK_FUNCTION(5, "CLKM5"), + MTK_FUNCTION(7, "TESTB_OUT6") + ), + MTK_PIN( + PINCTRL_PIN(64, "MSDC1_SDWPI"), + "W18", "mt8135", + MTK_EINT_FUNCTION(2, 58), + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "MSDC1_SDWPI"), + MTK_FUNCTION(2, "EINT58"), + MTK_FUNCTION(3, "SDA5"), + MTK_FUNCTION(4, "PWM7"), + MTK_FUNCTION(5, "CLKM6"), + MTK_FUNCTION(7, "TESTB_OUT7") + ), + MTK_PIN( + PINCTRL_PIN(65, "MSDC2_INSI"), + "U22", "mt8135", + MTK_EINT_FUNCTION(1, 14), + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "MSDC2_INSI"), + MTK_FUNCTION(5, "USB_TEST_IO[27]"), + MTK_FUNCTION(7, "TESTA_OUT3") + ), + MTK_PIN( + PINCTRL_PIN(66, "MSDC2_SDWPI"), + "U21", "mt8135", + MTK_EINT_FUNCTION(2, 66), + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "MSDC2_SDWPI"), + MTK_FUNCTION(2, "EINT66"), + MTK_FUNCTION(5, "USB_TEST_IO[28]") + ), + MTK_PIN( + PINCTRL_PIN(67, "URXD4"), + "V23", "mt8135", + MTK_EINT_FUNCTION(2, 89), + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "URXD4"), + MTK_FUNCTION(2, "EINT89"), + MTK_FUNCTION(3, "URXD1"), + MTK_FUNCTION(6, "UTXD4"), + MTK_FUNCTION(7, "TESTB_OUT10") + ), + MTK_PIN( + PINCTRL_PIN(68, "UTXD4"), + "V22", "mt8135", + MTK_EINT_FUNCTION(2, 88), + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "UTXD4"), + MTK_FUNCTION(2, "EINT88"), + MTK_FUNCTION(3, "UTXD1"), + MTK_FUNCTION(6, "URXD4"), + MTK_FUNCTION(7, "TESTB_OUT11") + ), + MTK_PIN( + PINCTRL_PIN(69, "URXD1"), + "W22", "mt8135", + MTK_EINT_FUNCTION(2, 79), + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "EINT79"), + MTK_FUNCTION(3, "URXD4"), + MTK_FUNCTION(6, "UTXD1"), + MTK_FUNCTION(7, "TESTB_OUT24") + ), + MTK_PIN( + PINCTRL_PIN(70, "UTXD1"), + "V21", "mt8135", + MTK_EINT_FUNCTION(2, 78), + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "EINT78"), + MTK_FUNCTION(3, "UTXD4"), + MTK_FUNCTION(6, "URXD1"), + MTK_FUNCTION(7, "TESTB_OUT25") + ), + MTK_PIN( + PINCTRL_PIN(71, "UCTS1"), + "V19", "mt8135", + MTK_EINT_FUNCTION(2, 80), + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "UCTS1"), + MTK_FUNCTION(2, "EINT80"), + MTK_FUNCTION(5, "CLKM0"), + MTK_FUNCTION(6, "URTS1"), + MTK_FUNCTION(7, "TESTB_OUT31") + ), + MTK_PIN( + PINCTRL_PIN(72, "URTS1"), + "V20", "mt8135", + MTK_EINT_FUNCTION(2, 81), + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "URTS1"), + MTK_FUNCTION(2, "EINT81"), + MTK_FUNCTION(5, "CLKM1"), + MTK_FUNCTION(6, "UCTS1"), + MTK_FUNCTION(7, "TESTB_OUT21") + ), + MTK_PIN( + PINCTRL_PIN(73, "PWM1"), + "W17", "mt8135", + MTK_EINT_FUNCTION(2, 73), + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "PWM1"), + MTK_FUNCTION(2, "EINT73"), + MTK_FUNCTION(5, "USB_DRVVBUS"), + MTK_FUNCTION(6, "DISP_PWM"), + MTK_FUNCTION(7, "TESTB_OUT8") + ), + MTK_PIN( + PINCTRL_PIN(74, "PWM2"), + "Y17", "mt8135", + MTK_EINT_FUNCTION(2, 74), + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "PWM2"), + MTK_FUNCTION(2, "EINT74"), + MTK_FUNCTION(3, "DPI33_CK"), + MTK_FUNCTION(4, "PWM5"), + MTK_FUNCTION(5, "URXD2"), + MTK_FUNCTION(6, "DISP_PWM"), + MTK_FUNCTION(7, "TESTB_OUT9") + ), + MTK_PIN( + PINCTRL_PIN(75, "PWM3"), + "Y19", "mt8135", + MTK_EINT_FUNCTION(2, 75), + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "PWM3"), + MTK_FUNCTION(2, "EINT75"), + MTK_FUNCTION(3, "DPI33_D0"), + MTK_FUNCTION(4, "PWM6"), + MTK_FUNCTION(5, "UTXD2"), + MTK_FUNCTION(6, "DISP_PWM"), + MTK_FUNCTION(7, "TESTB_OUT12") + ), + MTK_PIN( + PINCTRL_PIN(76, "PWM4"), + "W19", "mt8135", + MTK_EINT_FUNCTION(2, 76), + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "PWM4"), + MTK_FUNCTION(2, "EINT76"), + MTK_FUNCTION(3, "DPI33_D1"), + MTK_FUNCTION(4, "PWM7"), + MTK_FUNCTION(6, "DISP_PWM"), + MTK_FUNCTION(7, "TESTB_OUT13") + ), + MTK_PIN( + PINCTRL_PIN(77, "MSDC2_DAT2"), + "W21", "mt8135", + MTK_EINT_FUNCTION(2, 63), + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "MSDC2_DAT2"), + MTK_FUNCTION(2, "EINT63"), + MTK_FUNCTION(4, "DSP2_IMS"), + MTK_FUNCTION(6, "DPI33_D6"), + MTK_FUNCTION(7, "TESTA_OUT25") + ), + MTK_PIN( + PINCTRL_PIN(78, "MSDC2_DAT3"), + "AA23", "mt8135", + MTK_EINT_FUNCTION(2, 64), + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "MSDC2_DAT3"), + MTK_FUNCTION(2, "EINT64"), + MTK_FUNCTION(4, "DSP2_ID"), + MTK_FUNCTION(6, "DPI33_D7"), + MTK_FUNCTION(7, "TESTA_OUT26") + ), + MTK_PIN( + PINCTRL_PIN(79, "MSDC2_CMD"), + "Y22", "mt8135", + MTK_EINT_FUNCTION(2, 60), + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "MSDC2_CMD"), + MTK_FUNCTION(2, "EINT60"), + MTK_FUNCTION(4, "DSP1_IMS"), + MTK_FUNCTION(5, "PCM1_WS"), + MTK_FUNCTION(6, "DPI33_D3"), + MTK_FUNCTION(7, "TESTA_OUT0") + ), + MTK_PIN( + PINCTRL_PIN(80, "MSDC2_CLK"), + "AA22", "mt8135", + MTK_EINT_FUNCTION(2, 59), + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "MSDC2_CLK"), + MTK_FUNCTION(2, "EINT59"), + MTK_FUNCTION(4, "DSP1_ICK"), + MTK_FUNCTION(5, "PCM1_CK"), + MTK_FUNCTION(6, "DPI33_D2"), + MTK_FUNCTION(7, "TESTA_OUT1") + ), + MTK_PIN( + PINCTRL_PIN(81, "MSDC2_DAT1"), + "Y21", "mt8135", + MTK_EINT_FUNCTION(2, 62), + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "MSDC2_DAT1"), + MTK_FUNCTION(2, "EINT62"), + MTK_FUNCTION(4, "DSP2_ICK"), + MTK_FUNCTION(5, "PCM1_DO"), + MTK_FUNCTION(6, "DPI33_D5") + ), + MTK_PIN( + PINCTRL_PIN(82, "MSDC2_DAT0"), + "AB22", "mt8135", + MTK_EINT_FUNCTION(2, 61), + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "MSDC2_DAT0"), + MTK_FUNCTION(2, "EINT61"), + MTK_FUNCTION(4, "DSP1_ID"), + MTK_FUNCTION(5, "PCM1_DI"), + MTK_FUNCTION(6, "DPI33_D4") + ), + MTK_PIN( + PINCTRL_PIN(83, "MSDC1_DAT0"), + "AC19", "mt8135", + MTK_EINT_FUNCTION(2, 53), + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(2, "EINT53"), + MTK_FUNCTION(3, "SCL1"), + MTK_FUNCTION(4, "PWM2"), + MTK_FUNCTION(5, "CLKM1"), + MTK_FUNCTION(7, "TESTB_OUT2") + ), + MTK_PIN( + PINCTRL_PIN(84, "MSDC1_DAT1"), + "AA19", "mt8135", + MTK_EINT_FUNCTION(2, 54), + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(2, "EINT54"), + MTK_FUNCTION(3, "SDA1"), + MTK_FUNCTION(4, "PWM3"), + MTK_FUNCTION(5, "CLKM2"), + MTK_FUNCTION(7, "TESTB_OUT3") + ), + MTK_PIN( + PINCTRL_PIN(85, "MSDC1_CMD"), + "AA20", "mt8135", + MTK_EINT_FUNCTION(2, 52), + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "MSDC1_CMD"), + MTK_FUNCTION(2, "EINT52"), + MTK_FUNCTION(3, "SDA0"), + MTK_FUNCTION(4, "PWM1"), + MTK_FUNCTION(5, "CLKM0"), + MTK_FUNCTION(7, "TESTB_OUT1") + ), + MTK_PIN( + PINCTRL_PIN(86, "MSDC1_CLK"), + "AB19", "mt8135", + MTK_EINT_FUNCTION(2, 51), + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(2, "EINT51"), + MTK_FUNCTION(3, "SCL0"), + MTK_FUNCTION(4, "DISP_PWM"), + MTK_FUNCTION(7, "TESTB_OUT0") + ), + MTK_PIN( + PINCTRL_PIN(87, "MSDC1_DAT2"), + "AA21", "mt8135", + MTK_EINT_FUNCTION(2, 55), + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(2, "EINT55"), + MTK_FUNCTION(3, "SCL4"), + MTK_FUNCTION(4, "PWM4"), + MTK_FUNCTION(5, "CLKM3"), + MTK_FUNCTION(7, "TESTB_OUT4") + ), + MTK_PIN( + PINCTRL_PIN(88, "MSDC1_DAT3"), + "AB20", "mt8135", + MTK_EINT_FUNCTION(2, 56), + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "MSDC1_DAT3"), + MTK_FUNCTION(2, "EINT56"), + MTK_FUNCTION(3, "SDA4"), + MTK_FUNCTION(4, "PWM5"), + MTK_FUNCTION(5, "CLKM4"), + MTK_FUNCTION(7, "TESTB_OUT5") + ), + MTK_PIN( + PINCTRL_PIN(89, "MSDC4_DAT0"), + "AB8", "mt8135", + MTK_EINT_FUNCTION(2, 133), + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "MSDC4_DAT0"), + MTK_FUNCTION(2, "EINT133"), + MTK_FUNCTION(4, "EXT_FRAME_SYNC"), + MTK_FUNCTION(5, "USB_DRVVBUS"), + MTK_FUNCTION(6, "A_FUNC_DIN[9]"), + MTK_FUNCTION(7, "LPTE") + ), + MTK_PIN( + PINCTRL_PIN(90, "MSDC4_DAT1"), + "AB7", "mt8135", + MTK_EINT_FUNCTION(2, 134), + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "MSDC4_DAT1"), + MTK_FUNCTION(2, "EINT134"), + MTK_FUNCTION(6, "A_FUNC_DIN[10]"), + MTK_FUNCTION(7, "LRSTB_1X") + ), + MTK_PIN( + PINCTRL_PIN(91, "MSDC4_DAT5"), + "AA8", "mt8135", + MTK_EINT_FUNCTION(2, 136), + MTK_FUNCTION(0, "GPIO91"), + MTK_FUNCTION(1, "MSDC4_DAT5"), + MTK_FUNCTION(2, "EINT136"), + MTK_FUNCTION(3, "I2SIN_WS"), + MTK_FUNCTION(4, "DAC_WS"), + MTK_FUNCTION(5, "PCM1_WS"), + MTK_FUNCTION(6, "A_FUNC_DIN[11]"), + MTK_FUNCTION(7, "SPI1_CSN") + ), + MTK_PIN( + PINCTRL_PIN(92, "MSDC4_DAT6"), + "AC4", "mt8135", + MTK_EINT_FUNCTION(2, 137), + MTK_FUNCTION(0, "GPIO92"), + MTK_FUNCTION(1, "MSDC4_DAT6"), + MTK_FUNCTION(2, "EINT137"), + MTK_FUNCTION(3, "I2SOUT_DAT"), + MTK_FUNCTION(4, "DAC_DAT_OUT"), + MTK_FUNCTION(5, "PCM1_DO"), + MTK_FUNCTION(6, "A_FUNC_DIN[12]"), + MTK_FUNCTION(7, "SPI1_MO") + ), + MTK_PIN( + PINCTRL_PIN(93, "MSDC4_DAT7"), + "AC6", "mt8135", + MTK_EINT_FUNCTION(2, 138), + MTK_FUNCTION(0, "GPIO93"), + MTK_FUNCTION(1, "MSDC4_DAT7"), + MTK_FUNCTION(2, "EINT138"), + MTK_FUNCTION(3, "I2SIN_DAT"), + MTK_FUNCTION(5, "PCM1_DI"), + MTK_FUNCTION(6, "A_FUNC_DIN[13]"), + MTK_FUNCTION(7, "SPI1_MI") + ), + MTK_PIN( + PINCTRL_PIN(94, "MSDC4_DAT4"), + "AA7", "mt8135", + MTK_EINT_FUNCTION(2, 135), + MTK_FUNCTION(0, "GPIO94"), + MTK_FUNCTION(1, "MSDC4_DAT4"), + MTK_FUNCTION(2, "EINT135"), + MTK_FUNCTION(3, "I2SIN_CK"), + MTK_FUNCTION(4, "DAC_CK"), + MTK_FUNCTION(5, "PCM1_CK"), + MTK_FUNCTION(6, "A_FUNC_DIN[14]"), + MTK_FUNCTION(7, "SPI1_CLK") + ), + MTK_PIN( + PINCTRL_PIN(95, "MSDC4_DAT2"), + "AB6", "mt8135", + MTK_EINT_FUNCTION(2, 131), + MTK_FUNCTION(0, "GPIO95"), + MTK_FUNCTION(1, "MSDC4_DAT2"), + MTK_FUNCTION(2, "EINT131"), + MTK_FUNCTION(3, "I2SIN_WS"), + MTK_FUNCTION(4, "CM2PDN_2X"), + MTK_FUNCTION(5, "DAC_WS"), + MTK_FUNCTION(6, "PCM1_WS"), + MTK_FUNCTION(7, "LSCE0B_1X") + ), + MTK_PIN( + PINCTRL_PIN(96, "MSDC4_CLK"), + "AB5", "mt8135", + MTK_EINT_FUNCTION(2, 129), + MTK_FUNCTION(0, "GPIO96"), + MTK_FUNCTION(1, "MSDC4_CLK"), + MTK_FUNCTION(2, "EINT129"), + MTK_FUNCTION(3, "DPI1_CK_2X"), + MTK_FUNCTION(4, "CM2PCLK_2X"), + MTK_FUNCTION(5, "PWM4"), + MTK_FUNCTION(6, "PCM1_DI"), + MTK_FUNCTION(7, "LSCK_1X") + ), + MTK_PIN( + PINCTRL_PIN(97, "MSDC4_DAT3"), + "Y8", "mt8135", + MTK_EINT_FUNCTION(2, 132), + MTK_FUNCTION(0, "GPIO97"), + MTK_FUNCTION(1, "MSDC4_DAT3"), + MTK_FUNCTION(2, "EINT132"), + MTK_FUNCTION(3, "I2SOUT_DAT"), + MTK_FUNCTION(4, "CM2RST_2X"), + MTK_FUNCTION(5, "DAC_DAT_OUT"), + MTK_FUNCTION(6, "PCM1_DO"), + MTK_FUNCTION(7, "LSCE1B_1X") + ), + MTK_PIN( + PINCTRL_PIN(98, "MSDC4_CMD"), + "AC3", "mt8135", + MTK_EINT_FUNCTION(2, 128), + MTK_FUNCTION(0, "GPIO98"), + MTK_FUNCTION(1, "MSDC4_CMD"), + MTK_FUNCTION(2, "EINT128"), + MTK_FUNCTION(3, "DPI1_DE_2X"), + MTK_FUNCTION(5, "PWM3"), + MTK_FUNCTION(7, "LSDA_1X") + ), + MTK_PIN( + PINCTRL_PIN(99, "MSDC4_RSTB"), + "AB4", "mt8135", + MTK_EINT_FUNCTION(2, 130), + MTK_FUNCTION(0, "GPIO99"), + MTK_FUNCTION(1, "MSDC4_RSTB"), + MTK_FUNCTION(2, "EINT130"), + MTK_FUNCTION(3, "I2SIN_CK"), + MTK_FUNCTION(4, "CM2MCLK_2X"), + MTK_FUNCTION(5, "DAC_CK"), + MTK_FUNCTION(6, "PCM1_CK"), + MTK_FUNCTION(7, "LSA0_1X") + ), + MTK_PIN( + PINCTRL_PIN(100, "SDA0"), + "W9", "mt8135", + MTK_EINT_FUNCTION(2, 91), + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "SDA0"), + MTK_FUNCTION(2, "EINT91"), + MTK_FUNCTION(3, "CLKM1"), + MTK_FUNCTION(4, "PWM1"), + MTK_FUNCTION(7, "A_FUNC_DIN[15]") + ), + MTK_PIN( + PINCTRL_PIN(101, "SCL0"), + "W11", "mt8135", + MTK_EINT_FUNCTION(2, 90), + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "SCL0"), + MTK_FUNCTION(2, "EINT90"), + MTK_FUNCTION(3, "CLKM0"), + MTK_FUNCTION(4, "DISP_PWM"), + MTK_FUNCTION(7, "A_FUNC_DIN[16]") + ), + MTK_PIN( + PINCTRL_PIN(102, "EINT10_AUXIN2"), + "AA3", "mt8135", + MTK_EINT_FUNCTION(1, 10), + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "EINT10"), + MTK_FUNCTION(5, "USB_TEST_IO[16]"), + MTK_FUNCTION(6, "TESTB_OUT16"), + MTK_FUNCTION(7, "A_FUNC_DIN[17]") + ), + MTK_PIN( + PINCTRL_PIN(103, "EINT11_AUXIN3"), + "AB2", "mt8135", + MTK_EINT_FUNCTION(1, 11), + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "EINT11"), + MTK_FUNCTION(5, "USB_TEST_IO[17]"), + MTK_FUNCTION(6, "TESTB_OUT17"), + MTK_FUNCTION(7, "A_FUNC_DIN[18]") + ), + MTK_PIN( + PINCTRL_PIN(104, "EINT16_AUXIN4"), + "AB3", "mt8135", + MTK_EINT_FUNCTION(1, 16), + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "EINT16"), + MTK_FUNCTION(5, "USB_TEST_IO[18]"), + MTK_FUNCTION(6, "TESTB_OUT18"), + MTK_FUNCTION(7, "A_FUNC_DIN[19]") + ), + MTK_PIN( + PINCTRL_PIN(105, "I2S_CLK"), + "W6", "mt8135", + MTK_EINT_FUNCTION(2, 10), + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "I2SIN_CK"), + MTK_FUNCTION(2, "EINT10"), + MTK_FUNCTION(3, "DAC_CK"), + MTK_FUNCTION(4, "PCM1_CK"), + MTK_FUNCTION(5, "USB_TEST_IO[19]"), + MTK_FUNCTION(6, "TESTB_OUT19"), + MTK_FUNCTION(7, "A_FUNC_DIN[20]") + ), + MTK_PIN( + PINCTRL_PIN(106, "I2S_WS"), + "AA6", "mt8135", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "I2SIN_WS"), + MTK_FUNCTION(3, "DAC_WS"), + MTK_FUNCTION(4, "PCM1_WS"), + MTK_FUNCTION(5, "USB_TEST_IO[20]"), + MTK_FUNCTION(6, "TESTB_OUT20"), + MTK_FUNCTION(7, "A_FUNC_DIN[21]") + ), + MTK_PIN( + PINCTRL_PIN(107, "I2S_DATA_IN"), + "AA5", "mt8135", + MTK_EINT_FUNCTION(2, 11), + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "I2SIN_DAT"), + MTK_FUNCTION(2, "EINT11"), + MTK_FUNCTION(4, "PCM1_DI"), + MTK_FUNCTION(5, "USB_TEST_IO[21]"), + MTK_FUNCTION(6, "TESTB_OUT22"), + MTK_FUNCTION(7, "A_FUNC_DIN[22]") + ), + MTK_PIN( + PINCTRL_PIN(108, "I2S_DATA_OUT"), + "AA4", "mt8135", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "I2SOUT_DAT"), + MTK_FUNCTION(3, "DAC_DAT_OUT"), + MTK_FUNCTION(4, "PCM1_DO"), + MTK_FUNCTION(5, "USB_TEST_IO[22]"), + MTK_FUNCTION(6, "TESTB_OUT23"), + MTK_FUNCTION(7, "A_FUNC_DIN[23]") + ), + MTK_PIN( + PINCTRL_PIN(109, "EINT5"), + "W5", "mt8135", + MTK_EINT_FUNCTION(1, 5), + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(1, "EINT5"), + MTK_FUNCTION(2, "PWM5"), + MTK_FUNCTION(3, "CLKM3"), + MTK_FUNCTION(4, "GPU_JTRSTB"), + MTK_FUNCTION(5, "USB_TEST_IO[23]"), + MTK_FUNCTION(6, "TESTB_OUT26"), + MTK_FUNCTION(7, "A_FUNC_DIN[24]") + ), + MTK_PIN( + PINCTRL_PIN(110, "EINT6"), + "V5", "mt8135", + MTK_EINT_FUNCTION(1, 6), + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "EINT6"), + MTK_FUNCTION(2, "PWM6"), + MTK_FUNCTION(3, "CLKM4"), + MTK_FUNCTION(4, "GPU_JTMS"), + MTK_FUNCTION(5, "USB_TEST_IO[24]"), + MTK_FUNCTION(6, "TESTB_OUT27"), + MTK_FUNCTION(7, "A_FUNC_DIN[25]") + ), + MTK_PIN( + PINCTRL_PIN(111, "EINT7"), + "W3", "mt8135", + MTK_EINT_FUNCTION(1, 7), + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "EINT7"), + MTK_FUNCTION(2, "PWM7"), + MTK_FUNCTION(3, "CLKM5"), + MTK_FUNCTION(4, "GPU_JTDO"), + MTK_FUNCTION(5, "USB_TEST_IO[25]"), + MTK_FUNCTION(6, "TESTB_OUT28"), + MTK_FUNCTION(7, "A_FUNC_DIN[26]") + ), + MTK_PIN( + PINCTRL_PIN(112, "EINT8"), + "V6", "mt8135", + MTK_EINT_FUNCTION(1, 8), + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "EINT8"), + MTK_FUNCTION(2, "DISP_PWM"), + MTK_FUNCTION(3, "CLKM6"), + MTK_FUNCTION(4, "GPU_JTDI"), + MTK_FUNCTION(5, "USB_TEST_IO[26]"), + MTK_FUNCTION(6, "TESTB_OUT29"), + MTK_FUNCTION(7, "EXT_FRAME_SYNC") + ), + MTK_PIN( + PINCTRL_PIN(113, "EINT9"), + "W8", "mt8135", + MTK_EINT_FUNCTION(1, 9), + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "EINT9"), + MTK_FUNCTION(4, "GPU_JTCK"), + MTK_FUNCTION(5, "USB_DRVVBUS"), + MTK_FUNCTION(6, "TESTB_OUT30"), + MTK_FUNCTION(7, "A_FUNC_DIN[27]") + ), + MTK_PIN( + PINCTRL_PIN(114, "LPCE1B"), + "W4", "mt8135", + MTK_EINT_FUNCTION(2, 127), + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "LPCE1B"), + MTK_FUNCTION(2, "EINT127"), + MTK_FUNCTION(5, "PWM2"), + MTK_FUNCTION(6, "TESTB_OUT14"), + MTK_FUNCTION(7, "A_FUNC_DIN[28]") + ), + MTK_PIN( + PINCTRL_PIN(115, "LPCE0B"), + "T5", "mt8135", + MTK_EINT_FUNCTION(2, 126), + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "LPCE0B"), + MTK_FUNCTION(2, "EINT126"), + MTK_FUNCTION(5, "PWM1"), + MTK_FUNCTION(6, "TESTB_OUT15"), + MTK_FUNCTION(7, "A_FUNC_DIN[29]") + ), + MTK_PIN( + PINCTRL_PIN(116, "DISP_PWM"), + "V4", "mt8135", + MTK_EINT_FUNCTION(2, 77), + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(2, "EINT77"), + MTK_FUNCTION(3, "LSDI"), + MTK_FUNCTION(4, "PWM1"), + MTK_FUNCTION(5, "PWM2"), + MTK_FUNCTION(7, "PWM3") + ), + MTK_PIN( + PINCTRL_PIN(117, "EINT1"), + "T6", "mt8135", + MTK_EINT_FUNCTION(1, 1), + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "EINT1"), + MTK_FUNCTION(2, "PWM2"), + MTK_FUNCTION(3, "CLKM1"), + MTK_FUNCTION(5, "USB_TEST_IO[13]"), + MTK_FUNCTION(7, "USB_SDA") + ), + MTK_PIN( + PINCTRL_PIN(118, "EINT2"), + "T4", "mt8135", + MTK_EINT_FUNCTION(1, 2), + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "EINT2"), + MTK_FUNCTION(2, "PWM3"), + MTK_FUNCTION(3, "CLKM2"), + MTK_FUNCTION(5, "USB_TEST_IO[14]"), + MTK_FUNCTION(6, "SRCLKENAI2"), + MTK_FUNCTION(7, "A_FUNC_DIN[30]") + ), + MTK_PIN( + PINCTRL_PIN(119, "EINT3"), + "R4", "mt8135", + MTK_EINT_FUNCTION(1, 3), + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "EINT3"), + MTK_FUNCTION(5, "USB_TEST_IO[15]"), + MTK_FUNCTION(6, "SRCLKENAI1"), + MTK_FUNCTION(7, "EXT_26M_CK") + ), + MTK_PIN( + PINCTRL_PIN(120, "EINT4"), + "R5", "mt8135", + MTK_EINT_FUNCTION(1, 4), + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "EINT4"), + MTK_FUNCTION(2, "PWM4"), + MTK_FUNCTION(5, "USB_DRVVBUS"), + MTK_FUNCTION(7, "A_FUNC_DIN[31]") + ), + MTK_PIN( + PINCTRL_PIN(121, "DPIDE"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 100), + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "DPI0_DE"), + MTK_FUNCTION(2, "EINT100"), + MTK_FUNCTION(3, "I2SOUT_DAT"), + MTK_FUNCTION(4, "DAC_DAT_OUT"), + MTK_FUNCTION(5, "PCM1_DO"), + MTK_FUNCTION(6, "IRDA_TXD") + ), + MTK_PIN( + PINCTRL_PIN(122, "DPICK"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 101), + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "DPI0_CK"), + MTK_FUNCTION(2, "EINT101"), + MTK_FUNCTION(3, "I2SIN_DAT"), + MTK_FUNCTION(5, "PCM1_DI"), + MTK_FUNCTION(6, "IRDA_PDN") + ), + MTK_PIN( + PINCTRL_PIN(123, "DPIG4"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 114), + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "DPI0_G4"), + MTK_FUNCTION(2, "EINT114"), + MTK_FUNCTION(4, "CM2DAT_2X[0]"), + MTK_FUNCTION(5, "DSP2_ID") + ), + MTK_PIN( + PINCTRL_PIN(124, "DPIG5"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 115), + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "DPI0_G5"), + MTK_FUNCTION(2, "EINT115"), + MTK_FUNCTION(4, "CM2DAT_2X[1]"), + MTK_FUNCTION(5, "DSP2_ICK") + ), + MTK_PIN( + PINCTRL_PIN(125, "DPIR3"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 121), + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "DPI0_R3"), + MTK_FUNCTION(2, "EINT121"), + MTK_FUNCTION(4, "CM2DAT_2X[7]") + ), + MTK_PIN( + PINCTRL_PIN(126, "DPIG1"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 111), + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "DPI0_G1"), + MTK_FUNCTION(2, "EINT111"), + MTK_FUNCTION(5, "DSP1_ICK") + ), + MTK_PIN( + PINCTRL_PIN(127, "DPIVSYNC"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 98), + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "DPI0_VSYNC"), + MTK_FUNCTION(2, "EINT98"), + MTK_FUNCTION(3, "I2SIN_CK"), + MTK_FUNCTION(4, "DAC_CK"), + MTK_FUNCTION(5, "PCM1_CK") + ), + MTK_PIN( + PINCTRL_PIN(128, "DPIHSYNC"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 99), + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "DPI0_HSYNC"), + MTK_FUNCTION(2, "EINT99"), + MTK_FUNCTION(3, "I2SIN_WS"), + MTK_FUNCTION(4, "DAC_WS"), + MTK_FUNCTION(5, "PCM1_WS"), + MTK_FUNCTION(6, "IRDA_RXD") + ), + MTK_PIN( + PINCTRL_PIN(129, "DPIB0"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 102), + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "DPI0_B0"), + MTK_FUNCTION(2, "EINT102"), + MTK_FUNCTION(4, "SCL0"), + MTK_FUNCTION(5, "DISP_PWM") + ), + MTK_PIN( + PINCTRL_PIN(130, "DPIB1"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 103), + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(1, "DPI0_B1"), + MTK_FUNCTION(2, "EINT103"), + MTK_FUNCTION(3, "CLKM0"), + MTK_FUNCTION(4, "SDA0"), + MTK_FUNCTION(5, "PWM1") + ), + MTK_PIN( + PINCTRL_PIN(131, "DPIB2"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 104), + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "DPI0_B2"), + MTK_FUNCTION(2, "EINT104"), + MTK_FUNCTION(3, "CLKM1"), + MTK_FUNCTION(4, "SCL1"), + MTK_FUNCTION(5, "PWM2") + ), + MTK_PIN( + PINCTRL_PIN(132, "DPIB3"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 105), + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "DPI0_B3"), + MTK_FUNCTION(2, "EINT105"), + MTK_FUNCTION(3, "CLKM2"), + MTK_FUNCTION(4, "SDA1"), + MTK_FUNCTION(5, "PWM3") + ), + MTK_PIN( + PINCTRL_PIN(133, "DPIB4"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 106), + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "DPI0_B4"), + MTK_FUNCTION(2, "EINT106"), + MTK_FUNCTION(3, "CLKM3"), + MTK_FUNCTION(4, "SCL2"), + MTK_FUNCTION(5, "PWM4") + ), + MTK_PIN( + PINCTRL_PIN(134, "DPIB5"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 107), + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "DPI0_B5"), + MTK_FUNCTION(2, "EINT107"), + MTK_FUNCTION(3, "CLKM4"), + MTK_FUNCTION(4, "SDA2"), + MTK_FUNCTION(5, "PWM5") + ), + MTK_PIN( + PINCTRL_PIN(135, "DPIB6"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 108), + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "DPI0_B6"), + MTK_FUNCTION(2, "EINT108"), + MTK_FUNCTION(3, "CLKM5"), + MTK_FUNCTION(4, "SCL3"), + MTK_FUNCTION(5, "PWM6") + ), + MTK_PIN( + PINCTRL_PIN(136, "DPIB7"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 109), + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "DPI0_B7"), + MTK_FUNCTION(2, "EINT109"), + MTK_FUNCTION(3, "CLKM6"), + MTK_FUNCTION(4, "SDA3"), + MTK_FUNCTION(5, "PWM7") + ), + MTK_PIN( + PINCTRL_PIN(137, "DPIG0"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 110), + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(1, "DPI0_G0"), + MTK_FUNCTION(2, "EINT110"), + MTK_FUNCTION(5, "DSP1_ID") + ), + MTK_PIN( + PINCTRL_PIN(138, "DPIG2"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 112), + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(1, "DPI0_G2"), + MTK_FUNCTION(2, "EINT112"), + MTK_FUNCTION(5, "DSP1_IMS") + ), + MTK_PIN( + PINCTRL_PIN(139, "DPIG3"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 113), + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "DPI0_G3"), + MTK_FUNCTION(2, "EINT113"), + MTK_FUNCTION(5, "DSP2_IMS") + ), + MTK_PIN( + PINCTRL_PIN(140, "DPIG6"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 116), + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(1, "DPI0_G6"), + MTK_FUNCTION(2, "EINT116"), + MTK_FUNCTION(4, "CM2DAT_2X[2]") + ), + MTK_PIN( + PINCTRL_PIN(141, "DPIG7"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 117), + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "DPI0_G7"), + MTK_FUNCTION(2, "EINT117"), + MTK_FUNCTION(4, "CM2DAT_2X[3]") + ), + MTK_PIN( + PINCTRL_PIN(142, "DPIR0"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 118), + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "DPI0_R0"), + MTK_FUNCTION(2, "EINT118"), + MTK_FUNCTION(4, "CM2DAT_2X[4]") + ), + MTK_PIN( + PINCTRL_PIN(143, "DPIR1"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 119), + MTK_FUNCTION(0, "GPIO143"), + MTK_FUNCTION(1, "DPI0_R1"), + MTK_FUNCTION(2, "EINT119"), + MTK_FUNCTION(4, "CM2DAT_2X[5]") + ), + MTK_PIN( + PINCTRL_PIN(144, "DPIR2"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 120), + MTK_FUNCTION(0, "GPIO144"), + MTK_FUNCTION(1, "DPI0_R2"), + MTK_FUNCTION(2, "EINT120"), + MTK_FUNCTION(4, "CM2DAT_2X[6]") + ), + MTK_PIN( + PINCTRL_PIN(145, "DPIR4"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 122), + MTK_FUNCTION(0, "GPIO145"), + MTK_FUNCTION(1, "DPI0_R4"), + MTK_FUNCTION(2, "EINT122"), + MTK_FUNCTION(4, "CM2DAT_2X[8]") + ), + MTK_PIN( + PINCTRL_PIN(146, "DPIR5"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 123), + MTK_FUNCTION(0, "GPIO146"), + MTK_FUNCTION(1, "DPI0_R5"), + MTK_FUNCTION(2, "EINT123"), + MTK_FUNCTION(4, "CM2DAT_2X[9]") + ), + MTK_PIN( + PINCTRL_PIN(147, "DPIR6"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 124), + MTK_FUNCTION(0, "GPIO147"), + MTK_FUNCTION(1, "DPI0_R6"), + MTK_FUNCTION(2, "EINT124"), + MTK_FUNCTION(4, "CM2VSYNC_2X") + ), + MTK_PIN( + PINCTRL_PIN(148, "DPIR7"), + NULL, "mt8135", + MTK_EINT_FUNCTION(2, 125), + MTK_FUNCTION(0, "GPIO148"), + MTK_FUNCTION(1, "DPI0_R7"), + MTK_FUNCTION(2, "EINT125"), + MTK_FUNCTION(4, "CM2HSYNC_2X") + ), + MTK_PIN( + PINCTRL_PIN(149, "TDN3/LVDS(TDN3)"), + "AA2", "mt8135", + MTK_EINT_FUNCTION(2, 36), + MTK_FUNCTION(0, "GPIO149"), + MTK_FUNCTION(2, "EINT36") + ), + MTK_PIN( + PINCTRL_PIN(150, "TDP3/LVDS(TDP3)"), + "AA1", "mt8135", + MTK_EINT_FUNCTION(2, 35), + MTK_FUNCTION(0, "GPIO150"), + MTK_FUNCTION(2, "EINT35") + ), + MTK_PIN( + PINCTRL_PIN(151, "TDN2/LVDS(TCN)"), + "Y2", "mt8135", + MTK_EINT_FUNCTION(2, 169), + MTK_FUNCTION(0, "GPIO151"), + MTK_FUNCTION(2, "EINT169") + ), + MTK_PIN( + PINCTRL_PIN(152, "TDP2/LVDS(TCP)"), + "Y1", "mt8135", + MTK_EINT_FUNCTION(2, 168), + MTK_FUNCTION(0, "GPIO152"), + MTK_FUNCTION(2, "EINT168") + ), + MTK_PIN( + PINCTRL_PIN(153, "TCN/LVDS(TDN2)"), + "W2", "mt8135", + MTK_EINT_FUNCTION(2, 163), + MTK_FUNCTION(0, "GPIO153"), + MTK_FUNCTION(2, "EINT163") + ), + MTK_PIN( + PINCTRL_PIN(154, "TCP/LVDS(TDP2)"), + "W1", "mt8135", + MTK_EINT_FUNCTION(2, 162), + MTK_FUNCTION(0, "GPIO154"), + MTK_FUNCTION(2, "EINT162") + ), + MTK_PIN( + PINCTRL_PIN(155, "TDN1/LVDS(TDN1)"), + "V3", "mt8135", + MTK_EINT_FUNCTION(2, 167), + MTK_FUNCTION(0, "GPIO155"), + MTK_FUNCTION(2, "EINT167") + ), + MTK_PIN( + PINCTRL_PIN(156, "TDP1/LVDS(TDP1)"), + "V2", "mt8135", + MTK_EINT_FUNCTION(2, 166), + MTK_FUNCTION(0, "GPIO156"), + MTK_FUNCTION(2, "EINT166") + ), + MTK_PIN( + PINCTRL_PIN(157, "TDN0/LVDS(TDN0)"), + "U3", "mt8135", + MTK_EINT_FUNCTION(2, 165), + MTK_FUNCTION(0, "GPIO157"), + MTK_FUNCTION(2, "EINT165") + ), + MTK_PIN( + PINCTRL_PIN(158, "TDP0/LVDS(TDP0)"), + "U2", "mt8135", + MTK_EINT_FUNCTION(2, 164), + MTK_FUNCTION(0, "GPIO158"), + MTK_FUNCTION(2, "EINT164") + ), + MTK_PIN( + PINCTRL_PIN(159, "RDN3"), + "N5", "mt8135", + MTK_EINT_FUNCTION(2, 18), + MTK_FUNCTION(0, "GPIO159"), + MTK_FUNCTION(2, "EINT18") + ), + MTK_PIN( + PINCTRL_PIN(160, "RDP3"), + "N4", "mt8135", + MTK_EINT_FUNCTION(2, 30), + MTK_FUNCTION(0, "GPIO160"), + MTK_FUNCTION(2, "EINT30") + ), + MTK_PIN( + PINCTRL_PIN(161, "RDN2"), + "T2", "mt8135", + MTK_EINT_FUNCTION(2, 31), + MTK_FUNCTION(0, "GPIO161"), + MTK_FUNCTION(2, "EINT31") + ), + MTK_PIN( + PINCTRL_PIN(162, "RDP2"), + "T3", "mt8135", + MTK_EINT_FUNCTION(2, 32), + MTK_FUNCTION(0, "GPIO162"), + MTK_FUNCTION(2, "EINT32") + ), + MTK_PIN( + PINCTRL_PIN(163, "RCN"), + "P2", "mt8135", + MTK_EINT_FUNCTION(2, 33), + MTK_FUNCTION(0, "GPIO163"), + MTK_FUNCTION(2, "EINT33") + ), + MTK_PIN( + PINCTRL_PIN(164, "RCP"), + "P3", "mt8135", + MTK_EINT_FUNCTION(2, 39), + MTK_FUNCTION(0, "GPIO164"), + MTK_FUNCTION(2, "EINT39") + ), + MTK_PIN( + PINCTRL_PIN(165, "RDN1"), + "R3", "mt8135", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO165") + ), + MTK_PIN( + PINCTRL_PIN(166, "RDP1"), + "R2", "mt8135", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO166") + ), + MTK_PIN( + PINCTRL_PIN(167, "RDN0"), + "N3", "mt8135", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO167") + ), + MTK_PIN( + PINCTRL_PIN(168, "RDP0"), + "N2", "mt8135", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO168") + ), + MTK_PIN( + PINCTRL_PIN(169, "RDN1_A"), + "M4", "mt8135", + MTK_EINT_FUNCTION(2, 175), + MTK_FUNCTION(0, "GPIO169"), + MTK_FUNCTION(1, "CMDAT6"), + MTK_FUNCTION(2, "EINT175") + ), + MTK_PIN( + PINCTRL_PIN(170, "RDP1_A"), + "M3", "mt8135", + MTK_EINT_FUNCTION(2, 174), + MTK_FUNCTION(0, "GPIO170"), + MTK_FUNCTION(1, "CMDAT7"), + MTK_FUNCTION(2, "EINT174") + ), + MTK_PIN( + PINCTRL_PIN(171, "RCN_A"), + "L3", "mt8135", + MTK_EINT_FUNCTION(2, 171), + MTK_FUNCTION(0, "GPIO171"), + MTK_FUNCTION(1, "CMDAT8"), + MTK_FUNCTION(2, "EINT171") + ), + MTK_PIN( + PINCTRL_PIN(172, "RCP_A"), + "L2", "mt8135", + MTK_EINT_FUNCTION(2, 170), + MTK_FUNCTION(0, "GPIO172"), + MTK_FUNCTION(1, "CMDAT9"), + MTK_FUNCTION(2, "EINT170") + ), + MTK_PIN( + PINCTRL_PIN(173, "RDN0_A"), + "M2", "mt8135", + MTK_EINT_FUNCTION(2, 173), + MTK_FUNCTION(0, "GPIO173"), + MTK_FUNCTION(1, "CMHSYNC"), + MTK_FUNCTION(2, "EINT173") + ), + MTK_PIN( + PINCTRL_PIN(174, "RDP0_A"), + "M1", "mt8135", + MTK_EINT_FUNCTION(2, 172), + MTK_FUNCTION(0, "GPIO174"), + MTK_FUNCTION(1, "CMVSYNC"), + MTK_FUNCTION(2, "EINT172") + ), + MTK_PIN( + PINCTRL_PIN(175, "RDN1_B"), + "H2", "mt8135", + MTK_EINT_FUNCTION(2, 181), + MTK_FUNCTION(0, "GPIO175"), + MTK_FUNCTION(1, "CMDAT2"), + MTK_FUNCTION(2, "EINT181"), + MTK_FUNCTION(3, "CMCSD2") + ), + MTK_PIN( + PINCTRL_PIN(176, "RDP1_B"), + "H1", "mt8135", + MTK_EINT_FUNCTION(2, 180), + MTK_FUNCTION(0, "GPIO176"), + MTK_FUNCTION(1, "CMDAT3"), + MTK_FUNCTION(2, "EINT180"), + MTK_FUNCTION(3, "CMCSD3") + ), + MTK_PIN( + PINCTRL_PIN(177, "RCN_B"), + "K3", "mt8135", + MTK_EINT_FUNCTION(2, 177), + MTK_FUNCTION(0, "GPIO177"), + MTK_FUNCTION(1, "CMDAT4"), + MTK_FUNCTION(2, "EINT177") + ), + MTK_PIN( + PINCTRL_PIN(178, "RCP_B"), + "K2", "mt8135", + MTK_EINT_FUNCTION(2, 176), + MTK_FUNCTION(0, "GPIO178"), + MTK_FUNCTION(1, "CMDAT5"), + MTK_FUNCTION(2, "EINT176") + ), + MTK_PIN( + PINCTRL_PIN(179, "RDN0_B"), + "J3", "mt8135", + MTK_EINT_FUNCTION(2, 179), + MTK_FUNCTION(0, "GPIO179"), + MTK_FUNCTION(1, "CMDAT0"), + MTK_FUNCTION(2, "EINT179"), + MTK_FUNCTION(3, "CMCSD0") + ), + MTK_PIN( + PINCTRL_PIN(180, "RDP0_B"), + "J2", "mt8135", + MTK_EINT_FUNCTION(2, 178), + MTK_FUNCTION(0, "GPIO180"), + MTK_FUNCTION(1, "CMDAT1"), + MTK_FUNCTION(2, "EINT178"), + MTK_FUNCTION(3, "CMCSD1") + ), + MTK_PIN( + PINCTRL_PIN(181, "CMPCLK"), + "K4", "mt8135", + MTK_EINT_FUNCTION(2, 182), + MTK_FUNCTION(0, "GPIO181"), + MTK_FUNCTION(1, "CMPCLK"), + MTK_FUNCTION(2, "EINT182"), + MTK_FUNCTION(3, "CMCSK"), + MTK_FUNCTION(4, "CM2MCLK_4X"), + MTK_FUNCTION(5, "TS_AUXADC_SEL[3]"), + MTK_FUNCTION(6, "VENC_TEST_CK"), + MTK_FUNCTION(7, "TESTA_OUT27") + ), + MTK_PIN( + PINCTRL_PIN(182, "CMMCLK"), + "J5", "mt8135", + MTK_EINT_FUNCTION(2, 183), + MTK_FUNCTION(0, "GPIO182"), + MTK_FUNCTION(1, "CMMCLK"), + MTK_FUNCTION(2, "EINT183"), + MTK_FUNCTION(5, "TS_AUXADC_SEL[2]"), + MTK_FUNCTION(7, "TESTA_OUT28") + ), + MTK_PIN( + PINCTRL_PIN(183, "CMRST"), + "J6", "mt8135", + MTK_EINT_FUNCTION(2, 185), + MTK_FUNCTION(0, "GPIO183"), + MTK_FUNCTION(1, "CMRST"), + MTK_FUNCTION(2, "EINT185"), + MTK_FUNCTION(5, "TS_AUXADC_SEL[1]"), + MTK_FUNCTION(7, "TESTA_OUT30") + ), + MTK_PIN( + PINCTRL_PIN(184, "CMPDN"), + "J4", "mt8135", + MTK_EINT_FUNCTION(2, 184), + MTK_FUNCTION(0, "GPIO184"), + MTK_FUNCTION(1, "CMPDN"), + MTK_FUNCTION(2, "EINT184"), + MTK_FUNCTION(5, "TS_AUXADC_SEL[0]"), + MTK_FUNCTION(7, "TESTA_OUT29") + ), + MTK_PIN( + PINCTRL_PIN(185, "CMFLASH"), + "G4", "mt8135", + MTK_EINT_FUNCTION(2, 186), + MTK_FUNCTION(0, "GPIO185"), + MTK_FUNCTION(1, "CMFLASH"), + MTK_FUNCTION(2, "EINT186"), + MTK_FUNCTION(3, "CM2MCLK_3X"), + MTK_FUNCTION(6, "MFG_TEST_CK_1"), + MTK_FUNCTION(7, "TESTA_OUT31") + ), + MTK_PIN( + PINCTRL_PIN(186, "MRG_I2S_PCM_CLK"), + "F5", "mt8135", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO186"), + MTK_FUNCTION(1, "MRG_I2S_PCM_CLK"), + MTK_FUNCTION(3, "I2SIN_CK"), + MTK_FUNCTION(4, "PCM0_CK"), + MTK_FUNCTION(5, "DSP2_ICK"), + MTK_FUNCTION(6, "IMG_TEST_CK"), + MTK_FUNCTION(7, "USB_SCL") + ), + MTK_PIN( + PINCTRL_PIN(187, "MRG_I2S_PCM_SYNC"), + "G6", "mt8135", + MTK_EINT_FUNCTION(2, 16), + MTK_FUNCTION(0, "GPIO187"), + MTK_FUNCTION(1, "MRG_I2S_PCM_SYNC"), + MTK_FUNCTION(2, "EINT16"), + MTK_FUNCTION(3, "I2SIN_WS"), + MTK_FUNCTION(4, "PCM0_WS"), + MTK_FUNCTION(6, "DISP_TEST_CK") + ), + MTK_PIN( + PINCTRL_PIN(188, "MRG_I2S_PCM_RX"), + "G3", "mt8135", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO188"), + MTK_FUNCTION(1, "MRG_I2S_PCM_RX"), + MTK_FUNCTION(3, "I2SIN_DAT"), + MTK_FUNCTION(4, "PCM0_DI"), + MTK_FUNCTION(5, "DSP2_ID"), + MTK_FUNCTION(6, "MFG_TEST_CK"), + MTK_FUNCTION(7, "USB_SDA") + ), + MTK_PIN( + PINCTRL_PIN(189, "MRG_I2S_PCM_TX"), + "G5", "mt8135", + MTK_EINT_FUNCTION(2, 17), + MTK_FUNCTION(0, "GPIO189"), + MTK_FUNCTION(1, "MRG_I2S_PCM_TX"), + MTK_FUNCTION(2, "EINT17"), + MTK_FUNCTION(3, "I2SOUT_DAT"), + MTK_FUNCTION(4, "PCM0_DO"), + MTK_FUNCTION(6, "VDEC_TEST_CK") + ), + MTK_PIN( + PINCTRL_PIN(190, "SRCLKENAI"), + "K5", "mt8135", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO190"), + MTK_FUNCTION(1, "SRCLKENAI") + ), + MTK_PIN( + PINCTRL_PIN(191, "URXD3"), + "C3", "mt8135", + MTK_EINT_FUNCTION(2, 87), + MTK_FUNCTION(0, "GPIO191"), + MTK_FUNCTION(1, "URXD3"), + MTK_FUNCTION(2, "EINT87"), + MTK_FUNCTION(3, "UTXD3"), + MTK_FUNCTION(5, "TS_AUX_ST"), + MTK_FUNCTION(6, "PWM4") + ), + MTK_PIN( + PINCTRL_PIN(192, "UTXD3"), + "B2", "mt8135", + MTK_EINT_FUNCTION(2, 86), + MTK_FUNCTION(0, "GPIO192"), + MTK_FUNCTION(1, "UTXD3"), + MTK_FUNCTION(2, "EINT86"), + MTK_FUNCTION(3, "URXD3"), + MTK_FUNCTION(5, "TS_AUX_CS_B"), + MTK_FUNCTION(6, "PWM3") + ), + MTK_PIN( + PINCTRL_PIN(193, "SDA2"), + "G2", "mt8135", + MTK_EINT_FUNCTION(2, 95), + MTK_FUNCTION(0, "GPIO193"), + MTK_FUNCTION(1, "SDA2"), + MTK_FUNCTION(2, "EINT95"), + MTK_FUNCTION(3, "CLKM5"), + MTK_FUNCTION(4, "PWM5"), + MTK_FUNCTION(5, "TS_AUX_PWDB") + ), + MTK_PIN( + PINCTRL_PIN(194, "SCL2"), + "F4", "mt8135", + MTK_EINT_FUNCTION(2, 94), + MTK_FUNCTION(0, "GPIO194"), + MTK_FUNCTION(1, "SCL2"), + MTK_FUNCTION(2, "EINT94"), + MTK_FUNCTION(3, "CLKM4"), + MTK_FUNCTION(4, "PWM4"), + MTK_FUNCTION(5, "TS_AUXADC_TEST_CK") + ), + MTK_PIN( + PINCTRL_PIN(195, "SDA1"), + "F2", "mt8135", + MTK_EINT_FUNCTION(2, 93), + MTK_FUNCTION(0, "GPIO195"), + MTK_FUNCTION(1, "SDA1"), + MTK_FUNCTION(2, "EINT93"), + MTK_FUNCTION(3, "CLKM3"), + MTK_FUNCTION(4, "PWM3"), + MTK_FUNCTION(5, "TS_AUX_SCLK_PWDB") + ), + MTK_PIN( + PINCTRL_PIN(196, "SCL1"), + "F3", "mt8135", + MTK_EINT_FUNCTION(2, 92), + MTK_FUNCTION(0, "GPIO196"), + MTK_FUNCTION(1, "SCL1"), + MTK_FUNCTION(2, "EINT92"), + MTK_FUNCTION(3, "CLKM2"), + MTK_FUNCTION(4, "PWM2"), + MTK_FUNCTION(5, "TS_AUX_DIN") + ), + MTK_PIN( + PINCTRL_PIN(197, "MSDC3_DAT2"), + "E1", "mt8135", + MTK_EINT_FUNCTION(2, 71), + MTK_FUNCTION(0, "GPIO197"), + MTK_FUNCTION(1, "MSDC3_DAT2"), + MTK_FUNCTION(2, "EINT71"), + MTK_FUNCTION(3, "SCL6"), + MTK_FUNCTION(4, "PWM5"), + MTK_FUNCTION(5, "CLKM4"), + MTK_FUNCTION(6, "MFG_TEST_CK_2") + ), + MTK_PIN( + PINCTRL_PIN(198, "MSDC3_DAT3"), + "C2", "mt8135", + MTK_EINT_FUNCTION(2, 72), + MTK_FUNCTION(0, "GPIO198"), + MTK_FUNCTION(1, "MSDC3_DAT3"), + MTK_FUNCTION(2, "EINT72"), + MTK_FUNCTION(3, "SDA6"), + MTK_FUNCTION(4, "PWM6"), + MTK_FUNCTION(5, "CLKM5"), + MTK_FUNCTION(6, "MFG_TEST_CK_3") + ), + MTK_PIN( + PINCTRL_PIN(199, "MSDC3_CMD"), + "D2", "mt8135", + MTK_EINT_FUNCTION(2, 68), + MTK_FUNCTION(0, "GPIO199"), + MTK_FUNCTION(1, "MSDC3_CMD"), + MTK_FUNCTION(2, "EINT68"), + MTK_FUNCTION(3, "SDA2"), + MTK_FUNCTION(4, "PWM2"), + MTK_FUNCTION(5, "CLKM1"), + MTK_FUNCTION(6, "MFG_TEST_CK_4") + ), + MTK_PIN( + PINCTRL_PIN(200, "MSDC3_CLK"), + "E2", "mt8135", + MTK_EINT_FUNCTION(2, 67), + MTK_FUNCTION(0, "GPIO200"), + MTK_FUNCTION(1, "MSDC3_CLK"), + MTK_FUNCTION(2, "EINT67"), + MTK_FUNCTION(3, "SCL2"), + MTK_FUNCTION(4, "PWM1"), + MTK_FUNCTION(5, "CLKM0") + ), + MTK_PIN( + PINCTRL_PIN(201, "MSDC3_DAT1"), + "D3", "mt8135", + MTK_EINT_FUNCTION(2, 70), + MTK_FUNCTION(0, "GPIO201"), + MTK_FUNCTION(1, "MSDC3_DAT1"), + MTK_FUNCTION(2, "EINT70"), + MTK_FUNCTION(3, "SDA3"), + MTK_FUNCTION(4, "PWM4"), + MTK_FUNCTION(5, "CLKM3") + ), + MTK_PIN( + PINCTRL_PIN(202, "MSDC3_DAT0"), + "E3", "mt8135", + MTK_EINT_FUNCTION(2, 69), + MTK_FUNCTION(0, "GPIO202"), + MTK_FUNCTION(1, "MSDC3_DAT0"), + MTK_FUNCTION(2, "EINT69"), + MTK_FUNCTION(3, "SCL3"), + MTK_FUNCTION(4, "PWM3"), + MTK_FUNCTION(5, "CLKM2") + ), +}; + +#endif /* __PINCTRL_MTK_MT8135_H */ diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8173.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8173.h new file mode 100644 index 000000000000..13e5b68bfe1b --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8173.h @@ -0,0 +1,1226 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __PINCTRL_MTK_MT8173_H +#define __PINCTRL_MTK_MT8173_H + +#include <linux/pinctrl/pinctrl.h> +#include "pinctrl-mtk-common.h" + +static const struct mtk_desc_pin mtk_pins_mt8173[] = { + MTK_PIN( + PINCTRL_PIN(0, "EINT0"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 0), + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "IRDA_PDN"), + MTK_FUNCTION(2, "I2S1_WS"), + MTK_FUNCTION(3, "AUD_SPDIF"), + MTK_FUNCTION(4, "UTXD0"), + MTK_FUNCTION(7, "DBG_MON_A_20_") + ), + MTK_PIN( + PINCTRL_PIN(1, "EINT1"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 1), + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "IRDA_RXD"), + MTK_FUNCTION(2, "I2S1_BCK"), + MTK_FUNCTION(3, "SDA5"), + MTK_FUNCTION(4, "URXD0"), + MTK_FUNCTION(7, "DBG_MON_A_21_") + ), + MTK_PIN( + PINCTRL_PIN(2, "EINT2"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 2), + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "IRDA_TXD"), + MTK_FUNCTION(2, "I2S1_MCK"), + MTK_FUNCTION(3, "SCL5"), + MTK_FUNCTION(4, "UTXD3"), + MTK_FUNCTION(7, "DBG_MON_A_22_") + ), + MTK_PIN( + PINCTRL_PIN(3, "EINT3"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 3), + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "DSI1_TE"), + MTK_FUNCTION(2, "I2S1_DO_1"), + MTK_FUNCTION(3, "SDA3"), + MTK_FUNCTION(4, "URXD3"), + MTK_FUNCTION(7, "DBG_MON_A_23_") + ), + MTK_PIN( + PINCTRL_PIN(4, "EINT4"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 4), + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "DISP_PWM1"), + MTK_FUNCTION(2, "I2S1_DO_2"), + MTK_FUNCTION(3, "SCL3"), + MTK_FUNCTION(4, "UCTS3"), + MTK_FUNCTION(6, "SFWP_B") + ), + MTK_PIN( + PINCTRL_PIN(5, "EINT5"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 5), + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "PCM1_CLK"), + MTK_FUNCTION(2, "I2S2_WS"), + MTK_FUNCTION(3, "SPI_CK_3_"), + MTK_FUNCTION(4, "URTS3"), + MTK_FUNCTION(5, "AP_MD32_JTAG_TMS"), + MTK_FUNCTION(6, "SFOUT") + ), + MTK_PIN( + PINCTRL_PIN(6, "EINT6"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 6), + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "PCM1_SYNC"), + MTK_FUNCTION(2, "I2S2_BCK"), + MTK_FUNCTION(3, "SPI_MI_3_"), + MTK_FUNCTION(5, "AP_MD32_JTAG_TCK"), + MTK_FUNCTION(6, "SFCS0") + ), + MTK_PIN( + PINCTRL_PIN(7, "EINT7"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 7), + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "PCM1_DI"), + MTK_FUNCTION(2, "I2S2_DI_1"), + MTK_FUNCTION(3, "SPI_MO_3_"), + MTK_FUNCTION(5, "AP_MD32_JTAG_TDI"), + MTK_FUNCTION(6, "SFHOLD") + ), + MTK_PIN( + PINCTRL_PIN(8, "EINT8"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 8), + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "PCM1_DO"), + MTK_FUNCTION(2, "I2S2_DI_2"), + MTK_FUNCTION(3, "SPI_CS_3_"), + MTK_FUNCTION(4, "AUD_SPDIF"), + MTK_FUNCTION(5, "AP_MD32_JTAG_TDO"), + MTK_FUNCTION(6, "SFIN") + ), + MTK_PIN( + PINCTRL_PIN(9, "EINT9"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 9), + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "USB_DRVVBUS_P0"), + MTK_FUNCTION(2, "I2S2_MCK"), + MTK_FUNCTION(4, "USB_DRVVBUS_P1"), + MTK_FUNCTION(5, "AP_MD32_JTAG_TRST"), + MTK_FUNCTION(6, "SFCK") + ), + MTK_PIN( + PINCTRL_PIN(10, "EINT10"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 10), + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "CLKM0"), + MTK_FUNCTION(2, "DSI1_TE"), + MTK_FUNCTION(3, "DISP_PWM1"), + MTK_FUNCTION(4, "PWM4"), + MTK_FUNCTION(5, "IRDA_RXD") + ), + MTK_PIN( + PINCTRL_PIN(11, "EINT11"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 11), + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "CLKM1"), + MTK_FUNCTION(2, "I2S3_WS"), + MTK_FUNCTION(3, "USB_DRVVBUS_P0"), + MTK_FUNCTION(4, "PWM5"), + MTK_FUNCTION(5, "IRDA_TXD"), + MTK_FUNCTION(6, "USB_DRVVBUS_P1"), + MTK_FUNCTION(7, "DBG_MON_B_30_") + ), + MTK_PIN( + PINCTRL_PIN(12, "EINT12"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 12), + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "CLKM2"), + MTK_FUNCTION(2, "I2S3_BCK"), + MTK_FUNCTION(3, "SRCLKENA0"), + MTK_FUNCTION(5, "I2S2_WS"), + MTK_FUNCTION(7, "DBG_MON_B_32_") + ), + MTK_PIN( + PINCTRL_PIN(13, "EINT13"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 13), + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "CLKM3"), + MTK_FUNCTION(2, "I2S3_MCK"), + MTK_FUNCTION(3, "SRCLKENA0"), + MTK_FUNCTION(5, "I2S2_BCK"), + MTK_FUNCTION(7, "DBG_MON_A_32_") + ), + MTK_PIN( + PINCTRL_PIN(14, "EINT14"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 14), + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "CMDAT0"), + MTK_FUNCTION(2, "CMCSD0"), + MTK_FUNCTION(4, "CLKM2"), + MTK_FUNCTION(7, "DBG_MON_B_6_") + ), + MTK_PIN( + PINCTRL_PIN(15, "EINT15"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 15), + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "CMDAT1"), + MTK_FUNCTION(2, "CMCSD1"), + MTK_FUNCTION(3, "CMFLASH"), + MTK_FUNCTION(4, "CLKM3"), + MTK_FUNCTION(7, "DBG_MON_B_29_") + ), + MTK_PIN( + PINCTRL_PIN(16, "IDDIG"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 16), + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "IDDIG"), + MTK_FUNCTION(2, "CMFLASH"), + MTK_FUNCTION(4, "PWM5") + ), + MTK_PIN( + PINCTRL_PIN(17, "WATCHDOG"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 17), + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "WATCHDOG_AO") + ), + MTK_PIN( + PINCTRL_PIN(18, "CEC"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 18), + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "CEC") + ), + MTK_PIN( + PINCTRL_PIN(19, "HDMISCK"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 19), + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "HDMISCK"), + MTK_FUNCTION(2, "HDCP_SCL") + ), + MTK_PIN( + PINCTRL_PIN(20, "HDMISD"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 20), + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "HDMISD"), + MTK_FUNCTION(2, "HDCP_SDA") + ), + MTK_PIN( + PINCTRL_PIN(21, "HTPLG"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 21), + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "HTPLG") + ), + MTK_PIN( + PINCTRL_PIN(22, "MSDC3_DAT0"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 22), + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "MSDC3_DAT0") + ), + MTK_PIN( + PINCTRL_PIN(23, "MSDC3_DAT1"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 23), + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "MSDC3_DAT1") + ), + MTK_PIN( + PINCTRL_PIN(24, "MSDC3_DAT2"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 24), + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "MSDC3_DAT2") + ), + MTK_PIN( + PINCTRL_PIN(25, "MSDC3_DAT3"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 25), + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "MSDC3_DAT3") + ), + MTK_PIN( + PINCTRL_PIN(26, "MSDC3_CLK"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 26), + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "MSDC3_CLK") + ), + MTK_PIN( + PINCTRL_PIN(27, "MSDC3_CMD"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 27), + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "MSDC3_CMD") + ), + MTK_PIN( + PINCTRL_PIN(28, "MSDC3_DSL"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 28), + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "MSDC3_DSL") + ), + MTK_PIN( + PINCTRL_PIN(29, "UCTS2"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 29), + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "UCTS2") + ), + MTK_PIN( + PINCTRL_PIN(30, "URTS2"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 30), + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "URTS2") + ), + MTK_PIN( + PINCTRL_PIN(31, "URXD2"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 31), + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "URXD2"), + MTK_FUNCTION(2, "UTXD2") + ), + MTK_PIN( + PINCTRL_PIN(32, "UTXD2"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 32), + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "UTXD2"), + MTK_FUNCTION(2, "URXD2") + ), + MTK_PIN( + PINCTRL_PIN(33, "DAICLK"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 33), + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, " MRG_CLK"), + MTK_FUNCTION(2, "PCM0_CLK") + ), + MTK_PIN( + PINCTRL_PIN(34, "DAIPCMIN"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 34), + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, " MRG_DI"), + MTK_FUNCTION(2, "PCM0_DI") + ), + MTK_PIN( + PINCTRL_PIN(35, "DAIPCMOUT"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 35), + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, " MRG_DO"), + MTK_FUNCTION(2, "PCM0_DO") + ), + MTK_PIN( + PINCTRL_PIN(36, "DAISYNC"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 36), + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, " MRG_SYNC"), + MTK_FUNCTION(2, "PCM0_SYNC") + ), + MTK_PIN( + PINCTRL_PIN(37, "EINT16"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 37), + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "USB_DRVVBUS_P0"), + MTK_FUNCTION(2, "USB_DRVVBUS_P1"), + MTK_FUNCTION(3, "PWM0"), + MTK_FUNCTION(4, "PWM1"), + MTK_FUNCTION(5, "PWM2"), + MTK_FUNCTION(6, "CLKM0") + ), + MTK_PIN( + PINCTRL_PIN(38, "CONN_RST"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 38), + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "USB_DRVVBUS_P0"), + MTK_FUNCTION(2, "USB_DRVVBUS_P1"), + MTK_FUNCTION(6, "CLKM1") + ), + MTK_PIN( + PINCTRL_PIN(39, "CM2MCLK"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 39), + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "CM2MCLK"), + MTK_FUNCTION(2, "CMCSD0"), + MTK_FUNCTION(7, "DBG_MON_A_17_") + ), + MTK_PIN( + PINCTRL_PIN(40, "CMPCLK"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 40), + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "CMPCLK"), + MTK_FUNCTION(2, "CMCSK"), + MTK_FUNCTION(3, "CMCSD2"), + MTK_FUNCTION(7, "DBG_MON_A_18_") + ), + MTK_PIN( + PINCTRL_PIN(41, "CMMCLK"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 41), + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "CMMCLK"), + MTK_FUNCTION(7, "DBG_MON_A_19_") + ), + MTK_PIN( + PINCTRL_PIN(42, "DSI_TE"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 42), + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "DSI_TE") + ), + MTK_PIN( + PINCTRL_PIN(43, "SDA2"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 43), + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "SDA2") + ), + MTK_PIN( + PINCTRL_PIN(44, "SCL2"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 44), + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "SCL2") + ), + MTK_PIN( + PINCTRL_PIN(45, "SDA0"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 45), + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "SDA0") + ), + MTK_PIN( + PINCTRL_PIN(46, "SCL0"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 46), + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "SCL0") + ), + MTK_PIN( + PINCTRL_PIN(47, "RDN0_A"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 47), + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "CMDAT2") + ), + MTK_PIN( + PINCTRL_PIN(48, "RDP0_A"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 48), + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "CMDAT3") + ), + MTK_PIN( + PINCTRL_PIN(49, "RDN1_A"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 49), + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "CMDAT4") + ), + MTK_PIN( + PINCTRL_PIN(50, "RDP1_A"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 50), + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "CMDAT5") + ), + MTK_PIN( + PINCTRL_PIN(51, "RCN_A"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 51), + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "CMDAT6") + ), + MTK_PIN( + PINCTRL_PIN(52, "RCP_A"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 52), + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "CMDAT7") + ), + MTK_PIN( + PINCTRL_PIN(53, "RDN2_A"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 53), + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "CMDAT8"), + MTK_FUNCTION(2, "CMCSD3") + ), + MTK_PIN( + PINCTRL_PIN(54, "RDP2_A"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 54), + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "CMDAT9"), + MTK_FUNCTION(2, "CMCSD2") + ), + MTK_PIN( + PINCTRL_PIN(55, "RDN3_A"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 55), + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "CMHSYNC"), + MTK_FUNCTION(2, "CMCSD1") + ), + MTK_PIN( + PINCTRL_PIN(56, "RDP3_A"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 56), + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "CMVSYNC"), + MTK_FUNCTION(2, "CMCSD0") + ), + MTK_PIN( + PINCTRL_PIN(57, "MSDC0_DAT0"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 57), + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "MSDC0_DAT0"), + MTK_FUNCTION(2, "I2S1_WS"), + MTK_FUNCTION(7, "DBG_MON_B_7_") + ), + MTK_PIN( + PINCTRL_PIN(58, "MSDC0_DAT1"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 58), + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "MSDC0_DAT1"), + MTK_FUNCTION(2, "I2S1_BCK"), + MTK_FUNCTION(7, "DBG_MON_B_8_") + ), + MTK_PIN( + PINCTRL_PIN(59, "MSDC0_DAT2"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 59), + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "MSDC0_DAT2"), + MTK_FUNCTION(2, "I2S1_MCK"), + MTK_FUNCTION(7, "DBG_MON_B_9_") + ), + MTK_PIN( + PINCTRL_PIN(60, "MSDC0_DAT3"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 60), + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "MSDC0_DAT3"), + MTK_FUNCTION(2, "I2S1_DO_1"), + MTK_FUNCTION(7, "DBG_MON_B_10_") + ), + MTK_PIN( + PINCTRL_PIN(61, "MSDC0_DAT4"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 61), + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "MSDC0_DAT4"), + MTK_FUNCTION(2, "I2S1_DO_2"), + MTK_FUNCTION(7, "DBG_MON_B_11_") + ), + MTK_PIN( + PINCTRL_PIN(62, "MSDC0_DAT5"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 62), + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "MSDC0_DAT5"), + MTK_FUNCTION(2, "I2S2_WS"), + MTK_FUNCTION(7, "DBG_MON_B_12_") + ), + MTK_PIN( + PINCTRL_PIN(63, "MSDC0_DAT6"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 63), + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "MSDC0_DAT6"), + MTK_FUNCTION(2, "I2S2_BCK"), + MTK_FUNCTION(7, "DBG_MON_B_13_") + ), + MTK_PIN( + PINCTRL_PIN(64, "MSDC0_DAT7"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 64), + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "MSDC0_DAT7"), + MTK_FUNCTION(2, "I2S2_DI_1"), + MTK_FUNCTION(7, "DBG_MON_B_14_") + ), + MTK_PIN( + PINCTRL_PIN(65, "MSDC0_CLK"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 65), + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "MSDC0_CLK"), + MTK_FUNCTION(7, "DBG_MON_B_16_") + ), + MTK_PIN( + PINCTRL_PIN(66, "MSDC0_CMD"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 66), + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "MSDC0_CMD"), + MTK_FUNCTION(2, "I2S2_DI_2"), + MTK_FUNCTION(7, "DBG_MON_B_15_") + ), + MTK_PIN( + PINCTRL_PIN(67, "MSDC0_DSL"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 67), + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "MSDC0_DSL"), + MTK_FUNCTION(7, "DBG_MON_B_17_") + ), + MTK_PIN( + PINCTRL_PIN(68, "MSDC0_RST_"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 68), + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "MSDC0_RSTB"), + MTK_FUNCTION(2, "I2S2_MCK"), + MTK_FUNCTION(7, "DBG_MON_B_18_") + ), + MTK_PIN( + PINCTRL_PIN(69, "SPI_CK"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 69), + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "SPI_CK_0_"), + MTK_FUNCTION(2, "I2S3_DO_1"), + MTK_FUNCTION(3, "PWM0"), + MTK_FUNCTION(4, "PWM5"), + MTK_FUNCTION(5, "I2S2_MCK"), + MTK_FUNCTION(7, "DBG_MON_B_19_") + ), + MTK_PIN( + PINCTRL_PIN(70, "SPI_MI"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 70), + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "SPI_MI_0_"), + MTK_FUNCTION(2, "I2S3_DO_2"), + MTK_FUNCTION(3, "PWM1"), + MTK_FUNCTION(4, "SPI_MO_0_"), + MTK_FUNCTION(5, "I2S2_DI_1"), + MTK_FUNCTION(6, "DSI1_TE"), + MTK_FUNCTION(7, "DBG_MON_B_20_") + ), + MTK_PIN( + PINCTRL_PIN(71, "SPI_MO"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 71), + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "SPI_MO_0_"), + MTK_FUNCTION(2, "I2S3_DO_3"), + MTK_FUNCTION(3, "PWM2"), + MTK_FUNCTION(4, "SPI_MI_0_"), + MTK_FUNCTION(5, "I2S2_DI_2"), + MTK_FUNCTION(7, "DBG_MON_B_21_") + ), + MTK_PIN( + PINCTRL_PIN(72, "SPI_CS"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 72), + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "SPI_CS_0_"), + MTK_FUNCTION(2, "I2S3_DO_4"), + MTK_FUNCTION(3, "PWM3"), + MTK_FUNCTION(4, "PWM6"), + MTK_FUNCTION(5, "DISP_PWM1"), + MTK_FUNCTION(7, "DBG_MON_B_22_") + ), + MTK_PIN( + PINCTRL_PIN(73, "MSDC1_DAT0"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 73), + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(7, "DBG_MON_B_24_") + ), + MTK_PIN( + PINCTRL_PIN(74, "MSDC1_DAT1"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 74), + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(7, "DBG_MON_B_25_") + ), + MTK_PIN( + PINCTRL_PIN(75, "MSDC1_DAT2"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 75), + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(7, "DBG_MON_B_26_") + ), + MTK_PIN( + PINCTRL_PIN(76, "MSDC1_DAT3"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 76), + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "MSDC1_DAT3"), + MTK_FUNCTION(7, "DBG_MON_B_27_") + ), + MTK_PIN( + PINCTRL_PIN(77, "MSDC1_CLK"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 77), + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(7, "DBG_MON_B_28_") + ), + MTK_PIN( + PINCTRL_PIN(78, "MSDC1_CMD"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 78), + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "MSDC1_CMD"), + MTK_FUNCTION(7, "DBG_MON_B_23_") + ), + MTK_PIN( + PINCTRL_PIN(79, "PWRAP_SPI0_MI"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 79), + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "PWRAP_SPIMI"), + MTK_FUNCTION(2, "PWRAP_SPIMO") + ), + MTK_PIN( + PINCTRL_PIN(80, "PWRAP_SPI0_MO"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 80), + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "PWRAP_SPIMO"), + MTK_FUNCTION(2, "PWRAP_SPIMI") + ), + MTK_PIN( + PINCTRL_PIN(81, "PWRAP_SPI0_CK"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 81), + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "PWRAP_SPICK") + ), + MTK_PIN( + PINCTRL_PIN(82, "PWRAP_SPI0_CSN"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 82), + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "PWRAP_SPICS") + ), + MTK_PIN( + PINCTRL_PIN(83, "AUD_CLK_MOSI"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 83), + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "AUD_CLK_MOSI") + ), + MTK_PIN( + PINCTRL_PIN(84, "AUD_DAT_MISO"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 84), + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "AUD_DAT_MISO"), + MTK_FUNCTION(2, "AUD_DAT_MOSI") + ), + MTK_PIN( + PINCTRL_PIN(85, "AUD_DAT_MOSI"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 85), + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "AUD_DAT_MOSI"), + MTK_FUNCTION(2, "AUD_DAT_MISO") + ), + MTK_PIN( + PINCTRL_PIN(86, "RTC32K_CK"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 86), + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "RTC32K_CK") + ), + MTK_PIN( + PINCTRL_PIN(87, "DISP_PWM0"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 87), + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "DISP_PWM0"), + MTK_FUNCTION(2, "DISP_PWM1"), + MTK_FUNCTION(7, "DBG_MON_B_31_") + ), + MTK_PIN( + PINCTRL_PIN(88, "SRCLKENAI"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 88), + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "SRCLKENAI") + ), + MTK_PIN( + PINCTRL_PIN(89, "SRCLKENAI2"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 89), + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "SRCLKENAI2") + ), + MTK_PIN( + PINCTRL_PIN(90, "SRCLKENA0"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 90), + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "SRCLKENA0") + ), + MTK_PIN( + PINCTRL_PIN(91, "SRCLKENA1"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 91), + MTK_FUNCTION(0, "GPIO91"), + MTK_FUNCTION(1, "SRCLKENA1") + ), + MTK_PIN( + PINCTRL_PIN(92, "PCM_CLK"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 92), + MTK_FUNCTION(0, "GPIO92"), + MTK_FUNCTION(1, "PCM1_CLK"), + MTK_FUNCTION(2, "I2S0_BCK"), + MTK_FUNCTION(7, "DBG_MON_A_24_") + ), + MTK_PIN( + PINCTRL_PIN(93, "PCM_SYNC"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 93), + MTK_FUNCTION(0, "GPIO93"), + MTK_FUNCTION(1, "PCM1_SYNC"), + MTK_FUNCTION(2, "I2S0_WS"), + MTK_FUNCTION(7, "DBG_MON_A_25_") + ), + MTK_PIN( + PINCTRL_PIN(94, "PCM_RX"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 94), + MTK_FUNCTION(0, "GPIO94"), + MTK_FUNCTION(1, "PCM1_DI"), + MTK_FUNCTION(2, "I2S0_DI"), + MTK_FUNCTION(7, "DBG_MON_A_26_") + ), + MTK_PIN( + PINCTRL_PIN(95, "PCM_TX"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 95), + MTK_FUNCTION(0, "GPIO95"), + MTK_FUNCTION(1, "PCM1_DO"), + MTK_FUNCTION(2, "I2S0_DO"), + MTK_FUNCTION(7, "DBG_MON_A_27_") + ), + MTK_PIN( + PINCTRL_PIN(96, "URXD1"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 96), + MTK_FUNCTION(0, "GPIO96"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "UTXD1"), + MTK_FUNCTION(7, "DBG_MON_A_28_") + ), + MTK_PIN( + PINCTRL_PIN(97, "UTXD1"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 97), + MTK_FUNCTION(0, "GPIO97"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "URXD1"), + MTK_FUNCTION(7, "DBG_MON_A_29_") + ), + MTK_PIN( + PINCTRL_PIN(98, "URTS1"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 98), + MTK_FUNCTION(0, "GPIO98"), + MTK_FUNCTION(1, "URTS1"), + MTK_FUNCTION(2, "UCTS1"), + MTK_FUNCTION(7, "DBG_MON_A_30_") + ), + MTK_PIN( + PINCTRL_PIN(99, "UCTS1"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 99), + MTK_FUNCTION(0, "GPIO99"), + MTK_FUNCTION(1, "UCTS1"), + MTK_FUNCTION(2, "URTS1"), + MTK_FUNCTION(7, "DBG_MON_A_31_") + ), + MTK_PIN( + PINCTRL_PIN(100, "MSDC2_DAT0"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 100), + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "MSDC2_DAT0"), + MTK_FUNCTION(3, "USB_DRVVBUS_P0"), + MTK_FUNCTION(4, "SDA5"), + MTK_FUNCTION(5, "USB_DRVVBUS_P1"), + MTK_FUNCTION(7, "DBG_MON_B_0_") + ), + MTK_PIN( + PINCTRL_PIN(101, "MSDC2_DAT1"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 101), + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "MSDC2_DAT1"), + MTK_FUNCTION(3, "AUD_SPDIF"), + MTK_FUNCTION(4, "SCL5"), + MTK_FUNCTION(7, "DBG_MON_B_1_") + ), + MTK_PIN( + PINCTRL_PIN(102, "MSDC2_DAT2"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 102), + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "MSDC2_DAT2"), + MTK_FUNCTION(3, "UTXD0"), + MTK_FUNCTION(5, "PWM0"), + MTK_FUNCTION(6, "SPI_CK_1_"), + MTK_FUNCTION(7, "DBG_MON_B_2_") + ), + MTK_PIN( + PINCTRL_PIN(103, "MSDC2_DAT3"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 103), + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "MSDC2_DAT3"), + MTK_FUNCTION(3, "URXD0"), + MTK_FUNCTION(5, "PWM1"), + MTK_FUNCTION(6, "SPI_MI_1_"), + MTK_FUNCTION(7, "DBG_MON_B_3_") + ), + MTK_PIN( + PINCTRL_PIN(104, "MSDC2_CLK"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 104), + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "MSDC2_CLK"), + MTK_FUNCTION(3, "UTXD3"), + MTK_FUNCTION(4, "SDA3"), + MTK_FUNCTION(5, "PWM2"), + MTK_FUNCTION(6, "SPI_MO_1_"), + MTK_FUNCTION(7, "DBG_MON_B_4_") + ), + MTK_PIN( + PINCTRL_PIN(105, "MSDC2_CMD"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 105), + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "MSDC2_CMD"), + MTK_FUNCTION(3, "URXD3"), + MTK_FUNCTION(4, "SCL3"), + MTK_FUNCTION(5, "PWM3"), + MTK_FUNCTION(6, "SPI_CS_1_"), + MTK_FUNCTION(7, "DBG_MON_B_5_") + ), + MTK_PIN( + PINCTRL_PIN(106, "SDA3"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 106), + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "SDA3") + ), + MTK_PIN( + PINCTRL_PIN(107, "SCL3"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 107), + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "SCL3") + ), + MTK_PIN( + PINCTRL_PIN(108, "JTMS"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 108), + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "JTMS"), + MTK_FUNCTION(2, " MFG_JTAG_TMS"), + MTK_FUNCTION(5, "AP_MD32_JTAG_TMS"), + MTK_FUNCTION(6, "DFD_TMS") + ), + MTK_PIN( + PINCTRL_PIN(109, "JTCK"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 109), + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(1, "JTCK"), + MTK_FUNCTION(2, " MFG_JTAG_TCK"), + MTK_FUNCTION(5, "AP_MD32_JTAG_TCK"), + MTK_FUNCTION(6, "DFD_TCK") + ), + MTK_PIN( + PINCTRL_PIN(110, "JTDI"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 110), + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "JTDI"), + MTK_FUNCTION(2, " MFG_JTAG_TDI"), + MTK_FUNCTION(5, "AP_MD32_JTAG_TDI"), + MTK_FUNCTION(6, "DFD_TDI") + ), + MTK_PIN( + PINCTRL_PIN(111, "JTDO"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 111), + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "JTDO"), + MTK_FUNCTION(2, "MFG_JTAG_TDO"), + MTK_FUNCTION(5, "AP_MD32_JTAG_TDO"), + MTK_FUNCTION(6, "DFD_TDO") + ), + MTK_PIN( + PINCTRL_PIN(112, "JTRST_B"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 112), + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "JTRST_B"), + MTK_FUNCTION(2, " MFG_JTAG_TRSTN"), + MTK_FUNCTION(5, "AP_MD32_JTAG_TRST"), + MTK_FUNCTION(6, "DFD_NTRST") + ), + MTK_PIN( + PINCTRL_PIN(113, "URXD0"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 113), + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "URXD0"), + MTK_FUNCTION(2, "UTXD0"), + MTK_FUNCTION(6, "I2S2_WS"), + MTK_FUNCTION(7, "DBG_MON_A_0_") + ), + MTK_PIN( + PINCTRL_PIN(114, "UTXD0"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 114), + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "UTXD0"), + MTK_FUNCTION(2, "URXD0"), + MTK_FUNCTION(6, "I2S2_BCK"), + MTK_FUNCTION(7, "DBG_MON_A_1_") + ), + MTK_PIN( + PINCTRL_PIN(115, "URTS0"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 115), + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "URTS0"), + MTK_FUNCTION(2, "UCTS0"), + MTK_FUNCTION(6, "I2S2_MCK"), + MTK_FUNCTION(7, "DBG_MON_A_2_") + ), + MTK_PIN( + PINCTRL_PIN(116, "UCTS0"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 116), + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "UCTS0"), + MTK_FUNCTION(2, "URTS0"), + MTK_FUNCTION(6, "I2S2_DI_1"), + MTK_FUNCTION(7, "DBG_MON_A_3_") + ), + MTK_PIN( + PINCTRL_PIN(117, "URXD3"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 117), + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "URXD3"), + MTK_FUNCTION(2, "UTXD3"), + MTK_FUNCTION(7, "DBG_MON_A_9_") + ), + MTK_PIN( + PINCTRL_PIN(118, "UTXD3"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 118), + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "UTXD3"), + MTK_FUNCTION(2, "URXD3"), + MTK_FUNCTION(7, "DBG_MON_A_10_") + ), + MTK_PIN( + PINCTRL_PIN(119, "KPROW0"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 119), + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "KROW0"), + MTK_FUNCTION(7, "DBG_MON_A_11_") + ), + MTK_PIN( + PINCTRL_PIN(120, "KPROW1"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 120), + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "KROW1"), + MTK_FUNCTION(3, "PWM6"), + MTK_FUNCTION(7, "DBG_MON_A_12_") + ), + MTK_PIN( + PINCTRL_PIN(121, "KPROW2"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 121), + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "KROW2"), + MTK_FUNCTION(2, "IRDA_PDN"), + MTK_FUNCTION(3, "USB_DRVVBUS_P0"), + MTK_FUNCTION(4, "PWM4"), + MTK_FUNCTION(5, "USB_DRVVBUS_P1"), + MTK_FUNCTION(7, "DBG_MON_A_13_") + ), + MTK_PIN( + PINCTRL_PIN(122, "KPCOL0"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 122), + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "KCOL0"), + MTK_FUNCTION(7, "DBG_MON_A_14_") + ), + MTK_PIN( + PINCTRL_PIN(123, "KPCOL1"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 123), + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "KCOL1"), + MTK_FUNCTION(2, "IRDA_RXD"), + MTK_FUNCTION(3, "PWM5"), + MTK_FUNCTION(7, "DBG_MON_A_15_") + ), + MTK_PIN( + PINCTRL_PIN(124, "KPCOL2"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 124), + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "KCOL2"), + MTK_FUNCTION(2, "IRDA_TXD"), + MTK_FUNCTION(3, "USB_DRVVBUS_P0"), + MTK_FUNCTION(4, "PWM3"), + MTK_FUNCTION(5, "USB_DRVVBUS_P1"), + MTK_FUNCTION(7, "DBG_MON_A_16_") + ), + MTK_PIN( + PINCTRL_PIN(125, "SDA1"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 125), + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "SDA1") + ), + MTK_PIN( + PINCTRL_PIN(126, "SCL1"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 126), + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "SCL1") + ), + MTK_PIN( + PINCTRL_PIN(127, "LCM_RST"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 127), + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "LCM_RST") + ), + MTK_PIN( + PINCTRL_PIN(128, "I2S0_LRCK"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 128), + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "I2S0_WS"), + MTK_FUNCTION(2, "I2S1_WS"), + MTK_FUNCTION(3, "I2S2_WS"), + MTK_FUNCTION(5, "SPI_CK_2_"), + MTK_FUNCTION(7, "DBG_MON_A_4_") + ), + MTK_PIN( + PINCTRL_PIN(129, "I2S0_BCK"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 129), + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "I2S0_BCK"), + MTK_FUNCTION(2, "I2S1_BCK"), + MTK_FUNCTION(3, "I2S2_BCK"), + MTK_FUNCTION(5, "SPI_MI_2_"), + MTK_FUNCTION(7, "DBG_MON_A_5_") + ), + MTK_PIN( + PINCTRL_PIN(130, "I2S0_MCK"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 130), + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(1, "I2S0_MCK"), + MTK_FUNCTION(2, "I2S1_MCK"), + MTK_FUNCTION(3, "I2S2_MCK"), + MTK_FUNCTION(5, "SPI_MO_2_"), + MTK_FUNCTION(7, "DBG_MON_A_6_") + ), + MTK_PIN( + PINCTRL_PIN(131, "I2S0_DATA0"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 131), + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "I2S0_DO"), + MTK_FUNCTION(2, "I2S1_DO_1"), + MTK_FUNCTION(3, "I2S2_DI_1"), + MTK_FUNCTION(5, "SPI_CS_2_"), + MTK_FUNCTION(7, "DBG_MON_A_7_") + ), + MTK_PIN( + PINCTRL_PIN(132, "I2S0_DATA1"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 132), + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "I2S0_DI"), + MTK_FUNCTION(2, "I2S1_DO_2"), + MTK_FUNCTION(3, "I2S2_DI_2"), + MTK_FUNCTION(7, "DBG_MON_A_8_") + ), + MTK_PIN( + PINCTRL_PIN(133, "SDA4"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 133), + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "SDA4") + ), + MTK_PIN( + PINCTRL_PIN(134, "SCL4"), + NULL, "mt8173", + MTK_EINT_FUNCTION(0, 134), + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "SCL4") + ), +}; + +#endif /* __PINCTRL_MTK_MT8173_H */ diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile index eafc216067a4..c751d22fdf29 100644 --- a/drivers/pinctrl/meson/Makefile +++ b/drivers/pinctrl/meson/Makefile @@ -1,2 +1,2 @@ -obj-y += pinctrl-meson8.o +obj-y += pinctrl-meson8.o pinctrl-meson8b.o obj-y += pinctrl-meson.o diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index a2bf49ce16e7..edcd140e0899 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -13,8 +13,9 @@ /* * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO, - * BOOT,CARD for meson6 and X,Y,DV,H,Z,AO,BOOT,CARD for meson8) and - * each bank has a variable number of pins. + * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and + * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a + * variable number of pins. * * The AO bank is special because it belongs to the Always-On power * domain which can't be powered off; the bank also uses a set of @@ -544,6 +545,10 @@ static const struct of_device_id meson_pinctrl_dt_match[] = { .compatible = "amlogic,meson8-pinctrl", .data = &meson8_pinctrl_data, }, + { + .compatible = "amlogic,meson8b-pinctrl", + .data = &meson8b_pinctrl_data, + }, { }, }; MODULE_DEVICE_TABLE(of, meson_pinctrl_dt_match); diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h index bfea8adc7953..0fe7d53849ce 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.h +++ b/drivers/pinctrl/meson/pinctrl-meson.h @@ -155,6 +155,8 @@ struct meson_pinctrl { struct meson_domain *domains; }; +#define PIN(x, b) (b + x) + #define GROUP(grp, r, b) \ { \ .name = #grp, \ @@ -165,10 +167,10 @@ struct meson_pinctrl { .domain = 0, \ } -#define GPIO_GROUP(gpio) \ +#define GPIO_GROUP(gpio, b) \ { \ .name = #gpio, \ - .pins = (const unsigned int[]){ PIN_ ## gpio}, \ + .pins = (const unsigned int[]){ PIN(gpio, b) }, \ .num_pins = 1, \ .is_gpio = true, \ } @@ -204,6 +206,7 @@ struct meson_pinctrl { }, \ } -#define MESON_PIN(x) PINCTRL_PIN(PIN_ ## x, #x) +#define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x) extern struct meson_pinctrl_data meson8_pinctrl_data; +extern struct meson_pinctrl_data meson8b_pinctrl_data; diff --git a/drivers/pinctrl/meson/pinctrl-meson8.c b/drivers/pinctrl/meson/pinctrl-meson8.c index f8aa3a281767..7b1cc91733ef 100644 --- a/drivers/pinctrl/meson/pinctrl-meson8.c +++ b/drivers/pinctrl/meson/pinctrl-meson8.c @@ -14,620 +14,482 @@ #include <dt-bindings/gpio/meson8-gpio.h> #include "pinctrl-meson.h" -#define AO_OFFSET 120 - -#define PIN_GPIOX_0 GPIOX_0 -#define PIN_GPIOX_1 GPIOX_1 -#define PIN_GPIOX_2 GPIOX_2 -#define PIN_GPIOX_3 GPIOX_3 -#define PIN_GPIOX_4 GPIOX_4 -#define PIN_GPIOX_5 GPIOX_5 -#define PIN_GPIOX_6 GPIOX_6 -#define PIN_GPIOX_7 GPIOX_7 -#define PIN_GPIOX_8 GPIOX_8 -#define PIN_GPIOX_9 GPIOX_9 -#define PIN_GPIOX_10 GPIOX_10 -#define PIN_GPIOX_11 GPIOX_11 -#define PIN_GPIOX_12 GPIOX_12 -#define PIN_GPIOX_13 GPIOX_13 -#define PIN_GPIOX_14 GPIOX_14 -#define PIN_GPIOX_15 GPIOX_15 -#define PIN_GPIOX_16 GPIOX_16 -#define PIN_GPIOX_17 GPIOX_17 -#define PIN_GPIOX_18 GPIOX_18 -#define PIN_GPIOX_19 GPIOX_19 -#define PIN_GPIOX_20 GPIOX_20 -#define PIN_GPIOX_21 GPIOX_21 -#define PIN_GPIOY_0 GPIOY_0 -#define PIN_GPIOY_1 GPIOY_1 -#define PIN_GPIOY_2 GPIOY_2 -#define PIN_GPIOY_3 GPIOY_3 -#define PIN_GPIOY_4 GPIOY_4 -#define PIN_GPIOY_5 GPIOY_5 -#define PIN_GPIOY_6 GPIOY_6 -#define PIN_GPIOY_7 GPIOY_7 -#define PIN_GPIOY_8 GPIOY_8 -#define PIN_GPIOY_9 GPIOY_9 -#define PIN_GPIOY_10 GPIOY_10 -#define PIN_GPIOY_11 GPIOY_11 -#define PIN_GPIOY_12 GPIOY_12 -#define PIN_GPIOY_13 GPIOY_13 -#define PIN_GPIOY_14 GPIOY_14 -#define PIN_GPIOY_15 GPIOY_15 -#define PIN_GPIOY_16 GPIOY_16 -#define PIN_GPIODV_0 GPIODV_0 -#define PIN_GPIODV_1 GPIODV_1 -#define PIN_GPIODV_2 GPIODV_2 -#define PIN_GPIODV_3 GPIODV_3 -#define PIN_GPIODV_4 GPIODV_4 -#define PIN_GPIODV_5 GPIODV_5 -#define PIN_GPIODV_6 GPIODV_6 -#define PIN_GPIODV_7 GPIODV_7 -#define PIN_GPIODV_8 GPIODV_8 -#define PIN_GPIODV_9 GPIODV_9 -#define PIN_GPIODV_10 GPIODV_10 -#define PIN_GPIODV_11 GPIODV_11 -#define PIN_GPIODV_12 GPIODV_12 -#define PIN_GPIODV_13 GPIODV_13 -#define PIN_GPIODV_14 GPIODV_14 -#define PIN_GPIODV_15 GPIODV_15 -#define PIN_GPIODV_16 GPIODV_16 -#define PIN_GPIODV_17 GPIODV_17 -#define PIN_GPIODV_18 GPIODV_18 -#define PIN_GPIODV_19 GPIODV_19 -#define PIN_GPIODV_20 GPIODV_20 -#define PIN_GPIODV_21 GPIODV_21 -#define PIN_GPIODV_22 GPIODV_22 -#define PIN_GPIODV_23 GPIODV_23 -#define PIN_GPIODV_24 GPIODV_24 -#define PIN_GPIODV_25 GPIODV_25 -#define PIN_GPIODV_26 GPIODV_26 -#define PIN_GPIODV_27 GPIODV_27 -#define PIN_GPIODV_28 GPIODV_28 -#define PIN_GPIODV_29 GPIODV_29 -#define PIN_GPIOH_0 GPIOH_0 -#define PIN_GPIOH_1 GPIOH_1 -#define PIN_GPIOH_2 GPIOH_2 -#define PIN_GPIOH_3 GPIOH_3 -#define PIN_GPIOH_4 GPIOH_4 -#define PIN_GPIOH_5 GPIOH_5 -#define PIN_GPIOH_6 GPIOH_6 -#define PIN_GPIOH_7 GPIOH_7 -#define PIN_GPIOH_8 GPIOH_8 -#define PIN_GPIOH_9 GPIOH_9 -#define PIN_GPIOZ_0 GPIOZ_0 -#define PIN_GPIOZ_1 GPIOZ_1 -#define PIN_GPIOZ_2 GPIOZ_2 -#define PIN_GPIOZ_3 GPIOZ_3 -#define PIN_GPIOZ_4 GPIOZ_4 -#define PIN_GPIOZ_5 GPIOZ_5 -#define PIN_GPIOZ_6 GPIOZ_6 -#define PIN_GPIOZ_7 GPIOZ_7 -#define PIN_GPIOZ_8 GPIOZ_8 -#define PIN_GPIOZ_9 GPIOZ_9 -#define PIN_GPIOZ_10 GPIOZ_10 -#define PIN_GPIOZ_11 GPIOZ_11 -#define PIN_GPIOZ_12 GPIOZ_12 -#define PIN_GPIOZ_13 GPIOZ_13 -#define PIN_GPIOZ_14 GPIOZ_14 -#define PIN_CARD_0 CARD_0 -#define PIN_CARD_1 CARD_1 -#define PIN_CARD_2 CARD_2 -#define PIN_CARD_3 CARD_3 -#define PIN_CARD_4 CARD_4 -#define PIN_CARD_5 CARD_5 -#define PIN_CARD_6 CARD_6 -#define PIN_BOOT_0 BOOT_0 -#define PIN_BOOT_1 BOOT_1 -#define PIN_BOOT_2 BOOT_2 -#define PIN_BOOT_3 BOOT_3 -#define PIN_BOOT_4 BOOT_4 -#define PIN_BOOT_5 BOOT_5 -#define PIN_BOOT_6 BOOT_6 -#define PIN_BOOT_7 BOOT_7 -#define PIN_BOOT_8 BOOT_8 -#define PIN_BOOT_9 BOOT_9 -#define PIN_BOOT_10 BOOT_10 -#define PIN_BOOT_11 BOOT_11 -#define PIN_BOOT_12 BOOT_12 -#define PIN_BOOT_13 BOOT_13 -#define PIN_BOOT_14 BOOT_14 -#define PIN_BOOT_15 BOOT_15 -#define PIN_BOOT_16 BOOT_16 -#define PIN_BOOT_17 BOOT_17 -#define PIN_BOOT_18 BOOT_18 - -#define PIN_GPIOAO_0 (AO_OFFSET + GPIOAO_0) -#define PIN_GPIOAO_1 (AO_OFFSET + GPIOAO_1) -#define PIN_GPIOAO_2 (AO_OFFSET + GPIOAO_2) -#define PIN_GPIOAO_3 (AO_OFFSET + GPIOAO_3) -#define PIN_GPIOAO_4 (AO_OFFSET + GPIOAO_4) -#define PIN_GPIOAO_5 (AO_OFFSET + GPIOAO_5) -#define PIN_GPIOAO_6 (AO_OFFSET + GPIOAO_6) -#define PIN_GPIOAO_7 (AO_OFFSET + GPIOAO_7) -#define PIN_GPIOAO_8 (AO_OFFSET + GPIOAO_8) -#define PIN_GPIOAO_9 (AO_OFFSET + GPIOAO_9) -#define PIN_GPIOAO_10 (AO_OFFSET + GPIOAO_10) -#define PIN_GPIOAO_11 (AO_OFFSET + GPIOAO_11) -#define PIN_GPIOAO_12 (AO_OFFSET + GPIOAO_12) -#define PIN_GPIOAO_13 (AO_OFFSET + GPIOAO_13) -#define PIN_GPIO_BSD_EN (AO_OFFSET + GPIO_BSD_EN) -#define PIN_GPIO_TEST_N (AO_OFFSET + GPIO_TEST_N) +#define AO_OFF 120 static const struct pinctrl_pin_desc meson8_pins[] = { - MESON_PIN(GPIOX_0), - MESON_PIN(GPIOX_1), - MESON_PIN(GPIOX_2), - MESON_PIN(GPIOX_3), - MESON_PIN(GPIOX_4), - MESON_PIN(GPIOX_5), - MESON_PIN(GPIOX_6), - MESON_PIN(GPIOX_7), - MESON_PIN(GPIOX_8), - MESON_PIN(GPIOX_9), - MESON_PIN(GPIOX_10), - MESON_PIN(GPIOX_11), - MESON_PIN(GPIOX_12), - MESON_PIN(GPIOX_13), - MESON_PIN(GPIOX_14), - MESON_PIN(GPIOX_15), - MESON_PIN(GPIOX_16), - MESON_PIN(GPIOX_17), - MESON_PIN(GPIOX_18), - MESON_PIN(GPIOX_19), - MESON_PIN(GPIOX_20), - MESON_PIN(GPIOX_21), - MESON_PIN(GPIOY_0), - MESON_PIN(GPIOY_1), - MESON_PIN(GPIOY_2), - MESON_PIN(GPIOY_3), - MESON_PIN(GPIOY_4), - MESON_PIN(GPIOY_5), - MESON_PIN(GPIOY_6), - MESON_PIN(GPIOY_7), - MESON_PIN(GPIOY_8), - MESON_PIN(GPIOY_9), - MESON_PIN(GPIOY_10), - MESON_PIN(GPIOY_11), - MESON_PIN(GPIOY_12), - MESON_PIN(GPIOY_13), - MESON_PIN(GPIOY_14), - MESON_PIN(GPIOY_15), - MESON_PIN(GPIOY_16), - MESON_PIN(GPIODV_0), - MESON_PIN(GPIODV_1), - MESON_PIN(GPIODV_2), - MESON_PIN(GPIODV_3), - MESON_PIN(GPIODV_4), - MESON_PIN(GPIODV_5), - MESON_PIN(GPIODV_6), - MESON_PIN(GPIODV_7), - MESON_PIN(GPIODV_8), - MESON_PIN(GPIODV_9), - MESON_PIN(GPIODV_10), - MESON_PIN(GPIODV_11), - MESON_PIN(GPIODV_12), - MESON_PIN(GPIODV_13), - MESON_PIN(GPIODV_14), - MESON_PIN(GPIODV_15), - MESON_PIN(GPIODV_16), - MESON_PIN(GPIODV_17), - MESON_PIN(GPIODV_18), - MESON_PIN(GPIODV_19), - MESON_PIN(GPIODV_20), - MESON_PIN(GPIODV_21), - MESON_PIN(GPIODV_22), - MESON_PIN(GPIODV_23), - MESON_PIN(GPIODV_24), - MESON_PIN(GPIODV_25), - MESON_PIN(GPIODV_26), - MESON_PIN(GPIODV_27), - MESON_PIN(GPIODV_28), - MESON_PIN(GPIODV_29), - MESON_PIN(GPIOH_0), - MESON_PIN(GPIOH_1), - MESON_PIN(GPIOH_2), - MESON_PIN(GPIOH_3), - MESON_PIN(GPIOH_4), - MESON_PIN(GPIOH_5), - MESON_PIN(GPIOH_6), - MESON_PIN(GPIOH_7), - MESON_PIN(GPIOH_8), - MESON_PIN(GPIOH_9), - MESON_PIN(GPIOZ_0), - MESON_PIN(GPIOZ_1), - MESON_PIN(GPIOZ_2), - MESON_PIN(GPIOZ_3), - MESON_PIN(GPIOZ_4), - MESON_PIN(GPIOZ_5), - MESON_PIN(GPIOZ_6), - MESON_PIN(GPIOZ_7), - MESON_PIN(GPIOZ_8), - MESON_PIN(GPIOZ_9), - MESON_PIN(GPIOZ_10), - MESON_PIN(GPIOZ_11), - MESON_PIN(GPIOZ_12), - MESON_PIN(GPIOZ_13), - MESON_PIN(GPIOZ_14), - MESON_PIN(CARD_0), - MESON_PIN(CARD_1), - MESON_PIN(CARD_2), - MESON_PIN(CARD_3), - MESON_PIN(CARD_4), - MESON_PIN(CARD_5), - MESON_PIN(CARD_6), - MESON_PIN(BOOT_0), - MESON_PIN(BOOT_1), - MESON_PIN(BOOT_2), - MESON_PIN(BOOT_3), - MESON_PIN(BOOT_4), - MESON_PIN(BOOT_5), - MESON_PIN(BOOT_6), - MESON_PIN(BOOT_7), - MESON_PIN(BOOT_8), - MESON_PIN(BOOT_9), - MESON_PIN(BOOT_10), - MESON_PIN(BOOT_11), - MESON_PIN(BOOT_12), - MESON_PIN(BOOT_13), - MESON_PIN(BOOT_14), - MESON_PIN(BOOT_15), - MESON_PIN(BOOT_16), - MESON_PIN(BOOT_17), - MESON_PIN(BOOT_18), - MESON_PIN(GPIOAO_0), - MESON_PIN(GPIOAO_1), - MESON_PIN(GPIOAO_2), - MESON_PIN(GPIOAO_3), - MESON_PIN(GPIOAO_4), - MESON_PIN(GPIOAO_5), - MESON_PIN(GPIOAO_6), - MESON_PIN(GPIOAO_7), - MESON_PIN(GPIOAO_8), - MESON_PIN(GPIOAO_9), - MESON_PIN(GPIOAO_10), - MESON_PIN(GPIOAO_11), - MESON_PIN(GPIOAO_12), - MESON_PIN(GPIOAO_13), - MESON_PIN(GPIO_BSD_EN), - MESON_PIN(GPIO_TEST_N), + MESON_PIN(GPIOX_0, 0), + MESON_PIN(GPIOX_1, 0), + MESON_PIN(GPIOX_2, 0), + MESON_PIN(GPIOX_3, 0), + MESON_PIN(GPIOX_4, 0), + MESON_PIN(GPIOX_5, 0), + MESON_PIN(GPIOX_6, 0), + MESON_PIN(GPIOX_7, 0), + MESON_PIN(GPIOX_8, 0), + MESON_PIN(GPIOX_9, 0), + MESON_PIN(GPIOX_10, 0), + MESON_PIN(GPIOX_11, 0), + MESON_PIN(GPIOX_12, 0), + MESON_PIN(GPIOX_13, 0), + MESON_PIN(GPIOX_14, 0), + MESON_PIN(GPIOX_15, 0), + MESON_PIN(GPIOX_16, 0), + MESON_PIN(GPIOX_17, 0), + MESON_PIN(GPIOX_18, 0), + MESON_PIN(GPIOX_19, 0), + MESON_PIN(GPIOX_20, 0), + MESON_PIN(GPIOX_21, 0), + MESON_PIN(GPIOY_0, 0), + MESON_PIN(GPIOY_1, 0), + MESON_PIN(GPIOY_2, 0), + MESON_PIN(GPIOY_3, 0), + MESON_PIN(GPIOY_4, 0), + MESON_PIN(GPIOY_5, 0), + MESON_PIN(GPIOY_6, 0), + MESON_PIN(GPIOY_7, 0), + MESON_PIN(GPIOY_8, 0), + MESON_PIN(GPIOY_9, 0), + MESON_PIN(GPIOY_10, 0), + MESON_PIN(GPIOY_11, 0), + MESON_PIN(GPIOY_12, 0), + MESON_PIN(GPIOY_13, 0), + MESON_PIN(GPIOY_14, 0), + MESON_PIN(GPIOY_15, 0), + MESON_PIN(GPIOY_16, 0), + MESON_PIN(GPIODV_0, 0), + MESON_PIN(GPIODV_1, 0), + MESON_PIN(GPIODV_2, 0), + MESON_PIN(GPIODV_3, 0), + MESON_PIN(GPIODV_4, 0), + MESON_PIN(GPIODV_5, 0), + MESON_PIN(GPIODV_6, 0), + MESON_PIN(GPIODV_7, 0), + MESON_PIN(GPIODV_8, 0), + MESON_PIN(GPIODV_9, 0), + MESON_PIN(GPIODV_10, 0), + MESON_PIN(GPIODV_11, 0), + MESON_PIN(GPIODV_12, 0), + MESON_PIN(GPIODV_13, 0), + MESON_PIN(GPIODV_14, 0), + MESON_PIN(GPIODV_15, 0), + MESON_PIN(GPIODV_16, 0), + MESON_PIN(GPIODV_17, 0), + MESON_PIN(GPIODV_18, 0), + MESON_PIN(GPIODV_19, 0), + MESON_PIN(GPIODV_20, 0), + MESON_PIN(GPIODV_21, 0), + MESON_PIN(GPIODV_22, 0), + MESON_PIN(GPIODV_23, 0), + MESON_PIN(GPIODV_24, 0), + MESON_PIN(GPIODV_25, 0), + MESON_PIN(GPIODV_26, 0), + MESON_PIN(GPIODV_27, 0), + MESON_PIN(GPIODV_28, 0), + MESON_PIN(GPIODV_29, 0), + MESON_PIN(GPIOH_0, 0), + MESON_PIN(GPIOH_1, 0), + MESON_PIN(GPIOH_2, 0), + MESON_PIN(GPIOH_3, 0), + MESON_PIN(GPIOH_4, 0), + MESON_PIN(GPIOH_5, 0), + MESON_PIN(GPIOH_6, 0), + MESON_PIN(GPIOH_7, 0), + MESON_PIN(GPIOH_8, 0), + MESON_PIN(GPIOH_9, 0), + MESON_PIN(GPIOZ_0, 0), + MESON_PIN(GPIOZ_1, 0), + MESON_PIN(GPIOZ_2, 0), + MESON_PIN(GPIOZ_3, 0), + MESON_PIN(GPIOZ_4, 0), + MESON_PIN(GPIOZ_5, 0), + MESON_PIN(GPIOZ_6, 0), + MESON_PIN(GPIOZ_7, 0), + MESON_PIN(GPIOZ_8, 0), + MESON_PIN(GPIOZ_9, 0), + MESON_PIN(GPIOZ_10, 0), + MESON_PIN(GPIOZ_11, 0), + MESON_PIN(GPIOZ_12, 0), + MESON_PIN(GPIOZ_13, 0), + MESON_PIN(GPIOZ_14, 0), + MESON_PIN(CARD_0, 0), + MESON_PIN(CARD_1, 0), + MESON_PIN(CARD_2, 0), + MESON_PIN(CARD_3, 0), + MESON_PIN(CARD_4, 0), + MESON_PIN(CARD_5, 0), + MESON_PIN(CARD_6, 0), + MESON_PIN(BOOT_0, 0), + MESON_PIN(BOOT_1, 0), + MESON_PIN(BOOT_2, 0), + MESON_PIN(BOOT_3, 0), + MESON_PIN(BOOT_4, 0), + MESON_PIN(BOOT_5, 0), + MESON_PIN(BOOT_6, 0), + MESON_PIN(BOOT_7, 0), + MESON_PIN(BOOT_8, 0), + MESON_PIN(BOOT_9, 0), + MESON_PIN(BOOT_10, 0), + MESON_PIN(BOOT_11, 0), + MESON_PIN(BOOT_12, 0), + MESON_PIN(BOOT_13, 0), + MESON_PIN(BOOT_14, 0), + MESON_PIN(BOOT_15, 0), + MESON_PIN(BOOT_16, 0), + MESON_PIN(BOOT_17, 0), + MESON_PIN(BOOT_18, 0), + MESON_PIN(GPIOAO_0, AO_OFF), + MESON_PIN(GPIOAO_1, AO_OFF), + MESON_PIN(GPIOAO_2, AO_OFF), + MESON_PIN(GPIOAO_3, AO_OFF), + MESON_PIN(GPIOAO_4, AO_OFF), + MESON_PIN(GPIOAO_5, AO_OFF), + MESON_PIN(GPIOAO_6, AO_OFF), + MESON_PIN(GPIOAO_7, AO_OFF), + MESON_PIN(GPIOAO_8, AO_OFF), + MESON_PIN(GPIOAO_9, AO_OFF), + MESON_PIN(GPIOAO_10, AO_OFF), + MESON_PIN(GPIOAO_11, AO_OFF), + MESON_PIN(GPIOAO_12, AO_OFF), + MESON_PIN(GPIOAO_13, AO_OFF), + MESON_PIN(GPIO_BSD_EN, AO_OFF), + MESON_PIN(GPIO_TEST_N, AO_OFF), }; /* bank X */ -static const unsigned int sd_d0_a_pins[] = { PIN_GPIOX_0 }; -static const unsigned int sd_d1_a_pins[] = { PIN_GPIOX_1 }; -static const unsigned int sd_d2_a_pins[] = { PIN_GPIOX_2 }; -static const unsigned int sd_d3_a_pins[] = { PIN_GPIOX_3 }; -static const unsigned int sd_clk_a_pins[] = { PIN_GPIOX_8 }; -static const unsigned int sd_cmd_a_pins[] = { PIN_GPIOX_9 }; - -static const unsigned int sdxc_d0_a_pins[] = { PIN_GPIOX_0 }; -static const unsigned int sdxc_d13_a_pins[] = { PIN_GPIOX_1, PIN_GPIOX_2, - PIN_GPIOX_3 }; -static const unsigned int sdxc_d47_a_pins[] = { PIN_GPIOX_4, PIN_GPIOX_5, - PIN_GPIOX_6, PIN_GPIOX_7 }; -static const unsigned int sdxc_clk_a_pins[] = { PIN_GPIOX_8 }; -static const unsigned int sdxc_cmd_a_pins[] = { PIN_GPIOX_9 }; - -static const unsigned int pcm_out_a_pins[] = { PIN_GPIOX_4 }; -static const unsigned int pcm_in_a_pins[] = { PIN_GPIOX_5 }; -static const unsigned int pcm_fs_a_pins[] = { PIN_GPIOX_6 }; -static const unsigned int pcm_clk_a_pins[] = { PIN_GPIOX_7 }; - -static const unsigned int uart_tx_a0_pins[] = { PIN_GPIOX_4 }; -static const unsigned int uart_rx_a0_pins[] = { PIN_GPIOX_5 }; -static const unsigned int uart_cts_a0_pins[] = { PIN_GPIOX_6 }; -static const unsigned int uart_rts_a0_pins[] = { PIN_GPIOX_7 }; - -static const unsigned int uart_tx_a1_pins[] = { PIN_GPIOX_12 }; -static const unsigned int uart_rx_a1_pins[] = { PIN_GPIOX_13 }; -static const unsigned int uart_cts_a1_pins[] = { PIN_GPIOX_14 }; -static const unsigned int uart_rts_a1_pins[] = { PIN_GPIOX_15 }; - -static const unsigned int uart_tx_b0_pins[] = { PIN_GPIOX_16 }; -static const unsigned int uart_rx_b0_pins[] = { PIN_GPIOX_17 }; -static const unsigned int uart_cts_b0_pins[] = { PIN_GPIOX_18 }; -static const unsigned int uart_rts_b0_pins[] = { PIN_GPIOX_19 }; - -static const unsigned int iso7816_det_pins[] = { PIN_GPIOX_16 }; -static const unsigned int iso7816_reset_pins[] = { PIN_GPIOX_17 }; -static const unsigned int iso7816_clk_pins[] = { PIN_GPIOX_18 }; -static const unsigned int iso7816_data_pins[] = { PIN_GPIOX_19 }; - -static const unsigned int i2c_sda_d0_pins[] = { PIN_GPIOX_16 }; -static const unsigned int i2c_sck_d0_pins[] = { PIN_GPIOX_17 }; - -static const unsigned int xtal_32k_out_pins[] = { PIN_GPIOX_10 }; -static const unsigned int xtal_24m_out_pins[] = { PIN_GPIOX_11 }; +static const unsigned int sd_d0_a_pins[] = { PIN(GPIOX_0, 0) }; +static const unsigned int sd_d1_a_pins[] = { PIN(GPIOX_1, 0) }; +static const unsigned int sd_d2_a_pins[] = { PIN(GPIOX_2, 0) }; +static const unsigned int sd_d3_a_pins[] = { PIN(GPIOX_3, 0) }; +static const unsigned int sd_clk_a_pins[] = { PIN(GPIOX_8, 0) }; +static const unsigned int sd_cmd_a_pins[] = { PIN(GPIOX_9, 0) }; + +static const unsigned int sdxc_d0_a_pins[] = { PIN(GPIOX_0, 0) }; +static const unsigned int sdxc_d13_a_pins[] = { PIN(GPIOX_1, 0), PIN(GPIOX_2, 0), + PIN(GPIOX_3, 0) }; +static const unsigned int sdxc_d47_a_pins[] = { PIN(GPIOX_4, 0), PIN(GPIOX_5, 0), + PIN(GPIOX_6, 0), PIN(GPIOX_7, 0) }; +static const unsigned int sdxc_clk_a_pins[] = { PIN(GPIOX_8, 0) }; +static const unsigned int sdxc_cmd_a_pins[] = { PIN(GPIOX_9, 0) }; + +static const unsigned int pcm_out_a_pins[] = { PIN(GPIOX_4, 0) }; +static const unsigned int pcm_in_a_pins[] = { PIN(GPIOX_5, 0) }; +static const unsigned int pcm_fs_a_pins[] = { PIN(GPIOX_6, 0) }; +static const unsigned int pcm_clk_a_pins[] = { PIN(GPIOX_7, 0) }; + +static const unsigned int uart_tx_a0_pins[] = { PIN(GPIOX_4, 0) }; +static const unsigned int uart_rx_a0_pins[] = { PIN(GPIOX_5, 0) }; +static const unsigned int uart_cts_a0_pins[] = { PIN(GPIOX_6, 0) }; +static const unsigned int uart_rts_a0_pins[] = { PIN(GPIOX_7, 0) }; + +static const unsigned int uart_tx_a1_pins[] = { PIN(GPIOX_12, 0) }; +static const unsigned int uart_rx_a1_pins[] = { PIN(GPIOX_13, 0) }; +static const unsigned int uart_cts_a1_pins[] = { PIN(GPIOX_14, 0) }; +static const unsigned int uart_rts_a1_pins[] = { PIN(GPIOX_15, 0) }; + +static const unsigned int uart_tx_b0_pins[] = { PIN(GPIOX_16, 0) }; +static const unsigned int uart_rx_b0_pins[] = { PIN(GPIOX_17, 0) }; +static const unsigned int uart_cts_b0_pins[] = { PIN(GPIOX_18, 0) }; +static const unsigned int uart_rts_b0_pins[] = { PIN(GPIOX_19, 0) }; + +static const unsigned int iso7816_det_pins[] = { PIN(GPIOX_16, 0) }; +static const unsigned int iso7816_reset_pins[] = { PIN(GPIOX_17, 0) }; +static const unsigned int iso7816_clk_pins[] = { PIN(GPIOX_18, 0) }; +static const unsigned int iso7816_data_pins[] = { PIN(GPIOX_19, 0) }; + +static const unsigned int i2c_sda_d0_pins[] = { PIN(GPIOX_16, 0) }; +static const unsigned int i2c_sck_d0_pins[] = { PIN(GPIOX_17, 0) }; + +static const unsigned int xtal_32k_out_pins[] = { PIN(GPIOX_10, 0) }; +static const unsigned int xtal_24m_out_pins[] = { PIN(GPIOX_11, 0) }; /* bank Y */ -static const unsigned int uart_tx_c_pins[] = { PIN_GPIOY_0 }; -static const unsigned int uart_rx_c_pins[] = { PIN_GPIOY_1 }; -static const unsigned int uart_cts_c_pins[] = { PIN_GPIOY_2 }; -static const unsigned int uart_rts_c_pins[] = { PIN_GPIOY_3 }; +static const unsigned int uart_tx_c_pins[] = { PIN(GPIOY_0, 0) }; +static const unsigned int uart_rx_c_pins[] = { PIN(GPIOY_1, 0) }; +static const unsigned int uart_cts_c_pins[] = { PIN(GPIOY_2, 0) }; +static const unsigned int uart_rts_c_pins[] = { PIN(GPIOY_3, 0) }; -static const unsigned int pcm_out_b_pins[] = { PIN_GPIOY_4 }; -static const unsigned int pcm_in_b_pins[] = { PIN_GPIOY_5 }; -static const unsigned int pcm_fs_b_pins[] = { PIN_GPIOY_6 }; -static const unsigned int pcm_clk_b_pins[] = { PIN_GPIOY_7 }; +static const unsigned int pcm_out_b_pins[] = { PIN(GPIOY_4, 0) }; +static const unsigned int pcm_in_b_pins[] = { PIN(GPIOY_5, 0) }; +static const unsigned int pcm_fs_b_pins[] = { PIN(GPIOY_6, 0) }; +static const unsigned int pcm_clk_b_pins[] = { PIN(GPIOY_7, 0) }; -static const unsigned int i2c_sda_c0_pins[] = { PIN_GPIOY_0 }; -static const unsigned int i2c_sck_c0_pins[] = { PIN_GPIOY_1 }; +static const unsigned int i2c_sda_c0_pins[] = { PIN(GPIOY_0, 0) }; +static const unsigned int i2c_sck_c0_pins[] = { PIN(GPIOY_1, 0) }; /* bank DV */ -static const unsigned int dvin_rgb_pins[] = { PIN_GPIODV_0, PIN_GPIODV_1, - PIN_GPIODV_2, PIN_GPIODV_3, - PIN_GPIODV_4, PIN_GPIODV_5, - PIN_GPIODV_6, PIN_GPIODV_7, - PIN_GPIODV_8, PIN_GPIODV_9, - PIN_GPIODV_10, PIN_GPIODV_11, - PIN_GPIODV_12, PIN_GPIODV_13, - PIN_GPIODV_14, PIN_GPIODV_15, - PIN_GPIODV_16, PIN_GPIODV_17, - PIN_GPIODV_18, PIN_GPIODV_19, - PIN_GPIODV_20, PIN_GPIODV_21, - PIN_GPIODV_22, PIN_GPIODV_23 }; -static const unsigned int dvin_vs_pins[] = { PIN_GPIODV_24 }; -static const unsigned int dvin_hs_pins[] = { PIN_GPIODV_25 }; -static const unsigned int dvin_clk_pins[] = { PIN_GPIODV_26 }; -static const unsigned int dvin_de_pins[] = { PIN_GPIODV_27 }; - -static const unsigned int enc_0_pins[] = { PIN_GPIODV_0 }; -static const unsigned int enc_1_pins[] = { PIN_GPIODV_1 }; -static const unsigned int enc_2_pins[] = { PIN_GPIODV_2 }; -static const unsigned int enc_3_pins[] = { PIN_GPIODV_3 }; -static const unsigned int enc_4_pins[] = { PIN_GPIODV_4 }; -static const unsigned int enc_5_pins[] = { PIN_GPIODV_5 }; -static const unsigned int enc_6_pins[] = { PIN_GPIODV_6 }; -static const unsigned int enc_7_pins[] = { PIN_GPIODV_7 }; -static const unsigned int enc_8_pins[] = { PIN_GPIODV_8 }; -static const unsigned int enc_9_pins[] = { PIN_GPIODV_9 }; -static const unsigned int enc_10_pins[] = { PIN_GPIODV_10 }; -static const unsigned int enc_11_pins[] = { PIN_GPIODV_11 }; -static const unsigned int enc_12_pins[] = { PIN_GPIODV_12 }; -static const unsigned int enc_13_pins[] = { PIN_GPIODV_13 }; -static const unsigned int enc_14_pins[] = { PIN_GPIODV_14 }; -static const unsigned int enc_15_pins[] = { PIN_GPIODV_15 }; -static const unsigned int enc_16_pins[] = { PIN_GPIODV_16 }; -static const unsigned int enc_17_pins[] = { PIN_GPIODV_17 }; - -static const unsigned int uart_tx_b1_pins[] = { PIN_GPIODV_24 }; -static const unsigned int uart_rx_b1_pins[] = { PIN_GPIODV_25 }; -static const unsigned int uart_cts_b1_pins[] = { PIN_GPIODV_26 }; -static const unsigned int uart_rts_b1_pins[] = { PIN_GPIODV_27 }; - -static const unsigned int vga_vs_pins[] = { PIN_GPIODV_24 }; -static const unsigned int vga_hs_pins[] = { PIN_GPIODV_25 }; +static const unsigned int dvin_rgb_pins[] = { PIN(GPIODV_0, 0), PIN(GPIODV_1, 0), + PIN(GPIODV_2, 0), PIN(GPIODV_3, 0), + PIN(GPIODV_4, 0), PIN(GPIODV_5, 0), + PIN(GPIODV_6, 0), PIN(GPIODV_7, 0), + PIN(GPIODV_8, 0), PIN(GPIODV_9, 0), + PIN(GPIODV_10, 0), PIN(GPIODV_11, 0), + PIN(GPIODV_12, 0), PIN(GPIODV_13, 0), + PIN(GPIODV_14, 0), PIN(GPIODV_15, 0), + PIN(GPIODV_16, 0), PIN(GPIODV_17, 0), + PIN(GPIODV_18, 0), PIN(GPIODV_19, 0), + PIN(GPIODV_20, 0), PIN(GPIODV_21, 0), + PIN(GPIODV_22, 0), PIN(GPIODV_23, 0) }; +static const unsigned int dvin_vs_pins[] = { PIN(GPIODV_24, 0) }; +static const unsigned int dvin_hs_pins[] = { PIN(GPIODV_25, 0) }; +static const unsigned int dvin_clk_pins[] = { PIN(GPIODV_26, 0) }; +static const unsigned int dvin_de_pins[] = { PIN(GPIODV_27, 0) }; + +static const unsigned int enc_0_pins[] = { PIN(GPIODV_0, 0) }; +static const unsigned int enc_1_pins[] = { PIN(GPIODV_1, 0) }; +static const unsigned int enc_2_pins[] = { PIN(GPIODV_2, 0) }; +static const unsigned int enc_3_pins[] = { PIN(GPIODV_3, 0) }; +static const unsigned int enc_4_pins[] = { PIN(GPIODV_4, 0) }; +static const unsigned int enc_5_pins[] = { PIN(GPIODV_5, 0) }; +static const unsigned int enc_6_pins[] = { PIN(GPIODV_6, 0) }; +static const unsigned int enc_7_pins[] = { PIN(GPIODV_7, 0) }; +static const unsigned int enc_8_pins[] = { PIN(GPIODV_8, 0) }; +static const unsigned int enc_9_pins[] = { PIN(GPIODV_9, 0) }; +static const unsigned int enc_10_pins[] = { PIN(GPIODV_10, 0) }; +static const unsigned int enc_11_pins[] = { PIN(GPIODV_11, 0) }; +static const unsigned int enc_12_pins[] = { PIN(GPIODV_12, 0) }; +static const unsigned int enc_13_pins[] = { PIN(GPIODV_13, 0) }; +static const unsigned int enc_14_pins[] = { PIN(GPIODV_14, 0) }; +static const unsigned int enc_15_pins[] = { PIN(GPIODV_15, 0) }; +static const unsigned int enc_16_pins[] = { PIN(GPIODV_16, 0) }; +static const unsigned int enc_17_pins[] = { PIN(GPIODV_17, 0) }; + +static const unsigned int uart_tx_b1_pins[] = { PIN(GPIODV_24, 0) }; +static const unsigned int uart_rx_b1_pins[] = { PIN(GPIODV_25, 0) }; +static const unsigned int uart_cts_b1_pins[] = { PIN(GPIODV_26, 0) }; +static const unsigned int uart_rts_b1_pins[] = { PIN(GPIODV_27, 0) }; + +static const unsigned int vga_vs_pins[] = { PIN(GPIODV_24, 0) }; +static const unsigned int vga_hs_pins[] = { PIN(GPIODV_25, 0) }; /* bank H */ -static const unsigned int hdmi_hpd_pins[] = { PIN_GPIOH_0 }; -static const unsigned int hdmi_sda_pins[] = { PIN_GPIOH_1 }; -static const unsigned int hdmi_scl_pins[] = { PIN_GPIOH_2 }; -static const unsigned int hdmi_cec_pins[] = { PIN_GPIOH_3 }; +static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, 0) }; +static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, 0) }; +static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, 0) }; +static const unsigned int hdmi_cec_pins[] = { PIN(GPIOH_3, 0) }; -static const unsigned int spi_ss0_0_pins[] = { PIN_GPIOH_3 }; -static const unsigned int spi_miso_0_pins[] = { PIN_GPIOH_4 }; -static const unsigned int spi_mosi_0_pins[] = { PIN_GPIOH_5 }; -static const unsigned int spi_sclk_0_pins[] = { PIN_GPIOH_6 }; +static const unsigned int spi_ss0_0_pins[] = { PIN(GPIOH_3, 0) }; +static const unsigned int spi_miso_0_pins[] = { PIN(GPIOH_4, 0) }; +static const unsigned int spi_mosi_0_pins[] = { PIN(GPIOH_5, 0) }; +static const unsigned int spi_sclk_0_pins[] = { PIN(GPIOH_6, 0) }; -static const unsigned int i2c_sda_d1_pins[] = { PIN_GPIOH_7 }; -static const unsigned int i2c_sck_d1_pins[] = { PIN_GPIOH_8 }; +static const unsigned int i2c_sda_d1_pins[] = { PIN(GPIOH_7, 0) }; +static const unsigned int i2c_sck_d1_pins[] = { PIN(GPIOH_8, 0) }; /* bank Z */ -static const unsigned int spi_ss0_1_pins[] = { PIN_GPIOZ_9 }; -static const unsigned int spi_ss1_1_pins[] = { PIN_GPIOZ_10 }; -static const unsigned int spi_sclk_1_pins[] = { PIN_GPIOZ_11 }; -static const unsigned int spi_mosi_1_pins[] = { PIN_GPIOZ_12 }; -static const unsigned int spi_miso_1_pins[] = { PIN_GPIOZ_13 }; -static const unsigned int spi_ss2_1_pins[] = { PIN_GPIOZ_14 }; - -static const unsigned int eth_tx_clk_50m_pins[] = { PIN_GPIOZ_4 }; -static const unsigned int eth_tx_en_pins[] = { PIN_GPIOZ_5 }; -static const unsigned int eth_txd1_pins[] = { PIN_GPIOZ_6 }; -static const unsigned int eth_txd0_pins[] = { PIN_GPIOZ_7 }; -static const unsigned int eth_rx_clk_in_pins[] = { PIN_GPIOZ_8 }; -static const unsigned int eth_rx_dv_pins[] = { PIN_GPIOZ_9 }; -static const unsigned int eth_rxd1_pins[] = { PIN_GPIOZ_10 }; -static const unsigned int eth_rxd0_pins[] = { PIN_GPIOZ_11 }; -static const unsigned int eth_mdio_pins[] = { PIN_GPIOZ_12 }; -static const unsigned int eth_mdc_pins[] = { PIN_GPIOZ_13 }; - -static const unsigned int i2c_sda_a0_pins[] = { PIN_GPIOZ_0 }; -static const unsigned int i2c_sck_a0_pins[] = { PIN_GPIOZ_1 }; - -static const unsigned int i2c_sda_b_pins[] = { PIN_GPIOZ_2 }; -static const unsigned int i2c_sck_b_pins[] = { PIN_GPIOZ_3 }; - -static const unsigned int i2c_sda_c1_pins[] = { PIN_GPIOZ_4 }; -static const unsigned int i2c_sck_c1_pins[] = { PIN_GPIOZ_5 }; - -static const unsigned int i2c_sda_a1_pins[] = { PIN_GPIOZ_0 }; -static const unsigned int i2c_sck_a1_pins[] = { PIN_GPIOZ_1 }; - -static const unsigned int i2c_sda_a2_pins[] = { PIN_GPIOZ_0 }; -static const unsigned int i2c_sck_a2_pins[] = { PIN_GPIOZ_1 }; +static const unsigned int spi_ss0_1_pins[] = { PIN(GPIOZ_9, 0) }; +static const unsigned int spi_ss1_1_pins[] = { PIN(GPIOZ_10, 0) }; +static const unsigned int spi_sclk_1_pins[] = { PIN(GPIOZ_11, 0) }; +static const unsigned int spi_mosi_1_pins[] = { PIN(GPIOZ_12, 0) }; +static const unsigned int spi_miso_1_pins[] = { PIN(GPIOZ_13, 0) }; +static const unsigned int spi_ss2_1_pins[] = { PIN(GPIOZ_14, 0) }; + +static const unsigned int eth_tx_clk_50m_pins[] = { PIN(GPIOZ_4, 0) }; +static const unsigned int eth_tx_en_pins[] = { PIN(GPIOZ_5, 0) }; +static const unsigned int eth_txd1_pins[] = { PIN(GPIOZ_6, 0) }; +static const unsigned int eth_txd0_pins[] = { PIN(GPIOZ_7, 0) }; +static const unsigned int eth_rx_clk_in_pins[] = { PIN(GPIOZ_8, 0) }; +static const unsigned int eth_rx_dv_pins[] = { PIN(GPIOZ_9, 0) }; +static const unsigned int eth_rxd1_pins[] = { PIN(GPIOZ_10, 0) }; +static const unsigned int eth_rxd0_pins[] = { PIN(GPIOZ_11, 0) }; +static const unsigned int eth_mdio_pins[] = { PIN(GPIOZ_12, 0) }; +static const unsigned int eth_mdc_pins[] = { PIN(GPIOZ_13, 0) }; + +static const unsigned int i2c_sda_a0_pins[] = { PIN(GPIOZ_0, 0) }; +static const unsigned int i2c_sck_a0_pins[] = { PIN(GPIOZ_1, 0) }; + +static const unsigned int i2c_sda_b_pins[] = { PIN(GPIOZ_2, 0) }; +static const unsigned int i2c_sck_b_pins[] = { PIN(GPIOZ_3, 0) }; + +static const unsigned int i2c_sda_c1_pins[] = { PIN(GPIOZ_4, 0) }; +static const unsigned int i2c_sck_c1_pins[] = { PIN(GPIOZ_5, 0) }; + +static const unsigned int i2c_sda_a1_pins[] = { PIN(GPIOZ_0, 0) }; +static const unsigned int i2c_sck_a1_pins[] = { PIN(GPIOZ_1, 0) }; + +static const unsigned int i2c_sda_a2_pins[] = { PIN(GPIOZ_0, 0) }; +static const unsigned int i2c_sck_a2_pins[] = { PIN(GPIOZ_1, 0) }; /* bank BOOT */ -static const unsigned int sd_d0_c_pins[] = { PIN_BOOT_0 }; -static const unsigned int sd_d1_c_pins[] = { PIN_BOOT_1 }; -static const unsigned int sd_d2_c_pins[] = { PIN_BOOT_2 }; -static const unsigned int sd_d3_c_pins[] = { PIN_BOOT_3 }; -static const unsigned int sd_cmd_c_pins[] = { PIN_BOOT_16 }; -static const unsigned int sd_clk_c_pins[] = { PIN_BOOT_17 }; - -static const unsigned int sdxc_d0_c_pins[] = { PIN_BOOT_0}; -static const unsigned int sdxc_d13_c_pins[] = { PIN_BOOT_1, PIN_BOOT_2, - PIN_BOOT_3 }; -static const unsigned int sdxc_d47_c_pins[] = { PIN_BOOT_4, PIN_BOOT_5, - PIN_BOOT_6, PIN_BOOT_7 }; -static const unsigned int sdxc_cmd_c_pins[] = { PIN_BOOT_16 }; -static const unsigned int sdxc_clk_c_pins[] = { PIN_BOOT_17 }; - -static const unsigned int nand_io_pins[] = { PIN_BOOT_0, PIN_BOOT_1, - PIN_BOOT_2, PIN_BOOT_3, - PIN_BOOT_4, PIN_BOOT_5, - PIN_BOOT_6, PIN_BOOT_7 }; -static const unsigned int nand_io_ce0_pins[] = { PIN_BOOT_8 }; -static const unsigned int nand_io_ce1_pins[] = { PIN_BOOT_9 }; -static const unsigned int nand_io_rb0_pins[] = { PIN_BOOT_10 }; -static const unsigned int nand_ale_pins[] = { PIN_BOOT_11 }; -static const unsigned int nand_cle_pins[] = { PIN_BOOT_12 }; -static const unsigned int nand_wen_clk_pins[] = { PIN_BOOT_13 }; -static const unsigned int nand_ren_clk_pins[] = { PIN_BOOT_14 }; -static const unsigned int nand_dqs_pins[] = { PIN_BOOT_15 }; -static const unsigned int nand_ce2_pins[] = { PIN_BOOT_16 }; -static const unsigned int nand_ce3_pins[] = { PIN_BOOT_17 }; - -static const unsigned int nor_d_pins[] = { PIN_BOOT_11 }; -static const unsigned int nor_q_pins[] = { PIN_BOOT_12 }; -static const unsigned int nor_c_pins[] = { PIN_BOOT_13 }; -static const unsigned int nor_cs_pins[] = { PIN_BOOT_18 }; +static const unsigned int sd_d0_c_pins[] = { PIN(BOOT_0, 0) }; +static const unsigned int sd_d1_c_pins[] = { PIN(BOOT_1, 0) }; +static const unsigned int sd_d2_c_pins[] = { PIN(BOOT_2, 0) }; +static const unsigned int sd_d3_c_pins[] = { PIN(BOOT_3, 0) }; +static const unsigned int sd_cmd_c_pins[] = { PIN(BOOT_16, 0) }; +static const unsigned int sd_clk_c_pins[] = { PIN(BOOT_17, 0) }; + +static const unsigned int sdxc_d0_c_pins[] = { PIN(BOOT_0, 0)}; +static const unsigned int sdxc_d13_c_pins[] = { PIN(BOOT_1, 0), PIN(BOOT_2, 0), + PIN(BOOT_3, 0) }; +static const unsigned int sdxc_d47_c_pins[] = { PIN(BOOT_4, 0), PIN(BOOT_5, 0), + PIN(BOOT_6, 0), PIN(BOOT_7, 0) }; +static const unsigned int sdxc_cmd_c_pins[] = { PIN(BOOT_16, 0) }; +static const unsigned int sdxc_clk_c_pins[] = { PIN(BOOT_17, 0) }; + +static const unsigned int nand_io_pins[] = { PIN(BOOT_0, 0), PIN(BOOT_1, 0), + PIN(BOOT_2, 0), PIN(BOOT_3, 0), + PIN(BOOT_4, 0), PIN(BOOT_5, 0), + PIN(BOOT_6, 0), PIN(BOOT_7, 0) }; +static const unsigned int nand_io_ce0_pins[] = { PIN(BOOT_8, 0) }; +static const unsigned int nand_io_ce1_pins[] = { PIN(BOOT_9, 0) }; +static const unsigned int nand_io_rb0_pins[] = { PIN(BOOT_10, 0) }; +static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, 0) }; +static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, 0) }; +static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, 0) }; +static const unsigned int nand_ren_clk_pins[] = { PIN(BOOT_14, 0) }; +static const unsigned int nand_dqs_pins[] = { PIN(BOOT_15, 0) }; +static const unsigned int nand_ce2_pins[] = { PIN(BOOT_16, 0) }; +static const unsigned int nand_ce3_pins[] = { PIN(BOOT_17, 0) }; + +static const unsigned int nor_d_pins[] = { PIN(BOOT_11, 0) }; +static const unsigned int nor_q_pins[] = { PIN(BOOT_12, 0) }; +static const unsigned int nor_c_pins[] = { PIN(BOOT_13, 0) }; +static const unsigned int nor_cs_pins[] = { PIN(BOOT_18, 0) }; /* bank CARD */ -static const unsigned int sd_d1_b_pins[] = { PIN_CARD_0 }; -static const unsigned int sd_d0_b_pins[] = { PIN_CARD_1 }; -static const unsigned int sd_clk_b_pins[] = { PIN_CARD_2 }; -static const unsigned int sd_cmd_b_pins[] = { PIN_CARD_3 }; -static const unsigned int sd_d3_b_pins[] = { PIN_CARD_4 }; -static const unsigned int sd_d2_b_pins[] = { PIN_CARD_5 }; - -static const unsigned int sdxc_d13_b_pins[] = { PIN_CARD_0, PIN_CARD_4, - PIN_CARD_5 }; -static const unsigned int sdxc_d0_b_pins[] = { PIN_CARD_1 }; -static const unsigned int sdxc_clk_b_pins[] = { PIN_CARD_2 }; -static const unsigned int sdxc_cmd_b_pins[] = { PIN_CARD_3 }; +static const unsigned int sd_d1_b_pins[] = { PIN(CARD_0, 0) }; +static const unsigned int sd_d0_b_pins[] = { PIN(CARD_1, 0) }; +static const unsigned int sd_clk_b_pins[] = { PIN(CARD_2, 0) }; +static const unsigned int sd_cmd_b_pins[] = { PIN(CARD_3, 0) }; +static const unsigned int sd_d3_b_pins[] = { PIN(CARD_4, 0) }; +static const unsigned int sd_d2_b_pins[] = { PIN(CARD_5, 0) }; + +static const unsigned int sdxc_d13_b_pins[] = { PIN(CARD_0, 0), PIN(CARD_4, 0), + PIN(CARD_5, 0) }; +static const unsigned int sdxc_d0_b_pins[] = { PIN(CARD_1, 0) }; +static const unsigned int sdxc_clk_b_pins[] = { PIN(CARD_2, 0) }; +static const unsigned int sdxc_cmd_b_pins[] = { PIN(CARD_3, 0) }; /* bank AO */ -static const unsigned int uart_tx_ao_a_pins[] = { PIN_GPIOAO_0 }; -static const unsigned int uart_rx_ao_a_pins[] = { PIN_GPIOAO_1 }; -static const unsigned int uart_cts_ao_a_pins[] = { PIN_GPIOAO_2 }; -static const unsigned int uart_rts_ao_a_pins[] = { PIN_GPIOAO_3 }; +static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, AO_OFF) }; +static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, AO_OFF) }; +static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, AO_OFF) }; +static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, AO_OFF) }; -static const unsigned int remote_input_pins[] = { PIN_GPIOAO_7 }; +static const unsigned int remote_input_pins[] = { PIN(GPIOAO_7, AO_OFF) }; -static const unsigned int i2c_slave_sck_ao_pins[] = { PIN_GPIOAO_4 }; -static const unsigned int i2c_slave_sda_ao_pins[] = { PIN_GPIOAO_5 }; +static const unsigned int i2c_slave_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) }; +static const unsigned int i2c_slave_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) }; -static const unsigned int uart_tx_ao_b0_pins[] = { PIN_GPIOAO_0 }; -static const unsigned int uart_rx_ao_b0_pins[] = { PIN_GPIOAO_1 }; +static const unsigned int uart_tx_ao_b0_pins[] = { PIN(GPIOAO_0, AO_OFF) }; +static const unsigned int uart_rx_ao_b0_pins[] = { PIN(GPIOAO_1, AO_OFF) }; -static const unsigned int uart_tx_ao_b1_pins[] = { PIN_GPIOAO_4 }; -static const unsigned int uart_rx_ao_b1_pins[] = { PIN_GPIOAO_5 }; +static const unsigned int uart_tx_ao_b1_pins[] = { PIN(GPIOAO_4, AO_OFF) }; +static const unsigned int uart_rx_ao_b1_pins[] = { PIN(GPIOAO_5, AO_OFF) }; -static const unsigned int i2c_mst_sck_ao_pins[] = { PIN_GPIOAO_4 }; -static const unsigned int i2c_mst_sda_ao_pins[] = { PIN_GPIOAO_5 }; +static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) }; +static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) }; static struct meson_pmx_group meson8_groups[] = { - GPIO_GROUP(GPIOX_0), - GPIO_GROUP(GPIOX_1), - GPIO_GROUP(GPIOX_2), - GPIO_GROUP(GPIOX_3), - GPIO_GROUP(GPIOX_4), - GPIO_GROUP(GPIOX_5), - GPIO_GROUP(GPIOX_6), - GPIO_GROUP(GPIOX_7), - GPIO_GROUP(GPIOX_8), - GPIO_GROUP(GPIOX_9), - GPIO_GROUP(GPIOX_10), - GPIO_GROUP(GPIOX_11), - GPIO_GROUP(GPIOX_12), - GPIO_GROUP(GPIOX_13), - GPIO_GROUP(GPIOX_14), - GPIO_GROUP(GPIOX_15), - GPIO_GROUP(GPIOX_16), - GPIO_GROUP(GPIOX_17), - GPIO_GROUP(GPIOX_18), - GPIO_GROUP(GPIOX_19), - GPIO_GROUP(GPIOX_20), - GPIO_GROUP(GPIOX_21), - GPIO_GROUP(GPIOY_0), - GPIO_GROUP(GPIOY_1), - GPIO_GROUP(GPIOY_2), - GPIO_GROUP(GPIOY_3), - GPIO_GROUP(GPIOY_4), - GPIO_GROUP(GPIOY_5), - GPIO_GROUP(GPIOY_6), - GPIO_GROUP(GPIOY_7), - GPIO_GROUP(GPIOY_8), - GPIO_GROUP(GPIOY_9), - GPIO_GROUP(GPIOY_10), - GPIO_GROUP(GPIOY_11), - GPIO_GROUP(GPIOY_12), - GPIO_GROUP(GPIOY_13), - GPIO_GROUP(GPIOY_14), - GPIO_GROUP(GPIOY_15), - GPIO_GROUP(GPIOY_16), - GPIO_GROUP(GPIODV_0), - GPIO_GROUP(GPIODV_1), - GPIO_GROUP(GPIODV_2), - GPIO_GROUP(GPIODV_3), - GPIO_GROUP(GPIODV_4), - GPIO_GROUP(GPIODV_5), - GPIO_GROUP(GPIODV_6), - GPIO_GROUP(GPIODV_7), - GPIO_GROUP(GPIODV_8), - GPIO_GROUP(GPIODV_9), - GPIO_GROUP(GPIODV_10), - GPIO_GROUP(GPIODV_11), - GPIO_GROUP(GPIODV_12), - GPIO_GROUP(GPIODV_13), - GPIO_GROUP(GPIODV_14), - GPIO_GROUP(GPIODV_15), - GPIO_GROUP(GPIODV_16), - GPIO_GROUP(GPIODV_17), - GPIO_GROUP(GPIODV_18), - GPIO_GROUP(GPIODV_19), - GPIO_GROUP(GPIODV_20), - GPIO_GROUP(GPIODV_21), - GPIO_GROUP(GPIODV_22), - GPIO_GROUP(GPIODV_23), - GPIO_GROUP(GPIODV_24), - GPIO_GROUP(GPIODV_25), - GPIO_GROUP(GPIODV_26), - GPIO_GROUP(GPIODV_27), - GPIO_GROUP(GPIODV_28), - GPIO_GROUP(GPIODV_29), - GPIO_GROUP(GPIOH_0), - GPIO_GROUP(GPIOH_1), - GPIO_GROUP(GPIOH_2), - GPIO_GROUP(GPIOH_3), - GPIO_GROUP(GPIOH_4), - GPIO_GROUP(GPIOH_5), - GPIO_GROUP(GPIOH_6), - GPIO_GROUP(GPIOH_7), - GPIO_GROUP(GPIOH_8), - GPIO_GROUP(GPIOH_9), - GPIO_GROUP(GPIOZ_0), - GPIO_GROUP(GPIOZ_1), - GPIO_GROUP(GPIOZ_2), - GPIO_GROUP(GPIOZ_3), - GPIO_GROUP(GPIOZ_4), - GPIO_GROUP(GPIOZ_5), - GPIO_GROUP(GPIOZ_6), - GPIO_GROUP(GPIOZ_7), - GPIO_GROUP(GPIOZ_8), - GPIO_GROUP(GPIOZ_9), - GPIO_GROUP(GPIOZ_10), - GPIO_GROUP(GPIOZ_11), - GPIO_GROUP(GPIOZ_12), - GPIO_GROUP(GPIOZ_13), - GPIO_GROUP(GPIOZ_14), - GPIO_GROUP(GPIOAO_0), - GPIO_GROUP(GPIOAO_1), - GPIO_GROUP(GPIOAO_2), - GPIO_GROUP(GPIOAO_3), - GPIO_GROUP(GPIOAO_4), - GPIO_GROUP(GPIOAO_5), - GPIO_GROUP(GPIOAO_6), - GPIO_GROUP(GPIOAO_7), - GPIO_GROUP(GPIOAO_8), - GPIO_GROUP(GPIOAO_9), - GPIO_GROUP(GPIOAO_10), - GPIO_GROUP(GPIOAO_11), - GPIO_GROUP(GPIOAO_12), - GPIO_GROUP(GPIOAO_13), - GPIO_GROUP(GPIO_BSD_EN), - GPIO_GROUP(GPIO_TEST_N), + GPIO_GROUP(GPIOX_0, 0), + GPIO_GROUP(GPIOX_1, 0), + GPIO_GROUP(GPIOX_2, 0), + GPIO_GROUP(GPIOX_3, 0), + GPIO_GROUP(GPIOX_4, 0), + GPIO_GROUP(GPIOX_5, 0), + GPIO_GROUP(GPIOX_6, 0), + GPIO_GROUP(GPIOX_7, 0), + GPIO_GROUP(GPIOX_8, 0), + GPIO_GROUP(GPIOX_9, 0), + GPIO_GROUP(GPIOX_10, 0), + GPIO_GROUP(GPIOX_11, 0), + GPIO_GROUP(GPIOX_12, 0), + GPIO_GROUP(GPIOX_13, 0), + GPIO_GROUP(GPIOX_14, 0), + GPIO_GROUP(GPIOX_15, 0), + GPIO_GROUP(GPIOX_16, 0), + GPIO_GROUP(GPIOX_17, 0), + GPIO_GROUP(GPIOX_18, 0), + GPIO_GROUP(GPIOX_19, 0), + GPIO_GROUP(GPIOX_20, 0), + GPIO_GROUP(GPIOX_21, 0), + GPIO_GROUP(GPIOY_0, 0), + GPIO_GROUP(GPIOY_1, 0), + GPIO_GROUP(GPIOY_2, 0), + GPIO_GROUP(GPIOY_3, 0), + GPIO_GROUP(GPIOY_4, 0), + GPIO_GROUP(GPIOY_5, 0), + GPIO_GROUP(GPIOY_6, 0), + GPIO_GROUP(GPIOY_7, 0), + GPIO_GROUP(GPIOY_8, 0), + GPIO_GROUP(GPIOY_9, 0), + GPIO_GROUP(GPIOY_10, 0), + GPIO_GROUP(GPIOY_11, 0), + GPIO_GROUP(GPIOY_12, 0), + GPIO_GROUP(GPIOY_13, 0), + GPIO_GROUP(GPIOY_14, 0), + GPIO_GROUP(GPIOY_15, 0), + GPIO_GROUP(GPIOY_16, 0), + GPIO_GROUP(GPIODV_0, 0), + GPIO_GROUP(GPIODV_1, 0), + GPIO_GROUP(GPIODV_2, 0), + GPIO_GROUP(GPIODV_3, 0), + GPIO_GROUP(GPIODV_4, 0), + GPIO_GROUP(GPIODV_5, 0), + GPIO_GROUP(GPIODV_6, 0), + GPIO_GROUP(GPIODV_7, 0), + GPIO_GROUP(GPIODV_8, 0), + GPIO_GROUP(GPIODV_9, 0), + GPIO_GROUP(GPIODV_10, 0), + GPIO_GROUP(GPIODV_11, 0), + GPIO_GROUP(GPIODV_12, 0), + GPIO_GROUP(GPIODV_13, 0), + GPIO_GROUP(GPIODV_14, 0), + GPIO_GROUP(GPIODV_15, 0), + GPIO_GROUP(GPIODV_16, 0), + GPIO_GROUP(GPIODV_17, 0), + GPIO_GROUP(GPIODV_18, 0), + GPIO_GROUP(GPIODV_19, 0), + GPIO_GROUP(GPIODV_20, 0), + GPIO_GROUP(GPIODV_21, 0), + GPIO_GROUP(GPIODV_22, 0), + GPIO_GROUP(GPIODV_23, 0), + GPIO_GROUP(GPIODV_24, 0), + GPIO_GROUP(GPIODV_25, 0), + GPIO_GROUP(GPIODV_26, 0), + GPIO_GROUP(GPIODV_27, 0), + GPIO_GROUP(GPIODV_28, 0), + GPIO_GROUP(GPIODV_29, 0), + GPIO_GROUP(GPIOH_0, 0), + GPIO_GROUP(GPIOH_1, 0), + GPIO_GROUP(GPIOH_2, 0), + GPIO_GROUP(GPIOH_3, 0), + GPIO_GROUP(GPIOH_4, 0), + GPIO_GROUP(GPIOH_5, 0), + GPIO_GROUP(GPIOH_6, 0), + GPIO_GROUP(GPIOH_7, 0), + GPIO_GROUP(GPIOH_8, 0), + GPIO_GROUP(GPIOH_9, 0), + GPIO_GROUP(GPIOZ_0, 0), + GPIO_GROUP(GPIOZ_1, 0), + GPIO_GROUP(GPIOZ_2, 0), + GPIO_GROUP(GPIOZ_3, 0), + GPIO_GROUP(GPIOZ_4, 0), + GPIO_GROUP(GPIOZ_5, 0), + GPIO_GROUP(GPIOZ_6, 0), + GPIO_GROUP(GPIOZ_7, 0), + GPIO_GROUP(GPIOZ_8, 0), + GPIO_GROUP(GPIOZ_9, 0), + GPIO_GROUP(GPIOZ_10, 0), + GPIO_GROUP(GPIOZ_11, 0), + GPIO_GROUP(GPIOZ_12, 0), + GPIO_GROUP(GPIOZ_13, 0), + GPIO_GROUP(GPIOZ_14, 0), + GPIO_GROUP(GPIOAO_0, AO_OFF), + GPIO_GROUP(GPIOAO_1, AO_OFF), + GPIO_GROUP(GPIOAO_2, AO_OFF), + GPIO_GROUP(GPIOAO_3, AO_OFF), + GPIO_GROUP(GPIOAO_4, AO_OFF), + GPIO_GROUP(GPIOAO_5, AO_OFF), + GPIO_GROUP(GPIOAO_6, AO_OFF), + GPIO_GROUP(GPIOAO_7, AO_OFF), + GPIO_GROUP(GPIOAO_8, AO_OFF), + GPIO_GROUP(GPIOAO_9, AO_OFF), + GPIO_GROUP(GPIOAO_10, AO_OFF), + GPIO_GROUP(GPIOAO_11, AO_OFF), + GPIO_GROUP(GPIOAO_12, AO_OFF), + GPIO_GROUP(GPIOAO_13, AO_OFF), + GPIO_GROUP(GPIO_BSD_EN, AO_OFF), + GPIO_GROUP(GPIO_TEST_N, AO_OFF), /* bank X */ GROUP(sd_d0_a, 8, 5), @@ -1045,19 +907,19 @@ static struct meson_pmx_func meson8_functions[] = { }; static struct meson_bank meson8_banks[] = { - /* name first last pullen pull dir out in */ - BANK("X", PIN_GPIOX_0, PIN_GPIOX_21, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), - BANK("Y", PIN_GPIOY_0, PIN_GPIOY_16, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), - BANK("DV", PIN_GPIODV_0, PIN_GPIODV_29, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0), - BANK("H", PIN_GPIOH_0, PIN_GPIOH_9, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), - BANK("Z", PIN_GPIOZ_0, PIN_GPIOZ_14, 1, 0, 1, 0, 3, 17, 4, 17, 5, 17), - BANK("CARD", PIN_CARD_0, PIN_CARD_6, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), - BANK("BOOT", PIN_BOOT_0, PIN_BOOT_18, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), + /* name first last pullen pull dir out in */ + BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), + BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_16, 0), 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), + BANK("DV", PIN(GPIODV_0, 0), PIN(GPIODV_29, 0), 0, 0, 0, 0, 7, 0, 8, 0, 9, 0), + BANK("H", PIN(GPIOH_0, 0), PIN(GPIOH_9, 0), 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), + BANK("Z", PIN(GPIOZ_0, 0), PIN(GPIOZ_14, 0), 1, 0, 1, 0, 3, 17, 4, 17, 5, 17), + BANK("CARD", PIN(CARD_0, 0), PIN(CARD_6, 0), 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), + BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), }; static struct meson_bank meson8_ao_banks[] = { - /* name first last pullen pull dir out in */ - BANK("AO", PIN_GPIOAO_0, PIN_GPIO_TEST_N, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), + /* name first last pullen pull dir out in */ + BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), }; static struct meson_domain_data meson8_domain_data[] = { diff --git a/drivers/pinctrl/meson/pinctrl-meson8b.c b/drivers/pinctrl/meson/pinctrl-meson8b.c new file mode 100644 index 000000000000..2f7ea6229880 --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson8b.c @@ -0,0 +1,899 @@ +/* + * Pin controller and GPIO driver for Amlogic Meson8b. + * + * Copyright (C) 2015 Endless Mobile, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <dt-bindings/gpio/meson8b-gpio.h> +#include "pinctrl-meson.h" + +#define AO_OFF 130 + +static const struct pinctrl_pin_desc meson8b_pins[] = { + MESON_PIN(GPIOX_0, 0), + MESON_PIN(GPIOX_1, 0), + MESON_PIN(GPIOX_2, 0), + MESON_PIN(GPIOX_3, 0), + MESON_PIN(GPIOX_4, 0), + MESON_PIN(GPIOX_5, 0), + MESON_PIN(GPIOX_6, 0), + MESON_PIN(GPIOX_7, 0), + MESON_PIN(GPIOX_8, 0), + MESON_PIN(GPIOX_9, 0), + MESON_PIN(GPIOX_10, 0), + MESON_PIN(GPIOX_11, 0), + MESON_PIN(GPIOX_16, 0), + MESON_PIN(GPIOX_17, 0), + MESON_PIN(GPIOX_18, 0), + MESON_PIN(GPIOX_19, 0), + MESON_PIN(GPIOX_20, 0), + MESON_PIN(GPIOX_21, 0), + + MESON_PIN(GPIOY_0, 0), + MESON_PIN(GPIOY_1, 0), + MESON_PIN(GPIOY_3, 0), + MESON_PIN(GPIOY_6, 0), + MESON_PIN(GPIOY_7, 0), + MESON_PIN(GPIOY_8, 0), + MESON_PIN(GPIOY_9, 0), + MESON_PIN(GPIOY_10, 0), + MESON_PIN(GPIOY_11, 0), + MESON_PIN(GPIOY_12, 0), + MESON_PIN(GPIOY_13, 0), + MESON_PIN(GPIOY_14, 0), + + MESON_PIN(GPIODV_9, 0), + MESON_PIN(GPIODV_24, 0), + MESON_PIN(GPIODV_25, 0), + MESON_PIN(GPIODV_26, 0), + MESON_PIN(GPIODV_27, 0), + MESON_PIN(GPIODV_28, 0), + MESON_PIN(GPIODV_29, 0), + + MESON_PIN(GPIOH_0, 0), + MESON_PIN(GPIOH_1, 0), + MESON_PIN(GPIOH_2, 0), + MESON_PIN(GPIOH_3, 0), + MESON_PIN(GPIOH_4, 0), + MESON_PIN(GPIOH_5, 0), + MESON_PIN(GPIOH_6, 0), + MESON_PIN(GPIOH_7, 0), + MESON_PIN(GPIOH_8, 0), + MESON_PIN(GPIOH_9, 0), + + MESON_PIN(CARD_0, 0), + MESON_PIN(CARD_1, 0), + MESON_PIN(CARD_2, 0), + MESON_PIN(CARD_3, 0), + MESON_PIN(CARD_4, 0), + MESON_PIN(CARD_5, 0), + MESON_PIN(CARD_6, 0), + + MESON_PIN(BOOT_0, 0), + MESON_PIN(BOOT_1, 0), + MESON_PIN(BOOT_2, 0), + MESON_PIN(BOOT_3, 0), + MESON_PIN(BOOT_4, 0), + MESON_PIN(BOOT_5, 0), + MESON_PIN(BOOT_6, 0), + MESON_PIN(BOOT_7, 0), + MESON_PIN(BOOT_8, 0), + MESON_PIN(BOOT_9, 0), + MESON_PIN(BOOT_10, 0), + MESON_PIN(BOOT_11, 0), + MESON_PIN(BOOT_12, 0), + MESON_PIN(BOOT_13, 0), + MESON_PIN(BOOT_14, 0), + MESON_PIN(BOOT_15, 0), + MESON_PIN(BOOT_16, 0), + MESON_PIN(BOOT_17, 0), + MESON_PIN(BOOT_18, 0), + + MESON_PIN(DIF_0_P, 0), + MESON_PIN(DIF_0_N, 0), + MESON_PIN(DIF_1_P, 0), + MESON_PIN(DIF_1_N, 0), + MESON_PIN(DIF_2_P, 0), + MESON_PIN(DIF_2_N, 0), + MESON_PIN(DIF_3_P, 0), + MESON_PIN(DIF_3_N, 0), + MESON_PIN(DIF_4_P, 0), + MESON_PIN(DIF_4_N, 0), + + MESON_PIN(GPIOAO_0, AO_OFF), + MESON_PIN(GPIOAO_1, AO_OFF), + MESON_PIN(GPIOAO_2, AO_OFF), + MESON_PIN(GPIOAO_3, AO_OFF), + MESON_PIN(GPIOAO_4, AO_OFF), + MESON_PIN(GPIOAO_5, AO_OFF), + MESON_PIN(GPIOAO_6, AO_OFF), + MESON_PIN(GPIOAO_7, AO_OFF), + MESON_PIN(GPIOAO_8, AO_OFF), + MESON_PIN(GPIOAO_9, AO_OFF), + MESON_PIN(GPIOAO_10, AO_OFF), + MESON_PIN(GPIOAO_11, AO_OFF), + MESON_PIN(GPIOAO_12, AO_OFF), + MESON_PIN(GPIOAO_13, AO_OFF), + MESON_PIN(GPIO_BSD_EN, AO_OFF), + MESON_PIN(GPIO_TEST_N, AO_OFF), +}; + +/* bank X */ +static const unsigned int sd_d0_a_pins[] = { PIN(GPIOX_0, 0) }; +static const unsigned int sd_d1_a_pins[] = { PIN(GPIOX_1, 0) }; +static const unsigned int sd_d2_a_pins[] = { PIN(GPIOX_2, 0) }; +static const unsigned int sd_d3_a_pins[] = { PIN(GPIOX_3, 0) }; +static const unsigned int sdxc_d0_0_a_pins[] = { PIN(GPIOX_4, 0) }; +static const unsigned int sdxc_d47_a_pins[] = { PIN(GPIOX_4, 0), PIN(GPIOX_5, 0), + PIN(GPIOX_6, 0), PIN(GPIOX_7, 0) }; +static const unsigned int sdxc_d13_0_a_pins[] = { PIN(GPIOX_5, 0), PIN(GPIOX_6, 0), + PIN(GPIOX_7, 0) }; +static const unsigned int sd_clk_a_pins[] = { PIN(GPIOX_8, 0) }; +static const unsigned int sd_cmd_a_pins[] = { PIN(GPIOX_9, 0) }; +static const unsigned int xtal_32k_out_pins[] = { PIN(GPIOX_10, 0) }; +static const unsigned int xtal_24m_out_pins[] = { PIN(GPIOX_11, 0) }; +static const unsigned int uart_tx_b0_pins[] = { PIN(GPIOX_16, 0) }; +static const unsigned int uart_rx_b0_pins[] = { PIN(GPIOX_17, 0) }; +static const unsigned int uart_cts_b0_pins[] = { PIN(GPIOX_18, 0) }; +static const unsigned int uart_rts_b0_pins[] = { PIN(GPIOX_19, 0) }; + +static const unsigned int sdxc_d0_1_a_pins[] = { PIN(GPIOX_0, 0) }; +static const unsigned int sdxc_d13_1_a_pins[] = { PIN(GPIOX_1, 0), PIN(GPIOX_2, 0), + PIN(GPIOX_3, 0) }; +static const unsigned int pcm_out_a_pins[] = { PIN(GPIOX_4, 0) }; +static const unsigned int pcm_in_a_pins[] = { PIN(GPIOX_5, 0) }; +static const unsigned int pcm_fs_a_pins[] = { PIN(GPIOX_6, 0) }; +static const unsigned int pcm_clk_a_pins[] = { PIN(GPIOX_7, 0) }; +static const unsigned int sdxc_clk_a_pins[] = { PIN(GPIOX_8, 0) }; +static const unsigned int sdxc_cmd_a_pins[] = { PIN(GPIOX_9, 0) }; +static const unsigned int pwm_vs_0_pins[] = { PIN(GPIOX_10, 0) }; +static const unsigned int pwm_e_pins[] = { PIN(GPIOX_10, 0) }; +static const unsigned int pwm_vs_1_pins[] = { PIN(GPIOX_11, 0) }; + +static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_4, 0) }; +static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_5, 0) }; +static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_6, 0) }; +static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_7, 0) }; +static const unsigned int uart_tx_b1_pins[] = { PIN(GPIOX_8, 0) }; +static const unsigned int uart_rx_b1_pins[] = { PIN(GPIOX_9, 0) }; +static const unsigned int uart_cts_b1_pins[] = { PIN(GPIOX_10, 0) }; +static const unsigned int uart_rts_b1_pins[] = { PIN(GPIOX_20, 0) }; + +static const unsigned int iso7816_0_clk_pins[] = { PIN(GPIOX_6, 0) }; +static const unsigned int iso7816_0_data_pins[] = { PIN(GPIOX_7, 0) }; +static const unsigned int spi_sclk_0_pins[] = { PIN(GPIOX_8, 0) }; +static const unsigned int spi_miso_0_pins[] = { PIN(GPIOX_9, 0) }; +static const unsigned int spi_mosi_0_pins[] = { PIN(GPIOX_10, 0) }; +static const unsigned int iso7816_det_pins[] = { PIN(GPIOX_16, 0) }; +static const unsigned int iso7816_reset_pins[] = { PIN(GPIOX_17, 0) }; +static const unsigned int iso7816_1_clk_pins[] = { PIN(GPIOX_18, 0) }; +static const unsigned int iso7816_1_data_pins[] = { PIN(GPIOX_19, 0) }; +static const unsigned int spi_ss0_0_pins[] = { PIN(GPIOX_20, 0) }; + +static const unsigned int tsin_clk_b_pins[] = { PIN(GPIOX_8, 0) }; +static const unsigned int tsin_sop_b_pins[] = { PIN(GPIOX_9, 0) }; +static const unsigned int tsin_d0_b_pins[] = { PIN(GPIOX_10, 0) }; +static const unsigned int pwm_b_pins[] = { PIN(GPIOX_11, 0) }; +static const unsigned int i2c_sda_d0_pins[] = { PIN(GPIOX_16, 0) }; +static const unsigned int i2c_sck_d0_pins[] = { PIN(GPIOX_17, 0) }; +static const unsigned int tsin_d_valid_b_pins[] = { PIN(GPIOX_20, 0) }; + +/* bank Y */ +static const unsigned int tsin_d_valid_a_pins[] = { PIN(GPIOY_0, 0) }; +static const unsigned int tsin_sop_a_pins[] = { PIN(GPIOY_1, 0) }; +static const unsigned int tsin_d17_a_pins[] = { PIN(GPIOY_6, 0), PIN(GPIOY_7, 0), + PIN(GPIOY_10, 0), PIN(GPIOY_11, 0), + PIN(GPIOY_12, 0), PIN(GPIOY_13, 0), + PIN(GPIOY_14, 0) }; +static const unsigned int tsin_clk_a_pins[] = { PIN(GPIOY_8, 0) }; +static const unsigned int tsin_d0_a_pins[] = { PIN(GPIOY_9, 0) }; + +static const unsigned int spdif_out_0_pins[] = { PIN(GPIOY_3, 0) }; + +static const unsigned int xtal_24m_pins[] = { PIN(GPIOY_3, 0) }; +static const unsigned int iso7816_2_clk_pins[] = { PIN(GPIOY_13, 0) }; +static const unsigned int iso7816_2_data_pins[] = { PIN(GPIOY_14, 0) }; + +/* bank DV */ +static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, 0) }; +static const unsigned int pwm_c0_pins[] = { PIN(GPIODV_29, 0) }; + +static const unsigned int pwm_vs_2_pins[] = { PIN(GPIODV_9, 0) }; +static const unsigned int pwm_vs_3_pins[] = { PIN(GPIODV_28, 0) }; +static const unsigned int pwm_vs_4_pins[] = { PIN(GPIODV_29, 0) }; + +static const unsigned int xtal24_out_pins[] = { PIN(GPIODV_29, 0) }; + +static const unsigned int uart_tx_c_pins[] = { PIN(GPIODV_24, 0) }; +static const unsigned int uart_rx_c_pins[] = { PIN(GPIODV_25, 0) }; +static const unsigned int uart_cts_c_pins[] = { PIN(GPIODV_26, 0) }; +static const unsigned int uart_rts_c_pins[] = { PIN(GPIODV_27, 0) }; + +static const unsigned int pwm_c1_pins[] = { PIN(GPIODV_9, 0) }; + +static const unsigned int i2c_sda_a_pins[] = { PIN(GPIODV_24, 0) }; +static const unsigned int i2c_sck_a_pins[] = { PIN(GPIODV_25, 0) }; +static const unsigned int i2c_sda_b0_pins[] = { PIN(GPIODV_26, 0) }; +static const unsigned int i2c_sck_b0_pins[] = { PIN(GPIODV_27, 0) }; +static const unsigned int i2c_sda_c0_pins[] = { PIN(GPIODV_28, 0) }; +static const unsigned int i2c_sck_c0_pins[] = { PIN(GPIODV_29, 0) }; + +/* bank H */ +static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, 0) }; +static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, 0) }; +static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, 0) }; +static const unsigned int hdmi_cec_0_pins[] = { PIN(GPIOH_3, 0) }; +static const unsigned int eth_txd1_0_pins[] = { PIN(GPIOH_5, 0) }; +static const unsigned int eth_txd0_0_pins[] = { PIN(GPIOH_6, 0) }; +static const unsigned int clk_24m_out_pins[] = { PIN(GPIOH_9, 0) }; + +static const unsigned int spi_ss1_pins[] = { PIN(GPIOH_0, 0) }; +static const unsigned int spi_ss2_pins[] = { PIN(GPIOH_1, 0) }; +static const unsigned int spi_ss0_1_pins[] = { PIN(GPIOH_3, 0) }; +static const unsigned int spi_miso_1_pins[] = { PIN(GPIOH_4, 0) }; +static const unsigned int spi_mosi_1_pins[] = { PIN(GPIOH_5, 0) }; +static const unsigned int spi_sclk_1_pins[] = { PIN(GPIOH_6, 0) }; + +static const unsigned int eth_txd3_pins[] = { PIN(GPIOH_7, 0) }; +static const unsigned int eth_txd2_pins[] = { PIN(GPIOH_8, 0) }; +static const unsigned int eth_tx_clk_pins[] = { PIN(GPIOH_9, 0) }; + +static const unsigned int i2c_sda_b1_pins[] = { PIN(GPIOH_3, 0) }; +static const unsigned int i2c_sck_b1_pins[] = { PIN(GPIOH_4, 0) }; +static const unsigned int i2c_sda_c1_pins[] = { PIN(GPIOH_5, 0) }; +static const unsigned int i2c_sck_c1_pins[] = { PIN(GPIOH_6, 0) }; +static const unsigned int i2c_sda_d1_pins[] = { PIN(GPIOH_7, 0) }; +static const unsigned int i2c_sck_d1_pins[] = { PIN(GPIOH_8, 0) }; + +/* bank BOOT */ +static const unsigned int nand_io_pins[] = { PIN(BOOT_0, 0), PIN(BOOT_1, 0), + PIN(BOOT_2, 0), PIN(BOOT_3, 0), + PIN(BOOT_4, 0), PIN(BOOT_5, 0), + PIN(BOOT_6, 0), PIN(BOOT_7, 0) }; +static const unsigned int nand_io_ce0_pins[] = { PIN(BOOT_8, 0) }; +static const unsigned int nand_io_ce1_pins[] = { PIN(BOOT_9, 0) }; +static const unsigned int nand_io_rb0_pins[] = { PIN(BOOT_10, 0) }; +static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, 0) }; +static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, 0) }; +static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, 0) }; +static const unsigned int nand_ren_clk_pins[] = { PIN(BOOT_14, 0) }; +static const unsigned int nand_dqs_0_pins[] = { PIN(BOOT_15, 0) }; +static const unsigned int nand_dqs_1_pins[] = { PIN(BOOT_18, 0) }; + +static const unsigned int sdxc_d0_c_pins[] = { PIN(BOOT_0, 0)}; +static const unsigned int sdxc_d13_c_pins[] = { PIN(BOOT_1, 0), PIN(BOOT_2, 0), + PIN(BOOT_3, 0) }; +static const unsigned int sdxc_d47_c_pins[] = { PIN(BOOT_4, 0), PIN(BOOT_5, 0), + PIN(BOOT_6, 0), PIN(BOOT_7, 0) }; +static const unsigned int sdxc_clk_c_pins[] = { PIN(BOOT_8, 0) }; +static const unsigned int sdxc_cmd_c_pins[] = { PIN(BOOT_10, 0) }; +static const unsigned int nor_d_pins[] = { PIN(BOOT_11, 0) }; +static const unsigned int nor_q_pins[] = { PIN(BOOT_12, 0) }; +static const unsigned int nor_c_pins[] = { PIN(BOOT_13, 0) }; +static const unsigned int nor_cs_pins[] = { PIN(BOOT_18, 0) }; + +static const unsigned int sd_d0_c_pins[] = { PIN(BOOT_0, 0) }; +static const unsigned int sd_d1_c_pins[] = { PIN(BOOT_1, 0) }; +static const unsigned int sd_d2_c_pins[] = { PIN(BOOT_2, 0) }; +static const unsigned int sd_d3_c_pins[] = { PIN(BOOT_3, 0) }; +static const unsigned int sd_cmd_c_pins[] = { PIN(BOOT_8, 0) }; +static const unsigned int sd_clk_c_pins[] = { PIN(BOOT_10, 0) }; + +/* bank CARD */ +static const unsigned int sd_d1_b_pins[] = { PIN(CARD_0, 0) }; +static const unsigned int sd_d0_b_pins[] = { PIN(CARD_1, 0) }; +static const unsigned int sd_clk_b_pins[] = { PIN(CARD_2, 0) }; +static const unsigned int sd_cmd_b_pins[] = { PIN(CARD_3, 0) }; +static const unsigned int sd_d3_b_pins[] = { PIN(CARD_4, 0) }; +static const unsigned int sd_d2_b_pins[] = { PIN(CARD_5, 0) }; + +static const unsigned int sdxc_d13_b_pins[] = { PIN(CARD_0, 0), PIN(CARD_4, 0), + PIN(CARD_5, 0) }; +static const unsigned int sdxc_d0_b_pins[] = { PIN(CARD_1, 0) }; +static const unsigned int sdxc_clk_b_pins[] = { PIN(CARD_2, 0) }; +static const unsigned int sdxc_cmd_b_pins[] = { PIN(CARD_3, 0) }; + +/* bank AO */ +static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, AO_OFF) }; +static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, AO_OFF) }; +static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, AO_OFF) }; +static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, AO_OFF) }; +static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) }; +static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) }; +static const unsigned int clk_32k_in_out_pins[] = { PIN(GPIOAO_6, AO_OFF) }; +static const unsigned int remote_input_pins[] = { PIN(GPIOAO_7, AO_OFF) }; +static const unsigned int hdmi_cec_1_pins[] = { PIN(GPIOAO_12, AO_OFF) }; +static const unsigned int ir_blaster_pins[] = { PIN(GPIOAO_13, AO_OFF) }; + +static const unsigned int pwm_c2_pins[] = { PIN(GPIOAO_3, AO_OFF) }; +static const unsigned int i2c_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) }; +static const unsigned int i2c_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) }; +static const unsigned int ir_remote_out_pins[] = { PIN(GPIOAO_7, AO_OFF) }; +static const unsigned int i2s_am_clk_out_pins[] = { PIN(GPIOAO_8, AO_OFF) }; +static const unsigned int i2s_ao_clk_out_pins[] = { PIN(GPIOAO_9, AO_OFF) }; +static const unsigned int i2s_lr_clk_out_pins[] = { PIN(GPIOAO_10, AO_OFF) }; +static const unsigned int i2s_out_01_pins[] = { PIN(GPIOAO_11, AO_OFF) }; + +static const unsigned int uart_tx_ao_b0_pins[] = { PIN(GPIOAO_0, AO_OFF) }; +static const unsigned int uart_rx_ao_b0_pins[] = { PIN(GPIOAO_1, AO_OFF) }; +static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, AO_OFF) }; +static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, AO_OFF) }; +static const unsigned int uart_tx_ao_b1_pins[] = { PIN(GPIOAO_4, AO_OFF) }; +static const unsigned int uart_rx_ao_b1_pins[] = { PIN(GPIOAO_5, AO_OFF) }; +static const unsigned int spdif_out_1_pins[] = { PIN(GPIOAO_6, AO_OFF) }; + +static const unsigned int i2s_in_ch01_pins[] = { PIN(GPIOAO_6, AO_OFF) }; +static const unsigned int i2s_ao_clk_in_pins[] = { PIN(GPIOAO_9, AO_OFF) }; +static const unsigned int i2s_lr_clk_in_pins[] = { PIN(GPIOAO_10, AO_OFF) }; + +/* bank DIF */ +static const unsigned int eth_rxd1_pins[] = { PIN(DIF_0_P, 0) }; +static const unsigned int eth_rxd0_pins[] = { PIN(DIF_0_N, 0) }; +static const unsigned int eth_rx_dv_pins[] = { PIN(DIF_1_P, 0) }; +static const unsigned int eth_rx_clk_pins[] = { PIN(DIF_1_N, 0) }; +static const unsigned int eth_txd0_1_pins[] = { PIN(DIF_2_P, 0) }; +static const unsigned int eth_txd1_1_pins[] = { PIN(DIF_2_N, 0) }; +static const unsigned int eth_tx_en_pins[] = { PIN(DIF_3_P, 0) }; +static const unsigned int eth_ref_clk_pins[] = { PIN(DIF_3_N, 0) }; +static const unsigned int eth_mdc_pins[] = { PIN(DIF_4_P, 0) }; +static const unsigned int eth_mdio_en_pins[] = { PIN(DIF_4_N, 0) }; + +static struct meson_pmx_group meson8b_groups[] = { + GPIO_GROUP(GPIOX_0, 0), + GPIO_GROUP(GPIOX_1, 0), + GPIO_GROUP(GPIOX_2, 0), + GPIO_GROUP(GPIOX_3, 0), + GPIO_GROUP(GPIOX_4, 0), + GPIO_GROUP(GPIOX_5, 0), + GPIO_GROUP(GPIOX_6, 0), + GPIO_GROUP(GPIOX_7, 0), + GPIO_GROUP(GPIOX_8, 0), + GPIO_GROUP(GPIOX_9, 0), + GPIO_GROUP(GPIOX_10, 0), + GPIO_GROUP(GPIOX_11, 0), + GPIO_GROUP(GPIOX_16, 0), + GPIO_GROUP(GPIOX_17, 0), + GPIO_GROUP(GPIOX_18, 0), + GPIO_GROUP(GPIOX_19, 0), + GPIO_GROUP(GPIOX_20, 0), + GPIO_GROUP(GPIOX_21, 0), + + GPIO_GROUP(GPIOY_0, 0), + GPIO_GROUP(GPIOY_1, 0), + GPIO_GROUP(GPIOY_3, 0), + GPIO_GROUP(GPIOY_6, 0), + GPIO_GROUP(GPIOY_7, 0), + GPIO_GROUP(GPIOY_8, 0), + GPIO_GROUP(GPIOY_9, 0), + GPIO_GROUP(GPIOY_10, 0), + GPIO_GROUP(GPIOY_11, 0), + GPIO_GROUP(GPIOY_12, 0), + GPIO_GROUP(GPIOY_13, 0), + GPIO_GROUP(GPIOY_14, 0), + + GPIO_GROUP(GPIODV_9, 0), + GPIO_GROUP(GPIODV_24, 0), + GPIO_GROUP(GPIODV_25, 0), + GPIO_GROUP(GPIODV_26, 0), + GPIO_GROUP(GPIODV_27, 0), + GPIO_GROUP(GPIODV_28, 0), + GPIO_GROUP(GPIODV_29, 0), + + GPIO_GROUP(GPIOH_0, 0), + GPIO_GROUP(GPIOH_1, 0), + GPIO_GROUP(GPIOH_2, 0), + GPIO_GROUP(GPIOH_3, 0), + GPIO_GROUP(GPIOH_4, 0), + GPIO_GROUP(GPIOH_5, 0), + GPIO_GROUP(GPIOH_6, 0), + GPIO_GROUP(GPIOH_7, 0), + GPIO_GROUP(GPIOH_8, 0), + GPIO_GROUP(GPIOH_9, 0), + + GPIO_GROUP(DIF_0_P, 0), + GPIO_GROUP(DIF_0_N, 0), + GPIO_GROUP(DIF_1_P, 0), + GPIO_GROUP(DIF_1_N, 0), + GPIO_GROUP(DIF_2_P, 0), + GPIO_GROUP(DIF_2_N, 0), + GPIO_GROUP(DIF_3_P, 0), + GPIO_GROUP(DIF_3_N, 0), + GPIO_GROUP(DIF_4_P, 0), + GPIO_GROUP(DIF_4_N, 0), + + GPIO_GROUP(GPIOAO_0, AO_OFF), + GPIO_GROUP(GPIOAO_1, AO_OFF), + GPIO_GROUP(GPIOAO_2, AO_OFF), + GPIO_GROUP(GPIOAO_3, AO_OFF), + GPIO_GROUP(GPIOAO_4, AO_OFF), + GPIO_GROUP(GPIOAO_5, AO_OFF), + GPIO_GROUP(GPIOAO_6, AO_OFF), + GPIO_GROUP(GPIOAO_7, AO_OFF), + GPIO_GROUP(GPIOAO_8, AO_OFF), + GPIO_GROUP(GPIOAO_9, AO_OFF), + GPIO_GROUP(GPIOAO_10, AO_OFF), + GPIO_GROUP(GPIOAO_11, AO_OFF), + GPIO_GROUP(GPIOAO_12, AO_OFF), + GPIO_GROUP(GPIOAO_13, AO_OFF), + GPIO_GROUP(GPIO_BSD_EN, AO_OFF), + GPIO_GROUP(GPIO_TEST_N, AO_OFF), + + /* bank X */ + GROUP(sd_d0_a, 8, 5), + GROUP(sd_d1_a, 8, 4), + GROUP(sd_d2_a, 8, 3), + GROUP(sd_d3_a, 8, 2), + GROUP(sdxc_d0_0_a, 5, 29), + GROUP(sdxc_d47_a, 5, 12), + GROUP(sdxc_d13_0_a, 5, 28), + GROUP(sd_clk_a, 8, 1), + GROUP(sd_cmd_a, 8, 0), + GROUP(xtal_32k_out, 3, 22), + GROUP(xtal_24m_out, 3, 20), + GROUP(uart_tx_b0, 4, 9), + GROUP(uart_rx_b0, 4, 8), + GROUP(uart_cts_b0, 4, 7), + GROUP(uart_rts_b0, 4, 6), + GROUP(sdxc_d0_1_a, 5, 14), + GROUP(sdxc_d13_1_a, 5, 13), + GROUP(pcm_out_a, 3, 30), + GROUP(pcm_in_a, 3, 29), + GROUP(pcm_fs_a, 3, 28), + GROUP(pcm_clk_a, 3, 27), + GROUP(sdxc_clk_a, 5, 11), + GROUP(sdxc_cmd_a, 5, 10), + GROUP(pwm_vs_0, 7, 31), + GROUP(pwm_e, 9, 19), + GROUP(pwm_vs_1, 7, 30), + GROUP(uart_tx_a, 4, 17), + GROUP(uart_rx_a, 4, 16), + GROUP(uart_cts_a, 4, 15), + GROUP(uart_rts_a, 4, 14), + GROUP(uart_tx_b1, 6, 19), + GROUP(uart_rx_b1, 6, 18), + GROUP(uart_cts_b1, 6, 17), + GROUP(uart_rts_b1, 6, 16), + GROUP(iso7816_0_clk, 5, 9), + GROUP(iso7816_0_data, 5, 8), + GROUP(spi_sclk_0, 4, 22), + GROUP(spi_miso_0, 4, 24), + GROUP(spi_mosi_0, 4, 23), + GROUP(iso7816_det, 4, 21), + GROUP(iso7816_reset, 4, 20), + GROUP(iso7816_1_clk, 4, 19), + GROUP(iso7816_1_data, 4, 18), + GROUP(spi_ss0_0, 4, 25), + GROUP(tsin_clk_b, 3, 6), + GROUP(tsin_sop_b, 3, 7), + GROUP(tsin_d0_b, 3, 8), + GROUP(pwm_b, 2, 3), + GROUP(i2c_sda_d0, 4, 5), + GROUP(i2c_sck_d0, 4, 4), + GROUP(tsin_d_valid_b, 3, 9), + + /* bank Y */ + GROUP(tsin_d_valid_a, 3, 2), + GROUP(tsin_sop_a, 3, 1), + GROUP(tsin_d17_a, 3, 5), + GROUP(tsin_clk_a, 3, 0), + GROUP(tsin_d0_a, 3, 4), + GROUP(spdif_out_0, 1, 7), + GROUP(xtal_24m, 3, 18), + GROUP(iso7816_2_clk, 5, 7), + GROUP(iso7816_2_data, 5, 6), + + /* bank DV */ + GROUP(pwm_d, 3, 26), + GROUP(pwm_c0, 3, 25), + GROUP(pwm_vs_2, 7, 28), + GROUP(pwm_vs_3, 7, 27), + GROUP(pwm_vs_4, 7, 26), + GROUP(xtal24_out, 7, 25), + GROUP(uart_tx_c, 6, 23), + GROUP(uart_rx_c, 6, 22), + GROUP(uart_cts_c, 6, 21), + GROUP(uart_rts_c, 6, 20), + GROUP(pwm_c1, 3, 24), + GROUP(i2c_sda_a, 9, 31), + GROUP(i2c_sck_a, 9, 30), + GROUP(i2c_sda_b0, 9, 29), + GROUP(i2c_sck_b0, 9, 28), + GROUP(i2c_sda_c0, 9, 27), + GROUP(i2c_sck_c0, 9, 26), + + /* bank H */ + GROUP(hdmi_hpd, 1, 26), + GROUP(hdmi_sda, 1, 25), + GROUP(hdmi_scl, 1, 24), + GROUP(hdmi_cec_0, 1, 23), + GROUP(eth_txd1_0, 7, 21), + GROUP(eth_txd0_0, 7, 20), + GROUP(clk_24m_out, 4, 1), + GROUP(spi_ss1, 8, 11), + GROUP(spi_ss2, 8, 12), + GROUP(spi_ss0_1, 9, 13), + GROUP(spi_miso_1, 9, 12), + GROUP(spi_mosi_1, 9, 11), + GROUP(spi_sclk_1, 9, 10), + GROUP(eth_txd3, 6, 13), + GROUP(eth_txd2, 6, 12), + GROUP(eth_tx_clk, 6, 11), + GROUP(i2c_sda_b1, 5, 27), + GROUP(i2c_sck_b1, 5, 26), + GROUP(i2c_sda_c1, 5, 25), + GROUP(i2c_sck_c1, 5, 24), + GROUP(i2c_sda_d1, 4, 3), + GROUP(i2c_sck_d1, 4, 2), + + /* bank BOOT */ + GROUP(nand_io, 2, 26), + GROUP(nand_io_ce0, 2, 25), + GROUP(nand_io_ce1, 2, 24), + GROUP(nand_io_rb0, 2, 17), + GROUP(nand_ale, 2, 21), + GROUP(nand_cle, 2, 20), + GROUP(nand_wen_clk, 2, 19), + GROUP(nand_ren_clk, 2, 18), + GROUP(nand_dqs_0, 2, 27), + GROUP(nand_dqs_1, 2, 28), + GROUP(sdxc_d0_c, 4, 30), + GROUP(sdxc_d13_c, 4, 29), + GROUP(sdxc_d47_c, 4, 28), + GROUP(sdxc_clk_c, 7, 19), + GROUP(sdxc_cmd_c, 7, 18), + GROUP(nor_d, 5, 1), + GROUP(nor_q, 5, 3), + GROUP(nor_c, 5, 2), + GROUP(nor_cs, 5, 0), + GROUP(sd_d0_c, 6, 29), + GROUP(sd_d1_c, 6, 28), + GROUP(sd_d2_c, 6, 27), + GROUP(sd_d3_c, 6, 26), + GROUP(sd_cmd_c, 6, 30), + GROUP(sd_clk_c, 6, 31), + + /* bank CARD */ + GROUP(sd_d1_b, 2, 14), + GROUP(sd_d0_b, 2, 15), + GROUP(sd_clk_b, 2, 11), + GROUP(sd_cmd_b, 2, 10), + GROUP(sd_d3_b, 2, 12), + GROUP(sd_d2_b, 2, 13), + GROUP(sdxc_d13_b, 2, 6), + GROUP(sdxc_d0_b, 2, 7), + GROUP(sdxc_clk_b, 2, 5), + GROUP(sdxc_cmd_b, 2, 4), + + /* bank AO */ + GROUP(uart_tx_ao_a, 0, 12), + GROUP(uart_rx_ao_a, 0, 11), + GROUP(uart_cts_ao_a, 0, 10), + GROUP(uart_rts_ao_a, 0, 9), + GROUP(i2c_mst_sck_ao, 0, 6), + GROUP(i2c_mst_sda_ao, 0, 5), + GROUP(clk_32k_in_out, 0, 18), + GROUP(remote_input, 0, 0), + GROUP(hdmi_cec_1, 0, 17), + GROUP(ir_blaster, 0, 31), + GROUP(pwm_c2, 0, 22), + GROUP(i2c_sck_ao, 0, 2), + GROUP(i2c_sda_ao, 0, 1), + GROUP(ir_remote_out, 0, 21), + GROUP(i2s_am_clk_out, 0, 30), + GROUP(i2s_ao_clk_out, 0, 29), + GROUP(i2s_lr_clk_out, 0, 28), + GROUP(i2s_out_01, 0, 27), + GROUP(uart_tx_ao_b0, 0, 26), + GROUP(uart_rx_ao_b0, 0, 25), + GROUP(uart_cts_ao_b, 0, 8), + GROUP(uart_rts_ao_b, 0, 7), + GROUP(uart_tx_ao_b1, 0, 24), + GROUP(uart_rx_ao_b1, 0, 23), + GROUP(spdif_out_1, 0, 16), + GROUP(i2s_in_ch01, 0, 13), + GROUP(i2s_ao_clk_in, 0, 15), + GROUP(i2s_lr_clk_in, 0, 14), + + /* bank DIF */ + GROUP(eth_rxd1, 6, 0), + GROUP(eth_rxd0, 6, 1), + GROUP(eth_rx_dv, 6, 2), + GROUP(eth_rx_clk, 6, 3), + GROUP(eth_txd0_1, 6, 4), + GROUP(eth_txd1_1, 6, 5), + GROUP(eth_tx_en, 6, 0), + GROUP(eth_ref_clk, 6, 8), + GROUP(eth_mdc, 6, 9), + GROUP(eth_mdio_en, 6, 10), +}; + +static const char * const gpio_groups[] = { + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", + "GPIOX_10", "GPIOX_11", "GPIOX_16", "GPIOX_17", "GPIOX_18", + "GPIOX_19", "GPIOX_20", "GPIOX_21", + + "GPIOY_0", "GPIOY_1", "GPIOY_3", "GPIOY_6", "GPIOY_7", + "GPIOY_8", "GPIOY_9", "GPIOY_10", "GPIOY_11", "GPIOY_12", + "GPIOY_13", "GPIOY_14", + + "GPIODV_9", "GPIODV_24", "GPIODV_25", "GPIODV_26", + "GPIODV_27", "GPIODV_28", "GPIODV_29", + + "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", + "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9", + + "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4", + "CARD_5", "CARD_6", + + "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4", + "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9", + "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14", + "BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18", + + "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", + "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", + "GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11", + "GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N", + + "DIF_0_P", "DIF_0_N", "DIF_1_P", "DIF_1_N", + "DIF_2_P", "DIF_2_N", "DIF_3_P", "DIF_3_N", + "DIF_4_P", "DIF_4_N" +}; + +static const char * const sd_a_groups[] = { + "sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a", + "sd_cmd_a" +}; + +static const char * const sdxc_a_groups[] = { + "sdxc_d0_0_a", "sdxc_d13_0_a", "sdxc_d47_a", "sdxc_clk_a", + "sdxc_cmd_a", "sdxc_d0_1_a", "sdxc_d0_13_1_a" +}; + +static const char * const pcm_a_groups[] = { + "pcm_out_a", "pcm_in_a", "pcm_fs_a", "pcm_clk_a" +}; + +static const char * const uart_a_groups[] = { + "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a" +}; + +static const char * const uart_b_groups[] = { + "uart_tx_b0", "uart_rx_b0", "uart_cts_b0", "uart_rts_b0", + "uart_tx_b1", "uart_rx_b1", "uart_cts_b1", "uart_rts_b1" +}; + +static const char * const iso7816_groups[] = { + "iso7816_det", "iso7816_reset", "iso7816_0_clk", "iso7816_0_data", + "iso7816_1_clk", "iso7816_1_data", "iso7816_2_clk", "iso7816_2_data" +}; + +static const char * const i2c_d_groups[] = { + "i2c_sda_d0", "i2c_sck_d0", "i2c_sda_d1", "i2c_sck_d1" +}; + +static const char * const xtal_groups[] = { + "xtal_32k_out", "xtal_24m_out", "xtal_24m", "xtal24_out" +}; + +static const char * const uart_c_groups[] = { + "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c" +}; + +static const char * const i2c_c_groups[] = { + "i2c_sda_c0", "i2c_sck_c0", "i2c_sda_c1", "i2c_sck_c1" +}; + +static const char * const hdmi_groups[] = { + "hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec_0", + "hdmi_cec_1" +}; + +static const char * const spi_groups[] = { + "spi_ss0_0", "spi_miso_0", "spi_mosi_0", "spi_sclk_0", + "spi_ss0_1", "spi_ss1", "spi_sclk_1", "spi_mosi_1", + "spi_miso_1", "spi_ss2" +}; + +static const char * const ethernet_groups[] = { + "eth_tx_clk", "eth_tx_en", "eth_txd1_0", "eth_txd1_1", + "eth_txd0_0", "eth_txd0_1", "eth_rx_clk", "eth_rx_dv", + "eth_rxd1", "eth_rxd0", "eth_mdio_en", "eth_mdc", "eth_ref_clk", + "eth_txd2", "eth_txd3" +}; + +static const char * const i2c_a_groups[] = { + "i2c_sda_a", "i2c_sck_a", +}; + +static const char * const i2c_b_groups[] = { + "i2c_sda_b0", "i2c_sck_b0", "i2c_sda_b1", "i2c_sck_b1" +}; + +static const char * const sd_c_groups[] = { + "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c", + "sd_cmd_c", "sd_clk_c" +}; + +static const char * const sdxc_c_groups[] = { + "sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_cmd_c", + "sdxc_clk_c" +}; + +static const char * const nand_groups[] = { + "nand_io", "nand_io_ce0", "nand_io_ce1", + "nand_io_rb0", "nand_ale", "nand_cle", + "nand_wen_clk", "nand_ren_clk", "nand_dqs0", + "nand_dqs1" +}; + +static const char * const nor_groups[] = { + "nor_d", "nor_q", "nor_c", "nor_cs" +}; + +static const char * const sd_b_groups[] = { + "sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b", + "sd_d3_b", "sd_d2_b" +}; + +static const char * const sdxc_b_groups[] = { + "sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b" +}; + +static const char * const uart_ao_groups[] = { + "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a" +}; + +static const char * const remote_groups[] = { + "remote_input", "ir_blaster", "ir_remote_out" +}; + +static const char * const i2c_slave_ao_groups[] = { + "i2c_sck_ao", "i2c_sda_ao" +}; + +static const char * const uart_ao_b_groups[] = { + "uart_tx_ao_b0", "uart_rx_ao_b0", "uart_tx_ao_b1", "uart_rx_ao_b1", + "uart_cts_ao_b", "uart_rts_ao_b" +}; + +static const char * const i2c_mst_ao_groups[] = { + "i2c_mst_sck_ao", "i2c_mst_sda_ao" +}; + +static const char * const clk_groups[] = { + "clk_24m_out", "clk_32k_in_out" +}; + +static const char * const spdif_groups[] = { + "spdif_out_1", "spdif_out_0" +}; + +static const char * const i2s_groups[] = { + "i2s_am_clk_out", "i2s_ao_clk_out", "i2s_lr_clk_out", + "i2s_out_01", "i2s_in_ch01", "i2s_ao_clk_in", + "i2s_lr_clk_in" +}; + +static const char * const pwm_b_groups[] = { + "pwm_b" +}; + +static const char * const pwm_c_groups[] = { + "pwm_c0", "pwm_c1", "pwm_c2" +}; + +static const char * const pwm_d_groups[] = { + "pwm_d" +}; + +static const char * const pwm_e_groups[] = { + "pwm_e" +}; + +static const char * const pwm_vs_groups[] = { + "pwm_vs_0", "pwm_vs_1", "pwm_vs_2", + "pwm_vs_3", "pwm_vs_4" +}; + +static const char * const tsin_a_groups[] = { + "tsin_d0_a", "tsin_d17_a", "tsin_clk_a", "tsin_sop_a", + "tsin_d_valid_a" +}; + +static const char * const tsin_b_groups[] = { + "tsin_d0_b", "tsin_clk_b", "tsin_sop_b", "tsin_d_valid_b" +}; + +static struct meson_pmx_func meson8b_functions[] = { + FUNCTION(gpio), + FUNCTION(sd_a), + FUNCTION(sdxc_a), + FUNCTION(pcm_a), + FUNCTION(uart_a), + FUNCTION(uart_b), + FUNCTION(iso7816), + FUNCTION(i2c_d), + FUNCTION(xtal), + FUNCTION(uart_c), + FUNCTION(i2c_c), + FUNCTION(hdmi), + FUNCTION(spi), + FUNCTION(ethernet), + FUNCTION(i2c_a), + FUNCTION(i2c_b), + FUNCTION(sd_c), + FUNCTION(sdxc_c), + FUNCTION(nand), + FUNCTION(nor), + FUNCTION(sd_b), + FUNCTION(sdxc_b), + FUNCTION(uart_ao), + FUNCTION(remote), + FUNCTION(i2c_slave_ao), + FUNCTION(uart_ao_b), + FUNCTION(i2c_mst_ao), + FUNCTION(clk), + FUNCTION(spdif), + FUNCTION(i2s), + FUNCTION(pwm_b), + FUNCTION(pwm_c), + FUNCTION(pwm_d), + FUNCTION(pwm_e), + FUNCTION(pwm_vs), + FUNCTION(tsin_a), + FUNCTION(tsin_b), +}; + +static struct meson_bank meson8b_banks[] = { + /* name first last pullen pull dir out in */ + BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), + BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_14, 0), 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), + BANK("DV", PIN(GPIODV_9, 0), PIN(GPIODV_29, 0), 0, 0, 0, 0, 7, 0, 8, 0, 9, 0), + BANK("H", PIN(GPIOH_0, 0), PIN(GPIOH_9, 0), 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), + BANK("CARD", PIN(CARD_0, 0), PIN(CARD_6, 0), 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), + BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), + BANK("DIF", PIN(DIF_0_P, 0), PIN(DIF_4_N, 0), 5, 8, 5, 8, 12, 12, 13, 12, 14, 12), +}; + +static struct meson_bank meson8b_ao_banks[] = { + /* name first last pullen pull dir out in */ + BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), +}; + +static struct meson_domain_data meson8b_domain_data[] = { + { + .name = "banks", + .banks = meson8b_banks, + .num_banks = ARRAY_SIZE(meson8b_banks), + .pin_base = 0, + .num_pins = 83, + }, + { + .name = "ao-bank", + .banks = meson8b_ao_banks, + .num_banks = ARRAY_SIZE(meson8b_ao_banks), + .pin_base = 83, + .num_pins = 16, + }, +}; + +struct meson_pinctrl_data meson8b_pinctrl_data = { + .pins = meson8b_pins, + .groups = meson8b_groups, + .funcs = meson8b_functions, + .domain_data = meson8b_domain_data, + .num_pins = ARRAY_SIZE(meson8b_pins), + .num_groups = ARRAY_SIZE(meson8b_groups), + .num_funcs = ARRAY_SIZE(meson8b_functions), + .num_domains = ARRAY_SIZE(meson8b_domain_data), +}; diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig index d6dd8358a6f6..170602407c0d 100644 --- a/drivers/pinctrl/mvebu/Kconfig +++ b/drivers/pinctrl/mvebu/Kconfig @@ -26,6 +26,10 @@ config PINCTRL_ARMADA_38X bool select PINCTRL_MVEBU +config PINCTRL_ARMADA_39X + bool + select PINCTRL_MVEBU + config PINCTRL_ARMADA_XP bool select PINCTRL_MVEBU diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile index a0818e96374b..554d8af14eeb 100644 --- a/drivers/pinctrl/mvebu/Makefile +++ b/drivers/pinctrl/mvebu/Makefile @@ -4,5 +4,6 @@ obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o +obj-$(CONFIG_PINCTRL_ARMADA_39X) += pinctrl-armada-39x.o obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o obj-$(CONFIG_PINCTRL_ORION) += pinctrl-orion.o diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c index c4f51d0cd2cc..42f930f70de3 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c @@ -379,7 +379,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { static struct mvebu_pinctrl_soc_info armada_370_pinctrl_info; -static struct of_device_id armada_370_pinctrl_of_match[] = { +static const struct of_device_id armada_370_pinctrl_of_match[] = { { .compatible = "marvell,mv88f6710-pinctrl" }, { }, }; diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-375.c b/drivers/pinctrl/mvebu/pinctrl-armada-375.c index cd7c8f51f7d9..ca1e7571fedb 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-375.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c @@ -399,7 +399,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { static struct mvebu_pinctrl_soc_info armada_375_pinctrl_info; -static struct of_device_id armada_375_pinctrl_of_match[] = { +static const struct of_device_id armada_375_pinctrl_of_match[] = { { .compatible = "marvell,mv88f6720-pinctrl" }, { }, }; diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index 7302f66f4f19..83bbcc72be1f 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -389,7 +389,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { static struct mvebu_pinctrl_soc_info armada_38x_pinctrl_info; -static struct of_device_id armada_38x_pinctrl_of_match[] = { +static const struct of_device_id armada_38x_pinctrl_of_match[] = { { .compatible = "marvell,mv88f6810-pinctrl", .data = (void *) V_88F6810, diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c new file mode 100644 index 000000000000..42491624d660 --- /dev/null +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -0,0 +1,432 @@ +/* + * Marvell Armada 39x pinctrl driver based on mvebu pinctrl core + * + * Copyright (C) 2015 Marvell + * + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-mvebu.h" + +static void __iomem *mpp_base; + +static int armada_39x_mpp_ctrl_get(unsigned pid, unsigned long *config) +{ + return default_mpp_ctrl_get(mpp_base, pid, config); +} + +static int armada_39x_mpp_ctrl_set(unsigned pid, unsigned long config) +{ + return default_mpp_ctrl_set(mpp_base, pid, config); +} + +enum { + V_88F6920 = BIT(0), + V_88F6928 = BIT(1), + V_88F6920_PLUS = (V_88F6920 | V_88F6928), +}; + +static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { + MPP_MODE(0, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "ua0", "rxd", V_88F6920_PLUS)), + MPP_MODE(1, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "ua0", "txd", V_88F6920_PLUS)), + MPP_MODE(2, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "i2c0", "sck", V_88F6920_PLUS)), + MPP_MODE(3, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "i2c0", "sda", V_88F6920_PLUS)), + MPP_MODE(4, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(2, "ua1", "txd", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "smi", "mdc", V_88F6920_PLUS)), + MPP_MODE(5, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(2, "ua1", "rxd", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "smi", "mdio", V_88F6920_PLUS)), + MPP_MODE(6, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "cs3", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "xsmi", "mdio", V_88F6920_PLUS)), + MPP_MODE(7, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad9", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "xsmi", "mdc", V_88F6920_PLUS)), + MPP_MODE(8, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad10", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "ptp", "trig", V_88F6920_PLUS)), + MPP_MODE(9, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad11", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "ptp", "clk", V_88F6920_PLUS)), + MPP_MODE(10, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad12", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "ptp", "event", V_88F6920_PLUS)), + MPP_MODE(11, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad13", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "led", "clk", V_88F6920_PLUS)), + MPP_MODE(12, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad14", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "led", "stb", V_88F6920_PLUS)), + MPP_MODE(13, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad15", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "led", "data", V_88F6920_PLUS)), + MPP_MODE(14, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "m", "vtt", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "wen1", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "ua1", "txd", V_88F6920_PLUS)), + MPP_MODE(15, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "spi0", "mosi", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "i2c1", "sck", V_88F6920_PLUS)), + MPP_MODE(16, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "m", "decc", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "spi0", "miso", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "i2c1", "sda", V_88F6920_PLUS)), + MPP_MODE(17, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "spi0", "sck", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "smi", "mdio", V_88F6920_PLUS)), + MPP_MODE(18, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "spi0", "cs0", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "i2c2", "sck", V_88F6920_PLUS)), + MPP_MODE(19, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sata1", "present", V_88F6928), + MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6920_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "i2c2", "sda", V_88F6920_PLUS)), + MPP_MODE(20, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sata0", "present", V_88F6928), + MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6920_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "smi", "mdc", V_88F6920_PLUS)), + MPP_MODE(21, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "sata0", "present", V_88F6928), + MPP_VAR_FUNCTION(4, "sd", "cmd", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6920_PLUS), + MPP_VAR_FUNCTION(8, "ge", "rxd0", V_88F6920_PLUS)), + MPP_MODE(22, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "spi0", "mosi", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad0", V_88F6920_PLUS)), + MPP_MODE(23, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "spi0", "sck", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad2", V_88F6920_PLUS)), + MPP_MODE(24, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "spi0", "miso", V_88F6920_PLUS), + MPP_VAR_FUNCTION(2, "ua0", "cts", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd", "d4", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "readyn", V_88F6920_PLUS)), + MPP_MODE(25, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "spi0", "cs0", V_88F6920_PLUS), + MPP_VAR_FUNCTION(2, "ua0", "rts", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd", "d5", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "cs0", V_88F6920_PLUS)), + MPP_MODE(26, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "spi0", "cs2", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "i2c1", "sck", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd", "d6", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "cs1", V_88F6920_PLUS)), + MPP_MODE(27, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "spi0", "cs3", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "i2c1", "sda", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd", "d7", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "cs2", V_88F6920_PLUS), + MPP_VAR_FUNCTION(8, "ge", "txclkout", V_88F6920_PLUS)), + MPP_MODE(28, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd", "clk", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad5", V_88F6920_PLUS), + MPP_VAR_FUNCTION(8, "ge", "txd0", V_88F6920_PLUS)), + MPP_MODE(29, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ale0", V_88F6920_PLUS), + MPP_VAR_FUNCTION(8, "ge", "txd1", V_88F6920_PLUS)), + MPP_MODE(30, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "oen", V_88F6920_PLUS), + MPP_VAR_FUNCTION(8, "ge", "txd2", V_88F6920_PLUS)), + MPP_MODE(31, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ale1", V_88F6920_PLUS), + MPP_VAR_FUNCTION(8, "ge", "txd3", V_88F6920_PLUS)), + MPP_MODE(32, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "wen0", V_88F6920_PLUS), + MPP_VAR_FUNCTION(8, "ge", "txctl", V_88F6920_PLUS)), + MPP_MODE(33, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "m", "decc", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad3", V_88F6920_PLUS)), + MPP_MODE(34, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad1", V_88F6920_PLUS)), + MPP_MODE(35, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "ref", "clk", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "a1", V_88F6920_PLUS)), + MPP_MODE(36, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "a0", V_88F6920_PLUS)), + MPP_MODE(37, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd", "d3", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad8", V_88F6920_PLUS), + MPP_VAR_FUNCTION(8, "ge", "rxclk", V_88F6920_PLUS)), + MPP_MODE(38, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "ref", "clk", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd", "d0", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad4", V_88F6920_PLUS), + MPP_VAR_FUNCTION(8, "ge", "rxd1", V_88F6920_PLUS)), + MPP_MODE(39, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "i2c1", "sck", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd", "d1", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "a2", V_88F6920_PLUS), + MPP_VAR_FUNCTION(8, "ge", "rxd2", V_88F6920_PLUS)), + MPP_MODE(40, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "i2c1", "sda", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd", "d2", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad6", V_88F6920_PLUS), + MPP_VAR_FUNCTION(8, "ge", "rxd3", V_88F6920_PLUS)), + MPP_MODE(41, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "ua1", "rxd", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "spi1", "cs3", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "burstn", V_88F6920_PLUS), + MPP_VAR_FUNCTION(6, "nd", "rbn0", V_88F6920_PLUS), + MPP_VAR_FUNCTION(8, "ge", "rxctl", V_88F6920_PLUS)), + MPP_MODE(42, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "ua1", "txd", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad7", V_88F6920_PLUS)), + MPP_MODE(43, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "pcie0", "clkreq", V_88F6920_PLUS), + MPP_VAR_FUNCTION(2, "m", "vtt", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "m", "decc", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6920_PLUS), + MPP_VAR_FUNCTION(6, "nd", "rbn1", V_88F6920_PLUS)), + MPP_MODE(44, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928), + MPP_VAR_FUNCTION(2, "sata1", "present", V_88F6928), + MPP_VAR_FUNCTION(7, "led", "clk", V_88F6920_PLUS)), + MPP_MODE(45, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "ref", "clk", V_88F6920_PLUS), + MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6920_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS)), + MPP_MODE(46, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "ref", "clk", V_88F6920_PLUS), + MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6920_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "led", "stb", V_88F6920_PLUS)), + MPP_MODE(47, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928), + MPP_VAR_FUNCTION(2, "sata1", "present", V_88F6928), + MPP_VAR_FUNCTION(7, "led", "data", V_88F6920_PLUS)), + MPP_MODE(48, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928), + MPP_VAR_FUNCTION(2, "m", "vtt", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "tdm", "pclk", V_88F6928), + MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6928), + MPP_VAR_FUNCTION(5, "sd", "d4", V_88F6920_PLUS), + MPP_VAR_FUNCTION(6, "pcie0", "clkreq", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "ua1", "txd", V_88F6920_PLUS)), + MPP_MODE(49, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "tdm", "fsync", V_88F6928), + MPP_VAR_FUNCTION(4, "audio", "lrclk", V_88F6928), + MPP_VAR_FUNCTION(5, "sd", "d5", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "ua2", "rxd", V_88F6920_PLUS)), + MPP_MODE(50, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "tdm", "drx", V_88F6928), + MPP_VAR_FUNCTION(4, "audio", "extclk", V_88F6928), + MPP_VAR_FUNCTION(5, "sd", "cmd", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "ua2", "rxd", V_88F6920_PLUS)), + MPP_MODE(51, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "tdm", "dtx", V_88F6928), + MPP_VAR_FUNCTION(4, "audio", "sdo", V_88F6928), + MPP_VAR_FUNCTION(5, "m", "decc", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "ua2", "txd", V_88F6920_PLUS)), + MPP_MODE(52, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "tdm", "intn", V_88F6928), + MPP_VAR_FUNCTION(4, "audio", "sdi", V_88F6928), + MPP_VAR_FUNCTION(5, "sd", "d6", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "i2c3", "sck", V_88F6920_PLUS)), + MPP_MODE(53, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "sata1", "present", V_88F6928), + MPP_VAR_FUNCTION(2, "sata0", "present", V_88F6928), + MPP_VAR_FUNCTION(3, "tdm", "rstn", V_88F6928), + MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6928), + MPP_VAR_FUNCTION(5, "sd", "d7", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "i2c3", "sda", V_88F6920_PLUS)), + MPP_MODE(54, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928), + MPP_VAR_FUNCTION(2, "sata1", "present", V_88F6928), + MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd", "d3", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "ua3", "txd", V_88F6920_PLUS)), + MPP_MODE(55, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "ua1", "cts", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "spi1", "cs1", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd", "d0", V_88F6920_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS), + MPP_VAR_FUNCTION(7, "ua3", "rxd", V_88F6920_PLUS)), + MPP_MODE(56, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "ua1", "rts", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "m", "decc", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "spi1", "mosi", V_88F6920_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS)), + MPP_MODE(57, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "spi1", "sck", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd", "clk", V_88F6920_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS)), + MPP_MODE(58, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(2, "i2c1", "sck", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "pcie2", "clkreq", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "spi1", "miso", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd", "d1", V_88F6920_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS)), + MPP_MODE(59, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6920_PLUS), + MPP_VAR_FUNCTION(2, "i2c1", "sda", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "spi1", "cs0", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd", "d2", V_88F6920_PLUS)), +}; + +static struct mvebu_pinctrl_soc_info armada_39x_pinctrl_info; + +static const struct of_device_id armada_39x_pinctrl_of_match[] = { + { + .compatible = "marvell,mv88f6920-pinctrl", + .data = (void *) V_88F6920, + }, + { + .compatible = "marvell,mv88f6928-pinctrl", + .data = (void *) V_88F6928, + }, + { }, +}; + +static struct mvebu_mpp_ctrl armada_39x_mpp_controls[] = { + MPP_FUNC_CTRL(0, 59, NULL, armada_39x_mpp_ctrl), +}; + +static struct pinctrl_gpio_range armada_39x_mpp_gpio_ranges[] = { + MPP_GPIO_RANGE(0, 0, 0, 32), + MPP_GPIO_RANGE(1, 32, 32, 27), +}; + +static int armada_39x_pinctrl_probe(struct platform_device *pdev) +{ + struct mvebu_pinctrl_soc_info *soc = &armada_39x_pinctrl_info; + const struct of_device_id *match = + of_match_device(armada_39x_pinctrl_of_match, &pdev->dev); + struct resource *res; + + if (!match) + return -ENODEV; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mpp_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mpp_base)) + return PTR_ERR(mpp_base); + + soc->variant = (unsigned) match->data & 0xff; + soc->controls = armada_39x_mpp_controls; + soc->ncontrols = ARRAY_SIZE(armada_39x_mpp_controls); + soc->gpioranges = armada_39x_mpp_gpio_ranges; + soc->ngpioranges = ARRAY_SIZE(armada_39x_mpp_gpio_ranges); + soc->modes = armada_39x_mpp_modes; + soc->nmodes = armada_39x_mpp_controls[0].npins; + + pdev->dev.platform_data = soc; + + return mvebu_pinctrl_probe(pdev); +} + +static int armada_39x_pinctrl_remove(struct platform_device *pdev) +{ + return mvebu_pinctrl_remove(pdev); +} + +static struct platform_driver armada_39x_pinctrl_driver = { + .driver = { + .name = "armada-39x-pinctrl", + .of_match_table = of_match_ptr(armada_39x_pinctrl_of_match), + }, + .probe = armada_39x_pinctrl_probe, + .remove = armada_39x_pinctrl_remove, +}; + +module_platform_driver(armada_39x_pinctrl_driver); + +MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); +MODULE_DESCRIPTION("Marvell Armada 39x pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index fc3376147c18..578db9f033b2 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -34,6 +34,7 @@ #include "pinctrl-mvebu.h" static void __iomem *mpp_base; +static u32 *mpp_saved_regs; static int armada_xp_mpp_ctrl_get(unsigned pid, unsigned long *config) { @@ -361,7 +362,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { static struct mvebu_pinctrl_soc_info armada_xp_pinctrl_info; -static struct of_device_id armada_xp_pinctrl_of_match[] = { +static const struct of_device_id armada_xp_pinctrl_of_match[] = { { .compatible = "marvell,mv78230-pinctrl", .data = (void *) V_MV78230, @@ -406,12 +407,42 @@ static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = { MPP_GPIO_RANGE(2, 64, 64, 3), }; +static int armada_xp_pinctrl_suspend(struct platform_device *pdev, + pm_message_t state) +{ + struct mvebu_pinctrl_soc_info *soc = + platform_get_drvdata(pdev); + int i, nregs; + + nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG); + + for (i = 0; i < nregs; i++) + mpp_saved_regs[i] = readl(mpp_base + i * 4); + + return 0; +} + +static int armada_xp_pinctrl_resume(struct platform_device *pdev) +{ + struct mvebu_pinctrl_soc_info *soc = + platform_get_drvdata(pdev); + int i, nregs; + + nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG); + + for (i = 0; i < nregs; i++) + writel(mpp_saved_regs[i], mpp_base + i * 4); + + return 0; +} + static int armada_xp_pinctrl_probe(struct platform_device *pdev) { struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info; const struct of_device_id *match = of_match_device(armada_xp_pinctrl_of_match, &pdev->dev); struct resource *res; + int nregs; if (!match) return -ENODEV; @@ -459,6 +490,13 @@ static int armada_xp_pinctrl_probe(struct platform_device *pdev) break; } + nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG); + + mpp_saved_regs = devm_kmalloc(&pdev->dev, nregs * sizeof(u32), + GFP_KERNEL); + if (!mpp_saved_regs) + return -ENOMEM; + pdev->dev.platform_data = soc; return mvebu_pinctrl_probe(pdev); @@ -476,6 +514,8 @@ static struct platform_driver armada_xp_pinctrl_driver = { }, .probe = armada_xp_pinctrl_probe, .remove = armada_xp_pinctrl_remove, + .suspend = armada_xp_pinctrl_suspend, + .resume = armada_xp_pinctrl_resume, }; module_platform_driver(armada_xp_pinctrl_driver); diff --git a/drivers/pinctrl/mvebu/pinctrl-kirkwood.c b/drivers/pinctrl/mvebu/pinctrl-kirkwood.c index dbc673cf7131..0f07dc554a1d 100644 --- a/drivers/pinctrl/mvebu/pinctrl-kirkwood.c +++ b/drivers/pinctrl/mvebu/pinctrl-kirkwood.c @@ -456,7 +456,7 @@ static struct mvebu_pinctrl_soc_info mv98dx4122_info = { .ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges), }; -static struct of_device_id kirkwood_pinctrl_of_match[] = { +static const struct of_device_id kirkwood_pinctrl_of_match[] = { { .compatible = "marvell,88f6180-pinctrl", .data = &mv88f6180_info }, { .compatible = "marvell,88f6190-pinctrl", .data = &mv88f6190_info }, { .compatible = "marvell,88f6192-pinctrl", .data = &mv88f6192_info }, diff --git a/drivers/pinctrl/mvebu/pinctrl-orion.c b/drivers/pinctrl/mvebu/pinctrl-orion.c index 3a632efb56bb..3b7122d826e4 100644 --- a/drivers/pinctrl/mvebu/pinctrl-orion.c +++ b/drivers/pinctrl/mvebu/pinctrl-orion.c @@ -211,7 +211,7 @@ static struct mvebu_pinctrl_soc_info mv88f5281_info = { * There are multiple variants of the Orion SoCs, but in terms of pin * muxing, they are identical. */ -static struct of_device_id orion_pinctrl_of_match[] = { +static const struct of_device_id orion_pinctrl_of_match[] = { { .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181l_info }, { .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info }, { .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info }, diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 4db92f64b4de..e63ad9fbd388 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -283,23 +283,40 @@ int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev, struct device *dev = pctldev->dev; unsigned long *configs = NULL; unsigned num_configs = 0; - unsigned reserve; + unsigned reserve, strings_count; struct property *prop; const char *group; const char *subnode_target_type = "pins"; + ret = of_property_count_strings(np, "pins"); + if (ret < 0) { + ret = of_property_count_strings(np, "groups"); + if (ret < 0) + /* skip this node; may contain config child nodes */ + return 0; + if (type == PIN_MAP_TYPE_INVALID) + type = PIN_MAP_TYPE_CONFIGS_GROUP; + subnode_target_type = "groups"; + } else { + if (type == PIN_MAP_TYPE_INVALID) + type = PIN_MAP_TYPE_CONFIGS_PIN; + } + strings_count = ret; + ret = of_property_read_string(np, "function", &function); if (ret < 0) { /* EINVAL=missing, which is fine since it's optional */ if (ret != -EINVAL) - dev_err(dev, "could not parse property function\n"); + dev_err(dev, "%s: could not parse property function\n", + of_node_full_name(np)); function = NULL; } ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs); if (ret < 0) { - dev_err(dev, "could not parse node property\n"); + dev_err(dev, "%s: could not parse node property\n", + of_node_full_name(np)); return ret; } @@ -309,21 +326,7 @@ int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev, if (num_configs) reserve++; - ret = of_property_count_strings(np, "pins"); - if (ret < 0) { - ret = of_property_count_strings(np, "groups"); - if (ret < 0) { - dev_err(dev, "could not parse property pins/groups\n"); - goto exit; - } - if (type == PIN_MAP_TYPE_INVALID) - type = PIN_MAP_TYPE_CONFIGS_GROUP; - subnode_target_type = "groups"; - } else { - if (type == PIN_MAP_TYPE_INVALID) - type = PIN_MAP_TYPE_CONFIGS_PIN; - } - reserve *= ret; + reserve *= strings_count; ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, reserve); @@ -367,15 +370,22 @@ int pinconf_generic_dt_node_to_map(struct pinctrl_dev *pctldev, *map = NULL; *num_maps = 0; + ret = pinconf_generic_dt_subnode_to_map(pctldev, np_config, map, + &reserved_maps, num_maps, type); + if (ret < 0) + goto exit; + for_each_child_of_node(np_config, np) { ret = pinconf_generic_dt_subnode_to_map(pctldev, np, map, &reserved_maps, num_maps, type); - if (ret < 0) { - pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); - return ret; - } + if (ret < 0) + goto exit; } return 0; + +exit: + pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); + return ret; } EXPORT_SYMBOL_GPL(pinconf_generic_dt_node_to_map); diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c new file mode 100644 index 000000000000..7de3b64bf142 --- /dev/null +++ b/drivers/pinctrl/pinctrl-amd.c @@ -0,0 +1,869 @@ +/* + * GPIO driver for AMD + * + * Copyright (c) 2014,2015 AMD Corporation. + * Authors: Ken Xue <Ken.Xue@amd.com> + * Wu, Jeff <Jeff.Wu@amd.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ + +#include <linux/err.h> +#include <linux/bug.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/spinlock.h> +#include <linux/compiler.h> +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/log2.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/slab.h> +#include <linux/platform_device.h> +#include <linux/mutex.h> +#include <linux/acpi.h> +#include <linux/seq_file.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/bitops.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> + +#include "pinctrl-utils.h" +#include "pinctrl-amd.h" + +static inline struct amd_gpio *to_amd_gpio(struct gpio_chip *gc) +{ + return container_of(gc, struct amd_gpio, gc); +} + +static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) +{ + unsigned long flags; + u32 pin_reg; + struct amd_gpio *gpio_dev = to_amd_gpio(gc); + + spin_lock_irqsave(&gpio_dev->lock, flags); + pin_reg = readl(gpio_dev->base + offset * 4); + /* + * Suppose BIOS or Bootloader sets specific debounce for the + * GPIO. if not, set debounce to be 2.75ms and remove glitch. + */ + if ((pin_reg & DB_TMR_OUT_MASK) == 0) { + pin_reg |= 0xf; + pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); + pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; + pin_reg &= ~BIT(DB_TMR_LARGE_OFF); + } + + pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); + writel(pin_reg, gpio_dev->base + offset * 4); + spin_unlock_irqrestore(&gpio_dev->lock, flags); + + return 0; +} + +static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, + int value) +{ + u32 pin_reg; + unsigned long flags; + struct amd_gpio *gpio_dev = to_amd_gpio(gc); + + spin_lock_irqsave(&gpio_dev->lock, flags); + pin_reg = readl(gpio_dev->base + offset * 4); + pin_reg |= BIT(OUTPUT_ENABLE_OFF); + if (value) + pin_reg |= BIT(OUTPUT_VALUE_OFF); + else + pin_reg &= ~BIT(OUTPUT_VALUE_OFF); + writel(pin_reg, gpio_dev->base + offset * 4); + spin_unlock_irqrestore(&gpio_dev->lock, flags); + + return 0; +} + +static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) +{ + u32 pin_reg; + unsigned long flags; + struct amd_gpio *gpio_dev = to_amd_gpio(gc); + + spin_lock_irqsave(&gpio_dev->lock, flags); + pin_reg = readl(gpio_dev->base + offset * 4); + spin_unlock_irqrestore(&gpio_dev->lock, flags); + + return !!(pin_reg & BIT(PIN_STS_OFF)); +} + +static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) +{ + u32 pin_reg; + unsigned long flags; + struct amd_gpio *gpio_dev = to_amd_gpio(gc); + + spin_lock_irqsave(&gpio_dev->lock, flags); + pin_reg = readl(gpio_dev->base + offset * 4); + if (value) + pin_reg |= BIT(OUTPUT_VALUE_OFF); + else + pin_reg &= ~BIT(OUTPUT_VALUE_OFF); + writel(pin_reg, gpio_dev->base + offset * 4); + spin_unlock_irqrestore(&gpio_dev->lock, flags); +} + +static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, + unsigned debounce) +{ + u32 time; + u32 pin_reg; + int ret = 0; + unsigned long flags; + struct amd_gpio *gpio_dev = to_amd_gpio(gc); + + spin_lock_irqsave(&gpio_dev->lock, flags); + pin_reg = readl(gpio_dev->base + offset * 4); + + if (debounce) { + pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; + pin_reg &= ~DB_TMR_OUT_MASK; + /* + Debounce Debounce Timer Max + TmrLarge TmrOutUnit Unit Debounce + Time + 0 0 61 usec (2 RtcClk) 976 usec + 0 1 244 usec (8 RtcClk) 3.9 msec + 1 0 15.6 msec (512 RtcClk) 250 msec + 1 1 62.5 msec (2048 RtcClk) 1 sec + */ + + if (debounce < 61) { + pin_reg |= 1; + pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); + pin_reg &= ~BIT(DB_TMR_LARGE_OFF); + } else if (debounce < 976) { + time = debounce / 61; + pin_reg |= time & DB_TMR_OUT_MASK; + pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); + pin_reg &= ~BIT(DB_TMR_LARGE_OFF); + } else if (debounce < 3900) { + time = debounce / 244; + pin_reg |= time & DB_TMR_OUT_MASK; + pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); + pin_reg &= ~BIT(DB_TMR_LARGE_OFF); + } else if (debounce < 250000) { + time = debounce / 15600; + pin_reg |= time & DB_TMR_OUT_MASK; + pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); + pin_reg |= BIT(DB_TMR_LARGE_OFF); + } else if (debounce < 1000000) { + time = debounce / 62500; + pin_reg |= time & DB_TMR_OUT_MASK; + pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); + pin_reg |= BIT(DB_TMR_LARGE_OFF); + } else { + pin_reg &= ~DB_CNTRl_MASK; + ret = -EINVAL; + } + } else { + pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); + pin_reg &= ~BIT(DB_TMR_LARGE_OFF); + pin_reg &= ~DB_TMR_OUT_MASK; + pin_reg &= ~DB_CNTRl_MASK; + } + writel(pin_reg, gpio_dev->base + offset * 4); + spin_unlock_irqrestore(&gpio_dev->lock, flags); + + return ret; +} + +#ifdef CONFIG_DEBUG_FS +static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) +{ + u32 pin_reg; + unsigned long flags; + unsigned int bank, i, pin_num; + struct amd_gpio *gpio_dev = to_amd_gpio(gc); + + char *level_trig; + char *active_level; + char *interrupt_enable; + char *interrupt_mask; + char *wake_cntrl0; + char *wake_cntrl1; + char *wake_cntrl2; + char *pin_sts; + char *pull_up_sel; + char *pull_up_enable; + char *pull_down_enable; + char *output_value; + char *output_enable; + + for (bank = 0; bank < AMD_GPIO_TOTAL_BANKS; bank++) { + seq_printf(s, "GPIO bank%d\t", bank); + + switch (bank) { + case 0: + i = 0; + pin_num = AMD_GPIO_PINS_BANK0; + break; + case 1: + i = 64; + pin_num = AMD_GPIO_PINS_BANK1 + i; + break; + case 2: + i = 128; + pin_num = AMD_GPIO_PINS_BANK2 + i; + break; + } + + for (; i < pin_num; i++) { + seq_printf(s, "pin%d\t", i); + spin_lock_irqsave(&gpio_dev->lock, flags); + pin_reg = readl(gpio_dev->base + i * 4); + spin_unlock_irqrestore(&gpio_dev->lock, flags); + + if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { + interrupt_enable = "interrupt is enabled|"; + + if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) + && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1))) + active_level = "Active low|"; + else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) + && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1))) + active_level = "Active high|"; + else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) + && pin_reg & BIT(ACTIVE_LEVEL_OFF+1)) + active_level = "Active on both|"; + else + active_level = "Unknow Active level|"; + + if (pin_reg & BIT(LEVEL_TRIG_OFF)) + level_trig = "Level trigger|"; + else + level_trig = "Edge trigger|"; + + } else { + interrupt_enable = + "interrupt is disabled|"; + active_level = " "; + level_trig = " "; + } + + if (pin_reg & BIT(INTERRUPT_MASK_OFF)) + interrupt_mask = + "interrupt is unmasked|"; + else + interrupt_mask = + "interrupt is masked|"; + + if (pin_reg & BIT(WAKE_CNTRL_OFF)) + wake_cntrl0 = "enable wakeup in S0i3 state|"; + else + wake_cntrl0 = "disable wakeup in S0i3 state|"; + + if (pin_reg & BIT(WAKE_CNTRL_OFF)) + wake_cntrl1 = "enable wakeup in S3 state|"; + else + wake_cntrl1 = "disable wakeup in S3 state|"; + + if (pin_reg & BIT(WAKE_CNTRL_OFF)) + wake_cntrl2 = "enable wakeup in S4/S5 state|"; + else + wake_cntrl2 = "disable wakeup in S4/S5 state|"; + + if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { + pull_up_enable = "pull-up is enabled|"; + if (pin_reg & BIT(PULL_UP_SEL_OFF)) + pull_up_sel = "8k pull-up|"; + else + pull_up_sel = "4k pull-up|"; + } else { + pull_up_enable = "pull-up is disabled|"; + pull_up_sel = " "; + } + + if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) + pull_down_enable = "pull-down is enabled|"; + else + pull_down_enable = "Pull-down is disabled|"; + + if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { + pin_sts = " "; + output_enable = "output is enabled|"; + if (pin_reg & BIT(OUTPUT_VALUE_OFF)) + output_value = "output is high|"; + else + output_value = "output is low|"; + } else { + output_enable = "output is disabled|"; + output_value = " "; + + if (pin_reg & BIT(PIN_STS_OFF)) + pin_sts = "input is high|"; + else + pin_sts = "input is low|"; + } + + seq_printf(s, "%s %s %s %s %s %s\n" + " %s %s %s %s %s %s %s 0x%x\n", + level_trig, active_level, interrupt_enable, + interrupt_mask, wake_cntrl0, wake_cntrl1, + wake_cntrl2, pin_sts, pull_up_sel, + pull_up_enable, pull_down_enable, + output_value, output_enable, pin_reg); + } + } +} +#else +#define amd_gpio_dbg_show NULL +#endif + +static void amd_gpio_irq_enable(struct irq_data *d) +{ + u32 pin_reg; + unsigned long flags; + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct amd_gpio *gpio_dev = to_amd_gpio(gc); + + spin_lock_irqsave(&gpio_dev->lock, flags); + pin_reg = readl(gpio_dev->base + (d->hwirq)*4); + /* + Suppose BIOS or Bootloader sets specific debounce for the + GPIO. if not, set debounce to be 2.75ms. + */ + if ((pin_reg & DB_TMR_OUT_MASK) == 0) { + pin_reg |= 0xf; + pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); + pin_reg &= ~BIT(DB_TMR_LARGE_OFF); + } + pin_reg |= BIT(INTERRUPT_ENABLE_OFF); + pin_reg |= BIT(INTERRUPT_MASK_OFF); + writel(pin_reg, gpio_dev->base + (d->hwirq)*4); + spin_unlock_irqrestore(&gpio_dev->lock, flags); +} + +static void amd_gpio_irq_disable(struct irq_data *d) +{ + u32 pin_reg; + unsigned long flags; + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct amd_gpio *gpio_dev = to_amd_gpio(gc); + + spin_lock_irqsave(&gpio_dev->lock, flags); + pin_reg = readl(gpio_dev->base + (d->hwirq)*4); + pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); + pin_reg &= ~BIT(INTERRUPT_MASK_OFF); + writel(pin_reg, gpio_dev->base + (d->hwirq)*4); + spin_unlock_irqrestore(&gpio_dev->lock, flags); +} + +static void amd_gpio_irq_mask(struct irq_data *d) +{ + u32 pin_reg; + unsigned long flags; + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct amd_gpio *gpio_dev = to_amd_gpio(gc); + + spin_lock_irqsave(&gpio_dev->lock, flags); + pin_reg = readl(gpio_dev->base + (d->hwirq)*4); + pin_reg &= ~BIT(INTERRUPT_MASK_OFF); + writel(pin_reg, gpio_dev->base + (d->hwirq)*4); + spin_unlock_irqrestore(&gpio_dev->lock, flags); +} + +static void amd_gpio_irq_unmask(struct irq_data *d) +{ + u32 pin_reg; + unsigned long flags; + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct amd_gpio *gpio_dev = to_amd_gpio(gc); + + spin_lock_irqsave(&gpio_dev->lock, flags); + pin_reg = readl(gpio_dev->base + (d->hwirq)*4); + pin_reg |= BIT(INTERRUPT_MASK_OFF); + writel(pin_reg, gpio_dev->base + (d->hwirq)*4); + spin_unlock_irqrestore(&gpio_dev->lock, flags); +} + +static void amd_gpio_irq_eoi(struct irq_data *d) +{ + u32 reg; + unsigned long flags; + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct amd_gpio *gpio_dev = to_amd_gpio(gc); + + spin_lock_irqsave(&gpio_dev->lock, flags); + reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); + reg |= EOI_MASK; + writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); + spin_unlock_irqrestore(&gpio_dev->lock, flags); +} + +static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) +{ + int ret = 0; + u32 pin_reg; + unsigned long flags; + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct amd_gpio *gpio_dev = to_amd_gpio(gc); + + spin_lock_irqsave(&gpio_dev->lock, flags); + pin_reg = readl(gpio_dev->base + (d->hwirq)*4); + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_RISING: + pin_reg &= ~BIT(LEVEL_TRIG_OFF); + pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); + pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; + pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; + __irq_set_handler_locked(d->irq, handle_edge_irq); + break; + + case IRQ_TYPE_EDGE_FALLING: + pin_reg &= ~BIT(LEVEL_TRIG_OFF); + pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); + pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; + pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; + __irq_set_handler_locked(d->irq, handle_edge_irq); + break; + + case IRQ_TYPE_EDGE_BOTH: + pin_reg &= ~BIT(LEVEL_TRIG_OFF); + pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); + pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; + pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; + __irq_set_handler_locked(d->irq, handle_edge_irq); + break; + + case IRQ_TYPE_LEVEL_HIGH: + pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; + pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); + pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; + pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); + pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF; + __irq_set_handler_locked(d->irq, handle_level_irq); + break; + + case IRQ_TYPE_LEVEL_LOW: + pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; + pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); + pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; + pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); + pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF; + __irq_set_handler_locked(d->irq, handle_level_irq); + break; + + case IRQ_TYPE_NONE: + break; + + default: + dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); + ret = -EINVAL; + } + + pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; + writel(pin_reg, gpio_dev->base + (d->hwirq)*4); + spin_unlock_irqrestore(&gpio_dev->lock, flags); + + return ret; +} + +static void amd_irq_ack(struct irq_data *d) +{ + /* + * based on HW design,there is no need to ack HW + * before handle current irq. But this routine is + * necessary for handle_edge_irq + */ +} + +static struct irq_chip amd_gpio_irqchip = { + .name = "amd_gpio", + .irq_ack = amd_irq_ack, + .irq_enable = amd_gpio_irq_enable, + .irq_disable = amd_gpio_irq_disable, + .irq_mask = amd_gpio_irq_mask, + .irq_unmask = amd_gpio_irq_unmask, + .irq_eoi = amd_gpio_irq_eoi, + .irq_set_type = amd_gpio_irq_set_type, +}; + +static void amd_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + u32 i; + u32 off; + u32 reg; + u32 pin_reg; + u64 reg64; + int handled = 0; + unsigned long flags; + struct irq_chip *chip = irq_get_chip(irq); + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct amd_gpio *gpio_dev = to_amd_gpio(gc); + + chained_irq_enter(chip, desc); + /*enable GPIO interrupt again*/ + spin_lock_irqsave(&gpio_dev->lock, flags); + reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); + reg64 = reg; + reg64 = reg64 << 32; + + reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0); + reg64 |= reg; + spin_unlock_irqrestore(&gpio_dev->lock, flags); + + /* + * first 46 bits indicates interrupt status. + * one bit represents four interrupt sources. + */ + for (off = 0; off < 46 ; off++) { + if (reg64 & BIT(off)) { + for (i = 0; i < 4; i++) { + pin_reg = readl(gpio_dev->base + + (off * 4 + i) * 4); + if ((pin_reg & BIT(INTERRUPT_STS_OFF)) || + (pin_reg & BIT(WAKE_STS_OFF))) { + irq = irq_find_mapping(gc->irqdomain, + off * 4 + i); + generic_handle_irq(irq); + writel(pin_reg, + gpio_dev->base + + (off * 4 + i) * 4); + handled++; + } + } + } + } + + if (handled == 0) + handle_bad_irq(irq, desc); + + spin_lock_irqsave(&gpio_dev->lock, flags); + reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); + reg |= EOI_MASK; + writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); + spin_unlock_irqrestore(&gpio_dev->lock, flags); + + chained_irq_exit(chip, desc); +} + +static int amd_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); + + return gpio_dev->ngroups; +} + +static const char *amd_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); + + return gpio_dev->groups[group].name; +} + +static int amd_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); + + *pins = gpio_dev->groups[group].pins; + *num_pins = gpio_dev->groups[group].npins; + return 0; +} + +static const struct pinctrl_ops amd_pinctrl_ops = { + .get_groups_count = amd_get_groups_count, + .get_group_name = amd_get_group_name, + .get_group_pins = amd_get_group_pins, +#ifdef CONFIG_OF + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinctrl_utils_dt_free_map, +#endif +}; + +static int amd_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *config) +{ + u32 pin_reg; + unsigned arg; + unsigned long flags; + struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + + spin_lock_irqsave(&gpio_dev->lock, flags); + pin_reg = readl(gpio_dev->base + pin*4); + spin_unlock_irqrestore(&gpio_dev->lock, flags); + switch (param) { + case PIN_CONFIG_INPUT_DEBOUNCE: + arg = pin_reg & DB_TMR_OUT_MASK; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); + break; + + case PIN_CONFIG_BIAS_PULL_UP: + arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; + break; + + default: + dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", + param); + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned num_configs) +{ + int i; + u32 arg; + int ret = 0; + u32 pin_reg; + unsigned long flags; + enum pin_config_param param; + struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); + + spin_lock_irqsave(&gpio_dev->lock, flags); + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + pin_reg = readl(gpio_dev->base + pin*4); + + switch (param) { + case PIN_CONFIG_INPUT_DEBOUNCE: + pin_reg &= ~DB_TMR_OUT_MASK; + pin_reg |= arg & DB_TMR_OUT_MASK; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); + pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; + break; + + case PIN_CONFIG_BIAS_PULL_UP: + pin_reg &= ~BIT(PULL_UP_SEL_OFF); + pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; + pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); + pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + pin_reg &= ~(DRV_STRENGTH_SEL_MASK + << DRV_STRENGTH_SEL_OFF); + pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) + << DRV_STRENGTH_SEL_OFF; + break; + + default: + dev_err(&gpio_dev->pdev->dev, + "Invalid config param %04x\n", param); + ret = -ENOTSUPP; + } + + writel(pin_reg, gpio_dev->base + pin*4); + } + spin_unlock_irqrestore(&gpio_dev->lock, flags); + + return ret; +} + +static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long *config) +{ + const unsigned *pins; + unsigned npins; + int ret; + + ret = amd_get_group_pins(pctldev, group, &pins, &npins); + if (ret) + return ret; + + if (amd_pinconf_get(pctldev, pins[0], config)) + return -ENOTSUPP; + + return 0; +} + +static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned group, unsigned long *configs, + unsigned num_configs) +{ + const unsigned *pins; + unsigned npins; + int i, ret; + + ret = amd_get_group_pins(pctldev, group, &pins, &npins); + if (ret) + return ret; + for (i = 0; i < npins; i++) { + if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) + return -ENOTSUPP; + } + return 0; +} + +static const struct pinconf_ops amd_pinconf_ops = { + .pin_config_get = amd_pinconf_get, + .pin_config_set = amd_pinconf_set, + .pin_config_group_get = amd_pinconf_group_get, + .pin_config_group_set = amd_pinconf_group_set, +}; + +static struct pinctrl_desc amd_pinctrl_desc = { + .pins = kerncz_pins, + .npins = ARRAY_SIZE(kerncz_pins), + .pctlops = &amd_pinctrl_ops, + .confops = &amd_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int amd_gpio_probe(struct platform_device *pdev) +{ + int ret = 0; + int irq_base; + struct resource *res; + struct amd_gpio *gpio_dev; + + gpio_dev = devm_kzalloc(&pdev->dev, + sizeof(struct amd_gpio), GFP_KERNEL); + if (!gpio_dev) + return -ENOMEM; + + spin_lock_init(&gpio_dev->lock); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); + return -EINVAL; + } + + gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start, + resource_size(res)); + if (IS_ERR(gpio_dev->base)) + return PTR_ERR(gpio_dev->base); + + irq_base = platform_get_irq(pdev, 0); + if (irq_base < 0) { + dev_err(&pdev->dev, "Failed to get gpio IRQ.\n"); + return -EINVAL; + } + + gpio_dev->pdev = pdev; + gpio_dev->gc.direction_input = amd_gpio_direction_input; + gpio_dev->gc.direction_output = amd_gpio_direction_output; + gpio_dev->gc.get = amd_gpio_get_value; + gpio_dev->gc.set = amd_gpio_set_value; + gpio_dev->gc.set_debounce = amd_gpio_set_debounce; + gpio_dev->gc.dbg_show = amd_gpio_dbg_show; + + gpio_dev->gc.base = 0; + gpio_dev->gc.label = pdev->name; + gpio_dev->gc.owner = THIS_MODULE; + gpio_dev->gc.dev = &pdev->dev; + gpio_dev->gc.ngpio = TOTAL_NUMBER_OF_PINS; +#if defined(CONFIG_OF_GPIO) + gpio_dev->gc.of_node = pdev->dev.of_node; +#endif + + gpio_dev->groups = kerncz_groups; + gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); + + amd_pinctrl_desc.name = dev_name(&pdev->dev); + gpio_dev->pctrl = pinctrl_register(&amd_pinctrl_desc, + &pdev->dev, gpio_dev); + if (!gpio_dev->pctrl) { + dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); + return -ENODEV; + } + + ret = gpiochip_add(&gpio_dev->gc); + if (ret) + goto out1; + + ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), + 0, 0, TOTAL_NUMBER_OF_PINS); + if (ret) { + dev_err(&pdev->dev, "Failed to add pin range\n"); + goto out2; + } + + ret = gpiochip_irqchip_add(&gpio_dev->gc, + &amd_gpio_irqchip, + 0, + handle_simple_irq, + IRQ_TYPE_NONE); + if (ret) { + dev_err(&pdev->dev, "could not add irqchip\n"); + ret = -ENODEV; + goto out2; + } + + gpiochip_set_chained_irqchip(&gpio_dev->gc, + &amd_gpio_irqchip, + irq_base, + amd_gpio_irq_handler); + + platform_set_drvdata(pdev, gpio_dev); + + dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); + return ret; + +out2: + gpiochip_remove(&gpio_dev->gc); + +out1: + pinctrl_unregister(gpio_dev->pctrl); + return ret; +} + +static int amd_gpio_remove(struct platform_device *pdev) +{ + struct amd_gpio *gpio_dev; + + gpio_dev = platform_get_drvdata(pdev); + + gpiochip_remove(&gpio_dev->gc); + pinctrl_unregister(gpio_dev->pctrl); + + return 0; +} + +static const struct acpi_device_id amd_gpio_acpi_match[] = { + { "AMD0030", 0 }, + { }, +}; +MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); + +static struct platform_driver amd_gpio_driver = { + .driver = { + .name = "amd_gpio", + .owner = THIS_MODULE, + .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), + }, + .probe = amd_gpio_probe, + .remove = amd_gpio_remove, +}; + +module_platform_driver(amd_gpio_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); +MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h new file mode 100644 index 000000000000..7bfea47dbb47 --- /dev/null +++ b/drivers/pinctrl/pinctrl-amd.h @@ -0,0 +1,261 @@ +/* + * GPIO driver for AMD + * + * Copyright (c) 2014,2015 Ken Xue <Ken.Xue@amd.com> + * Jeff Wu <Jeff.Wu@amd.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + */ + +#ifndef _PINCTRL_AMD_H +#define _PINCTRL_AMD_H + +#define TOTAL_NUMBER_OF_PINS 192 +#define AMD_GPIO_PINS_PER_BANK 64 +#define AMD_GPIO_TOTAL_BANKS 3 + +#define AMD_GPIO_PINS_BANK0 63 +#define AMD_GPIO_PINS_BANK1 64 +#define AMD_GPIO_PINS_BANK2 56 + +#define WAKE_INT_MASTER_REG 0xfc +#define EOI_MASK (1 << 29) + +#define WAKE_INT_STATUS_REG0 0x2f8 +#define WAKE_INT_STATUS_REG1 0x2fc + +#define DB_TMR_OUT_OFF 0 +#define DB_TMR_OUT_UNIT_OFF 4 +#define DB_CNTRL_OFF 5 +#define DB_TMR_LARGE_OFF 7 +#define LEVEL_TRIG_OFF 8 +#define ACTIVE_LEVEL_OFF 9 +#define INTERRUPT_ENABLE_OFF 11 +#define INTERRUPT_MASK_OFF 12 +#define WAKE_CNTRL_OFF 13 +#define PIN_STS_OFF 16 +#define DRV_STRENGTH_SEL_OFF 17 +#define PULL_UP_SEL_OFF 19 +#define PULL_UP_ENABLE_OFF 20 +#define PULL_DOWN_ENABLE_OFF 21 +#define OUTPUT_VALUE_OFF 22 +#define OUTPUT_ENABLE_OFF 23 +#define SW_CNTRL_IN_OFF 24 +#define SW_CNTRL_EN_OFF 25 +#define INTERRUPT_STS_OFF 28 +#define WAKE_STS_OFF 29 + +#define DB_TMR_OUT_MASK 0xFUL +#define DB_CNTRl_MASK 0x3UL +#define ACTIVE_LEVEL_MASK 0x3UL +#define DRV_STRENGTH_SEL_MASK 0x3UL + +#define DB_TYPE_NO_DEBOUNCE 0x0UL +#define DB_TYPE_PRESERVE_LOW_GLITCH 0x1UL +#define DB_TYPE_PRESERVE_HIGH_GLITCH 0x2UL +#define DB_TYPE_REMOVE_GLITCH 0x3UL + +#define EDGE_TRAGGER 0x0UL +#define LEVEL_TRIGGER 0x1UL + +#define ACTIVE_HIGH 0x0UL +#define ACTIVE_LOW 0x1UL +#define BOTH_EADGE 0x2UL + +#define ENABLE_INTERRUPT 0x1UL +#define DISABLE_INTERRUPT 0x0UL + +#define ENABLE_INTERRUPT_MASK 0x0UL +#define DISABLE_INTERRUPT_MASK 0x1UL + +#define CLR_INTR_STAT 0x1UL + +struct amd_pingroup { + const char *name; + const unsigned *pins; + unsigned npins; +}; + +struct amd_function { + const char *name; + const char * const *groups; + unsigned ngroups; +}; + +struct amd_gpio { + spinlock_t lock; + void __iomem *base; + + const struct amd_pingroup *groups; + u32 ngroups; + struct pinctrl_dev *pctrl; + struct gpio_chip gc; + struct resource *res; + struct platform_device *pdev; +}; + +/* KERNCZ configuration*/ +static const struct pinctrl_pin_desc kerncz_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(43, "GPIO_42"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), +}; + +static const unsigned i2c0_pins[] = {145, 146}; +static const unsigned i2c1_pins[] = {147, 148}; +static const unsigned i2c2_pins[] = {113, 114}; +static const unsigned i2c3_pins[] = {19, 20}; + +static const unsigned uart0_pins[] = {135, 136, 137, 138, 139}; +static const unsigned uart1_pins[] = {140, 141, 142, 143, 144}; + +static const struct amd_pingroup kerncz_groups[] = { + { + .name = "i2c0", + .pins = i2c0_pins, + .npins = 2, + }, + { + .name = "i2c1", + .pins = i2c1_pins, + .npins = 2, + }, + { + .name = "i2c2", + .pins = i2c2_pins, + .npins = 2, + }, + { + .name = "i2c3", + .pins = i2c3_pins, + .npins = 2, + }, + { + .name = "uart0", + .pins = uart0_pins, + .npins = 9, + }, + { + .name = "uart1", + .pins = uart1_pins, + .npins = 5, + }, +}; + +#endif diff --git a/drivers/pinctrl/pinctrl-as3722.c b/drivers/pinctrl/pinctrl-as3722.c index 169b1bfa00c8..db0571ffbe99 100644 --- a/drivers/pinctrl/pinctrl-as3722.c +++ b/drivers/pinctrl/pinctrl-as3722.c @@ -625,7 +625,7 @@ static int as3722_pinctrl_remove(struct platform_device *pdev) return 0; } -static struct of_device_id as3722_pinctrl_of_match[] = { +static const struct of_device_id as3722_pinctrl_of_match[] = { { .compatible = "ams,as3722-pinctrl", }, { }, }; diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index a4814066ea08..2f797cb7e205 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -451,18 +451,18 @@ static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin) { - return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1; + return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1; } static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) { - __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); + writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); } static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin) { - if ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) - return !((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1); + if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) + return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1); return false; } @@ -470,55 +470,55 @@ static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin) static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) { if (is_on) - __raw_writel(mask, pio + PIO_IFSCDR); + writel_relaxed(mask, pio + PIO_IFSCDR); at91_mux_set_deglitch(pio, mask, is_on); } static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div) { - *div = __raw_readl(pio + PIO_SCDR); + *div = readl_relaxed(pio + PIO_SCDR); - return ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) && - ((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1); + return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) && + ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1); } static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, bool is_on, u32 div) { if (is_on) { - __raw_writel(mask, pio + PIO_IFSCER); - __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR); - __raw_writel(mask, pio + PIO_IFER); + writel_relaxed(mask, pio + PIO_IFSCER); + writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR); + writel_relaxed(mask, pio + PIO_IFER); } else - __raw_writel(mask, pio + PIO_IFSCDR); + writel_relaxed(mask, pio + PIO_IFSCDR); } static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) { - return !((__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1); + return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1); } static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) { if (is_on) - __raw_writel(mask, pio + PIO_PUDR); + writel_relaxed(mask, pio + PIO_PUDR); - __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); + writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); } static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) { - __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); + writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); } static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin) { - return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1; + return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1; } static inline u32 read_drive_strength(void __iomem *reg, unsigned pin) { - unsigned tmp = __raw_readl(reg); + unsigned tmp = readl_relaxed(reg); tmp = tmp >> two_bit_pin_value_shift_amount(pin); @@ -554,13 +554,13 @@ static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio, static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength) { - unsigned tmp = __raw_readl(reg); + unsigned tmp = readl_relaxed(reg); unsigned shift = two_bit_pin_value_shift_amount(pin); tmp &= ~(DRIVE_STRENGTH_MASK << shift); tmp |= strength << shift; - __raw_writel(tmp, reg); + writel_relaxed(tmp, reg); } static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin, @@ -1114,7 +1114,7 @@ static int at91_pinctrl_parse_functions(struct device_node *np, return 0; } -static struct of_device_id at91_pinctrl_of_match[] = { +static const struct of_device_id at91_pinctrl_of_match[] = { { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops }, { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops }, { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops }, @@ -1240,8 +1240,7 @@ static int at91_pinctrl_probe(struct platform_device *pdev) if (!info->pctl) { dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n"); - ret = -EINVAL; - goto err; + return -EINVAL; } /* We will handle a range of GPIO pins */ @@ -1252,9 +1251,6 @@ static int at91_pinctrl_probe(struct platform_device *pdev) dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n"); return 0; - -err: - return ret; } static int at91_pinctrl_remove(struct platform_device *pdev) @@ -1535,9 +1531,9 @@ void at91_pinctrl_gpio_suspend(void) pio = gpio_chips[i]->regbase; - backups[i] = __raw_readl(pio + PIO_IMR); - __raw_writel(backups[i], pio + PIO_IDR); - __raw_writel(wakeups[i], pio + PIO_IER); + backups[i] = readl_relaxed(pio + PIO_IMR); + writel_relaxed(backups[i], pio + PIO_IDR); + writel_relaxed(wakeups[i], pio + PIO_IER); if (!wakeups[i]) clk_disable_unprepare(gpio_chips[i]->clock); @@ -1562,8 +1558,8 @@ void at91_pinctrl_gpio_resume(void) if (!wakeups[i]) clk_prepare_enable(gpio_chips[i]->clock); - __raw_writel(wakeups[i], pio + PIO_IDR); - __raw_writel(backups[i], pio + PIO_IER); + writel_relaxed(wakeups[i], pio + PIO_IDR); + writel_relaxed(backups[i], pio + PIO_IER); } } @@ -1694,7 +1690,7 @@ static struct gpio_chip at91_gpio_template = { .ngpio = MAX_NB_GPIO_PER_BANK, }; -static struct of_device_id at91_gpio_of_match[] = { +static const struct of_device_id at91_gpio_of_match[] = { { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, }, { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops }, { /* sentinel */ } diff --git a/drivers/pinctrl/pinctrl-lantiq.h b/drivers/pinctrl/pinctrl-lantiq.h index c7cfad5527d7..eb89ba045228 100644 --- a/drivers/pinctrl/pinctrl-lantiq.h +++ b/drivers/pinctrl/pinctrl-lantiq.h @@ -193,4 +193,4 @@ enum ltq_pin { extern int ltq_pinctrl_register(struct platform_device *pdev, struct ltq_pinmux_info *info); extern int ltq_pinctrl_unregister(struct platform_device *pdev); -#endif /* __PINCTRL_PXA3XX_H */ +#endif /* __PINCTRL_LANTIQ_H */ diff --git a/drivers/pinctrl/pinctrl-palmas.c b/drivers/pinctrl/pinctrl-palmas.c index 26461e30f0ae..2631df0504bd 100644 --- a/drivers/pinctrl/pinctrl-palmas.c +++ b/drivers/pinctrl/pinctrl-palmas.c @@ -987,7 +987,7 @@ static struct palmas_pinctrl_data tps80036_pinctrl_data = { .num_pin_groups = ARRAY_SIZE(tps80036_pingroups), }; -static struct of_device_id palmas_pinctrl_of_match[] = { +static const struct of_device_id palmas_pinctrl_of_match[] = { { .compatible = "ti,palmas-pinctrl", .data = &tps65913_pinctrl_data}, { .compatible = "ti,tps65913-pinctrl", .data = &tps65913_pinctrl_data}, { .compatible = "ti,tps80036-pinctrl", .data = &tps80036_pinctrl_data}, diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 69e84427f913..13b45f297727 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1501,7 +1501,7 @@ static void pcs_free_resources(struct pcs_device *pcs) } \ } while (0); -static struct of_device_id pcs_of_match[]; +static const struct of_device_id pcs_of_match[]; static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs) { @@ -2000,7 +2000,7 @@ static const struct pcs_soc_data pinconf_single = { .flags = PCS_FEAT_PINCONF, }; -static struct of_device_id pcs_of_match[] = { +static const struct of_device_id pcs_of_match[] = { { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup }, { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup }, { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup }, diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 9e5ec00084bb..65bf73b70e34 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -206,6 +206,8 @@ #define gpio_chip_to_bank(chip) \ container_of(chip, struct st_gpio_bank, gpio_chip) +#define pc_to_bank(pc) \ + container_of(pc, struct st_gpio_bank, pc) enum st_retime_style { st_retime_style_none, @@ -398,6 +400,16 @@ static const struct st_pctl_data stih407_flashdata = { .rt = 100, }; +static struct st_pio_control *st_get_pio_control( + struct pinctrl_dev *pctldev, int pin) +{ + struct pinctrl_gpio_range *range = + pinctrl_find_gpio_range_from_pin(pctldev, pin); + struct st_gpio_bank *bank = gpio_range_to_bank(range); + + return &bank->pc; +} + /* Low level functions.. */ static inline int st_gpio_bank(int gpio) { @@ -460,6 +472,20 @@ static void st_pctl_set_function(struct st_pio_control *pc, regmap_field_write(alt, val); } +static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin) +{ + struct regmap_field *alt = pc->alt; + unsigned int val; + int offset = pin * 4; + + if (!alt) + return 0; + + regmap_field_read(alt, &val); + + return (val >> offset) & 0xf; +} + static unsigned long st_pinconf_delay_to_bit(unsigned int delay, const struct st_pctl_data *data, unsigned long config) { @@ -757,6 +783,35 @@ static int st_gpio_direction_output(struct gpio_chip *chip, return 0; } +static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset) +{ + struct st_gpio_bank *bank = gpio_chip_to_bank(chip); + struct st_pio_control pc = bank->pc; + unsigned long config; + unsigned int direction = 0; + unsigned int function; + unsigned int value; + int i = 0; + + /* Alternate function direction is handled by Pinctrl */ + function = st_pctl_get_pin_function(&pc, offset); + if (function) { + st_pinconf_get_direction(&pc, offset, &config); + return !ST_PINCONF_UNPACK_OE(config); + } + + /* + * GPIO direction is handled differently + * - See st_gpio_direction() above for an explanation + */ + for (i = 0; i <= 2; i++) { + value = readl(bank->base + REG_PIO_PC(i)); + direction |= ((value >> offset) & 0x1) << i; + } + + return (direction == ST_GPIO_DIRECTION_IN); +} + static int st_gpio_xlate(struct gpio_chip *gc, const struct of_phandle_args *gpiospec, u32 *flags) { @@ -904,16 +959,6 @@ static int st_pmx_get_groups(struct pinctrl_dev *pctldev, return 0; } -static struct st_pio_control *st_get_pio_control( - struct pinctrl_dev *pctldev, int pin) -{ - struct pinctrl_gpio_range *range = - pinctrl_find_gpio_range_from_pin(pctldev, pin); - struct st_gpio_bank *bank = gpio_range_to_bank(range); - - return &bank->pc; -} - static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector, unsigned group) { @@ -1011,17 +1056,30 @@ static int st_pinconf_get(struct pinctrl_dev *pctldev, static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned pin_id) { + struct st_pio_control *pc; unsigned long config; + unsigned int function; + int offset = st_gpio_pin(pin_id); + char f[16]; mutex_unlock(&pctldev->mutex); + pc = st_get_pio_control(pctldev, pin_id); st_pinconf_get(pctldev, pin_id, &config); mutex_lock(&pctldev->mutex); - seq_printf(s, "[OE:%ld,PU:%ld,OD:%ld]\n" + + function = st_pctl_get_pin_function(pc, offset); + if (function) + snprintf(f, 10, "Alt Fn %d", function); + else + snprintf(f, 5, "GPIO"); + + seq_printf(s, "[OE:%d,PU:%ld,OD:%ld]\t%s\n" "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld," "de:%ld,rt-clk:%ld,rt-delay:%ld]", - ST_PINCONF_UNPACK_OE(config), + !st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset), ST_PINCONF_UNPACK_PU(config), ST_PINCONF_UNPACK_OD(config), + f, ST_PINCONF_UNPACK_RT(config), ST_PINCONF_UNPACK_RT_INVERTCLK(config), ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), @@ -1438,6 +1496,7 @@ static struct gpio_chip st_gpio_template = { .set = st_gpio_set, .direction_input = st_gpio_direction_input, .direction_output = st_gpio_direction_output, + .get_direction = st_gpio_get_direction, .ngpio = ST_GPIO_PINS_PER_BANK, .of_gpio_n_cells = 1, .of_xlate = st_gpio_xlate, @@ -1531,7 +1590,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, return 0; } -static struct of_device_id st_pctl_of_match[] = { +static const struct of_device_id st_pctl_of_match[] = { { .compatible = "st,stih415-sbc-pinctrl", .data = &stih415_sbc_data }, { .compatible = "st,stih415-rear-pinctrl", .data = &stih415_rear_data }, { .compatible = "st,stih415-left-pinctrl", .data = &stih415_left_data }, diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c index e5949d51bc52..4c95c2024a1c 100644 --- a/drivers/pinctrl/pinctrl-tegra.c +++ b/drivers/pinctrl/pinctrl-tegra.c @@ -103,6 +103,7 @@ static const struct cfg_param { {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK}, {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET}, {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL}, + {"nvidia,io-hv", TEGRA_PINCONF_PARAM_RCV_SEL}, {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE}, {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT}, {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE}, @@ -348,14 +349,24 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx, *width = 1; break; case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE: - *bank = g->drv_bank; - *reg = g->drv_reg; + if (pmx->soc->hsm_in_mux) { + *bank = g->mux_bank; + *reg = g->mux_reg; + } else { + *bank = g->drv_bank; + *reg = g->drv_reg; + } *bit = g->hsm_bit; *width = 1; break; case TEGRA_PINCONF_PARAM_SCHMITT: - *bank = g->drv_bank; - *reg = g->drv_reg; + if (pmx->soc->schmitt_in_mux) { + *bank = g->mux_bank; + *reg = g->mux_reg; + } else { + *bank = g->drv_bank; + *reg = g->drv_reg; + } *bit = g->schmitt_bit; *width = 1; break; @@ -390,8 +401,13 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx, *width = g->slwr_width; break; case TEGRA_PINCONF_PARAM_DRIVE_TYPE: - *bank = g->drv_bank; - *reg = g->drv_reg; + if (pmx->soc->drvtype_in_mux) { + *bank = g->mux_bank; + *reg = g->mux_reg; + } else { + *bank = g->drv_bank; + *reg = g->drv_reg; + } *bit = g->drvtype_bit; *width = 2; break; diff --git a/drivers/pinctrl/pinctrl-tegra.h b/drivers/pinctrl/pinctrl-tegra.h index 8d94d1332e7b..1615db7e3a4b 100644 --- a/drivers/pinctrl/pinctrl-tegra.h +++ b/drivers/pinctrl/pinctrl-tegra.h @@ -139,26 +139,26 @@ struct tegra_pingroup { u32 pupd_bank:2; u32 tri_bank:2; u32 drv_bank:2; - u32 mux_bit:6; - u32 pupd_bit:6; - u32 tri_bit:6; - u32 einput_bit:6; - u32 odrain_bit:6; - u32 lock_bit:6; - u32 ioreset_bit:6; - u32 rcv_sel_bit:6; - u32 hsm_bit:6; - u32 schmitt_bit:6; - u32 lpmd_bit:6; - u32 drvdn_bit:6; - u32 drvup_bit:6; - u32 slwr_bit:6; - u32 slwf_bit:6; - u32 drvtype_bit:6; - u32 drvdn_width:6; - u32 drvup_width:6; - u32 slwr_width:6; - u32 slwf_width:6; + s32 mux_bit:6; + s32 pupd_bit:6; + s32 tri_bit:6; + s32 einput_bit:6; + s32 odrain_bit:6; + s32 lock_bit:6; + s32 ioreset_bit:6; + s32 rcv_sel_bit:6; + s32 hsm_bit:6; + s32 schmitt_bit:6; + s32 lpmd_bit:6; + s32 drvdn_bit:6; + s32 drvup_bit:6; + s32 slwr_bit:6; + s32 slwf_bit:6; + s32 drvtype_bit:6; + s32 drvdn_width:6; + s32 drvup_width:6; + s32 slwr_width:6; + s32 slwf_width:6; }; /** @@ -182,6 +182,9 @@ struct tegra_pinctrl_soc_data { unsigned nfunctions; const struct tegra_pingroup *groups; unsigned ngroups; + bool hsm_in_mux; + bool schmitt_in_mux; + bool drvtype_in_mux; }; int tegra_pinctrl_probe(struct platform_device *pdev, diff --git a/drivers/pinctrl/pinctrl-tegra114.c b/drivers/pinctrl/pinctrl-tegra114.c index 52e4ec6386b4..05e49d5137ab 100644 --- a/drivers/pinctrl/pinctrl-tegra114.c +++ b/drivers/pinctrl/pinctrl-tegra114.c @@ -1547,6 +1547,7 @@ static struct tegra_function tegra114_functions[] = { #define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ #define PINGROUP_REG_A 0x3000 /* bank 1 */ +#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A) #define PINGROUP_REG(r) ((r) - PINGROUP_REG_A) #define PINGROUP_BIT_Y(b) (b) @@ -1572,20 +1573,17 @@ static struct tegra_function tegra114_functions[] = { .tri_reg = PINGROUP_REG(r), \ .tri_bank = 1, \ .tri_bit = 4, \ - .einput_bit = PINGROUP_BIT_Y(5), \ + .einput_bit = 5, \ .odrain_bit = PINGROUP_BIT_##od(6), \ - .lock_bit = PINGROUP_BIT_Y(7), \ + .lock_bit = 7, \ .ioreset_bit = PINGROUP_BIT_##ior(8), \ .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \ .drv_reg = -1, \ } -#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A) - -#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ - drvdn_b, drvdn_w, drvup_b, drvup_w, \ - slwr_b, slwr_w, slwf_b, slwf_w, \ - drvtype) \ +#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \ + drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \ + slwf_b, slwf_w, drvtype) \ { \ .name = "drive_" #pg_name, \ .pins = drive_##pg_name##_pins, \ @@ -1843,6 +1841,9 @@ static const struct tegra_pinctrl_soc_data tegra114_pinctrl = { .nfunctions = ARRAY_SIZE(tegra114_functions), .groups = tegra114_groups, .ngroups = ARRAY_SIZE(tegra114_groups), + .hsm_in_mux = false, + .schmitt_in_mux = false, + .drvtype_in_mux = false, }; static int tegra114_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/pinctrl-tegra124.c index 2b20906c5356..7cd44c7c296d 100644 --- a/drivers/pinctrl/pinctrl-tegra124.c +++ b/drivers/pinctrl/pinctrl-tegra124.c @@ -1536,6 +1536,7 @@ enum tegra_mux { TEGRA_MUX_CLK, TEGRA_MUX_CLK12, TEGRA_MUX_CPU, + TEGRA_MUX_CSI, TEGRA_MUX_DAP, TEGRA_MUX_DAP1, TEGRA_MUX_DAP2, @@ -1544,6 +1545,7 @@ enum tegra_mux { TEGRA_MUX_DISPLAYA_ALT, TEGRA_MUX_DISPLAYB, TEGRA_MUX_DP, + TEGRA_MUX_DSI_B, TEGRA_MUX_DTV, TEGRA_MUX_EXTPERIPH1, TEGRA_MUX_EXTPERIPH2, @@ -1613,8 +1615,6 @@ enum tegra_mux { TEGRA_MUX_VI_ALT3, TEGRA_MUX_VIMCLK2, TEGRA_MUX_VIMCLK2_ALT, - TEGRA_MUX_CSI, - TEGRA_MUX_DSI_B, }; #define FUNCTION(fname) \ @@ -1630,6 +1630,7 @@ static struct tegra_function tegra124_functions[] = { FUNCTION(clk), FUNCTION(clk12), FUNCTION(cpu), + FUNCTION(csi), FUNCTION(dap), FUNCTION(dap1), FUNCTION(dap2), @@ -1638,6 +1639,7 @@ static struct tegra_function tegra124_functions[] = { FUNCTION(displaya_alt), FUNCTION(displayb), FUNCTION(dp), + FUNCTION(dsi_b), FUNCTION(dtv), FUNCTION(extperiph1), FUNCTION(extperiph2), @@ -1707,15 +1709,15 @@ static struct tegra_function tegra124_functions[] = { FUNCTION(vi_alt3), FUNCTION(vimclk2), FUNCTION(vimclk2_alt), - FUNCTION(csi), - FUNCTION(dsi_b), }; #define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ #define PINGROUP_REG_A 0x3000 /* bank 1 */ #define MIPI_PAD_CTRL_PINGROUP_REG_A 0x820 /* bank 2 */ +#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A) #define PINGROUP_REG(r) ((r) - PINGROUP_REG_A) +#define MIPI_PAD_CTRL_PINGROUP_REG_Y(r) ((r) - MIPI_PAD_CTRL_PINGROUP_REG_A) #define PINGROUP_BIT_Y(b) (b) #define PINGROUP_BIT_N(b) (-1) @@ -1740,20 +1742,17 @@ static struct tegra_function tegra124_functions[] = { .tri_reg = PINGROUP_REG(r), \ .tri_bank = 1, \ .tri_bit = 4, \ - .einput_bit = PINGROUP_BIT_Y(5), \ + .einput_bit = 5, \ .odrain_bit = PINGROUP_BIT_##od(6), \ - .lock_bit = PINGROUP_BIT_Y(7), \ + .lock_bit = 7, \ .ioreset_bit = PINGROUP_BIT_##ior(8), \ .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \ .drv_reg = -1, \ } -#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A) - -#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ - drvdn_b, drvdn_w, drvup_b, drvup_w, \ - slwr_b, slwr_w, slwf_b, slwf_w, \ - drvtype) \ +#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \ + drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \ + slwf_b, slwf_w, drvtype) \ { \ .name = "drive_" #pg_name, \ .pins = drive_##pg_name##_pins, \ @@ -1782,8 +1781,6 @@ static struct tegra_function tegra124_functions[] = { .drvtype_bit = PINGROUP_BIT_##drvtype(6), \ } -#define MIPI_PAD_CTRL_PINGROUP_REG_Y(r) ((r) - MIPI_PAD_CTRL_PINGROUP_REG_A) - #define MIPI_PAD_CTRL_PINGROUP(pg_name, r, b, f0, f1) \ { \ .name = "mipi_pad_ctrl_" #pg_name, \ @@ -2044,8 +2041,8 @@ static const struct tegra_pingroup tegra124_groups[] = { DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), - /* pg_name, r b f0, f1 */ - MIPI_PAD_CTRL_PINGROUP(dsi_b, 0x820, 1, CSI, DSI_B) + /* pg_name, r, b, f0, f1 */ + MIPI_PAD_CTRL_PINGROUP(dsi_b, 0x820, 1, CSI, DSI_B), }; static const struct tegra_pinctrl_soc_data tegra124_pinctrl = { @@ -2056,6 +2053,9 @@ static const struct tegra_pinctrl_soc_data tegra124_pinctrl = { .nfunctions = ARRAY_SIZE(tegra124_functions), .groups = tegra124_groups, .ngroups = ARRAY_SIZE(tegra124_groups), + .hsm_in_mux = false, + .schmitt_in_mux = false, + .drvtype_in_mux = false, }; static int tegra124_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/pinctrl-tegra20.c index d3a5722e4acb..4833db4433d9 100644 --- a/drivers/pinctrl/pinctrl-tegra20.c +++ b/drivers/pinctrl/pinctrl-tegra20.c @@ -2221,6 +2221,9 @@ static const struct tegra_pinctrl_soc_data tegra20_pinctrl = { .nfunctions = ARRAY_SIZE(tegra20_functions), .groups = tegra20_groups, .ngroups = ARRAY_SIZE(tegra20_groups), + .hsm_in_mux = false, + .schmitt_in_mux = false, + .drvtype_in_mux = false, }; static int tegra20_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/pinctrl-tegra210.c b/drivers/pinctrl/pinctrl-tegra210.c new file mode 100644 index 000000000000..252b464901c0 --- /dev/null +++ b/drivers/pinctrl/pinctrl-tegra210.c @@ -0,0 +1,1588 @@ +/* + * Pinctrl data for the NVIDIA Tegra210 pinmux + * + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + +#include "pinctrl-tegra.h" + +/* + * Most pins affected by the pinmux can also be GPIOs. Define these first. + * These must match how the GPIO driver names/numbers its pins. + */ +#define _GPIO(offset) (offset) + +#define TEGRA_PIN_PEX_L0_RST_N_PA0 _GPIO(0) +#define TEGRA_PIN_PEX_L0_CLKREQ_N_PA1 _GPIO(1) +#define TEGRA_PIN_PEX_WAKE_N_PA2 _GPIO(2) +#define TEGRA_PIN_PEX_L1_RST_N_PA3 _GPIO(3) +#define TEGRA_PIN_PEX_L1_CLKREQ_N_PA4 _GPIO(4) +#define TEGRA_PIN_SATA_LED_ACTIVE_PA5 _GPIO(5) +#define TEGRA_PIN_PA6 _GPIO(6) +#define TEGRA_PIN_DAP1_FS_PB0 _GPIO(8) +#define TEGRA_PIN_DAP1_DIN_PB1 _GPIO(9) +#define TEGRA_PIN_DAP1_DOUT_PB2 _GPIO(10) +#define TEGRA_PIN_DAP1_SCLK_PB3 _GPIO(11) +#define TEGRA_PIN_SPI2_MOSI_PB4 _GPIO(12) +#define TEGRA_PIN_SPI2_MISO_PB5 _GPIO(13) +#define TEGRA_PIN_SPI2_SCK_PB6 _GPIO(14) +#define TEGRA_PIN_SPI2_CS0_PB7 _GPIO(15) +#define TEGRA_PIN_SPI1_MOSI_PC0 _GPIO(16) +#define TEGRA_PIN_SPI1_MISO_PC1 _GPIO(17) +#define TEGRA_PIN_SPI1_SCK_PC2 _GPIO(18) +#define TEGRA_PIN_SPI1_CS0_PC3 _GPIO(19) +#define TEGRA_PIN_SPI1_CS1_PC4 _GPIO(20) +#define TEGRA_PIN_SPI4_SCK_PC5 _GPIO(21) +#define TEGRA_PIN_SPI4_CS0_PC6 _GPIO(22) +#define TEGRA_PIN_SPI4_MOSI_PC7 _GPIO(23) +#define TEGRA_PIN_SPI4_MISO_PD0 _GPIO(24) +#define TEGRA_PIN_UART3_TX_PD1 _GPIO(25) +#define TEGRA_PIN_UART3_RX_PD2 _GPIO(26) +#define TEGRA_PIN_UART3_RTS_PD3 _GPIO(27) +#define TEGRA_PIN_UART3_CTS_PD4 _GPIO(28) +#define TEGRA_PIN_DMIC1_CLK_PE0 _GPIO(32) +#define TEGRA_PIN_DMIC1_DAT_PE1 _GPIO(33) +#define TEGRA_PIN_DMIC2_CLK_PE2 _GPIO(34) +#define TEGRA_PIN_DMIC2_DAT_PE3 _GPIO(35) +#define TEGRA_PIN_DMIC3_CLK_PE4 _GPIO(36) +#define TEGRA_PIN_DMIC3_DAT_PE5 _GPIO(37) +#define TEGRA_PIN_PE6 _GPIO(38) +#define TEGRA_PIN_PE7 _GPIO(39) +#define TEGRA_PIN_GEN3_I2C_SCL_PF0 _GPIO(40) +#define TEGRA_PIN_GEN3_I2C_SDA_PF1 _GPIO(41) +#define TEGRA_PIN_UART2_TX_PG0 _GPIO(48) +#define TEGRA_PIN_UART2_RX_PG1 _GPIO(49) +#define TEGRA_PIN_UART2_RTS_PG2 _GPIO(50) +#define TEGRA_PIN_UART2_CTS_PG3 _GPIO(51) +#define TEGRA_PIN_WIFI_EN_PH0 _GPIO(56) +#define TEGRA_PIN_WIFI_RST_PH1 _GPIO(57) +#define TEGRA_PIN_WIFI_WAKE_AP_PH2 _GPIO(58) +#define TEGRA_PIN_AP_WAKE_BT_PH3 _GPIO(59) +#define TEGRA_PIN_BT_RST_PH4 _GPIO(60) +#define TEGRA_PIN_BT_WAKE_AP_PH5 _GPIO(61) +#define TEGRA_PIN_PH6 _GPIO(62) +#define TEGRA_PIN_AP_WAKE_NFC_PH7 _GPIO(63) +#define TEGRA_PIN_NFC_EN_PI0 _GPIO(64) +#define TEGRA_PIN_NFC_INT_PI1 _GPIO(65) +#define TEGRA_PIN_GPS_EN_PI2 _GPIO(66) +#define TEGRA_PIN_GPS_RST_PI3 _GPIO(67) +#define TEGRA_PIN_UART4_TX_PI4 _GPIO(68) +#define TEGRA_PIN_UART4_RX_PI5 _GPIO(69) +#define TEGRA_PIN_UART4_RTS_PI6 _GPIO(70) +#define TEGRA_PIN_UART4_CTS_PI7 _GPIO(71) +#define TEGRA_PIN_GEN1_I2C_SDA_PJ0 _GPIO(72) +#define TEGRA_PIN_GEN1_I2C_SCL_PJ1 _GPIO(73) +#define TEGRA_PIN_GEN2_I2C_SCL_PJ2 _GPIO(74) +#define TEGRA_PIN_GEN2_I2C_SDA_PJ3 _GPIO(75) +#define TEGRA_PIN_DAP4_FS_PJ4 _GPIO(76) +#define TEGRA_PIN_DAP4_DIN_PJ5 _GPIO(77) +#define TEGRA_PIN_DAP4_DOUT_PJ6 _GPIO(78) +#define TEGRA_PIN_DAP4_SCLK_PJ7 _GPIO(79) +#define TEGRA_PIN_PK0 _GPIO(80) +#define TEGRA_PIN_PK1 _GPIO(81) +#define TEGRA_PIN_PK2 _GPIO(82) +#define TEGRA_PIN_PK3 _GPIO(83) +#define TEGRA_PIN_PK4 _GPIO(84) +#define TEGRA_PIN_PK5 _GPIO(85) +#define TEGRA_PIN_PK6 _GPIO(86) +#define TEGRA_PIN_PK7 _GPIO(87) +#define TEGRA_PIN_PL0 _GPIO(88) +#define TEGRA_PIN_PL1 _GPIO(89) +#define TEGRA_PIN_SDMMC1_CLK_PM0 _GPIO(96) +#define TEGRA_PIN_SDMMC1_CMD_PM1 _GPIO(97) +#define TEGRA_PIN_SDMMC1_DAT3_PM2 _GPIO(98) +#define TEGRA_PIN_SDMMC1_DAT2_PM3 _GPIO(99) +#define TEGRA_PIN_SDMMC1_DAT1_PM4 _GPIO(100) +#define TEGRA_PIN_SDMMC1_DAT0_PM5 _GPIO(101) +#define TEGRA_PIN_SDMMC3_CLK_PP0 _GPIO(120) +#define TEGRA_PIN_SDMMC3_CMD_PP1 _GPIO(121) +#define TEGRA_PIN_SDMMC3_DAT3_PP2 _GPIO(122) +#define TEGRA_PIN_SDMMC3_DAT2_PP3 _GPIO(123) +#define TEGRA_PIN_SDMMC3_DAT1_PP4 _GPIO(124) +#define TEGRA_PIN_SDMMC3_DAT0_PP5 _GPIO(125) +#define TEGRA_PIN_CAM1_MCLK_PS0 _GPIO(144) +#define TEGRA_PIN_CAM2_MCLK_PS1 _GPIO(145) +#define TEGRA_PIN_CAM_I2C_SCL_PS2 _GPIO(146) +#define TEGRA_PIN_CAM_I2C_SDA_PS3 _GPIO(147) +#define TEGRA_PIN_CAM_RST_PS4 _GPIO(148) +#define TEGRA_PIN_CAM_AF_EN_PS5 _GPIO(149) +#define TEGRA_PIN_CAM_FLASH_EN_PS6 _GPIO(150) +#define TEGRA_PIN_CAM1_PWDN_PS7 _GPIO(151) +#define TEGRA_PIN_CAM2_PWDN_PT0 _GPIO(152) +#define TEGRA_PIN_CAM1_STROBE_PT1 _GPIO(153) +#define TEGRA_PIN_UART1_TX_PU0 _GPIO(160) +#define TEGRA_PIN_UART1_RX_PU1 _GPIO(161) +#define TEGRA_PIN_UART1_RTS_PU2 _GPIO(162) +#define TEGRA_PIN_UART1_CTS_PU3 _GPIO(163) +#define TEGRA_PIN_LCD_BL_PWM_PV0 _GPIO(168) +#define TEGRA_PIN_LCD_BL_EN_PV1 _GPIO(169) +#define TEGRA_PIN_LCD_RST_PV2 _GPIO(170) +#define TEGRA_PIN_LCD_GPIO1_PV3 _GPIO(171) +#define TEGRA_PIN_LCD_GPIO2_PV4 _GPIO(172) +#define TEGRA_PIN_AP_READY_PV5 _GPIO(173) +#define TEGRA_PIN_TOUCH_RST_PV6 _GPIO(174) +#define TEGRA_PIN_TOUCH_CLK_PV7 _GPIO(175) +#define TEGRA_PIN_MODEM_WAKE_AP_PX0 _GPIO(184) +#define TEGRA_PIN_TOUCH_INT_PX1 _GPIO(185) +#define TEGRA_PIN_MOTION_INT_PX2 _GPIO(186) +#define TEGRA_PIN_ALS_PROX_INT_PX3 _GPIO(187) +#define TEGRA_PIN_TEMP_ALERT_PX4 _GPIO(188) +#define TEGRA_PIN_BUTTON_POWER_ON_PX5 _GPIO(189) +#define TEGRA_PIN_BUTTON_VOL_UP_PX6 _GPIO(190) +#define TEGRA_PIN_BUTTON_VOL_DOWN_PX7 _GPIO(191) +#define TEGRA_PIN_BUTTON_SLIDE_SW_PY0 _GPIO(192) +#define TEGRA_PIN_BUTTON_HOME_PY1 _GPIO(193) +#define TEGRA_PIN_LCD_TE_PY2 _GPIO(194) +#define TEGRA_PIN_PWR_I2C_SCL_PY3 _GPIO(195) +#define TEGRA_PIN_PWR_I2C_SDA_PY4 _GPIO(196) +#define TEGRA_PIN_CLK_32K_OUT_PY5 _GPIO(197) +#define TEGRA_PIN_PZ0 _GPIO(200) +#define TEGRA_PIN_PZ1 _GPIO(201) +#define TEGRA_PIN_PZ2 _GPIO(202) +#define TEGRA_PIN_PZ3 _GPIO(203) +#define TEGRA_PIN_PZ4 _GPIO(204) +#define TEGRA_PIN_PZ5 _GPIO(205) +#define TEGRA_PIN_DAP2_FS_PAA0 _GPIO(208) +#define TEGRA_PIN_DAP2_SCLK_PAA1 _GPIO(209) +#define TEGRA_PIN_DAP2_DIN_PAA2 _GPIO(210) +#define TEGRA_PIN_DAP2_DOUT_PAA3 _GPIO(211) +#define TEGRA_PIN_AUD_MCLK_PBB0 _GPIO(216) +#define TEGRA_PIN_DVFS_PWM_PBB1 _GPIO(217) +#define TEGRA_PIN_DVFS_CLK_PBB2 _GPIO(218) +#define TEGRA_PIN_GPIO_X1_AUD_PBB3 _GPIO(219) +#define TEGRA_PIN_GPIO_X3_AUD_PBB4 _GPIO(220) +#define TEGRA_PIN_HDMI_CEC_PCC0 _GPIO(224) +#define TEGRA_PIN_HDMI_INT_DP_HPD_PCC1 _GPIO(225) +#define TEGRA_PIN_SPDIF_OUT_PCC2 _GPIO(226) +#define TEGRA_PIN_SPDIF_IN_PCC3 _GPIO(227) +#define TEGRA_PIN_USB_VBUS_EN0_PCC4 _GPIO(228) +#define TEGRA_PIN_USB_VBUS_EN1_PCC5 _GPIO(229) +#define TEGRA_PIN_DP_HPD0_PCC6 _GPIO(230) +#define TEGRA_PIN_PCC7 _GPIO(231) +#define TEGRA_PIN_SPI2_CS1_PDD0 _GPIO(232) +#define TEGRA_PIN_QSPI_SCK_PEE0 _GPIO(240) +#define TEGRA_PIN_QSPI_CS_N_PEE1 _GPIO(241) +#define TEGRA_PIN_QSPI_IO0_PEE2 _GPIO(242) +#define TEGRA_PIN_QSPI_IO1_PEE3 _GPIO(243) +#define TEGRA_PIN_QSPI_IO2_PEE4 _GPIO(244) +#define TEGRA_PIN_QSPI_IO3_PEE5 _GPIO(245) + +/* All non-GPIO pins follow */ +#define NUM_GPIOS (TEGRA_PIN_QSPI_IO3_PEE5 + 1) +#define _PIN(offset) (NUM_GPIOS + (offset)) + +/* Non-GPIO pins */ +#define TEGRA_PIN_CORE_PWR_REQ _PIN(0) +#define TEGRA_PIN_CPU_PWR_REQ _PIN(1) +#define TEGRA_PIN_PWR_INT_N _PIN(2) +#define TEGRA_PIN_CLK_32K_IN _PIN(3) +#define TEGRA_PIN_JTAG_RTCK _PIN(4) +#define TEGRA_PIN_BATT_BCL _PIN(5) +#define TEGRA_PIN_CLK_REQ _PIN(6) +#define TEGRA_PIN_SHUTDOWN _PIN(7) + +static const struct pinctrl_pin_desc tegra210_pins[] = { + PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PA0, "PEX_L0_RST_N PA0"), + PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PA1, "PEX_L0_CLKREQ_N PA1"), + PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PA2, "PEX_WAKE_N PA2"), + PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PA3, "PEX_L1_RST_N PA3"), + PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PA4, "PEX_L1_CLKREQ_N PA4"), + PINCTRL_PIN(TEGRA_PIN_SATA_LED_ACTIVE_PA5, "SATA_LED_ACTIVE PA5"), + PINCTRL_PIN(TEGRA_PIN_PA6, "PA6"), + PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PB0, "DAP1_FS PB0"), + PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PB1, "DAP1_DIN PB1"), + PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PB2, "DAP1_DOUT PB2"), + PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PB3, "DAP1_SCLK PB3"), + PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PB4, "SPI2_MOSI PB4"), + PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PB5, "SPI2_MISO PB5"), + PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PB6, "SPI2_SCK PB6"), + PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PB7, "SPI2_CS0 PB7"), + PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PC0, "SPI1_MOSI PC0"), + PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PC1, "SPI1_MISO PC1"), + PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PC2, "SPI1_SCK PC2"), + PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PC3, "SPI1_CS0 PC3"), + PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PC4, "SPI1_CS1 PC4"), + PINCTRL_PIN(TEGRA_PIN_SPI4_SCK_PC5, "SPI4_SCK PC5"), + PINCTRL_PIN(TEGRA_PIN_SPI4_CS0_PC6, "SPI4_CS0 PC6"), + PINCTRL_PIN(TEGRA_PIN_SPI4_MOSI_PC7, "SPI4_MOSI PC7"), + PINCTRL_PIN(TEGRA_PIN_SPI4_MISO_PD0, "SPI4_MISO PD0"), + PINCTRL_PIN(TEGRA_PIN_UART3_TX_PD1, "UART3_TX PD1"), + PINCTRL_PIN(TEGRA_PIN_UART3_RX_PD2, "UART3_RX PD2"), + PINCTRL_PIN(TEGRA_PIN_UART3_RTS_PD3, "UART3_RTS PD3"), + PINCTRL_PIN(TEGRA_PIN_UART3_CTS_PD4, "UART3_CTS PD4"), + PINCTRL_PIN(TEGRA_PIN_DMIC1_CLK_PE0, "DMIC1_CLK PE0"), + PINCTRL_PIN(TEGRA_PIN_DMIC1_DAT_PE1, "DMIC1_DAT PE1"), + PINCTRL_PIN(TEGRA_PIN_DMIC2_CLK_PE2, "DMIC2_CLK PE2"), + PINCTRL_PIN(TEGRA_PIN_DMIC2_DAT_PE3, "DMIC2_DAT PE3"), + PINCTRL_PIN(TEGRA_PIN_DMIC3_CLK_PE4, "DMIC3_CLK PE4"), + PINCTRL_PIN(TEGRA_PIN_DMIC3_DAT_PE5, "DMIC3_DAT PE5"), + PINCTRL_PIN(TEGRA_PIN_PE6, "PE6"), + PINCTRL_PIN(TEGRA_PIN_PE7, "PE7"), + PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SCL_PF0, "GEN3_I2C_SCL PF0"), + PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SDA_PF1, "GEN3_I2C_SDA PF1"), + PINCTRL_PIN(TEGRA_PIN_UART2_TX_PG0, "UART2_TX PG0"), + PINCTRL_PIN(TEGRA_PIN_UART2_RX_PG1, "UART2_RX PG1"), + PINCTRL_PIN(TEGRA_PIN_UART2_RTS_PG2, "UART2_RTS PG2"), + PINCTRL_PIN(TEGRA_PIN_UART2_CTS_PG3, "UART2_CTS PG3"), + PINCTRL_PIN(TEGRA_PIN_WIFI_EN_PH0, "WIFI_EN PH0"), + PINCTRL_PIN(TEGRA_PIN_WIFI_RST_PH1, "WIFI_RST PH1"), + PINCTRL_PIN(TEGRA_PIN_WIFI_WAKE_AP_PH2, "WIFI_WAKE_AP PH2"), + PINCTRL_PIN(TEGRA_PIN_AP_WAKE_BT_PH3, "AP_WAKE_BT PH3"), + PINCTRL_PIN(TEGRA_PIN_BT_RST_PH4, "BT_RST PH4"), + PINCTRL_PIN(TEGRA_PIN_BT_WAKE_AP_PH5, "BT_WAKE_AP PH5"), + PINCTRL_PIN(TEGRA_PIN_PH6, "PH6"), + PINCTRL_PIN(TEGRA_PIN_AP_WAKE_NFC_PH7, "AP_WAKE_NFC PH7"), + PINCTRL_PIN(TEGRA_PIN_NFC_EN_PI0, "NFC_EN PI0"), + PINCTRL_PIN(TEGRA_PIN_NFC_INT_PI1, "NFC_INT PI1"), + PINCTRL_PIN(TEGRA_PIN_GPS_EN_PI2, "GPS_EN PI2"), + PINCTRL_PIN(TEGRA_PIN_GPS_RST_PI3, "GPS_RST PI3"), + PINCTRL_PIN(TEGRA_PIN_UART4_TX_PI4, "UART4_TX PI4"), + PINCTRL_PIN(TEGRA_PIN_UART4_RX_PI5, "UART4_RX PI5"), + PINCTRL_PIN(TEGRA_PIN_UART4_RTS_PI6, "UART4_RTS PI6"), + PINCTRL_PIN(TEGRA_PIN_UART4_CTS_PI7, "UART4_CTS PI7"), + PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PJ0, "GEN1_I2C_SDA PJ0"), + PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PJ1, "GEN1_I2C_SCL PJ1"), + PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PJ2, "GEN2_I2C_SCL PJ2"), + PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PJ3, "GEN2_I2C_SDA PJ3"), + PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PJ4, "DAP4_FS PJ4"), + PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PJ5, "DAP4_DIN PJ5"), + PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PJ6, "DAP4_DOUT PJ6"), + PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PJ7, "DAP4_SCLK PJ7"), + PINCTRL_PIN(TEGRA_PIN_PK0, "PK0"), + PINCTRL_PIN(TEGRA_PIN_PK1, "PK1"), + PINCTRL_PIN(TEGRA_PIN_PK2, "PK2"), + PINCTRL_PIN(TEGRA_PIN_PK3, "PK3"), + PINCTRL_PIN(TEGRA_PIN_PK4, "PK4"), + PINCTRL_PIN(TEGRA_PIN_PK5, "PK5"), + PINCTRL_PIN(TEGRA_PIN_PK6, "PK6"), + PINCTRL_PIN(TEGRA_PIN_PK7, "PK7"), + PINCTRL_PIN(TEGRA_PIN_PL0, "PL0"), + PINCTRL_PIN(TEGRA_PIN_PL1, "PL1"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PM0, "SDMMC1_CLK PM0"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PM1, "SDMMC1_CMD PM1"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PM2, "SDMMC1_DAT3 PM2"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PM3, "SDMMC1_DAT2 PM3"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PM4, "SDMMC1_DAT1 PM4"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PM5, "SDMMC1_DAT0 PM5"), + PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PP0, "SDMMC3_CLK PP0"), + PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PP1, "SDMMC3_CMD PP1"), + PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PP2, "SDMMC3_DAT3 PP2"), + PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PP3, "SDMMC3_DAT2 PP3"), + PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PP4, "SDMMC3_DAT1 PP4"), + PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PP5, "SDMMC3_DAT0 PP5"), + PINCTRL_PIN(TEGRA_PIN_CAM1_MCLK_PS0, "CAM1_MCLK PS0"), + PINCTRL_PIN(TEGRA_PIN_CAM2_MCLK_PS1, "CAM2_MCLK PS1"), + PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PS2, "CAM_I2C_SCL PS2"), + PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PS3, "CAM_I2C_SDA PS3"), + PINCTRL_PIN(TEGRA_PIN_CAM_RST_PS4, "CAM_RST PS4"), + PINCTRL_PIN(TEGRA_PIN_CAM_AF_EN_PS5, "CAM_AF_EN PS5"), + PINCTRL_PIN(TEGRA_PIN_CAM_FLASH_EN_PS6, "CAM_FLASH_EN PS6"), + PINCTRL_PIN(TEGRA_PIN_CAM1_PWDN_PS7, "CAM1_PWDN PS7"), + PINCTRL_PIN(TEGRA_PIN_CAM2_PWDN_PT0, "CAM2_PWDN PT0"), + PINCTRL_PIN(TEGRA_PIN_CAM1_STROBE_PT1, "CAM1_STROBE PT1"), + PINCTRL_PIN(TEGRA_PIN_UART1_TX_PU0, "UART1_TX PU0"), + PINCTRL_PIN(TEGRA_PIN_UART1_RX_PU1, "UART1_RX PU1"), + PINCTRL_PIN(TEGRA_PIN_UART1_RTS_PU2, "UART1_RTS PU2"), + PINCTRL_PIN(TEGRA_PIN_UART1_CTS_PU3, "UART1_CTS PU3"), + PINCTRL_PIN(TEGRA_PIN_LCD_BL_PWM_PV0, "LCD_BL_PWM PV0"), + PINCTRL_PIN(TEGRA_PIN_LCD_BL_EN_PV1, "LCD_BL_EN PV1"), + PINCTRL_PIN(TEGRA_PIN_LCD_RST_PV2, "LCD_RST PV2"), + PINCTRL_PIN(TEGRA_PIN_LCD_GPIO1_PV3, "LCD_GPIO1 PV3"), + PINCTRL_PIN(TEGRA_PIN_LCD_GPIO2_PV4, "LCD_GPIO2 PV4"), + PINCTRL_PIN(TEGRA_PIN_AP_READY_PV5, "AP_READY PV5"), + PINCTRL_PIN(TEGRA_PIN_TOUCH_RST_PV6, "TOUCH_RST PV6"), + PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PV7, "TOUCH_CLK PV7"), + PINCTRL_PIN(TEGRA_PIN_MODEM_WAKE_AP_PX0, "MODEM_WAKE_AP PX0"), + PINCTRL_PIN(TEGRA_PIN_TOUCH_INT_PX1, "TOUCH_INT PX1"), + PINCTRL_PIN(TEGRA_PIN_MOTION_INT_PX2, "MOTION_INT PX2"), + PINCTRL_PIN(TEGRA_PIN_ALS_PROX_INT_PX3, "ALS_PROX_INT PX3"), + PINCTRL_PIN(TEGRA_PIN_TEMP_ALERT_PX4, "TEMP_ALERT PX4"), + PINCTRL_PIN(TEGRA_PIN_BUTTON_POWER_ON_PX5, "BUTTON_POWER_ON PX5"), + PINCTRL_PIN(TEGRA_PIN_BUTTON_VOL_UP_PX6, "BUTTON_VOL_UP PX6"), + PINCTRL_PIN(TEGRA_PIN_BUTTON_VOL_DOWN_PX7, "BUTTON_VOL_DOWN PX7"), + PINCTRL_PIN(TEGRA_PIN_BUTTON_SLIDE_SW_PY0, "BUTTON_SLIDE_SW PY0"), + PINCTRL_PIN(TEGRA_PIN_BUTTON_HOME_PY1, "BUTTON_HOME PY1"), + PINCTRL_PIN(TEGRA_PIN_LCD_TE_PY2, "LCD_TE PY2"), + PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PY3, "PWR_I2C_SCL PY3"), + PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PY4, "PWR_I2C_SDA PY4"), + PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PY5, "CLK_32K_OUT PY5"), + PINCTRL_PIN(TEGRA_PIN_PZ0, "PZ0"), + PINCTRL_PIN(TEGRA_PIN_PZ1, "PZ1"), + PINCTRL_PIN(TEGRA_PIN_PZ2, "PZ2"), + PINCTRL_PIN(TEGRA_PIN_PZ3, "PZ3"), + PINCTRL_PIN(TEGRA_PIN_PZ4, "PZ4"), + PINCTRL_PIN(TEGRA_PIN_PZ5, "PZ5"), + PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PAA0, "DAP2_FS PAA0"), + PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PAA1, "DAP2_SCLK PAA1"), + PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PAA2, "DAP2_DIN PAA2"), + PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PAA3, "DAP2_DOUT PAA3"), + PINCTRL_PIN(TEGRA_PIN_AUD_MCLK_PBB0, "AUD_MCLK PBB0"), + PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PBB1, "DVFS_PWM PBB1"), + PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PBB2, "DVFS_CLK PBB2"), + PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PBB3, "GPIO_X1_AUD PBB3"), + PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PBB4, "GPIO_X3_AUD PBB4"), + PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PCC0, "HDMI_CEC PCC0"), + PINCTRL_PIN(TEGRA_PIN_HDMI_INT_DP_HPD_PCC1, "HDMI_INT_DP_HPD PCC1"), + PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PCC2, "SPDIF_OUT PCC2"), + PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PCC3, "SPDIF_IN PCC3"), + PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PCC4, "USB_VBUS_EN0 PCC4"), + PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PCC5, "USB_VBUS_EN1 PCC5"), + PINCTRL_PIN(TEGRA_PIN_DP_HPD0_PCC6, "DP_HPD0 PCC6"), + PINCTRL_PIN(TEGRA_PIN_PCC7, "PCC7"), + PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_PDD0, "SPI2_CS1 PDD0"), + PINCTRL_PIN(TEGRA_PIN_QSPI_SCK_PEE0, "QSPI_SCK PEE0"), + PINCTRL_PIN(TEGRA_PIN_QSPI_CS_N_PEE1, "QSPI_CS_N PEE1"), + PINCTRL_PIN(TEGRA_PIN_QSPI_IO0_PEE2, "QSPI_IO0 PEE2"), + PINCTRL_PIN(TEGRA_PIN_QSPI_IO1_PEE3, "QSPI_IO1 PEE3"), + PINCTRL_PIN(TEGRA_PIN_QSPI_IO2_PEE4, "QSPI_IO2 PEE4"), + PINCTRL_PIN(TEGRA_PIN_QSPI_IO3_PEE5, "QSPI_IO3 PEE5"), + PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"), + PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"), + PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"), + PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"), + PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"), + PINCTRL_PIN(TEGRA_PIN_BATT_BCL, "BATT_BCL"), + PINCTRL_PIN(TEGRA_PIN_CLK_REQ, "CLK_REQ"), + PINCTRL_PIN(TEGRA_PIN_SHUTDOWN, "SHUTDOWN"), +}; + +static const unsigned pex_l0_rst_n_pa0_pins[] = { + TEGRA_PIN_PEX_L0_RST_N_PA0, +}; + +static const unsigned pex_l0_clkreq_n_pa1_pins[] = { + TEGRA_PIN_PEX_L0_CLKREQ_N_PA1, +}; + +static const unsigned pex_wake_n_pa2_pins[] = { + TEGRA_PIN_PEX_WAKE_N_PA2, +}; + +static const unsigned pex_l1_rst_n_pa3_pins[] = { + TEGRA_PIN_PEX_L1_RST_N_PA3, +}; + +static const unsigned pex_l1_clkreq_n_pa4_pins[] = { + TEGRA_PIN_PEX_L1_CLKREQ_N_PA4, +}; + +static const unsigned sata_led_active_pa5_pins[] = { + TEGRA_PIN_SATA_LED_ACTIVE_PA5, +}; + +static const unsigned pa6_pins[] = { + TEGRA_PIN_PA6, +}; + +static const unsigned dap1_fs_pb0_pins[] = { + TEGRA_PIN_DAP1_FS_PB0, +}; + +static const unsigned dap1_din_pb1_pins[] = { + TEGRA_PIN_DAP1_DIN_PB1, +}; + +static const unsigned dap1_dout_pb2_pins[] = { + TEGRA_PIN_DAP1_DOUT_PB2, +}; + +static const unsigned dap1_sclk_pb3_pins[] = { + TEGRA_PIN_DAP1_SCLK_PB3, +}; + +static const unsigned spi2_mosi_pb4_pins[] = { + TEGRA_PIN_SPI2_MOSI_PB4, +}; + +static const unsigned spi2_miso_pb5_pins[] = { + TEGRA_PIN_SPI2_MISO_PB5, +}; + +static const unsigned spi2_sck_pb6_pins[] = { + TEGRA_PIN_SPI2_SCK_PB6, +}; + +static const unsigned spi2_cs0_pb7_pins[] = { + TEGRA_PIN_SPI2_CS0_PB7, +}; + +static const unsigned spi1_mosi_pc0_pins[] = { + TEGRA_PIN_SPI1_MOSI_PC0, +}; + +static const unsigned spi1_miso_pc1_pins[] = { + TEGRA_PIN_SPI1_MISO_PC1, +}; + +static const unsigned spi1_sck_pc2_pins[] = { + TEGRA_PIN_SPI1_SCK_PC2, +}; + +static const unsigned spi1_cs0_pc3_pins[] = { + TEGRA_PIN_SPI1_CS0_PC3, +}; + +static const unsigned spi1_cs1_pc4_pins[] = { + TEGRA_PIN_SPI1_CS1_PC4, +}; + +static const unsigned spi4_sck_pc5_pins[] = { + TEGRA_PIN_SPI4_SCK_PC5, +}; + +static const unsigned spi4_cs0_pc6_pins[] = { + TEGRA_PIN_SPI4_CS0_PC6, +}; + +static const unsigned spi4_mosi_pc7_pins[] = { + TEGRA_PIN_SPI4_MOSI_PC7, +}; + +static const unsigned spi4_miso_pd0_pins[] = { + TEGRA_PIN_SPI4_MISO_PD0, +}; + +static const unsigned uart3_tx_pd1_pins[] = { + TEGRA_PIN_UART3_TX_PD1, +}; + +static const unsigned uart3_rx_pd2_pins[] = { + TEGRA_PIN_UART3_RX_PD2, +}; + +static const unsigned uart3_rts_pd3_pins[] = { + TEGRA_PIN_UART3_RTS_PD3, +}; + +static const unsigned uart3_cts_pd4_pins[] = { + TEGRA_PIN_UART3_CTS_PD4, +}; + +static const unsigned dmic1_clk_pe0_pins[] = { + TEGRA_PIN_DMIC1_CLK_PE0, +}; + +static const unsigned dmic1_dat_pe1_pins[] = { + TEGRA_PIN_DMIC1_DAT_PE1, +}; + +static const unsigned dmic2_clk_pe2_pins[] = { + TEGRA_PIN_DMIC2_CLK_PE2, +}; + +static const unsigned dmic2_dat_pe3_pins[] = { + TEGRA_PIN_DMIC2_DAT_PE3, +}; + +static const unsigned dmic3_clk_pe4_pins[] = { + TEGRA_PIN_DMIC3_CLK_PE4, +}; + +static const unsigned dmic3_dat_pe5_pins[] = { + TEGRA_PIN_DMIC3_DAT_PE5, +}; + +static const unsigned pe6_pins[] = { + TEGRA_PIN_PE6, +}; + +static const unsigned pe7_pins[] = { + TEGRA_PIN_PE7, +}; + +static const unsigned gen3_i2c_scl_pf0_pins[] = { + TEGRA_PIN_GEN3_I2C_SCL_PF0, +}; + +static const unsigned gen3_i2c_sda_pf1_pins[] = { + TEGRA_PIN_GEN3_I2C_SDA_PF1, +}; + +static const unsigned uart2_tx_pg0_pins[] = { + TEGRA_PIN_UART2_TX_PG0, +}; + +static const unsigned uart2_rx_pg1_pins[] = { + TEGRA_PIN_UART2_RX_PG1, +}; + +static const unsigned uart2_rts_pg2_pins[] = { + TEGRA_PIN_UART2_RTS_PG2, +}; + +static const unsigned uart2_cts_pg3_pins[] = { + TEGRA_PIN_UART2_CTS_PG3, +}; + +static const unsigned wifi_en_ph0_pins[] = { + TEGRA_PIN_WIFI_EN_PH0, +}; + +static const unsigned wifi_rst_ph1_pins[] = { + TEGRA_PIN_WIFI_RST_PH1, +}; + +static const unsigned wifi_wake_ap_ph2_pins[] = { + TEGRA_PIN_WIFI_WAKE_AP_PH2, +}; + +static const unsigned ap_wake_bt_ph3_pins[] = { + TEGRA_PIN_AP_WAKE_BT_PH3, +}; + +static const unsigned bt_rst_ph4_pins[] = { + TEGRA_PIN_BT_RST_PH4, +}; + +static const unsigned bt_wake_ap_ph5_pins[] = { + TEGRA_PIN_BT_WAKE_AP_PH5, +}; + +static const unsigned ph6_pins[] = { + TEGRA_PIN_PH6, +}; + +static const unsigned ap_wake_nfc_ph7_pins[] = { + TEGRA_PIN_AP_WAKE_NFC_PH7, +}; + +static const unsigned nfc_en_pi0_pins[] = { + TEGRA_PIN_NFC_EN_PI0, +}; + +static const unsigned nfc_int_pi1_pins[] = { + TEGRA_PIN_NFC_INT_PI1, +}; + +static const unsigned gps_en_pi2_pins[] = { + TEGRA_PIN_GPS_EN_PI2, +}; + +static const unsigned gps_rst_pi3_pins[] = { + TEGRA_PIN_GPS_RST_PI3, +}; + +static const unsigned uart4_tx_pi4_pins[] = { + TEGRA_PIN_UART4_TX_PI4, +}; + +static const unsigned uart4_rx_pi5_pins[] = { + TEGRA_PIN_UART4_RX_PI5, +}; + +static const unsigned uart4_rts_pi6_pins[] = { + TEGRA_PIN_UART4_RTS_PI6, +}; + +static const unsigned uart4_cts_pi7_pins[] = { + TEGRA_PIN_UART4_CTS_PI7, +}; + +static const unsigned gen1_i2c_sda_pj0_pins[] = { + TEGRA_PIN_GEN1_I2C_SDA_PJ0, +}; + +static const unsigned gen1_i2c_scl_pj1_pins[] = { + TEGRA_PIN_GEN1_I2C_SCL_PJ1, +}; + +static const unsigned gen2_i2c_scl_pj2_pins[] = { + TEGRA_PIN_GEN2_I2C_SCL_PJ2, +}; + +static const unsigned gen2_i2c_sda_pj3_pins[] = { + TEGRA_PIN_GEN2_I2C_SDA_PJ3, +}; + +static const unsigned dap4_fs_pj4_pins[] = { + TEGRA_PIN_DAP4_FS_PJ4, +}; + +static const unsigned dap4_din_pj5_pins[] = { + TEGRA_PIN_DAP4_DIN_PJ5, +}; + +static const unsigned dap4_dout_pj6_pins[] = { + TEGRA_PIN_DAP4_DOUT_PJ6, +}; + +static const unsigned dap4_sclk_pj7_pins[] = { + TEGRA_PIN_DAP4_SCLK_PJ7, +}; + +static const unsigned pk0_pins[] = { + TEGRA_PIN_PK0, +}; + +static const unsigned pk1_pins[] = { + TEGRA_PIN_PK1, +}; + +static const unsigned pk2_pins[] = { + TEGRA_PIN_PK2, +}; + +static const unsigned pk3_pins[] = { + TEGRA_PIN_PK3, +}; + +static const unsigned pk4_pins[] = { + TEGRA_PIN_PK4, +}; + +static const unsigned pk5_pins[] = { + TEGRA_PIN_PK5, +}; + +static const unsigned pk6_pins[] = { + TEGRA_PIN_PK6, +}; + +static const unsigned pk7_pins[] = { + TEGRA_PIN_PK7, +}; + +static const unsigned pl0_pins[] = { + TEGRA_PIN_PL0, +}; + +static const unsigned pl1_pins[] = { + TEGRA_PIN_PL1, +}; + +static const unsigned sdmmc1_clk_pm0_pins[] = { + TEGRA_PIN_SDMMC1_CLK_PM0, +}; + +static const unsigned sdmmc1_cmd_pm1_pins[] = { + TEGRA_PIN_SDMMC1_CMD_PM1, +}; + +static const unsigned sdmmc1_dat3_pm2_pins[] = { + TEGRA_PIN_SDMMC1_DAT3_PM2, +}; + +static const unsigned sdmmc1_dat2_pm3_pins[] = { + TEGRA_PIN_SDMMC1_DAT2_PM3, +}; + +static const unsigned sdmmc1_dat1_pm4_pins[] = { + TEGRA_PIN_SDMMC1_DAT1_PM4, +}; + +static const unsigned sdmmc1_dat0_pm5_pins[] = { + TEGRA_PIN_SDMMC1_DAT0_PM5, +}; + +static const unsigned sdmmc3_clk_pp0_pins[] = { + TEGRA_PIN_SDMMC3_CLK_PP0, +}; + +static const unsigned sdmmc3_cmd_pp1_pins[] = { + TEGRA_PIN_SDMMC3_CMD_PP1, +}; + +static const unsigned sdmmc3_dat3_pp2_pins[] = { + TEGRA_PIN_SDMMC3_DAT3_PP2, +}; + +static const unsigned sdmmc3_dat2_pp3_pins[] = { + TEGRA_PIN_SDMMC3_DAT2_PP3, +}; + +static const unsigned sdmmc3_dat1_pp4_pins[] = { + TEGRA_PIN_SDMMC3_DAT1_PP4, +}; + +static const unsigned sdmmc3_dat0_pp5_pins[] = { + TEGRA_PIN_SDMMC3_DAT0_PP5, +}; + +static const unsigned cam1_mclk_ps0_pins[] = { + TEGRA_PIN_CAM1_MCLK_PS0, +}; + +static const unsigned cam2_mclk_ps1_pins[] = { + TEGRA_PIN_CAM2_MCLK_PS1, +}; + +static const unsigned cam_i2c_scl_ps2_pins[] = { + TEGRA_PIN_CAM_I2C_SCL_PS2, +}; + +static const unsigned cam_i2c_sda_ps3_pins[] = { + TEGRA_PIN_CAM_I2C_SDA_PS3, +}; + +static const unsigned cam_rst_ps4_pins[] = { + TEGRA_PIN_CAM_RST_PS4, +}; + +static const unsigned cam_af_en_ps5_pins[] = { + TEGRA_PIN_CAM_AF_EN_PS5, +}; + +static const unsigned cam_flash_en_ps6_pins[] = { + TEGRA_PIN_CAM_FLASH_EN_PS6, +}; + +static const unsigned cam1_pwdn_ps7_pins[] = { + TEGRA_PIN_CAM1_PWDN_PS7, +}; + +static const unsigned cam2_pwdn_pt0_pins[] = { + TEGRA_PIN_CAM2_PWDN_PT0, +}; + +static const unsigned cam1_strobe_pt1_pins[] = { + TEGRA_PIN_CAM1_STROBE_PT1, +}; + +static const unsigned uart1_tx_pu0_pins[] = { + TEGRA_PIN_UART1_TX_PU0, +}; + +static const unsigned uart1_rx_pu1_pins[] = { + TEGRA_PIN_UART1_RX_PU1, +}; + +static const unsigned uart1_rts_pu2_pins[] = { + TEGRA_PIN_UART1_RTS_PU2, +}; + +static const unsigned uart1_cts_pu3_pins[] = { + TEGRA_PIN_UART1_CTS_PU3, +}; + +static const unsigned lcd_bl_pwm_pv0_pins[] = { + TEGRA_PIN_LCD_BL_PWM_PV0, +}; + +static const unsigned lcd_bl_en_pv1_pins[] = { + TEGRA_PIN_LCD_BL_EN_PV1, +}; + +static const unsigned lcd_rst_pv2_pins[] = { + TEGRA_PIN_LCD_RST_PV2, +}; + +static const unsigned lcd_gpio1_pv3_pins[] = { + TEGRA_PIN_LCD_GPIO1_PV3, +}; + +static const unsigned lcd_gpio2_pv4_pins[] = { + TEGRA_PIN_LCD_GPIO2_PV4, +}; + +static const unsigned ap_ready_pv5_pins[] = { + TEGRA_PIN_AP_READY_PV5, +}; + +static const unsigned touch_rst_pv6_pins[] = { + TEGRA_PIN_TOUCH_RST_PV6, +}; + +static const unsigned touch_clk_pv7_pins[] = { + TEGRA_PIN_TOUCH_CLK_PV7, +}; + +static const unsigned modem_wake_ap_px0_pins[] = { + TEGRA_PIN_MODEM_WAKE_AP_PX0, +}; + +static const unsigned touch_int_px1_pins[] = { + TEGRA_PIN_TOUCH_INT_PX1, +}; + +static const unsigned motion_int_px2_pins[] = { + TEGRA_PIN_MOTION_INT_PX2, +}; + +static const unsigned als_prox_int_px3_pins[] = { + TEGRA_PIN_ALS_PROX_INT_PX3, +}; + +static const unsigned temp_alert_px4_pins[] = { + TEGRA_PIN_TEMP_ALERT_PX4, +}; + +static const unsigned button_power_on_px5_pins[] = { + TEGRA_PIN_BUTTON_POWER_ON_PX5, +}; + +static const unsigned button_vol_up_px6_pins[] = { + TEGRA_PIN_BUTTON_VOL_UP_PX6, +}; + +static const unsigned button_vol_down_px7_pins[] = { + TEGRA_PIN_BUTTON_VOL_DOWN_PX7, +}; + +static const unsigned button_slide_sw_py0_pins[] = { + TEGRA_PIN_BUTTON_SLIDE_SW_PY0, +}; + +static const unsigned button_home_py1_pins[] = { + TEGRA_PIN_BUTTON_HOME_PY1, +}; + +static const unsigned lcd_te_py2_pins[] = { + TEGRA_PIN_LCD_TE_PY2, +}; + +static const unsigned pwr_i2c_scl_py3_pins[] = { + TEGRA_PIN_PWR_I2C_SCL_PY3, +}; + +static const unsigned pwr_i2c_sda_py4_pins[] = { + TEGRA_PIN_PWR_I2C_SDA_PY4, +}; + +static const unsigned clk_32k_out_py5_pins[] = { + TEGRA_PIN_CLK_32K_OUT_PY5, +}; + +static const unsigned pz0_pins[] = { + TEGRA_PIN_PZ0, +}; + +static const unsigned pz1_pins[] = { + TEGRA_PIN_PZ1, +}; + +static const unsigned pz2_pins[] = { + TEGRA_PIN_PZ2, +}; + +static const unsigned pz3_pins[] = { + TEGRA_PIN_PZ3, +}; + +static const unsigned pz4_pins[] = { + TEGRA_PIN_PZ4, +}; + +static const unsigned pz5_pins[] = { + TEGRA_PIN_PZ5, +}; + +static const unsigned dap2_fs_paa0_pins[] = { + TEGRA_PIN_DAP2_FS_PAA0, +}; + +static const unsigned dap2_sclk_paa1_pins[] = { + TEGRA_PIN_DAP2_SCLK_PAA1, +}; + +static const unsigned dap2_din_paa2_pins[] = { + TEGRA_PIN_DAP2_DIN_PAA2, +}; + +static const unsigned dap2_dout_paa3_pins[] = { + TEGRA_PIN_DAP2_DOUT_PAA3, +}; + +static const unsigned aud_mclk_pbb0_pins[] = { + TEGRA_PIN_AUD_MCLK_PBB0, +}; + +static const unsigned dvfs_pwm_pbb1_pins[] = { + TEGRA_PIN_DVFS_PWM_PBB1, +}; + +static const unsigned dvfs_clk_pbb2_pins[] = { + TEGRA_PIN_DVFS_CLK_PBB2, +}; + +static const unsigned gpio_x1_aud_pbb3_pins[] = { + TEGRA_PIN_GPIO_X1_AUD_PBB3, +}; + +static const unsigned gpio_x3_aud_pbb4_pins[] = { + TEGRA_PIN_GPIO_X3_AUD_PBB4, +}; + +static const unsigned hdmi_cec_pcc0_pins[] = { + TEGRA_PIN_HDMI_CEC_PCC0, +}; + +static const unsigned hdmi_int_dp_hpd_pcc1_pins[] = { + TEGRA_PIN_HDMI_INT_DP_HPD_PCC1, +}; + +static const unsigned spdif_out_pcc2_pins[] = { + TEGRA_PIN_SPDIF_OUT_PCC2, +}; + +static const unsigned spdif_in_pcc3_pins[] = { + TEGRA_PIN_SPDIF_IN_PCC3, +}; + +static const unsigned usb_vbus_en0_pcc4_pins[] = { + TEGRA_PIN_USB_VBUS_EN0_PCC4, +}; + +static const unsigned usb_vbus_en1_pcc5_pins[] = { + TEGRA_PIN_USB_VBUS_EN1_PCC5, +}; + +static const unsigned dp_hpd0_pcc6_pins[] = { + TEGRA_PIN_DP_HPD0_PCC6, +}; + +static const unsigned pcc7_pins[] = { + TEGRA_PIN_PCC7, +}; + +static const unsigned spi2_cs1_pdd0_pins[] = { + TEGRA_PIN_SPI2_CS1_PDD0, +}; + +static const unsigned qspi_sck_pee0_pins[] = { + TEGRA_PIN_QSPI_SCK_PEE0, +}; + +static const unsigned qspi_cs_n_pee1_pins[] = { + TEGRA_PIN_QSPI_CS_N_PEE1, +}; + +static const unsigned qspi_io0_pee2_pins[] = { + TEGRA_PIN_QSPI_IO0_PEE2, +}; + +static const unsigned qspi_io1_pee3_pins[] = { + TEGRA_PIN_QSPI_IO1_PEE3, +}; + +static const unsigned qspi_io2_pee4_pins[] = { + TEGRA_PIN_QSPI_IO2_PEE4, +}; + +static const unsigned qspi_io3_pee5_pins[] = { + TEGRA_PIN_QSPI_IO3_PEE5, +}; + +static const unsigned core_pwr_req_pins[] = { + TEGRA_PIN_CORE_PWR_REQ, +}; + +static const unsigned cpu_pwr_req_pins[] = { + TEGRA_PIN_CPU_PWR_REQ, +}; + +static const unsigned pwr_int_n_pins[] = { + TEGRA_PIN_PWR_INT_N, +}; + +static const unsigned clk_32k_in_pins[] = { + TEGRA_PIN_CLK_32K_IN, +}; + +static const unsigned jtag_rtck_pins[] = { + TEGRA_PIN_JTAG_RTCK, +}; + +static const unsigned batt_bcl_pins[] = { + TEGRA_PIN_BATT_BCL, +}; + +static const unsigned clk_req_pins[] = { + TEGRA_PIN_CLK_REQ, +}; + +static const unsigned shutdown_pins[] = { + TEGRA_PIN_SHUTDOWN, +}; + +static const unsigned drive_pa6_pins[] = { + TEGRA_PIN_PA6, +}; + +static const unsigned drive_pcc7_pins[] = { + TEGRA_PIN_PCC7, +}; + +static const unsigned drive_pe6_pins[] = { + TEGRA_PIN_PE6, +}; + +static const unsigned drive_pe7_pins[] = { + TEGRA_PIN_PE7, +}; + +static const unsigned drive_ph6_pins[] = { + TEGRA_PIN_PH6, +}; + +static const unsigned drive_pk0_pins[] = { + TEGRA_PIN_PK0, +}; + +static const unsigned drive_pk1_pins[] = { + TEGRA_PIN_PK1, +}; + +static const unsigned drive_pk2_pins[] = { + TEGRA_PIN_PK2, +}; + +static const unsigned drive_pk3_pins[] = { + TEGRA_PIN_PK3, +}; + +static const unsigned drive_pk4_pins[] = { + TEGRA_PIN_PK4, +}; + +static const unsigned drive_pk5_pins[] = { + TEGRA_PIN_PK5, +}; + +static const unsigned drive_pk6_pins[] = { + TEGRA_PIN_PK6, +}; + +static const unsigned drive_pk7_pins[] = { + TEGRA_PIN_PK7, +}; + +static const unsigned drive_pl0_pins[] = { + TEGRA_PIN_PL0, +}; + +static const unsigned drive_pl1_pins[] = { + TEGRA_PIN_PL1, +}; + +static const unsigned drive_pz0_pins[] = { + TEGRA_PIN_PZ0, +}; + +static const unsigned drive_pz1_pins[] = { + TEGRA_PIN_PZ1, +}; + +static const unsigned drive_pz2_pins[] = { + TEGRA_PIN_PZ2, +}; + +static const unsigned drive_pz3_pins[] = { + TEGRA_PIN_PZ3, +}; + +static const unsigned drive_pz4_pins[] = { + TEGRA_PIN_PZ4, +}; + +static const unsigned drive_pz5_pins[] = { + TEGRA_PIN_PZ5, +}; + +static const unsigned drive_sdmmc1_pins[] = { + TEGRA_PIN_SDMMC1_CLK_PM0, + TEGRA_PIN_SDMMC1_CMD_PM1, + TEGRA_PIN_SDMMC1_DAT3_PM2, + TEGRA_PIN_SDMMC1_DAT2_PM3, + TEGRA_PIN_SDMMC1_DAT1_PM4, + TEGRA_PIN_SDMMC1_DAT0_PM5, +}; + +static const unsigned drive_sdmmc2_pins[] = { +}; + +static const unsigned drive_sdmmc3_pins[] = { + TEGRA_PIN_SDMMC3_CLK_PP0, + TEGRA_PIN_SDMMC3_CMD_PP1, + TEGRA_PIN_SDMMC3_DAT3_PP2, + TEGRA_PIN_SDMMC3_DAT2_PP3, + TEGRA_PIN_SDMMC3_DAT1_PP4, + TEGRA_PIN_SDMMC3_DAT0_PP5, +}; + +static const unsigned drive_sdmmc4_pins[] = { +}; + +enum tegra_mux { + TEGRA_MUX_AUD, + TEGRA_MUX_BCL, + TEGRA_MUX_BLINK, + TEGRA_MUX_CCLA, + TEGRA_MUX_CEC, + TEGRA_MUX_CLDVFS, + TEGRA_MUX_CLK, + TEGRA_MUX_CORE, + TEGRA_MUX_CPU, + TEGRA_MUX_DISPLAYA, + TEGRA_MUX_DISPLAYB, + TEGRA_MUX_DMIC1, + TEGRA_MUX_DMIC2, + TEGRA_MUX_DMIC3, + TEGRA_MUX_DP, + TEGRA_MUX_DTV, + TEGRA_MUX_EXTPERIPH3, + TEGRA_MUX_I2C1, + TEGRA_MUX_I2C2, + TEGRA_MUX_I2C3, + TEGRA_MUX_I2CPMU, + TEGRA_MUX_I2CVI, + TEGRA_MUX_I2S1, + TEGRA_MUX_I2S2, + TEGRA_MUX_I2S3, + TEGRA_MUX_I2S4A, + TEGRA_MUX_I2S4B, + TEGRA_MUX_I2S5A, + TEGRA_MUX_I2S5B, + TEGRA_MUX_IQC0, + TEGRA_MUX_IQC1, + TEGRA_MUX_JTAG, + TEGRA_MUX_PE, + TEGRA_MUX_PE0, + TEGRA_MUX_PE1, + TEGRA_MUX_PMI, + TEGRA_MUX_PWM0, + TEGRA_MUX_PWM1, + TEGRA_MUX_PWM2, + TEGRA_MUX_PWM3, + TEGRA_MUX_QSPI, + TEGRA_MUX_RSVD0, + TEGRA_MUX_RSVD1, + TEGRA_MUX_RSVD2, + TEGRA_MUX_RSVD3, + TEGRA_MUX_SATA, + TEGRA_MUX_SDMMC1, + TEGRA_MUX_SDMMC3, + TEGRA_MUX_SHUTDOWN, + TEGRA_MUX_SOC, + TEGRA_MUX_SOR0, + TEGRA_MUX_SOR1, + TEGRA_MUX_SPDIF, + TEGRA_MUX_SPI1, + TEGRA_MUX_SPI2, + TEGRA_MUX_SPI3, + TEGRA_MUX_SPI4, + TEGRA_MUX_SYS, + TEGRA_MUX_TOUCH, + TEGRA_MUX_UART, + TEGRA_MUX_UARTA, + TEGRA_MUX_UARTB, + TEGRA_MUX_UARTC, + TEGRA_MUX_UARTD, + TEGRA_MUX_USB, + TEGRA_MUX_VGP1, + TEGRA_MUX_VGP2, + TEGRA_MUX_VGP3, + TEGRA_MUX_VGP4, + TEGRA_MUX_VGP5, + TEGRA_MUX_VGP6, + TEGRA_MUX_VIMCLK, + TEGRA_MUX_VIMCLK2, +}; + +#define FUNCTION(fname) \ + { \ + .name = #fname, \ + } + +static struct tegra_function tegra210_functions[] = { + FUNCTION(aud), + FUNCTION(bcl), + FUNCTION(blink), + FUNCTION(ccla), + FUNCTION(cec), + FUNCTION(cldvfs), + FUNCTION(clk), + FUNCTION(core), + FUNCTION(cpu), + FUNCTION(displaya), + FUNCTION(displayb), + FUNCTION(dmic1), + FUNCTION(dmic2), + FUNCTION(dmic3), + FUNCTION(dp), + FUNCTION(dtv), + FUNCTION(extperiph3), + FUNCTION(i2c1), + FUNCTION(i2c2), + FUNCTION(i2c3), + FUNCTION(i2cpmu), + FUNCTION(i2cvi), + FUNCTION(i2s1), + FUNCTION(i2s2), + FUNCTION(i2s3), + FUNCTION(i2s4a), + FUNCTION(i2s4b), + FUNCTION(i2s5a), + FUNCTION(i2s5b), + FUNCTION(iqc0), + FUNCTION(iqc1), + FUNCTION(jtag), + FUNCTION(pe), + FUNCTION(pe0), + FUNCTION(pe1), + FUNCTION(pmi), + FUNCTION(pwm0), + FUNCTION(pwm1), + FUNCTION(pwm2), + FUNCTION(pwm3), + FUNCTION(qspi), + FUNCTION(rsvd0), + FUNCTION(rsvd1), + FUNCTION(rsvd2), + FUNCTION(rsvd3), + FUNCTION(sata), + FUNCTION(sdmmc1), + FUNCTION(sdmmc3), + FUNCTION(shutdown), + FUNCTION(soc), + FUNCTION(sor0), + FUNCTION(sor1), + FUNCTION(spdif), + FUNCTION(spi1), + FUNCTION(spi2), + FUNCTION(spi3), + FUNCTION(spi4), + FUNCTION(sys), + FUNCTION(touch), + FUNCTION(uart), + FUNCTION(uarta), + FUNCTION(uartb), + FUNCTION(uartc), + FUNCTION(uartd), + FUNCTION(usb), + FUNCTION(vgp1), + FUNCTION(vgp2), + FUNCTION(vgp3), + FUNCTION(vgp4), + FUNCTION(vgp5), + FUNCTION(vgp6), + FUNCTION(vimclk), + FUNCTION(vimclk2), +}; + +#define DRV_PINGROUP_REG_A 0x8d4 /* bank 0 */ +#define PINGROUP_REG_A 0x3000 /* bank 1 */ + +#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A) +#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A) + +#define PINGROUP_BIT_Y(b) (b) +#define PINGROUP_BIT_N(b) (-1) + +#define PINGROUP(pg_name, f0, f1, f2, f3, r, hsm, drvtype, e_io_hv, \ + rdrv, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, \ + slwr_w, slwf_b, slwf_w) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .funcs = { \ + TEGRA_MUX_##f0, \ + TEGRA_MUX_##f1, \ + TEGRA_MUX_##f2, \ + TEGRA_MUX_##f3, \ + }, \ + .mux_reg = PINGROUP_REG(r), \ + .mux_bank = 1, \ + .mux_bit = 0, \ + .pupd_reg = PINGROUP_REG(r), \ + .pupd_bank = 1, \ + .pupd_bit = 2, \ + .tri_reg = PINGROUP_REG(r), \ + .tri_bank = 1, \ + .tri_bit = 4, \ + .einput_bit = 6, \ + .odrain_bit = 11, \ + .lock_bit = 7, \ + .ioreset_bit = -1, \ + .rcv_sel_bit = PINGROUP_BIT_##e_io_hv(10), \ + .hsm_bit = PINGROUP_BIT_##hsm(9), \ + .schmitt_bit = 12, \ + .drvtype_bit = PINGROUP_BIT_##drvtype(13), \ + .drv_reg = DRV_PINGROUP_REG(rdrv), \ + .drv_bank = 0, \ + .lpmd_bit = -1, \ + .drvdn_bit = drvdn_b, \ + .drvdn_width = drvdn_w, \ + .drvup_bit = drvup_b, \ + .drvup_width = drvup_w, \ + .slwr_bit = slwr_b, \ + .slwr_width = slwr_w, \ + .slwf_bit = slwf_b, \ + .slwf_width = slwf_w, \ + } + +#define DRV_PINGROUP(pg_name, r, drvdn_b, drvdn_w, drvup_b, drvup_w, \ + slwr_b, slwr_w, slwf_b, slwf_w) \ + { \ + .name = "drive_" #pg_name, \ + .pins = drive_##pg_name##_pins, \ + .npins = ARRAY_SIZE(drive_##pg_name##_pins), \ + .mux_reg = -1, \ + .pupd_reg = -1, \ + .tri_reg = -1, \ + .einput_bit = -1, \ + .odrain_bit = -1, \ + .lock_bit = -1, \ + .ioreset_bit = -1, \ + .rcv_sel_bit = -1, \ + .drv_reg = DRV_PINGROUP_REG(r), \ + .drv_bank = 0, \ + .hsm_bit = -1, \ + .schmitt_bit = -1, \ + .lpmd_bit = -1, \ + .drvdn_bit = drvdn_b, \ + .drvdn_width = drvdn_w, \ + .drvup_bit = drvup_b, \ + .drvup_width = drvup_w, \ + .slwr_bit = slwr_b, \ + .slwr_width = slwr_w, \ + .slwf_bit = slwf_b, \ + .slwf_width = slwf_w, \ + .drvtype_bit = -1, \ + } + +static const struct tegra_pingroup tegra210_groups[] = { + /* pg_name, f0, f1, f2, f3, r, hsm, drvtype, e_io_hv, rdrv, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */ + PINGROUP(sdmmc1_clk_pm0, SDMMC1, RSVD1, RSVD2, RSVD3, 0x3000, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(sdmmc1_cmd_pm1, SDMMC1, SPI3, RSVD2, RSVD3, 0x3004, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(sdmmc1_dat3_pm2, SDMMC1, SPI3, RSVD2, RSVD3, 0x3008, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(sdmmc1_dat2_pm3, SDMMC1, SPI3, RSVD2, RSVD3, 0x300c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(sdmmc1_dat1_pm4, SDMMC1, SPI3, RSVD2, RSVD3, 0x3010, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(sdmmc1_dat0_pm5, SDMMC1, RSVD1, RSVD2, RSVD3, 0x3014, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(sdmmc3_clk_pp0, SDMMC3, RSVD1, RSVD2, RSVD3, 0x301c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(sdmmc3_cmd_pp1, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3020, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(sdmmc3_dat0_pp5, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3024, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(sdmmc3_dat1_pp4, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3028, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(sdmmc3_dat2_pp3, SDMMC3, RSVD1, RSVD2, RSVD3, 0x302c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(sdmmc3_dat3_pp2, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3030, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(pex_l0_rst_n_pa0, PE0, RSVD1, RSVD2, RSVD3, 0x3038, N, N, Y, 0xa5c, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(pex_l0_clkreq_n_pa1, PE0, RSVD1, RSVD2, RSVD3, 0x303c, N, N, Y, 0xa58, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(pex_wake_n_pa2, PE, RSVD1, RSVD2, RSVD3, 0x3040, N, N, Y, 0xa68, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(pex_l1_rst_n_pa3, PE1, RSVD1, RSVD2, RSVD3, 0x3044, N, N, Y, 0xa64, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(pex_l1_clkreq_n_pa4, PE1, RSVD1, RSVD2, RSVD3, 0x3048, N, N, Y, 0xa60, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(sata_led_active_pa5, SATA, RSVD1, RSVD2, RSVD3, 0x304c, N, N, N, 0xa94, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(spi1_mosi_pc0, SPI1, RSVD1, RSVD2, RSVD3, 0x3050, Y, Y, N, 0xae0, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(spi1_miso_pc1, SPI1, RSVD1, RSVD2, RSVD3, 0x3054, Y, Y, N, 0xadc, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(spi1_sck_pc2, SPI1, RSVD1, RSVD2, RSVD3, 0x3058, Y, Y, N, 0xae4, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(spi1_cs0_pc3, SPI1, RSVD1, RSVD2, RSVD3, 0x305c, Y, Y, N, 0xad4, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(spi1_cs1_pc4, SPI1, RSVD1, RSVD2, RSVD3, 0x3060, Y, Y, N, 0xad8, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(spi2_mosi_pb4, SPI2, DTV, RSVD2, RSVD3, 0x3064, Y, Y, N, 0xaf4, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(spi2_miso_pb5, SPI2, DTV, RSVD2, RSVD3, 0x3068, Y, Y, N, 0xaf0, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(spi2_sck_pb6, SPI2, DTV, RSVD2, RSVD3, 0x306c, Y, Y, N, 0xaf8, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(spi2_cs0_pb7, SPI2, DTV, RSVD2, RSVD3, 0x3070, Y, Y, N, 0xae8, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(spi2_cs1_pdd0, SPI2, RSVD1, RSVD2, RSVD3, 0x3074, Y, Y, N, 0xaec, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(spi4_mosi_pc7, SPI4, RSVD1, RSVD2, RSVD3, 0x3078, Y, Y, N, 0xb04, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(spi4_miso_pd0, SPI4, RSVD1, RSVD2, RSVD3, 0x307c, Y, Y, N, 0xb00, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(spi4_sck_pc5, SPI4, RSVD1, RSVD2, RSVD3, 0x3080, Y, Y, N, 0xb08, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(spi4_cs0_pc6, SPI4, RSVD1, RSVD2, RSVD3, 0x3084, Y, Y, N, 0xafc, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(qspi_sck_pee0, QSPI, RSVD1, RSVD2, RSVD3, 0x3088, Y, Y, N, 0xa90, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(qspi_cs_n_pee1, QSPI, RSVD1, RSVD2, RSVD3, 0x308c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(qspi_io0_pee2, QSPI, RSVD1, RSVD2, RSVD3, 0x3090, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(qspi_io1_pee3, QSPI, RSVD1, RSVD2, RSVD3, 0x3094, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(qspi_io2_pee4, QSPI, RSVD1, RSVD2, RSVD3, 0x3098, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(qspi_io3_pee5, QSPI, RSVD1, RSVD2, RSVD3, 0x309c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(dmic1_clk_pe0, DMIC1, I2S3, RSVD2, RSVD3, 0x30a4, N, N, N, 0x984, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(dmic1_dat_pe1, DMIC1, I2S3, RSVD2, RSVD3, 0x30a8, N, N, N, 0x988, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(dmic2_clk_pe2, DMIC2, I2S3, RSVD2, RSVD3, 0x30ac, N, N, N, 0x98c, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(dmic2_dat_pe3, DMIC2, I2S3, RSVD2, RSVD3, 0x30b0, N, N, N, 0x990, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(dmic3_clk_pe4, DMIC3, I2S5A, RSVD2, RSVD3, 0x30b4, N, N, N, 0x994, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(dmic3_dat_pe5, DMIC3, I2S5A, RSVD2, RSVD3, 0x30b8, N, N, N, 0x998, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(gen1_i2c_scl_pj1, I2C1, RSVD1, RSVD2, RSVD3, 0x30bc, N, N, Y, 0x9a8, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(gen1_i2c_sda_pj0, I2C1, RSVD1, RSVD2, RSVD3, 0x30c0, N, N, Y, 0x9ac, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(gen2_i2c_scl_pj2, I2C2, RSVD1, RSVD2, RSVD3, 0x30c4, N, N, Y, 0x9b0, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(gen2_i2c_sda_pj3, I2C2, RSVD1, RSVD2, RSVD3, 0x30c8, N, N, Y, 0x9b4, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(gen3_i2c_scl_pf0, I2C3, RSVD1, RSVD2, RSVD3, 0x30cc, N, N, Y, 0x9b8, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(gen3_i2c_sda_pf1, I2C3, RSVD1, RSVD2, RSVD3, 0x30d0, N, N, Y, 0x9bc, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(cam_i2c_scl_ps2, I2C3, I2CVI, RSVD2, RSVD3, 0x30d4, N, N, Y, 0x934, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(cam_i2c_sda_ps3, I2C3, I2CVI, RSVD2, RSVD3, 0x30d8, N, N, Y, 0x938, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(pwr_i2c_scl_py3, I2CPMU, RSVD1, RSVD2, RSVD3, 0x30dc, N, N, Y, 0xa6c, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(pwr_i2c_sda_py4, I2CPMU, RSVD1, RSVD2, RSVD3, 0x30e0, N, N, Y, 0xa70, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(uart1_tx_pu0, UARTA, RSVD1, RSVD2, RSVD3, 0x30e4, N, N, N, 0xb28, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(uart1_rx_pu1, UARTA, RSVD1, RSVD2, RSVD3, 0x30e8, N, N, N, 0xb24, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(uart1_rts_pu2, UARTA, RSVD1, RSVD2, RSVD3, 0x30ec, N, N, N, 0xb20, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(uart1_cts_pu3, UARTA, RSVD1, RSVD2, RSVD3, 0x30f0, N, N, N, 0xb1c, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(uart2_tx_pg0, UARTB, I2S4A, SPDIF, UART, 0x30f4, N, N, N, 0xb38, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(uart2_rx_pg1, UARTB, I2S4A, SPDIF, UART, 0x30f8, N, N, N, 0xb34, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(uart2_rts_pg2, UARTB, I2S4A, RSVD2, UART, 0x30fc, N, N, N, 0xb30, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(uart2_cts_pg3, UARTB, I2S4A, RSVD2, UART, 0x3100, N, N, N, 0xb2c, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(uart3_tx_pd1, UARTC, SPI4, RSVD2, RSVD3, 0x3104, N, N, N, 0xb48, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(uart3_rx_pd2, UARTC, SPI4, RSVD2, RSVD3, 0x3108, N, N, N, 0xb44, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(uart3_rts_pd3, UARTC, SPI4, RSVD2, RSVD3, 0x310c, N, N, N, 0xb40, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(uart3_cts_pd4, UARTC, SPI4, RSVD2, RSVD3, 0x3110, N, N, N, 0xb3c, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(uart4_tx_pi4, UARTD, UART, RSVD2, RSVD3, 0x3114, N, N, N, 0xb58, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(uart4_rx_pi5, UARTD, UART, RSVD2, RSVD3, 0x3118, N, N, N, 0xb54, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(uart4_rts_pi6, UARTD, UART, RSVD2, RSVD3, 0x311c, N, N, N, 0xb50, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(uart4_cts_pi7, UARTD, UART, RSVD2, RSVD3, 0x3120, N, N, N, 0xb4c, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(dap1_fs_pb0, I2S1, RSVD1, RSVD2, RSVD3, 0x3124, Y, Y, N, 0x95c, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(dap1_din_pb1, I2S1, RSVD1, RSVD2, RSVD3, 0x3128, Y, Y, N, 0x954, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(dap1_dout_pb2, I2S1, RSVD1, RSVD2, RSVD3, 0x312c, Y, Y, N, 0x958, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(dap1_sclk_pb3, I2S1, RSVD1, RSVD2, RSVD3, 0x3130, Y, Y, N, 0x960, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(dap2_fs_paa0, I2S2, RSVD1, RSVD2, RSVD3, 0x3134, Y, Y, N, 0x96c, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(dap2_din_paa2, I2S2, RSVD1, RSVD2, RSVD3, 0x3138, Y, Y, N, 0x964, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(dap2_dout_paa3, I2S2, RSVD1, RSVD2, RSVD3, 0x313c, Y, Y, N, 0x968, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(dap2_sclk_paa1, I2S2, RSVD1, RSVD2, RSVD3, 0x3140, Y, Y, N, 0x970, -1, -1, -1, -1, 28, 2, 30, 2), + PINGROUP(dap4_fs_pj4, I2S4B, RSVD1, RSVD2, RSVD3, 0x3144, N, N, N, 0x97c, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(dap4_din_pj5, I2S4B, RSVD1, RSVD2, RSVD3, 0x3148, N, N, N, 0x974, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(dap4_dout_pj6, I2S4B, RSVD1, RSVD2, RSVD3, 0x314c, N, N, N, 0x978, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(dap4_sclk_pj7, I2S4B, RSVD1, RSVD2, RSVD3, 0x3150, N, N, N, 0x980, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(cam1_mclk_ps0, EXTPERIPH3, RSVD1, RSVD2, RSVD3, 0x3154, N, N, N, 0x918, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(cam2_mclk_ps1, EXTPERIPH3, RSVD1, RSVD2, RSVD3, 0x3158, N, N, N, 0x924, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(jtag_rtck, JTAG, RSVD1, RSVD2, RSVD3, 0x315c, N, N, N, 0xa2c, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(clk_32k_in, CLK, RSVD1, RSVD2, RSVD3, 0x3160, N, N, N, 0x940, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(clk_32k_out_py5, SOC, BLINK, RSVD2, RSVD3, 0x3164, N, N, N, 0x944, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(batt_bcl, BCL, RSVD1, RSVD2, RSVD3, 0x3168, N, N, Y, 0x8f8, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(clk_req, SYS, RSVD1, RSVD2, RSVD3, 0x316c, N, N, N, 0x948, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(cpu_pwr_req, CPU, RSVD1, RSVD2, RSVD3, 0x3170, N, N, N, 0x950, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(pwr_int_n, PMI, RSVD1, RSVD2, RSVD3, 0x3174, N, N, N, 0xa74, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(shutdown, SHUTDOWN, RSVD1, RSVD2, RSVD3, 0x3178, N, N, N, 0xac8, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(core_pwr_req, CORE, RSVD1, RSVD2, RSVD3, 0x317c, N, N, N, 0x94c, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(aud_mclk_pbb0, AUD, RSVD1, RSVD2, RSVD3, 0x3180, N, N, N, 0x8f4, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(dvfs_pwm_pbb1, RSVD0, CLDVFS, SPI3, RSVD3, 0x3184, N, N, N, 0x9a4, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(dvfs_clk_pbb2, RSVD0, CLDVFS, SPI3, RSVD3, 0x3188, N, N, N, 0x9a0, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(gpio_x1_aud_pbb3, RSVD0, RSVD1, SPI3, RSVD3, 0x318c, N, N, N, 0xa14, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(gpio_x3_aud_pbb4, RSVD0, RSVD1, SPI3, RSVD3, 0x3190, N, N, N, 0xa18, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(pcc7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3194, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(hdmi_cec_pcc0, CEC, RSVD1, RSVD2, RSVD3, 0x3198, N, N, Y, 0xa24, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(hdmi_int_dp_hpd_pcc1, DP, RSVD1, RSVD2, RSVD3, 0x319c, N, N, Y, 0xa28, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(spdif_out_pcc2, SPDIF, RSVD1, RSVD2, RSVD3, 0x31a0, N, N, N, 0xad0, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(spdif_in_pcc3, SPDIF, RSVD1, RSVD2, RSVD3, 0x31a4, N, N, N, 0xacc, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(usb_vbus_en0_pcc4, USB, RSVD1, RSVD2, RSVD3, 0x31a8, N, N, Y, 0xb5c, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(usb_vbus_en1_pcc5, USB, RSVD1, RSVD2, RSVD3, 0x31ac, N, N, Y, 0xb60, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(dp_hpd0_pcc6, DP, RSVD1, RSVD2, RSVD3, 0x31b0, N, N, N, 0x99c, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(wifi_en_ph0, RSVD0, RSVD1, RSVD2, RSVD3, 0x31b4, N, N, N, 0xb64, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(wifi_rst_ph1, RSVD0, RSVD1, RSVD2, RSVD3, 0x31b8, N, N, N, 0xb68, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(wifi_wake_ap_ph2, RSVD0, RSVD1, RSVD2, RSVD3, 0x31bc, N, N, N, 0xb6c, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(ap_wake_bt_ph3, RSVD0, UARTB, SPDIF, RSVD3, 0x31c0, N, N, N, 0x8ec, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(bt_rst_ph4, RSVD0, UARTB, SPDIF, RSVD3, 0x31c4, N, N, N, 0x8fc, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(bt_wake_ap_ph5, RSVD0, RSVD1, RSVD2, RSVD3, 0x31c8, N, N, N, 0x900, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(ap_wake_nfc_ph7, RSVD0, RSVD1, RSVD2, RSVD3, 0x31cc, N, N, N, 0x8f0, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(nfc_en_pi0, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d0, N, N, N, 0xa50, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(nfc_int_pi1, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d4, N, N, N, 0xa54, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(gps_en_pi2, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d8, N, N, N, 0xa1c, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(gps_rst_pi3, RSVD0, RSVD1, RSVD2, RSVD3, 0x31dc, N, N, N, 0xa20, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(cam_rst_ps4, VGP1, RSVD1, RSVD2, RSVD3, 0x31e0, N, N, N, 0x93c, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(cam_af_en_ps5, VIMCLK, VGP2, RSVD2, RSVD3, 0x31e4, N, N, N, 0x92c, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(cam_flash_en_ps6, VIMCLK, VGP3, RSVD2, RSVD3, 0x31e8, N, N, N, 0x930, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(cam1_pwdn_ps7, VGP4, RSVD1, RSVD2, RSVD3, 0x31ec, N, N, N, 0x91c, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(cam2_pwdn_pt0, VGP5, RSVD1, RSVD2, RSVD3, 0x31f0, N, N, N, 0x928, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(cam1_strobe_pt1, VGP6, RSVD1, RSVD2, RSVD3, 0x31f4, N, N, N, 0x920, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(lcd_te_py2, DISPLAYA, RSVD1, RSVD2, RSVD3, 0x31f8, N, N, N, 0xa44, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(lcd_bl_pwm_pv0, DISPLAYA, PWM0, SOR0, RSVD3, 0x31fc, N, N, N, 0xa34, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(lcd_bl_en_pv1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3200, N, N, N, 0xa30, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(lcd_rst_pv2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3204, N, N, N, 0xa40, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(lcd_gpio1_pv3, DISPLAYB, RSVD1, RSVD2, RSVD3, 0x3208, N, N, N, 0xa38, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(lcd_gpio2_pv4, DISPLAYB, PWM1, RSVD2, SOR1, 0x320c, N, N, N, 0xa3c, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(ap_ready_pv5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3210, N, N, N, 0x8e8, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(touch_rst_pv6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3214, N, N, N, 0xb18, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(touch_clk_pv7, TOUCH, RSVD1, RSVD2, RSVD3, 0x3218, N, N, N, 0xb10, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(modem_wake_ap_px0, RSVD0, RSVD1, RSVD2, RSVD3, 0x321c, N, N, N, 0xa48, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(touch_int_px1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3220, N, N, N, 0xb14, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(motion_int_px2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3224, N, N, N, 0xa4c, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(als_prox_int_px3, RSVD0, RSVD1, RSVD2, RSVD3, 0x3228, N, N, N, 0x8e4, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(temp_alert_px4, RSVD0, RSVD1, RSVD2, RSVD3, 0x322c, N, N, N, 0xb0c, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(button_power_on_px5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3230, N, N, N, 0x908, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(button_vol_up_px6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3234, N, N, N, 0x914, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(button_vol_down_px7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3238, N, N, N, 0x910, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(button_slide_sw_py0, RSVD0, RSVD1, RSVD2, RSVD3, 0x323c, N, N, N, 0x90c, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(button_home_py1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3240, N, N, N, 0x904, 12, 5, 20, 5, -1, -1, -1, -1), + PINGROUP(pa6, SATA, RSVD1, RSVD2, RSVD3, 0x3244, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(pe6, RSVD0, I2S5A, PWM2, RSVD3, 0x3248, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(pe7, RSVD0, I2S5A, PWM3, RSVD3, 0x324c, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(ph6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3250, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(pk0, IQC0, I2S5B, RSVD2, RSVD3, 0x3254, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(pk1, IQC0, I2S5B, RSVD2, RSVD3, 0x3258, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(pk2, IQC0, I2S5B, RSVD2, RSVD3, 0x325c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(pk3, IQC0, I2S5B, RSVD2, RSVD3, 0x3260, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(pk4, IQC1, RSVD1, RSVD2, RSVD3, 0x3264, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(pk5, IQC1, RSVD1, RSVD2, RSVD3, 0x3268, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(pk6, IQC1, RSVD1, RSVD2, RSVD3, 0x326c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(pk7, IQC1, RSVD1, RSVD2, RSVD3, 0x3270, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(pl0, RSVD0, RSVD1, RSVD2, RSVD3, 0x3274, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(pl1, SOC, RSVD1, RSVD2, RSVD3, 0x3278, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(pz0, VIMCLK2, RSVD1, RSVD2, RSVD3, 0x327c, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(pz1, VIMCLK2, SDMMC1, RSVD2, RSVD3, 0x3280, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(pz2, SDMMC3, CCLA, RSVD2, RSVD3, 0x3284, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(pz3, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3288, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(pz4, SDMMC1, RSVD1, RSVD2, RSVD3, 0x328c, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(pz5, SOC, RSVD1, RSVD2, RSVD3, 0x3290, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), + + /* pg_name, r, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */ + DRV_PINGROUP(pa6, 0x9c0, 12, 5, 20, 5, -1, -1, -1, -1), + DRV_PINGROUP(pcc7, 0x9c4, 12, 5, 20, 5, -1, -1, -1, -1), + DRV_PINGROUP(pe6, 0x9c8, 12, 5, 20, 5, -1, -1, -1, -1), + DRV_PINGROUP(pe7, 0x9cc, 12, 5, 20, 5, -1, -1, -1, -1), + DRV_PINGROUP(ph6, 0x9d0, 12, 5, 20, 5, -1, -1, -1, -1), + DRV_PINGROUP(pk0, 0x9d4, -1, -1, -1, -1, 28, 2, 30, 2), + DRV_PINGROUP(pk1, 0x9d8, -1, -1, -1, -1, 28, 2, 30, 2), + DRV_PINGROUP(pk2, 0x9dc, -1, -1, -1, -1, 28, 2, 30, 2), + DRV_PINGROUP(pk3, 0x9e0, -1, -1, -1, -1, 28, 2, 30, 2), + DRV_PINGROUP(pk4, 0x9e4, -1, -1, -1, -1, 28, 2, 30, 2), + DRV_PINGROUP(pk5, 0x9e8, -1, -1, -1, -1, 28, 2, 30, 2), + DRV_PINGROUP(pk6, 0x9ec, -1, -1, -1, -1, 28, 2, 30, 2), + DRV_PINGROUP(pk7, 0x9f0, -1, -1, -1, -1, 28, 2, 30, 2), + DRV_PINGROUP(pl0, 0x9f4, -1, -1, -1, -1, 28, 2, 30, 2), + DRV_PINGROUP(pl1, 0x9f8, -1, -1, -1, -1, 28, 2, 30, 2), + DRV_PINGROUP(pz0, 0x9fc, 12, 7, 20, 7, -1, -1, -1, -1), + DRV_PINGROUP(pz1, 0xa00, 12, 7, 20, 7, -1, -1, -1, -1), + DRV_PINGROUP(pz2, 0xa04, 12, 7, 20, 7, -1, -1, -1, -1), + DRV_PINGROUP(pz3, 0xa08, 12, 7, 20, 7, -1, -1, -1, -1), + DRV_PINGROUP(pz4, 0xa0c, 12, 7, 20, 7, -1, -1, -1, -1), + DRV_PINGROUP(pz5, 0xa10, 12, 7, 20, 7, -1, -1, -1, -1), + DRV_PINGROUP(sdmmc1, 0xa98, 12, 7, 20, 7, 28, 2, 30, 2), + DRV_PINGROUP(sdmmc2, 0xa9c, 2, 6, 8, 6, 28, 2, 30, 2), + DRV_PINGROUP(sdmmc3, 0xab0, 12, 7, 20, 7, 28, 2, 30, 2), + DRV_PINGROUP(sdmmc4, 0xab4, 2, 6, 8, 6, 28, 2, 30, 2), +}; + +static const struct tegra_pinctrl_soc_data tegra210_pinctrl = { + .ngpios = NUM_GPIOS, + .pins = tegra210_pins, + .npins = ARRAY_SIZE(tegra210_pins), + .functions = tegra210_functions, + .nfunctions = ARRAY_SIZE(tegra210_functions), + .groups = tegra210_groups, + .ngroups = ARRAY_SIZE(tegra210_groups), + .hsm_in_mux = true, + .schmitt_in_mux = true, + .drvtype_in_mux = true, +}; + +static int tegra210_pinctrl_probe(struct platform_device *pdev) +{ + return tegra_pinctrl_probe(pdev, &tegra210_pinctrl); +} + +static const struct of_device_id tegra210_pinctrl_of_match[] = { + { .compatible = "nvidia,tegra210-pinmux", }, + { }, +}; +MODULE_DEVICE_TABLE(of, tegra210_pinctrl_of_match); + +static struct platform_driver tegra210_pinctrl_driver = { + .driver = { + .name = "tegra210-pinctrl", + .of_match_table = tegra210_pinctrl_of_match, + }, + .probe = tegra210_pinctrl_probe, + .remove = tegra_pinctrl_remove, +}; +module_platform_driver(tegra210_pinctrl_driver); + +MODULE_AUTHOR("NVIDIA"); +MODULE_DESCRIPTION("NVIDIA Tegra210 pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c index f6edc2ff5494..47b2fd8bb2e9 100644 --- a/drivers/pinctrl/pinctrl-tegra30.c +++ b/drivers/pinctrl/pinctrl-tegra30.c @@ -2108,70 +2108,69 @@ static struct tegra_function tegra30_functions[] = { #define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ #define PINGROUP_REG_A 0x3000 /* bank 1 */ +#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A) #define PINGROUP_REG(r) ((r) - PINGROUP_REG_A) #define PINGROUP_BIT_Y(b) (b) #define PINGROUP_BIT_N(b) (-1) -#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior) \ - { \ - .name = #pg_name, \ - .pins = pg_name##_pins, \ - .npins = ARRAY_SIZE(pg_name##_pins), \ - .funcs = { \ - TEGRA_MUX_##f0, \ - TEGRA_MUX_##f1, \ - TEGRA_MUX_##f2, \ - TEGRA_MUX_##f3, \ - }, \ - .mux_reg = PINGROUP_REG(r), \ - .mux_bank = 1, \ - .mux_bit = 0, \ - .pupd_reg = PINGROUP_REG(r), \ - .pupd_bank = 1, \ - .pupd_bit = 2, \ - .tri_reg = PINGROUP_REG(r), \ - .tri_bank = 1, \ - .tri_bit = 4, \ - .einput_bit = PINGROUP_BIT_Y(5), \ - .odrain_bit = PINGROUP_BIT_##od(6), \ - .lock_bit = PINGROUP_BIT_Y(7), \ - .ioreset_bit = PINGROUP_BIT_##ior(8), \ - .rcv_sel_bit = -1, \ - .drv_reg = -1, \ +#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .funcs = { \ + TEGRA_MUX_##f0, \ + TEGRA_MUX_##f1, \ + TEGRA_MUX_##f2, \ + TEGRA_MUX_##f3, \ + }, \ + .mux_reg = PINGROUP_REG(r), \ + .mux_bank = 1, \ + .mux_bit = 0, \ + .pupd_reg = PINGROUP_REG(r), \ + .pupd_bank = 1, \ + .pupd_bit = 2, \ + .tri_reg = PINGROUP_REG(r), \ + .tri_bank = 1, \ + .tri_bit = 4, \ + .einput_bit = 5, \ + .odrain_bit = PINGROUP_BIT_##od(6), \ + .lock_bit = 7, \ + .ioreset_bit = PINGROUP_BIT_##ior(8), \ + .rcv_sel_bit = -1, \ + .drv_reg = -1, \ } -#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A) - -#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ - drvdn_b, drvdn_w, drvup_b, drvup_w, \ - slwr_b, slwr_w, slwf_b, slwf_w) \ - { \ - .name = "drive_" #pg_name, \ - .pins = drive_##pg_name##_pins, \ - .npins = ARRAY_SIZE(drive_##pg_name##_pins), \ - .mux_reg = -1, \ - .pupd_reg = -1, \ - .tri_reg = -1, \ - .einput_bit = -1, \ - .odrain_bit = -1, \ - .lock_bit = -1, \ - .ioreset_bit = -1, \ - .rcv_sel_bit = -1, \ - .drv_reg = DRV_PINGROUP_REG(r), \ - .drv_bank = 0, \ - .hsm_bit = hsm_b, \ - .schmitt_bit = schmitt_b, \ - .lpmd_bit = lpmd_b, \ - .drvdn_bit = drvdn_b, \ - .drvdn_width = drvdn_w, \ - .drvup_bit = drvup_b, \ - .drvup_width = drvup_w, \ - .slwr_bit = slwr_b, \ - .slwr_width = slwr_w, \ - .slwf_bit = slwf_b, \ - .slwf_width = slwf_w, \ - .drvtype_bit = -1, \ +#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \ + drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \ + slwf_b, slwf_w) \ + { \ + .name = "drive_" #pg_name, \ + .pins = drive_##pg_name##_pins, \ + .npins = ARRAY_SIZE(drive_##pg_name##_pins), \ + .mux_reg = -1, \ + .pupd_reg = -1, \ + .tri_reg = -1, \ + .einput_bit = -1, \ + .odrain_bit = -1, \ + .lock_bit = -1, \ + .ioreset_bit = -1, \ + .rcv_sel_bit = -1, \ + .drv_reg = DRV_PINGROUP_REG(r), \ + .drv_bank = 0, \ + .hsm_bit = hsm_b, \ + .schmitt_bit = schmitt_b, \ + .lpmd_bit = lpmd_b, \ + .drvdn_bit = drvdn_b, \ + .drvdn_width = drvdn_w, \ + .drvup_bit = drvup_b, \ + .drvup_width = drvup_w, \ + .slwr_bit = slwr_b, \ + .slwr_width = slwr_w, \ + .slwf_bit = slwf_b, \ + .slwf_width = slwf_w, \ + .drvtype_bit = -1, \ } static const struct tegra_pingroup tegra30_groups[] = { @@ -2477,6 +2476,9 @@ static const struct tegra_pinctrl_soc_data tegra30_pinctrl = { .nfunctions = ARRAY_SIZE(tegra30_functions), .groups = tegra30_groups, .ngroups = ARRAY_SIZE(tegra30_groups), + .hsm_in_mux = false, + .schmitt_in_mux = false, + .drvtype_in_mux = false, }; static int tegra30_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/pinctrl-tz1090-pdc.c b/drivers/pinctrl/pinctrl-tz1090-pdc.c index fab6aafa6a9f..8a8911bb883a 100644 --- a/drivers/pinctrl/pinctrl-tz1090-pdc.c +++ b/drivers/pinctrl/pinctrl-tz1090-pdc.c @@ -969,7 +969,7 @@ static int tz1090_pdc_pinctrl_remove(struct platform_device *pdev) return 0; } -static struct of_device_id tz1090_pdc_pinctrl_of_match[] = { +static const struct of_device_id tz1090_pdc_pinctrl_of_match[] = { { .compatible = "img,tz1090-pdc-pinctrl", }, { }, }; diff --git a/drivers/pinctrl/pinctrl-tz1090.c b/drivers/pinctrl/pinctrl-tz1090.c index 8bd73075f9dd..fc5594a530c2 100644 --- a/drivers/pinctrl/pinctrl-tz1090.c +++ b/drivers/pinctrl/pinctrl-tz1090.c @@ -1984,7 +1984,7 @@ static int tz1090_pinctrl_remove(struct platform_device *pdev) return 0; } -static struct of_device_id tz1090_pinctrl_of_match[] = { +static const struct of_device_id tz1090_pinctrl_of_match[] = { { .compatible = "img,tz1090-pinctrl", }, { }, }; diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index a535f9c23678..f3d800f796c2 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -193,11 +193,11 @@ static int msm_config_reg(struct msm_pinctrl *pctrl, *mask = 7; break; case PIN_CONFIG_OUTPUT: + case PIN_CONFIG_INPUT_ENABLE: *bit = g->oe_bit; *mask = 1; break; default: - dev_err(pctrl->dev, "Invalid config param %04x\n", param); return -ENOTSUPP; } @@ -261,10 +261,14 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev, val = readl(pctrl->regs + g->io_reg); arg = !!(val & BIT(g->in_bit)); break; + case PIN_CONFIG_INPUT_ENABLE: + /* Pin is output */ + if (arg) + return -EINVAL; + arg = 1; + break; default: - dev_err(pctrl->dev, "Unsupported config parameter: %x\n", - param); - return -EINVAL; + return -ENOTSUPP; } *config = pinconf_to_config_packed(param, arg); @@ -333,6 +337,10 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev, /* enable output */ arg = 1; break; + case PIN_CONFIG_INPUT_ENABLE: + /* disable output */ + arg = 0; + break; default: dev_err(pctrl->dev, "Unsupported config parameter: %x\n", param); @@ -357,6 +365,7 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev, } static const struct pinconf_ops msm_pinconf_ops = { + .is_generic = true, .pin_config_group_get = msm_config_group_get, .pin_config_group_set = msm_config_group_set, }; diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 0f11a26d932b..b2d22218a258 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -810,6 +810,7 @@ static int pmic_gpio_remove(struct platform_device *pdev) } static const struct of_device_id pmic_gpio_of_match[] = { + { .compatible = "qcom,pm8916-gpio" }, /* 4 GPIO's */ { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */ { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */ { }, diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index a8924dba335e..8f36c5f91949 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -925,6 +925,7 @@ static int pmic_mpp_remove(struct platform_device *pdev) static const struct of_device_id pmic_mpp_of_match[] = { { .compatible = "qcom,pm8841-mpp" }, /* 4 MPP's */ + { .compatible = "qcom,pm8916-mpp" }, /* 4 MPP's */ { .compatible = "qcom,pm8941-mpp" }, /* 8 MPP's */ { .compatible = "qcom,pma8084-mpp" }, /* 8 MPP's */ { }, diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index c8f83f96546c..0b7afa50121a 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -1240,6 +1240,159 @@ const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = { }, }; +/* pin banks of exynos5433 pin-controller - ALIVE */ +static const struct samsung_pin_bank_data exynos5433_pin_banks0[] = { + EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), +}; + +/* pin banks of exynos5433 pin-controller - AUD */ +static const struct samsung_pin_bank_data exynos5433_pin_banks1[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), +}; + +/* pin banks of exynos5433 pin-controller - CPIF */ +static const struct samsung_pin_bank_data exynos5433_pin_banks2[] = { + EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00), +}; + +/* pin banks of exynos5433 pin-controller - eSE */ +static const struct samsung_pin_bank_data exynos5433_pin_banks3[] = { + EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00), +}; + +/* pin banks of exynos5433 pin-controller - FINGER */ +static const struct samsung_pin_bank_data exynos5433_pin_banks4[] = { + EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00), +}; + +/* pin banks of exynos5433 pin-controller - FSYS */ +static const struct samsung_pin_bank_data exynos5433_pin_banks5[] = { + EXYNOS_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00), + EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04), + EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14), +}; + +/* pin banks of exynos5433 pin-controller - IMEM */ +static const struct samsung_pin_bank_data exynos5433_pin_banks6[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00), +}; + +/* pin banks of exynos5433 pin-controller - NFC */ +static const struct samsung_pin_bank_data exynos5433_pin_banks7[] = { + EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), +}; + +/* pin banks of exynos5433 pin-controller - PERIC */ +static const struct samsung_pin_bank_data exynos5433_pin_banks8[] = { + EXYNOS_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00), + EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08), + EXYNOS_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c), + EXYNOS_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14), + EXYNOS_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18), + EXYNOS_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c), + EXYNOS_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20), + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24), + EXYNOS_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28), + EXYNOS_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c), + EXYNOS_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30), + EXYNOS_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34), + EXYNOS_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38), + EXYNOS_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c), + EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), +}; + +/* pin banks of exynos5433 pin-controller - TOUCH */ +static const struct samsung_pin_bank_data exynos5433_pin_banks9[] = { + EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), +}; + +/* + * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes + * ten gpio/pin-mux/pinconfig controllers. + */ +const struct samsung_pin_ctrl exynos5433_pin_ctrl[] = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5433_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0), + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5433_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5433_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 3 data */ + .pin_banks = exynos5433_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 4 data */ + .pin_banks = exynos5433_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 5 data */ + .pin_banks = exynos5433_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 6 data */ + .pin_banks = exynos5433_pin_banks6, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks6), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 7 data */ + .pin_banks = exynos5433_pin_banks7, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks7), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 8 data */ + .pin_banks = exynos5433_pin_banks8, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks8), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 9 data */ + .pin_banks = exynos5433_pin_banks9, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks9), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, +}; + /* pin banks of exynos7 pin-controller - ALIVE */ static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = { EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), @@ -1324,7 +1477,6 @@ const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = { /* pin-controller instance 0 Alive data */ .pin_banks = exynos7_pin_banks0, .nr_banks = ARRAY_SIZE(exynos7_pin_banks0), - .eint_gpio_init = exynos_eint_gpio_init, .eint_wkup_init = exynos_eint_wkup_init, }, { /* pin-controller instance 1 BUS0 data */ diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index ec580af35856..ed165ba2eb2f 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1239,6 +1239,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = (void *)exynos5260_pin_ctrl }, { .compatible = "samsung,exynos5420-pinctrl", .data = (void *)exynos5420_pin_ctrl }, + { .compatible = "samsung,exynos5433-pinctrl", + .data = (void *)exynos5433_pin_ctrl }, { .compatible = "samsung,s5pv210-pinctrl", .data = (void *)s5pv210_pin_ctrl }, { .compatible = "samsung,exynos7-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 1b8c0139d604..c1239ff6157d 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -271,6 +271,7 @@ extern const struct samsung_pin_ctrl exynos4415_pin_ctrl[]; extern const struct samsung_pin_ctrl exynos5250_pin_ctrl[]; extern const struct samsung_pin_ctrl exynos5260_pin_ctrl[]; extern const struct samsung_pin_ctrl exynos5420_pin_ctrl[]; +extern const struct samsung_pin_ctrl exynos5433_pin_ctrl[]; extern const struct samsung_pin_ctrl exynos7_pin_ctrl[]; extern const struct samsung_pin_ctrl s3c64xx_pin_ctrl[]; extern const struct samsung_pin_ctrl s3c2412_pin_ctrl[]; diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index a56280814a3f..7b2c9495c383 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -92,10 +92,10 @@ static int sh_pfc_map_resources(struct sh_pfc *pfc, return 0; } -static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, - unsigned long address) +static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg) { struct sh_pfc_window *window; + phys_addr_t address = reg; unsigned int i; /* scan through physical windows and convert address */ @@ -144,8 +144,7 @@ static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r) return 1; } -unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, - unsigned long reg_width) +u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width) { switch (reg_width) { case 8: @@ -160,8 +159,8 @@ unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, return 0; } -void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width, - unsigned long data) +void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width, + u32 data) { switch (reg_width) { case 8: @@ -180,10 +179,9 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width, static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, const struct pinmux_cfg_reg *crp, - unsigned long in_pos, - void __iomem **mapped_regp, - unsigned long *maskp, - unsigned long *posp) + unsigned int in_pos, + void __iomem **mapped_regp, u32 *maskp, + unsigned int *posp) { unsigned int k; @@ -202,15 +200,16 @@ static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, static void sh_pfc_write_config_reg(struct sh_pfc *pfc, const struct pinmux_cfg_reg *crp, - unsigned long field, unsigned long value) + unsigned int field, u32 value) { void __iomem *mapped_reg; - unsigned long mask, pos, data; + unsigned int pos; + u32 mask, data; sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); - dev_dbg(pfc->dev, "write_reg addr = %lx, value = %ld, field = %ld, " - "r_width = %ld, f_width = %ld\n", + dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, " + "r_width = %u, f_width = %u\n", crp->reg, value, field, crp->reg_width, crp->field_width); mask = ~(mask << pos); @@ -229,26 +228,28 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc, } static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id, - const struct pinmux_cfg_reg **crp, int *fieldp, - int *valuep) + const struct pinmux_cfg_reg **crp, + unsigned int *fieldp, u32 *valuep) { - const struct pinmux_cfg_reg *config_reg; - unsigned long r_width, f_width, curr_width, ncomb; - unsigned int k, m, n, pos, bit_pos; + unsigned int k = 0; - k = 0; while (1) { - config_reg = pfc->info->cfg_regs + k; - - r_width = config_reg->reg_width; - f_width = config_reg->field_width; + const struct pinmux_cfg_reg *config_reg = + pfc->info->cfg_regs + k; + unsigned int r_width = config_reg->reg_width; + unsigned int f_width = config_reg->field_width; + unsigned int curr_width; + unsigned int bit_pos; + unsigned int pos = 0; + unsigned int m = 0; if (!r_width) break; - pos = 0; - m = 0; for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) { + u32 ncomb; + u32 n; + if (f_width) curr_width = f_width; else @@ -297,11 +298,8 @@ static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos, int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) { - const struct pinmux_cfg_reg *cr = NULL; - u16 enum_id; const struct pinmux_range *range; - int in_range, pos, field, value; - int ret; + int pos = 0; switch (pinmux_type) { case PINMUX_TYPE_GPIO: @@ -321,13 +319,15 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) return -EINVAL; } - pos = 0; - enum_id = 0; - field = 0; - value = 0; - /* Iterate over all the configuration fields we need to update. */ while (1) { + const struct pinmux_cfg_reg *cr; + unsigned int field; + u16 enum_id; + u32 value; + int in_range; + int ret; + pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id); if (pos < 0) return pos; @@ -579,9 +579,6 @@ static int sh_pfc_remove(struct platform_device *pdev) } static const struct platform_device_id sh_pfc_id_table[] = { -#ifdef CONFIG_PINCTRL_PFC_EMEV2 - { "pfc-emev2", (kernel_ulong_t)&emev2_pinmux_info }, -#endif #ifdef CONFIG_PINCTRL_PFC_R8A73A4 { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info }, #endif @@ -594,12 +591,6 @@ static const struct platform_device_id sh_pfc_id_table[] = { #ifdef CONFIG_PINCTRL_PFC_R8A7779 { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A7790 - { "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info }, -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A7791 - { "pfc-r8a7791", (kernel_ulong_t)&r8a7791_pinmux_info }, -#endif #ifdef CONFIG_PINCTRL_PFC_SH7203 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info }, #endif diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index 6b59d63b9c01..6dc8a6fc2746 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -57,10 +57,9 @@ int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc); int sh_pfc_register_pinctrl(struct sh_pfc *pfc); int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc); -unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, - unsigned long reg_width); -void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width, - unsigned long data); +u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width); +void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width, + u32 data); int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin); int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type); diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 80f641ee4dea..ba353735ecf2 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -21,7 +21,7 @@ struct sh_pfc_gpio_data_reg { const struct pinmux_data_reg *info; - unsigned long shadow; + u32 shadow; }; struct sh_pfc_gpio_pin { @@ -59,19 +59,20 @@ static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int offset, *bit = gpio_pin->dbit; } -static unsigned long gpio_read_data_reg(struct sh_pfc_chip *chip, - const struct pinmux_data_reg *dreg) +static u32 gpio_read_data_reg(struct sh_pfc_chip *chip, + const struct pinmux_data_reg *dreg) { - void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt; + phys_addr_t address = dreg->reg; + void __iomem *mem = address - chip->mem->phys + chip->mem->virt; return sh_pfc_read_raw_reg(mem, dreg->reg_width); } static void gpio_write_data_reg(struct sh_pfc_chip *chip, - const struct pinmux_data_reg *dreg, - unsigned long value) + const struct pinmux_data_reg *dreg, u32 value) { - void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt; + phys_addr_t address = dreg->reg; + void __iomem *mem = address - chip->mem->phys + chip->mem->virt; sh_pfc_write_raw_reg(mem, dreg->reg_width, value); } @@ -85,7 +86,7 @@ static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned idx) unsigned int bit; unsigned int i; - for (i = 0, dreg = pfc->info->data_regs; dreg->reg; ++i, ++dreg) { + for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) { for (bit = 0; bit < dreg->reg_width; bit++) { if (dreg->enum_ids[bit] == pin->enum_id) { gpio_pin->dreg = i; @@ -154,17 +155,17 @@ static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset, int value) { struct sh_pfc_gpio_data_reg *reg; - unsigned long pos; unsigned int bit; + unsigned int pos; gpio_get_data_reg(chip, offset, ®, &bit); pos = reg->info->reg_width - (bit + 1); if (value) - set_bit(pos, ®->shadow); + reg->shadow |= BIT(pos); else - clear_bit(pos, ®->shadow); + reg->shadow &= ~BIT(pos); gpio_write_data_reg(chip, reg->info, reg->shadow); } @@ -186,8 +187,8 @@ static int gpio_pin_get(struct gpio_chip *gc, unsigned offset) { struct sh_pfc_chip *chip = gpio_to_pfc_chip(gc); struct sh_pfc_gpio_data_reg *reg; - unsigned long pos; unsigned int bit; + unsigned int pos; gpio_get_data_reg(chip, offset, ®, &bit); @@ -341,6 +342,7 @@ sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *), int sh_pfc_register_gpiochip(struct sh_pfc *pfc) { struct sh_pfc_chip *chip; + phys_addr_t address; unsigned int i; int ret; @@ -352,11 +354,12 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) * that covers the data registers. In that case don't try to handle * GPIOs. */ + address = pfc->info->data_regs[0].reg; for (i = 0; i < pfc->num_windows; ++i) { struct sh_pfc_window *window = &pfc->windows[i]; - if (pfc->info->data_regs[0].reg >= window->phys && - pfc->info->data_regs[0].reg < window->phys + window->size) + if (address >= window->phys && + address < window->phys + window->size) break; } diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 80c1843bb6ad..22a5470889f5 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -1799,6 +1799,81 @@ static const unsigned int audio_clkout_d_pins[] = { static const unsigned int audio_clkout_d_mux[] = { AUDIO_CLKOUT_D_MARK, }; +/* - AVB -------------------------------------------------------------------- */ +static const unsigned int avb_link_pins[] = { + RCAR_GP_PIN(3, 11), +}; +static const unsigned int avb_link_mux[] = { + AVB_LINK_MARK, +}; +static const unsigned int avb_magic_pins[] = { + RCAR_GP_PIN(2, 14), +}; +static const unsigned int avb_magic_mux[] = { + AVB_MAGIC_MARK, +}; +static const unsigned int avb_phy_int_pins[] = { + RCAR_GP_PIN(2, 15), +}; +static const unsigned int avb_phy_int_mux[] = { + AVB_PHY_INT_MARK, +}; +static const unsigned int avb_mdio_pins[] = { + RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), +}; +static const unsigned int avb_mdio_mux[] = { + AVB_MDC_MARK, AVB_MDIO_MARK, +}; +static const unsigned int avb_mii_pins[] = { + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), + RCAR_GP_PIN(0, 11), + + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), + RCAR_GP_PIN(2, 2), + + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 10), + RCAR_GP_PIN(3, 12), +}; +static const unsigned int avb_mii_mux[] = { + AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, + AVB_TXD3_MARK, + + AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, + AVB_RXD3_MARK, + + AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, + AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK, + AVB_COL_MARK, +}; +static const unsigned int avb_gmii_pins[] = { + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), + RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), + + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16), + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), + RCAR_GP_PIN(3, 12), +}; +static const unsigned int avb_gmii_mux[] = { + AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, + AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK, + AVB_TXD6_MARK, AVB_TXD7_MARK, + + AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, + AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK, + AVB_RXD6_MARK, AVB_RXD7_MARK, + + AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, + AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK, + AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, + AVB_COL_MARK, +}; /* - DU RGB ----------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ @@ -3823,6 +3898,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(audio_clkout_b), SH_PFC_PIN_GROUP(audio_clkout_c), SH_PFC_PIN_GROUP(audio_clkout_d), + SH_PFC_PIN_GROUP(avb_link), + SH_PFC_PIN_GROUP(avb_magic), + SH_PFC_PIN_GROUP(avb_phy_int), + SH_PFC_PIN_GROUP(avb_mdio), + SH_PFC_PIN_GROUP(avb_mii), + SH_PFC_PIN_GROUP(avb_gmii), SH_PFC_PIN_GROUP(du_rgb666), SH_PFC_PIN_GROUP(du_rgb888), SH_PFC_PIN_GROUP(du_clk_out_0), @@ -4101,6 +4182,15 @@ static const char * const audio_clk_groups[] = { "audio_clkout_d", }; +static const char * const avb_groups[] = { + "avb_link", + "avb_magic", + "avb_phy_int", + "avb_mdio", + "avb_mii", + "avb_gmii", +}; + static const char * const du_groups[] = { "du_rgb666", "du_rgb888", @@ -4507,6 +4597,7 @@ static const char * const vin3_groups[] = { static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(audio_clk), + SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(du), SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index c83728626906..c7508d5f6886 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -69,9 +69,10 @@ struct pinmux_func { }; struct pinmux_cfg_reg { - unsigned long reg, reg_width, field_width; + u32 reg; + u8 reg_width, field_width; const u16 *enum_ids; - const unsigned long *var_field_width; + const u8 *var_field_width; }; #define PINMUX_CFG_REG(name, r, r_width, f_width) \ @@ -80,12 +81,13 @@ struct pinmux_cfg_reg { #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ .reg = r, .reg_width = r_width, \ - .var_field_width = (const unsigned long [r_width]) \ + .var_field_width = (const u8 [r_width]) \ { var_fw0, var_fwn, 0 }, \ .enum_ids = (const u16 []) struct pinmux_data_reg { - unsigned long reg, reg_width; + u32 reg; + u8 reg_width; const u16 *enum_ids; }; @@ -148,7 +150,7 @@ struct sh_pfc_soc_info { const struct pinmux_irq *gpio_irq; unsigned int gpio_irq_size; - unsigned long unlock_reg; + u32 unlock_reg; }; /* ----------------------------------------------------------------------------- @@ -302,20 +304,21 @@ struct sh_pfc_soc_info { /* * PORTnCR macro */ -#define _PCRH(in, in_pd, in_pu, out) \ - 0, (out), (in), 0, \ - 0, 0, 0, 0, \ - 0, 0, (in_pd), 0, \ - 0, 0, (in_pu), 0 - #define PORTCR(nr, reg) \ { \ - PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ - _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \ - PORT##nr##_FN0, PORT##nr##_FN1, \ - PORT##nr##_FN2, PORT##nr##_FN3, \ - PORT##nr##_FN4, PORT##nr##_FN5, \ - PORT##nr##_FN6, PORT##nr##_FN7 } \ + PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\ + /* PULMD[1:0], handled by .set_bias() */ \ + 0, 0, 0, 0, \ + /* IE and OE */ \ + 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \ + /* SEC, not supported */ \ + 0, 0, \ + /* PTMD[2:0] */ \ + PORT##nr##_FN0, PORT##nr##_FN1, \ + PORT##nr##_FN2, PORT##nr##_FN3, \ + PORT##nr##_FN4, PORT##nr##_FN5, \ + PORT##nr##_FN6, PORT##nr##_FN7 \ + } \ } #endif /* __SH_PFC_H */ diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index 2a1f07249b2f..e2efbbae4061 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -39,10 +39,9 @@ struct sirfsoc_gpio_bank { struct sirfsoc_gpio_chip { struct of_mm_gpio_chip chip; struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS]; + spinlock_t lock; }; -static DEFINE_SPINLOCK(sgpio_lock); - static struct sirfsoc_pin_group *sirfsoc_pin_groups; static int sirfsoc_pingrp_cnt; @@ -427,13 +426,13 @@ static void sirfsoc_gpio_irq_ack(struct irq_data *d) offset = SIRFSOC_GPIO_CTRL(bank->id, idx); - spin_lock_irqsave(&sgpio_lock, flags); + spin_lock_irqsave(&sgpio->lock, flags); val = readl(sgpio->chip.regs + offset); writel(val, sgpio->chip.regs + offset); - spin_unlock_irqrestore(&sgpio_lock, flags); + spin_unlock_irqrestore(&sgpio->lock, flags); } static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio, @@ -445,14 +444,14 @@ static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio, offset = SIRFSOC_GPIO_CTRL(bank->id, idx); - spin_lock_irqsave(&sgpio_lock, flags); + spin_lock_irqsave(&sgpio->lock, flags); val = readl(sgpio->chip.regs + offset); val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; writel(val, sgpio->chip.regs + offset); - spin_unlock_irqrestore(&sgpio_lock, flags); + spin_unlock_irqrestore(&sgpio->lock, flags); } static void sirfsoc_gpio_irq_mask(struct irq_data *d) @@ -475,14 +474,14 @@ static void sirfsoc_gpio_irq_unmask(struct irq_data *d) offset = SIRFSOC_GPIO_CTRL(bank->id, idx); - spin_lock_irqsave(&sgpio_lock, flags); + spin_lock_irqsave(&sgpio->lock, flags); val = readl(sgpio->chip.regs + offset); val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK; writel(val, sgpio->chip.regs + offset); - spin_unlock_irqrestore(&sgpio_lock, flags); + spin_unlock_irqrestore(&sgpio->lock, flags); } static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) @@ -496,7 +495,7 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) offset = SIRFSOC_GPIO_CTRL(bank->id, idx); - spin_lock_irqsave(&sgpio_lock, flags); + spin_lock_irqsave(&sgpio->lock, flags); val = readl(sgpio->chip.regs + offset); val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK); @@ -533,7 +532,7 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) writel(val, sgpio->chip.regs + offset); - spin_unlock_irqrestore(&sgpio_lock, flags); + spin_unlock_irqrestore(&sgpio->lock, flags); return 0; } @@ -568,7 +567,7 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id)); if (!status) { printk(KERN_WARNING - "%s: gpio id %d status %#x no interrupt is flaged\n", + "%s: gpio id %d status %#x no interrupt is flagged\n", __func__, bank->id, status); handle_bad_irq(irq, desc); return; @@ -697,11 +696,11 @@ static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, offset = SIRFSOC_GPIO_CTRL(bank->id, idx); - spin_lock_irqsave(&sgpio_lock, flags); + spin_lock_irqsave(&sgpio->lock, flags); sirfsoc_gpio_set_output(sgpio, bank, offset, value); - spin_unlock_irqrestore(&sgpio_lock, flags); + spin_unlock_irqrestore(&sgpio->lock, flags); return 0; } @@ -793,6 +792,7 @@ static int sirfsoc_gpio_probe(struct device_node *np) sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL); if (!sgpio) return -ENOMEM; + spin_lock_init(&sgpio->lock); regs = of_iomap(np, 0); if (!regs) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c index 3c68a8e5e0dd..7376a97b5e65 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c @@ -1020,7 +1020,7 @@ static int sun4i_a10_pinctrl_probe(struct platform_device *pdev) &sun4i_a10_pinctrl_data); } -static struct of_device_id sun4i_a10_pinctrl_match[] = { +static const struct of_device_id sun4i_a10_pinctrl_match[] = { { .compatible = "allwinner,sun4i-a10-pinctrl", }, {} }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c b/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c index 45a351affa59..63676617bc59 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c @@ -670,7 +670,7 @@ static int sun5i_a10s_pinctrl_probe(struct platform_device *pdev) &sun5i_a10s_pinctrl_data); } -static struct of_device_id sun5i_a10s_pinctrl_match[] = { +static const struct of_device_id sun5i_a10s_pinctrl_match[] = { { .compatible = "allwinner,sun5i-a10s-pinctrl", }, {} }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c index 4bd23471412c..2bb07b38834f 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c @@ -388,7 +388,7 @@ static int sun5i_a13_pinctrl_probe(struct platform_device *pdev) &sun5i_a13_pinctrl_data); } -static struct of_device_id sun5i_a13_pinctrl_match[] = { +static const struct of_device_id sun5i_a13_pinctrl_match[] = { { .compatible = "allwinner,sun5i-a13-pinctrl", }, {} }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c index 02174fa57997..9596b0a3df6b 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c @@ -120,7 +120,7 @@ static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev) return ret; } -static struct of_device_id sun6i_a31_r_pinctrl_match[] = { +static const struct of_device_id sun6i_a31_r_pinctrl_match[] = { { .compatible = "allwinner,sun6i-a31-r-pinctrl", }, {} }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c index 18038f0d6b52..022863ab0c58 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c @@ -922,7 +922,7 @@ static int sun6i_a31_pinctrl_probe(struct platform_device *pdev) &sun6i_a31_pinctrl_data); } -static struct of_device_id sun6i_a31_pinctrl_match[] = { +static const struct of_device_id sun6i_a31_pinctrl_match[] = { { .compatible = "allwinner,sun6i-a31-pinctrl", }, {} }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c index 9b5a91f610c7..d3725dcd6979 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c @@ -794,7 +794,7 @@ static int sun6i_a31s_pinctrl_probe(struct platform_device *pdev) &sun6i_a31s_pinctrl_data); } -static struct of_device_id sun6i_a31s_pinctrl_match[] = { +static const struct of_device_id sun6i_a31s_pinctrl_match[] = { { .compatible = "allwinner,sun6i-a31s-pinctrl", }, {} }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c index 6af6cc8547b0..cf1ce0c02600 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c @@ -1045,7 +1045,7 @@ static int sun7i_a20_pinctrl_probe(struct platform_device *pdev) &sun7i_a20_pinctrl_data); } -static struct of_device_id sun7i_a20_pinctrl_match[] = { +static const struct of_device_id sun7i_a20_pinctrl_match[] = { { .compatible = "allwinner,sun7i-a20-pinctrl", }, {} }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c index 327e03ff7c4d..056287635873 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c @@ -119,7 +119,7 @@ static int sun8i_a23_r_pinctrl_probe(struct platform_device *pdev) return ret; } -static struct of_device_id sun8i_a23_r_pinctrl_match[] = { +static const struct of_device_id sun8i_a23_r_pinctrl_match[] = { { .compatible = "allwinner,sun8i-a23-r-pinctrl", }, {} }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c index 62695c9a92c2..55083d278bb1 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c @@ -571,7 +571,7 @@ static int sun8i_a23_pinctrl_probe(struct platform_device *pdev) &sun8i_a23_pinctrl_data); } -static struct of_device_id sun8i_a23_pinctrl_match[] = { +static const struct of_device_id sun8i_a23_pinctrl_match[] = { { .compatible = "allwinner,sun8i-a23-pinctrl", }, {} }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c index adb29422efc9..1b580ba76453 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c @@ -729,7 +729,7 @@ static int sun9i_a80_pinctrl_probe(struct platform_device *pdev) &sun9i_a80_pinctrl_data); } -static struct of_device_id sun9i_a80_pinctrl_match[] = { +static const struct of_device_id sun9i_a80_pinctrl_match[] = { { .compatible = "allwinner,sun9i-a80-pinctrl", }, {} }; diff --git a/drivers/pinctrl/vt8500/pinctrl-vt8500.c b/drivers/pinctrl/vt8500/pinctrl-vt8500.c index cf8bbc946ff7..ca946b3dbdb4 100644 --- a/drivers/pinctrl/vt8500/pinctrl-vt8500.c +++ b/drivers/pinctrl/vt8500/pinctrl-vt8500.c @@ -478,7 +478,7 @@ static int vt8500_pinctrl_remove(struct platform_device *pdev) return wmt_pinctrl_remove(pdev); } -static struct of_device_id wmt_pinctrl_of_match[] = { +static const struct of_device_id wmt_pinctrl_of_match[] = { { .compatible = "via,vt8500-pinctrl" }, { /* sentinel */ }, }; diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8505.c b/drivers/pinctrl/vt8500/pinctrl-wm8505.c index 3f9c32dcb3d0..626fc7ec0174 100644 --- a/drivers/pinctrl/vt8500/pinctrl-wm8505.c +++ b/drivers/pinctrl/vt8500/pinctrl-wm8505.c @@ -509,7 +509,7 @@ static int wm8505_pinctrl_remove(struct platform_device *pdev) return wmt_pinctrl_remove(pdev); } -static struct of_device_id wmt_pinctrl_of_match[] = { +static const struct of_device_id wmt_pinctrl_of_match[] = { { .compatible = "wm,wm8505-pinctrl" }, { /* sentinel */ }, }; diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8650.c b/drivers/pinctrl/vt8500/pinctrl-wm8650.c index 4e80f98c2ba7..8953aba8bfc2 100644 --- a/drivers/pinctrl/vt8500/pinctrl-wm8650.c +++ b/drivers/pinctrl/vt8500/pinctrl-wm8650.c @@ -347,7 +347,7 @@ static int wm8650_pinctrl_remove(struct platform_device *pdev) return wmt_pinctrl_remove(pdev); } -static struct of_device_id wmt_pinctrl_of_match[] = { +static const struct of_device_id wmt_pinctrl_of_match[] = { { .compatible = "wm,wm8650-pinctrl" }, { /* sentinel */ }, }; diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8750.c b/drivers/pinctrl/vt8500/pinctrl-wm8750.c index 47b52a7cacac..c79053d430db 100644 --- a/drivers/pinctrl/vt8500/pinctrl-wm8750.c +++ b/drivers/pinctrl/vt8500/pinctrl-wm8750.c @@ -386,7 +386,7 @@ static int wm8750_pinctrl_remove(struct platform_device *pdev) return wmt_pinctrl_remove(pdev); } -static struct of_device_id wmt_pinctrl_of_match[] = { +static const struct of_device_id wmt_pinctrl_of_match[] = { { .compatible = "wm,wm8750-pinctrl" }, { /* sentinel */ }, }; diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8850.c b/drivers/pinctrl/vt8500/pinctrl-wm8850.c index 8bbb38c931f6..f232b163c735 100644 --- a/drivers/pinctrl/vt8500/pinctrl-wm8850.c +++ b/drivers/pinctrl/vt8500/pinctrl-wm8850.c @@ -365,7 +365,7 @@ static int wm8850_pinctrl_remove(struct platform_device *pdev) return wmt_pinctrl_remove(pdev); } -static struct of_device_id wmt_pinctrl_of_match[] = { +static const struct of_device_id wmt_pinctrl_of_match[] = { { .compatible = "wm,wm8850-pinctrl" }, { /* sentinel */ }, }; diff --git a/include/dt-bindings/gpio/meson8b-gpio.h b/include/dt-bindings/gpio/meson8b-gpio.h new file mode 100644 index 000000000000..c38cb20d7182 --- /dev/null +++ b/include/dt-bindings/gpio/meson8b-gpio.h @@ -0,0 +1,32 @@ +/* + * GPIO definitions for Amlogic Meson8b SoCs + * + * Copyright (C) 2015 Endless Mobile, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _DT_BINDINGS_MESON8B_GPIO_H +#define _DT_BINDINGS_MESON8B_GPIO_H + +#include <dt-bindings/gpio/meson8-gpio.h> + +/* GPIO Bank DIF */ +#define DIF_0_P 120 +#define DIF_0_N 121 +#define DIF_1_P 122 +#define DIF_1_N 123 +#define DIF_2_P 124 +#define DIF_2_N 125 +#define DIF_3_P 126 +#define DIF_3_N 127 +#define DIF_4_P 128 +#define DIF_4_N 129 + +#endif /* _DT_BINDINGS_MESON8B_GPIO_H */ diff --git a/include/dt-bindings/pinctrl/mt65xx.h b/include/dt-bindings/pinctrl/mt65xx.h new file mode 100644 index 000000000000..1198f4541327 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt65xx.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_PINCTRL_MT65XX_H +#define _DT_BINDINGS_PINCTRL_MT65XX_H + +#define MTK_PIN_NO(x) ((x) << 8) +#define MTK_GET_PIN_NO(x) ((x) >> 8) +#define MTK_GET_PIN_FUNC(x) ((x) & 0xf) + +#define MTK_PUPD_SET_R1R0_00 100 +#define MTK_PUPD_SET_R1R0_01 101 +#define MTK_PUPD_SET_R1R0_10 102 +#define MTK_PUPD_SET_R1R0_11 103 + +#define MTK_DRIVE_2mA 2 +#define MTK_DRIVE_4mA 4 +#define MTK_DRIVE_6mA 6 +#define MTK_DRIVE_8mA 8 +#define MTK_DRIVE_10mA 10 +#define MTK_DRIVE_12mA 12 +#define MTK_DRIVE_14mA 14 +#define MTK_DRIVE_16mA 16 +#define MTK_DRIVE_20mA 20 +#define MTK_DRIVE_24mA 24 +#define MTK_DRIVE_28mA 28 +#define MTK_DRIVE_32mA 32 + +#endif /* _DT_BINDINGS_PINCTRL_MT65XX_H */ diff --git a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h index fa74d7cc960c..aafa76cb569d 100644 --- a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h +++ b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h @@ -48,6 +48,14 @@ #define PM8058_GPIO_L5 6 #define PM8058_GPIO_L2 7 +/* + * Note: PM8916 GPIO1 and GPIO2 are supporting + * only L2(1.15V) and L5(1.8V) options + */ +#define PM8916_GPIO_VPH 0 +#define PM8916_GPIO_L2 2 +#define PM8916_GPIO_L5 3 + #define PM8917_GPIO_VPH 0 #define PM8917_GPIO_S4 2 #define PM8917_GPIO_L15 3 @@ -115,6 +123,13 @@ #define PM8058_GPIO39_MP3_CLK PMIC_GPIO_FUNC_FUNC1 #define PM8058_GPIO40_EXT_BB_EN PMIC_GPIO_FUNC_FUNC1 +#define PM8916_GPIO1_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 +#define PM8916_GPIO1_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 +#define PM8916_GPIO2_DIV_CLK PMIC_GPIO_FUNC_FUNC1 +#define PM8916_GPIO2_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 +#define PM8916_GPIO3_KEYP_DRV PMIC_GPIO_FUNC_FUNC1 +#define PM8916_GPIO4_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 + #define PM8917_GPIO9_18_KEYP_DRV PMIC_GPIO_FUNC_FUNC1 #define PM8917_GPIO20_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 #define PM8917_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2 diff --git a/include/dt-bindings/pinctrl/qcom,pmic-mpp.h b/include/dt-bindings/pinctrl/qcom,pmic-mpp.h index d2c7dabe3223..c10205491f8d 100644 --- a/include/dt-bindings/pinctrl/qcom,pmic-mpp.h +++ b/include/dt-bindings/pinctrl/qcom,pmic-mpp.h @@ -10,6 +10,10 @@ #define PM8841_MPP_VPH 0 #define PM8841_MPP_S3 2 +#define PM8916_MPP_VPH 0 +#define PM8916_MPP_L2 2 +#define PM8916_MPP_L5 3 + #define PM8941_MPP_VPH 0 #define PM8941_MPP_L1 1 #define PM8941_MPP_S3 2 |
