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authorWei Ni <wni@nvidia.com>2010-01-26 15:59:33 +0800
committerTakashi Iwai <tiwai@suse.de>2010-01-26 10:40:03 +0100
commitccc5df058da70d1c26c72cd1c24072a89998d735 (patch)
tree628d9b5a61588eb590f5fa1c816f3053f00f997c
parent0aea778efa0d632b62eb35122cbb3b9fae548c61 (diff)
downloadtalos-obmc-linux-ccc5df058da70d1c26c72cd1c24072a89998d735.tar.gz
talos-obmc-linux-ccc5df058da70d1c26c72cd1c24072a89998d735.zip
ALSA: hda - Add support for more the 8 streams
In azx_stream_start() and azx_stream_stop(), it use azx_readb/azx_writeb to read/write SIE, it just enable/disable 8 streams. But according to the HDA spec, it support 30 streams, and the new HDA controller will support more then 8 streams. So we should use azx_readl/azx_writel to read/write SIE. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
-rw-r--r--sound/pci/hda/hda_intel.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 6d331c4cf185..6eeefda63838 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -954,8 +954,8 @@ static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
azx_dev->insufficient = 1;
/* enable SIE */
- azx_writeb(chip, INTCTL,
- azx_readb(chip, INTCTL) | (1 << azx_dev->index));
+ azx_writel(chip, INTCTL,
+ azx_readl(chip, INTCTL) | (1 << azx_dev->index));
/* set DMA start and interrupt mask */
azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
SD_CTL_DMA_START | SD_INT_MASK);
@@ -974,8 +974,8 @@ static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
{
azx_stream_clear(chip, azx_dev);
/* disable SIE */
- azx_writeb(chip, INTCTL,
- azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
+ azx_writel(chip, INTCTL,
+ azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
}
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