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| author | Ben Dooks <ben-linux@fluff.org> | 2007-02-15 22:53:52 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-02-16 11:40:51 +0000 |
| commit | b4f14eb86cda9324a2ffbdf534385d012967acd8 (patch) | |
| tree | 657533198acc1f6d0130518bd88be75d84ca16f3 | |
| parent | d4156d52c7464e8f25a286e1c2975e91bdbc35d6 (diff) | |
| download | talos-obmc-linux-b4f14eb86cda9324a2ffbdf534385d012967acd8.tar.gz talos-obmc-linux-b4f14eb86cda9324a2ffbdf534385d012967acd8.zip | |
[ARM] 4205/1: S3C2443: Add cpu specific reset hook
Hook in a cpu specific reset function for the S3C2443
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| -rw-r--r-- | arch/arm/mach-s3c2443/s3c2443.c | 10 | ||||
| -rw-r--r-- | include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h | 2 |
2 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c index 9b91235c15d2..11b1d0b310c3 100644 --- a/arch/arm/mach-s3c2443/s3c2443.c +++ b/arch/arm/mach-s3c2443/s3c2443.c @@ -29,7 +29,8 @@ #include <asm/io.h> #include <asm/irq.h> -#include <asm/arch/regs-serial.h> +#include <asm/arch/regs-s3c2443-clock.h> +#include <asm/arch/reset.h> #include <asm/plat-s3c24xx/s3c2443.h> #include <asm/plat-s3c24xx/devs.h> @@ -49,10 +50,17 @@ static struct sys_device s3c2443_sysdev = { .cls = &s3c2443_sysclass, }; +static void s3c2443_hard_reset(void) +{ + __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST); +} + int __init s3c2443_init(void) { printk("S3C2443: Initialising architecture\n"); + s3c24xx_reset_hook = s3c2443_hard_reset; + s3c_device_nand.name = "s3c2412-nand"; return sysdev_register(&s3c2443_sysdev); diff --git a/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h b/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h index e696554f9c21..ff0536d2de42 100644 --- a/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h +++ b/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h @@ -38,6 +38,8 @@ #define S3C2443_PWRCFG S3C2443_CLKREG(0x60) #define S3C2443_RSTCON S3C2443_CLKREG(0x64) +#define S3C2443_SWRST_RESET (0x533c2443) + #define S3C2443_PLLCON_OFF (1<<24) #define S3C2443_CLKSRC_I2S_EXT (1<<14) |
