diff options
| author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2017-02-23 12:44:41 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-03-20 14:05:29 +0100 |
| commit | 8809eeac21c4fc8c964a4bbcda53c7228ad23370 (patch) | |
| tree | 87e292f9f5611fbabbf495a63cebc8da13c856e0 | |
| parent | e7a49675e2c273e5490ac4a5187fa1eeddbdd4b4 (diff) | |
| download | talos-obmc-linux-8809eeac21c4fc8c964a4bbcda53c7228ad23370.tar.gz talos-obmc-linux-8809eeac21c4fc8c964a4bbcda53c7228ad23370.zip | |
clk: tegra: Remove non-existing pll_m_out1 clock
This clock doesn't actually exist, so remove it.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | drivers/clk/tegra/clk-tegra210.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 7bda8ba449a8..b7ef8a78eeb0 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -2115,7 +2115,6 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { [tegra_clk_pll_c2] = { .dt_id = TEGRA210_CLK_PLL_C2, .present = true }, [tegra_clk_pll_c3] = { .dt_id = TEGRA210_CLK_PLL_C3, .present = true }, [tegra_clk_pll_m] = { .dt_id = TEGRA210_CLK_PLL_M, .present = true }, - [tegra_clk_pll_m_out1] = { .dt_id = TEGRA210_CLK_PLL_M_OUT1, .present = true }, [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true }, [tegra_clk_pll_p_out1] = { .dt_id = TEGRA210_CLK_PLL_P_OUT1, .present = true }, [tegra_clk_pll_p_out3] = { .dt_id = TEGRA210_CLK_PLL_P_OUT3, .present = true }, @@ -2229,7 +2228,6 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 }, { .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 }, { .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M }, - { .con_id = "pll_m_out1", .dt_id = TEGRA210_CLK_PLL_M_OUT1 }, { .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X }, { .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 }, { .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U }, @@ -2404,9 +2402,6 @@ static void __init tegra210_pll_init(void __iomem *clk_base, clk_register_clkdev(clk, "pll_mb", NULL); clks[TEGRA210_CLK_PLL_MB] = clk; - clk_register_clkdev(clk, "pll_m_out1", NULL); - clks[TEGRA210_CLK_PLL_M_OUT1] = clk; - /* PLLM_UD */ clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", CLK_SET_RATE_PARENT, 1, 1); |
