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author | Cédric Le Goater <clg@kaod.org> | 2019-04-17 15:39:38 +0200 |
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committer | Andrew Jeffery <andrew@aj.id.au> | 2019-04-18 11:11:12 +0930 |
commit | 85b9912a9d34e0d6809b6f97e1869ffea9c80d92 (patch) | |
tree | db438fdf8ba1c6e587cb9eea659d392cc8f13751 | |
parent | 39879fe4857e5ac8f19a351f57c3e6a206b05af4 (diff) | |
download | talos-obmc-linux-85b9912a9d34e0d6809b6f97e1869ffea9c80d92.tar.gz talos-obmc-linux-85b9912a9d34e0d6809b6f97e1869ffea9c80d92.zip |
mtd: spi-nor: aspeed: introduce a aspeed_smc_default_read() helper
OpenBMC-Staging-Count: 1
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
-rw-r--r-- | drivers/mtd/spi-nor/aspeed-smc.c | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c index ddf7ae78aa0a..ee3059b27c07 100644 --- a/drivers/mtd/spi-nor/aspeed-smc.c +++ b/drivers/mtd/spi-nor/aspeed-smc.c @@ -882,6 +882,17 @@ static const uint32_t aspeed_smc_hclk_divs[] = { }; #define ASPEED_SMC_HCLK_DIV(i) (aspeed_smc_hclk_divs[(i) - 1] << 8) +static u32 aspeed_smc_default_read(struct aspeed_smc_chip *chip) +{ + return (chip->ctl_val[smc_read] & 0x2000) | + (0x00 << 28) | /* Single bit */ + (0x00 << 24) | /* CE# max */ + (0x03 << 16) | /* use normal reads */ + (0x00 << 8) | /* HCLK/16 */ + (0x00 << 6) | /* no dummy cycle */ + (0x00); /* normal mode */ +} + static int aspeed_smc_optimize_read(struct aspeed_smc_chip *chip, u32 max_freq) { @@ -898,13 +909,7 @@ static int aspeed_smc_optimize_read(struct aspeed_smc_chip *chip, /* We start with the dumbest setting (keep 4Byte bit) and read * some data */ - chip->ctl_val[smc_read] = (chip->ctl_val[smc_read] & 0x2000) | - (0x00 << 28) | /* Single bit */ - (0x00 << 24) | /* CE# max */ - (0x03 << 16) | /* use normal reads */ - (0x00 << 8) | /* HCLK/16 */ - (0x00 << 6) | /* no dummy cycle */ - (0x00); /* normal read */ + chip->ctl_val[smc_read] = aspeed_smc_default_read(chip); writel(chip->ctl_val[smc_read], chip->ctl); |