summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorLeonard Crestez <leonard.crestez@nxp.com>2018-07-20 15:47:43 +0300
committerPhilipp Zabel <p.zabel@pengutronix.de>2018-07-23 13:00:28 +0200
commit26fce0557fa639fb7bbc33e31a57cff7df25c3a0 (patch)
tree349e7e2253fe0cd9768f2d829c2cc2063d7d6cc2
parentce397d215ccd07b8ae3f71db689aedb85d56ab40 (diff)
downloadtalos-obmc-linux-26fce0557fa639fb7bbc33e31a57cff7df25c3a0.tar.gz
talos-obmc-linux-26fce0557fa639fb7bbc33e31a57cff7df25c3a0.zip
reset: imx7: Fix always writing bits as 0
Right now the only user of reset-imx7 is pci-imx6 and the reset_control_assert and deassert calls on pciephy_reset don't toggle the PCIEPHY_BTN and PCIEPHY_G_RST bits as expected. Fix this by writing 1 or 0 respectively. The reference manual is not very clear regarding SRC_PCIEPHY_RCR but for other registers like MIPIPHY and HSICPHY the bits are explicitly documented as "1 means assert, 0 means deassert". The values are still reversed for IMX7_RESET_PCIE_CTRL_APPS_EN. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
-rw-r--r--drivers/reset/reset-imx7.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index 4db177bc89bc..fdeac1946429 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -80,7 +80,7 @@ static int imx7_reset_set(struct reset_controller_dev *rcdev,
{
struct imx7_src *imx7src = to_imx7_src(rcdev);
const struct imx7_src_signal *signal = &imx7_src_signals[id];
- unsigned int value = 0;
+ unsigned int value = assert ? signal->bit : 0;
switch (id) {
case IMX7_RESET_PCIEPHY:
OpenPOWER on IntegriCloud